Added many other

2026-08-06 18:56:32 +03:00
parent 9f2fd08ee5
commit d9d7ee49d2
2144 changed files with 1115424 additions and 1284 deletions
@@ -0,0 +1,99 @@
+//
+// Generated by NVIDIA NVVM Compiler
+//
+// Compiler Build ID: CL-23083092
+// Cuda compilation tools, release 9.1, V9.1.85
+// Based on LLVM 3.4svn
+//
+
+.version 6.1
+.target sm_30
+.address_size 64
+
+	// .globl	oxMain
+.const .align 8 .b8 params[88];
+
+.visible .entry oxMain(
+
+)
+{
+	.reg .pred 	%p<5>;
+	.reg .b16 	%rs<8>;
+	.reg .f32 	%f<16>;
+	.reg .b32 	%r<22>;
+	.reg .b64 	%rd<15>;
+
+
+	mov.u32 	%r6, %ctaid.x;
+	mov.u32 	%r7, %ntid.x;
+	mov.u32 	%r8, %tid.x;
+	mad.lo.s32 	%r1, %r7, %r6, %r8;
+	mov.u32 	%r9, %ntid.y;
+	mov.u32 	%r10, %ctaid.y;
+	mov.u32 	%r11, %tid.y;
+	mad.lo.s32 	%r2, %r9, %r10, %r11;
+	mov.u32 	%r12, %nctaid.x;
+	mul.lo.s32 	%r13, %r12, %r7;
+	mov.u32 	%r14, %nctaid.y;
+	mul.lo.s32 	%r15, %r14, %r9;
+	setp.lt.u32	%p1, %r1, %r13;
+	setp.lt.u32	%p2, %r2, %r15;
+	and.pred  	%p3, %p1, %p2;
+	@!%p3 bra 	BB0_5;
+	bra.uni 	BB0_1;
+
+BB0_1:
+	ld.const.u32 	%r16, [params+80];
+	setp.gt.s32	%p4, %r16, 0;
+	@%p4 bra 	BB0_3;
+	bra.uni 	BB0_2;
+
+BB0_3:
+	ld.const.u64 	%rd14, [params+56];
+	cvta.to.global.u64 	%rd8, %rd14;
+	ld.const.u32 	%r21, [params+48];
+	mad.lo.s32 	%r19, %r21, %r2, %r1;
+	mul.wide.u32 	%rd9, %r19, 12;
+	add.s64 	%rd10, %rd8, %rd9;
+	ld.global.f32 	%f13, [%rd10];
+	ld.global.f32 	%f14, [%rd10+4];
+	ld.global.f32 	%f15, [%rd10+8];
+	bra.uni 	BB0_4;
+
+BB0_2:
+	ld.const.u64 	%rd4, [params+8];
+	cvta.to.global.u64 	%rd5, %rd4;
+	ld.const.u32 	%r17, [params];
+	mad.lo.s32 	%r18, %r17, %r2, %r1;
+	mul.wide.u32 	%rd6, %r18, 8;
+	add.s64 	%rd7, %rd5, %rd6;
+	ld.global.v4.u16 	{%rs4, %rs5, %rs6, %rs7}, [%rd7];
+	// inline asm
+	{  cvt.f32.f16 %f13, %rs4;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f14, %rs5;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f15, %rs6;}
+
+	// inline asm
+	ld.const.u64 	%rd14, [params+56];
+	ld.const.u32 	%r21, [params+48];
+
+BB0_4:
+	mad.lo.s32 	%r20, %r21, %r2, %r1;
+	cvta.to.global.u64 	%rd11, %rd14;
+	mul.wide.u32 	%rd12, %r20, 12;
+	add.s64 	%rd13, %rd11, %rd12;
+	st.global.f32 	[%rd13], %f13;
+	st.global.f32 	[%rd13+4], %f14;
+	st.global.f32 	[%rd13+8], %f15;
+
+BB0_5:
+	ret;
+}
+
+