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AsanoRema
2026-08-06 18:56:32 +03:00
parent 9f2fd08ee5
commit d9d7ee49d2
2144 changed files with 1115424 additions and 1284 deletions
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Assets/Editor/x64/Bakery/optix9/attrib_trimeshLOD64.ptx
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//
.version 8.0
.target sm_52
.address_size 64
.const .align 16 .b8 params[1184];
.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
.param .b32 __direct_callable__oxMain_param_0,
.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
.reg .pred %p<5>;
.reg .b16 %rs<41>;
.reg .f32 %f<93>;
.reg .b32 %r<27>;
.reg .b64 %rd<50>;
ld.param.u32 %r4, [__direct_callable__oxMain_param_0];
ld.param.f32 %f21, [__direct_callable__oxMain_param_1+4];
ld.param.f32 %f20, [__direct_callable__oxMain_param_1];
// begin inline asm
call (%r5), _optix_get_launch_index_x, ();
// end inline asm
// begin inline asm
call (%r6), _optix_get_launch_index_y, ();
// end inline asm
ld.const.u64 %rd5, [params+72];
cvta.to.global.u64 %rd6, %rd5;
mul.wide.s32 %rd7, %r4, 8;
add.s64 %rd8, %rd6, %rd7;
ld.global.u64 %rd1, [%rd8];
setp.eq.s64 %p1, %rd1, 0;
@%p1 bra $L__BB0_2;
ld.const.u64 %rd9, [params+480];
cvta.to.global.u64 %rd10, %rd9;
ld.const.u32 %r8, [params+472];
mad.lo.s32 %r9, %r8, %r6, %r5;
cvt.u64.u32 %rd11, %r9;
add.s64 %rd12, %rd10, %rd11;
ld.global.u8 %r10, [%rd12];
mov.u64 %rd13, 1;
shl.b64 %rd14, %rd13, %r10;
and.b64 %rd15, %rd14, %rd1;
setp.eq.s64 %p2, %rd15, 0;
mov.f32 %f89, 0f00000000;
mov.f32 %f90, %f89;
mov.f32 %f91, %f89;
mov.f32 %f92, %f89;
@%p2 bra $L__BB0_6;
$L__BB0_2:
ld.const.u64 %rd16, [params+24];
cvta.to.global.u64 %rd17, %rd16;
mul.wide.u32 %rd18, %r4, 12;
add.s64 %rd19, %rd17, %rd18;
ld.global.s32 %rd2, [%rd19];
ld.global.s32 %rd3, [%rd19+4];
ld.global.s32 %rd4, [%rd19+8];
ld.const.u32 %r3, [params+32];
setp.gt.u32 %p3, %r3, %r4;
@%p3 bra $L__BB0_4;
bra.uni $L__BB0_3;
$L__BB0_4:
mov.f32 %f92, 0f3F800000;
sub.f32 %f61, %f92, %f20;
sub.f32 %f87, %f61, %f21;
bra.uni $L__BB0_5;
$L__BB0_3:
sub.s32 %r11, %r4, %r3;
ld.const.v2.u64 {%rd20, %rd21}, [params+48];
cvta.to.global.u64 %rd24, %rd20;
mul.wide.u32 %rd25, %r11, 4;
add.s64 %rd26, %rd24, %rd25;
ld.const.u64 %rd27, [params+40];
cvta.to.global.u64 %rd28, %rd27;
shl.b64 %rd29, %rd2, 3;
add.s64 %rd30, %rd28, %rd29;
ld.global.v2.f32 {%f30, %f31}, [%rd30];
shl.b64 %rd31, %rd3, 3;
add.s64 %rd32, %rd28, %rd31;
ld.global.v2.f32 {%f34, %f35}, [%rd32];
shl.b64 %rd33, %rd4, 3;
add.s64 %rd34, %rd28, %rd33;
ld.global.v2.f32 {%f38, %f39}, [%rd34];
mov.f32 %f42, 0f3F800000;
sub.f32 %f43, %f42, %f20;
sub.f32 %f87, %f43, %f21;
mul.f32 %f44, %f20, %f34;
mul.f32 %f45, %f20, %f35;
fma.rn.f32 %f46, %f87, %f30, %f44;
fma.rn.f32 %f47, %f87, %f31, %f45;
fma.rn.f32 %f48, %f21, %f38, %f46;
fma.rn.f32 %f49, %f21, %f39, %f47;
ld.global.u32 %r12, [%rd26];
shr.u32 %r13, %r12, 16;
abs.f32 %f50, %f48;
cvt.rmi.f32.f32 %f51, %f50;
sub.f32 %f52, %f50, %f51;
abs.f32 %f53, %f49;
cvt.rmi.f32.f32 %f54, %f53;
sub.f32 %f55, %f53, %f54;
cvta.to.global.u64 %rd35, %rd21;
shl.b32 %r14, %r12, 4;
cvt.u64.u32 %rd36, %r14;
and.b64 %rd37, %rd36, 1048560;
add.s64 %rd38, %rd35, %rd37;
ld.global.v2.u32 {%r15, %r16}, [%rd38];
cvt.rn.f32.u32 %f56, %r15;
mul.f32 %f57, %f52, %f56;
cvt.rzi.u32.f32 %r19, %f57;
cvt.rn.f32.u32 %f58, %r16;
mul.f32 %f59, %f55, %f58;
cvt.rzi.u32.f32 %r20, %f59;
mad.lo.s32 %r21, %r15, %r20, %r19;
cvt.u64.u32 %rd39, %r21;
ld.global.u64 %rd40, [%rd38+8];
add.s64 %rd41, %rd40, %rd39;
ld.u8 %r22, [%rd41];
and.b32 %r23, %r13, %r22;
setp.eq.s32 %p4, %r23, 0;
selp.f32 %f92, 0f00000000, 0f3F800000, %p4;
$L__BB0_5:
cvt.u32.u64 %r24, %rd2;
cvt.u32.u64 %r25, %rd3;
cvt.u32.u64 %r26, %rd4;
ld.const.u64 %rd42, [params+16];
cvta.to.global.u64 %rd43, %rd42;
mul.wide.s32 %rd44, %r24, 24;
add.s64 %rd45, %rd43, %rd44;
mul.wide.s32 %rd46, %r25, 24;
add.s64 %rd47, %rd43, %rd46;
mul.wide.s32 %rd48, %r26, 24;
add.s64 %rd49, %rd43, %rd48;
ld.global.f32 %f62, [%rd45+12];
ld.global.f32 %f63, [%rd45+16];
ld.global.f32 %f64, [%rd45+20];
ld.global.f32 %f65, [%rd47+12];
mul.f32 %f66, %f20, %f65;
ld.global.f32 %f67, [%rd47+16];
mul.f32 %f68, %f20, %f67;
ld.global.f32 %f69, [%rd47+20];
mul.f32 %f70, %f20, %f69;
fma.rn.f32 %f71, %f87, %f62, %f66;
fma.rn.f32 %f72, %f87, %f63, %f68;
fma.rn.f32 %f73, %f87, %f64, %f70;
ld.global.f32 %f74, [%rd49+12];
ld.global.f32 %f75, [%rd49+16];
ld.global.f32 %f76, [%rd49+20];
fma.rn.f32 %f77, %f21, %f74, %f71;
fma.rn.f32 %f78, %f21, %f75, %f72;
fma.rn.f32 %f79, %f21, %f76, %f73;
mul.f32 %f80, %f78, %f78;
fma.rn.f32 %f81, %f77, %f77, %f80;
fma.rn.f32 %f82, %f79, %f79, %f81;
sqrt.rn.f32 %f83, %f82;
rcp.rn.f32 %f84, %f83;
mul.f32 %f91, %f79, %f84;
mul.f32 %f90, %f78, %f84;
mul.f32 %f89, %f77, %f84;
$L__BB0_6:
st.param.f32 [func_retval0+0], %f89;
st.param.f32 [func_retval0+4], %f90;
st.param.f32 [func_retval0+8], %f91;
st.param.v4.b8 [func_retval0+12], {%rs9, %rs10, %rs11, %rs12};
st.param.f32 [func_retval0+16], %f17;
st.param.f32 [func_retval0+20], %f18;
st.param.f32 [func_retval0+24], %f92;
st.param.v4.b8 [func_retval0+28], {%rs13, %rs14, %rs15, %rs16};
ret;
}
// .globl oxMain
.visible .entry oxMain()
{
.reg .b64 %rd<2>;
mov.u64 %rd1, __direct_callable__oxMain;
// begin inline asm
// end inline asm
ret;
}