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AsanoRema
2026-08-06 18:56:32 +03:00
parent 9f2fd08ee5
commit d9d7ee49d2
2144 changed files with 1115424 additions and 1284 deletions
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//
.version 8.0
.target sm_52
.address_size 64
.const .align 16 .b8 params[1184];
.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
.param .b32 __direct_callable__oxMain_param_0,
.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
.reg .pred %p<5>;
.reg .b16 %rs<41>;
.reg .f32 %f<132>;
.reg .b32 %r<29>;
.reg .b64 %rd<43>;
ld.param.u32 %r3, [__direct_callable__oxMain_param_0];
ld.param.f32 %f1, [__direct_callable__oxMain_param_1];
ld.param.f32 %f2, [__direct_callable__oxMain_param_1+4];
ld.const.u64 %rd6, [params+24];
cvta.to.global.u64 %rd7, %rd6;
mul.wide.u32 %rd8, %r3, 12;
add.s64 %rd9, %rd7, %rd8;
ld.global.s32 %rd1, [%rd9];
ld.global.s32 %rd2, [%rd9+4];
ld.global.s32 %rd3, [%rd9+8];
ld.const.u32 %r1, [params+32];
setp.gt.u32 %p1, %r1, %r3;
@%p1 bra $L__BB0_4;
bra.uni $L__BB0_1;
$L__BB0_4:
mov.f32 %f131, 0f3F800000;
sub.f32 %f84, %f131, %f1;
sub.f32 %f122, %f84, %f2;
bra.uni $L__BB0_5;
$L__BB0_1:
sub.s32 %r4, %r3, %r1;
ld.const.u64 %rd10, [params+48];
cvta.to.global.u64 %rd11, %rd10;
mul.wide.u32 %rd12, %r4, 4;
add.s64 %rd13, %rd11, %rd12;
ld.const.u64 %rd14, [params+40];
cvta.to.global.u64 %rd15, %rd14;
shl.b64 %rd16, %rd1, 3;
add.s64 %rd17, %rd15, %rd16;
ld.global.v2.f32 {%f40, %f41}, [%rd17];
shl.b64 %rd18, %rd2, 3;
add.s64 %rd19, %rd15, %rd18;
ld.global.v2.f32 {%f44, %f45}, [%rd19];
shl.b64 %rd20, %rd3, 3;
add.s64 %rd21, %rd15, %rd20;
ld.global.v2.f32 {%f48, %f49}, [%rd21];
mov.f32 %f52, 0f3F800000;
sub.f32 %f53, %f52, %f1;
sub.f32 %f122, %f53, %f2;
mul.f32 %f54, %f1, %f44;
mul.f32 %f55, %f1, %f45;
fma.rn.f32 %f56, %f122, %f40, %f54;
fma.rn.f32 %f57, %f122, %f41, %f55;
fma.rn.f32 %f4, %f2, %f48, %f56;
fma.rn.f32 %f5, %f2, %f49, %f57;
ld.global.u32 %r2, [%rd13];
and.b32 %r5, %r2, -16384;
setp.eq.s32 %p2, %r5, 16384;
@%p2 bra $L__BB0_3;
bra.uni $L__BB0_2;
$L__BB0_3:
add.s32 %r17, %r2, -16384;
ld.const.u64 %rd30, [params+64];
cvta.to.global.u64 %rd31, %rd30;
mul.wide.u32 %rd32, %r17, 8;
add.s64 %rd33, %rd31, %rd32;
ld.global.u64 %rd34, [%rd33];
tex.2d.v4.f32.f32 {%f68, %f69, %f70, %f71}, [%rd34, {%f4, %f5}];
cvt.sat.f32.f32 %f72, %f68;
mul.f32 %f73, %f72, 0f437F0000;
cvt.rzi.s32.f32 %r18, %f73;
cvt.sat.f32.f32 %f74, %f69;
mul.f32 %f75, %f74, 0f437F0000;
cvt.rzi.s32.f32 %r19, %f75;
cvt.sat.f32.f32 %f76, %f70;
mul.f32 %f77, %f76, 0f437F0000;
cvt.rzi.s32.f32 %r20, %f77;
shl.b32 %r21, %r19, 8;
or.b32 %r22, %r21, %r18;
shl.b32 %r23, %r20, 16;
or.b32 %r24, %r22, %r23;
not.b32 %r25, %r24;
cvt.rn.f32.s32 %f131, %r25;
bra.uni $L__BB0_9;
$L__BB0_2:
abs.f32 %f58, %f4;
cvt.rmi.f32.f32 %f59, %f58;
sub.f32 %f60, %f58, %f59;
abs.f32 %f61, %f5;
cvt.rmi.f32.f32 %f62, %f61;
sub.f32 %f63, %f61, %f62;
ld.const.u64 %rd22, [params+56];
cvta.to.global.u64 %rd23, %rd22;
shl.b32 %r6, %r2, 4;
cvt.u64.u32 %rd24, %r6;
and.b64 %rd25, %rd24, 1048560;
add.s64 %rd26, %rd23, %rd25;
ld.global.v2.u32 {%r7, %r8}, [%rd26];
cvt.rn.f32.u32 %f64, %r7;
mul.f32 %f65, %f60, %f64;
cvt.rzi.u32.f32 %r11, %f65;
cvt.rn.f32.u32 %f66, %r8;
mul.f32 %f67, %f63, %f66;
cvt.rzi.u32.f32 %r12, %f67;
mad.lo.s32 %r13, %r7, %r12, %r11;
cvt.u64.u32 %rd27, %r13;
ld.global.u64 %rd28, [%rd26+8];
add.s64 %rd29, %rd28, %rd27;
ld.u8 %r14, [%rd29];
shr.u32 %r15, %r2, 16;
and.b32 %r16, %r15, %r14;
setp.eq.s32 %p3, %r16, 0;
selp.f32 %f131, 0f00000000, 0f3F800000, %p3;
$L__BB0_5:
cvt.u32.u64 %r26, %rd1;
cvt.u32.u64 %r27, %rd2;
cvt.u32.u64 %r28, %rd3;
ld.const.u64 %rd35, [params+16];
cvta.to.global.u64 %rd36, %rd35;
mul.wide.s32 %rd37, %r26, 32;
add.s64 %rd38, %rd36, %rd37;
mul.wide.s32 %rd39, %r27, 32;
add.s64 %rd40, %rd36, %rd39;
add.s64 %rd4, %rd40, 12;
mul.wide.s32 %rd41, %r28, 32;
add.s64 %rd42, %rd36, %rd41;
add.s64 %rd5, %rd42, 12;
ld.global.f32 %f85, [%rd38+12];
ld.global.f32 %f86, [%rd38+16];
ld.global.f32 %f87, [%rd38+20];
ld.global.f32 %f88, [%rd40+12];
mul.f32 %f89, %f1, %f88;
ld.global.f32 %f90, [%rd40+16];
mul.f32 %f91, %f1, %f90;
ld.global.f32 %f92, [%rd40+20];
mul.f32 %f93, %f1, %f92;
fma.rn.f32 %f94, %f122, %f85, %f89;
fma.rn.f32 %f95, %f122, %f86, %f91;
fma.rn.f32 %f96, %f122, %f87, %f93;
ld.global.f32 %f97, [%rd42+12];
ld.global.f32 %f98, [%rd42+16];
ld.global.f32 %f99, [%rd42+20];
fma.rn.f32 %f100, %f2, %f97, %f94;
fma.rn.f32 %f101, %f2, %f98, %f95;
fma.rn.f32 %f102, %f2, %f99, %f96;
mul.f32 %f103, %f101, %f101;
fma.rn.f32 %f104, %f100, %f100, %f103;
fma.rn.f32 %f105, %f102, %f102, %f104;
sqrt.rn.f32 %f106, %f105;
rcp.rn.f32 %f107, %f106;
mul.f32 %f126, %f100, %f107;
mul.f32 %f127, %f101, %f107;
mul.f32 %f128, %f102, %f107;
ld.global.v2.f32 {%f129, %f109}, [%rd38+24];
setp.lt.f32 %p4, %f109, 0f00000000;
@%p4 bra $L__BB0_7;
bra.uni $L__BB0_6;
$L__BB0_7:
add.f32 %f130, %f109, 0f3F800000;
bra.uni $L__BB0_9;
$L__BB0_6:
ld.global.v2.f32 {%f110, %f111}, [%rd4+12];
ld.global.v2.f32 {%f112, %f113}, [%rd5+12];
mul.f32 %f115, %f1, %f110;
mul.f32 %f117, %f1, %f111;
fma.rn.f32 %f118, %f122, %f129, %f115;
fma.rn.f32 %f119, %f122, %f109, %f117;
fma.rn.f32 %f129, %f2, %f112, %f118;
fma.rn.f32 %f130, %f2, %f113, %f119;
$L__BB0_9:
st.param.f32 [func_retval0+0], %f126;
st.param.f32 [func_retval0+4], %f127;
st.param.f32 [func_retval0+8], %f128;
st.param.v4.b8 [func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
st.param.f32 [func_retval0+16], %f129;
st.param.f32 [func_retval0+20], %f130;
st.param.f32 [func_retval0+24], %f131;
st.param.v4.b8 [func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
ret;
}
// .globl oxMain
.visible .entry oxMain()
{
.reg .b64 %rd<2>;
mov.u64 %rd1, __direct_callable__oxMain;
// begin inline asm
// end inline asm
ret;
}