//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<201>;
	.reg .b16 	%rs<177>;
	.reg .f32 	%f<1645>;
	.reg .b32 	%r<503>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<127>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r93), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r94), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+616];
	ld.const.u32 	%r4, [params+540];
	ld.const.u64 	%rd34, [params+400];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r99, [params+392];
	mad.lo.s32 	%r100, %r99, %r94, %r93;
	mul.wide.u32 	%rd36, %r100, 4;
	add.s64 	%rd2, %rd35, %rd36;
	ld.global.v2.u8 	{%rs7, %rs176}, [%rd2];
	or.b16  	%rs9, %rs7, %rs176;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p10, %rs10, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs175, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs175, [%rd2+2];
	setp.eq.s16 	%p11, %rs175, 0;
	mov.f32 	%f1481, 0f00000000;
	mov.u16 	%rs176, 0;
	mov.f32 	%f1482, %f1481;
	mov.f32 	%f1483, %f1481;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f401, %rs7;
	div.rn.f32 	%f402, %f401, 0f437F0000;
	fma.rn.f32 	%f403, %f402, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs176, 255;
	cvt.rn.f32.u16 	%f404, %rs13;
	div.rn.f32 	%f405, %f404, 0f437F0000;
	fma.rn.f32 	%f406, %f405, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f407, %rs175;
	div.rn.f32 	%f408, %f407, 0f437F0000;
	fma.rn.f32 	%f409, %f408, 0f40000000, 0fBF800000;
	mul.f32 	%f410, %f406, %f406;
	fma.rn.f32 	%f411, %f403, %f403, %f410;
	fma.rn.f32 	%f412, %f409, %f409, %f411;
	sqrt.rn.f32 	%f413, %f412;
	rcp.rn.f32 	%f414, %f413;
	mul.f32 	%f1483, %f414, %f409;
	mul.f32 	%f1482, %f414, %f406;
	mul.f32 	%f1481, %f403, %f414;

$L__BB0_4:
	ld.const.v2.u32 	{%r101, %r102}, [params];
	add.s32 	%r5, %r101, %r93;
	add.s32 	%r6, %r102, %r94;
	setp.eq.f32 	%p12, %f1481, 0f00000000;
	setp.eq.f32 	%p13, %f1482, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1483, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_162;
	bra.uni 	$L__BB0_5;

$L__BB0_162:
	ld.const.u32 	%r90, [params+104];
	and.b32  	%r465, %r90, 1;
	setp.eq.b32 	%p189, %r465, 1;
	mov.pred 	%p190, 0;
	xor.pred  	%p191, %p189, %p190;
	not.pred 	%p192, %p191;
	@%p192 bra 	$L__BB0_164;

	ld.const.u64 	%rd97, [params+144];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r466, [params+136];
	mad.lo.s32 	%r467, %r466, %r6, %r5;
	mul.wide.u32 	%rd99, %r467, 4;
	add.s64 	%rd100, %rd98, %rd99;
	mov.u16 	%rs97, 0;
	st.global.v4.u8 	[%rd100], {%rs97, %rs97, %rs97, %rs97};

$L__BB0_164:
	and.b32  	%r468, %r90, 8;
	setp.eq.s32 	%p193, %r468, 0;
	@%p193 bra 	$L__BB0_166;

	ld.const.u64 	%rd101, [params+192];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r469, [params+184];
	mad.lo.s32 	%r470, %r469, %r6, %r5;
	mov.f32 	%f1427, 0f00000000;
	cvt.rzi.u32.f32 	%r471, %f1427;
	mul.wide.u32 	%rd103, %r470, 2;
	add.s64 	%rd104, %rd102, %rd103;
	mov.u16 	%rs98, 0;
	cvt.u16.u32 	%rs99, %r471;
	st.global.v2.u8 	[%rd104], {%rs99, %rs98};

$L__BB0_166:
	and.b32  	%r472, %r90, 4;
	setp.eq.s32 	%p194, %r472, 0;
	ld.const.u32 	%r502, [params+108];
	@%p194 bra 	$L__BB0_170;

	setp.eq.s32 	%p195, %r502, 0;
	ld.const.u64 	%rd105, [params+224];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r473, [params+216];
	mad.lo.s32 	%r474, %r473, %r6, %r5;
	mul.wide.u32 	%rd107, %r474, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p195 bra 	$L__BB0_169;

	ld.global.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1428, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1429, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1430, %rs108;}

	// end inline asm
	add.f32 	%f1431, %f1428, 0f00000000;
	add.f32 	%f1432, %f1429, 0f00000000;
	add.f32 	%f1433, %f1430, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1433;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1432;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1431;}

	// end inline asm
	mov.u16 	%rs110, 0;
	st.global.v4.u16 	[%rd28], {%rs103, %rs104, %rs105, %rs110};
	bra.uni 	$L__BB0_170;

$L__BB0_5:
	ld.const.u64 	%rd37, [params+432];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r106, [params+424];
	mad.lo.s32 	%r107, %r106, %r94, %r93;
	mul.wide.u32 	%rd39, %r107, 12;
	add.s64 	%rd40, %rd38, %rd39;
	ld.global.f32 	%f10, [%rd40];
	mul.f32 	%f431, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd40+4];
	mul.f32 	%f432, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd40+8];
	mul.f32 	%f433, %f12, 0f3456BF95;
	abs.f32 	%f13, %f1481;
	div.rn.f32 	%f434, %f431, %f13;
	abs.f32 	%f435, %f1482;
	div.rn.f32 	%f436, %f432, %f435;
	abs.f32 	%f14, %f1483;
	div.rn.f32 	%f437, %f433, %f14;
	abs.f32 	%f438, %f434;
	abs.f32 	%f439, %f436;
	abs.f32 	%f440, %f437;
	mov.f32 	%f441, 0f38D1B717;
	max.f32 	%f442, %f438, %f441;
	max.f32 	%f443, %f439, %f441;
	max.f32 	%f444, %f440, %f441;
	fma.rn.f32 	%f15, %f1481, %f442, %f10;
	fma.rn.f32 	%f16, %f1482, %f443, %f11;
	fma.rn.f32 	%f17, %f1483, %f444, %f12;
	ld.const.u64 	%rd41, [params+128];
	cvta.to.global.u64 	%rd42, %rd41;
	ld.const.u32 	%r108, [params+120];
	mad.lo.s32 	%r109, %r108, %r94, %r93;
	mul.wide.u32 	%rd43, %r109, 4;
	add.s64 	%rd44, %rd42, %rd43;
	ld.global.u32 	%r493, [%rd44];
	mov.u32 	%r489, 0;
	abs.s32 	%r110, %r3;
	setp.lt.s32 	%p18, %r110, 1;
	mov.pred 	%p17, 0;
	mov.f32 	%f1503, 0f00000000;
	mov.f32 	%f1504, %f1503;
	mov.f32 	%f1505, %f1503;
	mov.f32 	%f1506, %f1503;
	mov.f32 	%f1507, %f1503;
	mov.f32 	%f1508, %f1503;
	mov.f32 	%f1509, %f1503;
	mov.f32 	%f1510, %f1503;
	mov.f32 	%f1511, %f1503;
	mov.f32 	%f1512, %f1503;
	mov.f32 	%f1513, %f1503;
	mov.f32 	%f1514, %f1503;
	mov.f32 	%f1515, %f1503;
	mov.f32 	%f1516, %f1503;
	mov.f32 	%f1517, %f1503;
	mov.f32 	%f1518, %f1503;
	mov.pred 	%p200, %p17;
	@%p18 bra 	$L__BB0_25;

	ld.const.f32 	%f18, [params+620];
	ld.const.u64 	%rd45, [params+624];
	cvta.to.global.u64 	%rd3, %rd45;
	ld.const.u64 	%rd46, [params+640];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r113, [params+632];
	and.b32  	%r114, %r94, 255;
	and.b32  	%r115, %r93, 255;
	mad.lo.s32 	%r116, %r113, %r114, %r115;
	mul.wide.u32 	%rd48, %r116, 3;
	add.s64 	%rd4, %rd47, %rd48;
	ld.const.f32 	%f19, [params+660];
	mul.f32 	%f20, %f15, 0f3456BF95;
	mul.f32 	%f21, %f16, 0f3456BF95;
	mul.f32 	%f22, %f17, 0f3456BF95;
	ld.const.u64 	%rd5, [params+96];
	abs.f32 	%f588, %f21;
	abs.f32 	%f589, %f20;
	max.f32 	%f590, %f589, %f588;
	abs.f32 	%f591, %f22;
	max.f32 	%f592, %f590, %f591;
	mov.u32 	%r486, %r489;

$L__BB0_7:
	shl.b32 	%r117, %r486, 1;
	mul.wide.s32 	%rd49, %r117, 12;
	add.s64 	%rd6, %rd3, %rd49;
	ld.global.f32 	%f461, [%rd6];
	sub.f32 	%f462, %f461, %f10;
	ld.global.f32 	%f463, [%rd6+4];
	sub.f32 	%f464, %f463, %f11;
	ld.global.f32 	%f465, [%rd6+8];
	sub.f32 	%f466, %f465, %f12;
	mul.f32 	%f467, %f464, %f464;
	fma.rn.f32 	%f468, %f462, %f462, %f467;
	fma.rn.f32 	%f469, %f466, %f466, %f468;
	sqrt.rn.f32 	%f39, %f469;
	rcp.rn.f32 	%f470, %f39;
	mul.f32 	%f40, %f462, %f470;
	mul.f32 	%f41, %f464, %f470;
	mul.f32 	%f42, %f466, %f470;
	mul.f32 	%f471, %f1482, %f41;
	fma.rn.f32 	%f472, %f1481, %f40, %f471;
	fma.rn.f32 	%f43, %f1483, %f42, %f472;
	setp.leu.f32 	%p19, %f43, 0f00000000;
	@%p19 bra 	$L__BB0_24;

	setp.ne.s32 	%p21, %r4, 0;
	mul.f32 	%f473, %f39, %f39;
	div.rn.f32 	%f44, %f18, %f473;
	ld.global.u8 	%rs15, [%rd4];
	cvt.rn.f32.u16 	%f474, %rs15;
	div.rn.f32 	%f475, %f474, 0fC37F0000;
	fma.rn.f32 	%f476, %f475, 0f3F333333, 0f3F800000;
	setp.gt.f32 	%p22, %f44, %f476;
	and.pred  	%p23, %p21, %p22;
	mov.pred 	%p200, -1;
	@%p23 bra 	$L__BB0_25;

	mul.f32 	%f45, %f39, %f19;
	mov.f32 	%f481, 0f40800000;
	abs.f32 	%f47, %f45;
	setp.lt.f32 	%p24, %f47, 0f00800000;
	mul.f32 	%f483, %f47, 0f4B800000;
	selp.f32 	%f484, %f483, %f47, %p24;
	selp.f32 	%f485, 0fC3170000, 0fC2FE0000, %p24;
	mov.b32 	%r118, %f484;
	and.b32  	%r119, %r118, 8388607;
	or.b32  	%r120, %r119, 1065353216;
	mov.b32 	%f486, %r120;
	shr.u32 	%r121, %r118, 23;
	cvt.rn.f32.u32 	%f487, %r121;
	add.f32 	%f488, %f485, %f487;
	setp.gt.f32 	%p25, %f486, 0f3FB504F3;
	mul.f32 	%f489, %f486, 0f3F000000;
	add.f32 	%f490, %f488, 0f3F800000;
	selp.f32 	%f491, %f490, %f488, %p25;
	selp.f32 	%f492, %f489, %f486, %p25;
	add.f32 	%f493, %f492, 0fBF800000;
	add.f32 	%f494, %f492, 0f3F800000;
	rcp.approx.ftz.f32 	%f495, %f494;
	add.f32 	%f496, %f493, %f493;
	mul.f32 	%f497, %f496, %f495;
	mul.f32 	%f498, %f497, %f497;
	mov.f32 	%f499, 0f3C4CAF63;
	mov.f32 	%f500, 0f3B18F0FE;
	fma.rn.f32 	%f501, %f500, %f498, %f499;
	mov.f32 	%f502, 0f3DAAAABD;
	fma.rn.f32 	%f503, %f501, %f498, %f502;
	mul.rn.f32 	%f504, %f503, %f498;
	mul.rn.f32 	%f505, %f504, %f497;
	sub.f32 	%f506, %f493, %f497;
	add.f32 	%f507, %f506, %f506;
	neg.f32 	%f508, %f497;
	fma.rn.f32 	%f509, %f508, %f493, %f507;
	mul.rn.f32 	%f510, %f495, %f509;
	add.f32 	%f511, %f505, %f497;
	sub.f32 	%f512, %f497, %f511;
	add.f32 	%f513, %f505, %f512;
	add.f32 	%f514, %f510, %f513;
	add.f32 	%f515, %f511, %f514;
	sub.f32 	%f516, %f511, %f515;
	add.f32 	%f517, %f514, %f516;
	mov.f32 	%f518, 0f3F317200;
	mul.rn.f32 	%f519, %f491, %f518;
	mov.f32 	%f520, 0f35BFBE8E;
	mul.rn.f32 	%f521, %f491, %f520;
	add.f32 	%f522, %f519, %f515;
	sub.f32 	%f523, %f519, %f522;
	add.f32 	%f524, %f515, %f523;
	add.f32 	%f525, %f517, %f524;
	add.f32 	%f526, %f521, %f525;
	add.f32 	%f527, %f522, %f526;
	sub.f32 	%f528, %f522, %f527;
	add.f32 	%f529, %f526, %f528;
	mul.rn.f32 	%f530, %f481, %f527;
	neg.f32 	%f531, %f530;
	fma.rn.f32 	%f532, %f481, %f527, %f531;
	fma.rn.f32 	%f533, %f481, %f529, %f532;
	mov.f32 	%f534, 0f00000000;
	fma.rn.f32 	%f535, %f534, %f527, %f533;
	add.rn.f32 	%f536, %f530, %f535;
	neg.f32 	%f537, %f536;
	add.rn.f32 	%f538, %f530, %f537;
	add.rn.f32 	%f539, %f538, %f535;
	mov.b32 	%r122, %f536;
	setp.eq.s32 	%p26, %r122, 1118925336;
	add.s32 	%r123, %r122, -1;
	mov.b32 	%f540, %r123;
	add.f32 	%f541, %f539, 0f37000000;
	selp.f32 	%f48, %f541, %f539, %p26;
	selp.f32 	%f542, %f540, %f536, %p26;
	mov.f32 	%f543, 0f3FB8AA3B;
	mul.rn.f32 	%f544, %f542, %f543;
	cvt.rzi.f32.f32 	%f545, %f544;
	abs.f32 	%f546, %f545;
	setp.gt.f32 	%p27, %f546, 0f42FC0000;
	mov.b32 	%r124, %f545;
	and.b32  	%r125, %r124, -2147483648;
	or.b32  	%r126, %r125, 1123811328;
	mov.b32 	%f547, %r126;
	selp.f32 	%f548, %f547, %f545, %p27;
	mov.f32 	%f549, 0fBF317218;
	fma.rn.f32 	%f550, %f548, %f549, %f542;
	mov.f32 	%f551, 0f3102E308;
	fma.rn.f32 	%f552, %f548, %f551, %f550;
	mul.f32 	%f553, %f552, 0f3FB8AA3B;
	add.f32 	%f554, %f548, 0f4B40007F;
	mov.b32 	%r127, %f554;
	shl.b32 	%r128, %r127, 23;
	mov.b32 	%f555, %r128;
	ex2.approx.ftz.f32 	%f556, %f553;
	mul.f32 	%f49, %f556, %f555;
	setp.eq.f32 	%p28, %f49, 0f7F800000;
	mov.f32 	%f1500, 0f7F800000;
	@%p28 bra 	$L__BB0_11;

	fma.rn.f32 	%f1500, %f49, %f48, %f49;

$L__BB0_11:
	mov.f32 	%f1478, 0f40000000;
	cvt.rzi.f32.f32 	%f1477, %f1478;
	add.f32 	%f1476, %f1477, %f1477;
	mov.f32 	%f1475, 0f40800000;
	sub.f32 	%f1474, %f1475, %f1476;
	abs.f32 	%f1473, %f1474;
	setp.lt.f32 	%p29, %f45, 0f00000000;
	setp.eq.f32 	%p30, %f1473, 0f3F800000;
	and.pred  	%p1, %p29, %p30;
	setp.eq.f32 	%p31, %f45, 0f00000000;
	@%p31 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_12;

$L__BB0_15:
	add.f32 	%f561, %f45, %f45;
	selp.f32 	%f1502, %f561, 0f00000000, %p30;
	bra.uni 	$L__BB0_16;

$L__BB0_12:
	mov.b32 	%r129, %f1500;
	xor.b32  	%r130, %r129, -2147483648;
	mov.b32 	%f557, %r130;
	selp.f32 	%f1502, %f557, %f1500, %p1;
	setp.geu.f32 	%p32, %f45, 0f00000000;
	@%p32 bra 	$L__BB0_16;

	mov.f32 	%f558, 0f40800000;
	cvt.rzi.f32.f32 	%f559, %f558;
	setp.eq.f32 	%p33, %f559, 0f40800000;
	@%p33 bra 	$L__BB0_16;

	mov.f32 	%f1502, 0f7FFFFFFF;

$L__BB0_16:
	add.f32 	%f562, %f47, 0f40800000;
	mov.b32 	%r131, %f562;
	setp.lt.s32 	%p35, %r131, 2139095040;
	@%p35 bra 	$L__BB0_21;

	setp.gtu.f32 	%p36, %f47, 0f7F800000;
	@%p36 bra 	$L__BB0_20;
	bra.uni 	$L__BB0_18;

$L__BB0_20:
	add.f32 	%f1502, %f45, 0f40800000;
	bra.uni 	$L__BB0_21;

$L__BB0_18:
	setp.neu.f32 	%p37, %f47, 0f7F800000;
	@%p37 bra 	$L__BB0_21;

	selp.f32 	%f1502, 0fFF800000, 0f7F800000, %p1;

$L__BB0_21:
	shl.b32 	%r484, %r486, 1;
	mul.wide.s32 	%rd121, %r484, 12;
	add.s64 	%rd120, %rd3, %rd121;
	mov.f32 	%f563, 0f3F800000;
	sub.f32 	%f564, %f563, %f1502;
	setp.eq.f32 	%p38, %f45, 0f3F800000;
	selp.f32 	%f565, 0f00000000, %f564, %p38;
	cvt.sat.f32.f32 	%f566, %f565;
	mul.f32 	%f567, %f44, %f566;
	ld.global.f32 	%f568, [%rd120+12];
	mul.f32 	%f569, %f40, %f568;
	ld.global.f32 	%f570, [%rd120+16];
	mul.f32 	%f571, %f41, %f570;
	neg.f32 	%f572, %f571;
	sub.f32 	%f573, %f572, %f569;
	ld.global.f32 	%f574, [%rd120+20];
	mul.f32 	%f575, %f42, %f574;
	sub.f32 	%f576, %f573, %f575;
	cvt.sat.f32.f32 	%f577, %f576;
	mul.f32 	%f58, %f567, %f577;
	setp.leu.f32 	%p39, %f58, 0f3727C5AC;
	@%p39 bra 	$L__BB0_23;

	cvt.sat.f32.f32 	%f587, %f43;
	mov.f32 	%f593, 0f38D1B717;
	max.f32 	%f584, %f592, %f593;
	sub.f32 	%f585, %f39, %f584;
	mov.f32 	%f586, 0f00000000;
	mov.u32 	%r168, 2;
	mov.u32 	%r169, 1;
	mov.u32 	%r170, 3;
	mov.u32 	%r173, 1065353216;
	mov.u32 	%r202, 0;
	// begin inline asm
	call(%r132,%r133,%r134,%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163),_optix_trace_typed_32,(%r202,%rd5,%f15,%f16,%f17,%f40,%f41,%f42,%f584,%f585,%f586,%r169,%r202,%r169,%r168,%r169,%r170,%r173,%r173,%r173,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202);
	// end inline asm
	mov.b32 	%f594, %r132;
	mov.b32 	%f595, %r133;
	mov.b32 	%f596, %r134;
	mul.f32 	%f597, %f58, 0f3EA2F983;
	mul.f32 	%f598, %f597, %f594;
	mul.f32 	%f599, %f597, %f595;
	mul.f32 	%f600, %f597, %f596;
	fma.rn.f32 	%f1515, %f587, %f598, %f1515;
	fma.rn.f32 	%f1516, %f587, %f599, %f1516;
	fma.rn.f32 	%f1517, %f587, %f600, %f1517;
	mul.f32 	%f601, %f43, 0f40800000;
	cvt.sat.f32.f32 	%f602, %f601;
	mul.f32 	%f603, %f602, %f598;
	mul.f32 	%f604, %f602, %f599;
	mul.f32 	%f605, %f602, %f600;
	fma.rn.f32 	%f1509, %f40, %f603, %f1509;
	fma.rn.f32 	%f1510, %f40, %f604, %f1510;
	fma.rn.f32 	%f1511, %f40, %f605, %f1511;
	fma.rn.f32 	%f1506, %f41, %f603, %f1506;
	fma.rn.f32 	%f1507, %f41, %f604, %f1507;
	fma.rn.f32 	%f1508, %f41, %f605, %f1508;
	fma.rn.f32 	%f1503, %f42, %f603, %f1503;
	fma.rn.f32 	%f1504, %f42, %f604, %f1504;
	fma.rn.f32 	%f1505, %f42, %f605, %f1505;
	add.f32 	%f1512, %f1512, %f603;
	add.f32 	%f1513, %f1513, %f604;
	add.f32 	%f1514, %f1514, %f605;
	add.f32 	%f1518, %f1518, %f594;

$L__BB0_23:
	add.s32 	%r489, %r489, 1;

$L__BB0_24:
	add.s32 	%r486, %r486, 1;
	setp.lt.s32 	%p41, %r486, %r110;
	mov.pred 	%p200, %p17;
	@%p41 bra 	$L__BB0_7;

$L__BB0_25:
	cvt.rn.f32.s32 	%f606, %r489;
	mov.f32 	%f607, 0f3F800000;
	max.f32 	%f608, %f606, %f607;
	rcp.rn.f32 	%f609, %f608;
	mul.f32 	%f1620, %f1515, %f609;
	mul.f32 	%f1621, %f1516, %f609;
	mul.f32 	%f1622, %f1517, %f609;
	div.rn.f32 	%f1623, %f1518, %f608;
	mul.f32 	%f1617, %f1512, %f609;
	mul.f32 	%f1618, %f1513, %f609;
	mul.f32 	%f1619, %f1514, %f609;
	mul.f32 	%f1614, %f1509, %f609;
	mul.f32 	%f1615, %f1510, %f609;
	mul.f32 	%f1616, %f1511, %f609;
	mul.f32 	%f1611, %f1506, %f609;
	mul.f32 	%f1612, %f1507, %f609;
	mul.f32 	%f1613, %f1508, %f609;
	mul.f32 	%f1608, %f1503, %f609;
	mul.f32 	%f1609, %f1504, %f609;
	mul.f32 	%f1610, %f1505, %f609;
	not.pred 	%p42, %p200;
	@%p42 bra 	$L__BB0_58;

	abs.f32 	%f1480, %f1483;
	abs.f32 	%f1479, %f1481;
	setp.gt.f32 	%p43, %f1479, %f1480;
	selp.f32 	%f626, 0f00000000, %f1482, %p43;
	mov.f32 	%f1582, 0f00000000;
	neg.f32 	%f627, %f1483;
	selp.f32 	%f628, %f1481, %f627, %p43;
	neg.f32 	%f629, %f1482;
	selp.f32 	%f630, %f629, 0f00000000, %p43;
	mul.f32 	%f631, %f628, %f628;
	fma.rn.f32 	%f632, %f630, %f630, %f631;
	fma.rn.f32 	%f633, %f626, %f626, %f632;
	sqrt.rn.f32 	%f634, %f633;
	rcp.rn.f32 	%f635, %f634;
	mul.f32 	%f139, %f630, %f635;
	mul.f32 	%f140, %f628, %f635;
	mul.f32 	%f141, %f626, %f635;
	setp.lt.s32 	%p44, %r4, 1;
	mov.f32 	%f1581, %f1582;
	mov.f32 	%f1580, %f1582;
	mov.f32 	%f1579, %f1582;
	mov.f32 	%f1578, %f1582;
	mov.f32 	%f1577, %f1582;
	mov.f32 	%f1576, %f1582;
	mov.f32 	%f1575, %f1582;
	mov.f32 	%f1574, %f1582;
	mov.f32 	%f1573, %f1582;
	mov.f32 	%f1572, %f1582;
	mov.f32 	%f1571, %f1582;
	mov.f32 	%f1570, %f1582;
	mov.f32 	%f1569, %f1582;
	mov.f32 	%f1568, %f1582;
	mov.f32 	%f1567, %f1582;
	@%p44 bra 	$L__BB0_57;

	cvt.rn.f32.s32 	%f652, %r4;
	rcp.rn.f32 	%f142, %f652;
	mul.f32 	%f143, %f15, 0f3456BF95;
	mul.f32 	%f144, %f16, 0f3456BF95;
	mul.f32 	%f145, %f17, 0f3456BF95;
	ld.const.u64 	%rd7, [params+96];
	mul.f32 	%f653, %f1481, %f140;
	mul.f32 	%f654, %f1482, %f139;
	sub.f32 	%f146, %f654, %f653;
	mul.f32 	%f655, %f1483, %f139;
	mul.f32 	%f656, %f1481, %f141;
	sub.f32 	%f147, %f656, %f655;
	mul.f32 	%f657, %f1482, %f141;
	mul.f32 	%f658, %f1483, %f140;
	sub.f32 	%f148, %f658, %f657;
	mov.u32 	%r204, 0;
	add.s64 	%rd8, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f724, %f144;
	abs.f32 	%f725, %f143;
	max.f32 	%f726, %f725, %f724;
	abs.f32 	%f727, %f145;
	max.f32 	%f728, %f726, %f727;
	mov.u32 	%r490, %r204;

$L__BB0_28:
	cvt.rn.f32.s32 	%f165, %r490;
	mov.u32 	%r492, %r204;

$L__BB0_29:
	mad.lo.s32 	%r206, %r493, 1664525, 1013904223;
	and.b32  	%r207, %r206, 16777215;
	cvt.rn.f32.u32 	%f659, %r207;
	fma.rn.f32 	%f660, %f659, 0f33800000, %f165;
	mul.f32 	%f182, %f142, %f660;
	mad.lo.s32 	%r493, %r206, 1664525, 1013904223;
	and.b32  	%r208, %r493, 16777215;
	cvt.rn.f32.u32 	%f661, %r208;
	cvt.rn.f32.s32 	%f662, %r492;
	fma.rn.f32 	%f663, %f661, 0f33800000, %f662;
	mul.f32 	%f664, %f142, %f663;
	mul.f32 	%f665, %f182, %f182;
	mov.f32 	%f666, 0f3F800000;
	sub.f32 	%f667, %f666, %f665;
	mov.f32 	%f668, 0f00000000;
	max.f32 	%f669, %f668, %f667;
	sqrt.rn.f32 	%f183, %f669;
	mul.f32 	%f184, %f664, 0f40C90FDB;
	mul.f32 	%f670, %f184, 0f3F22F983;
	cvt.rni.s32.f32 	%r500, %f670;
	cvt.rn.f32.s32 	%f671, %r500;
	mov.f32 	%f672, 0fBFC90FDA;
	fma.rn.f32 	%f673, %f671, %f672, %f184;
	mov.f32 	%f674, 0fB3A22168;
	fma.rn.f32 	%f675, %f671, %f674, %f673;
	mov.f32 	%f676, 0fA7C234C5;
	fma.rn.f32 	%f1586, %f671, %f676, %f675;
	abs.f32 	%f186, %f184;
	setp.ltu.f32 	%p45, %f186, 0f47CE4780;
	mov.u32 	%r497, %r500;
	mov.f32 	%f1583, %f1586;
	@%p45 bra 	$L__BB0_37;

	setp.eq.f32 	%p46, %f186, 0f7F800000;
	@%p46 bra 	$L__BB0_36;
	bra.uni 	$L__BB0_31;

$L__BB0_36:
	mov.f32 	%f679, 0f00000000;
	mul.rn.f32 	%f1583, %f184, %f679;
	mov.u32 	%r497, 0;
	bra.uni 	$L__BB0_37;

$L__BB0_31:
	mov.b32 	%r20, %f184;
	bfe.u32 	%r210, %r20, 23, 8;
	add.s32 	%r21, %r210, -128;
	shl.b32 	%r211, %r20, 8;
	or.b32  	%r22, %r211, -2147483648;
	shr.u32 	%r23, %r21, 5;
	mov.u64 	%rd124, 0;
	mov.u32 	%r494, 0;
	mov.u64 	%rd122, %rd1;
	mov.u64 	%rd123, %rd51;

$L__BB0_32:
	.pragma "nounroll";
	ld.global.nc.u32 	%r212, [%rd123];
	mad.wide.u32 	%rd53, %r212, %r22, %rd124;
	shr.u64 	%rd124, %rd53, 32;
	st.local.u32 	[%rd122], %rd53;
	add.s64 	%rd123, %rd123, 4;
	add.s64 	%rd122, %rd122, 4;
	add.s32 	%r494, %r494, 1;
	setp.ne.s32 	%p47, %r494, 6;
	@%p47 bra 	$L__BB0_32;

	st.local.u32 	[%rd8], %rd124;
	mov.u32 	%r213, 4;
	sub.s32 	%r26, %r213, %r23;
	mov.u32 	%r214, 6;
	sub.s32 	%r215, %r214, %r23;
	mul.wide.s32 	%rd54, %r215, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r495, [%rd55];
	ld.local.u32 	%r496, [%rd55+-4];
	and.b32  	%r29, %r21, 31;
	setp.eq.s32 	%p48, %r29, 0;
	@%p48 bra 	$L__BB0_35;

	mov.u32 	%r216, 32;
	sub.s32 	%r217, %r216, %r29;
	shr.u32 	%r218, %r496, %r217;
	shl.b32 	%r219, %r495, %r29;
	add.s32 	%r495, %r218, %r219;
	mul.wide.s32 	%rd56, %r26, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r220, [%rd57];
	shr.u32 	%r221, %r220, %r217;
	shl.b32 	%r222, %r496, %r29;
	add.s32 	%r496, %r221, %r222;

$L__BB0_35:
	and.b32  	%r223, %r20, -2147483648;
	shr.u32 	%r224, %r496, 30;
	shl.b32 	%r225, %r495, 2;
	or.b32  	%r226, %r224, %r225;
	shr.u32 	%r227, %r226, 31;
	shr.u32 	%r228, %r495, 30;
	add.s32 	%r229, %r227, %r228;
	neg.s32 	%r230, %r229;
	setp.eq.s32 	%p49, %r223, 0;
	selp.b32 	%r497, %r229, %r230, %p49;
	setp.ne.s32 	%p50, %r227, 0;
	xor.b32  	%r231, %r223, -2147483648;
	selp.b32 	%r232, %r231, %r223, %p50;
	selp.b32 	%r233, -1, 0, %p50;
	xor.b32  	%r234, %r226, %r233;
	shl.b32 	%r235, %r496, 2;
	xor.b32  	%r236, %r235, %r233;
	cvt.u64.u32 	%rd58, %r234;
	cvt.u64.u32 	%rd59, %r236;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f677, %fd2;
	setp.eq.s32 	%p51, %r232, 0;
	neg.f32 	%f678, %f677;
	selp.f32 	%f1583, %f677, %f678, %p51;

$L__BB0_37:
	add.s32 	%r36, %r497, 1;
	and.b32  	%r37, %r36, 1;
	setp.eq.s32 	%p52, %r37, 0;
	selp.f32 	%f190, %f1583, 0f3F800000, %p52;
	mul.rn.f32 	%f191, %f1583, %f1583;
	mov.f32 	%f1584, 0fB94D4153;
	@%p52 bra 	$L__BB0_39;

	mov.f32 	%f681, 0fBAB607ED;
	mov.f32 	%f682, 0f37CBAC00;
	fma.rn.f32 	%f1584, %f682, %f191, %f681;

$L__BB0_39:
	selp.f32 	%f683, 0f3C0885E4, 0f3D2AAABB, %p52;
	fma.rn.f32 	%f684, %f1584, %f191, %f683;
	selp.f32 	%f685, 0fBE2AAAA8, 0fBEFFFFFF, %p52;
	fma.rn.f32 	%f686, %f684, %f191, %f685;
	mov.f32 	%f687, 0f00000000;
	fma.rn.f32 	%f688, %f191, %f190, %f687;
	fma.rn.f32 	%f1585, %f686, %f688, %f190;
	and.b32  	%r238, %r36, 2;
	setp.eq.s32 	%p54, %r238, 0;
	@%p54 bra 	$L__BB0_41;

	mov.f32 	%f690, 0fBF800000;
	fma.rn.f32 	%f1585, %f1585, %f690, %f687;

$L__BB0_41:
	@%p45 bra 	$L__BB0_49;

	setp.eq.f32 	%p56, %f186, 0f7F800000;
	@%p56 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_43;

$L__BB0_48:
	mov.f32 	%f693, 0f00000000;
	mul.rn.f32 	%f1586, %f184, %f693;
	mov.u32 	%r500, 0;
	bra.uni 	$L__BB0_49;

$L__BB0_43:
	mov.b32 	%r38, %f184;
	bfe.u32 	%r239, %r38, 23, 8;
	add.s32 	%r39, %r239, -128;
	shl.b32 	%r240, %r38, 8;
	or.b32  	%r40, %r240, -2147483648;
	shr.u32 	%r41, %r39, 5;
	mov.u64 	%rd125, 0;
	mov.u64 	%rd126, %rd125;

$L__BB0_44:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd125, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r241, [%rd65];
	mad.wide.u32 	%rd66, %r241, %r40, %rd126;
	shr.u64 	%rd126, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r242, %rd125;
	add.s32 	%r243, %r242, 1;
	cvt.s64.s32 	%rd125, %r243;
	setp.ne.s32 	%p57, %r243, 6;
	@%p57 bra 	$L__BB0_44;

	st.local.u32 	[%rd8], %rd126;
	mov.u32 	%r244, 4;
	sub.s32 	%r42, %r244, %r41;
	mov.u32 	%r245, 6;
	sub.s32 	%r246, %r245, %r41;
	mul.wide.s32 	%rd68, %r246, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r498, [%rd69];
	ld.local.u32 	%r499, [%rd69+-4];
	and.b32  	%r45, %r39, 31;
	setp.eq.s32 	%p58, %r45, 0;
	@%p58 bra 	$L__BB0_47;

	mov.u32 	%r247, 32;
	sub.s32 	%r248, %r247, %r45;
	shr.u32 	%r249, %r499, %r248;
	shl.b32 	%r250, %r498, %r45;
	add.s32 	%r498, %r249, %r250;
	mul.wide.s32 	%rd70, %r42, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r251, [%rd71];
	shr.u32 	%r252, %r251, %r248;
	shl.b32 	%r253, %r499, %r45;
	add.s32 	%r499, %r252, %r253;

$L__BB0_47:
	and.b32  	%r254, %r38, -2147483648;
	shr.u32 	%r255, %r499, 30;
	shl.b32 	%r256, %r498, 2;
	or.b32  	%r257, %r255, %r256;
	shr.u32 	%r258, %r257, 31;
	shr.u32 	%r259, %r498, 30;
	add.s32 	%r260, %r258, %r259;
	neg.s32 	%r261, %r260;
	setp.eq.s32 	%p59, %r254, 0;
	selp.b32 	%r500, %r260, %r261, %p59;
	setp.ne.s32 	%p60, %r258, 0;
	xor.b32  	%r262, %r254, -2147483648;
	selp.b32 	%r263, %r262, %r254, %p60;
	selp.b32 	%r264, -1, 0, %p60;
	xor.b32  	%r265, %r257, %r264;
	shl.b32 	%r266, %r499, 2;
	xor.b32  	%r267, %r266, %r264;
	cvt.u64.u32 	%rd72, %r265;
	cvt.u64.u32 	%rd73, %r267;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f691, %fd4;
	setp.eq.s32 	%p61, %r263, 0;
	neg.f32 	%f692, %f691;
	selp.f32 	%f1586, %f691, %f692, %p61;

$L__BB0_49:
	mul.f32 	%f200, %f183, %f1585;
	and.b32  	%r52, %r500, 1;
	setp.eq.s32 	%p62, %r52, 0;
	selp.f32 	%f201, %f1586, 0f3F800000, %p62;
	mul.rn.f32 	%f202, %f1586, %f1586;
	mov.f32 	%f1587, 0fB94D4153;
	@%p62 bra 	$L__BB0_51;

	mov.f32 	%f695, 0fBAB607ED;
	mov.f32 	%f696, 0f37CBAC00;
	fma.rn.f32 	%f1587, %f696, %f202, %f695;

$L__BB0_51:
	selp.f32 	%f697, 0f3C0885E4, 0f3D2AAABB, %p62;
	fma.rn.f32 	%f698, %f1587, %f202, %f697;
	selp.f32 	%f699, 0fBE2AAAA8, 0fBEFFFFFF, %p62;
	fma.rn.f32 	%f700, %f698, %f202, %f699;
	mov.f32 	%f1589, 0f00000000;
	fma.rn.f32 	%f702, %f202, %f201, %f1589;
	fma.rn.f32 	%f1588, %f700, %f702, %f201;
	and.b32  	%r269, %r500, 2;
	setp.eq.s32 	%p64, %r269, 0;
	@%p64 bra 	$L__BB0_53;

	mov.f32 	%f703, 0f00000000;
	mov.f32 	%f704, 0fBF800000;
	fma.rn.f32 	%f1588, %f1588, %f704, %f703;

$L__BB0_53:
	mul.f32 	%f717, %f183, %f1588;
	mul.f32 	%f718, %f139, %f717;
	mul.f32 	%f719, %f140, %f717;
	mul.f32 	%f720, %f141, %f717;
	fma.rn.f32 	%f721, %f148, %f200, %f718;
	fma.rn.f32 	%f722, %f147, %f200, %f719;
	fma.rn.f32 	%f723, %f146, %f200, %f720;
	fma.rn.f32 	%f208, %f1481, %f182, %f721;
	fma.rn.f32 	%f209, %f1482, %f182, %f722;
	fma.rn.f32 	%f210, %f1483, %f182, %f723;
	mov.f32 	%f729, 0f38D1B717;
	max.f32 	%f711, %f728, %f729;
	mov.f32 	%f712, 0f6C4ECB8F;
	mov.u32 	%r303, 1;
	mov.u32 	%r306, 2;
	mov.u32 	%r308, 4;
	mov.u32 	%r311, 1065353216;
	mov.u32 	%r312, 2139095039;
	mov.u32 	%r340, 0;
	// begin inline asm
	call(%r270,%r271,%r272,%r273,%r274,%r275,%r276,%r277,%r278,%r279,%r280,%r281,%r282,%r283,%r284,%r285,%r286,%r287,%r288,%r289,%r290,%r291,%r292,%r293,%r294,%r295,%r296,%r297,%r298,%r299,%r300,%r301),_optix_trace_typed_32,(%r340,%rd7,%f15,%f16,%f17,%f208,%f209,%f210,%f711,%f712,%f1589,%r303,%r340,%r340,%r306,%r340,%r308,%r311,%r311,%r311,%r312,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340,%r340);
	// end inline asm
	mov.b32 	%f211, %r273;
	setp.ge.f32 	%p65, %f211, 0f00000000;
	mov.f32 	%f1590, %f1589;
	mov.f32 	%f1591, %f1589;
	@%p65 bra 	$L__BB0_55;

	mov.b32 	%f1591, %r270;
	mov.b32 	%f1590, %r271;
	mov.b32 	%f1589, %r272;

$L__BB0_55:
	setp.ltu.f32 	%p66, %f211, 0f00000000;
	selp.f32 	%f730, 0f3F800000, 0f00000000, %p66;
	add.f32 	%f1567, %f1567, %f730;
	fma.rn.f32 	%f1576, %f208, %f1591, %f1576;
	fma.rn.f32 	%f1575, %f208, %f1590, %f1575;
	fma.rn.f32 	%f1574, %f208, %f1589, %f1574;
	fma.rn.f32 	%f1579, %f209, %f1591, %f1579;
	fma.rn.f32 	%f1578, %f209, %f1590, %f1578;
	fma.rn.f32 	%f1577, %f209, %f1589, %f1577;
	fma.rn.f32 	%f1582, %f210, %f1591, %f1582;
	fma.rn.f32 	%f1581, %f210, %f1590, %f1581;
	fma.rn.f32 	%f1580, %f210, %f1589, %f1580;
	add.f32 	%f1573, %f1573, %f1591;
	add.f32 	%f1572, %f1572, %f1590;
	add.f32 	%f1571, %f1571, %f1589;
	mul.f32 	%f731, %f1482, %f209;
	fma.rn.f32 	%f732, %f1481, %f208, %f731;
	fma.rn.f32 	%f733, %f1483, %f210, %f732;
	cvt.sat.f32.f32 	%f734, %f733;
	fma.rn.f32 	%f1570, %f1591, %f734, %f1570;
	fma.rn.f32 	%f1569, %f1590, %f734, %f1569;
	fma.rn.f32 	%f1568, %f1589, %f734, %f1568;
	add.s32 	%r492, %r492, 1;
	setp.lt.s32 	%p67, %r492, %r4;
	@%p67 bra 	$L__BB0_29;

	add.s32 	%r490, %r490, 1;
	setp.lt.s32 	%p68, %r490, %r4;
	@%p68 bra 	$L__BB0_28;

$L__BB0_57:
	mul.lo.s32 	%r341, %r4, %r4;
	cvt.rn.f32.s32 	%f735, %r341;
	rcp.rn.f32 	%f736, %f735;
	mul.f32 	%f737, %f736, %f1570;
	mul.f32 	%f738, %f736, %f1569;
	mul.f32 	%f739, %f736, %f1568;
	div.rn.f32 	%f1623, %f1567, %f735;
	mul.f32 	%f1617, %f736, %f1573;
	mul.f32 	%f1618, %f736, %f1572;
	mul.f32 	%f1619, %f736, %f1571;
	mul.f32 	%f1614, %f736, %f1576;
	mul.f32 	%f1615, %f736, %f1575;
	mul.f32 	%f1616, %f736, %f1574;
	mul.f32 	%f1611, %f736, %f1579;
	mul.f32 	%f1612, %f736, %f1578;
	mul.f32 	%f1613, %f736, %f1577;
	mul.f32 	%f1608, %f736, %f1582;
	mul.f32 	%f1609, %f736, %f1581;
	mul.f32 	%f1610, %f736, %f1580;
	fma.rn.f32 	%f1620, %f736, %f1570, %f737;
	fma.rn.f32 	%f1621, %f736, %f1569, %f738;
	fma.rn.f32 	%f1622, %f736, %f1568, %f739;

$L__BB0_58:
	ld.const.u32 	%r485, [params+616];
	setp.lt.s32 	%p69, %r485, 0;
	selp.f32 	%f282, %f1620, %f1623, %p69;
	ld.const.u32 	%r87, [params+104];
	and.b32  	%r342, %r87, 8;
	setp.eq.s32 	%p70, %r342, 0;
	@%p70 bra 	$L__BB0_72;

	ld.const.u64 	%rd76, [params+192];
	cvta.to.global.u64 	%rd19, %rd76;
	ld.const.u32 	%r343, [params+184];
	mad.lo.s32 	%r344, %r343, %r6, %r5;
	cvt.u64.u32 	%rd20, %r344;
	mov.f32 	%f741, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f742, %f741;
	add.f32 	%f743, %f742, %f742;
	mov.f32 	%f744, 0f3EE8BA2E;
	sub.f32 	%f745, %f744, %f743;
	abs.f32 	%f283, %f745;
	abs.f32 	%f284, %f282;
	setp.lt.f32 	%p71, %f284, 0f00800000;
	mul.f32 	%f746, %f284, 0f4B800000;
	selp.f32 	%f747, %f746, %f284, %p71;
	selp.f32 	%f748, 0fC3170000, 0fC2FE0000, %p71;
	mov.b32 	%r345, %f747;
	and.b32  	%r346, %r345, 8388607;
	or.b32  	%r347, %r346, 1065353216;
	mov.b32 	%f749, %r347;
	shr.u32 	%r348, %r345, 23;
	cvt.rn.f32.u32 	%f750, %r348;
	add.f32 	%f751, %f748, %f750;
	setp.gt.f32 	%p72, %f749, 0f3FB504F3;
	mul.f32 	%f752, %f749, 0f3F000000;
	add.f32 	%f753, %f751, 0f3F800000;
	selp.f32 	%f754, %f753, %f751, %p72;
	selp.f32 	%f755, %f752, %f749, %p72;
	add.f32 	%f756, %f755, 0fBF800000;
	add.f32 	%f757, %f755, 0f3F800000;
	rcp.approx.ftz.f32 	%f758, %f757;
	add.f32 	%f759, %f756, %f756;
	mul.f32 	%f760, %f759, %f758;
	mul.f32 	%f761, %f760, %f760;
	mov.f32 	%f762, 0f3C4CAF63;
	mov.f32 	%f763, 0f3B18F0FE;
	fma.rn.f32 	%f764, %f763, %f761, %f762;
	mov.f32 	%f765, 0f3DAAAABD;
	fma.rn.f32 	%f766, %f764, %f761, %f765;
	mul.rn.f32 	%f767, %f766, %f761;
	mul.rn.f32 	%f768, %f767, %f760;
	sub.f32 	%f769, %f756, %f760;
	add.f32 	%f770, %f769, %f769;
	neg.f32 	%f771, %f760;
	fma.rn.f32 	%f772, %f771, %f756, %f770;
	mul.rn.f32 	%f773, %f758, %f772;
	add.f32 	%f774, %f768, %f760;
	sub.f32 	%f775, %f760, %f774;
	add.f32 	%f776, %f768, %f775;
	add.f32 	%f777, %f773, %f776;
	add.f32 	%f778, %f774, %f777;
	sub.f32 	%f779, %f774, %f778;
	add.f32 	%f780, %f777, %f779;
	mov.f32 	%f781, 0f3F317200;
	mul.rn.f32 	%f782, %f754, %f781;
	mov.f32 	%f783, 0f35BFBE8E;
	mul.rn.f32 	%f784, %f754, %f783;
	add.f32 	%f785, %f782, %f778;
	sub.f32 	%f786, %f782, %f785;
	add.f32 	%f787, %f778, %f786;
	add.f32 	%f788, %f780, %f787;
	add.f32 	%f789, %f784, %f788;
	add.f32 	%f790, %f785, %f789;
	sub.f32 	%f791, %f785, %f790;
	add.f32 	%f792, %f789, %f791;
	mul.rn.f32 	%f793, %f744, %f790;
	neg.f32 	%f794, %f793;
	fma.rn.f32 	%f795, %f744, %f790, %f794;
	fma.rn.f32 	%f796, %f744, %f792, %f795;
	mov.f32 	%f797, 0f00000000;
	fma.rn.f32 	%f798, %f797, %f790, %f796;
	add.rn.f32 	%f799, %f793, %f798;
	neg.f32 	%f800, %f799;
	add.rn.f32 	%f801, %f793, %f800;
	add.rn.f32 	%f802, %f801, %f798;
	mov.b32 	%r349, %f799;
	setp.eq.s32 	%p73, %r349, 1118925336;
	add.s32 	%r350, %r349, -1;
	mov.b32 	%f803, %r350;
	add.f32 	%f804, %f802, 0f37000000;
	selp.f32 	%f285, %f804, %f802, %p73;
	selp.f32 	%f805, %f803, %f799, %p73;
	mov.f32 	%f806, 0f3FB8AA3B;
	mul.rn.f32 	%f807, %f805, %f806;
	cvt.rzi.f32.f32 	%f808, %f807;
	abs.f32 	%f809, %f808;
	setp.gt.f32 	%p74, %f809, 0f42FC0000;
	mov.b32 	%r351, %f808;
	and.b32  	%r352, %r351, -2147483648;
	or.b32  	%r353, %r352, 1123811328;
	mov.b32 	%f810, %r353;
	selp.f32 	%f811, %f810, %f808, %p74;
	mov.f32 	%f812, 0fBF317218;
	fma.rn.f32 	%f813, %f811, %f812, %f805;
	mov.f32 	%f814, 0f3102E308;
	fma.rn.f32 	%f815, %f811, %f814, %f813;
	mul.f32 	%f816, %f815, 0f3FB8AA3B;
	add.f32 	%f817, %f811, 0f4B40007F;
	mov.b32 	%r354, %f817;
	shl.b32 	%r355, %r354, 23;
	mov.b32 	%f818, %r355;
	ex2.approx.ftz.f32 	%f819, %f816;
	mul.f32 	%f286, %f819, %f818;
	setp.eq.f32 	%p75, %f286, 0f7F800000;
	mov.f32 	%f1624, 0f7F800000;
	@%p75 bra 	$L__BB0_61;

	fma.rn.f32 	%f1624, %f286, %f285, %f286;

$L__BB0_61:
	setp.lt.f32 	%p76, %f282, 0f00000000;
	setp.eq.f32 	%p77, %f283, 0f3F800000;
	and.pred  	%p3, %p76, %p77;
	setp.eq.f32 	%p78, %f282, 0f00000000;
	@%p78 bra 	$L__BB0_65;
	bra.uni 	$L__BB0_62;

$L__BB0_65:
	add.f32 	%f824, %f282, %f282;
	selp.f32 	%f1626, %f824, 0f00000000, %p77;
	bra.uni 	$L__BB0_66;

$L__BB0_169:
	mov.f32 	%f1436, 0f00000000;
	mov.u32 	%r502, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1436;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1436;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1436;}

	// end inline asm
	mov.u16 	%rs114, 0;
	st.global.v4.u16 	[%rd28], {%rs111, %rs112, %rs113, %rs114};

$L__BB0_170:
	ld.const.u64 	%rd108, [params+256];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r476, [params+248];
	mad.lo.s32 	%r477, %r476, %r6, %r5;
	mul.wide.u32 	%rd110, %r477, 8;
	add.s64 	%rd29, %rd109, %rd110;
	setp.eq.s32 	%p196, %r502, 0;
	@%p196 bra 	$L__BB0_172;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1437, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1438, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1439, %rs123;}

	// end inline asm
	add.f32 	%f1440, %f1437, 0f00000000;
	add.f32 	%f1441, %f1438, 0f00000000;
	add.f32 	%f1442, %f1439, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1442;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1441;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1440;}

	// end inline asm
	mov.u16 	%rs125, 0;
	st.global.v4.u16 	[%rd29], {%rs118, %rs119, %rs120, %rs125};
	bra.uni 	$L__BB0_173;

$L__BB0_172:
	mov.f32 	%f1445, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1445;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1445;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1445;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd29], {%rs126, %rs127, %rs128, %rs129};

$L__BB0_173:
	ld.const.u64 	%rd111, [params+272];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r478, [params+264];
	mad.lo.s32 	%r479, %r478, %r6, %r5;
	mul.wide.u32 	%rd113, %r479, 8;
	add.s64 	%rd30, %rd112, %rd113;
	@%p196 bra 	$L__BB0_175;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1446, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1447, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1448, %rs138;}

	// end inline asm
	add.f32 	%f1449, %f1446, 0f00000000;
	add.f32 	%f1450, %f1447, 0f00000000;
	add.f32 	%f1451, %f1448, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1451;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1450;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1449;}

	// end inline asm
	mov.u16 	%rs140, 0;
	st.global.v4.u16 	[%rd30], {%rs133, %rs134, %rs135, %rs140};
	bra.uni 	$L__BB0_176;

$L__BB0_175:
	mov.f32 	%f1454, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1454;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1454;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1454;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd30], {%rs141, %rs142, %rs143, %rs144};

$L__BB0_176:
	ld.const.u64 	%rd114, [params+288];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r480, [params+280];
	mad.lo.s32 	%r481, %r480, %r6, %r5;
	mul.wide.u32 	%rd116, %r481, 8;
	add.s64 	%rd31, %rd115, %rd116;
	@%p196 bra 	$L__BB0_178;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1455, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1456, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1457, %rs153;}

	// end inline asm
	add.f32 	%f1458, %f1455, 0f00000000;
	add.f32 	%f1459, %f1456, 0f00000000;
	add.f32 	%f1460, %f1457, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1460;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1459;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1458;}

	// end inline asm
	mov.u16 	%rs155, 0;
	st.global.v4.u16 	[%rd31], {%rs148, %rs149, %rs150, %rs155};
	bra.uni 	$L__BB0_179;

$L__BB0_178:
	mov.f32 	%f1463, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1463;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1463;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1463;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd31], {%rs156, %rs157, %rs158, %rs159};

$L__BB0_179:
	ld.const.u64 	%rd117, [params+304];
	cvta.to.global.u64 	%rd118, %rd117;
	ld.const.u32 	%r482, [params+296];
	mad.lo.s32 	%r483, %r482, %r6, %r5;
	mul.wide.u32 	%rd119, %r483, 8;
	add.s64 	%rd32, %rd118, %rd119;
	@%p196 bra 	$L__BB0_181;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1464, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1465, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1466, %rs168;}

	// end inline asm
	add.f32 	%f1467, %f1464, 0f00000000;
	add.f32 	%f1468, %f1465, 0f00000000;
	add.f32 	%f1469, %f1466, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1469;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1468;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1467;}

	// end inline asm
	mov.u16 	%rs170, 0;
	st.global.v4.u16 	[%rd32], {%rs163, %rs164, %rs165, %rs170};
	bra.uni 	$L__BB0_182;

$L__BB0_181:
	mov.f32 	%f1472, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1472;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1472;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1472;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd32], {%rs171, %rs172, %rs173, %rs174};
	bra.uni 	$L__BB0_182;

$L__BB0_62:
	mov.b32 	%r356, %f1624;
	xor.b32  	%r357, %r356, -2147483648;
	mov.b32 	%f820, %r357;
	selp.f32 	%f1626, %f820, %f1624, %p3;
	setp.geu.f32 	%p79, %f282, 0f00000000;
	@%p79 bra 	$L__BB0_66;

	mov.f32 	%f821, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f822, %f821;
	setp.eq.f32 	%p80, %f822, 0f3EE8BA2E;
	@%p80 bra 	$L__BB0_66;

	mov.f32 	%f1626, 0f7FFFFFFF;

$L__BB0_66:
	add.f32 	%f825, %f284, 0f3EE8BA2E;
	mov.b32 	%r358, %f825;
	setp.lt.s32 	%p82, %r358, 2139095040;
	@%p82 bra 	$L__BB0_71;

	setp.gtu.f32 	%p83, %f284, 0f7F800000;
	@%p83 bra 	$L__BB0_70;
	bra.uni 	$L__BB0_68;

$L__BB0_70:
	add.f32 	%f1626, %f282, 0f3EE8BA2E;
	bra.uni 	$L__BB0_71;

$L__BB0_68:
	setp.neu.f32 	%p84, %f284, 0f7F800000;
	@%p84 bra 	$L__BB0_71;

	selp.f32 	%f1626, 0fFF800000, 0f7F800000, %p3;

$L__BB0_71:
	mul.f32 	%f826, %f1626, 0f437F0000;
	setp.eq.f32 	%p85, %f282, 0f3F800000;
	selp.f32 	%f827, 0f437F0000, %f826, %p85;
	cvt.rzi.u32.f32 	%r359, %f827;
	shl.b64 	%rd77, %rd20, 1;
	add.s64 	%rd78, %rd19, %rd77;
	cvt.u16.u32 	%rs16, %r359;
	mov.u16 	%rs17, 255;
	st.global.v2.u8 	[%rd78], {%rs16, %rs17};

$L__BB0_72:
	ld.const.v2.f32 	{%f828, %f829}, [params+648];
	mul.f32 	%f297, %f1620, %f828;
	mul.f32 	%f298, %f1621, %f829;
	ld.const.f32 	%f299, [params+656];
	mul.f32 	%f300, %f1622, %f299;
	and.b32  	%r360, %r87, 1;
	setp.eq.b32 	%p86, %r360, 1;
	mov.pred 	%p87, 0;
	xor.pred  	%p88, %p86, %p87;
	not.pred 	%p89, %p88;
	@%p89 bra 	$L__BB0_146;

	mov.f32 	%f831, 0f3E666666;
	cvt.rzi.f32.f32 	%f832, %f831;
	add.f32 	%f833, %f832, %f832;
	mov.f32 	%f834, 0f3EE66666;
	sub.f32 	%f835, %f834, %f833;
	abs.f32 	%f301, %f835;
	abs.f32 	%f302, %f297;
	setp.lt.f32 	%p90, %f302, 0f00800000;
	mul.f32 	%f836, %f302, 0f4B800000;
	selp.f32 	%f837, %f836, %f302, %p90;
	selp.f32 	%f838, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r361, %f837;
	and.b32  	%r362, %r361, 8388607;
	or.b32  	%r363, %r362, 1065353216;
	mov.b32 	%f839, %r363;
	shr.u32 	%r364, %r361, 23;
	cvt.rn.f32.u32 	%f840, %r364;
	add.f32 	%f841, %f838, %f840;
	setp.gt.f32 	%p91, %f839, 0f3FB504F3;
	mul.f32 	%f842, %f839, 0f3F000000;
	add.f32 	%f843, %f841, 0f3F800000;
	selp.f32 	%f844, %f843, %f841, %p91;
	selp.f32 	%f845, %f842, %f839, %p91;
	add.f32 	%f846, %f845, 0fBF800000;
	add.f32 	%f847, %f845, 0f3F800000;
	rcp.approx.ftz.f32 	%f848, %f847;
	add.f32 	%f849, %f846, %f846;
	mul.f32 	%f850, %f849, %f848;
	mul.f32 	%f851, %f850, %f850;
	mov.f32 	%f852, 0f3C4CAF63;
	mov.f32 	%f853, 0f3B18F0FE;
	fma.rn.f32 	%f854, %f853, %f851, %f852;
	mov.f32 	%f855, 0f3DAAAABD;
	fma.rn.f32 	%f856, %f854, %f851, %f855;
	mul.rn.f32 	%f857, %f856, %f851;
	mul.rn.f32 	%f858, %f857, %f850;
	sub.f32 	%f859, %f846, %f850;
	add.f32 	%f860, %f859, %f859;
	neg.f32 	%f861, %f850;
	fma.rn.f32 	%f862, %f861, %f846, %f860;
	mul.rn.f32 	%f863, %f848, %f862;
	add.f32 	%f864, %f858, %f850;
	sub.f32 	%f865, %f850, %f864;
	add.f32 	%f866, %f858, %f865;
	add.f32 	%f867, %f863, %f866;
	add.f32 	%f868, %f864, %f867;
	sub.f32 	%f869, %f864, %f868;
	add.f32 	%f870, %f867, %f869;
	mov.f32 	%f871, 0f3F317200;
	mul.rn.f32 	%f872, %f844, %f871;
	mov.f32 	%f873, 0f35BFBE8E;
	mul.rn.f32 	%f874, %f844, %f873;
	add.f32 	%f875, %f872, %f868;
	sub.f32 	%f876, %f872, %f875;
	add.f32 	%f877, %f868, %f876;
	add.f32 	%f878, %f870, %f877;
	add.f32 	%f879, %f874, %f878;
	add.f32 	%f880, %f875, %f879;
	sub.f32 	%f881, %f875, %f880;
	add.f32 	%f882, %f879, %f881;
	mul.rn.f32 	%f883, %f834, %f880;
	neg.f32 	%f884, %f883;
	fma.rn.f32 	%f885, %f834, %f880, %f884;
	fma.rn.f32 	%f886, %f834, %f882, %f885;
	mov.f32 	%f887, 0f00000000;
	fma.rn.f32 	%f888, %f887, %f880, %f886;
	add.rn.f32 	%f889, %f883, %f888;
	neg.f32 	%f890, %f889;
	add.rn.f32 	%f891, %f883, %f890;
	add.rn.f32 	%f892, %f891, %f888;
	mov.b32 	%r365, %f889;
	setp.eq.s32 	%p92, %r365, 1118925336;
	add.s32 	%r366, %r365, -1;
	mov.b32 	%f893, %r366;
	add.f32 	%f894, %f892, 0f37000000;
	selp.f32 	%f303, %f894, %f892, %p92;
	selp.f32 	%f895, %f893, %f889, %p92;
	mov.f32 	%f896, 0f3FB8AA3B;
	mul.rn.f32 	%f897, %f895, %f896;
	cvt.rzi.f32.f32 	%f898, %f897;
	abs.f32 	%f899, %f898;
	setp.gt.f32 	%p93, %f899, 0f42FC0000;
	mov.b32 	%r367, %f898;
	and.b32  	%r368, %r367, -2147483648;
	or.b32  	%r369, %r368, 1123811328;
	mov.b32 	%f900, %r369;
	selp.f32 	%f901, %f900, %f898, %p93;
	mov.f32 	%f902, 0fBF317218;
	fma.rn.f32 	%f903, %f901, %f902, %f895;
	mov.f32 	%f904, 0f3102E308;
	fma.rn.f32 	%f905, %f901, %f904, %f903;
	mul.f32 	%f906, %f905, 0f3FB8AA3B;
	add.f32 	%f907, %f901, 0f4B40007F;
	mov.b32 	%r370, %f907;
	shl.b32 	%r371, %r370, 23;
	mov.b32 	%f908, %r371;
	ex2.approx.ftz.f32 	%f909, %f906;
	mul.f32 	%f304, %f909, %f908;
	setp.eq.f32 	%p94, %f304, 0f7F800000;
	mov.f32 	%f1627, 0f7F800000;
	@%p94 bra 	$L__BB0_75;

	fma.rn.f32 	%f1627, %f304, %f303, %f304;

$L__BB0_75:
	setp.lt.f32 	%p95, %f297, 0f00000000;
	setp.eq.f32 	%p96, %f301, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f297, 0f00000000;
	@%p97 bra 	$L__BB0_79;
	bra.uni 	$L__BB0_76;

$L__BB0_79:
	add.f32 	%f914, %f297, %f297;
	selp.f32 	%f1629, %f914, 0f00000000, %p96;
	bra.uni 	$L__BB0_80;

$L__BB0_76:
	mov.b32 	%r372, %f1627;
	xor.b32  	%r373, %r372, -2147483648;
	mov.b32 	%f910, %r373;
	selp.f32 	%f1629, %f910, %f1627, %p4;
	setp.geu.f32 	%p98, %f297, 0f00000000;
	@%p98 bra 	$L__BB0_80;

	mov.f32 	%f911, 0f3EE66666;
	cvt.rzi.f32.f32 	%f912, %f911;
	setp.eq.f32 	%p99, %f912, 0f3EE66666;
	@%p99 bra 	$L__BB0_80;

	mov.f32 	%f1629, 0f7FFFFFFF;

$L__BB0_80:
	add.f32 	%f915, %f302, 0f3EE66666;
	mov.b32 	%r374, %f915;
	setp.lt.s32 	%p101, %r374, 2139095040;
	@%p101 bra 	$L__BB0_85;

	setp.gtu.f32 	%p102, %f302, 0f7F800000;
	@%p102 bra 	$L__BB0_84;
	bra.uni 	$L__BB0_82;

$L__BB0_84:
	add.f32 	%f1629, %f297, 0f3EE66666;
	bra.uni 	$L__BB0_85;

$L__BB0_82:
	setp.neu.f32 	%p103, %f302, 0f7F800000;
	@%p103 bra 	$L__BB0_85;

	selp.f32 	%f1629, 0fFF800000, 0f7F800000, %p4;

$L__BB0_85:
	setp.eq.f32 	%p104, %f297, 0f3F800000;
	selp.f32 	%f313, 0f3F800000, %f1629, %p104;
	abs.f32 	%f314, %f298;
	setp.lt.f32 	%p105, %f314, 0f00800000;
	mul.f32 	%f917, %f314, 0f4B800000;
	selp.f32 	%f918, %f917, %f314, %p105;
	selp.f32 	%f919, 0fC3170000, 0fC2FE0000, %p105;
	mov.b32 	%r375, %f918;
	and.b32  	%r376, %r375, 8388607;
	or.b32  	%r377, %r376, 1065353216;
	mov.b32 	%f920, %r377;
	shr.u32 	%r378, %r375, 23;
	cvt.rn.f32.u32 	%f921, %r378;
	add.f32 	%f922, %f919, %f921;
	setp.gt.f32 	%p106, %f920, 0f3FB504F3;
	mul.f32 	%f923, %f920, 0f3F000000;
	add.f32 	%f924, %f922, 0f3F800000;
	selp.f32 	%f925, %f924, %f922, %p106;
	selp.f32 	%f926, %f923, %f920, %p106;
	add.f32 	%f927, %f926, 0fBF800000;
	add.f32 	%f928, %f926, 0f3F800000;
	rcp.approx.ftz.f32 	%f929, %f928;
	add.f32 	%f930, %f927, %f927;
	mul.f32 	%f931, %f930, %f929;
	mul.f32 	%f932, %f931, %f931;
	mov.f32 	%f933, 0f3C4CAF63;
	mov.f32 	%f934, 0f3B18F0FE;
	fma.rn.f32 	%f935, %f934, %f932, %f933;
	mov.f32 	%f936, 0f3DAAAABD;
	fma.rn.f32 	%f937, %f935, %f932, %f936;
	mul.rn.f32 	%f938, %f937, %f932;
	mul.rn.f32 	%f939, %f938, %f931;
	sub.f32 	%f940, %f927, %f931;
	add.f32 	%f941, %f940, %f940;
	neg.f32 	%f942, %f931;
	fma.rn.f32 	%f943, %f942, %f927, %f941;
	mul.rn.f32 	%f944, %f929, %f943;
	add.f32 	%f945, %f939, %f931;
	sub.f32 	%f946, %f931, %f945;
	add.f32 	%f947, %f939, %f946;
	add.f32 	%f948, %f944, %f947;
	add.f32 	%f949, %f945, %f948;
	sub.f32 	%f950, %f945, %f949;
	add.f32 	%f951, %f948, %f950;
	mov.f32 	%f952, 0f3F317200;
	mul.rn.f32 	%f953, %f925, %f952;
	mov.f32 	%f954, 0f35BFBE8E;
	mul.rn.f32 	%f955, %f925, %f954;
	add.f32 	%f956, %f953, %f949;
	sub.f32 	%f957, %f953, %f956;
	add.f32 	%f958, %f949, %f957;
	add.f32 	%f959, %f951, %f958;
	add.f32 	%f960, %f955, %f959;
	add.f32 	%f961, %f956, %f960;
	sub.f32 	%f962, %f956, %f961;
	add.f32 	%f963, %f960, %f962;
	mov.f32 	%f964, 0f3EE66666;
	mul.rn.f32 	%f965, %f964, %f961;
	neg.f32 	%f966, %f965;
	fma.rn.f32 	%f967, %f964, %f961, %f966;
	fma.rn.f32 	%f968, %f964, %f963, %f967;
	mov.f32 	%f969, 0f00000000;
	fma.rn.f32 	%f970, %f969, %f961, %f968;
	add.rn.f32 	%f971, %f965, %f970;
	neg.f32 	%f972, %f971;
	add.rn.f32 	%f973, %f965, %f972;
	add.rn.f32 	%f974, %f973, %f970;
	mov.b32 	%r379, %f971;
	setp.eq.s32 	%p107, %r379, 1118925336;
	add.s32 	%r380, %r379, -1;
	mov.b32 	%f975, %r380;
	add.f32 	%f976, %f974, 0f37000000;
	selp.f32 	%f315, %f976, %f974, %p107;
	selp.f32 	%f977, %f975, %f971, %p107;
	mov.f32 	%f978, 0f3FB8AA3B;
	mul.rn.f32 	%f979, %f977, %f978;
	cvt.rzi.f32.f32 	%f980, %f979;
	abs.f32 	%f981, %f980;
	setp.gt.f32 	%p108, %f981, 0f42FC0000;
	mov.b32 	%r381, %f980;
	and.b32  	%r382, %r381, -2147483648;
	or.b32  	%r383, %r382, 1123811328;
	mov.b32 	%f982, %r383;
	selp.f32 	%f983, %f982, %f980, %p108;
	mov.f32 	%f984, 0fBF317218;
	fma.rn.f32 	%f985, %f983, %f984, %f977;
	mov.f32 	%f986, 0f3102E308;
	fma.rn.f32 	%f987, %f983, %f986, %f985;
	mul.f32 	%f988, %f987, 0f3FB8AA3B;
	add.f32 	%f989, %f983, 0f4B40007F;
	mov.b32 	%r384, %f989;
	shl.b32 	%r385, %r384, 23;
	mov.b32 	%f990, %r385;
	ex2.approx.ftz.f32 	%f991, %f988;
	mul.f32 	%f316, %f991, %f990;
	setp.eq.f32 	%p109, %f316, 0f7F800000;
	mov.f32 	%f1630, 0f7F800000;
	@%p109 bra 	$L__BB0_87;

	fma.rn.f32 	%f1630, %f316, %f315, %f316;

$L__BB0_87:
	setp.lt.f32 	%p110, %f298, 0f00000000;
	and.pred  	%p5, %p110, %p96;
	setp.eq.f32 	%p112, %f298, 0f00000000;
	@%p112 bra 	$L__BB0_91;
	bra.uni 	$L__BB0_88;

$L__BB0_91:
	add.f32 	%f996, %f298, %f298;
	selp.f32 	%f1632, %f996, 0f00000000, %p96;
	bra.uni 	$L__BB0_92;

$L__BB0_88:
	mov.b32 	%r386, %f1630;
	xor.b32  	%r387, %r386, -2147483648;
	mov.b32 	%f992, %r387;
	selp.f32 	%f1632, %f992, %f1630, %p5;
	setp.geu.f32 	%p113, %f298, 0f00000000;
	@%p113 bra 	$L__BB0_92;

	mov.f32 	%f993, 0f3EE66666;
	cvt.rzi.f32.f32 	%f994, %f993;
	setp.eq.f32 	%p114, %f994, 0f3EE66666;
	@%p114 bra 	$L__BB0_92;

	mov.f32 	%f1632, 0f7FFFFFFF;

$L__BB0_92:
	add.f32 	%f997, %f314, 0f3EE66666;
	mov.b32 	%r388, %f997;
	setp.lt.s32 	%p116, %r388, 2139095040;
	@%p116 bra 	$L__BB0_97;

	setp.gtu.f32 	%p117, %f314, 0f7F800000;
	@%p117 bra 	$L__BB0_96;
	bra.uni 	$L__BB0_94;

$L__BB0_96:
	add.f32 	%f1632, %f298, 0f3EE66666;
	bra.uni 	$L__BB0_97;

$L__BB0_94:
	setp.neu.f32 	%p118, %f314, 0f7F800000;
	@%p118 bra 	$L__BB0_97;

	selp.f32 	%f1632, 0fFF800000, 0f7F800000, %p5;

$L__BB0_97:
	setp.eq.f32 	%p119, %f298, 0f3F800000;
	selp.f32 	%f325, 0f3F800000, %f1632, %p119;
	abs.f32 	%f326, %f300;
	setp.lt.f32 	%p120, %f326, 0f00800000;
	mul.f32 	%f999, %f326, 0f4B800000;
	selp.f32 	%f1000, %f999, %f326, %p120;
	selp.f32 	%f1001, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r389, %f1000;
	and.b32  	%r390, %r389, 8388607;
	or.b32  	%r391, %r390, 1065353216;
	mov.b32 	%f1002, %r391;
	shr.u32 	%r392, %r389, 23;
	cvt.rn.f32.u32 	%f1003, %r392;
	add.f32 	%f1004, %f1001, %f1003;
	setp.gt.f32 	%p121, %f1002, 0f3FB504F3;
	mul.f32 	%f1005, %f1002, 0f3F000000;
	add.f32 	%f1006, %f1004, 0f3F800000;
	selp.f32 	%f1007, %f1006, %f1004, %p121;
	selp.f32 	%f1008, %f1005, %f1002, %p121;
	add.f32 	%f1009, %f1008, 0fBF800000;
	add.f32 	%f1010, %f1008, 0f3F800000;
	rcp.approx.ftz.f32 	%f1011, %f1010;
	add.f32 	%f1012, %f1009, %f1009;
	mul.f32 	%f1013, %f1012, %f1011;
	mul.f32 	%f1014, %f1013, %f1013;
	mov.f32 	%f1015, 0f3C4CAF63;
	mov.f32 	%f1016, 0f3B18F0FE;
	fma.rn.f32 	%f1017, %f1016, %f1014, %f1015;
	mov.f32 	%f1018, 0f3DAAAABD;
	fma.rn.f32 	%f1019, %f1017, %f1014, %f1018;
	mul.rn.f32 	%f1020, %f1019, %f1014;
	mul.rn.f32 	%f1021, %f1020, %f1013;
	sub.f32 	%f1022, %f1009, %f1013;
	add.f32 	%f1023, %f1022, %f1022;
	neg.f32 	%f1024, %f1013;
	fma.rn.f32 	%f1025, %f1024, %f1009, %f1023;
	mul.rn.f32 	%f1026, %f1011, %f1025;
	add.f32 	%f1027, %f1021, %f1013;
	sub.f32 	%f1028, %f1013, %f1027;
	add.f32 	%f1029, %f1021, %f1028;
	add.f32 	%f1030, %f1026, %f1029;
	add.f32 	%f1031, %f1027, %f1030;
	sub.f32 	%f1032, %f1027, %f1031;
	add.f32 	%f1033, %f1030, %f1032;
	mov.f32 	%f1034, 0f3F317200;
	mul.rn.f32 	%f1035, %f1007, %f1034;
	mov.f32 	%f1036, 0f35BFBE8E;
	mul.rn.f32 	%f1037, %f1007, %f1036;
	add.f32 	%f1038, %f1035, %f1031;
	sub.f32 	%f1039, %f1035, %f1038;
	add.f32 	%f1040, %f1031, %f1039;
	add.f32 	%f1041, %f1033, %f1040;
	add.f32 	%f1042, %f1037, %f1041;
	add.f32 	%f1043, %f1038, %f1042;
	sub.f32 	%f1044, %f1038, %f1043;
	add.f32 	%f1045, %f1042, %f1044;
	mov.f32 	%f1046, 0f3EE66666;
	mul.rn.f32 	%f1047, %f1046, %f1043;
	neg.f32 	%f1048, %f1047;
	fma.rn.f32 	%f1049, %f1046, %f1043, %f1048;
	fma.rn.f32 	%f1050, %f1046, %f1045, %f1049;
	mov.f32 	%f1051, 0f00000000;
	fma.rn.f32 	%f1052, %f1051, %f1043, %f1050;
	add.rn.f32 	%f1053, %f1047, %f1052;
	neg.f32 	%f1054, %f1053;
	add.rn.f32 	%f1055, %f1047, %f1054;
	add.rn.f32 	%f1056, %f1055, %f1052;
	mov.b32 	%r393, %f1053;
	setp.eq.s32 	%p122, %r393, 1118925336;
	add.s32 	%r394, %r393, -1;
	mov.b32 	%f1057, %r394;
	add.f32 	%f1058, %f1056, 0f37000000;
	selp.f32 	%f327, %f1058, %f1056, %p122;
	selp.f32 	%f1059, %f1057, %f1053, %p122;
	mov.f32 	%f1060, 0f3FB8AA3B;
	mul.rn.f32 	%f1061, %f1059, %f1060;
	cvt.rzi.f32.f32 	%f1062, %f1061;
	abs.f32 	%f1063, %f1062;
	setp.gt.f32 	%p123, %f1063, 0f42FC0000;
	mov.b32 	%r395, %f1062;
	and.b32  	%r396, %r395, -2147483648;
	or.b32  	%r397, %r396, 1123811328;
	mov.b32 	%f1064, %r397;
	selp.f32 	%f1065, %f1064, %f1062, %p123;
	mov.f32 	%f1066, 0fBF317218;
	fma.rn.f32 	%f1067, %f1065, %f1066, %f1059;
	mov.f32 	%f1068, 0f3102E308;
	fma.rn.f32 	%f1069, %f1065, %f1068, %f1067;
	mul.f32 	%f1070, %f1069, 0f3FB8AA3B;
	add.f32 	%f1071, %f1065, 0f4B40007F;
	mov.b32 	%r398, %f1071;
	shl.b32 	%r399, %r398, 23;
	mov.b32 	%f1072, %r399;
	ex2.approx.ftz.f32 	%f1073, %f1070;
	mul.f32 	%f328, %f1073, %f1072;
	setp.eq.f32 	%p124, %f328, 0f7F800000;
	mov.f32 	%f1633, 0f7F800000;
	@%p124 bra 	$L__BB0_99;

	fma.rn.f32 	%f1633, %f328, %f327, %f328;

$L__BB0_99:
	setp.lt.f32 	%p125, %f300, 0f00000000;
	and.pred  	%p6, %p125, %p96;
	setp.eq.f32 	%p127, %f300, 0f00000000;
	@%p127 bra 	$L__BB0_103;
	bra.uni 	$L__BB0_100;

$L__BB0_103:
	add.f32 	%f1078, %f300, %f300;
	selp.f32 	%f1635, %f1078, 0f00000000, %p96;
	bra.uni 	$L__BB0_104;

$L__BB0_100:
	mov.b32 	%r400, %f1633;
	xor.b32  	%r401, %r400, -2147483648;
	mov.b32 	%f1074, %r401;
	selp.f32 	%f1635, %f1074, %f1633, %p6;
	setp.geu.f32 	%p128, %f300, 0f00000000;
	@%p128 bra 	$L__BB0_104;

	mov.f32 	%f1075, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1076, %f1075;
	setp.eq.f32 	%p129, %f1076, 0f3EE66666;
	@%p129 bra 	$L__BB0_104;

	mov.f32 	%f1635, 0f7FFFFFFF;

$L__BB0_104:
	add.f32 	%f1079, %f326, 0f3EE66666;
	mov.b32 	%r402, %f1079;
	setp.lt.s32 	%p131, %r402, 2139095040;
	@%p131 bra 	$L__BB0_109;

	setp.gtu.f32 	%p132, %f326, 0f7F800000;
	@%p132 bra 	$L__BB0_108;
	bra.uni 	$L__BB0_106;

$L__BB0_108:
	add.f32 	%f1635, %f300, 0f3EE66666;
	bra.uni 	$L__BB0_109;

$L__BB0_106:
	setp.neu.f32 	%p133, %f326, 0f7F800000;
	@%p133 bra 	$L__BB0_109;

	selp.f32 	%f1635, 0fFF800000, 0f7F800000, %p6;

$L__BB0_109:
	setp.eq.f32 	%p134, %f300, 0f3F800000;
	mov.f32 	%f1081, 0f3F800000;
	selp.f32 	%f1082, 0f3F800000, %f1635, %p134;
	ld.const.u64 	%rd79, [params+144];
	cvta.to.global.u64 	%rd21, %rd79;
	ld.const.u32 	%r403, [params+136];
	mad.lo.s32 	%r404, %r403, %r6, %r5;
	cvt.u64.u32 	%rd22, %r404;
	min.f32 	%f1083, %f313, %f1081;
	mov.f32 	%f1084, 0f00000000;
	max.f32 	%f337, %f1084, %f1083;
	min.f32 	%f1085, %f325, %f1081;
	max.f32 	%f338, %f1084, %f1085;
	min.f32 	%f1086, %f1082, %f1081;
	max.f32 	%f339, %f1084, %f1086;
	mov.f32 	%f1087, 0f3E555555;
	cvt.rzi.f32.f32 	%f1088, %f1087;
	add.f32 	%f1089, %f1088, %f1088;
	mov.f32 	%f1090, 0f3ED55555;
	sub.f32 	%f1091, %f1090, %f1089;
	abs.f32 	%f340, %f1091;
	abs.f32 	%f341, %f337;
	setp.lt.f32 	%p135, %f341, 0f00800000;
	mul.f32 	%f1092, %f341, 0f4B800000;
	selp.f32 	%f1093, %f1092, %f341, %p135;
	selp.f32 	%f1094, 0fC3170000, 0fC2FE0000, %p135;
	mov.b32 	%r405, %f1093;
	and.b32  	%r406, %r405, 8388607;
	or.b32  	%r407, %r406, 1065353216;
	mov.b32 	%f1095, %r407;
	shr.u32 	%r408, %r405, 23;
	cvt.rn.f32.u32 	%f1096, %r408;
	add.f32 	%f1097, %f1094, %f1096;
	setp.gt.f32 	%p136, %f1095, 0f3FB504F3;
	mul.f32 	%f1098, %f1095, 0f3F000000;
	add.f32 	%f1099, %f1097, 0f3F800000;
	selp.f32 	%f1100, %f1099, %f1097, %p136;
	selp.f32 	%f1101, %f1098, %f1095, %p136;
	add.f32 	%f1102, %f1101, 0fBF800000;
	add.f32 	%f1103, %f1101, 0f3F800000;
	rcp.approx.ftz.f32 	%f1104, %f1103;
	add.f32 	%f1105, %f1102, %f1102;
	mul.f32 	%f1106, %f1105, %f1104;
	mul.f32 	%f1107, %f1106, %f1106;
	mov.f32 	%f1108, 0f3C4CAF63;
	mov.f32 	%f1109, 0f3B18F0FE;
	fma.rn.f32 	%f1110, %f1109, %f1107, %f1108;
	mov.f32 	%f1111, 0f3DAAAABD;
	fma.rn.f32 	%f1112, %f1110, %f1107, %f1111;
	mul.rn.f32 	%f1113, %f1112, %f1107;
	mul.rn.f32 	%f1114, %f1113, %f1106;
	sub.f32 	%f1115, %f1102, %f1106;
	add.f32 	%f1116, %f1115, %f1115;
	neg.f32 	%f1117, %f1106;
	fma.rn.f32 	%f1118, %f1117, %f1102, %f1116;
	mul.rn.f32 	%f1119, %f1104, %f1118;
	add.f32 	%f1120, %f1114, %f1106;
	sub.f32 	%f1121, %f1106, %f1120;
	add.f32 	%f1122, %f1114, %f1121;
	add.f32 	%f1123, %f1119, %f1122;
	add.f32 	%f1124, %f1120, %f1123;
	sub.f32 	%f1125, %f1120, %f1124;
	add.f32 	%f1126, %f1123, %f1125;
	mov.f32 	%f1127, 0f3F317200;
	mul.rn.f32 	%f1128, %f1100, %f1127;
	mov.f32 	%f1129, 0f35BFBE8E;
	mul.rn.f32 	%f1130, %f1100, %f1129;
	add.f32 	%f1131, %f1128, %f1124;
	sub.f32 	%f1132, %f1128, %f1131;
	add.f32 	%f1133, %f1124, %f1132;
	add.f32 	%f1134, %f1126, %f1133;
	add.f32 	%f1135, %f1130, %f1134;
	add.f32 	%f1136, %f1131, %f1135;
	sub.f32 	%f1137, %f1131, %f1136;
	add.f32 	%f1138, %f1135, %f1137;
	mul.rn.f32 	%f1139, %f1090, %f1136;
	neg.f32 	%f1140, %f1139;
	fma.rn.f32 	%f1141, %f1090, %f1136, %f1140;
	fma.rn.f32 	%f1142, %f1090, %f1138, %f1141;
	fma.rn.f32 	%f1143, %f1084, %f1136, %f1142;
	add.rn.f32 	%f1144, %f1139, %f1143;
	neg.f32 	%f1145, %f1144;
	add.rn.f32 	%f1146, %f1139, %f1145;
	add.rn.f32 	%f1147, %f1146, %f1143;
	mov.b32 	%r409, %f1144;
	setp.eq.s32 	%p137, %r409, 1118925336;
	add.s32 	%r410, %r409, -1;
	mov.b32 	%f1148, %r410;
	add.f32 	%f1149, %f1147, 0f37000000;
	selp.f32 	%f342, %f1149, %f1147, %p137;
	selp.f32 	%f1150, %f1148, %f1144, %p137;
	mov.f32 	%f1151, 0f3FB8AA3B;
	mul.rn.f32 	%f1152, %f1150, %f1151;
	cvt.rzi.f32.f32 	%f1153, %f1152;
	abs.f32 	%f1154, %f1153;
	setp.gt.f32 	%p138, %f1154, 0f42FC0000;
	mov.b32 	%r411, %f1153;
	and.b32  	%r412, %r411, -2147483648;
	or.b32  	%r413, %r412, 1123811328;
	mov.b32 	%f1155, %r413;
	selp.f32 	%f1156, %f1155, %f1153, %p138;
	mov.f32 	%f1157, 0fBF317218;
	fma.rn.f32 	%f1158, %f1156, %f1157, %f1150;
	mov.f32 	%f1159, 0f3102E308;
	fma.rn.f32 	%f1160, %f1156, %f1159, %f1158;
	mul.f32 	%f1161, %f1160, 0f3FB8AA3B;
	add.f32 	%f1162, %f1156, 0f4B40007F;
	mov.b32 	%r414, %f1162;
	shl.b32 	%r415, %r414, 23;
	mov.b32 	%f1163, %r415;
	ex2.approx.ftz.f32 	%f1164, %f1161;
	mul.f32 	%f343, %f1164, %f1163;
	setp.eq.f32 	%p139, %f343, 0f7F800000;
	mov.f32 	%f1636, 0f7F800000;
	@%p139 bra 	$L__BB0_111;

	fma.rn.f32 	%f1636, %f343, %f342, %f343;

$L__BB0_111:
	setp.lt.f32 	%p140, %f337, 0f00000000;
	setp.eq.f32 	%p141, %f340, 0f3F800000;
	and.pred  	%p7, %p140, %p141;
	setp.eq.f32 	%p142, %f337, 0f00000000;
	@%p142 bra 	$L__BB0_115;
	bra.uni 	$L__BB0_112;

$L__BB0_115:
	add.f32 	%f1169, %f337, %f337;
	selp.f32 	%f1638, %f1169, 0f00000000, %p141;
	bra.uni 	$L__BB0_116;

$L__BB0_112:
	mov.b32 	%r416, %f1636;
	xor.b32  	%r417, %r416, -2147483648;
	mov.b32 	%f1165, %r417;
	selp.f32 	%f1638, %f1165, %f1636, %p7;
	setp.geu.f32 	%p143, %f337, 0f00000000;
	@%p143 bra 	$L__BB0_116;

	mov.f32 	%f1166, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1167, %f1166;
	setp.eq.f32 	%p144, %f1167, 0f3ED55555;
	@%p144 bra 	$L__BB0_116;

	mov.f32 	%f1638, 0f7FFFFFFF;

$L__BB0_116:
	add.f32 	%f1170, %f341, 0f3ED55555;
	mov.b32 	%r418, %f1170;
	setp.lt.s32 	%p146, %r418, 2139095040;
	@%p146 bra 	$L__BB0_121;

	setp.gtu.f32 	%p147, %f341, 0f7F800000;
	@%p147 bra 	$L__BB0_120;
	bra.uni 	$L__BB0_118;

$L__BB0_120:
	add.f32 	%f1638, %f337, 0f3ED55555;
	bra.uni 	$L__BB0_121;

$L__BB0_118:
	setp.neu.f32 	%p148, %f341, 0f7F800000;
	@%p148 bra 	$L__BB0_121;

	selp.f32 	%f1638, 0fFF800000, 0f7F800000, %p7;

$L__BB0_121:
	abs.f32 	%f352, %f338;
	setp.lt.f32 	%p149, %f352, 0f00800000;
	mul.f32 	%f1172, %f352, 0f4B800000;
	selp.f32 	%f1173, %f1172, %f352, %p149;
	selp.f32 	%f1174, 0fC3170000, 0fC2FE0000, %p149;
	mov.b32 	%r419, %f1173;
	and.b32  	%r420, %r419, 8388607;
	or.b32  	%r421, %r420, 1065353216;
	mov.b32 	%f1175, %r421;
	shr.u32 	%r422, %r419, 23;
	cvt.rn.f32.u32 	%f1176, %r422;
	add.f32 	%f1177, %f1174, %f1176;
	setp.gt.f32 	%p150, %f1175, 0f3FB504F3;
	mul.f32 	%f1178, %f1175, 0f3F000000;
	add.f32 	%f1179, %f1177, 0f3F800000;
	selp.f32 	%f1180, %f1179, %f1177, %p150;
	selp.f32 	%f1181, %f1178, %f1175, %p150;
	add.f32 	%f1182, %f1181, 0fBF800000;
	add.f32 	%f1183, %f1181, 0f3F800000;
	rcp.approx.ftz.f32 	%f1184, %f1183;
	add.f32 	%f1185, %f1182, %f1182;
	mul.f32 	%f1186, %f1185, %f1184;
	mul.f32 	%f1187, %f1186, %f1186;
	mov.f32 	%f1188, 0f3C4CAF63;
	mov.f32 	%f1189, 0f3B18F0FE;
	fma.rn.f32 	%f1190, %f1189, %f1187, %f1188;
	mov.f32 	%f1191, 0f3DAAAABD;
	fma.rn.f32 	%f1192, %f1190, %f1187, %f1191;
	mul.rn.f32 	%f1193, %f1192, %f1187;
	mul.rn.f32 	%f1194, %f1193, %f1186;
	sub.f32 	%f1195, %f1182, %f1186;
	add.f32 	%f1196, %f1195, %f1195;
	neg.f32 	%f1197, %f1186;
	fma.rn.f32 	%f1198, %f1197, %f1182, %f1196;
	mul.rn.f32 	%f1199, %f1184, %f1198;
	add.f32 	%f1200, %f1194, %f1186;
	sub.f32 	%f1201, %f1186, %f1200;
	add.f32 	%f1202, %f1194, %f1201;
	add.f32 	%f1203, %f1199, %f1202;
	add.f32 	%f1204, %f1200, %f1203;
	sub.f32 	%f1205, %f1200, %f1204;
	add.f32 	%f1206, %f1203, %f1205;
	mov.f32 	%f1207, 0f3F317200;
	mul.rn.f32 	%f1208, %f1180, %f1207;
	mov.f32 	%f1209, 0f35BFBE8E;
	mul.rn.f32 	%f1210, %f1180, %f1209;
	add.f32 	%f1211, %f1208, %f1204;
	sub.f32 	%f1212, %f1208, %f1211;
	add.f32 	%f1213, %f1204, %f1212;
	add.f32 	%f1214, %f1206, %f1213;
	add.f32 	%f1215, %f1210, %f1214;
	add.f32 	%f1216, %f1211, %f1215;
	sub.f32 	%f1217, %f1211, %f1216;
	add.f32 	%f1218, %f1215, %f1217;
	mov.f32 	%f1219, 0f3ED55555;
	mul.rn.f32 	%f1220, %f1219, %f1216;
	neg.f32 	%f1221, %f1220;
	fma.rn.f32 	%f1222, %f1219, %f1216, %f1221;
	fma.rn.f32 	%f1223, %f1219, %f1218, %f1222;
	mov.f32 	%f1224, 0f00000000;
	fma.rn.f32 	%f1225, %f1224, %f1216, %f1223;
	add.rn.f32 	%f1226, %f1220, %f1225;
	neg.f32 	%f1227, %f1226;
	add.rn.f32 	%f1228, %f1220, %f1227;
	add.rn.f32 	%f1229, %f1228, %f1225;
	mov.b32 	%r423, %f1226;
	setp.eq.s32 	%p151, %r423, 1118925336;
	add.s32 	%r424, %r423, -1;
	mov.b32 	%f1230, %r424;
	add.f32 	%f1231, %f1229, 0f37000000;
	selp.f32 	%f353, %f1231, %f1229, %p151;
	selp.f32 	%f1232, %f1230, %f1226, %p151;
	mov.f32 	%f1233, 0f3FB8AA3B;
	mul.rn.f32 	%f1234, %f1232, %f1233;
	cvt.rzi.f32.f32 	%f1235, %f1234;
	abs.f32 	%f1236, %f1235;
	setp.gt.f32 	%p152, %f1236, 0f42FC0000;
	mov.b32 	%r425, %f1235;
	and.b32  	%r426, %r425, -2147483648;
	or.b32  	%r427, %r426, 1123811328;
	mov.b32 	%f1237, %r427;
	selp.f32 	%f1238, %f1237, %f1235, %p152;
	mov.f32 	%f1239, 0fBF317218;
	fma.rn.f32 	%f1240, %f1238, %f1239, %f1232;
	mov.f32 	%f1241, 0f3102E308;
	fma.rn.f32 	%f1242, %f1238, %f1241, %f1240;
	mul.f32 	%f1243, %f1242, 0f3FB8AA3B;
	add.f32 	%f1244, %f1238, 0f4B40007F;
	mov.b32 	%r428, %f1244;
	shl.b32 	%r429, %r428, 23;
	mov.b32 	%f1245, %r429;
	ex2.approx.ftz.f32 	%f1246, %f1243;
	mul.f32 	%f354, %f1246, %f1245;
	setp.eq.f32 	%p153, %f354, 0f7F800000;
	mov.f32 	%f1639, 0f7F800000;
	@%p153 bra 	$L__BB0_123;

	fma.rn.f32 	%f1639, %f354, %f353, %f354;

$L__BB0_123:
	setp.lt.f32 	%p154, %f338, 0f00000000;
	and.pred  	%p8, %p154, %p141;
	setp.eq.f32 	%p156, %f338, 0f00000000;
	@%p156 bra 	$L__BB0_127;
	bra.uni 	$L__BB0_124;

$L__BB0_127:
	add.f32 	%f1251, %f338, %f338;
	selp.f32 	%f1641, %f1251, 0f00000000, %p141;
	bra.uni 	$L__BB0_128;

$L__BB0_124:
	mov.b32 	%r430, %f1639;
	xor.b32  	%r431, %r430, -2147483648;
	mov.b32 	%f1247, %r431;
	selp.f32 	%f1641, %f1247, %f1639, %p8;
	setp.geu.f32 	%p157, %f338, 0f00000000;
	@%p157 bra 	$L__BB0_128;

	mov.f32 	%f1248, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1249, %f1248;
	setp.eq.f32 	%p158, %f1249, 0f3ED55555;
	@%p158 bra 	$L__BB0_128;

	mov.f32 	%f1641, 0f7FFFFFFF;

$L__BB0_128:
	add.f32 	%f1252, %f352, 0f3ED55555;
	mov.b32 	%r432, %f1252;
	setp.lt.s32 	%p160, %r432, 2139095040;
	@%p160 bra 	$L__BB0_133;

	setp.gtu.f32 	%p161, %f352, 0f7F800000;
	@%p161 bra 	$L__BB0_132;
	bra.uni 	$L__BB0_130;

$L__BB0_132:
	add.f32 	%f1641, %f338, 0f3ED55555;
	bra.uni 	$L__BB0_133;

$L__BB0_130:
	setp.neu.f32 	%p162, %f352, 0f7F800000;
	@%p162 bra 	$L__BB0_133;

	selp.f32 	%f1641, 0fFF800000, 0f7F800000, %p8;

$L__BB0_133:
	abs.f32 	%f363, %f339;
	setp.lt.f32 	%p163, %f363, 0f00800000;
	mul.f32 	%f1254, %f363, 0f4B800000;
	selp.f32 	%f1255, %f1254, %f363, %p163;
	selp.f32 	%f1256, 0fC3170000, 0fC2FE0000, %p163;
	mov.b32 	%r433, %f1255;
	and.b32  	%r434, %r433, 8388607;
	or.b32  	%r435, %r434, 1065353216;
	mov.b32 	%f1257, %r435;
	shr.u32 	%r436, %r433, 23;
	cvt.rn.f32.u32 	%f1258, %r436;
	add.f32 	%f1259, %f1256, %f1258;
	setp.gt.f32 	%p164, %f1257, 0f3FB504F3;
	mul.f32 	%f1260, %f1257, 0f3F000000;
	add.f32 	%f1261, %f1259, 0f3F800000;
	selp.f32 	%f1262, %f1261, %f1259, %p164;
	selp.f32 	%f1263, %f1260, %f1257, %p164;
	add.f32 	%f1264, %f1263, 0fBF800000;
	add.f32 	%f1265, %f1263, 0f3F800000;
	rcp.approx.ftz.f32 	%f1266, %f1265;
	add.f32 	%f1267, %f1264, %f1264;
	mul.f32 	%f1268, %f1267, %f1266;
	mul.f32 	%f1269, %f1268, %f1268;
	mov.f32 	%f1270, 0f3C4CAF63;
	mov.f32 	%f1271, 0f3B18F0FE;
	fma.rn.f32 	%f1272, %f1271, %f1269, %f1270;
	mov.f32 	%f1273, 0f3DAAAABD;
	fma.rn.f32 	%f1274, %f1272, %f1269, %f1273;
	mul.rn.f32 	%f1275, %f1274, %f1269;
	mul.rn.f32 	%f1276, %f1275, %f1268;
	sub.f32 	%f1277, %f1264, %f1268;
	add.f32 	%f1278, %f1277, %f1277;
	neg.f32 	%f1279, %f1268;
	fma.rn.f32 	%f1280, %f1279, %f1264, %f1278;
	mul.rn.f32 	%f1281, %f1266, %f1280;
	add.f32 	%f1282, %f1276, %f1268;
	sub.f32 	%f1283, %f1268, %f1282;
	add.f32 	%f1284, %f1276, %f1283;
	add.f32 	%f1285, %f1281, %f1284;
	add.f32 	%f1286, %f1282, %f1285;
	sub.f32 	%f1287, %f1282, %f1286;
	add.f32 	%f1288, %f1285, %f1287;
	mov.f32 	%f1289, 0f3F317200;
	mul.rn.f32 	%f1290, %f1262, %f1289;
	mov.f32 	%f1291, 0f35BFBE8E;
	mul.rn.f32 	%f1292, %f1262, %f1291;
	add.f32 	%f1293, %f1290, %f1286;
	sub.f32 	%f1294, %f1290, %f1293;
	add.f32 	%f1295, %f1286, %f1294;
	add.f32 	%f1296, %f1288, %f1295;
	add.f32 	%f1297, %f1292, %f1296;
	add.f32 	%f1298, %f1293, %f1297;
	sub.f32 	%f1299, %f1293, %f1298;
	add.f32 	%f1300, %f1297, %f1299;
	mov.f32 	%f1301, 0f3ED55555;
	mul.rn.f32 	%f1302, %f1301, %f1298;
	neg.f32 	%f1303, %f1302;
	fma.rn.f32 	%f1304, %f1301, %f1298, %f1303;
	fma.rn.f32 	%f1305, %f1301, %f1300, %f1304;
	mov.f32 	%f1306, 0f00000000;
	fma.rn.f32 	%f1307, %f1306, %f1298, %f1305;
	add.rn.f32 	%f1308, %f1302, %f1307;
	neg.f32 	%f1309, %f1308;
	add.rn.f32 	%f1310, %f1302, %f1309;
	add.rn.f32 	%f1311, %f1310, %f1307;
	mov.b32 	%r437, %f1308;
	setp.eq.s32 	%p165, %r437, 1118925336;
	add.s32 	%r438, %r437, -1;
	mov.b32 	%f1312, %r438;
	add.f32 	%f1313, %f1311, 0f37000000;
	selp.f32 	%f364, %f1313, %f1311, %p165;
	selp.f32 	%f1314, %f1312, %f1308, %p165;
	mov.f32 	%f1315, 0f3FB8AA3B;
	mul.rn.f32 	%f1316, %f1314, %f1315;
	cvt.rzi.f32.f32 	%f1317, %f1316;
	abs.f32 	%f1318, %f1317;
	setp.gt.f32 	%p166, %f1318, 0f42FC0000;
	mov.b32 	%r439, %f1317;
	and.b32  	%r440, %r439, -2147483648;
	or.b32  	%r441, %r440, 1123811328;
	mov.b32 	%f1319, %r441;
	selp.f32 	%f1320, %f1319, %f1317, %p166;
	mov.f32 	%f1321, 0fBF317218;
	fma.rn.f32 	%f1322, %f1320, %f1321, %f1314;
	mov.f32 	%f1323, 0f3102E308;
	fma.rn.f32 	%f1324, %f1320, %f1323, %f1322;
	mul.f32 	%f1325, %f1324, 0f3FB8AA3B;
	add.f32 	%f1326, %f1320, 0f4B40007F;
	mov.b32 	%r442, %f1326;
	shl.b32 	%r443, %r442, 23;
	mov.b32 	%f1327, %r443;
	ex2.approx.ftz.f32 	%f1328, %f1325;
	mul.f32 	%f365, %f1328, %f1327;
	setp.eq.f32 	%p167, %f365, 0f7F800000;
	mov.f32 	%f1642, 0f7F800000;
	@%p167 bra 	$L__BB0_135;

	fma.rn.f32 	%f1642, %f365, %f364, %f365;

$L__BB0_135:
	setp.lt.f32 	%p168, %f339, 0f00000000;
	and.pred  	%p9, %p168, %p141;
	setp.eq.f32 	%p170, %f339, 0f00000000;
	@%p170 bra 	$L__BB0_139;
	bra.uni 	$L__BB0_136;

$L__BB0_139:
	add.f32 	%f1333, %f339, %f339;
	selp.f32 	%f1644, %f1333, 0f00000000, %p141;
	bra.uni 	$L__BB0_140;

$L__BB0_136:
	mov.b32 	%r444, %f1642;
	xor.b32  	%r445, %r444, -2147483648;
	mov.b32 	%f1329, %r445;
	selp.f32 	%f1644, %f1329, %f1642, %p9;
	setp.geu.f32 	%p171, %f339, 0f00000000;
	@%p171 bra 	$L__BB0_140;

	mov.f32 	%f1330, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1331, %f1330;
	setp.eq.f32 	%p172, %f1331, 0f3ED55555;
	@%p172 bra 	$L__BB0_140;

	mov.f32 	%f1644, 0f7FFFFFFF;

$L__BB0_140:
	add.f32 	%f1334, %f363, 0f3ED55555;
	mov.b32 	%r446, %f1334;
	setp.lt.s32 	%p174, %r446, 2139095040;
	@%p174 bra 	$L__BB0_145;

	setp.gtu.f32 	%p175, %f363, 0f7F800000;
	@%p175 bra 	$L__BB0_144;
	bra.uni 	$L__BB0_142;

$L__BB0_144:
	add.f32 	%f1644, %f339, 0f3ED55555;
	bra.uni 	$L__BB0_145;

$L__BB0_142:
	setp.neu.f32 	%p176, %f363, 0f7F800000;
	@%p176 bra 	$L__BB0_145;

	selp.f32 	%f1644, 0fFF800000, 0f7F800000, %p9;

$L__BB0_145:
	fma.rn.f32 	%f1335, %f1638, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p177, %f337, 0f3F800000;
	mov.f32 	%f1336, 0f3F800000;
	selp.f32 	%f1337, 0f3F7FFFFF, %f1335, %p177;
	mul.f32 	%f1338, %f337, 0f414EB852;
	setp.lt.f32 	%p178, %f337, 0f3B4D2E1C;
	selp.f32 	%f1339, %f1338, %f1337, %p178;
	fma.rn.f32 	%f1340, %f1641, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p179, %f338, 0f3F800000;
	selp.f32 	%f1341, 0f3F7FFFFF, %f1340, %p179;
	mul.f32 	%f1342, %f338, 0f414EB852;
	setp.lt.f32 	%p180, %f338, 0f3B4D2E1C;
	selp.f32 	%f1343, %f1342, %f1341, %p180;
	fma.rn.f32 	%f1344, %f1644, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p181, %f339, 0f3F800000;
	selp.f32 	%f1345, 0f3F7FFFFF, %f1344, %p181;
	mul.f32 	%f1346, %f339, 0f414EB852;
	setp.lt.f32 	%p182, %f339, 0f3B4D2E1C;
	selp.f32 	%f1347, %f1346, %f1345, %p182;
	min.f32 	%f1348, %f1339, %f1336;
	mov.f32 	%f1349, 0f00000000;
	max.f32 	%f1350, %f1349, %f1348;
	mul.f32 	%f1351, %f1350, 0f43800000;
	cvt.rzi.u32.f32 	%r447, %f1351;
	min.u32 	%r448, %r447, 255;
	min.f32 	%f1352, %f1343, %f1336;
	max.f32 	%f1353, %f1349, %f1352;
	mul.f32 	%f1354, %f1353, 0f43800000;
	cvt.rzi.u32.f32 	%r449, %f1354;
	min.u32 	%r450, %r449, 255;
	min.f32 	%f1355, %f1347, %f1336;
	max.f32 	%f1356, %f1349, %f1355;
	mul.f32 	%f1357, %f1356, 0f43800000;
	cvt.rzi.u32.f32 	%r451, %f1357;
	min.u32 	%r452, %r451, 255;
	shl.b64 	%rd80, %rd22, 2;
	add.s64 	%rd81, %rd21, %rd80;
	cvt.u16.u32 	%rs18, %r452;
	cvt.u16.u32 	%rs19, %r450;
	cvt.u16.u32 	%rs20, %r448;
	mov.u16 	%rs21, 255;
	st.global.v4.u8 	[%rd81], {%rs20, %rs19, %rs18, %rs21};

$L__BB0_146:
	and.b32  	%r453, %r87, 4;
	setp.eq.s32 	%p183, %r453, 0;
	ld.const.u32 	%r501, [params+108];
	@%p183 bra 	$L__BB0_150;

	setp.eq.s32 	%p184, %r501, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r454, [params+216];
	mad.lo.s32 	%r455, %r454, %r6, %r5;
	mul.wide.u32 	%rd84, %r455, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p184 bra 	$L__BB0_149;

	ld.global.v4.u16 	{%rs29, %rs30, %rs31, %rs32}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1358, %rs29;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1359, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1360, %rs31;}

	// end inline asm
	add.f32 	%f1361, %f297, %f1358;
	add.f32 	%f1362, %f298, %f1359;
	add.f32 	%f1363, %f300, %f1360;
	mov.f32 	%f1364, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1363;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f1362;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f1361;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1364;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs25, %rs26, %rs27, %rs28};
	bra.uni 	$L__BB0_150;

$L__BB0_149:
	mov.f32 	%f1368, 0f3F800000;
	mov.u32 	%r501, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1368;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f300;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f298;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f297;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs33, %rs34, %rs35, %rs36};

$L__BB0_150:
	selp.f32 	%f1369, 0f3F000000, 0f3E800000, %p200;
	mul.f32 	%f374, %f1369, %f1617;
	mul.f32 	%f375, %f1369, %f1618;
	mul.f32 	%f376, %f1369, %f1619;
	mul.f32 	%f377, %f1369, %f1614;
	mul.f32 	%f378, %f1369, %f1615;
	mul.f32 	%f379, %f1369, %f1616;
	mul.f32 	%f380, %f1369, %f1611;
	mul.f32 	%f381, %f1369, %f1612;
	mul.f32 	%f382, %f1369, %f1613;
	mul.f32 	%f383, %f1369, %f1608;
	mul.f32 	%f384, %f1369, %f1609;
	mul.f32 	%f385, %f1369, %f1610;
	mul.f32 	%f386, %f374, %f828;
	mul.f32 	%f387, %f375, %f829;
	mul.f32 	%f388, %f376, %f299;
	ld.const.u64 	%rd85, [params+256];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r457, [params+248];
	mad.lo.s32 	%r458, %r457, %r6, %r5;
	mul.wide.u32 	%rd87, %r458, 8;
	add.s64 	%rd24, %rd86, %rd87;
	setp.eq.s32 	%p185, %r501, 0;
	@%p185 bra 	$L__BB0_152;

	ld.global.v4.u16 	{%rs44, %rs45, %rs46, %rs47}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1370, %rs44;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1371, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1372, %rs46;}

	// end inline asm
	add.f32 	%f1373, %f386, %f1370;
	add.f32 	%f1374, %f387, %f1371;
	add.f32 	%f1375, %f388, %f1372;
	mov.f32 	%f1376, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1375;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1374;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1373;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1376;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs40, %rs41, %rs42, %rs43};
	bra.uni 	$L__BB0_153;

$L__BB0_152:
	mov.f32 	%f1380, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1380;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f388;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f387;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f386;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs48, %rs49, %rs50, %rs51};

$L__BB0_153:
	mov.f32 	%f1381, 0f34000000;
	max.f32 	%f1382, %f374, %f1381;
	div.rn.f32 	%f1383, %f377, %f1382;
	max.f32 	%f1384, %f375, %f1381;
	div.rn.f32 	%f1385, %f378, %f1384;
	max.f32 	%f1386, %f376, %f1381;
	div.rn.f32 	%f1387, %f379, %f1386;
	fma.rn.f32 	%f389, %f1383, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f390, %f1385, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f391, %f1387, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1388, %f380, %f1382;
	div.rn.f32 	%f1389, %f381, %f1384;
	div.rn.f32 	%f1390, %f382, %f1386;
	fma.rn.f32 	%f392, %f1388, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f393, %f1389, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f394, %f1390, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1391, %f383, %f1382;
	div.rn.f32 	%f1392, %f384, %f1384;
	div.rn.f32 	%f1393, %f385, %f1386;
	fma.rn.f32 	%f395, %f1391, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f396, %f1392, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f397, %f1393, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd88, [params+272];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r459, [params+264];
	mad.lo.s32 	%r460, %r459, %r6, %r5;
	mul.wide.u32 	%rd90, %r460, 8;
	add.s64 	%rd25, %rd89, %rd90;
	@%p185 bra 	$L__BB0_155;

	ld.global.v4.u16 	{%rs59, %rs60, %rs61, %rs62}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1394, %rs59;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1395, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1396, %rs61;}

	// end inline asm
	add.f32 	%f1397, %f389, %f1394;
	add.f32 	%f1398, %f390, %f1395;
	add.f32 	%f1399, %f391, %f1396;
	mov.f32 	%f1400, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1399;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1398;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1397;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1400;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs55, %rs56, %rs57, %rs58};
	bra.uni 	$L__BB0_156;

$L__BB0_155:
	mov.f32 	%f1404, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1404;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f391;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f390;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f389;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs63, %rs64, %rs65, %rs66};

$L__BB0_156:
	ld.const.u64 	%rd91, [params+288];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r461, [params+280];
	mad.lo.s32 	%r462, %r461, %r6, %r5;
	mul.wide.u32 	%rd93, %r462, 8;
	add.s64 	%rd26, %rd92, %rd93;
	@%p185 bra 	$L__BB0_158;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1405, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1406, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1407, %rs76;}

	// end inline asm
	add.f32 	%f1408, %f392, %f1405;
	add.f32 	%f1409, %f393, %f1406;
	add.f32 	%f1410, %f394, %f1407;
	mov.f32 	%f1411, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1410;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1409;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1408;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1411;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_159;

$L__BB0_158:
	mov.f32 	%f1415, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1415;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f394;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f393;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f392;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_159:
	ld.const.u64 	%rd94, [params+304];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r463, [params+296];
	mad.lo.s32 	%r464, %r463, %r6, %r5;
	mul.wide.u32 	%rd96, %r464, 8;
	add.s64 	%rd27, %rd95, %rd96;
	@%p185 bra 	$L__BB0_161;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1416, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1417, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1418, %rs91;}

	// end inline asm
	add.f32 	%f1419, %f395, %f1416;
	add.f32 	%f1420, %f396, %f1417;
	add.f32 	%f1421, %f397, %f1418;
	mov.f32 	%f1422, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1421;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1420;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1419;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1422;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_182;

$L__BB0_161:
	mov.f32 	%f1426, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1426;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f397;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f396;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f395;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_182:
	ret;

}