//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<171>;
	.reg .b16 	%rs<178>;
	.reg .f32 	%f<1190>;
	.reg .b32 	%r<369>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<122>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r54), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r55), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd31, [params+400];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r60, [params+392];
	mad.lo.s32 	%r61, %r60, %r55, %r54;
	mul.wide.u32 	%rd33, %r61, 4;
	add.s64 	%rd2, %rd32, %rd33;
	ld.global.v2.u8 	{%rs7, %rs177}, [%rd2];
	or.b16  	%rs9, %rs7, %rs177;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p8, %rs10, 0;
	@%p8 bra 	$L__BB0_2;

	ld.global.u8 	%rs176, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs176, [%rd2+2];
	setp.eq.s16 	%p9, %rs176, 0;
	mov.f32 	%f1148, 0f00000000;
	mov.u16 	%rs177, 0;
	mov.f32 	%f1149, %f1148;
	mov.f32 	%f1150, %f1148;
	@%p9 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f174, %rs7;
	div.rn.f32 	%f175, %f174, 0f437F0000;
	fma.rn.f32 	%f176, %f175, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs177, 255;
	cvt.rn.f32.u16 	%f177, %rs13;
	div.rn.f32 	%f178, %f177, 0f437F0000;
	fma.rn.f32 	%f179, %f178, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f180, %rs176;
	div.rn.f32 	%f181, %f180, 0f437F0000;
	fma.rn.f32 	%f182, %f181, 0f40000000, 0fBF800000;
	mul.f32 	%f183, %f179, %f179;
	fma.rn.f32 	%f184, %f176, %f176, %f183;
	fma.rn.f32 	%f185, %f182, %f182, %f184;
	sqrt.rn.f32 	%f186, %f185;
	rcp.rn.f32 	%f187, %f186;
	mul.f32 	%f1150, %f187, %f182;
	mul.f32 	%f1149, %f187, %f179;
	mul.f32 	%f1148, %f176, %f187;

$L__BB0_4:
	ld.const.v2.u32 	{%r62, %r63}, [params];
	add.s32 	%r3, %r62, %r54;
	add.s32 	%r4, %r63, %r55;
	setp.eq.f32 	%p10, %f1148, 0f00000000;
	setp.eq.f32 	%p11, %f1149, 0f00000000;
	and.pred  	%p12, %p10, %p11;
	setp.eq.f32 	%p13, %f1150, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	@%p14 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_5;

$L__BB0_140:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r331, %r51, 1;
	setp.eq.b32 	%p160, %r331, 1;
	mov.pred 	%p161, 0;
	xor.pred  	%p162, %p160, %p161;
	not.pred 	%p163, %p162;
	@%p163 bra 	$L__BB0_142;

	ld.const.u64 	%rd88, [params+144];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r332, [params+136];
	mad.lo.s32 	%r333, %r332, %r4, %r3;
	mul.wide.u32 	%rd90, %r333, 4;
	add.s64 	%rd91, %rd89, %rd90;
	mov.u16 	%rs98, 0;
	st.global.v4.u8 	[%rd91], {%rs98, %rs98, %rs98, %rs98};

$L__BB0_142:
	and.b32  	%r334, %r51, 8;
	setp.eq.s32 	%p164, %r334, 0;
	@%p164 bra 	$L__BB0_144;

	ld.const.u64 	%rd92, [params+192];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r335, [params+184];
	mad.lo.s32 	%r336, %r335, %r4, %r3;
	mov.f32 	%f1043, 0f00000000;
	cvt.rzi.u32.f32 	%r337, %f1043;
	mul.wide.u32 	%rd94, %r336, 2;
	add.s64 	%rd95, %rd93, %rd94;
	mov.u16 	%rs99, 0;
	cvt.u16.u32 	%rs100, %r337;
	st.global.v2.u8 	[%rd95], {%rs100, %rs99};

$L__BB0_144:
	and.b32  	%r338, %r51, 4;
	setp.eq.s32 	%p165, %r338, 0;
	ld.const.u32 	%r368, [params+108];
	@%p165 bra 	$L__BB0_148;

	setp.eq.s32 	%p166, %r368, 0;
	ld.const.u64 	%rd96, [params+224];
	cvta.to.global.u64 	%rd97, %rd96;
	ld.const.u32 	%r339, [params+216];
	mad.lo.s32 	%r340, %r339, %r4, %r3;
	mul.wide.u32 	%rd98, %r340, 8;
	add.s64 	%rd25, %rd97, %rd98;
	@%p166 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs107, %rs108, %rs109, %rs110}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1044, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1045, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1046, %rs109;}

	// end inline asm
	add.f32 	%f1047, %f1044, 0f00000000;
	add.f32 	%f1048, %f1045, 0f00000000;
	add.f32 	%f1049, %f1046, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1049;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1048;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1047;}

	// end inline asm
	mov.u16 	%rs111, 0;
	st.global.v4.u16 	[%rd25], {%rs104, %rs105, %rs106, %rs111};
	bra.uni 	$L__BB0_148;

$L__BB0_5:
	ld.const.v4.f32 	{%f191, %f192, %f193, %f194}, [params+512];
	neg.f32 	%f195, %f192;
	neg.f32 	%f196, %f193;
	mul.f32 	%f197, %f1148, %f191;
	mul.f32 	%f198, %f1149, %f195;
	sub.f32 	%f199, %f198, %f197;
	mul.f32 	%f200, %f1150, %f193;
	sub.f32 	%f13, %f199, %f200;
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r66, [params+424];
	mad.lo.s32 	%r67, %r66, %r55, %r54;
	mul.wide.u32 	%rd36, %r67, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f14, [%rd37];
	mul.f32 	%f201, %f14, 0f3456BF95;
	ld.global.f32 	%f15, [%rd37+4];
	mul.f32 	%f202, %f15, 0f3456BF95;
	ld.global.f32 	%f16, [%rd37+8];
	mul.f32 	%f203, %f16, 0f3456BF95;
	abs.f32 	%f204, %f1148;
	div.rn.f32 	%f205, %f201, %f204;
	abs.f32 	%f206, %f1149;
	div.rn.f32 	%f207, %f202, %f206;
	abs.f32 	%f208, %f1150;
	div.rn.f32 	%f209, %f203, %f208;
	abs.f32 	%f210, %f205;
	abs.f32 	%f211, %f207;
	abs.f32 	%f212, %f209;
	mov.f32 	%f213, 0f38D1B717;
	max.f32 	%f214, %f210, %f213;
	max.f32 	%f215, %f211, %f213;
	max.f32 	%f216, %f212, %f213;
	fma.rn.f32 	%f17, %f1148, %f214, %f14;
	fma.rn.f32 	%f18, %f1149, %f215, %f15;
	fma.rn.f32 	%f19, %f1150, %f216, %f16;
	abs.f32 	%f217, %f191;
	abs.f32 	%f218, %f193;
	setp.gt.f32 	%p15, %f217, %f218;
	selp.f32 	%f219, %f195, 0f00000000, %p15;
	mov.f32 	%f1156, 0f00000000;
	selp.f32 	%f220, %f191, %f196, %p15;
	selp.f32 	%f221, 0f00000000, %f192, %p15;
	mul.f32 	%f222, %f220, %f220;
	fma.rn.f32 	%f223, %f219, %f219, %f222;
	fma.rn.f32 	%f224, %f221, %f221, %f223;
	sqrt.rn.f32 	%f225, %f224;
	rcp.rn.f32 	%f226, %f225;
	mul.f32 	%f20, %f219, %f226;
	mul.f32 	%f21, %f220, %f226;
	mul.f32 	%f22, %f221, %f226;
	mul.f32 	%f227, %f193, %f21;
	mul.f32 	%f228, %f192, %f22;
	sub.f32 	%f23, %f227, %f228;
	mul.f32 	%f229, %f191, %f22;
	mul.f32 	%f230, %f193, %f20;
	sub.f32 	%f24, %f229, %f230;
	mul.f32 	%f231, %f192, %f20;
	mul.f32 	%f232, %f191, %f21;
	sub.f32 	%f25, %f231, %f232;
	ld.const.u64 	%rd38, [params+128];
	cvta.to.global.u64 	%rd39, %rd38;
	ld.const.u32 	%r68, [params+120];
	mad.lo.s32 	%r69, %r68, %r55, %r54;
	mul.wide.u32 	%rd40, %r69, 4;
	add.s64 	%rd3, %rd39, %rd40;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p16, %r5, 1;
	mov.f32 	%f1155, %f1156;
	mov.f32 	%f1154, %f1156;
	@%p16 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f236, %r5;
	rcp.rn.f32 	%f26, %f236;
	ld.global.u32 	%r359, [%rd3];
	ld.const.f32 	%f27, [params+536];
	ld.const.u8 	%rs15, [params+104];
	and.b16  	%rs16, %rs15, 32;
	setp.eq.s16 	%p17, %rs16, 0;
	mov.u32 	%r70, 0;
	selp.f32 	%f28, 0f3F800000, 0f41200000, %p17;
	mul.f32 	%f29, %f17, 0f3456BF95;
	mul.f32 	%f30, %f18, 0f3456BF95;
	mul.f32 	%f31, %f19, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd41, __cudart_i2opi_f;
	abs.f32 	%f319, %f30;
	abs.f32 	%f320, %f29;
	max.f32 	%f321, %f320, %f319;
	abs.f32 	%f322, %f31;
	max.f32 	%f323, %f321, %f322;
	mov.u32 	%r356, %r70;

$L__BB0_7:
	mov.u32 	%r358, %r70;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1095, %r356;
	mad.lo.s32 	%r72, %r359, 1664525, 1013904223;
	and.b32  	%r73, %r72, 16777215;
	cvt.rn.f32.u32 	%f237, %r73;
	fma.rn.f32 	%f238, %f237, 0f33800000, %f1095;
	mul.f32 	%f239, %f26, %f238;
	mad.lo.s32 	%r359, %r72, 1664525, 1013904223;
	and.b32  	%r74, %r359, 16777215;
	cvt.rn.f32.u32 	%f240, %r74;
	cvt.rn.f32.s32 	%f241, %r358;
	fma.rn.f32 	%f242, %f240, 0f33800000, %f241;
	mul.f32 	%f243, %f26, %f242;
	sqrt.rn.f32 	%f39, %f239;
	mul.f32 	%f40, %f243, 0f40C90FDB;
	mul.f32 	%f244, %f40, 0f3F22F983;
	cvt.rni.s32.f32 	%r366, %f244;
	cvt.rn.f32.s32 	%f245, %r366;
	mov.f32 	%f246, 0fBFC90FDA;
	fma.rn.f32 	%f247, %f245, %f246, %f40;
	mov.f32 	%f248, 0fB3A22168;
	fma.rn.f32 	%f249, %f245, %f248, %f247;
	mov.f32 	%f250, 0fA7C234C5;
	fma.rn.f32 	%f1160, %f245, %f250, %f249;
	abs.f32 	%f42, %f40;
	setp.ltu.f32 	%p18, %f42, 0f47CE4780;
	mov.u32 	%r363, %r366;
	mov.f32 	%f1157, %f1160;
	@%p18 bra 	$L__BB0_16;

	setp.eq.f32 	%p19, %f42, 0f7F800000;
	@%p19 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f253, 0f00000000;
	mul.rn.f32 	%f1157, %f40, %f253;
	mov.u32 	%r363, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f40;
	bfe.u32 	%r76, %r13, 23, 8;
	add.s32 	%r14, %r76, -128;
	shl.b32 	%r77, %r13, 8;
	or.b32  	%r15, %r77, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd119, 0;
	mov.u32 	%r360, 0;
	mov.u64 	%rd117, %rd1;
	mov.u64 	%rd118, %rd41;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r78, [%rd118];
	mad.wide.u32 	%rd43, %r78, %r15, %rd119;
	shr.u64 	%rd119, %rd43, 32;
	st.local.u32 	[%rd117], %rd43;
	add.s64 	%rd118, %rd118, 4;
	add.s64 	%rd117, %rd117, 4;
	add.s32 	%r360, %r360, 1;
	setp.ne.s32 	%p20, %r360, 6;
	@%p20 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd119;
	mov.u32 	%r79, 4;
	sub.s32 	%r19, %r79, %r16;
	mov.u32 	%r80, 6;
	sub.s32 	%r81, %r80, %r16;
	mul.wide.s32 	%rd44, %r81, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r361, [%rd45];
	ld.local.u32 	%r362, [%rd45+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p21, %r22, 0;
	@%p21 bra 	$L__BB0_14;

	mov.u32 	%r82, 32;
	sub.s32 	%r83, %r82, %r22;
	shr.u32 	%r84, %r362, %r83;
	shl.b32 	%r85, %r361, %r22;
	add.s32 	%r361, %r84, %r85;
	mul.wide.s32 	%rd46, %r19, 4;
	add.s64 	%rd47, %rd1, %rd46;
	ld.local.u32 	%r86, [%rd47];
	shr.u32 	%r87, %r86, %r83;
	shl.b32 	%r88, %r362, %r22;
	add.s32 	%r362, %r87, %r88;

$L__BB0_14:
	and.b32  	%r89, %r13, -2147483648;
	shr.u32 	%r90, %r362, 30;
	shl.b32 	%r91, %r361, 2;
	or.b32  	%r92, %r90, %r91;
	shr.u32 	%r93, %r92, 31;
	shr.u32 	%r94, %r361, 30;
	add.s32 	%r95, %r93, %r94;
	neg.s32 	%r96, %r95;
	setp.eq.s32 	%p22, %r89, 0;
	selp.b32 	%r363, %r95, %r96, %p22;
	setp.ne.s32 	%p23, %r93, 0;
	xor.b32  	%r97, %r89, -2147483648;
	selp.b32 	%r98, %r97, %r89, %p23;
	selp.b32 	%r99, -1, 0, %p23;
	xor.b32  	%r100, %r92, %r99;
	shl.b32 	%r101, %r362, 2;
	xor.b32  	%r102, %r101, %r99;
	cvt.u64.u32 	%rd48, %r100;
	cvt.u64.u32 	%rd49, %r102;
	bfi.b64 	%rd50, %rd48, %rd49, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd50;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f251, %fd2;
	setp.eq.s32 	%p24, %r98, 0;
	neg.f32 	%f252, %f251;
	selp.f32 	%f1157, %f251, %f252, %p24;

$L__BB0_16:
	add.s32 	%r29, %r363, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p25, %r30, 0;
	selp.f32 	%f46, %f1157, 0f3F800000, %p25;
	mul.rn.f32 	%f47, %f1157, %f1157;
	mov.f32 	%f1158, 0fB94D4153;
	@%p25 bra 	$L__BB0_18;

	mov.f32 	%f255, 0fBAB607ED;
	mov.f32 	%f256, 0f37CBAC00;
	fma.rn.f32 	%f1158, %f256, %f47, %f255;

$L__BB0_18:
	selp.f32 	%f257, 0f3C0885E4, 0f3D2AAABB, %p25;
	fma.rn.f32 	%f258, %f1158, %f47, %f257;
	selp.f32 	%f259, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
	fma.rn.f32 	%f260, %f258, %f47, %f259;
	mov.f32 	%f261, 0f00000000;
	fma.rn.f32 	%f262, %f47, %f46, %f261;
	fma.rn.f32 	%f1159, %f260, %f262, %f46;
	and.b32  	%r104, %r29, 2;
	setp.eq.s32 	%p27, %r104, 0;
	@%p27 bra 	$L__BB0_20;

	mov.f32 	%f264, 0fBF800000;
	fma.rn.f32 	%f1159, %f1159, %f264, %f261;

$L__BB0_20:
	@%p18 bra 	$L__BB0_28;

	setp.eq.f32 	%p29, %f42, 0f7F800000;
	@%p29 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f267, 0f00000000;
	mul.rn.f32 	%f1160, %f40, %f267;
	mov.u32 	%r366, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f40;
	bfe.u32 	%r105, %r31, 23, 8;
	add.s32 	%r32, %r105, -128;
	shl.b32 	%r106, %r31, 8;
	or.b32  	%r33, %r106, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd120, 0;
	mov.u64 	%rd121, %rd120;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd53, %rd120, 2;
	mov.u64 	%rd54, __cudart_i2opi_f;
	add.s64 	%rd55, %rd54, %rd53;
	ld.global.nc.u32 	%r107, [%rd55];
	mad.wide.u32 	%rd56, %r107, %r33, %rd121;
	shr.u64 	%rd121, %rd56, 32;
	add.s64 	%rd57, %rd1, %rd53;
	st.local.u32 	[%rd57], %rd56;
	cvt.u32.u64 	%r108, %rd120;
	add.s32 	%r109, %r108, 1;
	cvt.s64.s32 	%rd120, %r109;
	setp.ne.s32 	%p30, %r109, 6;
	@%p30 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd121;
	mov.u32 	%r110, 4;
	sub.s32 	%r35, %r110, %r34;
	mov.u32 	%r111, 6;
	sub.s32 	%r112, %r111, %r34;
	mul.wide.s32 	%rd58, %r112, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r364, [%rd59];
	ld.local.u32 	%r365, [%rd59+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p31, %r38, 0;
	@%p31 bra 	$L__BB0_26;

	mov.u32 	%r113, 32;
	sub.s32 	%r114, %r113, %r38;
	shr.u32 	%r115, %r365, %r114;
	shl.b32 	%r116, %r364, %r38;
	add.s32 	%r364, %r115, %r116;
	mul.wide.s32 	%rd60, %r35, 4;
	add.s64 	%rd61, %rd1, %rd60;
	ld.local.u32 	%r117, [%rd61];
	shr.u32 	%r118, %r117, %r114;
	shl.b32 	%r119, %r365, %r38;
	add.s32 	%r365, %r118, %r119;

$L__BB0_26:
	and.b32  	%r120, %r31, -2147483648;
	shr.u32 	%r121, %r365, 30;
	shl.b32 	%r122, %r364, 2;
	or.b32  	%r123, %r121, %r122;
	shr.u32 	%r124, %r123, 31;
	shr.u32 	%r125, %r364, 30;
	add.s32 	%r126, %r124, %r125;
	neg.s32 	%r127, %r126;
	setp.eq.s32 	%p32, %r120, 0;
	selp.b32 	%r366, %r126, %r127, %p32;
	setp.ne.s32 	%p33, %r124, 0;
	xor.b32  	%r128, %r120, -2147483648;
	selp.b32 	%r129, %r128, %r120, %p33;
	selp.b32 	%r130, -1, 0, %p33;
	xor.b32  	%r131, %r123, %r130;
	shl.b32 	%r132, %r365, 2;
	xor.b32  	%r133, %r132, %r130;
	cvt.u64.u32 	%rd62, %r131;
	cvt.u64.u32 	%rd63, %r133;
	bfi.b64 	%rd64, %rd62, %rd63, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd64;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f265, %fd4;
	setp.eq.s32 	%p34, %r129, 0;
	neg.f32 	%f266, %f265;
	selp.f32 	%f1160, %f265, %f266, %p34;

$L__BB0_28:
	mul.f32 	%f56, %f39, %f1159;
	and.b32  	%r45, %r366, 1;
	setp.eq.s32 	%p35, %r45, 0;
	selp.f32 	%f57, %f1160, 0f3F800000, %p35;
	mul.rn.f32 	%f58, %f1160, %f1160;
	mov.f32 	%f1161, 0fB94D4153;
	@%p35 bra 	$L__BB0_30;

	mov.f32 	%f269, 0fBAB607ED;
	mov.f32 	%f270, 0f37CBAC00;
	fma.rn.f32 	%f1161, %f270, %f58, %f269;

$L__BB0_30:
	selp.f32 	%f271, 0f3C0885E4, 0f3D2AAABB, %p35;
	fma.rn.f32 	%f272, %f1161, %f58, %f271;
	selp.f32 	%f273, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
	fma.rn.f32 	%f274, %f272, %f58, %f273;
	mov.f32 	%f275, 0f00000000;
	fma.rn.f32 	%f276, %f58, %f57, %f275;
	fma.rn.f32 	%f1162, %f274, %f276, %f57;
	and.b32  	%r135, %r366, 2;
	setp.eq.s32 	%p37, %r135, 0;
	@%p37 bra 	$L__BB0_32;

	mov.f32 	%f278, 0fBF800000;
	fma.rn.f32 	%f1162, %f1162, %f278, %f275;

$L__BB0_32:
	mul.f32 	%f288, %f56, %f56;
	mov.f32 	%f289, 0f3F800000;
	sub.f32 	%f290, %f289, %f288;
	mul.f32 	%f291, %f39, %f1162;
	mul.f32 	%f292, %f291, %f291;
	sub.f32 	%f293, %f290, %f292;
	max.f32 	%f294, %f275, %f293;
	sqrt.rn.f32 	%f295, %f294;
	mul.f32 	%f296, %f20, %f291;
	mul.f32 	%f297, %f21, %f291;
	mul.f32 	%f298, %f22, %f291;
	fma.rn.f32 	%f299, %f23, %f56, %f296;
	fma.rn.f32 	%f300, %f24, %f56, %f297;
	fma.rn.f32 	%f301, %f25, %f56, %f298;
	fma.rn.f32 	%f302, %f191, %f295, %f299;
	fma.rn.f32 	%f303, %f192, %f295, %f300;
	fma.rn.f32 	%f304, %f193, %f295, %f301;
	add.f32 	%f305, %f191, %f302;
	add.f32 	%f306, %f192, %f303;
	add.f32 	%f307, %f193, %f304;
	mul.f32 	%f308, %f27, %f305;
	mul.f32 	%f309, %f27, %f306;
	mul.f32 	%f310, %f27, %f307;
	sub.f32 	%f311, %f308, %f191;
	sub.f32 	%f312, %f309, %f192;
	sub.f32 	%f313, %f310, %f193;
	mul.f32 	%f314, %f312, %f312;
	fma.rn.f32 	%f315, %f311, %f311, %f314;
	fma.rn.f32 	%f316, %f313, %f313, %f315;
	sqrt.rn.f32 	%f317, %f316;
	rcp.rn.f32 	%f318, %f317;
	mul.f32 	%f282, %f318, %f311;
	mul.f32 	%f283, %f318, %f312;
	mul.f32 	%f284, %f318, %f313;
	mov.f32 	%f324, 0f38D1B717;
	max.f32 	%f325, %f323, %f324;
	mul.f32 	%f285, %f28, %f325;
	mov.f32 	%f286, 0f6C4ECB8F;
	mov.u32 	%r172, 2;
	mov.u32 	%r173, 1;
	mov.u32 	%r174, 3;
	mov.u32 	%r177, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f17,%f18,%f19,%f282,%f283,%f284,%f285,%f286,%f275,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f326, %r136;
	mov.b32 	%f327, %r137;
	mov.b32 	%f328, %r138;
	add.f32 	%f1156, %f1156, %f326;
	add.f32 	%f1155, %f1155, %f327;
	add.f32 	%f1154, %f1154, %f328;
	add.s32 	%r358, %r358, 1;
	setp.lt.s32 	%p38, %r358, %r5;
	@%p38 bra 	$L__BB0_8;

	add.s32 	%r356, %r356, 1;
	setp.lt.s32 	%p39, %r356, %r5;
	@%p39 bra 	$L__BB0_7;

$L__BB0_34:
	setp.eq.s32 	%p40, %r5, 0;
	mov.f32 	%f1166, 0f3F800000;
	mov.f32 	%f1167, %f1166;
	mov.f32 	%f1168, %f1166;
	@%p40 bra 	$L__BB0_36;

	mul.lo.s32 	%r207, %r5, %r5;
	cvt.rn.f32.s32 	%f332, %r207;
	rcp.rn.f32 	%f333, %f332;
	mul.f32 	%f1166, %f1156, %f333;
	mul.f32 	%f1167, %f1155, %f333;
	mul.f32 	%f1168, %f1154, %f333;

$L__BB0_36:
	mul.f32 	%f334, %f15, %f24;
	fma.rn.f32 	%f335, %f14, %f23, %f334;
	fma.rn.f32 	%f336, %f16, %f25, %f335;
	ld.const.v4.f32 	{%f337, %f338, %f339, %f340}, [params+560];
	fma.rn.f32 	%f345, %f336, %f337, %f339;
	mul.f32 	%f346, %f15, %f21;
	fma.rn.f32 	%f347, %f14, %f20, %f346;
	fma.rn.f32 	%f348, %f16, %f22, %f347;
	fma.rn.f32 	%f349, %f348, %f338, %f340;
	ld.const.u64 	%rd66, [params+552];
	tex.2d.v4.f32.f32 	{%f350, %f351, %f352, %f353}, [%rd66, {%f345, %f349}];
	min.f32 	%f354, %f350, %f351;
	min.f32 	%f355, %f354, %f352;
	mul.f32 	%f76, %f1166, %f355;
	ld.const.f32 	%f356, [params+524];
	mul.f32 	%f357, %f1166, %f356;
	ld.const.v2.f32 	{%f358, %f359}, [params+528];
	mul.f32 	%f362, %f1167, %f358;
	mul.f32 	%f363, %f1168, %f359;
	mul.f32 	%f364, %f350, %f357;
	mul.f32 	%f365, %f351, %f362;
	mul.f32 	%f366, %f352, %f363;
	cvt.sat.f32.f32 	%f367, %f13;
	mul.f32 	%f77, %f364, %f367;
	mul.f32 	%f78, %f365, %f367;
	mul.f32 	%f79, %f367, %f366;
	mul.f32 	%f80, %f364, 0f3E800000;
	mul.f32 	%f81, %f365, 0f3E800000;
	mul.f32 	%f82, %f366, 0f3E800000;
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r208, %r48, 8;
	setp.eq.s32 	%p41, %r208, 0;
	@%p41 bra 	$L__BB0_50;

	mov.f32 	%f372, 0f3EE8BA2E;
	abs.f32 	%f84, %f76;
	setp.lt.f32 	%p42, %f84, 0f00800000;
	mul.f32 	%f374, %f84, 0f4B800000;
	selp.f32 	%f375, %f374, %f84, %p42;
	selp.f32 	%f376, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r211, %f375;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f377, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f378, %r214;
	add.f32 	%f379, %f376, %f378;
	setp.gt.f32 	%p43, %f377, 0f3FB504F3;
	mul.f32 	%f380, %f377, 0f3F000000;
	add.f32 	%f381, %f379, 0f3F800000;
	selp.f32 	%f382, %f381, %f379, %p43;
	selp.f32 	%f383, %f380, %f377, %p43;
	add.f32 	%f384, %f383, 0fBF800000;
	add.f32 	%f385, %f383, 0f3F800000;
	rcp.approx.ftz.f32 	%f386, %f385;
	add.f32 	%f387, %f384, %f384;
	mul.f32 	%f388, %f387, %f386;
	mul.f32 	%f389, %f388, %f388;
	mov.f32 	%f390, 0f3C4CAF63;
	mov.f32 	%f391, 0f3B18F0FE;
	fma.rn.f32 	%f392, %f391, %f389, %f390;
	mov.f32 	%f393, 0f3DAAAABD;
	fma.rn.f32 	%f394, %f392, %f389, %f393;
	mul.rn.f32 	%f395, %f394, %f389;
	mul.rn.f32 	%f396, %f395, %f388;
	sub.f32 	%f397, %f384, %f388;
	add.f32 	%f398, %f397, %f397;
	neg.f32 	%f399, %f388;
	fma.rn.f32 	%f400, %f399, %f384, %f398;
	mul.rn.f32 	%f401, %f386, %f400;
	add.f32 	%f402, %f396, %f388;
	sub.f32 	%f403, %f388, %f402;
	add.f32 	%f404, %f396, %f403;
	add.f32 	%f405, %f401, %f404;
	add.f32 	%f406, %f402, %f405;
	sub.f32 	%f407, %f402, %f406;
	add.f32 	%f408, %f405, %f407;
	mov.f32 	%f409, 0f3F317200;
	mul.rn.f32 	%f410, %f382, %f409;
	mov.f32 	%f411, 0f35BFBE8E;
	mul.rn.f32 	%f412, %f382, %f411;
	add.f32 	%f413, %f410, %f406;
	sub.f32 	%f414, %f410, %f413;
	add.f32 	%f415, %f406, %f414;
	add.f32 	%f416, %f408, %f415;
	add.f32 	%f417, %f412, %f416;
	add.f32 	%f418, %f413, %f417;
	sub.f32 	%f419, %f413, %f418;
	add.f32 	%f420, %f417, %f419;
	mul.rn.f32 	%f421, %f372, %f418;
	neg.f32 	%f422, %f421;
	fma.rn.f32 	%f423, %f372, %f418, %f422;
	fma.rn.f32 	%f424, %f372, %f420, %f423;
	mov.f32 	%f425, 0f00000000;
	fma.rn.f32 	%f426, %f425, %f418, %f424;
	add.rn.f32 	%f427, %f421, %f426;
	neg.f32 	%f428, %f427;
	add.rn.f32 	%f429, %f421, %f428;
	add.rn.f32 	%f430, %f429, %f426;
	mov.b32 	%r215, %f427;
	setp.eq.s32 	%p44, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f431, %r216;
	add.f32 	%f432, %f430, 0f37000000;
	selp.f32 	%f85, %f432, %f430, %p44;
	selp.f32 	%f433, %f431, %f427, %p44;
	mov.f32 	%f434, 0f3FB8AA3B;
	mul.rn.f32 	%f435, %f433, %f434;
	cvt.rzi.f32.f32 	%f436, %f435;
	abs.f32 	%f437, %f436;
	setp.gt.f32 	%p45, %f437, 0f42FC0000;
	mov.b32 	%r217, %f436;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f438, %r219;
	selp.f32 	%f439, %f438, %f436, %p45;
	mov.f32 	%f440, 0fBF317218;
	fma.rn.f32 	%f441, %f439, %f440, %f433;
	mov.f32 	%f442, 0f3102E308;
	fma.rn.f32 	%f443, %f439, %f442, %f441;
	mul.f32 	%f444, %f443, 0f3FB8AA3B;
	add.f32 	%f445, %f439, 0f4B40007F;
	mov.b32 	%r220, %f445;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f446, %r221;
	ex2.approx.ftz.f32 	%f447, %f444;
	mul.f32 	%f86, %f447, %f446;
	setp.eq.f32 	%p46, %f86, 0f7F800000;
	mov.f32 	%f1169, 0f7F800000;
	@%p46 bra 	$L__BB0_39;

	fma.rn.f32 	%f1169, %f86, %f85, %f86;

$L__BB0_39:
	mov.f32 	%f1101, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1100, %f1101;
	add.f32 	%f1099, %f1100, %f1100;
	mov.f32 	%f1098, 0f3EE8BA2E;
	sub.f32 	%f1097, %f1098, %f1099;
	abs.f32 	%f1096, %f1097;
	setp.lt.f32 	%p47, %f76, 0f00000000;
	setp.eq.f32 	%p48, %f1096, 0f3F800000;
	and.pred  	%p1, %p47, %p48;
	setp.eq.f32 	%p49, %f76, 0f00000000;
	@%p49 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f452, %f76, %f76;
	selp.f32 	%f1171, %f452, 0f00000000, %p48;
	bra.uni 	$L__BB0_44;

$L__BB0_147:
	mov.f32 	%f1052, 0f00000000;
	mov.u32 	%r368, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1052;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1052;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1052;}

	// end inline asm
	mov.u16 	%rs115, 0;
	st.global.v4.u16 	[%rd25], {%rs112, %rs113, %rs114, %rs115};

$L__BB0_148:
	ld.const.u64 	%rd99, [params+256];
	cvta.to.global.u64 	%rd100, %rd99;
	ld.const.u32 	%r342, [params+248];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	mul.wide.u32 	%rd101, %r343, 8;
	add.s64 	%rd26, %rd100, %rd101;
	setp.eq.s32 	%p167, %r368, 0;
	@%p167 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs122, %rs123, %rs124, %rs125}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1053, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1054, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1055, %rs124;}

	// end inline asm
	add.f32 	%f1056, %f1053, 0f00000000;
	add.f32 	%f1057, %f1054, 0f00000000;
	add.f32 	%f1058, %f1055, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1058;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1057;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1056;}

	// end inline asm
	mov.u16 	%rs126, 0;
	st.global.v4.u16 	[%rd26], {%rs119, %rs120, %rs121, %rs126};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1061, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1061;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1061;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1061;}

	// end inline asm
	mov.u16 	%rs130, 0;
	st.global.v4.u16 	[%rd26], {%rs127, %rs128, %rs129, %rs130};

$L__BB0_151:
	ld.const.u64 	%rd102, [params+272];
	cvta.to.global.u64 	%rd103, %rd102;
	ld.const.u32 	%r344, [params+264];
	mad.lo.s32 	%r345, %r344, %r4, %r3;
	mul.wide.u32 	%rd104, %r345, 8;
	add.s64 	%rd27, %rd103, %rd104;
	@%p167 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs137, %rs138, %rs139, %rs140}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1062, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1063, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1064, %rs139;}

	// end inline asm
	add.f32 	%f1065, %f1062, 0f00000000;
	add.f32 	%f1066, %f1063, 0f00000000;
	add.f32 	%f1067, %f1064, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1067;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1066;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1065;}

	// end inline asm
	mov.u16 	%rs141, 0;
	st.global.v4.u16 	[%rd27], {%rs134, %rs135, %rs136, %rs141};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1070, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1070;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1070;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1070;}

	// end inline asm
	mov.u16 	%rs145, 0;
	st.global.v4.u16 	[%rd27], {%rs142, %rs143, %rs144, %rs145};

$L__BB0_154:
	ld.const.u64 	%rd105, [params+288];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r346, [params+280];
	mad.lo.s32 	%r347, %r346, %r4, %r3;
	mul.wide.u32 	%rd107, %r347, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p167 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs152, %rs153, %rs154, %rs155}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1071, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1072, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1073, %rs154;}

	// end inline asm
	add.f32 	%f1074, %f1071, 0f00000000;
	add.f32 	%f1075, %f1072, 0f00000000;
	add.f32 	%f1076, %f1073, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1076;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1075;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1074;}

	// end inline asm
	mov.u16 	%rs156, 0;
	st.global.v4.u16 	[%rd28], {%rs149, %rs150, %rs151, %rs156};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1079, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1079;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1079;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1079;}

	// end inline asm
	mov.u16 	%rs160, 0;
	st.global.v4.u16 	[%rd28], {%rs157, %rs158, %rs159, %rs160};

$L__BB0_157:
	ld.const.u64 	%rd108, [params+304];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r348, [params+296];
	mad.lo.s32 	%r349, %r348, %r4, %r3;
	mul.wide.u32 	%rd110, %r349, 8;
	add.s64 	%rd29, %rd109, %rd110;
	@%p167 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs167, %rs168, %rs169, %rs170}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1080, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1081, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1082, %rs169;}

	// end inline asm
	add.f32 	%f1083, %f1080, 0f00000000;
	add.f32 	%f1084, %f1081, 0f00000000;
	add.f32 	%f1085, %f1082, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1085;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1084;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1083;}

	// end inline asm
	mov.u16 	%rs171, 0;
	st.global.v4.u16 	[%rd29], {%rs164, %rs165, %rs166, %rs171};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1088, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1088;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1088;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1088;}

	// end inline asm
	mov.u16 	%rs175, 0;
	st.global.v4.u16 	[%rd29], {%rs172, %rs173, %rs174, %rs175};
	bra.uni 	$L__BB0_160;

$L__BB0_40:
	mov.b32 	%r222, %f1169;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f448, %r223;
	selp.f32 	%f1171, %f448, %f1169, %p1;
	setp.geu.f32 	%p50, %f76, 0f00000000;
	@%p50 bra 	$L__BB0_44;

	mov.f32 	%f449, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f450, %f449;
	setp.eq.f32 	%p51, %f450, 0f3EE8BA2E;
	@%p51 bra 	$L__BB0_44;

	mov.f32 	%f1171, 0f7FFFFFFF;

$L__BB0_44:
	abs.f32 	%f1102, %f76;
	add.f32 	%f453, %f1102, 0f3EE8BA2E;
	mov.b32 	%r224, %f453;
	setp.lt.s32 	%p53, %r224, 2139095040;
	@%p53 bra 	$L__BB0_49;

	abs.f32 	%f1103, %f76;
	setp.gtu.f32 	%p54, %f1103, 0f7F800000;
	@%p54 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1171, %f76, 0f3EE8BA2E;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	abs.f32 	%f1104, %f76;
	setp.neu.f32 	%p55, %f1104, 0f7F800000;
	@%p55 bra 	$L__BB0_49;

	selp.f32 	%f1171, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	ld.const.u32 	%r355, [params+184];
	mad.lo.s32 	%r354, %r355, %r4, %r3;
	cvt.u64.u32 	%rd116, %r354;
	ld.const.u64 	%rd115, [params+192];
	cvta.to.global.u64 	%rd114, %rd115;
	mul.f32 	%f454, %f1171, 0f437F0000;
	setp.eq.f32 	%p56, %f76, 0f3F800000;
	selp.f32 	%f455, 0f437F0000, %f454, %p56;
	cvt.rzi.u32.f32 	%r225, %f455;
	shl.b64 	%rd68, %rd116, 1;
	add.s64 	%rd69, %rd114, %rd68;
	cvt.u16.u32 	%rs17, %r225;
	mov.u16 	%rs18, 255;
	st.global.v2.u8 	[%rd69], {%rs17, %rs18};

$L__BB0_50:
	ld.const.u32 	%r353, [params+104];
	and.b32  	%r226, %r353, 1;
	setp.eq.b32 	%p57, %r226, 1;
	mov.pred 	%p58, 0;
	xor.pred  	%p59, %p57, %p58;
	not.pred 	%p60, %p59;
	@%p60 bra 	$L__BB0_124;

	mov.f32 	%f460, 0f3EE66666;
	abs.f32 	%f96, %f77;
	setp.lt.f32 	%p61, %f96, 0f00800000;
	mul.f32 	%f462, %f96, 0f4B800000;
	selp.f32 	%f463, %f462, %f96, %p61;
	selp.f32 	%f464, 0fC3170000, 0fC2FE0000, %p61;
	mov.b32 	%r227, %f463;
	and.b32  	%r228, %r227, 8388607;
	or.b32  	%r229, %r228, 1065353216;
	mov.b32 	%f465, %r229;
	shr.u32 	%r230, %r227, 23;
	cvt.rn.f32.u32 	%f466, %r230;
	add.f32 	%f467, %f464, %f466;
	setp.gt.f32 	%p62, %f465, 0f3FB504F3;
	mul.f32 	%f468, %f465, 0f3F000000;
	add.f32 	%f469, %f467, 0f3F800000;
	selp.f32 	%f470, %f469, %f467, %p62;
	selp.f32 	%f471, %f468, %f465, %p62;
	add.f32 	%f472, %f471, 0fBF800000;
	add.f32 	%f473, %f471, 0f3F800000;
	rcp.approx.ftz.f32 	%f474, %f473;
	add.f32 	%f475, %f472, %f472;
	mul.f32 	%f476, %f475, %f474;
	mul.f32 	%f477, %f476, %f476;
	mov.f32 	%f478, 0f3C4CAF63;
	mov.f32 	%f479, 0f3B18F0FE;
	fma.rn.f32 	%f480, %f479, %f477, %f478;
	mov.f32 	%f481, 0f3DAAAABD;
	fma.rn.f32 	%f482, %f480, %f477, %f481;
	mul.rn.f32 	%f483, %f482, %f477;
	mul.rn.f32 	%f484, %f483, %f476;
	sub.f32 	%f485, %f472, %f476;
	add.f32 	%f486, %f485, %f485;
	neg.f32 	%f487, %f476;
	fma.rn.f32 	%f488, %f487, %f472, %f486;
	mul.rn.f32 	%f489, %f474, %f488;
	add.f32 	%f490, %f484, %f476;
	sub.f32 	%f491, %f476, %f490;
	add.f32 	%f492, %f484, %f491;
	add.f32 	%f493, %f489, %f492;
	add.f32 	%f494, %f490, %f493;
	sub.f32 	%f495, %f490, %f494;
	add.f32 	%f496, %f493, %f495;
	mov.f32 	%f497, 0f3F317200;
	mul.rn.f32 	%f498, %f470, %f497;
	mov.f32 	%f499, 0f35BFBE8E;
	mul.rn.f32 	%f500, %f470, %f499;
	add.f32 	%f501, %f498, %f494;
	sub.f32 	%f502, %f498, %f501;
	add.f32 	%f503, %f494, %f502;
	add.f32 	%f504, %f496, %f503;
	add.f32 	%f505, %f500, %f504;
	add.f32 	%f506, %f501, %f505;
	sub.f32 	%f507, %f501, %f506;
	add.f32 	%f508, %f505, %f507;
	mul.rn.f32 	%f509, %f460, %f506;
	neg.f32 	%f510, %f509;
	fma.rn.f32 	%f511, %f460, %f506, %f510;
	fma.rn.f32 	%f512, %f460, %f508, %f511;
	mov.f32 	%f513, 0f00000000;
	fma.rn.f32 	%f514, %f513, %f506, %f512;
	add.rn.f32 	%f515, %f509, %f514;
	neg.f32 	%f516, %f515;
	add.rn.f32 	%f517, %f509, %f516;
	add.rn.f32 	%f518, %f517, %f514;
	mov.b32 	%r231, %f515;
	setp.eq.s32 	%p63, %r231, 1118925336;
	add.s32 	%r232, %r231, -1;
	mov.b32 	%f519, %r232;
	add.f32 	%f520, %f518, 0f37000000;
	selp.f32 	%f97, %f520, %f518, %p63;
	selp.f32 	%f521, %f519, %f515, %p63;
	mov.f32 	%f522, 0f3FB8AA3B;
	mul.rn.f32 	%f523, %f521, %f522;
	cvt.rzi.f32.f32 	%f524, %f523;
	abs.f32 	%f525, %f524;
	setp.gt.f32 	%p64, %f525, 0f42FC0000;
	mov.b32 	%r233, %f524;
	and.b32  	%r234, %r233, -2147483648;
	or.b32  	%r235, %r234, 1123811328;
	mov.b32 	%f526, %r235;
	selp.f32 	%f527, %f526, %f524, %p64;
	mov.f32 	%f528, 0fBF317218;
	fma.rn.f32 	%f529, %f527, %f528, %f521;
	mov.f32 	%f530, 0f3102E308;
	fma.rn.f32 	%f531, %f527, %f530, %f529;
	mul.f32 	%f532, %f531, 0f3FB8AA3B;
	add.f32 	%f533, %f527, 0f4B40007F;
	mov.b32 	%r236, %f533;
	shl.b32 	%r237, %r236, 23;
	mov.b32 	%f534, %r237;
	ex2.approx.ftz.f32 	%f535, %f532;
	mul.f32 	%f98, %f535, %f534;
	setp.eq.f32 	%p65, %f98, 0f7F800000;
	mov.f32 	%f1172, 0f7F800000;
	@%p65 bra 	$L__BB0_53;

	fma.rn.f32 	%f1172, %f98, %f97, %f98;

$L__BB0_53:
	mov.f32 	%f1110, 0f3E666666;
	cvt.rzi.f32.f32 	%f1109, %f1110;
	add.f32 	%f1108, %f1109, %f1109;
	mov.f32 	%f1107, 0f3EE66666;
	sub.f32 	%f1106, %f1107, %f1108;
	abs.f32 	%f1105, %f1106;
	setp.lt.f32 	%p66, %f77, 0f00000000;
	setp.eq.f32 	%p67, %f1105, 0f3F800000;
	and.pred  	%p2, %p66, %p67;
	setp.eq.f32 	%p68, %f77, 0f00000000;
	@%p68 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f540, %f77, %f77;
	selp.f32 	%f1174, %f540, 0f00000000, %p67;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r238, %f1172;
	xor.b32  	%r239, %r238, -2147483648;
	mov.b32 	%f536, %r239;
	selp.f32 	%f1174, %f536, %f1172, %p2;
	setp.geu.f32 	%p69, %f77, 0f00000000;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f537, 0f3EE66666;
	cvt.rzi.f32.f32 	%f538, %f537;
	setp.eq.f32 	%p70, %f538, 0f3EE66666;
	@%p70 bra 	$L__BB0_58;

	mov.f32 	%f1174, 0f7FFFFFFF;

$L__BB0_58:
	abs.f32 	%f1111, %f77;
	add.f32 	%f541, %f1111, 0f3EE66666;
	mov.b32 	%r240, %f541;
	setp.lt.s32 	%p72, %r240, 2139095040;
	@%p72 bra 	$L__BB0_63;

	abs.f32 	%f1112, %f77;
	setp.gtu.f32 	%p73, %f1112, 0f7F800000;
	@%p73 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1174, %f77, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	abs.f32 	%f1113, %f77;
	setp.neu.f32 	%p74, %f1113, 0f7F800000;
	@%p74 bra 	$L__BB0_63;

	selp.f32 	%f1174, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p75, %f77, 0f3F800000;
	selp.f32 	%f107, 0f3F800000, %f1174, %p75;
	abs.f32 	%f108, %f78;
	setp.lt.f32 	%p76, %f108, 0f00800000;
	mul.f32 	%f543, %f108, 0f4B800000;
	selp.f32 	%f544, %f543, %f108, %p76;
	selp.f32 	%f545, 0fC3170000, 0fC2FE0000, %p76;
	mov.b32 	%r241, %f544;
	and.b32  	%r242, %r241, 8388607;
	or.b32  	%r243, %r242, 1065353216;
	mov.b32 	%f546, %r243;
	shr.u32 	%r244, %r241, 23;
	cvt.rn.f32.u32 	%f547, %r244;
	add.f32 	%f548, %f545, %f547;
	setp.gt.f32 	%p77, %f546, 0f3FB504F3;
	mul.f32 	%f549, %f546, 0f3F000000;
	add.f32 	%f550, %f548, 0f3F800000;
	selp.f32 	%f551, %f550, %f548, %p77;
	selp.f32 	%f552, %f549, %f546, %p77;
	add.f32 	%f553, %f552, 0fBF800000;
	add.f32 	%f554, %f552, 0f3F800000;
	rcp.approx.ftz.f32 	%f555, %f554;
	add.f32 	%f556, %f553, %f553;
	mul.f32 	%f557, %f556, %f555;
	mul.f32 	%f558, %f557, %f557;
	mov.f32 	%f559, 0f3C4CAF63;
	mov.f32 	%f560, 0f3B18F0FE;
	fma.rn.f32 	%f561, %f560, %f558, %f559;
	mov.f32 	%f562, 0f3DAAAABD;
	fma.rn.f32 	%f563, %f561, %f558, %f562;
	mul.rn.f32 	%f564, %f563, %f558;
	mul.rn.f32 	%f565, %f564, %f557;
	sub.f32 	%f566, %f553, %f557;
	add.f32 	%f567, %f566, %f566;
	neg.f32 	%f568, %f557;
	fma.rn.f32 	%f569, %f568, %f553, %f567;
	mul.rn.f32 	%f570, %f555, %f569;
	add.f32 	%f571, %f565, %f557;
	sub.f32 	%f572, %f557, %f571;
	add.f32 	%f573, %f565, %f572;
	add.f32 	%f574, %f570, %f573;
	add.f32 	%f575, %f571, %f574;
	sub.f32 	%f576, %f571, %f575;
	add.f32 	%f577, %f574, %f576;
	mov.f32 	%f578, 0f3F317200;
	mul.rn.f32 	%f579, %f551, %f578;
	mov.f32 	%f580, 0f35BFBE8E;
	mul.rn.f32 	%f581, %f551, %f580;
	add.f32 	%f582, %f579, %f575;
	sub.f32 	%f583, %f579, %f582;
	add.f32 	%f584, %f575, %f583;
	add.f32 	%f585, %f577, %f584;
	add.f32 	%f586, %f581, %f585;
	add.f32 	%f587, %f582, %f586;
	sub.f32 	%f588, %f582, %f587;
	add.f32 	%f589, %f586, %f588;
	mov.f32 	%f590, 0f3EE66666;
	mul.rn.f32 	%f591, %f590, %f587;
	neg.f32 	%f592, %f591;
	fma.rn.f32 	%f593, %f590, %f587, %f592;
	fma.rn.f32 	%f594, %f590, %f589, %f593;
	mov.f32 	%f595, 0f00000000;
	fma.rn.f32 	%f596, %f595, %f587, %f594;
	add.rn.f32 	%f597, %f591, %f596;
	neg.f32 	%f598, %f597;
	add.rn.f32 	%f599, %f591, %f598;
	add.rn.f32 	%f600, %f599, %f596;
	mov.b32 	%r245, %f597;
	setp.eq.s32 	%p78, %r245, 1118925336;
	add.s32 	%r246, %r245, -1;
	mov.b32 	%f601, %r246;
	add.f32 	%f602, %f600, 0f37000000;
	selp.f32 	%f109, %f602, %f600, %p78;
	selp.f32 	%f603, %f601, %f597, %p78;
	mov.f32 	%f604, 0f3FB8AA3B;
	mul.rn.f32 	%f605, %f603, %f604;
	cvt.rzi.f32.f32 	%f606, %f605;
	abs.f32 	%f607, %f606;
	setp.gt.f32 	%p79, %f607, 0f42FC0000;
	mov.b32 	%r247, %f606;
	and.b32  	%r248, %r247, -2147483648;
	or.b32  	%r249, %r248, 1123811328;
	mov.b32 	%f608, %r249;
	selp.f32 	%f609, %f608, %f606, %p79;
	mov.f32 	%f610, 0fBF317218;
	fma.rn.f32 	%f611, %f609, %f610, %f603;
	mov.f32 	%f612, 0f3102E308;
	fma.rn.f32 	%f613, %f609, %f612, %f611;
	mul.f32 	%f614, %f613, 0f3FB8AA3B;
	add.f32 	%f615, %f609, 0f4B40007F;
	mov.b32 	%r250, %f615;
	shl.b32 	%r251, %r250, 23;
	mov.b32 	%f616, %r251;
	ex2.approx.ftz.f32 	%f617, %f614;
	mul.f32 	%f110, %f617, %f616;
	setp.eq.f32 	%p80, %f110, 0f7F800000;
	mov.f32 	%f1175, 0f7F800000;
	@%p80 bra 	$L__BB0_65;

	fma.rn.f32 	%f1175, %f110, %f109, %f110;

$L__BB0_65:
	setp.lt.f32 	%p81, %f78, 0f00000000;
	and.pred  	%p3, %p81, %p67;
	setp.eq.f32 	%p83, %f78, 0f00000000;
	@%p83 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f622, %f78, %f78;
	selp.f32 	%f1177, %f622, 0f00000000, %p67;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r252, %f1175;
	xor.b32  	%r253, %r252, -2147483648;
	mov.b32 	%f618, %r253;
	selp.f32 	%f1177, %f618, %f1175, %p3;
	setp.geu.f32 	%p84, %f78, 0f00000000;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f619, 0f3EE66666;
	cvt.rzi.f32.f32 	%f620, %f619;
	setp.eq.f32 	%p85, %f620, 0f3EE66666;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f1177, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1114, %f78;
	add.f32 	%f623, %f1114, 0f3EE66666;
	mov.b32 	%r254, %f623;
	setp.lt.s32 	%p87, %r254, 2139095040;
	@%p87 bra 	$L__BB0_75;

	abs.f32 	%f1115, %f78;
	setp.gtu.f32 	%p88, %f1115, 0f7F800000;
	@%p88 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1177, %f78, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1116, %f78;
	setp.neu.f32 	%p89, %f1116, 0f7F800000;
	@%p89 bra 	$L__BB0_75;

	selp.f32 	%f1177, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p90, %f78, 0f3F800000;
	selp.f32 	%f119, 0f3F800000, %f1177, %p90;
	abs.f32 	%f120, %f79;
	setp.lt.f32 	%p91, %f120, 0f00800000;
	mul.f32 	%f625, %f120, 0f4B800000;
	selp.f32 	%f626, %f625, %f120, %p91;
	selp.f32 	%f627, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r255, %f626;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f628, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f629, %r258;
	add.f32 	%f630, %f627, %f629;
	setp.gt.f32 	%p92, %f628, 0f3FB504F3;
	mul.f32 	%f631, %f628, 0f3F000000;
	add.f32 	%f632, %f630, 0f3F800000;
	selp.f32 	%f633, %f632, %f630, %p92;
	selp.f32 	%f634, %f631, %f628, %p92;
	add.f32 	%f635, %f634, 0fBF800000;
	add.f32 	%f636, %f634, 0f3F800000;
	rcp.approx.ftz.f32 	%f637, %f636;
	add.f32 	%f638, %f635, %f635;
	mul.f32 	%f639, %f638, %f637;
	mul.f32 	%f640, %f639, %f639;
	mov.f32 	%f641, 0f3C4CAF63;
	mov.f32 	%f642, 0f3B18F0FE;
	fma.rn.f32 	%f643, %f642, %f640, %f641;
	mov.f32 	%f644, 0f3DAAAABD;
	fma.rn.f32 	%f645, %f643, %f640, %f644;
	mul.rn.f32 	%f646, %f645, %f640;
	mul.rn.f32 	%f647, %f646, %f639;
	sub.f32 	%f648, %f635, %f639;
	add.f32 	%f649, %f648, %f648;
	neg.f32 	%f650, %f639;
	fma.rn.f32 	%f651, %f650, %f635, %f649;
	mul.rn.f32 	%f652, %f637, %f651;
	add.f32 	%f653, %f647, %f639;
	sub.f32 	%f654, %f639, %f653;
	add.f32 	%f655, %f647, %f654;
	add.f32 	%f656, %f652, %f655;
	add.f32 	%f657, %f653, %f656;
	sub.f32 	%f658, %f653, %f657;
	add.f32 	%f659, %f656, %f658;
	mov.f32 	%f660, 0f3F317200;
	mul.rn.f32 	%f661, %f633, %f660;
	mov.f32 	%f662, 0f35BFBE8E;
	mul.rn.f32 	%f663, %f633, %f662;
	add.f32 	%f664, %f661, %f657;
	sub.f32 	%f665, %f661, %f664;
	add.f32 	%f666, %f657, %f665;
	add.f32 	%f667, %f659, %f666;
	add.f32 	%f668, %f663, %f667;
	add.f32 	%f669, %f664, %f668;
	sub.f32 	%f670, %f664, %f669;
	add.f32 	%f671, %f668, %f670;
	mov.f32 	%f672, 0f3EE66666;
	mul.rn.f32 	%f673, %f672, %f669;
	neg.f32 	%f674, %f673;
	fma.rn.f32 	%f675, %f672, %f669, %f674;
	fma.rn.f32 	%f676, %f672, %f671, %f675;
	mov.f32 	%f677, 0f00000000;
	fma.rn.f32 	%f678, %f677, %f669, %f676;
	add.rn.f32 	%f679, %f673, %f678;
	neg.f32 	%f680, %f679;
	add.rn.f32 	%f681, %f673, %f680;
	add.rn.f32 	%f682, %f681, %f678;
	mov.b32 	%r259, %f679;
	setp.eq.s32 	%p93, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f683, %r260;
	add.f32 	%f684, %f682, 0f37000000;
	selp.f32 	%f121, %f684, %f682, %p93;
	selp.f32 	%f685, %f683, %f679, %p93;
	mov.f32 	%f686, 0f3FB8AA3B;
	mul.rn.f32 	%f687, %f685, %f686;
	cvt.rzi.f32.f32 	%f688, %f687;
	abs.f32 	%f689, %f688;
	setp.gt.f32 	%p94, %f689, 0f42FC0000;
	mov.b32 	%r261, %f688;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f690, %r263;
	selp.f32 	%f691, %f690, %f688, %p94;
	mov.f32 	%f692, 0fBF317218;
	fma.rn.f32 	%f693, %f691, %f692, %f685;
	mov.f32 	%f694, 0f3102E308;
	fma.rn.f32 	%f695, %f691, %f694, %f693;
	mul.f32 	%f696, %f695, 0f3FB8AA3B;
	add.f32 	%f697, %f691, 0f4B40007F;
	mov.b32 	%r264, %f697;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f698, %r265;
	ex2.approx.ftz.f32 	%f699, %f696;
	mul.f32 	%f122, %f699, %f698;
	setp.eq.f32 	%p95, %f122, 0f7F800000;
	mov.f32 	%f1178, 0f7F800000;
	@%p95 bra 	$L__BB0_77;

	fma.rn.f32 	%f1178, %f122, %f121, %f122;

$L__BB0_77:
	setp.lt.f32 	%p96, %f79, 0f00000000;
	and.pred  	%p4, %p96, %p67;
	setp.eq.f32 	%p98, %f79, 0f00000000;
	@%p98 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f704, %f79, %f79;
	selp.f32 	%f1180, %f704, 0f00000000, %p67;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r266, %f1178;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f700, %r267;
	selp.f32 	%f1180, %f700, %f1178, %p4;
	setp.geu.f32 	%p99, %f79, 0f00000000;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f701, 0f3EE66666;
	cvt.rzi.f32.f32 	%f702, %f701;
	setp.eq.f32 	%p100, %f702, 0f3EE66666;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f1180, 0f7FFFFFFF;

$L__BB0_82:
	abs.f32 	%f1117, %f79;
	add.f32 	%f705, %f1117, 0f3EE66666;
	mov.b32 	%r268, %f705;
	setp.lt.s32 	%p102, %r268, 2139095040;
	@%p102 bra 	$L__BB0_87;

	abs.f32 	%f1118, %f79;
	setp.gtu.f32 	%p103, %f1118, 0f7F800000;
	@%p103 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1180, %f79, 0f3EE66666;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	abs.f32 	%f1119, %f79;
	setp.neu.f32 	%p104, %f1119, 0f7F800000;
	@%p104 bra 	$L__BB0_87;

	selp.f32 	%f1180, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	setp.eq.f32 	%p105, %f79, 0f3F800000;
	mov.f32 	%f707, 0f3F800000;
	selp.f32 	%f708, 0f3F800000, %f1180, %p105;
	min.f32 	%f709, %f107, %f707;
	mov.f32 	%f710, 0f00000000;
	max.f32 	%f131, %f710, %f709;
	min.f32 	%f711, %f119, %f707;
	max.f32 	%f132, %f710, %f711;
	min.f32 	%f712, %f708, %f707;
	max.f32 	%f133, %f710, %f712;
	mov.f32 	%f716, 0f3ED55555;
	abs.f32 	%f135, %f131;
	setp.lt.f32 	%p106, %f135, 0f00800000;
	mul.f32 	%f718, %f135, 0f4B800000;
	selp.f32 	%f719, %f718, %f135, %p106;
	selp.f32 	%f720, 0fC3170000, 0fC2FE0000, %p106;
	mov.b32 	%r271, %f719;
	and.b32  	%r272, %r271, 8388607;
	or.b32  	%r273, %r272, 1065353216;
	mov.b32 	%f721, %r273;
	shr.u32 	%r274, %r271, 23;
	cvt.rn.f32.u32 	%f722, %r274;
	add.f32 	%f723, %f720, %f722;
	setp.gt.f32 	%p107, %f721, 0f3FB504F3;
	mul.f32 	%f724, %f721, 0f3F000000;
	add.f32 	%f725, %f723, 0f3F800000;
	selp.f32 	%f726, %f725, %f723, %p107;
	selp.f32 	%f727, %f724, %f721, %p107;
	add.f32 	%f728, %f727, 0fBF800000;
	add.f32 	%f729, %f727, 0f3F800000;
	rcp.approx.ftz.f32 	%f730, %f729;
	add.f32 	%f731, %f728, %f728;
	mul.f32 	%f732, %f731, %f730;
	mul.f32 	%f733, %f732, %f732;
	mov.f32 	%f734, 0f3C4CAF63;
	mov.f32 	%f735, 0f3B18F0FE;
	fma.rn.f32 	%f736, %f735, %f733, %f734;
	mov.f32 	%f737, 0f3DAAAABD;
	fma.rn.f32 	%f738, %f736, %f733, %f737;
	mul.rn.f32 	%f739, %f738, %f733;
	mul.rn.f32 	%f740, %f739, %f732;
	sub.f32 	%f741, %f728, %f732;
	add.f32 	%f742, %f741, %f741;
	neg.f32 	%f743, %f732;
	fma.rn.f32 	%f744, %f743, %f728, %f742;
	mul.rn.f32 	%f745, %f730, %f744;
	add.f32 	%f746, %f740, %f732;
	sub.f32 	%f747, %f732, %f746;
	add.f32 	%f748, %f740, %f747;
	add.f32 	%f749, %f745, %f748;
	add.f32 	%f750, %f746, %f749;
	sub.f32 	%f751, %f746, %f750;
	add.f32 	%f752, %f749, %f751;
	mov.f32 	%f753, 0f3F317200;
	mul.rn.f32 	%f754, %f726, %f753;
	mov.f32 	%f755, 0f35BFBE8E;
	mul.rn.f32 	%f756, %f726, %f755;
	add.f32 	%f757, %f754, %f750;
	sub.f32 	%f758, %f754, %f757;
	add.f32 	%f759, %f750, %f758;
	add.f32 	%f760, %f752, %f759;
	add.f32 	%f761, %f756, %f760;
	add.f32 	%f762, %f757, %f761;
	sub.f32 	%f763, %f757, %f762;
	add.f32 	%f764, %f761, %f763;
	mul.rn.f32 	%f765, %f716, %f762;
	neg.f32 	%f766, %f765;
	fma.rn.f32 	%f767, %f716, %f762, %f766;
	fma.rn.f32 	%f768, %f716, %f764, %f767;
	fma.rn.f32 	%f769, %f710, %f762, %f768;
	add.rn.f32 	%f770, %f765, %f769;
	neg.f32 	%f771, %f770;
	add.rn.f32 	%f772, %f765, %f771;
	add.rn.f32 	%f773, %f772, %f769;
	mov.b32 	%r275, %f770;
	setp.eq.s32 	%p108, %r275, 1118925336;
	add.s32 	%r276, %r275, -1;
	mov.b32 	%f774, %r276;
	add.f32 	%f775, %f773, 0f37000000;
	selp.f32 	%f136, %f775, %f773, %p108;
	selp.f32 	%f776, %f774, %f770, %p108;
	mov.f32 	%f777, 0f3FB8AA3B;
	mul.rn.f32 	%f778, %f776, %f777;
	cvt.rzi.f32.f32 	%f779, %f778;
	abs.f32 	%f780, %f779;
	setp.gt.f32 	%p109, %f780, 0f42FC0000;
	mov.b32 	%r277, %f779;
	and.b32  	%r278, %r277, -2147483648;
	or.b32  	%r279, %r278, 1123811328;
	mov.b32 	%f781, %r279;
	selp.f32 	%f782, %f781, %f779, %p109;
	mov.f32 	%f783, 0fBF317218;
	fma.rn.f32 	%f784, %f782, %f783, %f776;
	mov.f32 	%f785, 0f3102E308;
	fma.rn.f32 	%f786, %f782, %f785, %f784;
	mul.f32 	%f787, %f786, 0f3FB8AA3B;
	add.f32 	%f788, %f782, 0f4B40007F;
	mov.b32 	%r280, %f788;
	shl.b32 	%r281, %r280, 23;
	mov.b32 	%f789, %r281;
	ex2.approx.ftz.f32 	%f790, %f787;
	mul.f32 	%f137, %f790, %f789;
	setp.eq.f32 	%p110, %f137, 0f7F800000;
	mov.f32 	%f1181, 0f7F800000;
	@%p110 bra 	$L__BB0_89;

	fma.rn.f32 	%f1181, %f137, %f136, %f137;

$L__BB0_89:
	mov.f32 	%f1130, 0f00000000;
	max.f32 	%f1129, %f1130, %f709;
	mov.f32 	%f1094, 0f3E555555;
	cvt.rzi.f32.f32 	%f1093, %f1094;
	add.f32 	%f1092, %f1093, %f1093;
	mov.f32 	%f1091, 0f3ED55555;
	sub.f32 	%f1090, %f1091, %f1092;
	abs.f32 	%f1089, %f1090;
	setp.lt.f32 	%p111, %f1129, 0f00000000;
	setp.eq.f32 	%p112, %f1089, 0f3F800000;
	and.pred  	%p5, %p111, %p112;
	setp.eq.f32 	%p113, %f1129, 0f00000000;
	@%p113 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	mov.f32 	%f1147, 0f00000000;
	max.f32 	%f1146, %f1147, %f709;
	add.f32 	%f795, %f1146, %f1146;
	selp.f32 	%f1183, %f795, 0f00000000, %p112;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.f32 	%f1132, 0f00000000;
	max.f32 	%f1131, %f1132, %f709;
	mov.b32 	%r282, %f1181;
	xor.b32  	%r283, %r282, -2147483648;
	mov.b32 	%f791, %r283;
	selp.f32 	%f1183, %f791, %f1181, %p5;
	setp.geu.f32 	%p114, %f1131, 0f00000000;
	@%p114 bra 	$L__BB0_94;

	mov.f32 	%f792, 0f3ED55555;
	cvt.rzi.f32.f32 	%f793, %f792;
	setp.eq.f32 	%p115, %f793, 0f3ED55555;
	@%p115 bra 	$L__BB0_94;

	mov.f32 	%f1183, 0f7FFFFFFF;

$L__BB0_94:
	mov.f32 	%f1135, 0f00000000;
	max.f32 	%f1134, %f1135, %f709;
	abs.f32 	%f1133, %f1134;
	add.f32 	%f796, %f1133, 0f3ED55555;
	mov.b32 	%r284, %f796;
	setp.lt.s32 	%p117, %r284, 2139095040;
	@%p117 bra 	$L__BB0_99;

	mov.f32 	%f1140, 0f00000000;
	max.f32 	%f1139, %f1140, %f709;
	abs.f32 	%f1138, %f1139;
	setp.gtu.f32 	%p118, %f1138, 0f7F800000;
	@%p118 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	mov.f32 	%f1145, 0f00000000;
	max.f32 	%f1144, %f1145, %f709;
	add.f32 	%f1183, %f1144, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	mov.f32 	%f1143, 0f00000000;
	max.f32 	%f1142, %f1143, %f709;
	abs.f32 	%f1141, %f1142;
	setp.neu.f32 	%p119, %f1141, 0f7F800000;
	@%p119 bra 	$L__BB0_99;

	selp.f32 	%f1183, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f146, %f132;
	setp.lt.f32 	%p120, %f146, 0f00800000;
	mul.f32 	%f798, %f146, 0f4B800000;
	selp.f32 	%f799, %f798, %f146, %p120;
	selp.f32 	%f800, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r285, %f799;
	and.b32  	%r286, %r285, 8388607;
	or.b32  	%r287, %r286, 1065353216;
	mov.b32 	%f801, %r287;
	shr.u32 	%r288, %r285, 23;
	cvt.rn.f32.u32 	%f802, %r288;
	add.f32 	%f803, %f800, %f802;
	setp.gt.f32 	%p121, %f801, 0f3FB504F3;
	mul.f32 	%f804, %f801, 0f3F000000;
	add.f32 	%f805, %f803, 0f3F800000;
	selp.f32 	%f806, %f805, %f803, %p121;
	selp.f32 	%f807, %f804, %f801, %p121;
	add.f32 	%f808, %f807, 0fBF800000;
	add.f32 	%f809, %f807, 0f3F800000;
	rcp.approx.ftz.f32 	%f810, %f809;
	add.f32 	%f811, %f808, %f808;
	mul.f32 	%f812, %f811, %f810;
	mul.f32 	%f813, %f812, %f812;
	mov.f32 	%f814, 0f3C4CAF63;
	mov.f32 	%f815, 0f3B18F0FE;
	fma.rn.f32 	%f816, %f815, %f813, %f814;
	mov.f32 	%f817, 0f3DAAAABD;
	fma.rn.f32 	%f818, %f816, %f813, %f817;
	mul.rn.f32 	%f819, %f818, %f813;
	mul.rn.f32 	%f820, %f819, %f812;
	sub.f32 	%f821, %f808, %f812;
	add.f32 	%f822, %f821, %f821;
	neg.f32 	%f823, %f812;
	fma.rn.f32 	%f824, %f823, %f808, %f822;
	mul.rn.f32 	%f825, %f810, %f824;
	add.f32 	%f826, %f820, %f812;
	sub.f32 	%f827, %f812, %f826;
	add.f32 	%f828, %f820, %f827;
	add.f32 	%f829, %f825, %f828;
	add.f32 	%f830, %f826, %f829;
	sub.f32 	%f831, %f826, %f830;
	add.f32 	%f832, %f829, %f831;
	mov.f32 	%f833, 0f3F317200;
	mul.rn.f32 	%f834, %f806, %f833;
	mov.f32 	%f835, 0f35BFBE8E;
	mul.rn.f32 	%f836, %f806, %f835;
	add.f32 	%f837, %f834, %f830;
	sub.f32 	%f838, %f834, %f837;
	add.f32 	%f839, %f830, %f838;
	add.f32 	%f840, %f832, %f839;
	add.f32 	%f841, %f836, %f840;
	add.f32 	%f842, %f837, %f841;
	sub.f32 	%f843, %f837, %f842;
	add.f32 	%f844, %f841, %f843;
	mov.f32 	%f845, 0f3ED55555;
	mul.rn.f32 	%f846, %f845, %f842;
	neg.f32 	%f847, %f846;
	fma.rn.f32 	%f848, %f845, %f842, %f847;
	fma.rn.f32 	%f849, %f845, %f844, %f848;
	mov.f32 	%f850, 0f00000000;
	fma.rn.f32 	%f851, %f850, %f842, %f849;
	add.rn.f32 	%f852, %f846, %f851;
	neg.f32 	%f853, %f852;
	add.rn.f32 	%f854, %f846, %f853;
	add.rn.f32 	%f855, %f854, %f851;
	mov.b32 	%r289, %f852;
	setp.eq.s32 	%p122, %r289, 1118925336;
	add.s32 	%r290, %r289, -1;
	mov.b32 	%f856, %r290;
	add.f32 	%f857, %f855, 0f37000000;
	selp.f32 	%f147, %f857, %f855, %p122;
	selp.f32 	%f858, %f856, %f852, %p122;
	mov.f32 	%f859, 0f3FB8AA3B;
	mul.rn.f32 	%f860, %f858, %f859;
	cvt.rzi.f32.f32 	%f861, %f860;
	abs.f32 	%f862, %f861;
	setp.gt.f32 	%p123, %f862, 0f42FC0000;
	mov.b32 	%r291, %f861;
	and.b32  	%r292, %r291, -2147483648;
	or.b32  	%r293, %r292, 1123811328;
	mov.b32 	%f863, %r293;
	selp.f32 	%f864, %f863, %f861, %p123;
	mov.f32 	%f865, 0fBF317218;
	fma.rn.f32 	%f866, %f864, %f865, %f858;
	mov.f32 	%f867, 0f3102E308;
	fma.rn.f32 	%f868, %f864, %f867, %f866;
	mul.f32 	%f869, %f868, 0f3FB8AA3B;
	add.f32 	%f870, %f864, 0f4B40007F;
	mov.b32 	%r294, %f870;
	shl.b32 	%r295, %r294, 23;
	mov.b32 	%f871, %r295;
	ex2.approx.ftz.f32 	%f872, %f869;
	mul.f32 	%f148, %f872, %f871;
	setp.eq.f32 	%p124, %f148, 0f7F800000;
	mov.f32 	%f1184, 0f7F800000;
	@%p124 bra 	$L__BB0_101;

	fma.rn.f32 	%f1184, %f148, %f147, %f148;

$L__BB0_101:
	setp.lt.f32 	%p125, %f132, 0f00000000;
	and.pred  	%p6, %p125, %p112;
	setp.eq.f32 	%p127, %f132, 0f00000000;
	@%p127 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f877, %f132, %f132;
	selp.f32 	%f1186, %f877, 0f00000000, %p112;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r296, %f1184;
	xor.b32  	%r297, %r296, -2147483648;
	mov.b32 	%f873, %r297;
	selp.f32 	%f1186, %f873, %f1184, %p6;
	setp.geu.f32 	%p128, %f132, 0f00000000;
	@%p128 bra 	$L__BB0_106;

	mov.f32 	%f874, 0f3ED55555;
	cvt.rzi.f32.f32 	%f875, %f874;
	setp.eq.f32 	%p129, %f875, 0f3ED55555;
	@%p129 bra 	$L__BB0_106;

	mov.f32 	%f1186, 0f7FFFFFFF;

$L__BB0_106:
	mov.f32 	%f1122, 0f00000000;
	max.f32 	%f1121, %f1122, %f711;
	abs.f32 	%f1120, %f1121;
	add.f32 	%f878, %f1120, 0f3ED55555;
	mov.b32 	%r298, %f878;
	setp.lt.s32 	%p131, %r298, 2139095040;
	@%p131 bra 	$L__BB0_111;

	mov.f32 	%f1125, 0f00000000;
	max.f32 	%f1124, %f1125, %f711;
	abs.f32 	%f1123, %f1124;
	setp.gtu.f32 	%p132, %f1123, 0f7F800000;
	@%p132 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1186, %f132, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	mov.f32 	%f1128, 0f00000000;
	max.f32 	%f1127, %f1128, %f711;
	abs.f32 	%f1126, %f1127;
	setp.neu.f32 	%p133, %f1126, 0f7F800000;
	@%p133 bra 	$L__BB0_111;

	selp.f32 	%f1186, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	abs.f32 	%f157, %f133;
	setp.lt.f32 	%p134, %f157, 0f00800000;
	mul.f32 	%f880, %f157, 0f4B800000;
	selp.f32 	%f881, %f880, %f157, %p134;
	selp.f32 	%f882, 0fC3170000, 0fC2FE0000, %p134;
	mov.b32 	%r299, %f881;
	and.b32  	%r300, %r299, 8388607;
	or.b32  	%r301, %r300, 1065353216;
	mov.b32 	%f883, %r301;
	shr.u32 	%r302, %r299, 23;
	cvt.rn.f32.u32 	%f884, %r302;
	add.f32 	%f885, %f882, %f884;
	setp.gt.f32 	%p135, %f883, 0f3FB504F3;
	mul.f32 	%f886, %f883, 0f3F000000;
	add.f32 	%f887, %f885, 0f3F800000;
	selp.f32 	%f888, %f887, %f885, %p135;
	selp.f32 	%f889, %f886, %f883, %p135;
	add.f32 	%f890, %f889, 0fBF800000;
	add.f32 	%f891, %f889, 0f3F800000;
	rcp.approx.ftz.f32 	%f892, %f891;
	add.f32 	%f893, %f890, %f890;
	mul.f32 	%f894, %f893, %f892;
	mul.f32 	%f895, %f894, %f894;
	mov.f32 	%f896, 0f3C4CAF63;
	mov.f32 	%f897, 0f3B18F0FE;
	fma.rn.f32 	%f898, %f897, %f895, %f896;
	mov.f32 	%f899, 0f3DAAAABD;
	fma.rn.f32 	%f900, %f898, %f895, %f899;
	mul.rn.f32 	%f901, %f900, %f895;
	mul.rn.f32 	%f902, %f901, %f894;
	sub.f32 	%f903, %f890, %f894;
	add.f32 	%f904, %f903, %f903;
	neg.f32 	%f905, %f894;
	fma.rn.f32 	%f906, %f905, %f890, %f904;
	mul.rn.f32 	%f907, %f892, %f906;
	add.f32 	%f908, %f902, %f894;
	sub.f32 	%f909, %f894, %f908;
	add.f32 	%f910, %f902, %f909;
	add.f32 	%f911, %f907, %f910;
	add.f32 	%f912, %f908, %f911;
	sub.f32 	%f913, %f908, %f912;
	add.f32 	%f914, %f911, %f913;
	mov.f32 	%f915, 0f3F317200;
	mul.rn.f32 	%f916, %f888, %f915;
	mov.f32 	%f917, 0f35BFBE8E;
	mul.rn.f32 	%f918, %f888, %f917;
	add.f32 	%f919, %f916, %f912;
	sub.f32 	%f920, %f916, %f919;
	add.f32 	%f921, %f912, %f920;
	add.f32 	%f922, %f914, %f921;
	add.f32 	%f923, %f918, %f922;
	add.f32 	%f924, %f919, %f923;
	sub.f32 	%f925, %f919, %f924;
	add.f32 	%f926, %f923, %f925;
	mov.f32 	%f927, 0f3ED55555;
	mul.rn.f32 	%f928, %f927, %f924;
	neg.f32 	%f929, %f928;
	fma.rn.f32 	%f930, %f927, %f924, %f929;
	fma.rn.f32 	%f931, %f927, %f926, %f930;
	mov.f32 	%f932, 0f00000000;
	fma.rn.f32 	%f933, %f932, %f924, %f931;
	add.rn.f32 	%f934, %f928, %f933;
	neg.f32 	%f935, %f934;
	add.rn.f32 	%f936, %f928, %f935;
	add.rn.f32 	%f937, %f936, %f933;
	mov.b32 	%r303, %f934;
	setp.eq.s32 	%p136, %r303, 1118925336;
	add.s32 	%r304, %r303, -1;
	mov.b32 	%f938, %r304;
	add.f32 	%f939, %f937, 0f37000000;
	selp.f32 	%f158, %f939, %f937, %p136;
	selp.f32 	%f940, %f938, %f934, %p136;
	mov.f32 	%f941, 0f3FB8AA3B;
	mul.rn.f32 	%f942, %f940, %f941;
	cvt.rzi.f32.f32 	%f943, %f942;
	abs.f32 	%f944, %f943;
	setp.gt.f32 	%p137, %f944, 0f42FC0000;
	mov.b32 	%r305, %f943;
	and.b32  	%r306, %r305, -2147483648;
	or.b32  	%r307, %r306, 1123811328;
	mov.b32 	%f945, %r307;
	selp.f32 	%f946, %f945, %f943, %p137;
	mov.f32 	%f947, 0fBF317218;
	fma.rn.f32 	%f948, %f946, %f947, %f940;
	mov.f32 	%f949, 0f3102E308;
	fma.rn.f32 	%f950, %f946, %f949, %f948;
	mul.f32 	%f951, %f950, 0f3FB8AA3B;
	add.f32 	%f952, %f946, 0f4B40007F;
	mov.b32 	%r308, %f952;
	shl.b32 	%r309, %r308, 23;
	mov.b32 	%f953, %r309;
	ex2.approx.ftz.f32 	%f954, %f951;
	mul.f32 	%f159, %f954, %f953;
	setp.eq.f32 	%p138, %f159, 0f7F800000;
	mov.f32 	%f1187, 0f7F800000;
	@%p138 bra 	$L__BB0_113;

	fma.rn.f32 	%f1187, %f159, %f158, %f159;

$L__BB0_113:
	setp.lt.f32 	%p139, %f133, 0f00000000;
	and.pred  	%p7, %p139, %p112;
	setp.eq.f32 	%p141, %f133, 0f00000000;
	@%p141 bra 	$L__BB0_117;
	bra.uni 	$L__BB0_114;

$L__BB0_117:
	add.f32 	%f959, %f133, %f133;
	selp.f32 	%f1189, %f959, 0f00000000, %p112;
	bra.uni 	$L__BB0_118;

$L__BB0_114:
	mov.b32 	%r310, %f1187;
	xor.b32  	%r311, %r310, -2147483648;
	mov.b32 	%f955, %r311;
	selp.f32 	%f1189, %f955, %f1187, %p7;
	setp.geu.f32 	%p142, %f133, 0f00000000;
	@%p142 bra 	$L__BB0_118;

	mov.f32 	%f956, 0f3ED55555;
	cvt.rzi.f32.f32 	%f957, %f956;
	setp.eq.f32 	%p143, %f957, 0f3ED55555;
	@%p143 bra 	$L__BB0_118;

	mov.f32 	%f1189, 0f7FFFFFFF;

$L__BB0_118:
	add.f32 	%f960, %f157, 0f3ED55555;
	mov.b32 	%r312, %f960;
	setp.lt.s32 	%p145, %r312, 2139095040;
	@%p145 bra 	$L__BB0_123;

	setp.gtu.f32 	%p146, %f157, 0f7F800000;
	@%p146 bra 	$L__BB0_122;
	bra.uni 	$L__BB0_120;

$L__BB0_122:
	add.f32 	%f1189, %f133, 0f3ED55555;
	bra.uni 	$L__BB0_123;

$L__BB0_120:
	setp.neu.f32 	%p147, %f157, 0f7F800000;
	@%p147 bra 	$L__BB0_123;

	selp.f32 	%f1189, 0fFF800000, 0f7F800000, %p7;

$L__BB0_123:
	mov.f32 	%f1137, 0f00000000;
	max.f32 	%f1136, %f1137, %f709;
	ld.const.u64 	%rd113, [params+144];
	cvta.to.global.u64 	%rd112, %rd113;
	ld.const.u32 	%r351, [params+136];
	mad.lo.s32 	%r350, %r351, %r4, %r3;
	cvt.u64.u32 	%rd111, %r350;
	fma.rn.f32 	%f961, %f1183, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p148, %f1136, 0f3F800000;
	mov.f32 	%f962, 0f3F800000;
	selp.f32 	%f963, 0f3F7FFFFF, %f961, %p148;
	mul.f32 	%f964, %f1136, 0f414EB852;
	setp.lt.f32 	%p149, %f1136, 0f3B4D2E1C;
	selp.f32 	%f965, %f964, %f963, %p149;
	fma.rn.f32 	%f966, %f1186, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p150, %f132, 0f3F800000;
	selp.f32 	%f967, 0f3F7FFFFF, %f966, %p150;
	mul.f32 	%f968, %f132, 0f414EB852;
	setp.lt.f32 	%p151, %f132, 0f3B4D2E1C;
	selp.f32 	%f969, %f968, %f967, %p151;
	fma.rn.f32 	%f970, %f1189, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p152, %f133, 0f3F800000;
	selp.f32 	%f971, 0f3F7FFFFF, %f970, %p152;
	mul.f32 	%f972, %f133, 0f414EB852;
	setp.lt.f32 	%p153, %f133, 0f3B4D2E1C;
	selp.f32 	%f973, %f972, %f971, %p153;
	min.f32 	%f974, %f965, %f962;
	mov.f32 	%f975, 0f00000000;
	max.f32 	%f976, %f975, %f974;
	mul.f32 	%f977, %f976, 0f43800000;
	cvt.rzi.u32.f32 	%r313, %f977;
	min.u32 	%r314, %r313, 255;
	min.f32 	%f978, %f969, %f962;
	max.f32 	%f979, %f975, %f978;
	mul.f32 	%f980, %f979, 0f43800000;
	cvt.rzi.u32.f32 	%r315, %f980;
	min.u32 	%r316, %r315, 255;
	min.f32 	%f981, %f973, %f962;
	max.f32 	%f982, %f975, %f981;
	mul.f32 	%f983, %f982, 0f43800000;
	cvt.rzi.u32.f32 	%r317, %f983;
	min.u32 	%r318, %r317, 255;
	shl.b64 	%rd71, %rd111, 2;
	add.s64 	%rd72, %rd112, %rd71;
	cvt.u16.u32 	%rs19, %r318;
	cvt.u16.u32 	%rs20, %r316;
	cvt.u16.u32 	%rs21, %r314;
	mov.u16 	%rs22, 255;
	st.global.v4.u8 	[%rd72], {%rs21, %rs20, %rs19, %rs22};

$L__BB0_124:
	ld.const.u32 	%r352, [params+104];
	and.b32  	%r319, %r352, 4;
	setp.eq.s32 	%p154, %r319, 0;
	ld.const.u32 	%r367, [params+108];
	@%p154 bra 	$L__BB0_128;

	setp.eq.s32 	%p155, %r367, 0;
	ld.const.u64 	%rd73, [params+224];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r4, %r3;
	mul.wide.u32 	%rd75, %r321, 8;
	add.s64 	%rd20, %rd74, %rd75;
	@%p155 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs30, %rs31, %rs32, %rs33}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f984, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f985, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f986, %rs32;}

	// end inline asm
	add.f32 	%f987, %f77, %f984;
	add.f32 	%f988, %f78, %f985;
	add.f32 	%f989, %f79, %f986;
	mov.f32 	%f990, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f989;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f988;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f987;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f990;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs26, %rs27, %rs28, %rs29};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f994, 0f3F800000;
	mov.u32 	%r367, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f994;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f79;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f78;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f77;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs34, %rs35, %rs36, %rs37};

$L__BB0_128:
	ld.const.u64 	%rd76, [params+256];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r323, [params+248];
	mad.lo.s32 	%r324, %r323, %r4, %r3;
	mul.wide.u32 	%rd78, %r324, 8;
	add.s64 	%rd21, %rd77, %rd78;
	setp.eq.s32 	%p156, %r367, 0;
	@%p156 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs45, %rs46, %rs47, %rs48}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f995, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f997, %rs47;}

	// end inline asm
	add.f32 	%f998, %f80, %f995;
	add.f32 	%f999, %f81, %f996;
	add.f32 	%f1000, %f82, %f997;
	mov.f32 	%f1001, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1000;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1001;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs41, %rs42, %rs43, %rs44};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f1005, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f1005;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f82;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f81;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f80;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs49, %rs50, %rs51, %rs52};

$L__BB0_131:
	mul.f32 	%f1006, %f191, 0f3F000000;
	mov.f32 	%f1007, 0f3F000000;
	sub.f32 	%f168, %f1007, %f1006;
	mul.f32 	%f1008, %f192, 0f3F000000;
	sub.f32 	%f169, %f1007, %f1008;
	mul.f32 	%f1009, %f193, 0f3F000000;
	sub.f32 	%f170, %f1007, %f1009;
	ld.const.u64 	%rd79, [params+272];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r325, [params+264];
	mad.lo.s32 	%r326, %r325, %r4, %r3;
	mul.wide.u32 	%rd81, %r326, 8;
	add.s64 	%rd22, %rd80, %rd81;
	@%p156 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs60, %rs61, %rs62, %rs63}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1010, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1011, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1012, %rs62;}

	// end inline asm
	add.f32 	%f1013, %f168, %f1010;
	add.f32 	%f1014, %f168, %f1011;
	add.f32 	%f1015, %f168, %f1012;
	mov.f32 	%f1016, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1015;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1014;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1013;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1016;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs56, %rs57, %rs58, %rs59};
	bra.uni 	$L__BB0_134;

$L__BB0_133:
	mov.f32 	%f1020, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f1020;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f168;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs64, %rs65, %rs66, %rs67};

$L__BB0_134:
	ld.const.u64 	%rd82, [params+288];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r327, [params+280];
	mad.lo.s32 	%r328, %r327, %r4, %r3;
	mul.wide.u32 	%rd84, %r328, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p156 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs75, %rs76, %rs77, %rs78}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1021, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1022, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1023, %rs77;}

	// end inline asm
	add.f32 	%f1024, %f169, %f1021;
	add.f32 	%f1025, %f169, %f1022;
	add.f32 	%f1026, %f169, %f1023;
	mov.f32 	%f1027, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1025;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1024;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1027;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs71, %rs72, %rs73, %rs74};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1031, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f169;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f169;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f169;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs79, %rs80, %rs81, %rs82};

$L__BB0_137:
	ld.const.u64 	%rd85, [params+304];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r329, [params+296];
	mad.lo.s32 	%r330, %r329, %r4, %r3;
	mul.wide.u32 	%rd87, %r330, 8;
	add.s64 	%rd24, %rd86, %rd87;
	@%p156 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs90, %rs91, %rs92, %rs93}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1032, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1033, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1034, %rs92;}

	// end inline asm
	add.f32 	%f1035, %f170, %f1032;
	add.f32 	%f1036, %f170, %f1033;
	add.f32 	%f1037, %f170, %f1034;
	mov.f32 	%f1038, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1037;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1036;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1038;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs86, %rs87, %rs88, %rs89};
	bra.uni 	$L__BB0_160;

$L__BB0_139:
	mov.f32 	%f1042, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1042;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f170;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f170;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f170;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs94, %rs95, %rs96, %rs97};

$L__BB0_160:
	ret;

}