//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<234>;
	.reg .b16 	%rs<203>;
	.reg .f32 	%f<1857>;
	.reg .b32 	%r<1541>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<135>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r64), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r65), _optix_get_launch_index_y, ();
	// end inline asm
	// begin inline asm
	call (%r67), _optix_get_launch_dimension_x, ();
	// end inline asm
	// begin inline asm
	call (%r68), _optix_get_launch_dimension_y, ();
	// end inline asm
	ld.const.u64 	%rd31, [params+400];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r70, [params+392];
	mad.lo.s32 	%r71, %r70, %r65, %r64;
	mul.wide.u32 	%rd33, %r71, 4;
	add.s64 	%rd2, %rd32, %rd33;
	ld.global.v2.u8 	{%rs15, %rs194}, [%rd2];
	or.b16  	%rs17, %rs15, %rs194;
	and.b16  	%rs18, %rs17, 255;
	setp.eq.s16 	%p8, %rs18, 0;
	@%p8 bra 	$L__BB0_2;

	ld.global.u8 	%rs193, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs193, [%rd2+2];
	setp.eq.s16 	%p9, %rs193, 0;
	mov.f32 	%f1776, 0f00000000;
	mov.u16 	%rs194, 0;
	mov.f32 	%f1777, %f1776;
	mov.f32 	%f1778, %f1776;
	@%p9 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f277, %rs15;
	div.rn.f32 	%f278, %f277, 0f437F0000;
	fma.rn.f32 	%f279, %f278, 0f40000000, 0fBF800000;
	and.b16  	%rs21, %rs194, 255;
	cvt.rn.f32.u16 	%f280, %rs21;
	div.rn.f32 	%f281, %f280, 0f437F0000;
	fma.rn.f32 	%f282, %f281, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f283, %rs193;
	div.rn.f32 	%f284, %f283, 0f437F0000;
	fma.rn.f32 	%f285, %f284, 0f40000000, 0fBF800000;
	mul.f32 	%f286, %f282, %f282;
	fma.rn.f32 	%f287, %f279, %f279, %f286;
	fma.rn.f32 	%f288, %f285, %f285, %f287;
	sqrt.rn.f32 	%f289, %f288;
	rcp.rn.f32 	%f290, %f289;
	mul.f32 	%f1778, %f290, %f285;
	mul.f32 	%f1777, %f290, %f282;
	mul.f32 	%f1776, %f279, %f290;

$L__BB0_4:
	ld.const.v2.u32 	{%r72, %r73}, [params];
	add.s32 	%r5, %r72, %r64;
	add.s32 	%r6, %r73, %r65;
	setp.eq.f32 	%p10, %f1776, 0f00000000;
	setp.eq.f32 	%p11, %f1777, 0f00000000;
	and.pred  	%p12, %p10, %p11;
	setp.eq.f32 	%p13, %f1778, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	@%p14 bra 	$L__BB0_158;
	bra.uni 	$L__BB0_5;

$L__BB0_158:
	ld.const.u32 	%r61, [params+104];
	and.b32  	%r1509, %r61, 1;
	setp.eq.b32 	%p223, %r1509, 1;
	mov.pred 	%p224, 0;
	xor.pred  	%p225, %p223, %p224;
	not.pred 	%p226, %p225;
	@%p226 bra 	$L__BB0_160;

	ld.const.u64 	%rd107, [params+144];
	cvta.to.global.u64 	%rd108, %rd107;
	ld.const.u32 	%r1510, [params+136];
	mad.lo.s32 	%r1511, %r1510, %r6, %r5;
	mul.wide.u32 	%rd109, %r1511, 4;
	add.s64 	%rd110, %rd108, %rd109;
	mov.u16 	%rs115, 0;
	st.global.v4.u8 	[%rd110], {%rs115, %rs115, %rs115, %rs115};

$L__BB0_160:
	and.b32  	%r1512, %r61, 8;
	setp.eq.s32 	%p227, %r1512, 0;
	@%p227 bra 	$L__BB0_162;

	ld.const.u64 	%rd111, [params+192];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r1513, [params+184];
	mad.lo.s32 	%r1514, %r1513, %r6, %r5;
	mov.f32 	%f1729, 0f00000000;
	cvt.rzi.u32.f32 	%r1515, %f1729;
	mul.wide.u32 	%rd113, %r1514, 2;
	add.s64 	%rd114, %rd112, %rd113;
	mov.u16 	%rs116, 0;
	cvt.u16.u32 	%rs117, %r1515;
	st.global.v2.u8 	[%rd114], {%rs117, %rs116};

$L__BB0_162:
	and.b32  	%r1516, %r61, 4;
	setp.eq.s32 	%p228, %r1516, 0;
	ld.const.u32 	%r1540, [params+108];
	@%p228 bra 	$L__BB0_166;

	setp.eq.s32 	%p229, %r1540, 0;
	ld.const.u64 	%rd115, [params+224];
	cvta.to.global.u64 	%rd116, %rd115;
	ld.const.u32 	%r1517, [params+216];
	mad.lo.s32 	%r1518, %r1517, %r6, %r5;
	mul.wide.u32 	%rd117, %r1518, 8;
	add.s64 	%rd25, %rd116, %rd117;
	@%p229 bra 	$L__BB0_165;

	ld.global.v4.u16 	{%rs124, %rs125, %rs126, %rs127}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1730, %rs124;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1731, %rs125;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1732, %rs126;}

	// end inline asm
	add.f32 	%f1733, %f1730, 0f00000000;
	add.f32 	%f1734, %f1731, 0f00000000;
	add.f32 	%f1735, %f1732, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f1735;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1734;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1733;}

	// end inline asm
	mov.u16 	%rs128, 0;
	st.global.v4.u16 	[%rd25], {%rs121, %rs122, %rs123, %rs128};
	bra.uni 	$L__BB0_166;

$L__BB0_5:
	ld.const.v4.f32 	{%f295, %f296, %f297, %f298}, [params+512];
	neg.f32 	%f299, %f296;
	neg.f32 	%f300, %f297;
	mul.f32 	%f301, %f1776, %f295;
	mul.f32 	%f302, %f1777, %f299;
	sub.f32 	%f303, %f302, %f301;
	mul.f32 	%f304, %f1778, %f297;
	sub.f32 	%f13, %f303, %f304;
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r76, [params+424];
	mul.lo.s32 	%r77, %r76, %r65;
	add.s32 	%r78, %r77, %r64;
	mul.wide.u32 	%rd36, %r78, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f305, [%rd37];
	mul.f32 	%f306, %f305, 0f3456BF95;
	ld.global.f32 	%f307, [%rd37+4];
	mul.f32 	%f308, %f307, 0f3456BF95;
	ld.global.f32 	%f309, [%rd37+8];
	mul.f32 	%f310, %f309, 0f3456BF95;
	abs.f32 	%f311, %f1776;
	div.rn.f32 	%f312, %f306, %f311;
	abs.f32 	%f313, %f1777;
	div.rn.f32 	%f314, %f308, %f313;
	abs.f32 	%f315, %f1778;
	div.rn.f32 	%f316, %f310, %f315;
	abs.f32 	%f317, %f312;
	abs.f32 	%f318, %f314;
	abs.f32 	%f319, %f316;
	mov.f32 	%f320, 0f38D1B717;
	max.f32 	%f321, %f317, %f320;
	max.f32 	%f322, %f318, %f320;
	max.f32 	%f323, %f319, %f320;
	fma.rn.f32 	%f14, %f1776, %f321, %f305;
	fma.rn.f32 	%f15, %f1777, %f322, %f307;
	fma.rn.f32 	%f16, %f1778, %f323, %f309;
	setp.gt.f32 	%p15, %f311, %f315;
	neg.f32 	%f324, %f1777;
	selp.f32 	%f325, %f324, 0f00000000, %p15;
	mov.f32 	%f1793, 0f00000000;
	neg.f32 	%f326, %f1778;
	selp.f32 	%f327, %f1776, %f326, %p15;
	selp.f32 	%f328, 0f00000000, %f1777, %p15;
	mul.f32 	%f329, %f327, %f327;
	fma.rn.f32 	%f330, %f325, %f325, %f329;
	fma.rn.f32 	%f331, %f328, %f328, %f330;
	sqrt.rn.f32 	%f332, %f331;
	rcp.rn.f32 	%f333, %f332;
	mul.f32 	%f17, %f325, %f333;
	mul.f32 	%f18, %f327, %f333;
	mul.f32 	%f19, %f328, %f333;
	mul.f32 	%f334, %f1778, %f18;
	mul.f32 	%f335, %f1777, %f19;
	sub.f32 	%f20, %f334, %f335;
	mul.f32 	%f336, %f1776, %f19;
	mul.f32 	%f337, %f1778, %f17;
	sub.f32 	%f21, %f336, %f337;
	mul.f32 	%f338, %f1777, %f17;
	mul.f32 	%f339, %f1776, %f18;
	sub.f32 	%f22, %f338, %f339;
	add.s32 	%r79, %r67, -1;
	add.s32 	%r80, %r64, 1;
	min.u32 	%r81, %r80, %r79;
	add.s32 	%r82, %r77, %r81;
	mul.wide.u32 	%rd38, %r82, 12;
	add.s64 	%rd39, %rd35, %rd38;
	ld.global.f32 	%f340, [%rd39];
	setp.eq.f32 	%p16, %f340, 0f00000000;
	ld.global.f32 	%f341, [%rd39+4];
	setp.eq.f32 	%p17, %f341, 0f00000000;
	and.pred  	%p18, %p16, %p17;
	ld.global.f32 	%f342, [%rd39+8];
	setp.eq.f32 	%p19, %f342, 0f00000000;
	and.pred  	%p20, %p18, %p19;
	selp.f32 	%f343, %f305, %f340, %p20;
	selp.f32 	%f344, %f307, %f341, %p20;
	selp.f32 	%f345, %f309, %f342, %p20;
	add.s32 	%r83, %r68, -1;
	add.s32 	%r84, %r65, 1;
	min.u32 	%r85, %r84, %r83;
	mad.lo.s32 	%r86, %r76, %r85, %r64;
	mul.wide.u32 	%rd40, %r86, 12;
	add.s64 	%rd41, %rd35, %rd40;
	ld.global.f32 	%f346, [%rd41];
	setp.eq.f32 	%p21, %f346, 0f00000000;
	ld.global.f32 	%f347, [%rd41+4];
	setp.eq.f32 	%p22, %f347, 0f00000000;
	and.pred  	%p23, %p21, %p22;
	ld.global.f32 	%f348, [%rd41+8];
	setp.eq.f32 	%p24, %f348, 0f00000000;
	and.pred  	%p25, %p23, %p24;
	selp.f32 	%f349, %f305, %f346, %p25;
	selp.f32 	%f350, %f307, %f347, %p25;
	selp.f32 	%f351, %f309, %f348, %p25;
	sub.f32 	%f352, %f343, %f305;
	sub.f32 	%f353, %f344, %f307;
	sub.f32 	%f354, %f345, %f309;
	sub.f32 	%f355, %f349, %f305;
	sub.f32 	%f356, %f350, %f307;
	sub.f32 	%f357, %f351, %f309;
	abs.f32 	%f358, %f352;
	abs.f32 	%f359, %f355;
	max.f32 	%f360, %f358, %f359;
	abs.f32 	%f361, %f353;
	abs.f32 	%f362, %f356;
	max.f32 	%f363, %f361, %f362;
	abs.f32 	%f364, %f354;
	abs.f32 	%f365, %f357;
	max.f32 	%f366, %f364, %f365;
	max.f32 	%f367, %f360, %f363;
	max.f32 	%f368, %f367, %f366;
	setp.eq.f32 	%p26, %f352, 0f00000000;
	setp.eq.f32 	%p27, %f353, 0f00000000;
	and.pred  	%p28, %p26, %p27;
	setp.eq.f32 	%p29, %f354, 0f00000000;
	and.pred  	%p30, %p29, %p28;
	setp.eq.f32 	%p31, %f355, 0f00000000;
	setp.eq.f32 	%p32, %f356, 0f00000000;
	and.pred  	%p33, %p31, %p32;
	setp.eq.f32 	%p34, %f357, 0f00000000;
	and.pred  	%p35, %p34, %p33;
	or.pred  	%p36, %p30, %p35;
	selp.f32 	%f23, 0f00000000, %f368, %p36;
	abs.f32 	%f369, %f295;
	abs.f32 	%f370, %f297;
	setp.gt.f32 	%p37, %f369, %f370;
	selp.f32 	%f371, %f299, 0f00000000, %p37;
	selp.f32 	%f372, %f295, %f300, %p37;
	selp.f32 	%f373, 0f00000000, %f296, %p37;
	mul.f32 	%f374, %f372, %f372;
	fma.rn.f32 	%f375, %f371, %f371, %f374;
	fma.rn.f32 	%f376, %f373, %f373, %f375;
	sqrt.rn.f32 	%f377, %f376;
	rcp.rn.f32 	%f378, %f377;
	mul.f32 	%f24, %f371, %f378;
	mul.f32 	%f25, %f372, %f378;
	mul.f32 	%f26, %f373, %f378;
	ld.const.u64 	%rd42, [params+128];
	cvta.to.global.u64 	%rd43, %rd42;
	ld.const.u32 	%r87, [params+120];
	mad.lo.s32 	%r88, %r87, %r65, %r64;
	mul.wide.u32 	%rd44, %r88, 4;
	add.s64 	%rd3, %rd43, %rd44;
	ld.const.u32 	%r7, [params+540];
	setp.lt.s32 	%p38, %r7, 1;
	mov.f32 	%f1794, %f1793;
	mov.f32 	%f1795, %f1793;
	mov.f32 	%f1796, %f1793;
	@%p38 bra 	$L__BB0_52;

	cvt.rn.f32.s32 	%f383, %r7;
	rcp.rn.f32 	%f27, %f383;
	ld.global.u32 	%r1531, [%rd3];
	ld.const.f32 	%f28, [params+536];
	ld.const.u8 	%rs23, [params+104];
	and.b16  	%rs24, %rs23, 32;
	setp.eq.s16 	%p39, %rs24, 0;
	mov.u32 	%r89, 0;
	selp.f32 	%f29, 0f3F800000, 0f41200000, %p39;
	mul.f32 	%f30, %f14, 0f3456BF95;
	mul.f32 	%f31, %f15, 0f3456BF95;
	mul.f32 	%f32, %f16, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f384, %f295, %f25;
	mul.f32 	%f385, %f296, %f24;
	sub.f32 	%f33, %f385, %f384;
	mul.f32 	%f386, %f297, %f24;
	mul.f32 	%f387, %f295, %f26;
	sub.f32 	%f34, %f387, %f386;
	mul.f32 	%f388, %f296, %f26;
	mul.f32 	%f389, %f297, %f25;
	sub.f32 	%f35, %f389, %f388;
	abs.f32 	%f472, %f31;
	abs.f32 	%f473, %f30;
	max.f32 	%f474, %f473, %f472;
	abs.f32 	%f475, %f32;
	max.f32 	%f476, %f474, %f475;
	mov.u32 	%r1528, %r89;

$L__BB0_7:
	mov.u32 	%r1530, %r89;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1775, %r1528;
	mad.lo.s32 	%r91, %r1531, 1664525, 1013904223;
	and.b32  	%r92, %r91, 16777215;
	cvt.rn.f32.u32 	%f390, %r92;
	fma.rn.f32 	%f391, %f390, 0f33800000, %f1775;
	mul.f32 	%f392, %f27, %f391;
	mad.lo.s32 	%r13, %r91, 1664525, 1013904223;
	and.b32  	%r93, %r13, 16777215;
	cvt.rn.f32.u32 	%f393, %r93;
	cvt.rn.f32.s32 	%f394, %r1530;
	fma.rn.f32 	%f395, %f393, 0f33800000, %f394;
	mul.f32 	%f396, %f27, %f395;
	sqrt.rn.f32 	%f45, %f392;
	mul.f32 	%f46, %f396, 0f40C90FDB;
	mul.f32 	%f397, %f46, 0f3F22F983;
	cvt.rni.s32.f32 	%r1538, %f397;
	cvt.rn.f32.s32 	%f398, %r1538;
	mov.f32 	%f399, 0fBFC90FDA;
	fma.rn.f32 	%f400, %f398, %f399, %f46;
	mov.f32 	%f401, 0fB3A22168;
	fma.rn.f32 	%f402, %f398, %f401, %f400;
	mov.f32 	%f403, 0fA7C234C5;
	fma.rn.f32 	%f1790, %f398, %f403, %f402;
	abs.f32 	%f48, %f46;
	setp.ltu.f32 	%p40, %f48, 0f47CE4780;
	add.s64 	%rd5, %rd1, 24;
	mov.u32 	%r1535, %r1538;
	mov.f32 	%f1787, %f1790;
	@%p40 bra 	$L__BB0_16;

	setp.eq.f32 	%p41, %f48, 0f7F800000;
	@%p41 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f406, 0f00000000;
	mul.rn.f32 	%f1787, %f46, %f406;
	mov.u32 	%r1535, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r15, %f46;
	bfe.u32 	%r95, %r15, 23, 8;
	add.s32 	%r16, %r95, -128;
	shl.b32 	%r96, %r15, 8;
	or.b32  	%r17, %r96, -2147483648;
	shr.u32 	%r18, %r16, 5;
	mov.u64 	%rd132, 0;
	mov.u32 	%r1532, 0;
	mov.u64 	%rd131, __cudart_i2opi_f;
	mov.u64 	%rd130, %rd1;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r97, [%rd131];
	mad.wide.u32 	%rd47, %r97, %r17, %rd132;
	shr.u64 	%rd132, %rd47, 32;
	st.local.u32 	[%rd130], %rd47;
	add.s64 	%rd131, %rd131, 4;
	add.s64 	%rd130, %rd130, 4;
	add.s32 	%r1532, %r1532, 1;
	setp.ne.s32 	%p42, %r1532, 6;
	@%p42 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd132;
	mov.u32 	%r98, 4;
	sub.s32 	%r21, %r98, %r18;
	mov.u32 	%r99, 6;
	sub.s32 	%r100, %r99, %r18;
	mul.wide.s32 	%rd48, %r100, 4;
	add.s64 	%rd49, %rd1, %rd48;
	ld.local.u32 	%r1533, [%rd49];
	ld.local.u32 	%r1534, [%rd49+-4];
	and.b32  	%r24, %r16, 31;
	setp.eq.s32 	%p43, %r24, 0;
	@%p43 bra 	$L__BB0_14;

	mov.u32 	%r101, 32;
	sub.s32 	%r102, %r101, %r24;
	shr.u32 	%r103, %r1534, %r102;
	shl.b32 	%r104, %r1533, %r24;
	add.s32 	%r1533, %r103, %r104;
	mul.wide.s32 	%rd50, %r21, 4;
	add.s64 	%rd51, %rd1, %rd50;
	ld.local.u32 	%r105, [%rd51];
	shr.u32 	%r106, %r105, %r102;
	shl.b32 	%r107, %r1534, %r24;
	add.s32 	%r1534, %r106, %r107;

$L__BB0_14:
	and.b32  	%r108, %r15, -2147483648;
	shr.u32 	%r109, %r1534, 30;
	shl.b32 	%r110, %r1533, 2;
	or.b32  	%r111, %r109, %r110;
	shr.u32 	%r112, %r111, 31;
	shr.u32 	%r113, %r1533, 30;
	add.s32 	%r114, %r112, %r113;
	neg.s32 	%r115, %r114;
	setp.eq.s32 	%p44, %r108, 0;
	selp.b32 	%r1535, %r114, %r115, %p44;
	setp.ne.s32 	%p45, %r112, 0;
	xor.b32  	%r116, %r108, -2147483648;
	selp.b32 	%r117, %r116, %r108, %p45;
	selp.b32 	%r118, -1, 0, %p45;
	xor.b32  	%r119, %r111, %r118;
	shl.b32 	%r120, %r1534, 2;
	xor.b32  	%r121, %r120, %r118;
	cvt.u64.u32 	%rd52, %r119;
	cvt.u64.u32 	%rd53, %r121;
	bfi.b64 	%rd54, %rd52, %rd53, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd54;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f404, %fd2;
	setp.eq.s32 	%p46, %r117, 0;
	neg.f32 	%f405, %f404;
	selp.f32 	%f1787, %f404, %f405, %p46;

$L__BB0_16:
	add.s32 	%r31, %r1535, 1;
	and.b32  	%r32, %r31, 1;
	setp.eq.s32 	%p47, %r32, 0;
	selp.f32 	%f52, %f1787, 0f3F800000, %p47;
	mul.rn.f32 	%f53, %f1787, %f1787;
	mov.f32 	%f1788, 0fB94D4153;
	@%p47 bra 	$L__BB0_18;

	mov.f32 	%f408, 0fBAB607ED;
	mov.f32 	%f409, 0f37CBAC00;
	fma.rn.f32 	%f1788, %f409, %f53, %f408;

$L__BB0_18:
	selp.f32 	%f410, 0f3C0885E4, 0f3D2AAABB, %p47;
	fma.rn.f32 	%f411, %f1788, %f53, %f410;
	selp.f32 	%f412, 0fBE2AAAA8, 0fBEFFFFFF, %p47;
	fma.rn.f32 	%f413, %f411, %f53, %f412;
	mov.f32 	%f414, 0f00000000;
	fma.rn.f32 	%f415, %f53, %f52, %f414;
	fma.rn.f32 	%f1789, %f413, %f415, %f52;
	and.b32  	%r123, %r31, 2;
	setp.eq.s32 	%p49, %r123, 0;
	@%p49 bra 	$L__BB0_20;

	mov.f32 	%f417, 0fBF800000;
	fma.rn.f32 	%f1789, %f1789, %f417, %f414;

$L__BB0_20:
	@%p40 bra 	$L__BB0_28;

	setp.eq.f32 	%p51, %f48, 0f7F800000;
	@%p51 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f420, 0f00000000;
	mul.rn.f32 	%f1790, %f46, %f420;
	mov.u32 	%r1538, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r33, %f46;
	bfe.u32 	%r124, %r33, 23, 8;
	add.s32 	%r34, %r124, -128;
	shl.b32 	%r125, %r33, 8;
	or.b32  	%r35, %r125, -2147483648;
	shr.u32 	%r36, %r34, 5;
	mov.u64 	%rd133, 0;
	mov.u64 	%rd134, %rd133;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd57, %rd133, 2;
	mov.u64 	%rd58, __cudart_i2opi_f;
	add.s64 	%rd59, %rd58, %rd57;
	ld.global.nc.u32 	%r126, [%rd59];
	mad.wide.u32 	%rd60, %r126, %r35, %rd134;
	shr.u64 	%rd134, %rd60, 32;
	add.s64 	%rd61, %rd1, %rd57;
	st.local.u32 	[%rd61], %rd60;
	cvt.u32.u64 	%r127, %rd133;
	add.s32 	%r128, %r127, 1;
	cvt.s64.s32 	%rd133, %r128;
	setp.ne.s32 	%p52, %r128, 6;
	@%p52 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd134;
	mov.u32 	%r129, 4;
	sub.s32 	%r37, %r129, %r36;
	mov.u32 	%r130, 6;
	sub.s32 	%r131, %r130, %r36;
	mul.wide.s32 	%rd62, %r131, 4;
	add.s64 	%rd63, %rd1, %rd62;
	ld.local.u32 	%r1536, [%rd63];
	ld.local.u32 	%r1537, [%rd63+-4];
	and.b32  	%r40, %r34, 31;
	setp.eq.s32 	%p53, %r40, 0;
	@%p53 bra 	$L__BB0_26;

	mov.u32 	%r132, 32;
	sub.s32 	%r133, %r132, %r40;
	shr.u32 	%r134, %r1537, %r133;
	shl.b32 	%r135, %r1536, %r40;
	add.s32 	%r1536, %r134, %r135;
	mul.wide.s32 	%rd64, %r37, 4;
	add.s64 	%rd65, %rd1, %rd64;
	ld.local.u32 	%r136, [%rd65];
	shr.u32 	%r137, %r136, %r133;
	shl.b32 	%r138, %r1537, %r40;
	add.s32 	%r1537, %r137, %r138;

$L__BB0_26:
	and.b32  	%r139, %r33, -2147483648;
	shr.u32 	%r140, %r1537, 30;
	shl.b32 	%r141, %r1536, 2;
	or.b32  	%r142, %r140, %r141;
	shr.u32 	%r143, %r142, 31;
	shr.u32 	%r144, %r1536, 30;
	add.s32 	%r145, %r143, %r144;
	neg.s32 	%r146, %r145;
	setp.eq.s32 	%p54, %r139, 0;
	selp.b32 	%r1538, %r145, %r146, %p54;
	setp.ne.s32 	%p55, %r143, 0;
	xor.b32  	%r147, %r139, -2147483648;
	selp.b32 	%r148, %r147, %r139, %p55;
	selp.b32 	%r149, -1, 0, %p55;
	xor.b32  	%r150, %r142, %r149;
	shl.b32 	%r151, %r1537, 2;
	xor.b32  	%r152, %r151, %r149;
	cvt.u64.u32 	%rd66, %r150;
	cvt.u64.u32 	%rd67, %r152;
	bfi.b64 	%rd68, %rd66, %rd67, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd68;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f418, %fd4;
	setp.eq.s32 	%p56, %r148, 0;
	neg.f32 	%f419, %f418;
	selp.f32 	%f1790, %f418, %f419, %p56;

$L__BB0_28:
	mul.f32 	%f62, %f45, %f1789;
	and.b32  	%r47, %r1538, 1;
	setp.eq.s32 	%p57, %r47, 0;
	selp.f32 	%f63, %f1790, 0f3F800000, %p57;
	mul.rn.f32 	%f64, %f1790, %f1790;
	mov.f32 	%f1791, 0fB94D4153;
	@%p57 bra 	$L__BB0_30;

	mov.f32 	%f422, 0fBAB607ED;
	mov.f32 	%f423, 0f37CBAC00;
	fma.rn.f32 	%f1791, %f423, %f64, %f422;

$L__BB0_30:
	selp.f32 	%f424, 0f3C0885E4, 0f3D2AAABB, %p57;
	fma.rn.f32 	%f425, %f1791, %f64, %f424;
	selp.f32 	%f426, 0fBE2AAAA8, 0fBEFFFFFF, %p57;
	fma.rn.f32 	%f427, %f425, %f64, %f426;
	mov.f32 	%f428, 0f00000000;
	fma.rn.f32 	%f429, %f64, %f63, %f428;
	fma.rn.f32 	%f1792, %f427, %f429, %f63;
	and.b32  	%r154, %r1538, 2;
	setp.eq.s32 	%p59, %r154, 0;
	@%p59 bra 	$L__BB0_32;

	mov.f32 	%f431, 0fBF800000;
	fma.rn.f32 	%f1792, %f1792, %f431, %f428;

$L__BB0_32:
	mul.f32 	%f441, %f62, %f62;
	mov.f32 	%f442, 0f3F800000;
	sub.f32 	%f443, %f442, %f441;
	mul.f32 	%f444, %f45, %f1792;
	mul.f32 	%f445, %f444, %f444;
	sub.f32 	%f446, %f443, %f445;
	max.f32 	%f447, %f428, %f446;
	sqrt.rn.f32 	%f448, %f447;
	mul.f32 	%f449, %f24, %f444;
	mul.f32 	%f450, %f25, %f444;
	mul.f32 	%f451, %f26, %f444;
	fma.rn.f32 	%f452, %f35, %f62, %f449;
	fma.rn.f32 	%f453, %f34, %f62, %f450;
	fma.rn.f32 	%f454, %f33, %f62, %f451;
	fma.rn.f32 	%f455, %f295, %f448, %f452;
	fma.rn.f32 	%f456, %f296, %f448, %f453;
	fma.rn.f32 	%f457, %f297, %f448, %f454;
	add.f32 	%f458, %f295, %f455;
	add.f32 	%f459, %f296, %f456;
	add.f32 	%f460, %f297, %f457;
	mul.f32 	%f461, %f28, %f458;
	mul.f32 	%f462, %f28, %f459;
	mul.f32 	%f463, %f28, %f460;
	sub.f32 	%f464, %f461, %f295;
	sub.f32 	%f465, %f462, %f296;
	sub.f32 	%f466, %f463, %f297;
	mul.f32 	%f467, %f465, %f465;
	fma.rn.f32 	%f468, %f464, %f464, %f467;
	fma.rn.f32 	%f469, %f466, %f466, %f468;
	sqrt.rn.f32 	%f470, %f469;
	rcp.rn.f32 	%f471, %f470;
	mul.f32 	%f70, %f471, %f464;
	mul.f32 	%f71, %f471, %f465;
	mul.f32 	%f72, %f471, %f466;
	mov.f32 	%f477, 0f38D1B717;
	max.f32 	%f478, %f476, %f477;
	mul.f32 	%f438, %f29, %f478;
	mad.lo.s32 	%r226, %r13, 1664525, 1013904223;
	and.b32  	%r227, %r226, 16777215;
	cvt.rn.f32.u32 	%f479, %r227;
	mul.f32 	%f480, %f479, 0f33800000;
	fma.rn.f32 	%f481, %f480, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r48, %r226, 1664525, 1013904223;
	and.b32  	%r228, %r48, 16777215;
	cvt.rn.f32.u32 	%f482, %r228;
	mul.f32 	%f483, %f482, 0f33800000;
	fma.rn.f32 	%f484, %f483, 0f40000000, 0fBF800000;
	mul.f32 	%f485, %f17, %f484;
	mul.f32 	%f486, %f18, %f484;
	mul.f32 	%f487, %f19, %f484;
	fma.rn.f32 	%f488, %f20, %f481, %f485;
	fma.rn.f32 	%f489, %f21, %f481, %f486;
	fma.rn.f32 	%f490, %f22, %f481, %f487;
	mul.f32 	%f491, %f489, %f489;
	fma.rn.f32 	%f492, %f488, %f488, %f491;
	fma.rn.f32 	%f493, %f490, %f490, %f492;
	sqrt.rn.f32 	%f494, %f493;
	rcp.rn.f32 	%f495, %f494;
	mul.f32 	%f496, %f488, %f495;
	mul.f32 	%f497, %f489, %f495;
	mul.f32 	%f498, %f490, %f495;
	mul.f32 	%f499, %f1777, %f498;
	mul.f32 	%f500, %f1778, %f497;
	sub.f32 	%f501, %f499, %f500;
	mul.f32 	%f502, %f1778, %f496;
	mul.f32 	%f503, %f1776, %f498;
	sub.f32 	%f504, %f502, %f503;
	mul.f32 	%f505, %f1776, %f497;
	mul.f32 	%f506, %f1777, %f496;
	sub.f32 	%f507, %f505, %f506;
	mul.f32 	%f508, %f496, 0f3E24A490;
	mul.f32 	%f509, %f497, 0f3E24A490;
	mul.f32 	%f510, %f498, 0f3E24A490;
	fma.rn.f32 	%f511, %f23, %f508, %f14;
	fma.rn.f32 	%f512, %f23, %f509, %f15;
	fma.rn.f32 	%f513, %f23, %f510, %f16;
	mul.f32 	%f514, %f501, 0fBECECEDE;
	mul.f32 	%f515, %f504, 0fBECECEDE;
	mul.f32 	%f516, %f507, 0fBECECEDE;
	fma.rn.f32 	%f74, %f23, %f514, %f511;
	fma.rn.f32 	%f75, %f23, %f515, %f512;
	fma.rn.f32 	%f76, %f23, %f516, %f513;
	sub.f32 	%f517, %f74, %f14;
	sub.f32 	%f518, %f75, %f15;
	sub.f32 	%f519, %f76, %f16;
	mul.f32 	%f520, %f518, %f518;
	fma.rn.f32 	%f521, %f517, %f517, %f520;
	fma.rn.f32 	%f522, %f519, %f519, %f521;
	sqrt.rn.f32 	%f439, %f522;
	rcp.rn.f32 	%f523, %f439;
	mul.f32 	%f435, %f523, %f517;
	mul.f32 	%f436, %f523, %f518;
	mul.f32 	%f437, %f523, %f519;
	mov.u32 	%r191, 2;
	mov.u32 	%r192, 1;
	mov.u32 	%r193, 3;
	mov.u32 	%r196, 1065353216;
	mov.u32 	%r225, 0;
	// begin inline asm
	call(%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170,%r171,%r172,%r173,%r174,%r175,%r176,%r177,%r178,%r179,%r180,%r181,%r182,%r183,%r184,%r185,%r186),_optix_trace_typed_32,(%r225,%rd4,%f14,%f15,%f16,%f435,%f436,%f437,%f438,%f439,%f428,%r192,%r225,%r192,%r191,%r192,%r193,%r196,%r196,%r196,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225);
	// end inline asm
	mov.b32 	%f524, %r155;
	mov.b32 	%f525, %r156;
	mov.b32 	%f526, %r157;
	setp.neu.f32 	%p60, %f524, 0f3F800000;
	setp.neu.f32 	%p61, %f525, 0f3F800000;
	or.pred  	%p62, %p60, %p61;
	setp.neu.f32 	%p63, %f526, 0f3F800000;
	mov.u16 	%rs196, 0;
	or.pred  	%p64, %p63, %p62;
	@%p64 bra 	$L__BB0_34;

	mov.f32 	%f534, 0f6C4ECB8F;
	mov.f32 	%f535, 0f00000000;
	// begin inline asm
	call(%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260),_optix_trace_typed_32,(%r225,%rd4,%f74,%f75,%f76,%f70,%f71,%f72,%f438,%f534,%f535,%r192,%r225,%r192,%r191,%r192,%r193,%r196,%r196,%r196,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225);
	// end inline asm
	mov.b32 	%f536, %r229;
	mov.b32 	%f537, %r230;
	mov.b32 	%f538, %r231;
	add.f32 	%f1793, %f1793, %f536;
	add.f32 	%f1794, %f1794, %f537;
	add.f32 	%f1795, %f1795, %f538;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_34:
	mad.lo.s32 	%r371, %r48, 1664525, 1013904223;
	and.b32  	%r372, %r371, 16777215;
	cvt.rn.f32.u32 	%f548, %r372;
	mul.f32 	%f549, %f548, 0f33800000;
	fma.rn.f32 	%f550, %f549, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r49, %r371, 1664525, 1013904223;
	and.b32  	%r373, %r49, 16777215;
	cvt.rn.f32.u32 	%f551, %r373;
	mul.f32 	%f552, %f551, 0f33800000;
	fma.rn.f32 	%f553, %f552, 0f40000000, 0fBF800000;
	mul.f32 	%f554, %f17, %f553;
	mul.f32 	%f555, %f18, %f553;
	mul.f32 	%f556, %f19, %f553;
	fma.rn.f32 	%f557, %f20, %f550, %f554;
	fma.rn.f32 	%f558, %f21, %f550, %f555;
	fma.rn.f32 	%f559, %f22, %f550, %f556;
	mul.f32 	%f560, %f558, %f558;
	fma.rn.f32 	%f561, %f557, %f557, %f560;
	fma.rn.f32 	%f562, %f559, %f559, %f561;
	sqrt.rn.f32 	%f563, %f562;
	rcp.rn.f32 	%f564, %f563;
	mul.f32 	%f565, %f557, %f564;
	mul.f32 	%f566, %f558, %f564;
	mul.f32 	%f567, %f559, %f564;
	mul.f32 	%f568, %f1777, %f567;
	mul.f32 	%f569, %f1778, %f566;
	sub.f32 	%f570, %f568, %f569;
	mul.f32 	%f571, %f1778, %f565;
	mul.f32 	%f572, %f1776, %f567;
	sub.f32 	%f573, %f571, %f572;
	mul.f32 	%f574, %f1776, %f566;
	mul.f32 	%f575, %f1777, %f565;
	sub.f32 	%f576, %f574, %f575;
	mul.f32 	%f577, %f565, 0fBE24A490;
	mul.f32 	%f578, %f566, 0fBE24A490;
	mul.f32 	%f579, %f567, 0fBE24A490;
	fma.rn.f32 	%f580, %f23, %f577, %f14;
	fma.rn.f32 	%f581, %f23, %f578, %f15;
	fma.rn.f32 	%f582, %f23, %f579, %f16;
	mul.f32 	%f583, %f570, 0f3ECACABC;
	mul.f32 	%f584, %f573, 0f3ECACABC;
	mul.f32 	%f585, %f576, 0f3ECACABC;
	fma.rn.f32 	%f85, %f23, %f583, %f580;
	fma.rn.f32 	%f86, %f23, %f584, %f581;
	fma.rn.f32 	%f87, %f23, %f585, %f582;
	sub.f32 	%f586, %f85, %f14;
	sub.f32 	%f587, %f86, %f15;
	sub.f32 	%f588, %f87, %f16;
	mul.f32 	%f589, %f587, %f587;
	fma.rn.f32 	%f590, %f586, %f586, %f589;
	fma.rn.f32 	%f591, %f588, %f588, %f590;
	sqrt.rn.f32 	%f546, %f591;
	rcp.rn.f32 	%f592, %f546;
	mul.f32 	%f542, %f592, %f586;
	mul.f32 	%f543, %f592, %f587;
	mul.f32 	%f544, %f592, %f588;
	mov.f32 	%f547, 0f00000000;
	// begin inline asm
	call(%r300,%r301,%r302,%r303,%r304,%r305,%r306,%r307,%r308,%r309,%r310,%r311,%r312,%r313,%r314,%r315,%r316,%r317,%r318,%r319,%r320,%r321,%r322,%r323,%r324,%r325,%r326,%r327,%r328,%r329,%r330,%r331),_optix_trace_typed_32,(%r225,%rd4,%f14,%f15,%f16,%f542,%f543,%f544,%f438,%f546,%f547,%r192,%r225,%r192,%r191,%r192,%r193,%r196,%r196,%r196,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225,%r225);
	// end inline asm
	mov.b32 	%f593, %r300;
	mov.b32 	%f594, %r301;
	mov.b32 	%f595, %r302;
	setp.neu.f32 	%p65, %f593, 0f3F800000;
	setp.neu.f32 	%p66, %f594, 0f3F800000;
	or.pred  	%p67, %p65, %p66;
	setp.neu.f32 	%p68, %f595, 0f3F800000;
	or.pred  	%p69, %p68, %p67;
	@%p69 bra 	$L__BB0_36;

	mov.f32 	%f603, 0f6C4ECB8F;
	mov.u32 	%r410, 2;
	mov.u32 	%r411, 1;
	mov.u32 	%r412, 3;
	mov.u32 	%r415, 1065353216;
	mov.u32 	%r444, 0;
	// begin inline asm
	call(%r374,%r375,%r376,%r377,%r378,%r379,%r380,%r381,%r382,%r383,%r384,%r385,%r386,%r387,%r388,%r389,%r390,%r391,%r392,%r393,%r394,%r395,%r396,%r397,%r398,%r399,%r400,%r401,%r402,%r403,%r404,%r405),_optix_trace_typed_32,(%r444,%rd4,%f85,%f86,%f87,%f70,%f71,%f72,%f438,%f603,%f547,%r411,%r444,%r411,%r410,%r411,%r412,%r415,%r415,%r415,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444,%r444);
	// end inline asm
	mov.b32 	%f605, %r374;
	mov.b32 	%f606, %r375;
	mov.b32 	%f607, %r376;
	add.f32 	%f1793, %f1793, %f605;
	add.f32 	%f1794, %f1794, %f606;
	add.f32 	%f1795, %f1795, %f607;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_36:
	mad.lo.s32 	%r516, %r49, 1664525, 1013904223;
	and.b32  	%r517, %r516, 16777215;
	cvt.rn.f32.u32 	%f617, %r517;
	mul.f32 	%f618, %f617, 0f33800000;
	fma.rn.f32 	%f619, %f618, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r50, %r516, 1664525, 1013904223;
	and.b32  	%r518, %r50, 16777215;
	cvt.rn.f32.u32 	%f620, %r518;
	mul.f32 	%f621, %f620, 0f33800000;
	fma.rn.f32 	%f622, %f621, 0f40000000, 0fBF800000;
	mul.f32 	%f623, %f17, %f622;
	mul.f32 	%f624, %f18, %f622;
	mul.f32 	%f625, %f19, %f622;
	fma.rn.f32 	%f626, %f20, %f619, %f623;
	fma.rn.f32 	%f627, %f21, %f619, %f624;
	fma.rn.f32 	%f628, %f22, %f619, %f625;
	mul.f32 	%f629, %f627, %f627;
	fma.rn.f32 	%f630, %f626, %f626, %f629;
	fma.rn.f32 	%f631, %f628, %f628, %f630;
	sqrt.rn.f32 	%f632, %f631;
	rcp.rn.f32 	%f633, %f632;
	mul.f32 	%f634, %f626, %f633;
	mul.f32 	%f635, %f627, %f633;
	mul.f32 	%f636, %f628, %f633;
	mul.f32 	%f637, %f1777, %f636;
	mul.f32 	%f638, %f1778, %f635;
	sub.f32 	%f639, %f637, %f638;
	mul.f32 	%f640, %f1778, %f634;
	mul.f32 	%f641, %f1776, %f636;
	sub.f32 	%f642, %f640, %f641;
	mul.f32 	%f643, %f1776, %f635;
	mul.f32 	%f644, %f1777, %f634;
	sub.f32 	%f645, %f643, %f644;
	mul.f32 	%f646, %f634, 0f3F23A3A8;
	mul.f32 	%f647, %f635, 0f3F23A3A8;
	mul.f32 	%f648, %f636, 0f3F23A3A8;
	fma.rn.f32 	%f649, %f23, %f646, %f14;
	fma.rn.f32 	%f650, %f23, %f647, %f15;
	fma.rn.f32 	%f651, %f23, %f648, %f16;
	mul.f32 	%f652, %f639, 0f3E24A490;
	mul.f32 	%f653, %f642, 0f3E24A490;
	mul.f32 	%f654, %f645, 0f3E24A490;
	fma.rn.f32 	%f96, %f23, %f652, %f649;
	fma.rn.f32 	%f97, %f23, %f653, %f650;
	fma.rn.f32 	%f98, %f23, %f654, %f651;
	sub.f32 	%f655, %f96, %f14;
	sub.f32 	%f656, %f97, %f15;
	sub.f32 	%f657, %f98, %f16;
	mul.f32 	%f658, %f656, %f656;
	fma.rn.f32 	%f659, %f655, %f655, %f658;
	fma.rn.f32 	%f660, %f657, %f657, %f659;
	sqrt.rn.f32 	%f615, %f660;
	rcp.rn.f32 	%f661, %f615;
	mul.f32 	%f611, %f661, %f655;
	mul.f32 	%f612, %f661, %f656;
	mul.f32 	%f613, %f661, %f657;
	mov.u32 	%r481, 2;
	mov.u32 	%r482, 1;
	mov.u32 	%r483, 3;
	mov.u32 	%r486, 1065353216;
	mov.u32 	%r515, 0;
	// begin inline asm
	call(%r445,%r446,%r447,%r448,%r449,%r450,%r451,%r452,%r453,%r454,%r455,%r456,%r457,%r458,%r459,%r460,%r461,%r462,%r463,%r464,%r465,%r466,%r467,%r468,%r469,%r470,%r471,%r472,%r473,%r474,%r475,%r476),_optix_trace_typed_32,(%r515,%rd4,%f14,%f15,%f16,%f611,%f612,%f613,%f438,%f615,%f547,%r482,%r515,%r482,%r481,%r482,%r483,%r486,%r486,%r486,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515);
	// end inline asm
	mov.b32 	%f662, %r445;
	mov.b32 	%f663, %r446;
	mov.b32 	%f664, %r447;
	setp.neu.f32 	%p70, %f662, 0f3F800000;
	setp.neu.f32 	%p71, %f663, 0f3F800000;
	or.pred  	%p72, %p70, %p71;
	setp.neu.f32 	%p73, %f664, 0f3F800000;
	or.pred  	%p74, %p73, %p72;
	@%p74 bra 	$L__BB0_38;

	mov.f32 	%f672, 0f6C4ECB8F;
	mov.f32 	%f673, 0f00000000;
	// begin inline asm
	call(%r519,%r520,%r521,%r522,%r523,%r524,%r525,%r526,%r527,%r528,%r529,%r530,%r531,%r532,%r533,%r534,%r535,%r536,%r537,%r538,%r539,%r540,%r541,%r542,%r543,%r544,%r545,%r546,%r547,%r548,%r549,%r550),_optix_trace_typed_32,(%r515,%rd4,%f96,%f97,%f98,%f70,%f71,%f72,%f438,%f672,%f673,%r482,%r515,%r482,%r481,%r482,%r483,%r486,%r486,%r486,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515);
	// end inline asm
	mov.b32 	%f674, %r519;
	mov.b32 	%f675, %r520;
	mov.b32 	%f676, %r521;
	add.f32 	%f1793, %f1793, %f674;
	add.f32 	%f1794, %f1794, %f675;
	add.f32 	%f1795, %f1795, %f676;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_38:
	mad.lo.s32 	%r661, %r50, 1664525, 1013904223;
	and.b32  	%r662, %r661, 16777215;
	cvt.rn.f32.u32 	%f686, %r662;
	mul.f32 	%f687, %f686, 0f33800000;
	fma.rn.f32 	%f688, %f687, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r51, %r661, 1664525, 1013904223;
	and.b32  	%r663, %r51, 16777215;
	cvt.rn.f32.u32 	%f689, %r663;
	mul.f32 	%f690, %f689, 0f33800000;
	fma.rn.f32 	%f691, %f690, 0f40000000, 0fBF800000;
	mul.f32 	%f692, %f17, %f691;
	mul.f32 	%f693, %f18, %f691;
	mul.f32 	%f694, %f19, %f691;
	fma.rn.f32 	%f695, %f20, %f688, %f692;
	fma.rn.f32 	%f696, %f21, %f688, %f693;
	fma.rn.f32 	%f697, %f22, %f688, %f694;
	mul.f32 	%f698, %f696, %f696;
	fma.rn.f32 	%f699, %f695, %f695, %f698;
	fma.rn.f32 	%f700, %f697, %f697, %f699;
	sqrt.rn.f32 	%f701, %f700;
	rcp.rn.f32 	%f702, %f701;
	mul.f32 	%f703, %f695, %f702;
	mul.f32 	%f704, %f696, %f702;
	mul.f32 	%f705, %f697, %f702;
	mul.f32 	%f706, %f1777, %f705;
	mul.f32 	%f707, %f1778, %f704;
	sub.f32 	%f708, %f706, %f707;
	mul.f32 	%f709, %f1778, %f703;
	mul.f32 	%f710, %f1776, %f705;
	sub.f32 	%f711, %f709, %f710;
	mul.f32 	%f712, %f1776, %f704;
	mul.f32 	%f713, %f1777, %f703;
	sub.f32 	%f714, %f712, %f713;
	mul.f32 	%f715, %f703, 0fBECECEDE;
	mul.f32 	%f716, %f704, 0fBECECEDE;
	mul.f32 	%f717, %f705, 0fBECECEDE;
	fma.rn.f32 	%f718, %f23, %f715, %f14;
	fma.rn.f32 	%f719, %f23, %f716, %f15;
	fma.rn.f32 	%f720, %f23, %f717, %f16;
	mul.f32 	%f721, %f708, 0fBF23A3A9;
	mul.f32 	%f722, %f711, 0fBF23A3A9;
	mul.f32 	%f723, %f714, 0fBF23A3A9;
	fma.rn.f32 	%f107, %f23, %f721, %f718;
	fma.rn.f32 	%f108, %f23, %f722, %f719;
	fma.rn.f32 	%f109, %f23, %f723, %f720;
	sub.f32 	%f724, %f107, %f14;
	sub.f32 	%f725, %f108, %f15;
	sub.f32 	%f726, %f109, %f16;
	mul.f32 	%f727, %f725, %f725;
	fma.rn.f32 	%f728, %f724, %f724, %f727;
	fma.rn.f32 	%f729, %f726, %f726, %f728;
	sqrt.rn.f32 	%f684, %f729;
	rcp.rn.f32 	%f730, %f684;
	mul.f32 	%f680, %f730, %f724;
	mul.f32 	%f681, %f730, %f725;
	mul.f32 	%f682, %f730, %f726;
	mov.f32 	%f685, 0f00000000;
	// begin inline asm
	call(%r590,%r591,%r592,%r593,%r594,%r595,%r596,%r597,%r598,%r599,%r600,%r601,%r602,%r603,%r604,%r605,%r606,%r607,%r608,%r609,%r610,%r611,%r612,%r613,%r614,%r615,%r616,%r617,%r618,%r619,%r620,%r621),_optix_trace_typed_32,(%r515,%rd4,%f14,%f15,%f16,%f680,%f681,%f682,%f438,%f684,%f685,%r482,%r515,%r482,%r481,%r482,%r483,%r486,%r486,%r486,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515,%r515);
	// end inline asm
	mov.b32 	%f731, %r590;
	mov.b32 	%f732, %r591;
	mov.b32 	%f733, %r592;
	setp.neu.f32 	%p75, %f731, 0f3F800000;
	setp.neu.f32 	%p76, %f732, 0f3F800000;
	or.pred  	%p77, %p75, %p76;
	setp.neu.f32 	%p78, %f733, 0f3F800000;
	or.pred  	%p79, %p78, %p77;
	@%p79 bra 	$L__BB0_40;

	mov.f32 	%f741, 0f6C4ECB8F;
	mov.u32 	%r700, 2;
	mov.u32 	%r701, 1;
	mov.u32 	%r702, 3;
	mov.u32 	%r705, 1065353216;
	mov.u32 	%r734, 0;
	// begin inline asm
	call(%r664,%r665,%r666,%r667,%r668,%r669,%r670,%r671,%r672,%r673,%r674,%r675,%r676,%r677,%r678,%r679,%r680,%r681,%r682,%r683,%r684,%r685,%r686,%r687,%r688,%r689,%r690,%r691,%r692,%r693,%r694,%r695),_optix_trace_typed_32,(%r734,%rd4,%f107,%f108,%f109,%f70,%f71,%f72,%f438,%f741,%f685,%r701,%r734,%r701,%r700,%r701,%r702,%r705,%r705,%r705,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734,%r734);
	// end inline asm
	mov.b32 	%f743, %r664;
	mov.b32 	%f744, %r665;
	mov.b32 	%f745, %r666;
	add.f32 	%f1793, %f1793, %f743;
	add.f32 	%f1794, %f1794, %f744;
	add.f32 	%f1795, %f1795, %f745;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_40:
	mad.lo.s32 	%r806, %r51, 1664525, 1013904223;
	and.b32  	%r807, %r806, 16777215;
	cvt.rn.f32.u32 	%f755, %r807;
	mul.f32 	%f756, %f755, 0f33800000;
	fma.rn.f32 	%f757, %f756, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r52, %r806, 1664525, 1013904223;
	and.b32  	%r808, %r52, 16777215;
	cvt.rn.f32.u32 	%f758, %r808;
	mul.f32 	%f759, %f758, 0f33800000;
	fma.rn.f32 	%f760, %f759, 0f40000000, 0fBF800000;
	mul.f32 	%f761, %f17, %f760;
	mul.f32 	%f762, %f18, %f760;
	mul.f32 	%f763, %f19, %f760;
	fma.rn.f32 	%f764, %f20, %f757, %f761;
	fma.rn.f32 	%f765, %f21, %f757, %f762;
	fma.rn.f32 	%f766, %f22, %f757, %f763;
	mul.f32 	%f767, %f765, %f765;
	fma.rn.f32 	%f768, %f764, %f764, %f767;
	fma.rn.f32 	%f769, %f766, %f766, %f768;
	sqrt.rn.f32 	%f770, %f769;
	rcp.rn.f32 	%f771, %f770;
	mul.f32 	%f772, %f764, %f771;
	mul.f32 	%f773, %f765, %f771;
	mul.f32 	%f774, %f766, %f771;
	mul.f32 	%f775, %f1777, %f774;
	mul.f32 	%f776, %f1778, %f773;
	sub.f32 	%f777, %f775, %f776;
	mul.f32 	%f778, %f1778, %f772;
	mul.f32 	%f779, %f1776, %f774;
	sub.f32 	%f780, %f778, %f779;
	mul.f32 	%f781, %f1776, %f773;
	mul.f32 	%f782, %f1777, %f772;
	sub.f32 	%f783, %f781, %f782;
	mul.f32 	%f784, %f772, 0fBF23A3A9;
	mul.f32 	%f785, %f773, 0fBF23A3A9;
	mul.f32 	%f786, %f774, 0fBF23A3A9;
	fma.rn.f32 	%f787, %f23, %f784, %f14;
	fma.rn.f32 	%f788, %f23, %f785, %f15;
	fma.rn.f32 	%f789, %f23, %f786, %f16;
	mul.f32 	%f790, %f777, 0f3F23A3A8;
	mul.f32 	%f791, %f780, 0f3F23A3A8;
	mul.f32 	%f792, %f783, 0f3F23A3A8;
	fma.rn.f32 	%f118, %f23, %f790, %f787;
	fma.rn.f32 	%f119, %f23, %f791, %f788;
	fma.rn.f32 	%f120, %f23, %f792, %f789;
	sub.f32 	%f793, %f118, %f14;
	sub.f32 	%f794, %f119, %f15;
	sub.f32 	%f795, %f120, %f16;
	mul.f32 	%f796, %f794, %f794;
	fma.rn.f32 	%f797, %f793, %f793, %f796;
	fma.rn.f32 	%f798, %f795, %f795, %f797;
	sqrt.rn.f32 	%f753, %f798;
	rcp.rn.f32 	%f799, %f753;
	mul.f32 	%f749, %f799, %f793;
	mul.f32 	%f750, %f799, %f794;
	mul.f32 	%f751, %f799, %f795;
	mov.u32 	%r771, 2;
	mov.u32 	%r772, 1;
	mov.u32 	%r773, 3;
	mov.u32 	%r776, 1065353216;
	mov.u32 	%r805, 0;
	// begin inline asm
	call(%r735,%r736,%r737,%r738,%r739,%r740,%r741,%r742,%r743,%r744,%r745,%r746,%r747,%r748,%r749,%r750,%r751,%r752,%r753,%r754,%r755,%r756,%r757,%r758,%r759,%r760,%r761,%r762,%r763,%r764,%r765,%r766),_optix_trace_typed_32,(%r805,%rd4,%f14,%f15,%f16,%f749,%f750,%f751,%f438,%f753,%f685,%r772,%r805,%r772,%r771,%r772,%r773,%r776,%r776,%r776,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805);
	// end inline asm
	mov.b32 	%f800, %r735;
	mov.b32 	%f801, %r736;
	mov.b32 	%f802, %r737;
	setp.neu.f32 	%p80, %f800, 0f3F800000;
	setp.neu.f32 	%p81, %f801, 0f3F800000;
	or.pred  	%p82, %p80, %p81;
	setp.neu.f32 	%p83, %f802, 0f3F800000;
	or.pred  	%p84, %p83, %p82;
	@%p84 bra 	$L__BB0_42;

	mov.f32 	%f810, 0f6C4ECB8F;
	mov.f32 	%f811, 0f00000000;
	// begin inline asm
	call(%r809,%r810,%r811,%r812,%r813,%r814,%r815,%r816,%r817,%r818,%r819,%r820,%r821,%r822,%r823,%r824,%r825,%r826,%r827,%r828,%r829,%r830,%r831,%r832,%r833,%r834,%r835,%r836,%r837,%r838,%r839,%r840),_optix_trace_typed_32,(%r805,%rd4,%f118,%f119,%f120,%f70,%f71,%f72,%f438,%f810,%f811,%r772,%r805,%r772,%r771,%r772,%r773,%r776,%r776,%r776,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805);
	// end inline asm
	mov.b32 	%f812, %r809;
	mov.b32 	%f813, %r810;
	mov.b32 	%f814, %r811;
	add.f32 	%f1793, %f1793, %f812;
	add.f32 	%f1794, %f1794, %f813;
	add.f32 	%f1795, %f1795, %f814;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_42:
	mad.lo.s32 	%r951, %r52, 1664525, 1013904223;
	and.b32  	%r952, %r951, 16777215;
	cvt.rn.f32.u32 	%f824, %r952;
	mul.f32 	%f825, %f824, 0f33800000;
	fma.rn.f32 	%f826, %f825, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r53, %r951, 1664525, 1013904223;
	and.b32  	%r953, %r53, 16777215;
	cvt.rn.f32.u32 	%f827, %r953;
	mul.f32 	%f828, %f827, 0f33800000;
	fma.rn.f32 	%f829, %f828, 0f40000000, 0fBF800000;
	mul.f32 	%f830, %f17, %f829;
	mul.f32 	%f831, %f18, %f829;
	mul.f32 	%f832, %f19, %f829;
	fma.rn.f32 	%f833, %f20, %f826, %f830;
	fma.rn.f32 	%f834, %f21, %f826, %f831;
	fma.rn.f32 	%f835, %f22, %f826, %f832;
	mul.f32 	%f836, %f834, %f834;
	fma.rn.f32 	%f837, %f833, %f833, %f836;
	fma.rn.f32 	%f838, %f835, %f835, %f837;
	sqrt.rn.f32 	%f839, %f838;
	rcp.rn.f32 	%f840, %f839;
	mul.f32 	%f841, %f833, %f840;
	mul.f32 	%f842, %f834, %f840;
	mul.f32 	%f843, %f835, %f840;
	mul.f32 	%f844, %f1777, %f843;
	mul.f32 	%f845, %f1778, %f842;
	sub.f32 	%f846, %f844, %f845;
	mul.f32 	%f847, %f1778, %f841;
	mul.f32 	%f848, %f1776, %f843;
	sub.f32 	%f849, %f847, %f848;
	mul.f32 	%f850, %f1776, %f842;
	mul.f32 	%f851, %f1777, %f841;
	sub.f32 	%f852, %f850, %f851;
	mul.f32 	%f853, %f841, 0fBF61E1E3;
	mul.f32 	%f854, %f842, 0fBF61E1E3;
	mul.f32 	%f855, %f843, 0fBF61E1E3;
	fma.rn.f32 	%f856, %f23, %f853, %f14;
	fma.rn.f32 	%f857, %f23, %f854, %f15;
	fma.rn.f32 	%f858, %f23, %f855, %f16;
	mul.f32 	%f859, %f846, 0fBE24A490;
	mul.f32 	%f860, %f849, 0fBE24A490;
	mul.f32 	%f861, %f852, 0fBE24A490;
	fma.rn.f32 	%f129, %f23, %f859, %f856;
	fma.rn.f32 	%f130, %f23, %f860, %f857;
	fma.rn.f32 	%f131, %f23, %f861, %f858;
	sub.f32 	%f862, %f129, %f14;
	sub.f32 	%f863, %f130, %f15;
	sub.f32 	%f864, %f131, %f16;
	mul.f32 	%f865, %f863, %f863;
	fma.rn.f32 	%f866, %f862, %f862, %f865;
	fma.rn.f32 	%f867, %f864, %f864, %f866;
	sqrt.rn.f32 	%f822, %f867;
	rcp.rn.f32 	%f868, %f822;
	mul.f32 	%f818, %f868, %f862;
	mul.f32 	%f819, %f868, %f863;
	mul.f32 	%f820, %f868, %f864;
	mov.f32 	%f823, 0f00000000;
	// begin inline asm
	call(%r880,%r881,%r882,%r883,%r884,%r885,%r886,%r887,%r888,%r889,%r890,%r891,%r892,%r893,%r894,%r895,%r896,%r897,%r898,%r899,%r900,%r901,%r902,%r903,%r904,%r905,%r906,%r907,%r908,%r909,%r910,%r911),_optix_trace_typed_32,(%r805,%rd4,%f14,%f15,%f16,%f818,%f819,%f820,%f438,%f822,%f823,%r772,%r805,%r772,%r771,%r772,%r773,%r776,%r776,%r776,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805,%r805);
	// end inline asm
	mov.b32 	%f869, %r880;
	mov.b32 	%f870, %r881;
	mov.b32 	%f871, %r882;
	setp.neu.f32 	%p85, %f869, 0f3F800000;
	setp.neu.f32 	%p86, %f870, 0f3F800000;
	or.pred  	%p87, %p85, %p86;
	setp.neu.f32 	%p88, %f871, 0f3F800000;
	or.pred  	%p89, %p88, %p87;
	@%p89 bra 	$L__BB0_44;

	mov.f32 	%f879, 0f6C4ECB8F;
	mov.u32 	%r990, 2;
	mov.u32 	%r991, 1;
	mov.u32 	%r992, 3;
	mov.u32 	%r995, 1065353216;
	mov.u32 	%r1024, 0;
	// begin inline asm
	call(%r954,%r955,%r956,%r957,%r958,%r959,%r960,%r961,%r962,%r963,%r964,%r965,%r966,%r967,%r968,%r969,%r970,%r971,%r972,%r973,%r974,%r975,%r976,%r977,%r978,%r979,%r980,%r981,%r982,%r983,%r984,%r985),_optix_trace_typed_32,(%r1024,%rd4,%f129,%f130,%f131,%f70,%f71,%f72,%f438,%f879,%f823,%r991,%r1024,%r991,%r990,%r991,%r992,%r995,%r995,%r995,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024,%r1024);
	// end inline asm
	mov.b32 	%f881, %r954;
	mov.b32 	%f882, %r955;
	mov.b32 	%f883, %r956;
	add.f32 	%f1793, %f1793, %f881;
	add.f32 	%f1794, %f1794, %f882;
	add.f32 	%f1795, %f1795, %f883;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_44:
	mad.lo.s32 	%r1096, %r53, 1664525, 1013904223;
	and.b32  	%r1097, %r1096, 16777215;
	cvt.rn.f32.u32 	%f893, %r1097;
	mul.f32 	%f894, %f893, 0f33800000;
	fma.rn.f32 	%f895, %f894, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r54, %r1096, 1664525, 1013904223;
	and.b32  	%r1098, %r54, 16777215;
	cvt.rn.f32.u32 	%f896, %r1098;
	mul.f32 	%f897, %f896, 0f33800000;
	fma.rn.f32 	%f898, %f897, 0f40000000, 0fBF800000;
	mul.f32 	%f899, %f17, %f898;
	mul.f32 	%f900, %f18, %f898;
	mul.f32 	%f901, %f19, %f898;
	fma.rn.f32 	%f902, %f20, %f895, %f899;
	fma.rn.f32 	%f903, %f21, %f895, %f900;
	fma.rn.f32 	%f904, %f22, %f895, %f901;
	mul.f32 	%f905, %f903, %f903;
	fma.rn.f32 	%f906, %f902, %f902, %f905;
	fma.rn.f32 	%f907, %f904, %f904, %f906;
	sqrt.rn.f32 	%f908, %f907;
	rcp.rn.f32 	%f909, %f908;
	mul.f32 	%f910, %f902, %f909;
	mul.f32 	%f911, %f903, %f909;
	mul.f32 	%f912, %f904, %f909;
	mul.f32 	%f913, %f1777, %f912;
	mul.f32 	%f914, %f1778, %f911;
	sub.f32 	%f915, %f913, %f914;
	mul.f32 	%f916, %f1778, %f910;
	mul.f32 	%f917, %f1776, %f912;
	sub.f32 	%f918, %f916, %f917;
	mul.f32 	%f919, %f1776, %f911;
	mul.f32 	%f920, %f1777, %f910;
	sub.f32 	%f921, %f919, %f920;
	mul.f32 	%f922, %f910, 0f3ECACABC;
	mul.f32 	%f923, %f911, 0f3ECACABC;
	mul.f32 	%f924, %f912, 0f3ECACABC;
	fma.rn.f32 	%f925, %f23, %f922, %f14;
	fma.rn.f32 	%f926, %f23, %f923, %f15;
	fma.rn.f32 	%f927, %f23, %f924, %f16;
	mul.f32 	%f928, %f915, 0f3F61E1D2;
	mul.f32 	%f929, %f918, 0f3F61E1D2;
	mul.f32 	%f930, %f921, 0f3F61E1D2;
	fma.rn.f32 	%f140, %f23, %f928, %f925;
	fma.rn.f32 	%f141, %f23, %f929, %f926;
	fma.rn.f32 	%f142, %f23, %f930, %f927;
	sub.f32 	%f931, %f140, %f14;
	sub.f32 	%f932, %f141, %f15;
	sub.f32 	%f933, %f142, %f16;
	mul.f32 	%f934, %f932, %f932;
	fma.rn.f32 	%f935, %f931, %f931, %f934;
	fma.rn.f32 	%f936, %f933, %f933, %f935;
	sqrt.rn.f32 	%f891, %f936;
	rcp.rn.f32 	%f937, %f891;
	mul.f32 	%f887, %f937, %f931;
	mul.f32 	%f888, %f937, %f932;
	mul.f32 	%f889, %f937, %f933;
	mov.u32 	%r1061, 2;
	mov.u32 	%r1062, 1;
	mov.u32 	%r1063, 3;
	mov.u32 	%r1066, 1065353216;
	mov.u32 	%r1095, 0;
	// begin inline asm
	call(%r1025,%r1026,%r1027,%r1028,%r1029,%r1030,%r1031,%r1032,%r1033,%r1034,%r1035,%r1036,%r1037,%r1038,%r1039,%r1040,%r1041,%r1042,%r1043,%r1044,%r1045,%r1046,%r1047,%r1048,%r1049,%r1050,%r1051,%r1052,%r1053,%r1054,%r1055,%r1056),_optix_trace_typed_32,(%r1095,%rd4,%f14,%f15,%f16,%f887,%f888,%f889,%f438,%f891,%f823,%r1062,%r1095,%r1062,%r1061,%r1062,%r1063,%r1066,%r1066,%r1066,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095);
	// end inline asm
	mov.b32 	%f938, %r1025;
	mov.b32 	%f939, %r1026;
	mov.b32 	%f940, %r1027;
	setp.neu.f32 	%p90, %f938, 0f3F800000;
	setp.neu.f32 	%p91, %f939, 0f3F800000;
	or.pred  	%p92, %p90, %p91;
	setp.neu.f32 	%p93, %f940, 0f3F800000;
	or.pred  	%p94, %p93, %p92;
	@%p94 bra 	$L__BB0_46;

	mov.f32 	%f948, 0f6C4ECB8F;
	mov.f32 	%f949, 0f00000000;
	// begin inline asm
	call(%r1099,%r1100,%r1101,%r1102,%r1103,%r1104,%r1105,%r1106,%r1107,%r1108,%r1109,%r1110,%r1111,%r1112,%r1113,%r1114,%r1115,%r1116,%r1117,%r1118,%r1119,%r1120,%r1121,%r1122,%r1123,%r1124,%r1125,%r1126,%r1127,%r1128,%r1129,%r1130),_optix_trace_typed_32,(%r1095,%rd4,%f140,%f141,%f142,%f70,%f71,%f72,%f438,%f948,%f949,%r1062,%r1095,%r1062,%r1061,%r1062,%r1063,%r1066,%r1066,%r1066,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095);
	// end inline asm
	mov.b32 	%f950, %r1099;
	mov.b32 	%f951, %r1100;
	mov.b32 	%f952, %r1101;
	add.f32 	%f1793, %f1793, %f950;
	add.f32 	%f1794, %f1794, %f951;
	add.f32 	%f1795, %f1795, %f952;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_46:
	mad.lo.s32 	%r1241, %r54, 1664525, 1013904223;
	and.b32  	%r1242, %r1241, 16777215;
	cvt.rn.f32.u32 	%f962, %r1242;
	mul.f32 	%f963, %f962, 0f33800000;
	fma.rn.f32 	%f964, %f963, 0f40000000, 0fBF800000;
	mad.lo.s32 	%r1531, %r1241, 1664525, 1013904223;
	and.b32  	%r1243, %r1531, 16777215;
	cvt.rn.f32.u32 	%f965, %r1243;
	mul.f32 	%f966, %f965, 0f33800000;
	fma.rn.f32 	%f967, %f966, 0f40000000, 0fBF800000;
	mul.f32 	%f968, %f17, %f967;
	mul.f32 	%f969, %f18, %f967;
	mul.f32 	%f970, %f19, %f967;
	fma.rn.f32 	%f971, %f20, %f964, %f968;
	fma.rn.f32 	%f972, %f21, %f964, %f969;
	fma.rn.f32 	%f973, %f22, %f964, %f970;
	mul.f32 	%f974, %f972, %f972;
	fma.rn.f32 	%f975, %f971, %f971, %f974;
	fma.rn.f32 	%f976, %f973, %f973, %f975;
	sqrt.rn.f32 	%f977, %f976;
	rcp.rn.f32 	%f978, %f977;
	mul.f32 	%f979, %f971, %f978;
	mul.f32 	%f980, %f972, %f978;
	mul.f32 	%f981, %f973, %f978;
	mul.f32 	%f982, %f1777, %f981;
	mul.f32 	%f983, %f1778, %f980;
	sub.f32 	%f984, %f982, %f983;
	mul.f32 	%f985, %f1778, %f979;
	mul.f32 	%f986, %f1776, %f981;
	sub.f32 	%f987, %f985, %f986;
	mul.f32 	%f988, %f1776, %f980;
	mul.f32 	%f989, %f1777, %f979;
	sub.f32 	%f990, %f988, %f989;
	mul.f32 	%f991, %f979, 0f3F61E1D2;
	mul.f32 	%f992, %f980, 0f3F61E1D2;
	mul.f32 	%f993, %f981, 0f3F61E1D2;
	fma.rn.f32 	%f994, %f23, %f991, %f14;
	fma.rn.f32 	%f995, %f23, %f992, %f15;
	fma.rn.f32 	%f996, %f23, %f993, %f16;
	mul.f32 	%f997, %f984, 0fBF61E1E3;
	mul.f32 	%f998, %f987, 0fBF61E1E3;
	mul.f32 	%f999, %f990, 0fBF61E1E3;
	fma.rn.f32 	%f151, %f23, %f997, %f994;
	fma.rn.f32 	%f152, %f23, %f998, %f995;
	fma.rn.f32 	%f153, %f23, %f999, %f996;
	sub.f32 	%f1000, %f151, %f14;
	sub.f32 	%f1001, %f152, %f15;
	sub.f32 	%f1002, %f153, %f16;
	mul.f32 	%f1003, %f1001, %f1001;
	fma.rn.f32 	%f1004, %f1000, %f1000, %f1003;
	fma.rn.f32 	%f1005, %f1002, %f1002, %f1004;
	sqrt.rn.f32 	%f960, %f1005;
	rcp.rn.f32 	%f1006, %f960;
	mul.f32 	%f956, %f1006, %f1000;
	mul.f32 	%f957, %f1006, %f1001;
	mul.f32 	%f958, %f1006, %f1002;
	mov.f32 	%f961, 0f00000000;
	// begin inline asm
	call(%r1170,%r1171,%r1172,%r1173,%r1174,%r1175,%r1176,%r1177,%r1178,%r1179,%r1180,%r1181,%r1182,%r1183,%r1184,%r1185,%r1186,%r1187,%r1188,%r1189,%r1190,%r1191,%r1192,%r1193,%r1194,%r1195,%r1196,%r1197,%r1198,%r1199,%r1200,%r1201),_optix_trace_typed_32,(%r1095,%rd4,%f14,%f15,%f16,%f956,%f957,%f958,%f438,%f960,%f961,%r1062,%r1095,%r1062,%r1061,%r1062,%r1063,%r1066,%r1066,%r1066,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095,%r1095);
	// end inline asm
	mov.b32 	%f1007, %r1170;
	mov.b32 	%f1008, %r1171;
	mov.b32 	%f1009, %r1172;
	setp.neu.f32 	%p95, %f1007, 0f3F800000;
	setp.neu.f32 	%p96, %f1008, 0f3F800000;
	or.pred  	%p97, %p95, %p96;
	setp.neu.f32 	%p98, %f1009, 0f3F800000;
	or.pred  	%p99, %p98, %p97;
	@%p99 bra 	$L__BB0_48;

	mov.f32 	%f1017, 0f6C4ECB8F;
	mov.u32 	%r1280, 2;
	mov.u32 	%r1281, 1;
	mov.u32 	%r1282, 3;
	mov.u32 	%r1285, 1065353216;
	mov.u32 	%r1314, 0;
	// begin inline asm
	call(%r1244,%r1245,%r1246,%r1247,%r1248,%r1249,%r1250,%r1251,%r1252,%r1253,%r1254,%r1255,%r1256,%r1257,%r1258,%r1259,%r1260,%r1261,%r1262,%r1263,%r1264,%r1265,%r1266,%r1267,%r1268,%r1269,%r1270,%r1271,%r1272,%r1273,%r1274,%r1275),_optix_trace_typed_32,(%r1314,%rd4,%f151,%f152,%f153,%f70,%f71,%f72,%f438,%f1017,%f961,%r1281,%r1314,%r1281,%r1280,%r1281,%r1282,%r1285,%r1285,%r1285,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314,%r1314);
	// end inline asm
	mov.b32 	%f1019, %r1244;
	mov.b32 	%f1020, %r1245;
	mov.b32 	%f1021, %r1246;
	add.f32 	%f1793, %f1793, %f1019;
	add.f32 	%f1794, %f1794, %f1020;
	add.f32 	%f1795, %f1795, %f1021;
	add.f32 	%f1796, %f1796, 0f3F800000;
	mov.u16 	%rs196, 1;

$L__BB0_48:
	setp.ne.s16 	%p100, %rs196, 0;
	@%p100 bra 	$L__BB0_50;

	mov.f32 	%f1029, 0f6C4ECB8F;
	mov.f32 	%f1030, 0f00000000;
	mov.u32 	%r1351, 2;
	mov.u32 	%r1352, 1;
	mov.u32 	%r1353, 3;
	mov.u32 	%r1356, 1065353216;
	mov.u32 	%r1385, 0;
	// begin inline asm
	call(%r1315,%r1316,%r1317,%r1318,%r1319,%r1320,%r1321,%r1322,%r1323,%r1324,%r1325,%r1326,%r1327,%r1328,%r1329,%r1330,%r1331,%r1332,%r1333,%r1334,%r1335,%r1336,%r1337,%r1338,%r1339,%r1340,%r1341,%r1342,%r1343,%r1344,%r1345,%r1346),_optix_trace_typed_32,(%r1385,%rd4,%f14,%f15,%f16,%f70,%f71,%f72,%f438,%f1029,%f1030,%r1352,%r1385,%r1352,%r1351,%r1352,%r1353,%r1356,%r1356,%r1356,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385,%r1385);
	// end inline asm
	mov.b32 	%f1031, %r1315;
	mov.b32 	%f1032, %r1316;
	mov.b32 	%f1033, %r1317;
	add.f32 	%f1793, %f1793, %f1031;
	add.f32 	%f1794, %f1794, %f1032;
	add.f32 	%f1795, %f1795, %f1033;
	add.f32 	%f1796, %f1796, 0f3F800000;

$L__BB0_50:
	add.s32 	%r1530, %r1530, 1;
	setp.lt.s32 	%p101, %r1530, %r7;
	@%p101 bra 	$L__BB0_8;

	add.s32 	%r1528, %r1528, 1;
	setp.lt.s32 	%p102, %r1528, %r7;
	@%p102 bra 	$L__BB0_7;

$L__BB0_52:
	setp.eq.s32 	%p103, %r7, 0;
	mov.f32 	%f1833, 0f3F800000;
	mov.f32 	%f1834, %f1833;
	mov.f32 	%f1835, %f1833;
	@%p103 bra 	$L__BB0_54;

	mov.f32 	%f1037, 0f3F800000;
	max.f32 	%f1038, %f1796, %f1037;
	rcp.rn.f32 	%f1039, %f1038;
	mul.f32 	%f1833, %f1793, %f1039;
	mul.f32 	%f1834, %f1794, %f1039;
	mul.f32 	%f1835, %f1795, %f1039;

$L__BB0_54:
	ld.const.f32 	%f1040, [params+524];
	mul.f32 	%f1041, %f1833, %f1040;
	ld.const.v2.f32 	{%f1042, %f1043}, [params+528];
	mul.f32 	%f1046, %f1834, %f1042;
	mul.f32 	%f1047, %f1835, %f1043;
	cvt.sat.f32.f32 	%f1048, %f13;
	mul.f32 	%f180, %f1041, %f1048;
	mul.f32 	%f181, %f1046, %f1048;
	mul.f32 	%f182, %f1047, %f1048;
	mul.f32 	%f1049, %f13, 0f40800000;
	cvt.sat.f32.f32 	%f1050, %f1049;
	mul.f32 	%f1051, %f1041, %f1050;
	mul.f32 	%f1052, %f1046, %f1050;
	mul.f32 	%f1053, %f1047, %f1050;
	mul.f32 	%f183, %f1051, 0f3E800000;
	mul.f32 	%f184, %f1052, 0f3E800000;
	mul.f32 	%f185, %f1053, 0f3E800000;
	ld.const.u32 	%r58, [params+104];
	and.b32  	%r1386, %r58, 8;
	setp.eq.s32 	%p104, %r1386, 0;
	@%p104 bra 	$L__BB0_68;

	ld.const.u64 	%rd86, [params+192];
	cvta.to.global.u64 	%rd16, %rd86;
	ld.const.u32 	%r1387, [params+184];
	mad.lo.s32 	%r1388, %r1387, %r6, %r5;
	cvt.u64.u32 	%rd17, %r1388;
	mov.f32 	%f1055, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1056, %f1055;
	add.f32 	%f1057, %f1056, %f1056;
	mov.f32 	%f1058, 0f3EE8BA2E;
	sub.f32 	%f1059, %f1058, %f1057;
	abs.f32 	%f186, %f1059;
	abs.f32 	%f187, %f1833;
	setp.lt.f32 	%p105, %f187, 0f00800000;
	mul.f32 	%f1060, %f187, 0f4B800000;
	selp.f32 	%f1061, %f1060, %f187, %p105;
	selp.f32 	%f1062, 0fC3170000, 0fC2FE0000, %p105;
	mov.b32 	%r1389, %f1061;
	and.b32  	%r1390, %r1389, 8388607;
	or.b32  	%r1391, %r1390, 1065353216;
	mov.b32 	%f1063, %r1391;
	shr.u32 	%r1392, %r1389, 23;
	cvt.rn.f32.u32 	%f1064, %r1392;
	add.f32 	%f1065, %f1062, %f1064;
	setp.gt.f32 	%p106, %f1063, 0f3FB504F3;
	mul.f32 	%f1066, %f1063, 0f3F000000;
	add.f32 	%f1067, %f1065, 0f3F800000;
	selp.f32 	%f1068, %f1067, %f1065, %p106;
	selp.f32 	%f1069, %f1066, %f1063, %p106;
	add.f32 	%f1070, %f1069, 0fBF800000;
	add.f32 	%f1071, %f1069, 0f3F800000;
	rcp.approx.ftz.f32 	%f1072, %f1071;
	add.f32 	%f1073, %f1070, %f1070;
	mul.f32 	%f1074, %f1073, %f1072;
	mul.f32 	%f1075, %f1074, %f1074;
	mov.f32 	%f1076, 0f3C4CAF63;
	mov.f32 	%f1077, 0f3B18F0FE;
	fma.rn.f32 	%f1078, %f1077, %f1075, %f1076;
	mov.f32 	%f1079, 0f3DAAAABD;
	fma.rn.f32 	%f1080, %f1078, %f1075, %f1079;
	mul.rn.f32 	%f1081, %f1080, %f1075;
	mul.rn.f32 	%f1082, %f1081, %f1074;
	sub.f32 	%f1083, %f1070, %f1074;
	add.f32 	%f1084, %f1083, %f1083;
	neg.f32 	%f1085, %f1074;
	fma.rn.f32 	%f1086, %f1085, %f1070, %f1084;
	mul.rn.f32 	%f1087, %f1072, %f1086;
	add.f32 	%f1088, %f1082, %f1074;
	sub.f32 	%f1089, %f1074, %f1088;
	add.f32 	%f1090, %f1082, %f1089;
	add.f32 	%f1091, %f1087, %f1090;
	add.f32 	%f1092, %f1088, %f1091;
	sub.f32 	%f1093, %f1088, %f1092;
	add.f32 	%f1094, %f1091, %f1093;
	mov.f32 	%f1095, 0f3F317200;
	mul.rn.f32 	%f1096, %f1068, %f1095;
	mov.f32 	%f1097, 0f35BFBE8E;
	mul.rn.f32 	%f1098, %f1068, %f1097;
	add.f32 	%f1099, %f1096, %f1092;
	sub.f32 	%f1100, %f1096, %f1099;
	add.f32 	%f1101, %f1092, %f1100;
	add.f32 	%f1102, %f1094, %f1101;
	add.f32 	%f1103, %f1098, %f1102;
	add.f32 	%f1104, %f1099, %f1103;
	sub.f32 	%f1105, %f1099, %f1104;
	add.f32 	%f1106, %f1103, %f1105;
	mul.rn.f32 	%f1107, %f1058, %f1104;
	neg.f32 	%f1108, %f1107;
	fma.rn.f32 	%f1109, %f1058, %f1104, %f1108;
	fma.rn.f32 	%f1110, %f1058, %f1106, %f1109;
	mov.f32 	%f1111, 0f00000000;
	fma.rn.f32 	%f1112, %f1111, %f1104, %f1110;
	add.rn.f32 	%f1113, %f1107, %f1112;
	neg.f32 	%f1114, %f1113;
	add.rn.f32 	%f1115, %f1107, %f1114;
	add.rn.f32 	%f1116, %f1115, %f1112;
	mov.b32 	%r1393, %f1113;
	setp.eq.s32 	%p107, %r1393, 1118925336;
	add.s32 	%r1394, %r1393, -1;
	mov.b32 	%f1117, %r1394;
	add.f32 	%f1118, %f1116, 0f37000000;
	selp.f32 	%f188, %f1118, %f1116, %p107;
	selp.f32 	%f1119, %f1117, %f1113, %p107;
	mov.f32 	%f1120, 0f3FB8AA3B;
	mul.rn.f32 	%f1121, %f1119, %f1120;
	cvt.rzi.f32.f32 	%f1122, %f1121;
	abs.f32 	%f1123, %f1122;
	setp.gt.f32 	%p108, %f1123, 0f42FC0000;
	mov.b32 	%r1395, %f1122;
	and.b32  	%r1396, %r1395, -2147483648;
	or.b32  	%r1397, %r1396, 1123811328;
	mov.b32 	%f1124, %r1397;
	selp.f32 	%f1125, %f1124, %f1122, %p108;
	mov.f32 	%f1126, 0fBF317218;
	fma.rn.f32 	%f1127, %f1125, %f1126, %f1119;
	mov.f32 	%f1128, 0f3102E308;
	fma.rn.f32 	%f1129, %f1125, %f1128, %f1127;
	mul.f32 	%f1130, %f1129, 0f3FB8AA3B;
	add.f32 	%f1131, %f1125, 0f4B40007F;
	mov.b32 	%r1398, %f1131;
	shl.b32 	%r1399, %r1398, 23;
	mov.b32 	%f1132, %r1399;
	ex2.approx.ftz.f32 	%f1133, %f1130;
	mul.f32 	%f189, %f1133, %f1132;
	setp.eq.f32 	%p109, %f189, 0f7F800000;
	mov.f32 	%f1836, 0f7F800000;
	@%p109 bra 	$L__BB0_57;

	fma.rn.f32 	%f1836, %f189, %f188, %f189;

$L__BB0_57:
	setp.lt.f32 	%p110, %f1833, 0f00000000;
	setp.eq.f32 	%p111, %f186, 0f3F800000;
	and.pred  	%p1, %p110, %p111;
	setp.eq.f32 	%p112, %f1833, 0f00000000;
	@%p112 bra 	$L__BB0_61;
	bra.uni 	$L__BB0_58;

$L__BB0_61:
	add.f32 	%f1138, %f1833, %f1833;
	selp.f32 	%f1838, %f1138, 0f00000000, %p111;
	bra.uni 	$L__BB0_62;

$L__BB0_165:
	mov.f32 	%f1738, 0f00000000;
	mov.u32 	%r1540, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs131, %f1738;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1738;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1738;}

	// end inline asm
	mov.u16 	%rs132, 0;
	st.global.v4.u16 	[%rd25], {%rs129, %rs130, %rs131, %rs132};

$L__BB0_166:
	ld.const.u64 	%rd118, [params+256];
	cvta.to.global.u64 	%rd119, %rd118;
	ld.const.u32 	%r1520, [params+248];
	mad.lo.s32 	%r1521, %r1520, %r6, %r5;
	mul.wide.u32 	%rd120, %r1521, 8;
	add.s64 	%rd26, %rd119, %rd120;
	setp.eq.s32 	%p230, %r1540, 0;
	@%p230 bra 	$L__BB0_168;

	ld.global.v4.u16 	{%rs139, %rs140, %rs141, %rs142}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1739, %rs139;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1740, %rs140;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1741, %rs141;}

	// end inline asm
	add.f32 	%f1742, %f1739, 0f00000000;
	add.f32 	%f1743, %f1740, 0f00000000;
	add.f32 	%f1744, %f1741, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f1744;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1743;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1742;}

	// end inline asm
	mov.u16 	%rs143, 0;
	st.global.v4.u16 	[%rd26], {%rs136, %rs137, %rs138, %rs143};
	bra.uni 	$L__BB0_169;

$L__BB0_168:
	mov.f32 	%f1747, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs146, %f1747;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1747;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1747;}

	// end inline asm
	mov.u16 	%rs147, 0;
	st.global.v4.u16 	[%rd26], {%rs144, %rs145, %rs146, %rs147};

$L__BB0_169:
	ld.const.u64 	%rd121, [params+272];
	cvta.to.global.u64 	%rd122, %rd121;
	ld.const.u32 	%r1522, [params+264];
	mad.lo.s32 	%r1523, %r1522, %r6, %r5;
	mul.wide.u32 	%rd123, %r1523, 8;
	add.s64 	%rd27, %rd122, %rd123;
	@%p230 bra 	$L__BB0_171;

	ld.global.v4.u16 	{%rs154, %rs155, %rs156, %rs157}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1748, %rs154;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1749, %rs155;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1750, %rs156;}

	// end inline asm
	add.f32 	%f1751, %f1748, 0f00000000;
	add.f32 	%f1752, %f1749, 0f00000000;
	add.f32 	%f1753, %f1750, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f1753;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1752;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1751;}

	// end inline asm
	mov.u16 	%rs158, 0;
	st.global.v4.u16 	[%rd27], {%rs151, %rs152, %rs153, %rs158};
	bra.uni 	$L__BB0_172;

$L__BB0_171:
	mov.f32 	%f1756, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs161, %f1756;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1756;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1756;}

	// end inline asm
	mov.u16 	%rs162, 0;
	st.global.v4.u16 	[%rd27], {%rs159, %rs160, %rs161, %rs162};

$L__BB0_172:
	ld.const.u64 	%rd124, [params+288];
	cvta.to.global.u64 	%rd125, %rd124;
	ld.const.u32 	%r1524, [params+280];
	mad.lo.s32 	%r1525, %r1524, %r6, %r5;
	mul.wide.u32 	%rd126, %r1525, 8;
	add.s64 	%rd28, %rd125, %rd126;
	@%p230 bra 	$L__BB0_174;

	ld.global.v4.u16 	{%rs169, %rs170, %rs171, %rs172}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1757, %rs169;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1758, %rs170;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1759, %rs171;}

	// end inline asm
	add.f32 	%f1760, %f1757, 0f00000000;
	add.f32 	%f1761, %f1758, 0f00000000;
	add.f32 	%f1762, %f1759, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f1762;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1761;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1760;}

	// end inline asm
	mov.u16 	%rs173, 0;
	st.global.v4.u16 	[%rd28], {%rs166, %rs167, %rs168, %rs173};
	bra.uni 	$L__BB0_175;

$L__BB0_174:
	mov.f32 	%f1765, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs176, %f1765;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1765;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1765;}

	// end inline asm
	mov.u16 	%rs177, 0;
	st.global.v4.u16 	[%rd28], {%rs174, %rs175, %rs176, %rs177};

$L__BB0_175:
	ld.const.u64 	%rd127, [params+304];
	cvta.to.global.u64 	%rd128, %rd127;
	ld.const.u32 	%r1526, [params+296];
	mad.lo.s32 	%r1527, %r1526, %r6, %r5;
	mul.wide.u32 	%rd129, %r1527, 8;
	add.s64 	%rd29, %rd128, %rd129;
	@%p230 bra 	$L__BB0_177;

	ld.global.v4.u16 	{%rs184, %rs185, %rs186, %rs187}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1766, %rs184;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1767, %rs185;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1768, %rs186;}

	// end inline asm
	add.f32 	%f1769, %f1766, 0f00000000;
	add.f32 	%f1770, %f1767, 0f00000000;
	add.f32 	%f1771, %f1768, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs183, %f1771;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs182, %f1770;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs181, %f1769;}

	// end inline asm
	mov.u16 	%rs188, 0;
	st.global.v4.u16 	[%rd29], {%rs181, %rs182, %rs183, %rs188};
	bra.uni 	$L__BB0_178;

$L__BB0_177:
	mov.f32 	%f1774, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs191, %f1774;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs190, %f1774;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs189, %f1774;}

	// end inline asm
	mov.u16 	%rs192, 0;
	st.global.v4.u16 	[%rd29], {%rs189, %rs190, %rs191, %rs192};
	bra.uni 	$L__BB0_178;

$L__BB0_58:
	mov.b32 	%r1400, %f1836;
	xor.b32  	%r1401, %r1400, -2147483648;
	mov.b32 	%f1134, %r1401;
	selp.f32 	%f1838, %f1134, %f1836, %p1;
	setp.geu.f32 	%p113, %f1833, 0f00000000;
	@%p113 bra 	$L__BB0_62;

	mov.f32 	%f1135, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f1136, %f1135;
	setp.eq.f32 	%p114, %f1136, 0f3EE8BA2E;
	@%p114 bra 	$L__BB0_62;

	mov.f32 	%f1838, 0f7FFFFFFF;

$L__BB0_62:
	add.f32 	%f1139, %f187, 0f3EE8BA2E;
	mov.b32 	%r1402, %f1139;
	setp.lt.s32 	%p116, %r1402, 2139095040;
	@%p116 bra 	$L__BB0_67;

	setp.gtu.f32 	%p117, %f187, 0f7F800000;
	@%p117 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_64;

$L__BB0_66:
	add.f32 	%f1838, %f1833, 0f3EE8BA2E;
	bra.uni 	$L__BB0_67;

$L__BB0_64:
	setp.neu.f32 	%p118, %f187, 0f7F800000;
	@%p118 bra 	$L__BB0_67;

	selp.f32 	%f1838, 0fFF800000, 0f7F800000, %p1;

$L__BB0_67:
	mul.f32 	%f1140, %f1838, 0f437F0000;
	setp.eq.f32 	%p119, %f1833, 0f3F800000;
	selp.f32 	%f1141, 0f437F0000, %f1140, %p119;
	cvt.rzi.u32.f32 	%r1403, %f1141;
	shl.b64 	%rd87, %rd17, 1;
	add.s64 	%rd88, %rd16, %rd87;
	cvt.u16.u32 	%rs34, %r1403;
	mov.u16 	%rs35, 255;
	st.global.v2.u8 	[%rd88], {%rs34, %rs35};

$L__BB0_68:
	and.b32  	%r1404, %r58, 1;
	setp.eq.b32 	%p120, %r1404, 1;
	mov.pred 	%p121, 0;
	xor.pred  	%p122, %p120, %p121;
	not.pred 	%p123, %p122;
	@%p123 bra 	$L__BB0_142;

	mov.f32 	%f1143, 0f3E666666;
	cvt.rzi.f32.f32 	%f1144, %f1143;
	add.f32 	%f1145, %f1144, %f1144;
	mov.f32 	%f1146, 0f3EE66666;
	sub.f32 	%f1147, %f1146, %f1145;
	abs.f32 	%f198, %f1147;
	abs.f32 	%f199, %f180;
	setp.lt.f32 	%p124, %f199, 0f00800000;
	mul.f32 	%f1148, %f199, 0f4B800000;
	selp.f32 	%f1149, %f1148, %f199, %p124;
	selp.f32 	%f1150, 0fC3170000, 0fC2FE0000, %p124;
	mov.b32 	%r1405, %f1149;
	and.b32  	%r1406, %r1405, 8388607;
	or.b32  	%r1407, %r1406, 1065353216;
	mov.b32 	%f1151, %r1407;
	shr.u32 	%r1408, %r1405, 23;
	cvt.rn.f32.u32 	%f1152, %r1408;
	add.f32 	%f1153, %f1150, %f1152;
	setp.gt.f32 	%p125, %f1151, 0f3FB504F3;
	mul.f32 	%f1154, %f1151, 0f3F000000;
	add.f32 	%f1155, %f1153, 0f3F800000;
	selp.f32 	%f1156, %f1155, %f1153, %p125;
	selp.f32 	%f1157, %f1154, %f1151, %p125;
	add.f32 	%f1158, %f1157, 0fBF800000;
	add.f32 	%f1159, %f1157, 0f3F800000;
	rcp.approx.ftz.f32 	%f1160, %f1159;
	add.f32 	%f1161, %f1158, %f1158;
	mul.f32 	%f1162, %f1161, %f1160;
	mul.f32 	%f1163, %f1162, %f1162;
	mov.f32 	%f1164, 0f3C4CAF63;
	mov.f32 	%f1165, 0f3B18F0FE;
	fma.rn.f32 	%f1166, %f1165, %f1163, %f1164;
	mov.f32 	%f1167, 0f3DAAAABD;
	fma.rn.f32 	%f1168, %f1166, %f1163, %f1167;
	mul.rn.f32 	%f1169, %f1168, %f1163;
	mul.rn.f32 	%f1170, %f1169, %f1162;
	sub.f32 	%f1171, %f1158, %f1162;
	add.f32 	%f1172, %f1171, %f1171;
	neg.f32 	%f1173, %f1162;
	fma.rn.f32 	%f1174, %f1173, %f1158, %f1172;
	mul.rn.f32 	%f1175, %f1160, %f1174;
	add.f32 	%f1176, %f1170, %f1162;
	sub.f32 	%f1177, %f1162, %f1176;
	add.f32 	%f1178, %f1170, %f1177;
	add.f32 	%f1179, %f1175, %f1178;
	add.f32 	%f1180, %f1176, %f1179;
	sub.f32 	%f1181, %f1176, %f1180;
	add.f32 	%f1182, %f1179, %f1181;
	mov.f32 	%f1183, 0f3F317200;
	mul.rn.f32 	%f1184, %f1156, %f1183;
	mov.f32 	%f1185, 0f35BFBE8E;
	mul.rn.f32 	%f1186, %f1156, %f1185;
	add.f32 	%f1187, %f1184, %f1180;
	sub.f32 	%f1188, %f1184, %f1187;
	add.f32 	%f1189, %f1180, %f1188;
	add.f32 	%f1190, %f1182, %f1189;
	add.f32 	%f1191, %f1186, %f1190;
	add.f32 	%f1192, %f1187, %f1191;
	sub.f32 	%f1193, %f1187, %f1192;
	add.f32 	%f1194, %f1191, %f1193;
	mul.rn.f32 	%f1195, %f1146, %f1192;
	neg.f32 	%f1196, %f1195;
	fma.rn.f32 	%f1197, %f1146, %f1192, %f1196;
	fma.rn.f32 	%f1198, %f1146, %f1194, %f1197;
	mov.f32 	%f1199, 0f00000000;
	fma.rn.f32 	%f1200, %f1199, %f1192, %f1198;
	add.rn.f32 	%f1201, %f1195, %f1200;
	neg.f32 	%f1202, %f1201;
	add.rn.f32 	%f1203, %f1195, %f1202;
	add.rn.f32 	%f1204, %f1203, %f1200;
	mov.b32 	%r1409, %f1201;
	setp.eq.s32 	%p126, %r1409, 1118925336;
	add.s32 	%r1410, %r1409, -1;
	mov.b32 	%f1205, %r1410;
	add.f32 	%f1206, %f1204, 0f37000000;
	selp.f32 	%f200, %f1206, %f1204, %p126;
	selp.f32 	%f1207, %f1205, %f1201, %p126;
	mov.f32 	%f1208, 0f3FB8AA3B;
	mul.rn.f32 	%f1209, %f1207, %f1208;
	cvt.rzi.f32.f32 	%f1210, %f1209;
	abs.f32 	%f1211, %f1210;
	setp.gt.f32 	%p127, %f1211, 0f42FC0000;
	mov.b32 	%r1411, %f1210;
	and.b32  	%r1412, %r1411, -2147483648;
	or.b32  	%r1413, %r1412, 1123811328;
	mov.b32 	%f1212, %r1413;
	selp.f32 	%f1213, %f1212, %f1210, %p127;
	mov.f32 	%f1214, 0fBF317218;
	fma.rn.f32 	%f1215, %f1213, %f1214, %f1207;
	mov.f32 	%f1216, 0f3102E308;
	fma.rn.f32 	%f1217, %f1213, %f1216, %f1215;
	mul.f32 	%f1218, %f1217, 0f3FB8AA3B;
	add.f32 	%f1219, %f1213, 0f4B40007F;
	mov.b32 	%r1414, %f1219;
	shl.b32 	%r1415, %r1414, 23;
	mov.b32 	%f1220, %r1415;
	ex2.approx.ftz.f32 	%f1221, %f1218;
	mul.f32 	%f201, %f1221, %f1220;
	setp.eq.f32 	%p128, %f201, 0f7F800000;
	mov.f32 	%f1839, 0f7F800000;
	@%p128 bra 	$L__BB0_71;

	fma.rn.f32 	%f1839, %f201, %f200, %f201;

$L__BB0_71:
	setp.lt.f32 	%p129, %f180, 0f00000000;
	setp.eq.f32 	%p130, %f198, 0f3F800000;
	and.pred  	%p2, %p129, %p130;
	setp.eq.f32 	%p131, %f180, 0f00000000;
	@%p131 bra 	$L__BB0_75;
	bra.uni 	$L__BB0_72;

$L__BB0_75:
	add.f32 	%f1226, %f180, %f180;
	selp.f32 	%f1841, %f1226, 0f00000000, %p130;
	bra.uni 	$L__BB0_76;

$L__BB0_72:
	mov.b32 	%r1416, %f1839;
	xor.b32  	%r1417, %r1416, -2147483648;
	mov.b32 	%f1222, %r1417;
	selp.f32 	%f1841, %f1222, %f1839, %p2;
	setp.geu.f32 	%p132, %f180, 0f00000000;
	@%p132 bra 	$L__BB0_76;

	mov.f32 	%f1223, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1224, %f1223;
	setp.eq.f32 	%p133, %f1224, 0f3EE66666;
	@%p133 bra 	$L__BB0_76;

	mov.f32 	%f1841, 0f7FFFFFFF;

$L__BB0_76:
	add.f32 	%f1227, %f199, 0f3EE66666;
	mov.b32 	%r1418, %f1227;
	setp.lt.s32 	%p135, %r1418, 2139095040;
	@%p135 bra 	$L__BB0_81;

	setp.gtu.f32 	%p136, %f199, 0f7F800000;
	@%p136 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_78;

$L__BB0_80:
	add.f32 	%f1841, %f180, 0f3EE66666;
	bra.uni 	$L__BB0_81;

$L__BB0_78:
	setp.neu.f32 	%p137, %f199, 0f7F800000;
	@%p137 bra 	$L__BB0_81;

	selp.f32 	%f1841, 0fFF800000, 0f7F800000, %p2;

$L__BB0_81:
	setp.eq.f32 	%p138, %f180, 0f3F800000;
	selp.f32 	%f210, 0f3F800000, %f1841, %p138;
	abs.f32 	%f211, %f181;
	setp.lt.f32 	%p139, %f211, 0f00800000;
	mul.f32 	%f1229, %f211, 0f4B800000;
	selp.f32 	%f1230, %f1229, %f211, %p139;
	selp.f32 	%f1231, 0fC3170000, 0fC2FE0000, %p139;
	mov.b32 	%r1419, %f1230;
	and.b32  	%r1420, %r1419, 8388607;
	or.b32  	%r1421, %r1420, 1065353216;
	mov.b32 	%f1232, %r1421;
	shr.u32 	%r1422, %r1419, 23;
	cvt.rn.f32.u32 	%f1233, %r1422;
	add.f32 	%f1234, %f1231, %f1233;
	setp.gt.f32 	%p140, %f1232, 0f3FB504F3;
	mul.f32 	%f1235, %f1232, 0f3F000000;
	add.f32 	%f1236, %f1234, 0f3F800000;
	selp.f32 	%f1237, %f1236, %f1234, %p140;
	selp.f32 	%f1238, %f1235, %f1232, %p140;
	add.f32 	%f1239, %f1238, 0fBF800000;
	add.f32 	%f1240, %f1238, 0f3F800000;
	rcp.approx.ftz.f32 	%f1241, %f1240;
	add.f32 	%f1242, %f1239, %f1239;
	mul.f32 	%f1243, %f1242, %f1241;
	mul.f32 	%f1244, %f1243, %f1243;
	mov.f32 	%f1245, 0f3C4CAF63;
	mov.f32 	%f1246, 0f3B18F0FE;
	fma.rn.f32 	%f1247, %f1246, %f1244, %f1245;
	mov.f32 	%f1248, 0f3DAAAABD;
	fma.rn.f32 	%f1249, %f1247, %f1244, %f1248;
	mul.rn.f32 	%f1250, %f1249, %f1244;
	mul.rn.f32 	%f1251, %f1250, %f1243;
	sub.f32 	%f1252, %f1239, %f1243;
	add.f32 	%f1253, %f1252, %f1252;
	neg.f32 	%f1254, %f1243;
	fma.rn.f32 	%f1255, %f1254, %f1239, %f1253;
	mul.rn.f32 	%f1256, %f1241, %f1255;
	add.f32 	%f1257, %f1251, %f1243;
	sub.f32 	%f1258, %f1243, %f1257;
	add.f32 	%f1259, %f1251, %f1258;
	add.f32 	%f1260, %f1256, %f1259;
	add.f32 	%f1261, %f1257, %f1260;
	sub.f32 	%f1262, %f1257, %f1261;
	add.f32 	%f1263, %f1260, %f1262;
	mov.f32 	%f1264, 0f3F317200;
	mul.rn.f32 	%f1265, %f1237, %f1264;
	mov.f32 	%f1266, 0f35BFBE8E;
	mul.rn.f32 	%f1267, %f1237, %f1266;
	add.f32 	%f1268, %f1265, %f1261;
	sub.f32 	%f1269, %f1265, %f1268;
	add.f32 	%f1270, %f1261, %f1269;
	add.f32 	%f1271, %f1263, %f1270;
	add.f32 	%f1272, %f1267, %f1271;
	add.f32 	%f1273, %f1268, %f1272;
	sub.f32 	%f1274, %f1268, %f1273;
	add.f32 	%f1275, %f1272, %f1274;
	mov.f32 	%f1276, 0f3EE66666;
	mul.rn.f32 	%f1277, %f1276, %f1273;
	neg.f32 	%f1278, %f1277;
	fma.rn.f32 	%f1279, %f1276, %f1273, %f1278;
	fma.rn.f32 	%f1280, %f1276, %f1275, %f1279;
	mov.f32 	%f1281, 0f00000000;
	fma.rn.f32 	%f1282, %f1281, %f1273, %f1280;
	add.rn.f32 	%f1283, %f1277, %f1282;
	neg.f32 	%f1284, %f1283;
	add.rn.f32 	%f1285, %f1277, %f1284;
	add.rn.f32 	%f1286, %f1285, %f1282;
	mov.b32 	%r1423, %f1283;
	setp.eq.s32 	%p141, %r1423, 1118925336;
	add.s32 	%r1424, %r1423, -1;
	mov.b32 	%f1287, %r1424;
	add.f32 	%f1288, %f1286, 0f37000000;
	selp.f32 	%f212, %f1288, %f1286, %p141;
	selp.f32 	%f1289, %f1287, %f1283, %p141;
	mov.f32 	%f1290, 0f3FB8AA3B;
	mul.rn.f32 	%f1291, %f1289, %f1290;
	cvt.rzi.f32.f32 	%f1292, %f1291;
	abs.f32 	%f1293, %f1292;
	setp.gt.f32 	%p142, %f1293, 0f42FC0000;
	mov.b32 	%r1425, %f1292;
	and.b32  	%r1426, %r1425, -2147483648;
	or.b32  	%r1427, %r1426, 1123811328;
	mov.b32 	%f1294, %r1427;
	selp.f32 	%f1295, %f1294, %f1292, %p142;
	mov.f32 	%f1296, 0fBF317218;
	fma.rn.f32 	%f1297, %f1295, %f1296, %f1289;
	mov.f32 	%f1298, 0f3102E308;
	fma.rn.f32 	%f1299, %f1295, %f1298, %f1297;
	mul.f32 	%f1300, %f1299, 0f3FB8AA3B;
	add.f32 	%f1301, %f1295, 0f4B40007F;
	mov.b32 	%r1428, %f1301;
	shl.b32 	%r1429, %r1428, 23;
	mov.b32 	%f1302, %r1429;
	ex2.approx.ftz.f32 	%f1303, %f1300;
	mul.f32 	%f213, %f1303, %f1302;
	setp.eq.f32 	%p143, %f213, 0f7F800000;
	mov.f32 	%f1842, 0f7F800000;
	@%p143 bra 	$L__BB0_83;

	fma.rn.f32 	%f1842, %f213, %f212, %f213;

$L__BB0_83:
	setp.lt.f32 	%p144, %f181, 0f00000000;
	and.pred  	%p3, %p144, %p130;
	setp.eq.f32 	%p146, %f181, 0f00000000;
	@%p146 bra 	$L__BB0_87;
	bra.uni 	$L__BB0_84;

$L__BB0_87:
	add.f32 	%f1308, %f181, %f181;
	selp.f32 	%f1844, %f1308, 0f00000000, %p130;
	bra.uni 	$L__BB0_88;

$L__BB0_84:
	mov.b32 	%r1430, %f1842;
	xor.b32  	%r1431, %r1430, -2147483648;
	mov.b32 	%f1304, %r1431;
	selp.f32 	%f1844, %f1304, %f1842, %p3;
	setp.geu.f32 	%p147, %f181, 0f00000000;
	@%p147 bra 	$L__BB0_88;

	mov.f32 	%f1305, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1306, %f1305;
	setp.eq.f32 	%p148, %f1306, 0f3EE66666;
	@%p148 bra 	$L__BB0_88;

	mov.f32 	%f1844, 0f7FFFFFFF;

$L__BB0_88:
	add.f32 	%f1309, %f211, 0f3EE66666;
	mov.b32 	%r1432, %f1309;
	setp.lt.s32 	%p150, %r1432, 2139095040;
	@%p150 bra 	$L__BB0_93;

	setp.gtu.f32 	%p151, %f211, 0f7F800000;
	@%p151 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_90;

$L__BB0_92:
	add.f32 	%f1844, %f181, 0f3EE66666;
	bra.uni 	$L__BB0_93;

$L__BB0_90:
	setp.neu.f32 	%p152, %f211, 0f7F800000;
	@%p152 bra 	$L__BB0_93;

	selp.f32 	%f1844, 0fFF800000, 0f7F800000, %p3;

$L__BB0_93:
	setp.eq.f32 	%p153, %f181, 0f3F800000;
	selp.f32 	%f222, 0f3F800000, %f1844, %p153;
	abs.f32 	%f223, %f182;
	setp.lt.f32 	%p154, %f223, 0f00800000;
	mul.f32 	%f1311, %f223, 0f4B800000;
	selp.f32 	%f1312, %f1311, %f223, %p154;
	selp.f32 	%f1313, 0fC3170000, 0fC2FE0000, %p154;
	mov.b32 	%r1433, %f1312;
	and.b32  	%r1434, %r1433, 8388607;
	or.b32  	%r1435, %r1434, 1065353216;
	mov.b32 	%f1314, %r1435;
	shr.u32 	%r1436, %r1433, 23;
	cvt.rn.f32.u32 	%f1315, %r1436;
	add.f32 	%f1316, %f1313, %f1315;
	setp.gt.f32 	%p155, %f1314, 0f3FB504F3;
	mul.f32 	%f1317, %f1314, 0f3F000000;
	add.f32 	%f1318, %f1316, 0f3F800000;
	selp.f32 	%f1319, %f1318, %f1316, %p155;
	selp.f32 	%f1320, %f1317, %f1314, %p155;
	add.f32 	%f1321, %f1320, 0fBF800000;
	add.f32 	%f1322, %f1320, 0f3F800000;
	rcp.approx.ftz.f32 	%f1323, %f1322;
	add.f32 	%f1324, %f1321, %f1321;
	mul.f32 	%f1325, %f1324, %f1323;
	mul.f32 	%f1326, %f1325, %f1325;
	mov.f32 	%f1327, 0f3C4CAF63;
	mov.f32 	%f1328, 0f3B18F0FE;
	fma.rn.f32 	%f1329, %f1328, %f1326, %f1327;
	mov.f32 	%f1330, 0f3DAAAABD;
	fma.rn.f32 	%f1331, %f1329, %f1326, %f1330;
	mul.rn.f32 	%f1332, %f1331, %f1326;
	mul.rn.f32 	%f1333, %f1332, %f1325;
	sub.f32 	%f1334, %f1321, %f1325;
	add.f32 	%f1335, %f1334, %f1334;
	neg.f32 	%f1336, %f1325;
	fma.rn.f32 	%f1337, %f1336, %f1321, %f1335;
	mul.rn.f32 	%f1338, %f1323, %f1337;
	add.f32 	%f1339, %f1333, %f1325;
	sub.f32 	%f1340, %f1325, %f1339;
	add.f32 	%f1341, %f1333, %f1340;
	add.f32 	%f1342, %f1338, %f1341;
	add.f32 	%f1343, %f1339, %f1342;
	sub.f32 	%f1344, %f1339, %f1343;
	add.f32 	%f1345, %f1342, %f1344;
	mov.f32 	%f1346, 0f3F317200;
	mul.rn.f32 	%f1347, %f1319, %f1346;
	mov.f32 	%f1348, 0f35BFBE8E;
	mul.rn.f32 	%f1349, %f1319, %f1348;
	add.f32 	%f1350, %f1347, %f1343;
	sub.f32 	%f1351, %f1347, %f1350;
	add.f32 	%f1352, %f1343, %f1351;
	add.f32 	%f1353, %f1345, %f1352;
	add.f32 	%f1354, %f1349, %f1353;
	add.f32 	%f1355, %f1350, %f1354;
	sub.f32 	%f1356, %f1350, %f1355;
	add.f32 	%f1357, %f1354, %f1356;
	mov.f32 	%f1358, 0f3EE66666;
	mul.rn.f32 	%f1359, %f1358, %f1355;
	neg.f32 	%f1360, %f1359;
	fma.rn.f32 	%f1361, %f1358, %f1355, %f1360;
	fma.rn.f32 	%f1362, %f1358, %f1357, %f1361;
	mov.f32 	%f1363, 0f00000000;
	fma.rn.f32 	%f1364, %f1363, %f1355, %f1362;
	add.rn.f32 	%f1365, %f1359, %f1364;
	neg.f32 	%f1366, %f1365;
	add.rn.f32 	%f1367, %f1359, %f1366;
	add.rn.f32 	%f1368, %f1367, %f1364;
	mov.b32 	%r1437, %f1365;
	setp.eq.s32 	%p156, %r1437, 1118925336;
	add.s32 	%r1438, %r1437, -1;
	mov.b32 	%f1369, %r1438;
	add.f32 	%f1370, %f1368, 0f37000000;
	selp.f32 	%f224, %f1370, %f1368, %p156;
	selp.f32 	%f1371, %f1369, %f1365, %p156;
	mov.f32 	%f1372, 0f3FB8AA3B;
	mul.rn.f32 	%f1373, %f1371, %f1372;
	cvt.rzi.f32.f32 	%f1374, %f1373;
	abs.f32 	%f1375, %f1374;
	setp.gt.f32 	%p157, %f1375, 0f42FC0000;
	mov.b32 	%r1439, %f1374;
	and.b32  	%r1440, %r1439, -2147483648;
	or.b32  	%r1441, %r1440, 1123811328;
	mov.b32 	%f1376, %r1441;
	selp.f32 	%f1377, %f1376, %f1374, %p157;
	mov.f32 	%f1378, 0fBF317218;
	fma.rn.f32 	%f1379, %f1377, %f1378, %f1371;
	mov.f32 	%f1380, 0f3102E308;
	fma.rn.f32 	%f1381, %f1377, %f1380, %f1379;
	mul.f32 	%f1382, %f1381, 0f3FB8AA3B;
	add.f32 	%f1383, %f1377, 0f4B40007F;
	mov.b32 	%r1442, %f1383;
	shl.b32 	%r1443, %r1442, 23;
	mov.b32 	%f1384, %r1443;
	ex2.approx.ftz.f32 	%f1385, %f1382;
	mul.f32 	%f225, %f1385, %f1384;
	setp.eq.f32 	%p158, %f225, 0f7F800000;
	mov.f32 	%f1845, 0f7F800000;
	@%p158 bra 	$L__BB0_95;

	fma.rn.f32 	%f1845, %f225, %f224, %f225;

$L__BB0_95:
	setp.lt.f32 	%p159, %f182, 0f00000000;
	and.pred  	%p4, %p159, %p130;
	setp.eq.f32 	%p161, %f182, 0f00000000;
	@%p161 bra 	$L__BB0_99;
	bra.uni 	$L__BB0_96;

$L__BB0_99:
	add.f32 	%f1390, %f182, %f182;
	selp.f32 	%f1847, %f1390, 0f00000000, %p130;
	bra.uni 	$L__BB0_100;

$L__BB0_96:
	mov.b32 	%r1444, %f1845;
	xor.b32  	%r1445, %r1444, -2147483648;
	mov.b32 	%f1386, %r1445;
	selp.f32 	%f1847, %f1386, %f1845, %p4;
	setp.geu.f32 	%p162, %f182, 0f00000000;
	@%p162 bra 	$L__BB0_100;

	mov.f32 	%f1387, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1388, %f1387;
	setp.eq.f32 	%p163, %f1388, 0f3EE66666;
	@%p163 bra 	$L__BB0_100;

	mov.f32 	%f1847, 0f7FFFFFFF;

$L__BB0_100:
	add.f32 	%f1391, %f223, 0f3EE66666;
	mov.b32 	%r1446, %f1391;
	setp.lt.s32 	%p165, %r1446, 2139095040;
	@%p165 bra 	$L__BB0_105;

	setp.gtu.f32 	%p166, %f223, 0f7F800000;
	@%p166 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_102;

$L__BB0_104:
	add.f32 	%f1847, %f182, 0f3EE66666;
	bra.uni 	$L__BB0_105;

$L__BB0_102:
	setp.neu.f32 	%p167, %f223, 0f7F800000;
	@%p167 bra 	$L__BB0_105;

	selp.f32 	%f1847, 0fFF800000, 0f7F800000, %p4;

$L__BB0_105:
	setp.eq.f32 	%p168, %f182, 0f3F800000;
	mov.f32 	%f1393, 0f3F800000;
	selp.f32 	%f1394, 0f3F800000, %f1847, %p168;
	ld.const.u64 	%rd89, [params+144];
	cvta.to.global.u64 	%rd18, %rd89;
	ld.const.u32 	%r1447, [params+136];
	mad.lo.s32 	%r1448, %r1447, %r6, %r5;
	cvt.u64.u32 	%rd19, %r1448;
	min.f32 	%f1395, %f210, %f1393;
	mov.f32 	%f1396, 0f00000000;
	max.f32 	%f234, %f1396, %f1395;
	min.f32 	%f1397, %f222, %f1393;
	max.f32 	%f235, %f1396, %f1397;
	min.f32 	%f1398, %f1394, %f1393;
	max.f32 	%f236, %f1396, %f1398;
	mov.f32 	%f1399, 0f3E555555;
	cvt.rzi.f32.f32 	%f1400, %f1399;
	add.f32 	%f1401, %f1400, %f1400;
	mov.f32 	%f1402, 0f3ED55555;
	sub.f32 	%f1403, %f1402, %f1401;
	abs.f32 	%f237, %f1403;
	abs.f32 	%f238, %f234;
	setp.lt.f32 	%p169, %f238, 0f00800000;
	mul.f32 	%f1404, %f238, 0f4B800000;
	selp.f32 	%f1405, %f1404, %f238, %p169;
	selp.f32 	%f1406, 0fC3170000, 0fC2FE0000, %p169;
	mov.b32 	%r1449, %f1405;
	and.b32  	%r1450, %r1449, 8388607;
	or.b32  	%r1451, %r1450, 1065353216;
	mov.b32 	%f1407, %r1451;
	shr.u32 	%r1452, %r1449, 23;
	cvt.rn.f32.u32 	%f1408, %r1452;
	add.f32 	%f1409, %f1406, %f1408;
	setp.gt.f32 	%p170, %f1407, 0f3FB504F3;
	mul.f32 	%f1410, %f1407, 0f3F000000;
	add.f32 	%f1411, %f1409, 0f3F800000;
	selp.f32 	%f1412, %f1411, %f1409, %p170;
	selp.f32 	%f1413, %f1410, %f1407, %p170;
	add.f32 	%f1414, %f1413, 0fBF800000;
	add.f32 	%f1415, %f1413, 0f3F800000;
	rcp.approx.ftz.f32 	%f1416, %f1415;
	add.f32 	%f1417, %f1414, %f1414;
	mul.f32 	%f1418, %f1417, %f1416;
	mul.f32 	%f1419, %f1418, %f1418;
	mov.f32 	%f1420, 0f3C4CAF63;
	mov.f32 	%f1421, 0f3B18F0FE;
	fma.rn.f32 	%f1422, %f1421, %f1419, %f1420;
	mov.f32 	%f1423, 0f3DAAAABD;
	fma.rn.f32 	%f1424, %f1422, %f1419, %f1423;
	mul.rn.f32 	%f1425, %f1424, %f1419;
	mul.rn.f32 	%f1426, %f1425, %f1418;
	sub.f32 	%f1427, %f1414, %f1418;
	add.f32 	%f1428, %f1427, %f1427;
	neg.f32 	%f1429, %f1418;
	fma.rn.f32 	%f1430, %f1429, %f1414, %f1428;
	mul.rn.f32 	%f1431, %f1416, %f1430;
	add.f32 	%f1432, %f1426, %f1418;
	sub.f32 	%f1433, %f1418, %f1432;
	add.f32 	%f1434, %f1426, %f1433;
	add.f32 	%f1435, %f1431, %f1434;
	add.f32 	%f1436, %f1432, %f1435;
	sub.f32 	%f1437, %f1432, %f1436;
	add.f32 	%f1438, %f1435, %f1437;
	mov.f32 	%f1439, 0f3F317200;
	mul.rn.f32 	%f1440, %f1412, %f1439;
	mov.f32 	%f1441, 0f35BFBE8E;
	mul.rn.f32 	%f1442, %f1412, %f1441;
	add.f32 	%f1443, %f1440, %f1436;
	sub.f32 	%f1444, %f1440, %f1443;
	add.f32 	%f1445, %f1436, %f1444;
	add.f32 	%f1446, %f1438, %f1445;
	add.f32 	%f1447, %f1442, %f1446;
	add.f32 	%f1448, %f1443, %f1447;
	sub.f32 	%f1449, %f1443, %f1448;
	add.f32 	%f1450, %f1447, %f1449;
	mul.rn.f32 	%f1451, %f1402, %f1448;
	neg.f32 	%f1452, %f1451;
	fma.rn.f32 	%f1453, %f1402, %f1448, %f1452;
	fma.rn.f32 	%f1454, %f1402, %f1450, %f1453;
	fma.rn.f32 	%f1455, %f1396, %f1448, %f1454;
	add.rn.f32 	%f1456, %f1451, %f1455;
	neg.f32 	%f1457, %f1456;
	add.rn.f32 	%f1458, %f1451, %f1457;
	add.rn.f32 	%f1459, %f1458, %f1455;
	mov.b32 	%r1453, %f1456;
	setp.eq.s32 	%p171, %r1453, 1118925336;
	add.s32 	%r1454, %r1453, -1;
	mov.b32 	%f1460, %r1454;
	add.f32 	%f1461, %f1459, 0f37000000;
	selp.f32 	%f239, %f1461, %f1459, %p171;
	selp.f32 	%f1462, %f1460, %f1456, %p171;
	mov.f32 	%f1463, 0f3FB8AA3B;
	mul.rn.f32 	%f1464, %f1462, %f1463;
	cvt.rzi.f32.f32 	%f1465, %f1464;
	abs.f32 	%f1466, %f1465;
	setp.gt.f32 	%p172, %f1466, 0f42FC0000;
	mov.b32 	%r1455, %f1465;
	and.b32  	%r1456, %r1455, -2147483648;
	or.b32  	%r1457, %r1456, 1123811328;
	mov.b32 	%f1467, %r1457;
	selp.f32 	%f1468, %f1467, %f1465, %p172;
	mov.f32 	%f1469, 0fBF317218;
	fma.rn.f32 	%f1470, %f1468, %f1469, %f1462;
	mov.f32 	%f1471, 0f3102E308;
	fma.rn.f32 	%f1472, %f1468, %f1471, %f1470;
	mul.f32 	%f1473, %f1472, 0f3FB8AA3B;
	add.f32 	%f1474, %f1468, 0f4B40007F;
	mov.b32 	%r1458, %f1474;
	shl.b32 	%r1459, %r1458, 23;
	mov.b32 	%f1475, %r1459;
	ex2.approx.ftz.f32 	%f1476, %f1473;
	mul.f32 	%f240, %f1476, %f1475;
	setp.eq.f32 	%p173, %f240, 0f7F800000;
	mov.f32 	%f1848, 0f7F800000;
	@%p173 bra 	$L__BB0_107;

	fma.rn.f32 	%f1848, %f240, %f239, %f240;

$L__BB0_107:
	setp.lt.f32 	%p174, %f234, 0f00000000;
	setp.eq.f32 	%p175, %f237, 0f3F800000;
	and.pred  	%p5, %p174, %p175;
	setp.eq.f32 	%p176, %f234, 0f00000000;
	@%p176 bra 	$L__BB0_111;
	bra.uni 	$L__BB0_108;

$L__BB0_111:
	add.f32 	%f1481, %f234, %f234;
	selp.f32 	%f1850, %f1481, 0f00000000, %p175;
	bra.uni 	$L__BB0_112;

$L__BB0_108:
	mov.b32 	%r1460, %f1848;
	xor.b32  	%r1461, %r1460, -2147483648;
	mov.b32 	%f1477, %r1461;
	selp.f32 	%f1850, %f1477, %f1848, %p5;
	setp.geu.f32 	%p177, %f234, 0f00000000;
	@%p177 bra 	$L__BB0_112;

	mov.f32 	%f1478, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1479, %f1478;
	setp.eq.f32 	%p178, %f1479, 0f3ED55555;
	@%p178 bra 	$L__BB0_112;

	mov.f32 	%f1850, 0f7FFFFFFF;

$L__BB0_112:
	add.f32 	%f1482, %f238, 0f3ED55555;
	mov.b32 	%r1462, %f1482;
	setp.lt.s32 	%p180, %r1462, 2139095040;
	@%p180 bra 	$L__BB0_117;

	setp.gtu.f32 	%p181, %f238, 0f7F800000;
	@%p181 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_114;

$L__BB0_116:
	add.f32 	%f1850, %f234, 0f3ED55555;
	bra.uni 	$L__BB0_117;

$L__BB0_114:
	setp.neu.f32 	%p182, %f238, 0f7F800000;
	@%p182 bra 	$L__BB0_117;

	selp.f32 	%f1850, 0fFF800000, 0f7F800000, %p5;

$L__BB0_117:
	abs.f32 	%f249, %f235;
	setp.lt.f32 	%p183, %f249, 0f00800000;
	mul.f32 	%f1484, %f249, 0f4B800000;
	selp.f32 	%f1485, %f1484, %f249, %p183;
	selp.f32 	%f1486, 0fC3170000, 0fC2FE0000, %p183;
	mov.b32 	%r1463, %f1485;
	and.b32  	%r1464, %r1463, 8388607;
	or.b32  	%r1465, %r1464, 1065353216;
	mov.b32 	%f1487, %r1465;
	shr.u32 	%r1466, %r1463, 23;
	cvt.rn.f32.u32 	%f1488, %r1466;
	add.f32 	%f1489, %f1486, %f1488;
	setp.gt.f32 	%p184, %f1487, 0f3FB504F3;
	mul.f32 	%f1490, %f1487, 0f3F000000;
	add.f32 	%f1491, %f1489, 0f3F800000;
	selp.f32 	%f1492, %f1491, %f1489, %p184;
	selp.f32 	%f1493, %f1490, %f1487, %p184;
	add.f32 	%f1494, %f1493, 0fBF800000;
	add.f32 	%f1495, %f1493, 0f3F800000;
	rcp.approx.ftz.f32 	%f1496, %f1495;
	add.f32 	%f1497, %f1494, %f1494;
	mul.f32 	%f1498, %f1497, %f1496;
	mul.f32 	%f1499, %f1498, %f1498;
	mov.f32 	%f1500, 0f3C4CAF63;
	mov.f32 	%f1501, 0f3B18F0FE;
	fma.rn.f32 	%f1502, %f1501, %f1499, %f1500;
	mov.f32 	%f1503, 0f3DAAAABD;
	fma.rn.f32 	%f1504, %f1502, %f1499, %f1503;
	mul.rn.f32 	%f1505, %f1504, %f1499;
	mul.rn.f32 	%f1506, %f1505, %f1498;
	sub.f32 	%f1507, %f1494, %f1498;
	add.f32 	%f1508, %f1507, %f1507;
	neg.f32 	%f1509, %f1498;
	fma.rn.f32 	%f1510, %f1509, %f1494, %f1508;
	mul.rn.f32 	%f1511, %f1496, %f1510;
	add.f32 	%f1512, %f1506, %f1498;
	sub.f32 	%f1513, %f1498, %f1512;
	add.f32 	%f1514, %f1506, %f1513;
	add.f32 	%f1515, %f1511, %f1514;
	add.f32 	%f1516, %f1512, %f1515;
	sub.f32 	%f1517, %f1512, %f1516;
	add.f32 	%f1518, %f1515, %f1517;
	mov.f32 	%f1519, 0f3F317200;
	mul.rn.f32 	%f1520, %f1492, %f1519;
	mov.f32 	%f1521, 0f35BFBE8E;
	mul.rn.f32 	%f1522, %f1492, %f1521;
	add.f32 	%f1523, %f1520, %f1516;
	sub.f32 	%f1524, %f1520, %f1523;
	add.f32 	%f1525, %f1516, %f1524;
	add.f32 	%f1526, %f1518, %f1525;
	add.f32 	%f1527, %f1522, %f1526;
	add.f32 	%f1528, %f1523, %f1527;
	sub.f32 	%f1529, %f1523, %f1528;
	add.f32 	%f1530, %f1527, %f1529;
	mov.f32 	%f1531, 0f3ED55555;
	mul.rn.f32 	%f1532, %f1531, %f1528;
	neg.f32 	%f1533, %f1532;
	fma.rn.f32 	%f1534, %f1531, %f1528, %f1533;
	fma.rn.f32 	%f1535, %f1531, %f1530, %f1534;
	mov.f32 	%f1536, 0f00000000;
	fma.rn.f32 	%f1537, %f1536, %f1528, %f1535;
	add.rn.f32 	%f1538, %f1532, %f1537;
	neg.f32 	%f1539, %f1538;
	add.rn.f32 	%f1540, %f1532, %f1539;
	add.rn.f32 	%f1541, %f1540, %f1537;
	mov.b32 	%r1467, %f1538;
	setp.eq.s32 	%p185, %r1467, 1118925336;
	add.s32 	%r1468, %r1467, -1;
	mov.b32 	%f1542, %r1468;
	add.f32 	%f1543, %f1541, 0f37000000;
	selp.f32 	%f250, %f1543, %f1541, %p185;
	selp.f32 	%f1544, %f1542, %f1538, %p185;
	mov.f32 	%f1545, 0f3FB8AA3B;
	mul.rn.f32 	%f1546, %f1544, %f1545;
	cvt.rzi.f32.f32 	%f1547, %f1546;
	abs.f32 	%f1548, %f1547;
	setp.gt.f32 	%p186, %f1548, 0f42FC0000;
	mov.b32 	%r1469, %f1547;
	and.b32  	%r1470, %r1469, -2147483648;
	or.b32  	%r1471, %r1470, 1123811328;
	mov.b32 	%f1549, %r1471;
	selp.f32 	%f1550, %f1549, %f1547, %p186;
	mov.f32 	%f1551, 0fBF317218;
	fma.rn.f32 	%f1552, %f1550, %f1551, %f1544;
	mov.f32 	%f1553, 0f3102E308;
	fma.rn.f32 	%f1554, %f1550, %f1553, %f1552;
	mul.f32 	%f1555, %f1554, 0f3FB8AA3B;
	add.f32 	%f1556, %f1550, 0f4B40007F;
	mov.b32 	%r1472, %f1556;
	shl.b32 	%r1473, %r1472, 23;
	mov.b32 	%f1557, %r1473;
	ex2.approx.ftz.f32 	%f1558, %f1555;
	mul.f32 	%f251, %f1558, %f1557;
	setp.eq.f32 	%p187, %f251, 0f7F800000;
	mov.f32 	%f1851, 0f7F800000;
	@%p187 bra 	$L__BB0_119;

	fma.rn.f32 	%f1851, %f251, %f250, %f251;

$L__BB0_119:
	setp.lt.f32 	%p188, %f235, 0f00000000;
	and.pred  	%p6, %p188, %p175;
	setp.eq.f32 	%p190, %f235, 0f00000000;
	@%p190 bra 	$L__BB0_123;
	bra.uni 	$L__BB0_120;

$L__BB0_123:
	add.f32 	%f1563, %f235, %f235;
	selp.f32 	%f1853, %f1563, 0f00000000, %p175;
	bra.uni 	$L__BB0_124;

$L__BB0_120:
	mov.b32 	%r1474, %f1851;
	xor.b32  	%r1475, %r1474, -2147483648;
	mov.b32 	%f1559, %r1475;
	selp.f32 	%f1853, %f1559, %f1851, %p6;
	setp.geu.f32 	%p191, %f235, 0f00000000;
	@%p191 bra 	$L__BB0_124;

	mov.f32 	%f1560, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1561, %f1560;
	setp.eq.f32 	%p192, %f1561, 0f3ED55555;
	@%p192 bra 	$L__BB0_124;

	mov.f32 	%f1853, 0f7FFFFFFF;

$L__BB0_124:
	add.f32 	%f1564, %f249, 0f3ED55555;
	mov.b32 	%r1476, %f1564;
	setp.lt.s32 	%p194, %r1476, 2139095040;
	@%p194 bra 	$L__BB0_129;

	setp.gtu.f32 	%p195, %f249, 0f7F800000;
	@%p195 bra 	$L__BB0_128;
	bra.uni 	$L__BB0_126;

$L__BB0_128:
	add.f32 	%f1853, %f235, 0f3ED55555;
	bra.uni 	$L__BB0_129;

$L__BB0_126:
	setp.neu.f32 	%p196, %f249, 0f7F800000;
	@%p196 bra 	$L__BB0_129;

	selp.f32 	%f1853, 0fFF800000, 0f7F800000, %p6;

$L__BB0_129:
	abs.f32 	%f260, %f236;
	setp.lt.f32 	%p197, %f260, 0f00800000;
	mul.f32 	%f1566, %f260, 0f4B800000;
	selp.f32 	%f1567, %f1566, %f260, %p197;
	selp.f32 	%f1568, 0fC3170000, 0fC2FE0000, %p197;
	mov.b32 	%r1477, %f1567;
	and.b32  	%r1478, %r1477, 8388607;
	or.b32  	%r1479, %r1478, 1065353216;
	mov.b32 	%f1569, %r1479;
	shr.u32 	%r1480, %r1477, 23;
	cvt.rn.f32.u32 	%f1570, %r1480;
	add.f32 	%f1571, %f1568, %f1570;
	setp.gt.f32 	%p198, %f1569, 0f3FB504F3;
	mul.f32 	%f1572, %f1569, 0f3F000000;
	add.f32 	%f1573, %f1571, 0f3F800000;
	selp.f32 	%f1574, %f1573, %f1571, %p198;
	selp.f32 	%f1575, %f1572, %f1569, %p198;
	add.f32 	%f1576, %f1575, 0fBF800000;
	add.f32 	%f1577, %f1575, 0f3F800000;
	rcp.approx.ftz.f32 	%f1578, %f1577;
	add.f32 	%f1579, %f1576, %f1576;
	mul.f32 	%f1580, %f1579, %f1578;
	mul.f32 	%f1581, %f1580, %f1580;
	mov.f32 	%f1582, 0f3C4CAF63;
	mov.f32 	%f1583, 0f3B18F0FE;
	fma.rn.f32 	%f1584, %f1583, %f1581, %f1582;
	mov.f32 	%f1585, 0f3DAAAABD;
	fma.rn.f32 	%f1586, %f1584, %f1581, %f1585;
	mul.rn.f32 	%f1587, %f1586, %f1581;
	mul.rn.f32 	%f1588, %f1587, %f1580;
	sub.f32 	%f1589, %f1576, %f1580;
	add.f32 	%f1590, %f1589, %f1589;
	neg.f32 	%f1591, %f1580;
	fma.rn.f32 	%f1592, %f1591, %f1576, %f1590;
	mul.rn.f32 	%f1593, %f1578, %f1592;
	add.f32 	%f1594, %f1588, %f1580;
	sub.f32 	%f1595, %f1580, %f1594;
	add.f32 	%f1596, %f1588, %f1595;
	add.f32 	%f1597, %f1593, %f1596;
	add.f32 	%f1598, %f1594, %f1597;
	sub.f32 	%f1599, %f1594, %f1598;
	add.f32 	%f1600, %f1597, %f1599;
	mov.f32 	%f1601, 0f3F317200;
	mul.rn.f32 	%f1602, %f1574, %f1601;
	mov.f32 	%f1603, 0f35BFBE8E;
	mul.rn.f32 	%f1604, %f1574, %f1603;
	add.f32 	%f1605, %f1602, %f1598;
	sub.f32 	%f1606, %f1602, %f1605;
	add.f32 	%f1607, %f1598, %f1606;
	add.f32 	%f1608, %f1600, %f1607;
	add.f32 	%f1609, %f1604, %f1608;
	add.f32 	%f1610, %f1605, %f1609;
	sub.f32 	%f1611, %f1605, %f1610;
	add.f32 	%f1612, %f1609, %f1611;
	mov.f32 	%f1613, 0f3ED55555;
	mul.rn.f32 	%f1614, %f1613, %f1610;
	neg.f32 	%f1615, %f1614;
	fma.rn.f32 	%f1616, %f1613, %f1610, %f1615;
	fma.rn.f32 	%f1617, %f1613, %f1612, %f1616;
	mov.f32 	%f1618, 0f00000000;
	fma.rn.f32 	%f1619, %f1618, %f1610, %f1617;
	add.rn.f32 	%f1620, %f1614, %f1619;
	neg.f32 	%f1621, %f1620;
	add.rn.f32 	%f1622, %f1614, %f1621;
	add.rn.f32 	%f1623, %f1622, %f1619;
	mov.b32 	%r1481, %f1620;
	setp.eq.s32 	%p199, %r1481, 1118925336;
	add.s32 	%r1482, %r1481, -1;
	mov.b32 	%f1624, %r1482;
	add.f32 	%f1625, %f1623, 0f37000000;
	selp.f32 	%f261, %f1625, %f1623, %p199;
	selp.f32 	%f1626, %f1624, %f1620, %p199;
	mov.f32 	%f1627, 0f3FB8AA3B;
	mul.rn.f32 	%f1628, %f1626, %f1627;
	cvt.rzi.f32.f32 	%f1629, %f1628;
	abs.f32 	%f1630, %f1629;
	setp.gt.f32 	%p200, %f1630, 0f42FC0000;
	mov.b32 	%r1483, %f1629;
	and.b32  	%r1484, %r1483, -2147483648;
	or.b32  	%r1485, %r1484, 1123811328;
	mov.b32 	%f1631, %r1485;
	selp.f32 	%f1632, %f1631, %f1629, %p200;
	mov.f32 	%f1633, 0fBF317218;
	fma.rn.f32 	%f1634, %f1632, %f1633, %f1626;
	mov.f32 	%f1635, 0f3102E308;
	fma.rn.f32 	%f1636, %f1632, %f1635, %f1634;
	mul.f32 	%f1637, %f1636, 0f3FB8AA3B;
	add.f32 	%f1638, %f1632, 0f4B40007F;
	mov.b32 	%r1486, %f1638;
	shl.b32 	%r1487, %r1486, 23;
	mov.b32 	%f1639, %r1487;
	ex2.approx.ftz.f32 	%f1640, %f1637;
	mul.f32 	%f262, %f1640, %f1639;
	setp.eq.f32 	%p201, %f262, 0f7F800000;
	mov.f32 	%f1854, 0f7F800000;
	@%p201 bra 	$L__BB0_131;

	fma.rn.f32 	%f1854, %f262, %f261, %f262;

$L__BB0_131:
	setp.lt.f32 	%p202, %f236, 0f00000000;
	and.pred  	%p7, %p202, %p175;
	setp.eq.f32 	%p204, %f236, 0f00000000;
	@%p204 bra 	$L__BB0_135;
	bra.uni 	$L__BB0_132;

$L__BB0_135:
	add.f32 	%f1645, %f236, %f236;
	selp.f32 	%f1856, %f1645, 0f00000000, %p175;
	bra.uni 	$L__BB0_136;

$L__BB0_132:
	mov.b32 	%r1488, %f1854;
	xor.b32  	%r1489, %r1488, -2147483648;
	mov.b32 	%f1641, %r1489;
	selp.f32 	%f1856, %f1641, %f1854, %p7;
	setp.geu.f32 	%p205, %f236, 0f00000000;
	@%p205 bra 	$L__BB0_136;

	mov.f32 	%f1642, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1643, %f1642;
	setp.eq.f32 	%p206, %f1643, 0f3ED55555;
	@%p206 bra 	$L__BB0_136;

	mov.f32 	%f1856, 0f7FFFFFFF;

$L__BB0_136:
	add.f32 	%f1646, %f260, 0f3ED55555;
	mov.b32 	%r1490, %f1646;
	setp.lt.s32 	%p208, %r1490, 2139095040;
	@%p208 bra 	$L__BB0_141;

	setp.gtu.f32 	%p209, %f260, 0f7F800000;
	@%p209 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_138;

$L__BB0_140:
	add.f32 	%f1856, %f236, 0f3ED55555;
	bra.uni 	$L__BB0_141;

$L__BB0_138:
	setp.neu.f32 	%p210, %f260, 0f7F800000;
	@%p210 bra 	$L__BB0_141;

	selp.f32 	%f1856, 0fFF800000, 0f7F800000, %p7;

$L__BB0_141:
	fma.rn.f32 	%f1647, %f1850, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p211, %f234, 0f3F800000;
	mov.f32 	%f1648, 0f3F800000;
	selp.f32 	%f1649, 0f3F7FFFFF, %f1647, %p211;
	mul.f32 	%f1650, %f234, 0f414EB852;
	setp.lt.f32 	%p212, %f234, 0f3B4D2E1C;
	selp.f32 	%f1651, %f1650, %f1649, %p212;
	fma.rn.f32 	%f1652, %f1853, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p213, %f235, 0f3F800000;
	selp.f32 	%f1653, 0f3F7FFFFF, %f1652, %p213;
	mul.f32 	%f1654, %f235, 0f414EB852;
	setp.lt.f32 	%p214, %f235, 0f3B4D2E1C;
	selp.f32 	%f1655, %f1654, %f1653, %p214;
	fma.rn.f32 	%f1656, %f1856, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p215, %f236, 0f3F800000;
	selp.f32 	%f1657, 0f3F7FFFFF, %f1656, %p215;
	mul.f32 	%f1658, %f236, 0f414EB852;
	setp.lt.f32 	%p216, %f236, 0f3B4D2E1C;
	selp.f32 	%f1659, %f1658, %f1657, %p216;
	min.f32 	%f1660, %f1651, %f1648;
	mov.f32 	%f1661, 0f00000000;
	max.f32 	%f1662, %f1661, %f1660;
	mul.f32 	%f1663, %f1662, 0f43800000;
	cvt.rzi.u32.f32 	%r1491, %f1663;
	min.u32 	%r1492, %r1491, 255;
	min.f32 	%f1664, %f1655, %f1648;
	max.f32 	%f1665, %f1661, %f1664;
	mul.f32 	%f1666, %f1665, 0f43800000;
	cvt.rzi.u32.f32 	%r1493, %f1666;
	min.u32 	%r1494, %r1493, 255;
	min.f32 	%f1667, %f1659, %f1648;
	max.f32 	%f1668, %f1661, %f1667;
	mul.f32 	%f1669, %f1668, 0f43800000;
	cvt.rzi.u32.f32 	%r1495, %f1669;
	min.u32 	%r1496, %r1495, 255;
	shl.b64 	%rd90, %rd19, 2;
	add.s64 	%rd91, %rd18, %rd90;
	cvt.u16.u32 	%rs36, %r1496;
	cvt.u16.u32 	%rs37, %r1494;
	cvt.u16.u32 	%rs38, %r1492;
	mov.u16 	%rs39, 255;
	st.global.v4.u8 	[%rd91], {%rs38, %rs37, %rs36, %rs39};

$L__BB0_142:
	and.b32  	%r1497, %r58, 4;
	setp.eq.s32 	%p217, %r1497, 0;
	ld.const.u32 	%r1539, [params+108];
	@%p217 bra 	$L__BB0_146;

	setp.eq.s32 	%p218, %r1539, 0;
	ld.const.u64 	%rd92, [params+224];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r1498, [params+216];
	mad.lo.s32 	%r1499, %r1498, %r6, %r5;
	mul.wide.u32 	%rd94, %r1499, 8;
	add.s64 	%rd20, %rd93, %rd94;
	@%p218 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs47, %rs48, %rs49, %rs50}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1670, %rs47;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1671, %rs48;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1672, %rs49;}

	// end inline asm
	add.f32 	%f1673, %f180, %f1670;
	add.f32 	%f1674, %f181, %f1671;
	add.f32 	%f1675, %f182, %f1672;
	mov.f32 	%f1676, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f1675;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1674;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1673;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f1676;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs43, %rs44, %rs45, %rs46};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1680, 0f3F800000;
	mov.u32 	%r1539, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f1680;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f182;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f181;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f180;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs51, %rs52, %rs53, %rs54};

$L__BB0_146:
	ld.const.u64 	%rd95, [params+256];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r1501, [params+248];
	mad.lo.s32 	%r1502, %r1501, %r6, %r5;
	mul.wide.u32 	%rd97, %r1502, 8;
	add.s64 	%rd21, %rd96, %rd97;
	setp.eq.s32 	%p219, %r1539, 0;
	@%p219 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs62, %rs63, %rs64, %rs65}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1681, %rs62;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1682, %rs63;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1683, %rs64;}

	// end inline asm
	add.f32 	%f1684, %f183, %f1681;
	add.f32 	%f1685, %f184, %f1682;
	add.f32 	%f1686, %f185, %f1683;
	mov.f32 	%f1687, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1686;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1685;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1684;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f1687;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs58, %rs59, %rs60, %rs61};
	bra.uni 	$L__BB0_149;

$L__BB0_148:
	mov.f32 	%f1691, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1691;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f185;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f184;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f183;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs66, %rs67, %rs68, %rs69};

$L__BB0_149:
	mul.f32 	%f1692, %f295, 0f3F000000;
	mov.f32 	%f1693, 0f3F000000;
	sub.f32 	%f271, %f1693, %f1692;
	mul.f32 	%f1694, %f296, 0f3F000000;
	sub.f32 	%f272, %f1693, %f1694;
	mul.f32 	%f1695, %f297, 0f3F000000;
	sub.f32 	%f273, %f1693, %f1695;
	ld.const.u64 	%rd98, [params+272];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r1503, [params+264];
	mad.lo.s32 	%r1504, %r1503, %r6, %r5;
	mul.wide.u32 	%rd100, %r1504, 8;
	add.s64 	%rd22, %rd99, %rd100;
	@%p219 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs77, %rs78, %rs79, %rs80}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1696, %rs77;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1697, %rs78;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1698, %rs79;}

	// end inline asm
	add.f32 	%f1699, %f271, %f1696;
	add.f32 	%f1700, %f271, %f1697;
	add.f32 	%f1701, %f271, %f1698;
	mov.f32 	%f1702, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f1701;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1700;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1699;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f1702;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs73, %rs74, %rs75, %rs76};
	bra.uni 	$L__BB0_152;

$L__BB0_151:
	mov.f32 	%f1706, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1706;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f271;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f271;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f271;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs81, %rs82, %rs83, %rs84};

$L__BB0_152:
	ld.const.u64 	%rd101, [params+288];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r1505, [params+280];
	mad.lo.s32 	%r1506, %r1505, %r6, %r5;
	mul.wide.u32 	%rd103, %r1506, 8;
	add.s64 	%rd23, %rd102, %rd103;
	@%p219 bra 	$L__BB0_154;

	ld.global.v4.u16 	{%rs92, %rs93, %rs94, %rs95}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1707, %rs92;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1708, %rs93;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1709, %rs94;}

	// end inline asm
	add.f32 	%f1710, %f272, %f1707;
	add.f32 	%f1711, %f272, %f1708;
	add.f32 	%f1712, %f272, %f1709;
	mov.f32 	%f1713, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f1712;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1711;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1710;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f1713;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs88, %rs89, %rs90, %rs91};
	bra.uni 	$L__BB0_155;

$L__BB0_154:
	mov.f32 	%f1717, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1717;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f272;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f272;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f272;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs96, %rs97, %rs98, %rs99};

$L__BB0_155:
	ld.const.u64 	%rd104, [params+304];
	cvta.to.global.u64 	%rd105, %rd104;
	ld.const.u32 	%r1507, [params+296];
	mad.lo.s32 	%r1508, %r1507, %r6, %r5;
	mul.wide.u32 	%rd106, %r1508, 8;
	add.s64 	%rd24, %rd105, %rd106;
	@%p219 bra 	$L__BB0_157;

	ld.global.v4.u16 	{%rs107, %rs108, %rs109, %rs110}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1718, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1719, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1720, %rs109;}

	// end inline asm
	add.f32 	%f1721, %f273, %f1718;
	add.f32 	%f1722, %f273, %f1719;
	add.f32 	%f1723, %f273, %f1720;
	mov.f32 	%f1724, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1723;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1722;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1721;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1724;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs103, %rs104, %rs105, %rs106};
	bra.uni 	$L__BB0_178;

$L__BB0_157:
	mov.f32 	%f1728, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1728;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f273;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f273;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f273;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs111, %rs112, %rs113, %rs114};

$L__BB0_178:
	ret;

}