//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[1184];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<4>;
	.reg .b16 	%rs<41>;
	.reg .f32 	%f<106>;
	.reg .b32 	%r<29>;
	.reg .b64 	%rd<41>;


	ld.param.u32 	%r3, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f24, [__direct_callable__oxMain_param_1+4];
	ld.param.f32 	%f23, [__direct_callable__oxMain_param_1];
	ld.const.u64 	%rd4, [params+24];
	cvta.to.global.u64 	%rd5, %rd4;
	mul.wide.u32 	%rd6, %r3, 12;
	add.s64 	%rd7, %rd5, %rd6;
	ld.global.s32 	%rd1, [%rd7];
	ld.global.s32 	%rd2, [%rd7+4];
	ld.global.s32 	%rd3, [%rd7+8];
	ld.const.u32 	%r1, [params+32];
	setp.gt.u32 	%p1, %r1, %r3;
	@%p1 bra 	$L__BB0_4;
	bra.uni 	$L__BB0_1;

$L__BB0_4:
	mov.f32 	%f105, 0f3F800000;
	bra.uni 	$L__BB0_5;

$L__BB0_1:
	sub.s32 	%r4, %r3, %r1;
	ld.const.u64 	%rd8, [params+48];
	cvta.to.global.u64 	%rd9, %rd8;
	mul.wide.u32 	%rd10, %r4, 4;
	add.s64 	%rd11, %rd9, %rd10;
	ld.const.u64 	%rd12, [params+40];
	cvta.to.global.u64 	%rd13, %rd12;
	shl.b64 	%rd14, %rd1, 3;
	add.s64 	%rd15, %rd13, %rd14;
	ld.global.v2.f32 	{%f25, %f26}, [%rd15];
	shl.b64 	%rd16, %rd2, 3;
	add.s64 	%rd17, %rd13, %rd16;
	ld.global.v2.f32 	{%f29, %f30}, [%rd17];
	shl.b64 	%rd18, %rd3, 3;
	add.s64 	%rd19, %rd13, %rd18;
	ld.global.v2.f32 	{%f33, %f34}, [%rd19];
	mov.f32 	%f37, 0f3F800000;
	sub.f32 	%f38, %f37, %f23;
	sub.f32 	%f39, %f38, %f24;
	mul.f32 	%f40, %f23, %f29;
	mul.f32 	%f41, %f23, %f30;
	fma.rn.f32 	%f42, %f39, %f25, %f40;
	fma.rn.f32 	%f43, %f39, %f26, %f41;
	fma.rn.f32 	%f1, %f24, %f33, %f42;
	fma.rn.f32 	%f2, %f24, %f34, %f43;
	ld.global.u32 	%r2, [%rd11];
	and.b32  	%r5, %r2, -16384;
	setp.eq.s32 	%p2, %r5, 16384;
	@%p2 bra 	$L__BB0_3;
	bra.uni 	$L__BB0_2;

$L__BB0_3:
	add.s32 	%r17, %r2, -16384;
	ld.const.u64 	%rd28, [params+64];
	cvta.to.global.u64 	%rd29, %rd28;
	mul.wide.u32 	%rd30, %r17, 8;
	add.s64 	%rd31, %rd29, %rd30;
	ld.global.u64 	%rd32, [%rd31];
	tex.2d.v4.f32.f32 	{%f54, %f55, %f56, %f57}, [%rd32, {%f1, %f2}];
	cvt.sat.f32.f32 	%f58, %f54;
	mul.f32 	%f59, %f58, 0f437F0000;
	cvt.rzi.s32.f32 	%r18, %f59;
	cvt.sat.f32.f32 	%f60, %f55;
	mul.f32 	%f61, %f60, 0f437F0000;
	cvt.rzi.s32.f32 	%r19, %f61;
	cvt.sat.f32.f32 	%f62, %f56;
	mul.f32 	%f63, %f62, 0f437F0000;
	cvt.rzi.s32.f32 	%r20, %f63;
	shl.b32 	%r21, %r19, 8;
	or.b32  	%r22, %r21, %r18;
	shl.b32 	%r23, %r20, 16;
	or.b32  	%r24, %r22, %r23;
	not.b32 	%r25, %r24;
	cvt.rn.f32.s32 	%f105, %r25;
	bra.uni 	$L__BB0_6;

$L__BB0_2:
	abs.f32 	%f44, %f1;
	cvt.rmi.f32.f32 	%f45, %f44;
	sub.f32 	%f46, %f44, %f45;
	abs.f32 	%f47, %f2;
	cvt.rmi.f32.f32 	%f48, %f47;
	sub.f32 	%f49, %f47, %f48;
	ld.const.u64 	%rd20, [params+56];
	cvta.to.global.u64 	%rd21, %rd20;
	shl.b32 	%r6, %r2, 4;
	cvt.u64.u32 	%rd22, %r6;
	and.b64  	%rd23, %rd22, 1048560;
	add.s64 	%rd24, %rd21, %rd23;
	ld.global.v2.u32 	{%r7, %r8}, [%rd24];
	cvt.rn.f32.u32 	%f50, %r7;
	mul.f32 	%f51, %f46, %f50;
	cvt.rzi.u32.f32 	%r11, %f51;
	cvt.rn.f32.u32 	%f52, %r8;
	mul.f32 	%f53, %f49, %f52;
	cvt.rzi.u32.f32 	%r12, %f53;
	mad.lo.s32 	%r13, %r7, %r12, %r11;
	cvt.u64.u32 	%rd25, %r13;
	ld.global.u64 	%rd26, [%rd24+8];
	add.s64 	%rd27, %rd26, %rd25;
	ld.u8 	%r14, [%rd27];
	shr.u32 	%r15, %r2, 16;
	and.b32  	%r16, %r15, %r14;
	setp.eq.s32 	%p3, %r16, 0;
	selp.f32 	%f105, 0f00000000, 0f3F800000, %p3;

$L__BB0_5:
	cvt.u32.u64 	%r26, %rd1;
	cvt.u32.u64 	%r27, %rd2;
	cvt.u32.u64 	%r28, %rd3;
	ld.const.u64 	%rd33, [params+16];
	cvta.to.global.u64 	%rd34, %rd33;
	mul.wide.s32 	%rd35, %r26, 24;
	add.s64 	%rd36, %rd34, %rd35;
	mul.wide.s32 	%rd37, %r27, 24;
	add.s64 	%rd38, %rd34, %rd37;
	mul.wide.s32 	%rd39, %r28, 24;
	add.s64 	%rd40, %rd34, %rd39;
	ld.global.f32 	%f70, [%rd38];
	ld.global.f32 	%f71, [%rd36];
	sub.f32 	%f72, %f71, %f70;
	ld.global.f32 	%f73, [%rd38+4];
	ld.global.f32 	%f74, [%rd36+4];
	sub.f32 	%f75, %f74, %f73;
	ld.global.f32 	%f76, [%rd38+8];
	ld.global.f32 	%f77, [%rd36+8];
	sub.f32 	%f78, %f77, %f76;
	ld.global.f32 	%f79, [%rd40];
	sub.f32 	%f80, %f70, %f79;
	ld.global.f32 	%f81, [%rd40+4];
	sub.f32 	%f82, %f73, %f81;
	ld.global.f32 	%f83, [%rd40+8];
	sub.f32 	%f84, %f76, %f83;
	mul.f32 	%f85, %f75, %f84;
	mul.f32 	%f86, %f78, %f82;
	sub.f32 	%f87, %f85, %f86;
	mul.f32 	%f88, %f78, %f80;
	mul.f32 	%f89, %f72, %f84;
	sub.f32 	%f90, %f88, %f89;
	mul.f32 	%f91, %f72, %f82;
	mul.f32 	%f92, %f75, %f80;
	sub.f32 	%f93, %f91, %f92;
	mul.f32 	%f94, %f90, %f90;
	fma.rn.f32 	%f95, %f87, %f87, %f94;
	fma.rn.f32 	%f96, %f93, %f93, %f95;
	sqrt.rn.f32 	%f97, %f96;
	rcp.rn.f32 	%f98, %f97;
	mul.f32 	%f104, %f93, %f98;
	mul.f32 	%f103, %f98, %f90;
	mul.f32 	%f102, %f98, %f87;

$L__BB0_6:
	st.param.f32 	[func_retval0+0], %f102;
	st.param.f32 	[func_retval0+4], %f103;
	st.param.f32 	[func_retval0+8], %f104;
	st.param.v4.b8 	[func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
	st.param.f32 	[func_retval0+16], %f20;
	st.param.f32 	[func_retval0+20], %f21;
	st.param.f32 	[func_retval0+24], %f105;
	st.param.v4.b8 	[func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}