//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//

.version 6.1
.target sm_30
.address_size 64

	// .globl	oxMain
.const .align 8 .b8 params[88];

.visible .entry oxMain(

)
{
	.reg .pred 	%p<5>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<14>;
	.reg .b32 	%r<23>;
	.reg .b64 	%rd<13>;


	mov.u32 	%r3, %ctaid.x;
	mov.u32 	%r4, %ntid.x;
	mov.u32 	%r5, %tid.x;
	mad.lo.s32 	%r1, %r4, %r3, %r5;
	mov.u32 	%r6, %ntid.y;
	mov.u32 	%r7, %ctaid.y;
	mov.u32 	%r8, %tid.y;
	mad.lo.s32 	%r2, %r6, %r7, %r8;
	mov.u32 	%r9, %nctaid.x;
	mul.lo.s32 	%r10, %r9, %r4;
	mov.u32 	%r11, %nctaid.y;
	mul.lo.s32 	%r12, %r11, %r6;
	setp.lt.u32	%p1, %r1, %r10;
	setp.lt.u32	%p2, %r2, %r12;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	ld.const.u64 	%rd1, [params+72];
	cvta.to.global.u64 	%rd2, %rd1;
	ld.const.u32 	%r13, [params+64];
	mad.lo.s32 	%r14, %r13, %r2, %r1;
	mul.wide.u32 	%rd3, %r14, 12;
	add.s64 	%rd4, %rd2, %rd3;
	ld.global.f32 	%f1, [%rd4];
	ld.global.f32 	%f2, [%rd4+4];
	ld.global.f32 	%f3, [%rd4+8];
	ld.const.u32 	%r15, [params+80];
	setp.gt.s32	%p4, %r15, 0;
	@%p4 bra 	BB0_3;
	bra.uni 	BB0_2;

BB0_3:
	ld.const.u64 	%rd9, [params+40];
	cvta.to.global.u64 	%rd10, %rd9;
	ld.const.u32 	%r18, [params+32];
	mad.lo.s32 	%r19, %r18, %r2, %r1;
	cvt.sat.f32.f32	%f8, %f1;
	mul.f32 	%f9, %f8, 0f437F0000;
	cvt.rzi.u32.f32	%r20, %f9;
	cvt.sat.f32.f32	%f10, %f2;
	mul.f32 	%f11, %f10, 0f437F0000;
	cvt.rzi.u32.f32	%r21, %f11;
	cvt.sat.f32.f32	%f12, %f3;
	mul.f32 	%f13, %f12, 0f437F0000;
	cvt.rzi.u32.f32	%r22, %f13;
	mul.wide.u32 	%rd11, %r19, 4;
	add.s64 	%rd12, %rd10, %rd11;
	cvt.u16.u32	%rs5, %r22;
	cvt.u16.u32	%rs6, %r21;
	cvt.u16.u32	%rs7, %r20;
	mov.u16 	%rs8, 255;
	st.global.v4.u8 	[%rd12], {%rs7, %rs6, %rs5, %rs8};
	bra.uni 	BB0_4;

BB0_2:
	ld.const.u64 	%rd5, [params+24];
	ld.const.u32 	%r16, [params+16];
	mad.lo.s32 	%r17, %r16, %r2, %r1;
	cvta.to.global.u64 	%rd6, %rd5;
	mul.wide.u32 	%rd7, %r17, 8;
	add.s64 	%rd8, %rd6, %rd7;
	mov.f32 	%f7, 0f3F800000;
	// inline asm
	{  cvt.rn.f16.f32 %rs4, %f7;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs3, %f3;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs2, %f2;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs1, %f1;}

	// inline asm
	st.global.v4.u16 	[%rd8], {%rs1, %rs2, %rs3, %rs4};

BB0_4:
	ret;
}