//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];

.visible .entry __raygen__oxMain()
{
	.reg .pred 	%p<210>;
	.reg .b16 	%rs<180>;
	.reg .f32 	%f<1721>;
	.reg .b32 	%r<454>;
	.reg .b64 	%rd<78>;


	// begin inline asm
	call (%r26), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r27), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd21, [params+400];
	cvta.to.global.u64 	%rd22, %rd21;
	ld.const.u32 	%r32, [params+392];
	mad.lo.s32 	%r33, %r32, %r27, %r26;
	mul.wide.u32 	%rd23, %r33, 4;
	add.s64 	%rd1, %rd22, %rd23;
	ld.global.v2.u8 	{%rs9, %rs178}, [%rd1];
	or.b16  	%rs11, %rs9, %rs178;
	and.b16  	%rs12, %rs11, 255;
	setp.eq.s16 	%p11, %rs12, 0;
	@%p11 bra 	$L__BB0_2;

	ld.global.u8 	%rs177, [%rd1+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs177, [%rd1+2];
	setp.eq.s16 	%p12, %rs177, 0;
	mov.f32 	%f1614, 0f00000000;
	mov.u16 	%rs178, 0;
	mov.f32 	%f1615, %f1614;
	mov.f32 	%f1616, %f1614;
	@%p12 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f313, %rs9;
	div.rn.f32 	%f314, %f313, 0f437F0000;
	fma.rn.f32 	%f315, %f314, 0f40000000, 0fBF800000;
	and.b16  	%rs15, %rs178, 255;
	cvt.rn.f32.u16 	%f316, %rs15;
	div.rn.f32 	%f317, %f316, 0f437F0000;
	fma.rn.f32 	%f318, %f317, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f319, %rs177;
	div.rn.f32 	%f320, %f319, 0f437F0000;
	fma.rn.f32 	%f321, %f320, 0f40000000, 0fBF800000;
	mul.f32 	%f322, %f318, %f318;
	fma.rn.f32 	%f323, %f315, %f315, %f322;
	fma.rn.f32 	%f324, %f321, %f321, %f323;
	sqrt.rn.f32 	%f325, %f324;
	rcp.rn.f32 	%f326, %f325;
	mul.f32 	%f1616, %f326, %f321;
	mul.f32 	%f1615, %f326, %f318;
	mul.f32 	%f1614, %f315, %f326;

$L__BB0_4:
	ld.const.v2.u32 	{%r34, %r35}, [params];
	add.s32 	%r3, %r34, %r26;
	add.s32 	%r4, %r35, %r27;
	setp.eq.f32 	%p13, %f1614, 0f00000000;
	setp.eq.f32 	%p14, %f1615, 0f00000000;
	and.pred  	%p15, %p13, %p14;
	setp.eq.f32 	%p16, %f1616, 0f00000000;
	and.pred  	%p17, %p16, %p15;
	@%p17 bra 	$L__BB0_163;
	bra.uni 	$L__BB0_5;

$L__BB0_163:
	ld.const.u32 	%r23, [params+104];
	and.b32  	%r428, %r23, 1;
	setp.eq.b32 	%p198, %r428, 1;
	mov.pred 	%p199, 0;
	xor.pred  	%p200, %p198, %p199;
	not.pred 	%p201, %p200;
	@%p201 bra 	$L__BB0_165;

	ld.const.u64 	%rd54, [params+144];
	cvta.to.global.u64 	%rd55, %rd54;
	ld.const.u32 	%r429, [params+136];
	mad.lo.s32 	%r430, %r429, %r4, %r3;
	mul.wide.u32 	%rd56, %r430, 4;
	add.s64 	%rd57, %rd55, %rd56;
	mov.u16 	%rs99, 0;
	st.global.v4.u8 	[%rd57], {%rs99, %rs99, %rs99, %rs99};

$L__BB0_165:
	and.b32  	%r431, %r23, 8;
	setp.eq.s32 	%p202, %r431, 0;
	@%p202 bra 	$L__BB0_167;

	ld.const.u64 	%rd58, [params+192];
	cvta.to.global.u64 	%rd59, %rd58;
	ld.const.u32 	%r432, [params+184];
	mad.lo.s32 	%r433, %r432, %r4, %r3;
	mov.f32 	%f1565, 0f00000000;
	cvt.rzi.u32.f32 	%r434, %f1565;
	mul.wide.u32 	%rd60, %r433, 2;
	add.s64 	%rd61, %rd59, %rd60;
	mov.u16 	%rs100, 0;
	cvt.u16.u32 	%rs101, %r434;
	st.global.v2.u8 	[%rd61], {%rs101, %rs100};

$L__BB0_167:
	and.b32  	%r435, %r23, 4;
	setp.eq.s32 	%p203, %r435, 0;
	ld.const.u32 	%r453, [params+108];
	@%p203 bra 	$L__BB0_171;

	setp.eq.s32 	%p204, %r453, 0;
	ld.const.u64 	%rd62, [params+224];
	cvta.to.global.u64 	%rd63, %rd62;
	ld.const.u32 	%r436, [params+216];
	mad.lo.s32 	%r437, %r436, %r4, %r3;
	mul.wide.u32 	%rd64, %r437, 8;
	add.s64 	%rd16, %rd63, %rd64;
	@%p204 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs108, %rs109, %rs110, %rs111}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f1566, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1567, %rs109;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1568, %rs110;}

	// end inline asm
	add.f32 	%f1569, %f1566, 0f00000000;
	add.f32 	%f1570, %f1567, 0f00000000;
	add.f32 	%f1571, %f1568, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1571;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1570;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1569;}

	// end inline asm
	mov.u16 	%rs112, 0;
	st.global.v4.u16 	[%rd16], {%rs105, %rs106, %rs107, %rs112};
	bra.uni 	$L__BB0_171;

$L__BB0_5:
	ld.const.u64 	%rd24, [params+432];
	cvta.to.global.u64 	%rd25, %rd24;
	ld.const.u32 	%r38, [params+424];
	mad.lo.s32 	%r39, %r38, %r27, %r26;
	mul.wide.u32 	%rd26, %r39, 12;
	add.s64 	%rd27, %rd25, %rd26;
	ld.global.f32 	%f10, [%rd27];
	mul.f32 	%f327, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd27+4];
	mul.f32 	%f328, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd27+8];
	mul.f32 	%f329, %f12, 0f3456BF95;
	abs.f32 	%f330, %f1614;
	div.rn.f32 	%f331, %f327, %f330;
	abs.f32 	%f332, %f1615;
	div.rn.f32 	%f333, %f328, %f332;
	abs.f32 	%f334, %f1616;
	div.rn.f32 	%f335, %f329, %f334;
	abs.f32 	%f336, %f331;
	abs.f32 	%f337, %f333;
	abs.f32 	%f338, %f335;
	mov.f32 	%f339, 0f38D1B717;
	max.f32 	%f340, %f336, %f339;
	max.f32 	%f341, %f337, %f339;
	max.f32 	%f342, %f338, %f339;
	fma.rn.f32 	%f13, %f1614, %f340, %f10;
	fma.rn.f32 	%f14, %f1615, %f341, %f11;
	fma.rn.f32 	%f15, %f1616, %f342, %f12;
	ld.const.u32 	%r5, [params+600];
	setp.eq.s32 	%p18, %r5, 0;
	@%p18 bra 	$L__BB0_58;

	ld.const.u64 	%rd28, [params+608];
	cvta.to.global.u64 	%rd2, %rd28;
	mov.f32 	%f359, 0f40000000;
	cvt.rzi.f32.f32 	%f360, %f359;
	add.f32 	%f361, %f360, %f360;
	mov.f32 	%f362, 0f40800000;
	sub.f32 	%f363, %f362, %f361;
	abs.f32 	%f16, %f363;
	ld.const.u32 	%r6, [params+544];
	ld.const.u32 	%r451, [params+104];
	mul.f32 	%f17, %f13, 0f3456BF95;
	mul.f32 	%f18, %f14, 0f3456BF95;
	mul.f32 	%f19, %f15, 0f3456BF95;
	mov.f32 	%f358, 0f00000000;
	mov.u32 	%r447, 0;
	ld.const.u64 	%rd3, [params+96];
	abs.f32 	%f565, %f17;
	abs.f32 	%f566, %f18;
	max.f32 	%f567, %f565, %f566;
	abs.f32 	%f568, %f19;
	max.f32 	%f569, %f567, %f568;
	mov.f32 	%f1683, %f358;
	mov.f32 	%f1682, %f358;
	mov.f32 	%f1681, %f358;
	mov.f32 	%f1680, %f358;
	mov.f32 	%f1679, %f358;
	mov.f32 	%f1678, %f358;
	mov.f32 	%f1677, %f358;
	mov.f32 	%f1676, %f358;
	mov.f32 	%f1675, %f358;
	mov.f32 	%f1674, %f358;
	mov.f32 	%f1673, %f358;
	mov.f32 	%f1672, %f358;
	mov.f32 	%f1671, %f358;
	mov.f32 	%f1670, %f358;
	mov.f32 	%f1669, %f358;
	mov.f32 	%f1668, %f358;

$L__BB0_7:
	mul.wide.u32 	%rd29, %r447, 112;
	add.s64 	%rd5, %rd2, %rd29;
	ld.global.v4.f32 	{%f365, %f366, %f367, %f368}, [%rd5];
	ld.global.v4.f32 	{%f369, %f370, %f371, %f372}, [%rd5+16];
	ld.global.v4.f32 	{%f375, %f1641, %f1642, %f378}, [%rd5+32];
	ld.global.v4.f32 	{%f379, %f380, %f381, %f1639}, [%rd5+48];
	ld.global.v4.f32 	{%f383, %f384, %f385, %f386}, [%rd5+64];
	ld.global.v4.u32 	{%r41, %r42, %r43, %r44}, [%rd5+80];
	mov.b32 	%f55, %r43;
	mov.b32 	%f54, %r42;
	mov.b32 	%f53, %r41;
	ld.global.u64 	%rd6, [%rd5+96];
	sub.f32 	%f387, %f366, %f10;
	sub.f32 	%f388, %f367, %f11;
	sub.f32 	%f389, %f368, %f12;
	mul.f32 	%f390, %f388, %f388;
	fma.rn.f32 	%f391, %f387, %f387, %f390;
	fma.rn.f32 	%f392, %f389, %f389, %f391;
	sqrt.rn.f32 	%f393, %f392;
	rcp.rn.f32 	%f394, %f393;
	mul.f32 	%f57, %f387, %f394;
	mul.f32 	%f58, %f388, %f394;
	mul.f32 	%f59, %f389, %f394;
	mul.f32 	%f60, %f393, %f370;
	mul.f32 	%f61, %f393, %f372;
	abs.f32 	%f62, %f61;
	setp.lt.f32 	%p19, %f62, 0f00800000;
	mul.f32 	%f395, %f62, 0f4B800000;
	selp.f32 	%f396, %f395, %f62, %p19;
	selp.f32 	%f397, 0fC3170000, 0fC2FE0000, %p19;
	mov.b32 	%r48, %f396;
	and.b32  	%r49, %r48, 8388607;
	or.b32  	%r50, %r49, 1065353216;
	mov.b32 	%f398, %r50;
	shr.u32 	%r51, %r48, 23;
	cvt.rn.f32.u32 	%f399, %r51;
	add.f32 	%f400, %f397, %f399;
	setp.gt.f32 	%p20, %f398, 0f3FB504F3;
	mul.f32 	%f401, %f398, 0f3F000000;
	add.f32 	%f402, %f400, 0f3F800000;
	selp.f32 	%f403, %f402, %f400, %p20;
	selp.f32 	%f404, %f401, %f398, %p20;
	add.f32 	%f405, %f404, 0fBF800000;
	add.f32 	%f406, %f404, 0f3F800000;
	rcp.approx.ftz.f32 	%f407, %f406;
	add.f32 	%f408, %f405, %f405;
	mul.f32 	%f409, %f408, %f407;
	mul.f32 	%f410, %f409, %f409;
	mov.f32 	%f411, 0f3C4CAF63;
	mov.f32 	%f412, 0f3B18F0FE;
	fma.rn.f32 	%f413, %f412, %f410, %f411;
	mov.f32 	%f414, 0f3DAAAABD;
	fma.rn.f32 	%f415, %f413, %f410, %f414;
	mul.rn.f32 	%f416, %f415, %f410;
	mul.rn.f32 	%f417, %f416, %f409;
	sub.f32 	%f418, %f405, %f409;
	add.f32 	%f419, %f418, %f418;
	neg.f32 	%f420, %f409;
	fma.rn.f32 	%f421, %f420, %f405, %f419;
	mul.rn.f32 	%f422, %f407, %f421;
	add.f32 	%f423, %f417, %f409;
	sub.f32 	%f424, %f409, %f423;
	add.f32 	%f425, %f417, %f424;
	add.f32 	%f426, %f422, %f425;
	add.f32 	%f427, %f423, %f426;
	sub.f32 	%f428, %f423, %f427;
	add.f32 	%f429, %f426, %f428;
	mov.f32 	%f430, 0f3F317200;
	mul.rn.f32 	%f431, %f403, %f430;
	mov.f32 	%f432, 0f35BFBE8E;
	mul.rn.f32 	%f433, %f403, %f432;
	add.f32 	%f434, %f431, %f427;
	sub.f32 	%f435, %f431, %f434;
	add.f32 	%f436, %f427, %f435;
	add.f32 	%f437, %f429, %f436;
	add.f32 	%f438, %f433, %f437;
	add.f32 	%f439, %f434, %f438;
	sub.f32 	%f440, %f434, %f439;
	add.f32 	%f441, %f438, %f440;
	mul.rn.f32 	%f443, %f362, %f439;
	neg.f32 	%f444, %f443;
	fma.rn.f32 	%f445, %f362, %f439, %f444;
	fma.rn.f32 	%f446, %f362, %f441, %f445;
	fma.rn.f32 	%f448, %f358, %f439, %f446;
	add.rn.f32 	%f449, %f443, %f448;
	neg.f32 	%f450, %f449;
	add.rn.f32 	%f451, %f443, %f450;
	add.rn.f32 	%f452, %f451, %f448;
	mov.b32 	%r52, %f449;
	setp.eq.s32 	%p21, %r52, 1118925336;
	add.s32 	%r53, %r52, -1;
	mov.b32 	%f453, %r53;
	add.f32 	%f454, %f452, 0f37000000;
	selp.f32 	%f63, %f454, %f452, %p21;
	selp.f32 	%f455, %f453, %f449, %p21;
	mov.f32 	%f456, 0f3FB8AA3B;
	mul.rn.f32 	%f457, %f455, %f456;
	cvt.rzi.f32.f32 	%f458, %f457;
	abs.f32 	%f459, %f458;
	setp.gt.f32 	%p22, %f459, 0f42FC0000;
	mov.b32 	%r54, %f458;
	and.b32  	%r55, %r54, -2147483648;
	or.b32  	%r56, %r55, 1123811328;
	mov.b32 	%f460, %r56;
	selp.f32 	%f461, %f460, %f458, %p22;
	mov.f32 	%f462, 0fBF317218;
	fma.rn.f32 	%f463, %f461, %f462, %f455;
	mov.f32 	%f464, 0f3102E308;
	fma.rn.f32 	%f465, %f461, %f464, %f463;
	mul.f32 	%f466, %f465, 0f3FB8AA3B;
	add.f32 	%f467, %f461, 0f4B40007F;
	mov.b32 	%r57, %f467;
	shl.b32 	%r58, %r57, 23;
	mov.b32 	%f468, %r58;
	ex2.approx.ftz.f32 	%f469, %f466;
	mul.f32 	%f64, %f469, %f468;
	setp.eq.f32 	%p23, %f64, 0f7F800000;
	mov.f32 	%f1633, 0f7F800000;
	@%p23 bra 	$L__BB0_9;

	fma.rn.f32 	%f1633, %f64, %f63, %f64;

$L__BB0_9:
	setp.lt.f32 	%p24, %f61, 0f00000000;
	setp.eq.f32 	%p25, %f16, 0f3F800000;
	and.pred  	%p1, %p24, %p25;
	setp.eq.f32 	%p26, %f61, 0f00000000;
	@%p26 bra 	$L__BB0_13;
	bra.uni 	$L__BB0_10;

$L__BB0_13:
	add.f32 	%f474, %f61, %f61;
	selp.f32 	%f1635, %f474, 0f00000000, %p25;
	bra.uni 	$L__BB0_14;

$L__BB0_10:
	mov.b32 	%r59, %f1633;
	xor.b32  	%r60, %r59, -2147483648;
	mov.b32 	%f470, %r60;
	selp.f32 	%f1635, %f470, %f1633, %p1;
	setp.geu.f32 	%p27, %f61, 0f00000000;
	@%p27 bra 	$L__BB0_14;

	mov.f32 	%f471, 0f40800000;
	cvt.rzi.f32.f32 	%f472, %f471;
	setp.eq.f32 	%p28, %f472, 0f40800000;
	@%p28 bra 	$L__BB0_14;

	mov.f32 	%f1635, 0f7FFFFFFF;

$L__BB0_14:
	abs.f32 	%f1611, %f61;
	add.f32 	%f475, %f1611, 0f40800000;
	mov.b32 	%r61, %f475;
	setp.lt.s32 	%p30, %r61, 2139095040;
	@%p30 bra 	$L__BB0_19;

	abs.f32 	%f1612, %f61;
	setp.gtu.f32 	%p31, %f1612, 0f7F800000;
	@%p31 bra 	$L__BB0_18;
	bra.uni 	$L__BB0_16;

$L__BB0_18:
	add.f32 	%f1635, %f61, 0f40800000;
	bra.uni 	$L__BB0_19;

$L__BB0_16:
	abs.f32 	%f1613, %f61;
	setp.neu.f32 	%p32, %f1613, 0f7F800000;
	@%p32 bra 	$L__BB0_19;

	selp.f32 	%f1635, 0fFF800000, 0f7F800000, %p1;

$L__BB0_19:
	mov.f32 	%f476, 0f3F800000;
	sub.f32 	%f477, %f476, %f1635;
	setp.eq.f32 	%p33, %f61, 0f3F800000;
	selp.f32 	%f478, 0f00000000, %f477, %p33;
	cvt.sat.f32.f32 	%f479, %f478;
	fma.rn.f32 	%f480, %f60, %f60, %f371;
	div.rn.f32 	%f73, %f479, %f480;
	mul.f32 	%f481, %f1615, %f58;
	fma.rn.f32 	%f482, %f1614, %f57, %f481;
	fma.rn.f32 	%f483, %f1616, %f59, %f482;
	setp.eq.s32 	%p34, %r6, 0;
	selp.f32 	%f74, %f483, 0f3F800000, %p34;
	mul.f32 	%f484, %f74, 0f40800000;
	cvt.sat.f32.f32 	%f75, %f484;
	setp.eq.f32 	%p35, %f365, 0f3F800000;
	@%p35 bra 	$L__BB0_25;
	bra.uni 	$L__BB0_20;

$L__BB0_25:
	setp.eq.s64 	%p39, %rd6, 0;
	mov.f32 	%f1640, %f375;
	mov.f32 	%f1643, %f73;
	@%p39 bra 	$L__BB0_29;

	setp.geu.f32 	%p40, %f1639, 0f00000000;
	mov.f32 	%f1636, %f57;
	mov.f32 	%f1637, %f58;
	mov.f32 	%f1638, %f59;
	@%p40 bra 	$L__BB0_28;

	mul.f32 	%f509, %f54, %f388;
	fma.rn.f32 	%f510, %f53, %f387, %f509;
	fma.rn.f32 	%f512, %f55, %f389, %f510;
	rcp.rn.f32 	%f513, %f512;
	mul.f32 	%f1636, %f387, %f513;
	mul.f32 	%f1637, %f388, %f513;
	mul.f32 	%f1638, %f389, %f513;
	neg.f32 	%f1639, %f1639;

$L__BB0_28:
	mul.f32 	%f514, %f55, %f59;
	mul.f32 	%f515, %f54, %f58;
	neg.f32 	%f516, %f515;
	mul.f32 	%f517, %f53, %f57;
	sub.f32 	%f518, %f516, %f517;
	sub.f32 	%f519, %f518, %f514;
	setp.gt.f32 	%p41, %f519, 0f00000000;
	selp.f32 	%f520, 0f3F800000, 0f00000000, %p41;
	mov.f32 	%f521, 0f3F800000;
	mul.f32 	%f522, %f380, %f1637;
	mul.f32 	%f523, %f384, %f1637;
	fma.rn.f32 	%f524, %f379, %f1636, %f522;
	fma.rn.f32 	%f525, %f383, %f1636, %f523;
	fma.rn.f32 	%f526, %f381, %f1638, %f524;
	fma.rn.f32 	%f527, %f385, %f1638, %f525;
	fma.rn.f32 	%f528, %f1639, %f526, 0f3F000000;
	sub.f32 	%f529, %f521, %f528;
	fma.rn.f32 	%f530, %f1639, %f527, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f531, %f532, %f533, %f534}, [%rd6, {%f529, %f530}];
	mul.f32 	%f535, %f520, %f531;
	mul.f32 	%f536, %f520, %f532;
	mul.f32 	%f537, %f520, %f533;
	mul.f32 	%f1640, %f375, %f535;
	mul.f32 	%f1641, %f1641, %f536;
	mul.f32 	%f1642, %f1642, %f537;
	mov.f32 	%f1643, %f73;
	bra.uni 	$L__BB0_29;

$L__BB0_20:
	setp.eq.f32 	%p36, %f365, 0f40000000;
	@%p36 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_21;

$L__BB0_23:
	setp.eq.s64 	%p38, %rd6, 0;
	mov.f32 	%f1640, %f375;
	mov.f32 	%f1643, %f73;
	@%p38 bra 	$L__BB0_29;

	mul.f32 	%f494, %f380, %f58;
	mul.f32 	%f495, %f384, %f58;
	mul.f32 	%f496, %f54, %f58;
	fma.rn.f32 	%f497, %f379, %f57, %f494;
	fma.rn.f32 	%f498, %f383, %f57, %f495;
	fma.rn.f32 	%f499, %f53, %f57, %f496;
	fma.rn.f32 	%f500, %f381, %f59, %f497;
	fma.rn.f32 	%f501, %f385, %f59, %f498;
	fma.rn.f32 	%f502, %f55, %f59, %f499;
	tex.cube.v4.f32.f32 	{%f503, %f504, %f505, %f506}, [%rd6, {%f500, %f501, %f502, %f502}];
	mul.f32 	%f1640, %f375, %f503;
	mul.f32 	%f1641, %f1641, %f504;
	mul.f32 	%f1642, %f1642, %f505;
	mov.f32 	%f1643, %f73;
	bra.uni 	$L__BB0_29;

$L__BB0_21:
	setp.neu.f32 	%p37, %f365, 0f40800000;
	mov.f32 	%f1640, %f375;
	mov.f32 	%f1643, %f73;
	@%p37 bra 	$L__BB0_29;

	mul.f32 	%f485, %f53, %f57;
	mul.f32 	%f486, %f54, %f58;
	neg.f32 	%f487, %f486;
	sub.f32 	%f488, %f487, %f485;
	mul.f32 	%f489, %f55, %f59;
	sub.f32 	%f490, %f488, %f489;
	fma.rn.f32 	%f491, %f378, %f490, %f1639;
	cvt.sat.f32.f32 	%f492, %f491;
	mul.f32 	%f493, %f492, %f492;
	mul.f32 	%f1643, %f73, %f493;
	mov.f32 	%f1640, %f375;

$L__BB0_29:
	max.f32 	%f553, %f1640, %f1641;
	max.f32 	%f554, %f553, %f1642;
	mul.f32 	%f555, %f75, %f1643;
	mul.f32 	%f556, %f555, %f554;
	setp.lt.f32 	%p43, %f556, 0f3727C5AC;
	mov.pred 	%p209, -1;
	mov.f32 	%f1644, 0f00000000;
	mov.f32 	%f1645, %f1644;
	mov.f32 	%f1646, %f1644;
	mov.f32 	%f1647, %f1644;
	mov.f32 	%f1648, %f1644;
	mov.f32 	%f1649, %f1644;
	mov.f32 	%f1650, %f1644;
	mov.f32 	%f1651, %f1644;
	mov.f32 	%f1652, %f1644;
	mov.f32 	%f1653, %f1644;
	mov.f32 	%f1654, %f1644;
	mov.f32 	%f1655, %f1644;
	mov.f32 	%f1656, %f1644;
	mov.f32 	%f1657, %f1644;
	mov.f32 	%f1658, %f1644;
	@%p43 bra 	$L__BB0_31;

	cvt.sat.f32.f32 	%f557, %f74;
	mul.f32 	%f558, %f1643, %f557;
	mul.f32 	%f1645, %f1640, %f558;
	mul.f32 	%f1644, %f1641, %f558;
	mul.f32 	%f1646, %f1642, %f558;
	mul.f32 	%f559, %f1643, 0f3E800000;
	mul.f32 	%f560, %f75, %f559;
	mul.f32 	%f1647, %f1640, %f560;
	mul.f32 	%f1648, %f1641, %f560;
	mul.f32 	%f1649, %f1642, %f560;
	mul.f32 	%f1650, %f57, %f1647;
	mul.f32 	%f1651, %f57, %f1648;
	mul.f32 	%f1652, %f57, %f1649;
	mul.f32 	%f1653, %f58, %f1647;
	mul.f32 	%f1654, %f58, %f1648;
	mul.f32 	%f1655, %f58, %f1649;
	mul.f32 	%f1656, %f59, %f1647;
	mul.f32 	%f1657, %f59, %f1648;
	mul.f32 	%f1658, %f59, %f1649;
	mov.pred 	%p209, 0;

$L__BB0_31:
	@%p209 bra 	$L__BB0_57;

	setp.eq.s32 	%p45, %r44, 0;
	mov.u16 	%rs179, 0;
	mov.f32 	%f1667, 0f3F800000;
	@%p45 bra 	$L__BB0_40;

	abs.s32 	%r10, %r44;
	setp.lt.s32 	%p46, %r10, 1;
	mov.f32 	%f1660, 0f00000000;
	@%p46 bra 	$L__BB0_39;

	mov.f32 	%f570, 0f38D1B717;
	max.f32 	%f571, %f569, %f570;
	and.b32  	%r63, %r451, 32;
	setp.eq.s32 	%p47, %r63, 0;
	mov.u32 	%r450, 0;
	selp.f32 	%f572, 0f3F800000, 0f41200000, %p47;
	mul.f32 	%f138, %f572, %f571;
	and.b32  	%r11, %r10, 1;
	setp.eq.s32 	%p48, %r10, 1;
	mov.f32 	%f1660, 0f00000000;
	@%p48 bra 	$L__BB0_37;

	sub.s32 	%r449, %r10, %r11;

$L__BB0_36:
	cvt.rn.f32.s32 	%f592, %r450;
	mul.f32 	%f593, %f592, 0f3DD32618;
	cvt.rmi.f32.f32 	%f594, %f593;
	sub.f32 	%f595, %f593, %f594;
	mul.f32 	%f596, %f592, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f597, %f596;
	sub.f32 	%f598, %f596, %f597;
	mul.f32 	%f599, %f592, 0f3DC74539;
	cvt.rmi.f32.f32 	%f600, %f599;
	sub.f32 	%f601, %f599, %f600;
	add.f32 	%f602, %f598, 0f4199851F;
	add.f32 	%f603, %f601, 0f4199851F;
	add.f32 	%f604, %f595, 0f4199851F;
	mul.f32 	%f605, %f598, %f603;
	fma.rn.f32 	%f606, %f595, %f602, %f605;
	fma.rn.f32 	%f607, %f604, %f601, %f606;
	add.f32 	%f608, %f595, %f607;
	add.f32 	%f609, %f598, %f607;
	add.f32 	%f610, %f601, %f607;
	add.f32 	%f611, %f608, %f609;
	mul.f32 	%f612, %f610, %f611;
	cvt.rmi.f32.f32 	%f613, %f612;
	sub.f32 	%f614, %f612, %f613;
	add.f32 	%f615, %f608, %f610;
	mul.f32 	%f616, %f609, %f615;
	cvt.rmi.f32.f32 	%f617, %f616;
	sub.f32 	%f618, %f616, %f617;
	add.f32 	%f619, %f609, %f610;
	mul.f32 	%f620, %f608, %f619;
	cvt.rmi.f32.f32 	%f621, %f620;
	sub.f32 	%f622, %f620, %f621;
	fma.rn.f32 	%f623, %f614, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f624, %f618, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f625, %f622, 0f40000000, 0fBF800000;
	ld.global.f32 	%f626, [%rd5+16];
	ld.global.f32 	%f627, [%rd5+4];
	fma.rn.f32 	%f628, %f626, %f623, %f627;
	ld.global.f32 	%f629, [%rd5+8];
	fma.rn.f32 	%f630, %f626, %f624, %f629;
	ld.global.f32 	%f631, [%rd5+12];
	fma.rn.f32 	%f632, %f626, %f625, %f631;
	sub.f32 	%f633, %f628, %f10;
	sub.f32 	%f634, %f630, %f11;
	sub.f32 	%f635, %f632, %f12;
	mul.f32 	%f636, %f634, %f634;
	fma.rn.f32 	%f637, %f633, %f633, %f636;
	fma.rn.f32 	%f638, %f635, %f635, %f637;
	sqrt.rn.f32 	%f581, %f638;
	rcp.rn.f32 	%f639, %f581;
	mul.f32 	%f577, %f639, %f633;
	mul.f32 	%f578, %f639, %f634;
	mul.f32 	%f579, %f639, %f635;
	mov.f32 	%f591, 0f00000000;
	mov.u32 	%r172, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f577,%f578,%f579,%f138,%f581,%f591,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f640, %r65;
	add.f32 	%f641, %f1660, %f640;
	add.s32 	%r207, %r450, 1;
	cvt.rn.f32.s32 	%f642, %r207;
	mul.f32 	%f643, %f642, 0f3DD32618;
	cvt.rmi.f32.f32 	%f644, %f643;
	sub.f32 	%f645, %f643, %f644;
	mul.f32 	%f646, %f642, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f647, %f646;
	sub.f32 	%f648, %f646, %f647;
	mul.f32 	%f649, %f642, 0f3DC74539;
	cvt.rmi.f32.f32 	%f650, %f649;
	sub.f32 	%f651, %f649, %f650;
	add.f32 	%f652, %f648, 0f4199851F;
	add.f32 	%f653, %f651, 0f4199851F;
	add.f32 	%f654, %f645, 0f4199851F;
	mul.f32 	%f655, %f648, %f653;
	fma.rn.f32 	%f656, %f645, %f652, %f655;
	fma.rn.f32 	%f657, %f654, %f651, %f656;
	add.f32 	%f658, %f645, %f657;
	add.f32 	%f659, %f648, %f657;
	add.f32 	%f660, %f651, %f657;
	add.f32 	%f661, %f658, %f659;
	mul.f32 	%f662, %f660, %f661;
	cvt.rmi.f32.f32 	%f663, %f662;
	sub.f32 	%f664, %f662, %f663;
	add.f32 	%f665, %f658, %f660;
	mul.f32 	%f666, %f659, %f665;
	cvt.rmi.f32.f32 	%f667, %f666;
	sub.f32 	%f668, %f666, %f667;
	add.f32 	%f669, %f659, %f660;
	mul.f32 	%f670, %f658, %f669;
	cvt.rmi.f32.f32 	%f671, %f670;
	sub.f32 	%f672, %f670, %f671;
	fma.rn.f32 	%f673, %f664, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f674, %f668, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f675, %f672, 0f40000000, 0fBF800000;
	ld.global.f32 	%f676, [%rd5+16];
	ld.global.f32 	%f677, [%rd5+4];
	fma.rn.f32 	%f678, %f676, %f673, %f677;
	ld.global.f32 	%f679, [%rd5+8];
	fma.rn.f32 	%f680, %f676, %f674, %f679;
	ld.global.f32 	%f681, [%rd5+12];
	fma.rn.f32 	%f682, %f676, %f675, %f681;
	sub.f32 	%f683, %f678, %f10;
	sub.f32 	%f684, %f680, %f11;
	sub.f32 	%f685, %f682, %f12;
	mul.f32 	%f686, %f684, %f684;
	fma.rn.f32 	%f687, %f683, %f683, %f686;
	fma.rn.f32 	%f688, %f685, %f685, %f687;
	sqrt.rn.f32 	%f590, %f688;
	rcp.rn.f32 	%f689, %f590;
	mul.f32 	%f586, %f689, %f683;
	mul.f32 	%f587, %f689, %f684;
	mul.f32 	%f588, %f689, %f685;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f586,%f587,%f588,%f138,%f590,%f591,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f690, %r136;
	add.f32 	%f1660, %f641, %f690;
	add.s32 	%r450, %r450, 2;
	add.s32 	%r449, %r449, -2;
	setp.ne.s32 	%p49, %r449, 0;
	@%p49 bra 	$L__BB0_36;

$L__BB0_37:
	setp.eq.s32 	%p50, %r11, 0;
	@%p50 bra 	$L__BB0_39;

	cvt.rn.f32.s32 	%f700, %r450;
	mul.f32 	%f701, %f700, 0f3DD32618;
	cvt.rmi.f32.f32 	%f702, %f701;
	sub.f32 	%f703, %f701, %f702;
	mul.f32 	%f704, %f700, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f705, %f704;
	sub.f32 	%f706, %f704, %f705;
	mul.f32 	%f707, %f700, 0f3DC74539;
	cvt.rmi.f32.f32 	%f708, %f707;
	sub.f32 	%f709, %f707, %f708;
	add.f32 	%f710, %f706, 0f4199851F;
	add.f32 	%f711, %f709, 0f4199851F;
	add.f32 	%f712, %f703, 0f4199851F;
	mul.f32 	%f713, %f706, %f711;
	fma.rn.f32 	%f714, %f703, %f710, %f713;
	fma.rn.f32 	%f715, %f712, %f709, %f714;
	add.f32 	%f716, %f703, %f715;
	add.f32 	%f717, %f706, %f715;
	add.f32 	%f718, %f709, %f715;
	add.f32 	%f719, %f716, %f717;
	mul.f32 	%f720, %f718, %f719;
	cvt.rmi.f32.f32 	%f721, %f720;
	sub.f32 	%f722, %f720, %f721;
	add.f32 	%f723, %f716, %f718;
	mul.f32 	%f724, %f717, %f723;
	cvt.rmi.f32.f32 	%f725, %f724;
	sub.f32 	%f726, %f724, %f725;
	add.f32 	%f727, %f717, %f718;
	mul.f32 	%f728, %f716, %f727;
	cvt.rmi.f32.f32 	%f729, %f728;
	sub.f32 	%f730, %f728, %f729;
	fma.rn.f32 	%f731, %f722, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f732, %f726, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f733, %f730, 0f40000000, 0fBF800000;
	ld.global.f32 	%f734, [%rd5+16];
	ld.global.f32 	%f735, [%rd5+4];
	fma.rn.f32 	%f736, %f734, %f731, %f735;
	ld.global.f32 	%f737, [%rd5+8];
	fma.rn.f32 	%f738, %f734, %f732, %f737;
	ld.global.f32 	%f739, [%rd5+12];
	fma.rn.f32 	%f740, %f734, %f733, %f739;
	sub.f32 	%f741, %f736, %f10;
	sub.f32 	%f742, %f738, %f11;
	sub.f32 	%f743, %f740, %f12;
	mul.f32 	%f744, %f742, %f742;
	fma.rn.f32 	%f745, %f741, %f741, %f744;
	fma.rn.f32 	%f746, %f743, %f743, %f745;
	sqrt.rn.f32 	%f698, %f746;
	rcp.rn.f32 	%f747, %f698;
	mul.f32 	%f694, %f747, %f741;
	mul.f32 	%f695, %f747, %f742;
	mul.f32 	%f696, %f747, %f743;
	mov.f32 	%f699, 0f00000000;
	mov.u32 	%r244, 2;
	mov.u32 	%r246, 1;
	mov.u32 	%r247, 1065353216;
	mov.u32 	%r278, 0;
	// begin inline asm
	call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f694,%f695,%f696,%f138,%f698,%f699,%r246,%r278,%r246,%r244,%r246,%r246,%r247,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
	// end inline asm
	mov.b32 	%f748, %r208;
	add.f32 	%f1660, %f1660, %f748;

$L__BB0_39:
	cvt.rn.f32.s32 	%f749, %r10;
	div.rn.f32 	%f1667, %f1660, %f749;
	shr.u32 	%r279, %r44, 31;
	cvt.u16.u32 	%rs179, %r279;

$L__BB0_40:
	fma.rn.f32 	%f1668, %f1645, %f1667, %f1668;
	fma.rn.f32 	%f1669, %f1644, %f1667, %f1669;
	fma.rn.f32 	%f1670, %f1646, %f1667, %f1670;
	fma.rn.f32 	%f1671, %f1647, %f1667, %f1671;
	fma.rn.f32 	%f1672, %f1648, %f1667, %f1672;
	fma.rn.f32 	%f1673, %f1649, %f1667, %f1673;
	fma.rn.f32 	%f1674, %f1650, %f1667, %f1674;
	fma.rn.f32 	%f1675, %f1651, %f1667, %f1675;
	fma.rn.f32 	%f1676, %f1652, %f1667, %f1676;
	fma.rn.f32 	%f1677, %f1653, %f1667, %f1677;
	fma.rn.f32 	%f1678, %f1654, %f1667, %f1678;
	fma.rn.f32 	%f1679, %f1655, %f1667, %f1679;
	fma.rn.f32 	%f1680, %f1656, %f1667, %f1680;
	fma.rn.f32 	%f1681, %f1657, %f1667, %f1681;
	fma.rn.f32 	%f1682, %f1658, %f1667, %f1682;
	setp.eq.s16 	%p51, %rs179, 0;
	@%p51 bra 	$L__BB0_56;

	mul.f32 	%f751, %f1650, 0f3F000000;
	mul.f32 	%f752, %f1653, 0f3F000000;
	mul.f32 	%f753, %f752, %f752;
	fma.rn.f32 	%f754, %f751, %f751, %f753;
	mul.f32 	%f755, %f1656, 0f3F000000;
	fma.rn.f32 	%f756, %f755, %f755, %f754;
	sqrt.rn.f32 	%f757, %f756;
	rcp.rn.f32 	%f758, %f757;
	mov.f32 	%f759, 0f3F800000;
	mul.f32 	%f760, %f751, %f758;
	mul.f32 	%f761, %f752, %f758;
	mul.f32 	%f762, %f755, %f758;
	mul.f32 	%f763, %f1615, %f761;
	fma.rn.f32 	%f764, %f1614, %f760, %f763;
	fma.rn.f32 	%f765, %f1616, %f762, %f764;
	fma.rn.f32 	%f162, %f765, 0f3F000000, 0f3F000000;
	add.f32 	%f766, %f757, %f757;
	div.rn.f32 	%f767, %f766, %f1647;
	add.f32 	%f163, %f767, 0f3F800000;
	div.rn.f32 	%f768, %f757, %f1647;
	sub.f32 	%f769, %f759, %f768;
	add.f32 	%f770, %f768, 0f3F800000;
	div.rn.f32 	%f164, %f769, %f770;
	sub.f32 	%f771, %f759, %f164;
	add.f32 	%f772, %f163, 0f3F800000;
	mul.f32 	%f165, %f771, %f772;
	mul.f32 	%f773, %f163, 0f3F000000;
	cvt.rzi.f32.f32 	%f774, %f773;
	add.f32 	%f775, %f774, %f774;
	sub.f32 	%f776, %f163, %f775;
	abs.f32 	%f166, %f776;
	abs.f32 	%f167, %f162;
	setp.lt.f32 	%p52, %f167, 0f00800000;
	mul.f32 	%f777, %f167, 0f4B800000;
	selp.f32 	%f778, %f777, %f167, %p52;
	selp.f32 	%f779, 0fC3170000, 0fC2FE0000, %p52;
	mov.b32 	%r280, %f778;
	and.b32  	%r281, %r280, 8388607;
	or.b32  	%r282, %r281, 1065353216;
	mov.b32 	%f780, %r282;
	shr.u32 	%r283, %r280, 23;
	cvt.rn.f32.u32 	%f781, %r283;
	add.f32 	%f782, %f779, %f781;
	setp.gt.f32 	%p53, %f780, 0f3FB504F3;
	mul.f32 	%f783, %f780, 0f3F000000;
	add.f32 	%f784, %f782, 0f3F800000;
	selp.f32 	%f785, %f784, %f782, %p53;
	selp.f32 	%f786, %f783, %f780, %p53;
	add.f32 	%f787, %f786, 0fBF800000;
	add.f32 	%f788, %f786, 0f3F800000;
	rcp.approx.ftz.f32 	%f789, %f788;
	add.f32 	%f790, %f787, %f787;
	mul.f32 	%f791, %f790, %f789;
	mul.f32 	%f792, %f791, %f791;
	mov.f32 	%f793, 0f3C4CAF63;
	mov.f32 	%f794, 0f3B18F0FE;
	fma.rn.f32 	%f795, %f794, %f792, %f793;
	mov.f32 	%f796, 0f3DAAAABD;
	fma.rn.f32 	%f797, %f795, %f792, %f796;
	mul.rn.f32 	%f798, %f797, %f792;
	mul.rn.f32 	%f799, %f798, %f791;
	sub.f32 	%f800, %f787, %f791;
	add.f32 	%f801, %f800, %f800;
	neg.f32 	%f802, %f791;
	fma.rn.f32 	%f803, %f802, %f787, %f801;
	mul.rn.f32 	%f804, %f789, %f803;
	add.f32 	%f805, %f799, %f791;
	sub.f32 	%f806, %f791, %f805;
	add.f32 	%f807, %f799, %f806;
	add.f32 	%f808, %f804, %f807;
	add.f32 	%f809, %f805, %f808;
	sub.f32 	%f810, %f805, %f809;
	add.f32 	%f811, %f808, %f810;
	mov.f32 	%f812, 0f3F317200;
	mul.rn.f32 	%f813, %f785, %f812;
	mov.f32 	%f814, 0f35BFBE8E;
	mul.rn.f32 	%f815, %f785, %f814;
	add.f32 	%f816, %f813, %f809;
	sub.f32 	%f817, %f813, %f816;
	add.f32 	%f818, %f809, %f817;
	add.f32 	%f819, %f811, %f818;
	add.f32 	%f820, %f815, %f819;
	add.f32 	%f821, %f816, %f820;
	sub.f32 	%f822, %f816, %f821;
	add.f32 	%f823, %f820, %f822;
	abs.f32 	%f168, %f163;
	setp.gt.f32 	%p54, %f168, 0f77F684DF;
	mul.f32 	%f824, %f163, 0f39000000;
	selp.f32 	%f825, %f824, %f163, %p54;
	mul.rn.f32 	%f826, %f825, %f821;
	neg.f32 	%f827, %f826;
	fma.rn.f32 	%f828, %f825, %f821, %f827;
	fma.rn.f32 	%f829, %f825, %f823, %f828;
	mov.f32 	%f830, 0f00000000;
	fma.rn.f32 	%f831, %f830, %f821, %f829;
	add.rn.f32 	%f832, %f826, %f831;
	neg.f32 	%f833, %f832;
	add.rn.f32 	%f834, %f826, %f833;
	add.rn.f32 	%f835, %f834, %f831;
	mov.b32 	%r284, %f832;
	setp.eq.s32 	%p55, %r284, 1118925336;
	add.s32 	%r285, %r284, -1;
	mov.b32 	%f836, %r285;
	add.f32 	%f837, %f835, 0f37000000;
	selp.f32 	%f169, %f837, %f835, %p55;
	selp.f32 	%f838, %f836, %f832, %p55;
	mov.f32 	%f839, 0f3FB8AA3B;
	mul.rn.f32 	%f840, %f838, %f839;
	cvt.rzi.f32.f32 	%f841, %f840;
	abs.f32 	%f842, %f841;
	setp.gt.f32 	%p56, %f842, 0f42FC0000;
	mov.b32 	%r286, %f841;
	and.b32  	%r287, %r286, -2147483648;
	or.b32  	%r288, %r287, 1123811328;
	mov.b32 	%f843, %r288;
	selp.f32 	%f844, %f843, %f841, %p56;
	mov.f32 	%f845, 0fBF317218;
	fma.rn.f32 	%f846, %f844, %f845, %f838;
	mov.f32 	%f847, 0f3102E308;
	fma.rn.f32 	%f848, %f844, %f847, %f846;
	mul.f32 	%f849, %f848, 0f3FB8AA3B;
	add.f32 	%f850, %f844, 0f4B40007F;
	mov.b32 	%r289, %f850;
	shl.b32 	%r290, %r289, 23;
	mov.b32 	%f851, %r290;
	ex2.approx.ftz.f32 	%f852, %f849;
	mul.f32 	%f170, %f852, %f851;
	setp.eq.f32 	%p57, %f170, 0f7F800000;
	mov.f32 	%f1664, 0f7F800000;
	@%p57 bra 	$L__BB0_43;

	fma.rn.f32 	%f1664, %f170, %f169, %f170;

$L__BB0_43:
	setp.lt.f32 	%p58, %f162, 0f00000000;
	setp.eq.f32 	%p59, %f166, 0f3F800000;
	and.pred  	%p3, %p59, %p58;
	setp.eq.f32 	%p60, %f162, 0f00000000;
	@%p60 bra 	$L__BB0_47;
	bra.uni 	$L__BB0_44;

$L__BB0_47:
	add.f32 	%f856, %f162, %f162;
	mov.b32 	%r293, %f856;
	selp.b32 	%r294, %r293, 0, %p59;
	or.b32  	%r295, %r294, 2139095040;
	setp.lt.f32 	%p64, %f163, 0f00000000;
	selp.b32 	%r296, %r295, %r294, %p64;
	mov.b32 	%f1666, %r296;
	bra.uni 	$L__BB0_48;

$L__BB0_44:
	mov.b32 	%r291, %f1664;
	xor.b32  	%r292, %r291, -2147483648;
	mov.b32 	%f853, %r292;
	selp.f32 	%f1666, %f853, %f1664, %p3;
	setp.geu.f32 	%p61, %f162, 0f00000000;
	@%p61 bra 	$L__BB0_48;

	cvt.rzi.f32.f32 	%f854, %f163;
	setp.eq.f32 	%p62, %f854, %f163;
	@%p62 bra 	$L__BB0_48;

	mov.f32 	%f1666, 0f7FFFFFFF;

$L__BB0_48:
	add.f32 	%f857, %f167, %f168;
	mov.b32 	%r297, %f857;
	setp.lt.s32 	%p65, %r297, 2139095040;
	@%p65 bra 	$L__BB0_55;

	setp.gtu.f32 	%p66, %f167, 0f7F800000;
	setp.gtu.f32 	%p67, %f168, 0f7F800000;
	or.pred  	%p68, %p66, %p67;
	@%p68 bra 	$L__BB0_54;
	bra.uni 	$L__BB0_50;

$L__BB0_54:
	add.f32 	%f1666, %f163, %f162;
	bra.uni 	$L__BB0_55;

$L__BB0_50:
	setp.eq.f32 	%p69, %f168, 0f7F800000;
	@%p69 bra 	$L__BB0_53;
	bra.uni 	$L__BB0_51;

$L__BB0_53:
	setp.gt.f32 	%p72, %f167, 0f3F800000;
	selp.b32 	%r301, 2139095040, 0, %p72;
	xor.b32  	%r302, %r301, 2139095040;
	setp.lt.f32 	%p73, %f163, 0f00000000;
	selp.b32 	%r303, %r302, %r301, %p73;
	mov.b32 	%f858, %r303;
	setp.eq.f32 	%p74, %f162, 0fBF800000;
	selp.f32 	%f1666, 0f3F800000, %f858, %p74;
	bra.uni 	$L__BB0_55;

$L__BB0_51:
	setp.neu.f32 	%p70, %f167, 0f7F800000;
	@%p70 bra 	$L__BB0_55;

	setp.ge.f32 	%p71, %f163, 0f00000000;
	selp.b32 	%r298, 2139095040, 0, %p71;
	or.b32  	%r299, %r298, -2147483648;
	selp.b32 	%r300, %r299, %r298, %p3;
	mov.b32 	%f1666, %r300;

$L__BB0_55:
	setp.eq.f32 	%p75, %f163, 0f00000000;
	setp.eq.f32 	%p76, %f162, 0f3F800000;
	or.pred  	%p77, %p75, %p76;
	selp.f32 	%f859, 0f3F800000, %f1666, %p77;
	fma.rn.f32 	%f860, %f165, %f859, %f164;
	mul.f32 	%f861, %f1647, %f860;
	div.rn.f32 	%f862, %f861, %f375;
	div.rn.f32 	%f863, %f862, %f73;
	cvt.sat.f32.f32 	%f864, %f863;
	mul.f32 	%f1667, %f1667, %f864;

$L__BB0_56:
	add.f32 	%f1683, %f1683, %f1667;

$L__BB0_57:
	cvt.u64.u32 	%rd77, %r447;
	cvt.u32.u64 	%r304, %rd77;
	add.s32 	%r447, %r304, 1;
	setp.lt.u32 	%p78, %r447, %r5;
	@%p78 bra 	$L__BB0_7;
	bra.uni 	$L__BB0_59;

$L__BB0_58:
	mov.f32 	%f1668, 0f00000000;
	ld.const.u32 	%r451, [params+104];
	mov.f32 	%f1669, %f1668;
	mov.f32 	%f1670, %f1668;
	mov.f32 	%f1671, %f1668;
	mov.f32 	%f1672, %f1668;
	mov.f32 	%f1673, %f1668;
	mov.f32 	%f1674, %f1668;
	mov.f32 	%f1675, %f1668;
	mov.f32 	%f1676, %f1668;
	mov.f32 	%f1677, %f1668;
	mov.f32 	%f1678, %f1668;
	mov.f32 	%f1679, %f1668;
	mov.f32 	%f1680, %f1668;
	mov.f32 	%f1681, %f1668;
	mov.f32 	%f1682, %f1668;
	mov.f32 	%f1683, %f1668;

$L__BB0_59:
	and.b32  	%r305, %r451, 8;
	setp.eq.s32 	%p79, %r305, 0;
	@%p79 bra 	$L__BB0_73;

	cvt.sat.f32.f32 	%f215, %f1683;
	ld.const.u64 	%rd33, [params+192];
	cvta.to.global.u64 	%rd7, %rd33;
	ld.const.u32 	%r306, [params+184];
	mad.lo.s32 	%r307, %r306, %r4, %r3;
	cvt.u64.u32 	%rd8, %r307;
	mov.f32 	%f882, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f883, %f882;
	add.f32 	%f884, %f883, %f883;
	mov.f32 	%f885, 0f3EE8BA2E;
	sub.f32 	%f886, %f885, %f884;
	abs.f32 	%f216, %f886;
	abs.f32 	%f217, %f215;
	setp.lt.f32 	%p80, %f217, 0f00800000;
	mul.f32 	%f887, %f217, 0f4B800000;
	selp.f32 	%f888, %f887, %f217, %p80;
	selp.f32 	%f889, 0fC3170000, 0fC2FE0000, %p80;
	mov.b32 	%r308, %f888;
	and.b32  	%r309, %r308, 8388607;
	or.b32  	%r310, %r309, 1065353216;
	mov.b32 	%f890, %r310;
	shr.u32 	%r311, %r308, 23;
	cvt.rn.f32.u32 	%f891, %r311;
	add.f32 	%f892, %f889, %f891;
	setp.gt.f32 	%p81, %f890, 0f3FB504F3;
	mul.f32 	%f893, %f890, 0f3F000000;
	add.f32 	%f894, %f892, 0f3F800000;
	selp.f32 	%f895, %f894, %f892, %p81;
	selp.f32 	%f896, %f893, %f890, %p81;
	add.f32 	%f897, %f896, 0fBF800000;
	add.f32 	%f898, %f896, 0f3F800000;
	rcp.approx.ftz.f32 	%f899, %f898;
	add.f32 	%f900, %f897, %f897;
	mul.f32 	%f901, %f900, %f899;
	mul.f32 	%f902, %f901, %f901;
	mov.f32 	%f903, 0f3C4CAF63;
	mov.f32 	%f904, 0f3B18F0FE;
	fma.rn.f32 	%f905, %f904, %f902, %f903;
	mov.f32 	%f906, 0f3DAAAABD;
	fma.rn.f32 	%f907, %f905, %f902, %f906;
	mul.rn.f32 	%f908, %f907, %f902;
	mul.rn.f32 	%f909, %f908, %f901;
	sub.f32 	%f910, %f897, %f901;
	add.f32 	%f911, %f910, %f910;
	neg.f32 	%f912, %f901;
	fma.rn.f32 	%f913, %f912, %f897, %f911;
	mul.rn.f32 	%f914, %f899, %f913;
	add.f32 	%f915, %f909, %f901;
	sub.f32 	%f916, %f901, %f915;
	add.f32 	%f917, %f909, %f916;
	add.f32 	%f918, %f914, %f917;
	add.f32 	%f919, %f915, %f918;
	sub.f32 	%f920, %f915, %f919;
	add.f32 	%f921, %f918, %f920;
	mov.f32 	%f922, 0f3F317200;
	mul.rn.f32 	%f923, %f895, %f922;
	mov.f32 	%f924, 0f35BFBE8E;
	mul.rn.f32 	%f925, %f895, %f924;
	add.f32 	%f926, %f923, %f919;
	sub.f32 	%f927, %f923, %f926;
	add.f32 	%f928, %f919, %f927;
	add.f32 	%f929, %f921, %f928;
	add.f32 	%f930, %f925, %f929;
	add.f32 	%f931, %f926, %f930;
	sub.f32 	%f932, %f926, %f931;
	add.f32 	%f933, %f930, %f932;
	mul.rn.f32 	%f934, %f885, %f931;
	neg.f32 	%f935, %f934;
	fma.rn.f32 	%f936, %f885, %f931, %f935;
	fma.rn.f32 	%f937, %f885, %f933, %f936;
	mov.f32 	%f938, 0f00000000;
	fma.rn.f32 	%f939, %f938, %f931, %f937;
	add.rn.f32 	%f940, %f934, %f939;
	neg.f32 	%f941, %f940;
	add.rn.f32 	%f942, %f934, %f941;
	add.rn.f32 	%f943, %f942, %f939;
	mov.b32 	%r312, %f940;
	setp.eq.s32 	%p82, %r312, 1118925336;
	add.s32 	%r313, %r312, -1;
	mov.b32 	%f944, %r313;
	add.f32 	%f945, %f943, 0f37000000;
	selp.f32 	%f218, %f945, %f943, %p82;
	selp.f32 	%f946, %f944, %f940, %p82;
	mov.f32 	%f947, 0f3FB8AA3B;
	mul.rn.f32 	%f948, %f946, %f947;
	cvt.rzi.f32.f32 	%f949, %f948;
	abs.f32 	%f950, %f949;
	setp.gt.f32 	%p83, %f950, 0f42FC0000;
	mov.b32 	%r314, %f949;
	and.b32  	%r315, %r314, -2147483648;
	or.b32  	%r316, %r315, 1123811328;
	mov.b32 	%f951, %r316;
	selp.f32 	%f952, %f951, %f949, %p83;
	mov.f32 	%f953, 0fBF317218;
	fma.rn.f32 	%f954, %f952, %f953, %f946;
	mov.f32 	%f955, 0f3102E308;
	fma.rn.f32 	%f956, %f952, %f955, %f954;
	mul.f32 	%f957, %f956, 0f3FB8AA3B;
	add.f32 	%f958, %f952, 0f4B40007F;
	mov.b32 	%r317, %f958;
	shl.b32 	%r318, %r317, 23;
	mov.b32 	%f959, %r318;
	ex2.approx.ftz.f32 	%f960, %f957;
	mul.f32 	%f219, %f960, %f959;
	setp.eq.f32 	%p84, %f219, 0f7F800000;
	mov.f32 	%f1700, 0f7F800000;
	@%p84 bra 	$L__BB0_62;

	fma.rn.f32 	%f1700, %f219, %f218, %f219;

$L__BB0_62:
	setp.lt.f32 	%p85, %f215, 0f00000000;
	setp.eq.f32 	%p86, %f216, 0f3F800000;
	and.pred  	%p4, %p85, %p86;
	setp.eq.f32 	%p87, %f215, 0f00000000;
	@%p87 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_63;

$L__BB0_66:
	add.f32 	%f965, %f215, %f215;
	selp.f32 	%f1702, %f965, 0f00000000, %p86;
	bra.uni 	$L__BB0_67;

$L__BB0_170:
	mov.f32 	%f1574, 0f00000000;
	mov.u32 	%r453, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1574;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1574;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1574;}

	// end inline asm
	mov.u16 	%rs116, 0;
	st.global.v4.u16 	[%rd16], {%rs113, %rs114, %rs115, %rs116};

$L__BB0_171:
	ld.const.u64 	%rd65, [params+256];
	cvta.to.global.u64 	%rd66, %rd65;
	ld.const.u32 	%r439, [params+248];
	mad.lo.s32 	%r440, %r439, %r4, %r3;
	mul.wide.u32 	%rd67, %r440, 8;
	add.s64 	%rd17, %rd66, %rd67;
	setp.eq.s32 	%p205, %r453, 0;
	@%p205 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs123, %rs124, %rs125, %rs126}, [%rd17];
	// begin inline asm
	{  cvt.f32.f16 %f1575, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1576, %rs124;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1577, %rs125;}

	// end inline asm
	add.f32 	%f1578, %f1575, 0f00000000;
	add.f32 	%f1579, %f1576, 0f00000000;
	add.f32 	%f1580, %f1577, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1580;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1579;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1578;}

	// end inline asm
	mov.u16 	%rs127, 0;
	st.global.v4.u16 	[%rd17], {%rs120, %rs121, %rs122, %rs127};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1583, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1583;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1583;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1583;}

	// end inline asm
	mov.u16 	%rs131, 0;
	st.global.v4.u16 	[%rd17], {%rs128, %rs129, %rs130, %rs131};

$L__BB0_174:
	ld.const.u64 	%rd68, [params+272];
	cvta.to.global.u64 	%rd69, %rd68;
	ld.const.u32 	%r441, [params+264];
	mad.lo.s32 	%r442, %r441, %r4, %r3;
	mul.wide.u32 	%rd70, %r442, 8;
	add.s64 	%rd18, %rd69, %rd70;
	@%p205 bra 	$L__BB0_176;

	ld.global.v4.u16 	{%rs138, %rs139, %rs140, %rs141}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f1584, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1585, %rs139;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1586, %rs140;}

	// end inline asm
	add.f32 	%f1587, %f1584, 0f00000000;
	add.f32 	%f1588, %f1585, 0f00000000;
	add.f32 	%f1589, %f1586, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1589;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1588;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1587;}

	// end inline asm
	mov.u16 	%rs142, 0;
	st.global.v4.u16 	[%rd18], {%rs135, %rs136, %rs137, %rs142};
	bra.uni 	$L__BB0_177;

$L__BB0_176:
	mov.f32 	%f1592, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1592;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1592;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1592;}

	// end inline asm
	mov.u16 	%rs146, 0;
	st.global.v4.u16 	[%rd18], {%rs143, %rs144, %rs145, %rs146};

$L__BB0_177:
	ld.const.u64 	%rd71, [params+288];
	cvta.to.global.u64 	%rd72, %rd71;
	ld.const.u32 	%r443, [params+280];
	mad.lo.s32 	%r444, %r443, %r4, %r3;
	mul.wide.u32 	%rd73, %r444, 8;
	add.s64 	%rd19, %rd72, %rd73;
	@%p205 bra 	$L__BB0_179;

	ld.global.v4.u16 	{%rs153, %rs154, %rs155, %rs156}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1593, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1594, %rs154;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1595, %rs155;}

	// end inline asm
	add.f32 	%f1596, %f1593, 0f00000000;
	add.f32 	%f1597, %f1594, 0f00000000;
	add.f32 	%f1598, %f1595, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1598;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1597;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1596;}

	// end inline asm
	mov.u16 	%rs157, 0;
	st.global.v4.u16 	[%rd19], {%rs150, %rs151, %rs152, %rs157};
	bra.uni 	$L__BB0_180;

$L__BB0_179:
	mov.f32 	%f1601, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1601;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1601;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1601;}

	// end inline asm
	mov.u16 	%rs161, 0;
	st.global.v4.u16 	[%rd19], {%rs158, %rs159, %rs160, %rs161};

$L__BB0_180:
	ld.const.u64 	%rd74, [params+304];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r445, [params+296];
	mad.lo.s32 	%r446, %r445, %r4, %r3;
	mul.wide.u32 	%rd76, %r446, 8;
	add.s64 	%rd20, %rd75, %rd76;
	@%p205 bra 	$L__BB0_182;

	ld.global.v4.u16 	{%rs168, %rs169, %rs170, %rs171}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1602, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1603, %rs169;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1604, %rs170;}

	// end inline asm
	add.f32 	%f1605, %f1602, 0f00000000;
	add.f32 	%f1606, %f1603, 0f00000000;
	add.f32 	%f1607, %f1604, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1607;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1606;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1605;}

	// end inline asm
	mov.u16 	%rs172, 0;
	st.global.v4.u16 	[%rd20], {%rs165, %rs166, %rs167, %rs172};
	bra.uni 	$L__BB0_183;

$L__BB0_182:
	mov.f32 	%f1610, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1610;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1610;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1610;}

	// end inline asm
	mov.u16 	%rs176, 0;
	st.global.v4.u16 	[%rd20], {%rs173, %rs174, %rs175, %rs176};
	bra.uni 	$L__BB0_183;

$L__BB0_63:
	mov.b32 	%r319, %f1700;
	xor.b32  	%r320, %r319, -2147483648;
	mov.b32 	%f961, %r320;
	selp.f32 	%f1702, %f961, %f1700, %p4;
	setp.geu.f32 	%p88, %f215, 0f00000000;
	@%p88 bra 	$L__BB0_67;

	mov.f32 	%f962, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f963, %f962;
	setp.eq.f32 	%p89, %f963, 0f3EE8BA2E;
	@%p89 bra 	$L__BB0_67;

	mov.f32 	%f1702, 0f7FFFFFFF;

$L__BB0_67:
	add.f32 	%f966, %f217, 0f3EE8BA2E;
	mov.b32 	%r321, %f966;
	setp.lt.s32 	%p91, %r321, 2139095040;
	@%p91 bra 	$L__BB0_72;

	setp.gtu.f32 	%p92, %f217, 0f7F800000;
	@%p92 bra 	$L__BB0_71;
	bra.uni 	$L__BB0_69;

$L__BB0_71:
	add.f32 	%f1702, %f215, 0f3EE8BA2E;
	bra.uni 	$L__BB0_72;

$L__BB0_69:
	setp.neu.f32 	%p93, %f217, 0f7F800000;
	@%p93 bra 	$L__BB0_72;

	selp.f32 	%f1702, 0fFF800000, 0f7F800000, %p4;

$L__BB0_72:
	mul.f32 	%f967, %f1702, 0f437F0000;
	setp.eq.f32 	%p94, %f215, 0f3F800000;
	selp.f32 	%f968, 0f437F0000, %f967, %p94;
	cvt.rzi.u32.f32 	%r322, %f968;
	shl.b64 	%rd34, %rd8, 1;
	add.s64 	%rd35, %rd7, %rd34;
	cvt.u16.u32 	%rs18, %r322;
	mov.u16 	%rs19, 255;
	st.global.v2.u8 	[%rd35], {%rs18, %rs19};

$L__BB0_73:
	and.b32  	%r323, %r451, 1;
	setp.eq.b32 	%p95, %r323, 1;
	mov.pred 	%p96, 0;
	xor.pred  	%p97, %p95, %p96;
	not.pred 	%p98, %p97;
	@%p98 bra 	$L__BB0_147;

	mov.f32 	%f970, 0f3E666666;
	cvt.rzi.f32.f32 	%f971, %f970;
	add.f32 	%f972, %f971, %f971;
	mov.f32 	%f973, 0f3EE66666;
	sub.f32 	%f974, %f973, %f972;
	abs.f32 	%f228, %f974;
	abs.f32 	%f229, %f1668;
	setp.lt.f32 	%p99, %f229, 0f00800000;
	mul.f32 	%f975, %f229, 0f4B800000;
	selp.f32 	%f976, %f975, %f229, %p99;
	selp.f32 	%f977, 0fC3170000, 0fC2FE0000, %p99;
	mov.b32 	%r324, %f976;
	and.b32  	%r325, %r324, 8388607;
	or.b32  	%r326, %r325, 1065353216;
	mov.b32 	%f978, %r326;
	shr.u32 	%r327, %r324, 23;
	cvt.rn.f32.u32 	%f979, %r327;
	add.f32 	%f980, %f977, %f979;
	setp.gt.f32 	%p100, %f978, 0f3FB504F3;
	mul.f32 	%f981, %f978, 0f3F000000;
	add.f32 	%f982, %f980, 0f3F800000;
	selp.f32 	%f983, %f982, %f980, %p100;
	selp.f32 	%f984, %f981, %f978, %p100;
	add.f32 	%f985, %f984, 0fBF800000;
	add.f32 	%f986, %f984, 0f3F800000;
	rcp.approx.ftz.f32 	%f987, %f986;
	add.f32 	%f988, %f985, %f985;
	mul.f32 	%f989, %f988, %f987;
	mul.f32 	%f990, %f989, %f989;
	mov.f32 	%f991, 0f3C4CAF63;
	mov.f32 	%f992, 0f3B18F0FE;
	fma.rn.f32 	%f993, %f992, %f990, %f991;
	mov.f32 	%f994, 0f3DAAAABD;
	fma.rn.f32 	%f995, %f993, %f990, %f994;
	mul.rn.f32 	%f996, %f995, %f990;
	mul.rn.f32 	%f997, %f996, %f989;
	sub.f32 	%f998, %f985, %f989;
	add.f32 	%f999, %f998, %f998;
	neg.f32 	%f1000, %f989;
	fma.rn.f32 	%f1001, %f1000, %f985, %f999;
	mul.rn.f32 	%f1002, %f987, %f1001;
	add.f32 	%f1003, %f997, %f989;
	sub.f32 	%f1004, %f989, %f1003;
	add.f32 	%f1005, %f997, %f1004;
	add.f32 	%f1006, %f1002, %f1005;
	add.f32 	%f1007, %f1003, %f1006;
	sub.f32 	%f1008, %f1003, %f1007;
	add.f32 	%f1009, %f1006, %f1008;
	mov.f32 	%f1010, 0f3F317200;
	mul.rn.f32 	%f1011, %f983, %f1010;
	mov.f32 	%f1012, 0f35BFBE8E;
	mul.rn.f32 	%f1013, %f983, %f1012;
	add.f32 	%f1014, %f1011, %f1007;
	sub.f32 	%f1015, %f1011, %f1014;
	add.f32 	%f1016, %f1007, %f1015;
	add.f32 	%f1017, %f1009, %f1016;
	add.f32 	%f1018, %f1013, %f1017;
	add.f32 	%f1019, %f1014, %f1018;
	sub.f32 	%f1020, %f1014, %f1019;
	add.f32 	%f1021, %f1018, %f1020;
	mul.rn.f32 	%f1022, %f973, %f1019;
	neg.f32 	%f1023, %f1022;
	fma.rn.f32 	%f1024, %f973, %f1019, %f1023;
	fma.rn.f32 	%f1025, %f973, %f1021, %f1024;
	mov.f32 	%f1026, 0f00000000;
	fma.rn.f32 	%f1027, %f1026, %f1019, %f1025;
	add.rn.f32 	%f1028, %f1022, %f1027;
	neg.f32 	%f1029, %f1028;
	add.rn.f32 	%f1030, %f1022, %f1029;
	add.rn.f32 	%f1031, %f1030, %f1027;
	mov.b32 	%r328, %f1028;
	setp.eq.s32 	%p101, %r328, 1118925336;
	add.s32 	%r329, %r328, -1;
	mov.b32 	%f1032, %r329;
	add.f32 	%f1033, %f1031, 0f37000000;
	selp.f32 	%f230, %f1033, %f1031, %p101;
	selp.f32 	%f1034, %f1032, %f1028, %p101;
	mov.f32 	%f1035, 0f3FB8AA3B;
	mul.rn.f32 	%f1036, %f1034, %f1035;
	cvt.rzi.f32.f32 	%f1037, %f1036;
	abs.f32 	%f1038, %f1037;
	setp.gt.f32 	%p102, %f1038, 0f42FC0000;
	mov.b32 	%r330, %f1037;
	and.b32  	%r331, %r330, -2147483648;
	or.b32  	%r332, %r331, 1123811328;
	mov.b32 	%f1039, %r332;
	selp.f32 	%f1040, %f1039, %f1037, %p102;
	mov.f32 	%f1041, 0fBF317218;
	fma.rn.f32 	%f1042, %f1040, %f1041, %f1034;
	mov.f32 	%f1043, 0f3102E308;
	fma.rn.f32 	%f1044, %f1040, %f1043, %f1042;
	mul.f32 	%f1045, %f1044, 0f3FB8AA3B;
	add.f32 	%f1046, %f1040, 0f4B40007F;
	mov.b32 	%r333, %f1046;
	shl.b32 	%r334, %r333, 23;
	mov.b32 	%f1047, %r334;
	ex2.approx.ftz.f32 	%f1048, %f1045;
	mul.f32 	%f231, %f1048, %f1047;
	setp.eq.f32 	%p103, %f231, 0f7F800000;
	mov.f32 	%f1703, 0f7F800000;
	@%p103 bra 	$L__BB0_76;

	fma.rn.f32 	%f1703, %f231, %f230, %f231;

$L__BB0_76:
	setp.lt.f32 	%p104, %f1668, 0f00000000;
	setp.eq.f32 	%p105, %f228, 0f3F800000;
	and.pred  	%p5, %p104, %p105;
	setp.eq.f32 	%p106, %f1668, 0f00000000;
	@%p106 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_77;

$L__BB0_80:
	add.f32 	%f1053, %f1668, %f1668;
	selp.f32 	%f1705, %f1053, 0f00000000, %p105;
	bra.uni 	$L__BB0_81;

$L__BB0_77:
	mov.b32 	%r335, %f1703;
	xor.b32  	%r336, %r335, -2147483648;
	mov.b32 	%f1049, %r336;
	selp.f32 	%f1705, %f1049, %f1703, %p5;
	setp.geu.f32 	%p107, %f1668, 0f00000000;
	@%p107 bra 	$L__BB0_81;

	mov.f32 	%f1050, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1051, %f1050;
	setp.eq.f32 	%p108, %f1051, 0f3EE66666;
	@%p108 bra 	$L__BB0_81;

	mov.f32 	%f1705, 0f7FFFFFFF;

$L__BB0_81:
	add.f32 	%f1054, %f229, 0f3EE66666;
	mov.b32 	%r337, %f1054;
	setp.lt.s32 	%p110, %r337, 2139095040;
	@%p110 bra 	$L__BB0_86;

	setp.gtu.f32 	%p111, %f229, 0f7F800000;
	@%p111 bra 	$L__BB0_85;
	bra.uni 	$L__BB0_83;

$L__BB0_85:
	add.f32 	%f1705, %f1668, 0f3EE66666;
	bra.uni 	$L__BB0_86;

$L__BB0_83:
	setp.neu.f32 	%p112, %f229, 0f7F800000;
	@%p112 bra 	$L__BB0_86;

	selp.f32 	%f1705, 0fFF800000, 0f7F800000, %p5;

$L__BB0_86:
	setp.eq.f32 	%p113, %f1668, 0f3F800000;
	selp.f32 	%f240, 0f3F800000, %f1705, %p113;
	abs.f32 	%f241, %f1669;
	setp.lt.f32 	%p114, %f241, 0f00800000;
	mul.f32 	%f1056, %f241, 0f4B800000;
	selp.f32 	%f1057, %f1056, %f241, %p114;
	selp.f32 	%f1058, 0fC3170000, 0fC2FE0000, %p114;
	mov.b32 	%r338, %f1057;
	and.b32  	%r339, %r338, 8388607;
	or.b32  	%r340, %r339, 1065353216;
	mov.b32 	%f1059, %r340;
	shr.u32 	%r341, %r338, 23;
	cvt.rn.f32.u32 	%f1060, %r341;
	add.f32 	%f1061, %f1058, %f1060;
	setp.gt.f32 	%p115, %f1059, 0f3FB504F3;
	mul.f32 	%f1062, %f1059, 0f3F000000;
	add.f32 	%f1063, %f1061, 0f3F800000;
	selp.f32 	%f1064, %f1063, %f1061, %p115;
	selp.f32 	%f1065, %f1062, %f1059, %p115;
	add.f32 	%f1066, %f1065, 0fBF800000;
	add.f32 	%f1067, %f1065, 0f3F800000;
	rcp.approx.ftz.f32 	%f1068, %f1067;
	add.f32 	%f1069, %f1066, %f1066;
	mul.f32 	%f1070, %f1069, %f1068;
	mul.f32 	%f1071, %f1070, %f1070;
	mov.f32 	%f1072, 0f3C4CAF63;
	mov.f32 	%f1073, 0f3B18F0FE;
	fma.rn.f32 	%f1074, %f1073, %f1071, %f1072;
	mov.f32 	%f1075, 0f3DAAAABD;
	fma.rn.f32 	%f1076, %f1074, %f1071, %f1075;
	mul.rn.f32 	%f1077, %f1076, %f1071;
	mul.rn.f32 	%f1078, %f1077, %f1070;
	sub.f32 	%f1079, %f1066, %f1070;
	add.f32 	%f1080, %f1079, %f1079;
	neg.f32 	%f1081, %f1070;
	fma.rn.f32 	%f1082, %f1081, %f1066, %f1080;
	mul.rn.f32 	%f1083, %f1068, %f1082;
	add.f32 	%f1084, %f1078, %f1070;
	sub.f32 	%f1085, %f1070, %f1084;
	add.f32 	%f1086, %f1078, %f1085;
	add.f32 	%f1087, %f1083, %f1086;
	add.f32 	%f1088, %f1084, %f1087;
	sub.f32 	%f1089, %f1084, %f1088;
	add.f32 	%f1090, %f1087, %f1089;
	mov.f32 	%f1091, 0f3F317200;
	mul.rn.f32 	%f1092, %f1064, %f1091;
	mov.f32 	%f1093, 0f35BFBE8E;
	mul.rn.f32 	%f1094, %f1064, %f1093;
	add.f32 	%f1095, %f1092, %f1088;
	sub.f32 	%f1096, %f1092, %f1095;
	add.f32 	%f1097, %f1088, %f1096;
	add.f32 	%f1098, %f1090, %f1097;
	add.f32 	%f1099, %f1094, %f1098;
	add.f32 	%f1100, %f1095, %f1099;
	sub.f32 	%f1101, %f1095, %f1100;
	add.f32 	%f1102, %f1099, %f1101;
	mov.f32 	%f1103, 0f3EE66666;
	mul.rn.f32 	%f1104, %f1103, %f1100;
	neg.f32 	%f1105, %f1104;
	fma.rn.f32 	%f1106, %f1103, %f1100, %f1105;
	fma.rn.f32 	%f1107, %f1103, %f1102, %f1106;
	mov.f32 	%f1108, 0f00000000;
	fma.rn.f32 	%f1109, %f1108, %f1100, %f1107;
	add.rn.f32 	%f1110, %f1104, %f1109;
	neg.f32 	%f1111, %f1110;
	add.rn.f32 	%f1112, %f1104, %f1111;
	add.rn.f32 	%f1113, %f1112, %f1109;
	mov.b32 	%r342, %f1110;
	setp.eq.s32 	%p116, %r342, 1118925336;
	add.s32 	%r343, %r342, -1;
	mov.b32 	%f1114, %r343;
	add.f32 	%f1115, %f1113, 0f37000000;
	selp.f32 	%f242, %f1115, %f1113, %p116;
	selp.f32 	%f1116, %f1114, %f1110, %p116;
	mov.f32 	%f1117, 0f3FB8AA3B;
	mul.rn.f32 	%f1118, %f1116, %f1117;
	cvt.rzi.f32.f32 	%f1119, %f1118;
	abs.f32 	%f1120, %f1119;
	setp.gt.f32 	%p117, %f1120, 0f42FC0000;
	mov.b32 	%r344, %f1119;
	and.b32  	%r345, %r344, -2147483648;
	or.b32  	%r346, %r345, 1123811328;
	mov.b32 	%f1121, %r346;
	selp.f32 	%f1122, %f1121, %f1119, %p117;
	mov.f32 	%f1123, 0fBF317218;
	fma.rn.f32 	%f1124, %f1122, %f1123, %f1116;
	mov.f32 	%f1125, 0f3102E308;
	fma.rn.f32 	%f1126, %f1122, %f1125, %f1124;
	mul.f32 	%f1127, %f1126, 0f3FB8AA3B;
	add.f32 	%f1128, %f1122, 0f4B40007F;
	mov.b32 	%r347, %f1128;
	shl.b32 	%r348, %r347, 23;
	mov.b32 	%f1129, %r348;
	ex2.approx.ftz.f32 	%f1130, %f1127;
	mul.f32 	%f243, %f1130, %f1129;
	setp.eq.f32 	%p118, %f243, 0f7F800000;
	mov.f32 	%f1706, 0f7F800000;
	@%p118 bra 	$L__BB0_88;

	fma.rn.f32 	%f1706, %f243, %f242, %f243;

$L__BB0_88:
	setp.lt.f32 	%p119, %f1669, 0f00000000;
	and.pred  	%p6, %p119, %p105;
	setp.eq.f32 	%p121, %f1669, 0f00000000;
	@%p121 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_89;

$L__BB0_92:
	add.f32 	%f1135, %f1669, %f1669;
	selp.f32 	%f1708, %f1135, 0f00000000, %p105;
	bra.uni 	$L__BB0_93;

$L__BB0_89:
	mov.b32 	%r349, %f1706;
	xor.b32  	%r350, %r349, -2147483648;
	mov.b32 	%f1131, %r350;
	selp.f32 	%f1708, %f1131, %f1706, %p6;
	setp.geu.f32 	%p122, %f1669, 0f00000000;
	@%p122 bra 	$L__BB0_93;

	mov.f32 	%f1132, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1133, %f1132;
	setp.eq.f32 	%p123, %f1133, 0f3EE66666;
	@%p123 bra 	$L__BB0_93;

	mov.f32 	%f1708, 0f7FFFFFFF;

$L__BB0_93:
	add.f32 	%f1136, %f241, 0f3EE66666;
	mov.b32 	%r351, %f1136;
	setp.lt.s32 	%p125, %r351, 2139095040;
	@%p125 bra 	$L__BB0_98;

	setp.gtu.f32 	%p126, %f241, 0f7F800000;
	@%p126 bra 	$L__BB0_97;
	bra.uni 	$L__BB0_95;

$L__BB0_97:
	add.f32 	%f1708, %f1669, 0f3EE66666;
	bra.uni 	$L__BB0_98;

$L__BB0_95:
	setp.neu.f32 	%p127, %f241, 0f7F800000;
	@%p127 bra 	$L__BB0_98;

	selp.f32 	%f1708, 0fFF800000, 0f7F800000, %p6;

$L__BB0_98:
	setp.eq.f32 	%p128, %f1669, 0f3F800000;
	selp.f32 	%f252, 0f3F800000, %f1708, %p128;
	abs.f32 	%f253, %f1670;
	setp.lt.f32 	%p129, %f253, 0f00800000;
	mul.f32 	%f1138, %f253, 0f4B800000;
	selp.f32 	%f1139, %f1138, %f253, %p129;
	selp.f32 	%f1140, 0fC3170000, 0fC2FE0000, %p129;
	mov.b32 	%r352, %f1139;
	and.b32  	%r353, %r352, 8388607;
	or.b32  	%r354, %r353, 1065353216;
	mov.b32 	%f1141, %r354;
	shr.u32 	%r355, %r352, 23;
	cvt.rn.f32.u32 	%f1142, %r355;
	add.f32 	%f1143, %f1140, %f1142;
	setp.gt.f32 	%p130, %f1141, 0f3FB504F3;
	mul.f32 	%f1144, %f1141, 0f3F000000;
	add.f32 	%f1145, %f1143, 0f3F800000;
	selp.f32 	%f1146, %f1145, %f1143, %p130;
	selp.f32 	%f1147, %f1144, %f1141, %p130;
	add.f32 	%f1148, %f1147, 0fBF800000;
	add.f32 	%f1149, %f1147, 0f3F800000;
	rcp.approx.ftz.f32 	%f1150, %f1149;
	add.f32 	%f1151, %f1148, %f1148;
	mul.f32 	%f1152, %f1151, %f1150;
	mul.f32 	%f1153, %f1152, %f1152;
	mov.f32 	%f1154, 0f3C4CAF63;
	mov.f32 	%f1155, 0f3B18F0FE;
	fma.rn.f32 	%f1156, %f1155, %f1153, %f1154;
	mov.f32 	%f1157, 0f3DAAAABD;
	fma.rn.f32 	%f1158, %f1156, %f1153, %f1157;
	mul.rn.f32 	%f1159, %f1158, %f1153;
	mul.rn.f32 	%f1160, %f1159, %f1152;
	sub.f32 	%f1161, %f1148, %f1152;
	add.f32 	%f1162, %f1161, %f1161;
	neg.f32 	%f1163, %f1152;
	fma.rn.f32 	%f1164, %f1163, %f1148, %f1162;
	mul.rn.f32 	%f1165, %f1150, %f1164;
	add.f32 	%f1166, %f1160, %f1152;
	sub.f32 	%f1167, %f1152, %f1166;
	add.f32 	%f1168, %f1160, %f1167;
	add.f32 	%f1169, %f1165, %f1168;
	add.f32 	%f1170, %f1166, %f1169;
	sub.f32 	%f1171, %f1166, %f1170;
	add.f32 	%f1172, %f1169, %f1171;
	mov.f32 	%f1173, 0f3F317200;
	mul.rn.f32 	%f1174, %f1146, %f1173;
	mov.f32 	%f1175, 0f35BFBE8E;
	mul.rn.f32 	%f1176, %f1146, %f1175;
	add.f32 	%f1177, %f1174, %f1170;
	sub.f32 	%f1178, %f1174, %f1177;
	add.f32 	%f1179, %f1170, %f1178;
	add.f32 	%f1180, %f1172, %f1179;
	add.f32 	%f1181, %f1176, %f1180;
	add.f32 	%f1182, %f1177, %f1181;
	sub.f32 	%f1183, %f1177, %f1182;
	add.f32 	%f1184, %f1181, %f1183;
	mov.f32 	%f1185, 0f3EE66666;
	mul.rn.f32 	%f1186, %f1185, %f1182;
	neg.f32 	%f1187, %f1186;
	fma.rn.f32 	%f1188, %f1185, %f1182, %f1187;
	fma.rn.f32 	%f1189, %f1185, %f1184, %f1188;
	mov.f32 	%f1190, 0f00000000;
	fma.rn.f32 	%f1191, %f1190, %f1182, %f1189;
	add.rn.f32 	%f1192, %f1186, %f1191;
	neg.f32 	%f1193, %f1192;
	add.rn.f32 	%f1194, %f1186, %f1193;
	add.rn.f32 	%f1195, %f1194, %f1191;
	mov.b32 	%r356, %f1192;
	setp.eq.s32 	%p131, %r356, 1118925336;
	add.s32 	%r357, %r356, -1;
	mov.b32 	%f1196, %r357;
	add.f32 	%f1197, %f1195, 0f37000000;
	selp.f32 	%f254, %f1197, %f1195, %p131;
	selp.f32 	%f1198, %f1196, %f1192, %p131;
	mov.f32 	%f1199, 0f3FB8AA3B;
	mul.rn.f32 	%f1200, %f1198, %f1199;
	cvt.rzi.f32.f32 	%f1201, %f1200;
	abs.f32 	%f1202, %f1201;
	setp.gt.f32 	%p132, %f1202, 0f42FC0000;
	mov.b32 	%r358, %f1201;
	and.b32  	%r359, %r358, -2147483648;
	or.b32  	%r360, %r359, 1123811328;
	mov.b32 	%f1203, %r360;
	selp.f32 	%f1204, %f1203, %f1201, %p132;
	mov.f32 	%f1205, 0fBF317218;
	fma.rn.f32 	%f1206, %f1204, %f1205, %f1198;
	mov.f32 	%f1207, 0f3102E308;
	fma.rn.f32 	%f1208, %f1204, %f1207, %f1206;
	mul.f32 	%f1209, %f1208, 0f3FB8AA3B;
	add.f32 	%f1210, %f1204, 0f4B40007F;
	mov.b32 	%r361, %f1210;
	shl.b32 	%r362, %r361, 23;
	mov.b32 	%f1211, %r362;
	ex2.approx.ftz.f32 	%f1212, %f1209;
	mul.f32 	%f255, %f1212, %f1211;
	setp.eq.f32 	%p133, %f255, 0f7F800000;
	mov.f32 	%f1709, 0f7F800000;
	@%p133 bra 	$L__BB0_100;

	fma.rn.f32 	%f1709, %f255, %f254, %f255;

$L__BB0_100:
	setp.lt.f32 	%p134, %f1670, 0f00000000;
	and.pred  	%p7, %p134, %p105;
	setp.eq.f32 	%p136, %f1670, 0f00000000;
	@%p136 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_101;

$L__BB0_104:
	add.f32 	%f1217, %f1670, %f1670;
	selp.f32 	%f1711, %f1217, 0f00000000, %p105;
	bra.uni 	$L__BB0_105;

$L__BB0_101:
	mov.b32 	%r363, %f1709;
	xor.b32  	%r364, %r363, -2147483648;
	mov.b32 	%f1213, %r364;
	selp.f32 	%f1711, %f1213, %f1709, %p7;
	setp.geu.f32 	%p137, %f1670, 0f00000000;
	@%p137 bra 	$L__BB0_105;

	mov.f32 	%f1214, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1215, %f1214;
	setp.eq.f32 	%p138, %f1215, 0f3EE66666;
	@%p138 bra 	$L__BB0_105;

	mov.f32 	%f1711, 0f7FFFFFFF;

$L__BB0_105:
	add.f32 	%f1218, %f253, 0f3EE66666;
	mov.b32 	%r365, %f1218;
	setp.lt.s32 	%p140, %r365, 2139095040;
	@%p140 bra 	$L__BB0_110;

	setp.gtu.f32 	%p141, %f253, 0f7F800000;
	@%p141 bra 	$L__BB0_109;
	bra.uni 	$L__BB0_107;

$L__BB0_109:
	add.f32 	%f1711, %f1670, 0f3EE66666;
	bra.uni 	$L__BB0_110;

$L__BB0_107:
	setp.neu.f32 	%p142, %f253, 0f7F800000;
	@%p142 bra 	$L__BB0_110;

	selp.f32 	%f1711, 0fFF800000, 0f7F800000, %p7;

$L__BB0_110:
	setp.eq.f32 	%p143, %f1670, 0f3F800000;
	mov.f32 	%f1220, 0f3F800000;
	selp.f32 	%f1221, 0f3F800000, %f1711, %p143;
	ld.const.u64 	%rd36, [params+144];
	cvta.to.global.u64 	%rd9, %rd36;
	ld.const.u32 	%r366, [params+136];
	mad.lo.s32 	%r367, %r366, %r4, %r3;
	cvt.u64.u32 	%rd10, %r367;
	min.f32 	%f1222, %f240, %f1220;
	mov.f32 	%f1223, 0f00000000;
	max.f32 	%f264, %f1223, %f1222;
	min.f32 	%f1224, %f252, %f1220;
	max.f32 	%f265, %f1223, %f1224;
	min.f32 	%f1225, %f1221, %f1220;
	max.f32 	%f266, %f1223, %f1225;
	mov.f32 	%f1226, 0f3E555555;
	cvt.rzi.f32.f32 	%f1227, %f1226;
	add.f32 	%f1228, %f1227, %f1227;
	mov.f32 	%f1229, 0f3ED55555;
	sub.f32 	%f1230, %f1229, %f1228;
	abs.f32 	%f267, %f1230;
	abs.f32 	%f268, %f264;
	setp.lt.f32 	%p144, %f268, 0f00800000;
	mul.f32 	%f1231, %f268, 0f4B800000;
	selp.f32 	%f1232, %f1231, %f268, %p144;
	selp.f32 	%f1233, 0fC3170000, 0fC2FE0000, %p144;
	mov.b32 	%r368, %f1232;
	and.b32  	%r369, %r368, 8388607;
	or.b32  	%r370, %r369, 1065353216;
	mov.b32 	%f1234, %r370;
	shr.u32 	%r371, %r368, 23;
	cvt.rn.f32.u32 	%f1235, %r371;
	add.f32 	%f1236, %f1233, %f1235;
	setp.gt.f32 	%p145, %f1234, 0f3FB504F3;
	mul.f32 	%f1237, %f1234, 0f3F000000;
	add.f32 	%f1238, %f1236, 0f3F800000;
	selp.f32 	%f1239, %f1238, %f1236, %p145;
	selp.f32 	%f1240, %f1237, %f1234, %p145;
	add.f32 	%f1241, %f1240, 0fBF800000;
	add.f32 	%f1242, %f1240, 0f3F800000;
	rcp.approx.ftz.f32 	%f1243, %f1242;
	add.f32 	%f1244, %f1241, %f1241;
	mul.f32 	%f1245, %f1244, %f1243;
	mul.f32 	%f1246, %f1245, %f1245;
	mov.f32 	%f1247, 0f3C4CAF63;
	mov.f32 	%f1248, 0f3B18F0FE;
	fma.rn.f32 	%f1249, %f1248, %f1246, %f1247;
	mov.f32 	%f1250, 0f3DAAAABD;
	fma.rn.f32 	%f1251, %f1249, %f1246, %f1250;
	mul.rn.f32 	%f1252, %f1251, %f1246;
	mul.rn.f32 	%f1253, %f1252, %f1245;
	sub.f32 	%f1254, %f1241, %f1245;
	add.f32 	%f1255, %f1254, %f1254;
	neg.f32 	%f1256, %f1245;
	fma.rn.f32 	%f1257, %f1256, %f1241, %f1255;
	mul.rn.f32 	%f1258, %f1243, %f1257;
	add.f32 	%f1259, %f1253, %f1245;
	sub.f32 	%f1260, %f1245, %f1259;
	add.f32 	%f1261, %f1253, %f1260;
	add.f32 	%f1262, %f1258, %f1261;
	add.f32 	%f1263, %f1259, %f1262;
	sub.f32 	%f1264, %f1259, %f1263;
	add.f32 	%f1265, %f1262, %f1264;
	mov.f32 	%f1266, 0f3F317200;
	mul.rn.f32 	%f1267, %f1239, %f1266;
	mov.f32 	%f1268, 0f35BFBE8E;
	mul.rn.f32 	%f1269, %f1239, %f1268;
	add.f32 	%f1270, %f1267, %f1263;
	sub.f32 	%f1271, %f1267, %f1270;
	add.f32 	%f1272, %f1263, %f1271;
	add.f32 	%f1273, %f1265, %f1272;
	add.f32 	%f1274, %f1269, %f1273;
	add.f32 	%f1275, %f1270, %f1274;
	sub.f32 	%f1276, %f1270, %f1275;
	add.f32 	%f1277, %f1274, %f1276;
	mul.rn.f32 	%f1278, %f1229, %f1275;
	neg.f32 	%f1279, %f1278;
	fma.rn.f32 	%f1280, %f1229, %f1275, %f1279;
	fma.rn.f32 	%f1281, %f1229, %f1277, %f1280;
	fma.rn.f32 	%f1282, %f1223, %f1275, %f1281;
	add.rn.f32 	%f1283, %f1278, %f1282;
	neg.f32 	%f1284, %f1283;
	add.rn.f32 	%f1285, %f1278, %f1284;
	add.rn.f32 	%f1286, %f1285, %f1282;
	mov.b32 	%r372, %f1283;
	setp.eq.s32 	%p146, %r372, 1118925336;
	add.s32 	%r373, %r372, -1;
	mov.b32 	%f1287, %r373;
	add.f32 	%f1288, %f1286, 0f37000000;
	selp.f32 	%f269, %f1288, %f1286, %p146;
	selp.f32 	%f1289, %f1287, %f1283, %p146;
	mov.f32 	%f1290, 0f3FB8AA3B;
	mul.rn.f32 	%f1291, %f1289, %f1290;
	cvt.rzi.f32.f32 	%f1292, %f1291;
	abs.f32 	%f1293, %f1292;
	setp.gt.f32 	%p147, %f1293, 0f42FC0000;
	mov.b32 	%r374, %f1292;
	and.b32  	%r375, %r374, -2147483648;
	or.b32  	%r376, %r375, 1123811328;
	mov.b32 	%f1294, %r376;
	selp.f32 	%f1295, %f1294, %f1292, %p147;
	mov.f32 	%f1296, 0fBF317218;
	fma.rn.f32 	%f1297, %f1295, %f1296, %f1289;
	mov.f32 	%f1298, 0f3102E308;
	fma.rn.f32 	%f1299, %f1295, %f1298, %f1297;
	mul.f32 	%f1300, %f1299, 0f3FB8AA3B;
	add.f32 	%f1301, %f1295, 0f4B40007F;
	mov.b32 	%r377, %f1301;
	shl.b32 	%r378, %r377, 23;
	mov.b32 	%f1302, %r378;
	ex2.approx.ftz.f32 	%f1303, %f1300;
	mul.f32 	%f270, %f1303, %f1302;
	setp.eq.f32 	%p148, %f270, 0f7F800000;
	mov.f32 	%f1712, 0f7F800000;
	@%p148 bra 	$L__BB0_112;

	fma.rn.f32 	%f1712, %f270, %f269, %f270;

$L__BB0_112:
	setp.lt.f32 	%p149, %f264, 0f00000000;
	setp.eq.f32 	%p150, %f267, 0f3F800000;
	and.pred  	%p8, %p149, %p150;
	setp.eq.f32 	%p151, %f264, 0f00000000;
	@%p151 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_113;

$L__BB0_116:
	add.f32 	%f1308, %f264, %f264;
	selp.f32 	%f1714, %f1308, 0f00000000, %p150;
	bra.uni 	$L__BB0_117;

$L__BB0_113:
	mov.b32 	%r379, %f1712;
	xor.b32  	%r380, %r379, -2147483648;
	mov.b32 	%f1304, %r380;
	selp.f32 	%f1714, %f1304, %f1712, %p8;
	setp.geu.f32 	%p152, %f264, 0f00000000;
	@%p152 bra 	$L__BB0_117;

	mov.f32 	%f1305, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1306, %f1305;
	setp.eq.f32 	%p153, %f1306, 0f3ED55555;
	@%p153 bra 	$L__BB0_117;

	mov.f32 	%f1714, 0f7FFFFFFF;

$L__BB0_117:
	add.f32 	%f1309, %f268, 0f3ED55555;
	mov.b32 	%r381, %f1309;
	setp.lt.s32 	%p155, %r381, 2139095040;
	@%p155 bra 	$L__BB0_122;

	setp.gtu.f32 	%p156, %f268, 0f7F800000;
	@%p156 bra 	$L__BB0_121;
	bra.uni 	$L__BB0_119;

$L__BB0_121:
	add.f32 	%f1714, %f264, 0f3ED55555;
	bra.uni 	$L__BB0_122;

$L__BB0_119:
	setp.neu.f32 	%p157, %f268, 0f7F800000;
	@%p157 bra 	$L__BB0_122;

	selp.f32 	%f1714, 0fFF800000, 0f7F800000, %p8;

$L__BB0_122:
	abs.f32 	%f279, %f265;
	setp.lt.f32 	%p158, %f279, 0f00800000;
	mul.f32 	%f1311, %f279, 0f4B800000;
	selp.f32 	%f1312, %f1311, %f279, %p158;
	selp.f32 	%f1313, 0fC3170000, 0fC2FE0000, %p158;
	mov.b32 	%r382, %f1312;
	and.b32  	%r383, %r382, 8388607;
	or.b32  	%r384, %r383, 1065353216;
	mov.b32 	%f1314, %r384;
	shr.u32 	%r385, %r382, 23;
	cvt.rn.f32.u32 	%f1315, %r385;
	add.f32 	%f1316, %f1313, %f1315;
	setp.gt.f32 	%p159, %f1314, 0f3FB504F3;
	mul.f32 	%f1317, %f1314, 0f3F000000;
	add.f32 	%f1318, %f1316, 0f3F800000;
	selp.f32 	%f1319, %f1318, %f1316, %p159;
	selp.f32 	%f1320, %f1317, %f1314, %p159;
	add.f32 	%f1321, %f1320, 0fBF800000;
	add.f32 	%f1322, %f1320, 0f3F800000;
	rcp.approx.ftz.f32 	%f1323, %f1322;
	add.f32 	%f1324, %f1321, %f1321;
	mul.f32 	%f1325, %f1324, %f1323;
	mul.f32 	%f1326, %f1325, %f1325;
	mov.f32 	%f1327, 0f3C4CAF63;
	mov.f32 	%f1328, 0f3B18F0FE;
	fma.rn.f32 	%f1329, %f1328, %f1326, %f1327;
	mov.f32 	%f1330, 0f3DAAAABD;
	fma.rn.f32 	%f1331, %f1329, %f1326, %f1330;
	mul.rn.f32 	%f1332, %f1331, %f1326;
	mul.rn.f32 	%f1333, %f1332, %f1325;
	sub.f32 	%f1334, %f1321, %f1325;
	add.f32 	%f1335, %f1334, %f1334;
	neg.f32 	%f1336, %f1325;
	fma.rn.f32 	%f1337, %f1336, %f1321, %f1335;
	mul.rn.f32 	%f1338, %f1323, %f1337;
	add.f32 	%f1339, %f1333, %f1325;
	sub.f32 	%f1340, %f1325, %f1339;
	add.f32 	%f1341, %f1333, %f1340;
	add.f32 	%f1342, %f1338, %f1341;
	add.f32 	%f1343, %f1339, %f1342;
	sub.f32 	%f1344, %f1339, %f1343;
	add.f32 	%f1345, %f1342, %f1344;
	mov.f32 	%f1346, 0f3F317200;
	mul.rn.f32 	%f1347, %f1319, %f1346;
	mov.f32 	%f1348, 0f35BFBE8E;
	mul.rn.f32 	%f1349, %f1319, %f1348;
	add.f32 	%f1350, %f1347, %f1343;
	sub.f32 	%f1351, %f1347, %f1350;
	add.f32 	%f1352, %f1343, %f1351;
	add.f32 	%f1353, %f1345, %f1352;
	add.f32 	%f1354, %f1349, %f1353;
	add.f32 	%f1355, %f1350, %f1354;
	sub.f32 	%f1356, %f1350, %f1355;
	add.f32 	%f1357, %f1354, %f1356;
	mov.f32 	%f1358, 0f3ED55555;
	mul.rn.f32 	%f1359, %f1358, %f1355;
	neg.f32 	%f1360, %f1359;
	fma.rn.f32 	%f1361, %f1358, %f1355, %f1360;
	fma.rn.f32 	%f1362, %f1358, %f1357, %f1361;
	mov.f32 	%f1363, 0f00000000;
	fma.rn.f32 	%f1364, %f1363, %f1355, %f1362;
	add.rn.f32 	%f1365, %f1359, %f1364;
	neg.f32 	%f1366, %f1365;
	add.rn.f32 	%f1367, %f1359, %f1366;
	add.rn.f32 	%f1368, %f1367, %f1364;
	mov.b32 	%r386, %f1365;
	setp.eq.s32 	%p160, %r386, 1118925336;
	add.s32 	%r387, %r386, -1;
	mov.b32 	%f1369, %r387;
	add.f32 	%f1370, %f1368, 0f37000000;
	selp.f32 	%f280, %f1370, %f1368, %p160;
	selp.f32 	%f1371, %f1369, %f1365, %p160;
	mov.f32 	%f1372, 0f3FB8AA3B;
	mul.rn.f32 	%f1373, %f1371, %f1372;
	cvt.rzi.f32.f32 	%f1374, %f1373;
	abs.f32 	%f1375, %f1374;
	setp.gt.f32 	%p161, %f1375, 0f42FC0000;
	mov.b32 	%r388, %f1374;
	and.b32  	%r389, %r388, -2147483648;
	or.b32  	%r390, %r389, 1123811328;
	mov.b32 	%f1376, %r390;
	selp.f32 	%f1377, %f1376, %f1374, %p161;
	mov.f32 	%f1378, 0fBF317218;
	fma.rn.f32 	%f1379, %f1377, %f1378, %f1371;
	mov.f32 	%f1380, 0f3102E308;
	fma.rn.f32 	%f1381, %f1377, %f1380, %f1379;
	mul.f32 	%f1382, %f1381, 0f3FB8AA3B;
	add.f32 	%f1383, %f1377, 0f4B40007F;
	mov.b32 	%r391, %f1383;
	shl.b32 	%r392, %r391, 23;
	mov.b32 	%f1384, %r392;
	ex2.approx.ftz.f32 	%f1385, %f1382;
	mul.f32 	%f281, %f1385, %f1384;
	setp.eq.f32 	%p162, %f281, 0f7F800000;
	mov.f32 	%f1715, 0f7F800000;
	@%p162 bra 	$L__BB0_124;

	fma.rn.f32 	%f1715, %f281, %f280, %f281;

$L__BB0_124:
	setp.lt.f32 	%p163, %f265, 0f00000000;
	and.pred  	%p9, %p163, %p150;
	setp.eq.f32 	%p165, %f265, 0f00000000;
	@%p165 bra 	$L__BB0_128;
	bra.uni 	$L__BB0_125;

$L__BB0_128:
	add.f32 	%f1390, %f265, %f265;
	selp.f32 	%f1717, %f1390, 0f00000000, %p150;
	bra.uni 	$L__BB0_129;

$L__BB0_125:
	mov.b32 	%r393, %f1715;
	xor.b32  	%r394, %r393, -2147483648;
	mov.b32 	%f1386, %r394;
	selp.f32 	%f1717, %f1386, %f1715, %p9;
	setp.geu.f32 	%p166, %f265, 0f00000000;
	@%p166 bra 	$L__BB0_129;

	mov.f32 	%f1387, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1388, %f1387;
	setp.eq.f32 	%p167, %f1388, 0f3ED55555;
	@%p167 bra 	$L__BB0_129;

	mov.f32 	%f1717, 0f7FFFFFFF;

$L__BB0_129:
	add.f32 	%f1391, %f279, 0f3ED55555;
	mov.b32 	%r395, %f1391;
	setp.lt.s32 	%p169, %r395, 2139095040;
	@%p169 bra 	$L__BB0_134;

	setp.gtu.f32 	%p170, %f279, 0f7F800000;
	@%p170 bra 	$L__BB0_133;
	bra.uni 	$L__BB0_131;

$L__BB0_133:
	add.f32 	%f1717, %f265, 0f3ED55555;
	bra.uni 	$L__BB0_134;

$L__BB0_131:
	setp.neu.f32 	%p171, %f279, 0f7F800000;
	@%p171 bra 	$L__BB0_134;

	selp.f32 	%f1717, 0fFF800000, 0f7F800000, %p9;

$L__BB0_134:
	abs.f32 	%f290, %f266;
	setp.lt.f32 	%p172, %f290, 0f00800000;
	mul.f32 	%f1393, %f290, 0f4B800000;
	selp.f32 	%f1394, %f1393, %f290, %p172;
	selp.f32 	%f1395, 0fC3170000, 0fC2FE0000, %p172;
	mov.b32 	%r396, %f1394;
	and.b32  	%r397, %r396, 8388607;
	or.b32  	%r398, %r397, 1065353216;
	mov.b32 	%f1396, %r398;
	shr.u32 	%r399, %r396, 23;
	cvt.rn.f32.u32 	%f1397, %r399;
	add.f32 	%f1398, %f1395, %f1397;
	setp.gt.f32 	%p173, %f1396, 0f3FB504F3;
	mul.f32 	%f1399, %f1396, 0f3F000000;
	add.f32 	%f1400, %f1398, 0f3F800000;
	selp.f32 	%f1401, %f1400, %f1398, %p173;
	selp.f32 	%f1402, %f1399, %f1396, %p173;
	add.f32 	%f1403, %f1402, 0fBF800000;
	add.f32 	%f1404, %f1402, 0f3F800000;
	rcp.approx.ftz.f32 	%f1405, %f1404;
	add.f32 	%f1406, %f1403, %f1403;
	mul.f32 	%f1407, %f1406, %f1405;
	mul.f32 	%f1408, %f1407, %f1407;
	mov.f32 	%f1409, 0f3C4CAF63;
	mov.f32 	%f1410, 0f3B18F0FE;
	fma.rn.f32 	%f1411, %f1410, %f1408, %f1409;
	mov.f32 	%f1412, 0f3DAAAABD;
	fma.rn.f32 	%f1413, %f1411, %f1408, %f1412;
	mul.rn.f32 	%f1414, %f1413, %f1408;
	mul.rn.f32 	%f1415, %f1414, %f1407;
	sub.f32 	%f1416, %f1403, %f1407;
	add.f32 	%f1417, %f1416, %f1416;
	neg.f32 	%f1418, %f1407;
	fma.rn.f32 	%f1419, %f1418, %f1403, %f1417;
	mul.rn.f32 	%f1420, %f1405, %f1419;
	add.f32 	%f1421, %f1415, %f1407;
	sub.f32 	%f1422, %f1407, %f1421;
	add.f32 	%f1423, %f1415, %f1422;
	add.f32 	%f1424, %f1420, %f1423;
	add.f32 	%f1425, %f1421, %f1424;
	sub.f32 	%f1426, %f1421, %f1425;
	add.f32 	%f1427, %f1424, %f1426;
	mov.f32 	%f1428, 0f3F317200;
	mul.rn.f32 	%f1429, %f1401, %f1428;
	mov.f32 	%f1430, 0f35BFBE8E;
	mul.rn.f32 	%f1431, %f1401, %f1430;
	add.f32 	%f1432, %f1429, %f1425;
	sub.f32 	%f1433, %f1429, %f1432;
	add.f32 	%f1434, %f1425, %f1433;
	add.f32 	%f1435, %f1427, %f1434;
	add.f32 	%f1436, %f1431, %f1435;
	add.f32 	%f1437, %f1432, %f1436;
	sub.f32 	%f1438, %f1432, %f1437;
	add.f32 	%f1439, %f1436, %f1438;
	mov.f32 	%f1440, 0f3ED55555;
	mul.rn.f32 	%f1441, %f1440, %f1437;
	neg.f32 	%f1442, %f1441;
	fma.rn.f32 	%f1443, %f1440, %f1437, %f1442;
	fma.rn.f32 	%f1444, %f1440, %f1439, %f1443;
	mov.f32 	%f1445, 0f00000000;
	fma.rn.f32 	%f1446, %f1445, %f1437, %f1444;
	add.rn.f32 	%f1447, %f1441, %f1446;
	neg.f32 	%f1448, %f1447;
	add.rn.f32 	%f1449, %f1441, %f1448;
	add.rn.f32 	%f1450, %f1449, %f1446;
	mov.b32 	%r400, %f1447;
	setp.eq.s32 	%p174, %r400, 1118925336;
	add.s32 	%r401, %r400, -1;
	mov.b32 	%f1451, %r401;
	add.f32 	%f1452, %f1450, 0f37000000;
	selp.f32 	%f291, %f1452, %f1450, %p174;
	selp.f32 	%f1453, %f1451, %f1447, %p174;
	mov.f32 	%f1454, 0f3FB8AA3B;
	mul.rn.f32 	%f1455, %f1453, %f1454;
	cvt.rzi.f32.f32 	%f1456, %f1455;
	abs.f32 	%f1457, %f1456;
	setp.gt.f32 	%p175, %f1457, 0f42FC0000;
	mov.b32 	%r402, %f1456;
	and.b32  	%r403, %r402, -2147483648;
	or.b32  	%r404, %r403, 1123811328;
	mov.b32 	%f1458, %r404;
	selp.f32 	%f1459, %f1458, %f1456, %p175;
	mov.f32 	%f1460, 0fBF317218;
	fma.rn.f32 	%f1461, %f1459, %f1460, %f1453;
	mov.f32 	%f1462, 0f3102E308;
	fma.rn.f32 	%f1463, %f1459, %f1462, %f1461;
	mul.f32 	%f1464, %f1463, 0f3FB8AA3B;
	add.f32 	%f1465, %f1459, 0f4B40007F;
	mov.b32 	%r405, %f1465;
	shl.b32 	%r406, %r405, 23;
	mov.b32 	%f1466, %r406;
	ex2.approx.ftz.f32 	%f1467, %f1464;
	mul.f32 	%f292, %f1467, %f1466;
	setp.eq.f32 	%p176, %f292, 0f7F800000;
	mov.f32 	%f1718, 0f7F800000;
	@%p176 bra 	$L__BB0_136;

	fma.rn.f32 	%f1718, %f292, %f291, %f292;

$L__BB0_136:
	setp.lt.f32 	%p177, %f266, 0f00000000;
	and.pred  	%p10, %p177, %p150;
	setp.eq.f32 	%p179, %f266, 0f00000000;
	@%p179 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_137;

$L__BB0_140:
	add.f32 	%f1472, %f266, %f266;
	selp.f32 	%f1720, %f1472, 0f00000000, %p150;
	bra.uni 	$L__BB0_141;

$L__BB0_137:
	mov.b32 	%r407, %f1718;
	xor.b32  	%r408, %r407, -2147483648;
	mov.b32 	%f1468, %r408;
	selp.f32 	%f1720, %f1468, %f1718, %p10;
	setp.geu.f32 	%p180, %f266, 0f00000000;
	@%p180 bra 	$L__BB0_141;

	mov.f32 	%f1469, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1470, %f1469;
	setp.eq.f32 	%p181, %f1470, 0f3ED55555;
	@%p181 bra 	$L__BB0_141;

	mov.f32 	%f1720, 0f7FFFFFFF;

$L__BB0_141:
	add.f32 	%f1473, %f290, 0f3ED55555;
	mov.b32 	%r409, %f1473;
	setp.lt.s32 	%p183, %r409, 2139095040;
	@%p183 bra 	$L__BB0_146;

	setp.gtu.f32 	%p184, %f290, 0f7F800000;
	@%p184 bra 	$L__BB0_145;
	bra.uni 	$L__BB0_143;

$L__BB0_145:
	add.f32 	%f1720, %f266, 0f3ED55555;
	bra.uni 	$L__BB0_146;

$L__BB0_143:
	setp.neu.f32 	%p185, %f290, 0f7F800000;
	@%p185 bra 	$L__BB0_146;

	selp.f32 	%f1720, 0fFF800000, 0f7F800000, %p10;

$L__BB0_146:
	fma.rn.f32 	%f1474, %f1714, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p186, %f264, 0f3F800000;
	mov.f32 	%f1475, 0f3F800000;
	selp.f32 	%f1476, 0f3F7FFFFF, %f1474, %p186;
	mul.f32 	%f1477, %f264, 0f414EB852;
	setp.lt.f32 	%p187, %f264, 0f3B4D2E1C;
	selp.f32 	%f1478, %f1477, %f1476, %p187;
	fma.rn.f32 	%f1479, %f1717, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p188, %f265, 0f3F800000;
	selp.f32 	%f1480, 0f3F7FFFFF, %f1479, %p188;
	mul.f32 	%f1481, %f265, 0f414EB852;
	setp.lt.f32 	%p189, %f265, 0f3B4D2E1C;
	selp.f32 	%f1482, %f1481, %f1480, %p189;
	fma.rn.f32 	%f1483, %f1720, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p190, %f266, 0f3F800000;
	selp.f32 	%f1484, 0f3F7FFFFF, %f1483, %p190;
	mul.f32 	%f1485, %f266, 0f414EB852;
	setp.lt.f32 	%p191, %f266, 0f3B4D2E1C;
	selp.f32 	%f1486, %f1485, %f1484, %p191;
	min.f32 	%f1487, %f1478, %f1475;
	mov.f32 	%f1488, 0f00000000;
	max.f32 	%f1489, %f1488, %f1487;
	mul.f32 	%f1490, %f1489, 0f43800000;
	cvt.rzi.u32.f32 	%r410, %f1490;
	min.u32 	%r411, %r410, 255;
	min.f32 	%f1491, %f1482, %f1475;
	max.f32 	%f1492, %f1488, %f1491;
	mul.f32 	%f1493, %f1492, 0f43800000;
	cvt.rzi.u32.f32 	%r412, %f1493;
	min.u32 	%r413, %r412, 255;
	min.f32 	%f1494, %f1486, %f1475;
	max.f32 	%f1495, %f1488, %f1494;
	mul.f32 	%f1496, %f1495, 0f43800000;
	cvt.rzi.u32.f32 	%r414, %f1496;
	min.u32 	%r415, %r414, 255;
	shl.b64 	%rd37, %rd10, 2;
	add.s64 	%rd38, %rd9, %rd37;
	cvt.u16.u32 	%rs20, %r415;
	cvt.u16.u32 	%rs21, %r413;
	cvt.u16.u32 	%rs22, %r411;
	mov.u16 	%rs23, 255;
	st.global.v4.u8 	[%rd38], {%rs22, %rs21, %rs20, %rs23};

$L__BB0_147:
	and.b32  	%r416, %r451, 4;
	setp.eq.s32 	%p192, %r416, 0;
	ld.const.u32 	%r452, [params+108];
	@%p192 bra 	$L__BB0_151;

	setp.eq.s32 	%p193, %r452, 0;
	ld.const.u64 	%rd39, [params+224];
	cvta.to.global.u64 	%rd40, %rd39;
	ld.const.u32 	%r417, [params+216];
	mad.lo.s32 	%r418, %r417, %r4, %r3;
	mul.wide.u32 	%rd41, %r418, 8;
	add.s64 	%rd11, %rd40, %rd41;
	@%p193 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs31, %rs32, %rs33, %rs34}, [%rd11];
	// begin inline asm
	{  cvt.f32.f16 %f1497, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1498, %rs32;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1499, %rs33;}

	// end inline asm
	add.f32 	%f1500, %f1668, %f1497;
	add.f32 	%f1501, %f1669, %f1498;
	add.f32 	%f1502, %f1670, %f1499;
	mov.f32 	%f1503, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1502;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1501;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1500;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1503;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs27, %rs28, %rs29, %rs30};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1507, 0f3F800000;
	mov.u32 	%r452, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1507;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f1670;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1669;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f1668;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs35, %rs36, %rs37, %rs38};

$L__BB0_151:
	mov.f32 	%f1508, 0f34000000;
	max.f32 	%f1509, %f1671, %f1508;
	div.rn.f32 	%f1510, %f1674, %f1509;
	max.f32 	%f1511, %f1672, %f1508;
	div.rn.f32 	%f1512, %f1675, %f1511;
	max.f32 	%f1513, %f1673, %f1508;
	div.rn.f32 	%f1514, %f1676, %f1513;
	fma.rn.f32 	%f301, %f1510, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f302, %f1512, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f303, %f1514, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1515, %f1677, %f1509;
	div.rn.f32 	%f1516, %f1678, %f1511;
	div.rn.f32 	%f1517, %f1679, %f1513;
	fma.rn.f32 	%f304, %f1515, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f305, %f1516, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f306, %f1517, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1518, %f1680, %f1509;
	div.rn.f32 	%f1519, %f1681, %f1511;
	div.rn.f32 	%f1520, %f1682, %f1513;
	fma.rn.f32 	%f307, %f1518, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f308, %f1519, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f309, %f1520, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd42, [params+256];
	cvta.to.global.u64 	%rd43, %rd42;
	ld.const.u32 	%r420, [params+248];
	mad.lo.s32 	%r421, %r420, %r4, %r3;
	mul.wide.u32 	%rd44, %r421, 8;
	add.s64 	%rd12, %rd43, %rd44;
	setp.eq.s32 	%p194, %r452, 0;
	@%p194 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs46, %rs47, %rs48, %rs49}, [%rd12];
	// begin inline asm
	{  cvt.f32.f16 %f1521, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1522, %rs47;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1523, %rs48;}

	// end inline asm
	add.f32 	%f1524, %f1671, %f1521;
	add.f32 	%f1525, %f1672, %f1522;
	add.f32 	%f1526, %f1673, %f1523;
	mov.f32 	%f1527, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1526;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1525;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1524;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f1527;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs42, %rs43, %rs44, %rs45};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1531, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1531;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f1673;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1672;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f1671;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs50, %rs51, %rs52, %rs53};

$L__BB0_154:
	ld.const.u64 	%rd45, [params+272];
	cvta.to.global.u64 	%rd46, %rd45;
	ld.const.u32 	%r422, [params+264];
	mad.lo.s32 	%r423, %r422, %r4, %r3;
	mul.wide.u32 	%rd47, %r423, 8;
	add.s64 	%rd13, %rd46, %rd47;
	@%p194 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs61, %rs62, %rs63, %rs64}, [%rd13];
	// begin inline asm
	{  cvt.f32.f16 %f1532, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1533, %rs62;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1534, %rs63;}

	// end inline asm
	add.f32 	%f1535, %f301, %f1532;
	add.f32 	%f1536, %f302, %f1533;
	add.f32 	%f1537, %f303, %f1534;
	mov.f32 	%f1538, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1537;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1536;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1535;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1538;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs57, %rs58, %rs59, %rs60};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1542, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1542;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f303;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f302;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f301;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs65, %rs66, %rs67, %rs68};

$L__BB0_157:
	ld.const.u64 	%rd48, [params+288];
	cvta.to.global.u64 	%rd49, %rd48;
	ld.const.u32 	%r424, [params+280];
	mad.lo.s32 	%r425, %r424, %r4, %r3;
	mul.wide.u32 	%rd50, %r425, 8;
	add.s64 	%rd14, %rd49, %rd50;
	@%p194 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs76, %rs77, %rs78, %rs79}, [%rd14];
	// begin inline asm
	{  cvt.f32.f16 %f1543, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1544, %rs77;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1545, %rs78;}

	// end inline asm
	add.f32 	%f1546, %f304, %f1543;
	add.f32 	%f1547, %f305, %f1544;
	add.f32 	%f1548, %f306, %f1545;
	mov.f32 	%f1549, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1548;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1547;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1546;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f1549;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs72, %rs73, %rs74, %rs75};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1553, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1553;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f306;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f305;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f304;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs80, %rs81, %rs82, %rs83};

$L__BB0_160:
	ld.const.u64 	%rd51, [params+304];
	cvta.to.global.u64 	%rd52, %rd51;
	ld.const.u32 	%r426, [params+296];
	mad.lo.s32 	%r427, %r426, %r4, %r3;
	mul.wide.u32 	%rd53, %r427, 8;
	add.s64 	%rd15, %rd52, %rd53;
	@%p194 bra 	$L__BB0_162;

	ld.global.v4.u16 	{%rs91, %rs92, %rs93, %rs94}, [%rd15];
	// begin inline asm
	{  cvt.f32.f16 %f1554, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1555, %rs92;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1556, %rs93;}

	// end inline asm
	add.f32 	%f1557, %f307, %f1554;
	add.f32 	%f1558, %f308, %f1555;
	add.f32 	%f1559, %f309, %f1556;
	mov.f32 	%f1560, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1559;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1558;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1557;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f1560;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs87, %rs88, %rs89, %rs90};
	bra.uni 	$L__BB0_183;

$L__BB0_162:
	mov.f32 	%f1564, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1564;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f309;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f308;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f307;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs95, %rs96, %rs97, %rs98};

$L__BB0_183:
	ret;

}