//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<165>;
	.reg .b16 	%rs<316>;
	.reg .f32 	%f<1426>;
	.reg .b32 	%r<384>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<162>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r53), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r54), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	shl.b32 	%r4, %r3, 1;
	ld.const.u64 	%rd37, [params+400];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r59, [params+392];
	mad.lo.s32 	%r60, %r59, %r54, %r53;
	mul.wide.u32 	%rd39, %r60, 4;
	add.s64 	%rd2, %rd38, %rd39;
	ld.global.v2.u8 	{%rs7, %rs315}, [%rd2];
	or.b16  	%rs9, %rs7, %rs315;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p7, %rs10, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs314, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs314, [%rd2+2];
	setp.eq.s16 	%p8, %rs314, 0;
	mov.f32 	%f1306, 0f00000000;
	mov.u16 	%rs315, 0;
	mov.f32 	%f1307, %f1306;
	mov.f32 	%f1308, %f1306;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f318, %rs7;
	div.rn.f32 	%f319, %f318, 0f437F0000;
	fma.rn.f32 	%f320, %f319, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs315, 255;
	cvt.rn.f32.u16 	%f321, %rs13;
	div.rn.f32 	%f322, %f321, 0f437F0000;
	fma.rn.f32 	%f323, %f322, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f324, %rs314;
	div.rn.f32 	%f325, %f324, 0f437F0000;
	fma.rn.f32 	%f326, %f325, 0f40000000, 0fBF800000;
	mul.f32 	%f327, %f323, %f323;
	fma.rn.f32 	%f328, %f320, %f320, %f327;
	fma.rn.f32 	%f329, %f326, %f326, %f328;
	sqrt.rn.f32 	%f330, %f329;
	rcp.rn.f32 	%f331, %f330;
	mul.f32 	%f1308, %f331, %f326;
	mul.f32 	%f1307, %f331, %f323;
	mul.f32 	%f1306, %f320, %f331;

$L__BB0_4:
	ld.const.v2.u32 	{%r61, %r62}, [params];
	add.s32 	%r5, %r61, %r53;
	add.s32 	%r6, %r62, %r54;
	setp.eq.f32 	%p9, %f1306, 0f00000000;
	setp.eq.f32 	%p10, %f1307, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1308, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_143;
	bra.uni 	$L__BB0_5;

$L__BB0_143:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r326, %r51, 1;
	setp.eq.b32 	%p149, %r326, 1;
	mov.pred 	%p150, 0;
	xor.pred  	%p151, %p149, %p150;
	not.pred 	%p152, %p151;
	@%p152 bra 	$L__BB0_145;

	ld.const.u64 	%rd115, [params+144];
	cvta.to.global.u64 	%rd116, %rd115;
	ld.const.u32 	%r327, [params+136];
	mad.lo.s32 	%r328, %r327, %r6, %r5;
	mul.wide.u32 	%rd117, %r328, 4;
	add.s64 	%rd118, %rd116, %rd117;
	mov.u16 	%rs170, 0;
	st.global.v4.u8 	[%rd118], {%rs170, %rs170, %rs170, %rs170};

$L__BB0_145:
	and.b32  	%r329, %r51, 4;
	setp.eq.s32 	%p153, %r329, 0;
	@%p153 bra 	$L__BB0_147;

	ld.const.u64 	%rd119, [params+224];
	cvta.to.global.u64 	%rd120, %rd119;
	ld.const.u32 	%r330, [params+216];
	mad.lo.s32 	%r331, %r330, %r6, %r5;
	mov.f32 	%f1206, 0f00000000;
	mul.wide.u32 	%rd121, %r331, 8;
	add.s64 	%rd122, %rd120, %rd121;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1206;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1206;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1206;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd122], {%rs171, %rs172, %rs173, %rs174};

$L__BB0_147:
	and.b32  	%r332, %r51, 16;
	setp.eq.s32 	%p154, %r332, 0;
	@%p154 bra 	$L__BB0_149;

	ld.const.u64 	%rd123, [params+240];
	cvta.to.global.u64 	%rd124, %rd123;
	ld.const.u32 	%r333, [params+232];
	mad.lo.s32 	%r334, %r333, %r6, %r5;
	mov.f32 	%f1209, 0f00000000;
	mul.wide.u32 	%rd125, %r334, 8;
	add.s64 	%rd126, %rd124, %rd125;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs177, %f1209;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs176, %f1209;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1209;}

	// end inline asm
	mov.u16 	%rs178, 0;
	st.global.v4.u16 	[%rd126], {%rs175, %rs176, %rs177, %rs178};

$L__BB0_149:
	ld.const.u32 	%r52, [params+108];
	setp.eq.s32 	%p155, %r52, 0;
	ld.const.u64 	%rd127, [params+256];
	cvta.to.global.u64 	%rd128, %rd127;
	ld.const.u32 	%r335, [params+248];
	mad.lo.s32 	%r336, %r335, %r6, %r5;
	mul.wide.u32 	%rd129, %r336, 8;
	add.s64 	%rd27, %rd128, %rd129;
	@%p155 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs185, %rs186, %rs187, %rs188}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1210, %rs185;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1211, %rs186;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1212, %rs187;}

	// end inline asm
	add.f32 	%f1213, %f1210, 0f00000000;
	add.f32 	%f1214, %f1211, 0f00000000;
	add.f32 	%f1215, %f1212, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs184, %f1215;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs183, %f1214;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs182, %f1213;}

	// end inline asm
	mov.u16 	%rs189, 0;
	st.global.v4.u16 	[%rd27], {%rs182, %rs183, %rs184, %rs189};
	bra.uni 	$L__BB0_152;

$L__BB0_5:
	ld.const.u64 	%rd40, [params+496];
	cvta.to.global.u64 	%rd41, %rd40;
	ld.const.u32 	%r65, [params+488];
	mad.lo.s32 	%r66, %r65, %r54, %r53;
	mul.wide.u32 	%rd42, %r66, 8;
	add.s64 	%rd43, %rd41, %rd42;
	ld.global.v4.u16 	{%rs19, %rs20, %rs21, %rs22}, [%rd43];
	// begin inline asm
	{  cvt.f32.f16 %f332, %rs19;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f333, %rs20;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f334, %rs21;}

	// end inline asm
	ld.const.u64 	%rd44, [params+432];
	cvta.to.global.u64 	%rd45, %rd44;
	ld.const.u32 	%r67, [params+424];
	mad.lo.s32 	%r68, %r67, %r54, %r53;
	mul.wide.u32 	%rd46, %r68, 12;
	add.s64 	%rd47, %rd45, %rd46;
	ld.global.f32 	%f366, [%rd47];
	mul.f32 	%f367, %f366, 0f3456BF95;
	ld.global.f32 	%f368, [%rd47+4];
	mul.f32 	%f369, %f368, 0f3456BF95;
	ld.global.f32 	%f370, [%rd47+8];
	mul.f32 	%f371, %f370, 0f3456BF95;
	abs.f32 	%f372, %f1306;
	div.rn.f32 	%f373, %f367, %f372;
	abs.f32 	%f374, %f1307;
	div.rn.f32 	%f375, %f369, %f374;
	abs.f32 	%f376, %f1308;
	div.rn.f32 	%f377, %f371, %f376;
	abs.f32 	%f378, %f373;
	abs.f32 	%f379, %f375;
	abs.f32 	%f380, %f377;
	mov.f32 	%f381, 0f38D1B717;
	max.f32 	%f382, %f378, %f381;
	max.f32 	%f383, %f379, %f381;
	max.f32 	%f384, %f380, %f381;
	fma.rn.f32 	%f13, %f1306, %f382, %f366;
	fma.rn.f32 	%f14, %f1307, %f383, %f368;
	fma.rn.f32 	%f15, %f1308, %f384, %f370;
	setp.gt.f32 	%p14, %f372, %f376;
	neg.f32 	%f385, %f1307;
	selp.f32 	%f386, %f385, 0f00000000, %p14;
	mov.f32 	%f1368, 0f00000000;
	neg.f32 	%f387, %f1308;
	selp.f32 	%f388, %f1306, %f387, %p14;
	selp.f32 	%f389, 0f00000000, %f1307, %p14;
	mul.f32 	%f390, %f388, %f388;
	fma.rn.f32 	%f391, %f386, %f386, %f390;
	fma.rn.f32 	%f392, %f389, %f389, %f391;
	sqrt.rn.f32 	%f393, %f392;
	rcp.rn.f32 	%f394, %f393;
	mul.f32 	%f16, %f386, %f394;
	mul.f32 	%f17, %f388, %f394;
	mul.f32 	%f18, %f389, %f394;
	ld.const.u64 	%rd48, [params+128];
	cvta.to.global.u64 	%rd49, %rd48;
	ld.const.u32 	%r69, [params+120];
	mad.lo.s32 	%r70, %r69, %r54, %r53;
	mul.wide.u32 	%rd50, %r70, 4;
	add.s64 	%rd3, %rd49, %rd50;
	setp.lt.s32 	%p15, %r3, 1;
	mov.f32 	%f1367, %f1368;
	mov.f32 	%f1366, %f1368;
	mov.f32 	%f1365, %f1368;
	mov.f32 	%f1364, %f1368;
	mov.f32 	%f1363, %f1368;
	mov.f32 	%f1362, %f1368;
	mov.f32 	%f1361, %f1368;
	mov.f32 	%f1360, %f1368;
	mov.f32 	%f1359, %f1368;
	mov.f32 	%f1358, %f1368;
	mov.f32 	%f1357, %f1368;
	mov.f32 	%f1356, %f1368;
	mov.f32 	%f1355, %f1368;
	mov.f32 	%f1354, %f1368;
	mov.f32 	%f1353, %f1368;
	mov.f32 	%f1352, %f1368;
	mov.f32 	%f1351, %f1368;
	mov.f32 	%f1350, %f1368;
	mov.f32 	%f1349, %f1368;
	mov.f32 	%f1348, %f1368;
	mov.f32 	%f1347, %f1368;
	mov.f32 	%f1346, %f1368;
	mov.f32 	%f1345, %f1368;
	mov.f32 	%f1344, %f1368;
	mov.f32 	%f1343, %f1368;
	mov.f32 	%f1342, %f1368;
	mov.f32 	%f1341, %f1368;
	mov.f32 	%f1340, %f1368;
	mov.f32 	%f1339, %f1368;
	@%p15 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f425, %r4;
	rcp.rn.f32 	%f19, %f425;
	ld.global.u32 	%r376, [%rd3];
	mul.f32 	%f20, %f13, 0f3456BF95;
	mul.f32 	%f21, %f14, 0f3456BF95;
	mul.f32 	%f22, %f15, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f426, %f1306, %f17;
	mul.f32 	%f427, %f1307, %f16;
	sub.f32 	%f23, %f427, %f426;
	mul.f32 	%f428, %f1308, %f16;
	mul.f32 	%f429, %f1306, %f18;
	sub.f32 	%f24, %f429, %f428;
	mul.f32 	%f430, %f1307, %f18;
	mul.f32 	%f431, %f1308, %f17;
	sub.f32 	%f25, %f431, %f430;
	mov.u32 	%r71, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f496, %f21;
	abs.f32 	%f497, %f20;
	max.f32 	%f498, %f497, %f496;
	abs.f32 	%f499, %f22;
	max.f32 	%f500, %f498, %f499;
	mov.u32 	%r373, %r71;

$L__BB0_7:
	mov.u32 	%r375, %r71;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1297, %r373;
	mad.lo.s32 	%r73, %r376, 1664525, 1013904223;
	and.b32  	%r74, %r73, 16777215;
	cvt.rn.f32.u32 	%f432, %r74;
	fma.rn.f32 	%f433, %f432, 0f33800000, %f1297;
	mul.f32 	%f434, %f19, %f433;
	mad.lo.s32 	%r376, %r73, 1664525, 1013904223;
	and.b32  	%r75, %r376, 16777215;
	cvt.rn.f32.u32 	%f435, %r75;
	cvt.rn.f32.s32 	%f436, %r375;
	fma.rn.f32 	%f437, %f435, 0f33800000, %f436;
	mul.f32 	%f438, %f19, %f437;
	fma.rn.f32 	%f439, %f19, %f433, %f434;
	mov.f32 	%f440, 0f3F800000;
	sub.f32 	%f87, %f440, %f439;
	mul.f32 	%f441, %f87, %f87;
	sub.f32 	%f442, %f440, %f441;
	mov.f32 	%f443, 0f00000000;
	max.f32 	%f444, %f443, %f442;
	sqrt.rn.f32 	%f88, %f444;
	mul.f32 	%f89, %f438, 0f40C90FDB;
	mul.f32 	%f445, %f89, 0f3F22F983;
	cvt.rni.s32.f32 	%r380, %f445;
	cvt.rn.f32.s32 	%f446, %r380;
	mov.f32 	%f447, 0fBFC90FDA;
	fma.rn.f32 	%f448, %f446, %f447, %f89;
	mov.f32 	%f449, 0fB3A22168;
	fma.rn.f32 	%f450, %f446, %f449, %f448;
	mov.f32 	%f451, 0fA7C234C5;
	fma.rn.f32 	%f1372, %f446, %f451, %f450;
	abs.f32 	%f91, %f89;
	setp.ltu.f32 	%p16, %f91, 0f47CE4780;
	mov.f32 	%f1369, %f1372;
	@%p16 bra 	$L__BB0_16;

	setp.eq.f32 	%p17, %f91, 0f7F800000;
	@%p17 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f454, 0f00000000;
	mul.rn.f32 	%f1369, %f89, %f454;
	mov.u32 	%r380, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r14, %f89;
	bfe.u32 	%r77, %r14, 23, 8;
	mov.u64 	%rd159, 0;
	mov.u32 	%r377, 0;
	mov.u64 	%rd157, %rd1;
	mov.u64 	%rd158, %rd51;

$L__BB0_11:
	.pragma "nounroll";
	mov.b32 	%r356, %f89;
	shl.b32 	%r355, %r356, 8;
	or.b32  	%r354, %r355, -2147483648;
	ld.global.nc.u32 	%r79, [%rd158];
	mad.wide.u32 	%rd53, %r79, %r354, %rd159;
	shr.u64 	%rd159, %rd53, 32;
	st.local.u32 	[%rd157], %rd53;
	add.s64 	%rd158, %rd158, 4;
	add.s64 	%rd157, %rd157, 4;
	add.s32 	%r377, %r377, 1;
	setp.ne.s32 	%p18, %r377, 6;
	@%p18 bra 	$L__BB0_11;

	add.s32 	%r361, %r77, -128;
	mov.b32 	%r360, %f89;
	bfe.u32 	%r359, %r360, 23, 8;
	add.s32 	%r358, %r359, -128;
	shr.u32 	%r357, %r358, 5;
	st.local.u32 	[%rd5], %rd159;
	mov.u32 	%r81, 6;
	sub.s32 	%r82, %r81, %r357;
	mul.wide.s32 	%rd54, %r82, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r378, [%rd55];
	ld.local.u32 	%r379, [%rd55+-4];
	and.b32  	%r23, %r358, 31;
	setp.eq.s32 	%p19, %r23, 0;
	@%p19 bra 	$L__BB0_14;

	mov.b32 	%r368, %f89;
	bfe.u32 	%r367, %r368, 23, 8;
	add.s32 	%r366, %r367, -128;
	shr.u32 	%r365, %r366, 5;
	mov.u32 	%r364, 4;
	sub.s32 	%r363, %r364, %r365;
	mov.u32 	%r83, 32;
	sub.s32 	%r84, %r83, %r23;
	shr.u32 	%r85, %r379, %r84;
	shl.b32 	%r86, %r378, %r23;
	add.s32 	%r378, %r85, %r86;
	mul.wide.s32 	%rd56, %r363, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r87, [%rd57];
	shr.u32 	%r88, %r87, %r84;
	shl.b32 	%r89, %r379, %r23;
	add.s32 	%r379, %r88, %r89;

$L__BB0_14:
	mov.b32 	%r362, %f89;
	and.b32  	%r90, %r362, -2147483648;
	shr.u32 	%r91, %r379, 30;
	shl.b32 	%r92, %r378, 2;
	or.b32  	%r93, %r91, %r92;
	shr.u32 	%r94, %r93, 31;
	shr.u32 	%r95, %r378, 30;
	add.s32 	%r96, %r94, %r95;
	neg.s32 	%r97, %r96;
	setp.eq.s32 	%p20, %r90, 0;
	selp.b32 	%r380, %r96, %r97, %p20;
	setp.ne.s32 	%p21, %r94, 0;
	xor.b32  	%r98, %r90, -2147483648;
	selp.b32 	%r99, %r98, %r90, %p21;
	selp.b32 	%r100, -1, 0, %p21;
	xor.b32  	%r101, %r93, %r100;
	shl.b32 	%r102, %r379, 2;
	xor.b32  	%r103, %r102, %r100;
	cvt.u64.u32 	%rd58, %r101;
	cvt.u64.u32 	%rd59, %r103;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f452, %fd2;
	setp.eq.s32 	%p22, %r99, 0;
	neg.f32 	%f453, %f452;
	selp.f32 	%f1369, %f452, %f453, %p22;

$L__BB0_16:
	add.s32 	%r30, %r380, 1;
	and.b32  	%r31, %r30, 1;
	setp.eq.s32 	%p23, %r31, 0;
	selp.f32 	%f95, %f1369, 0f3F800000, %p23;
	mul.rn.f32 	%f96, %f1369, %f1369;
	mov.f32 	%f1370, 0fB94D4153;
	@%p23 bra 	$L__BB0_18;

	mov.f32 	%f456, 0fBAB607ED;
	mov.f32 	%f457, 0f37CBAC00;
	fma.rn.f32 	%f1370, %f457, %f96, %f456;

$L__BB0_18:
	selp.f32 	%f458, 0f3C0885E4, 0f3D2AAABB, %p23;
	fma.rn.f32 	%f459, %f1370, %f96, %f458;
	selp.f32 	%f460, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
	fma.rn.f32 	%f461, %f459, %f96, %f460;
	mov.f32 	%f462, 0f00000000;
	fma.rn.f32 	%f463, %f96, %f95, %f462;
	fma.rn.f32 	%f1371, %f461, %f463, %f95;
	and.b32  	%r105, %r30, 2;
	setp.eq.s32 	%p25, %r105, 0;
	@%p25 bra 	$L__BB0_20;

	mov.f32 	%f465, 0fBF800000;
	fma.rn.f32 	%f1371, %f1371, %f465, %f462;

$L__BB0_20:
	mul.f32 	%f1298, %f89, 0f3F22F983;
	cvt.rni.s32.f32 	%r383, %f1298;
	setp.ltu.f32 	%p164, %f91, 0f47CE4780;
	@%p164 bra 	$L__BB0_28;

	setp.eq.f32 	%p27, %f91, 0f7F800000;
	@%p27 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f468, 0f00000000;
	mul.rn.f32 	%f1372, %f89, %f468;
	mov.u32 	%r383, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r32, %f89;
	bfe.u32 	%r106, %r32, 23, 8;
	add.s32 	%r33, %r106, -128;
	shl.b32 	%r107, %r32, 8;
	or.b32  	%r34, %r107, -2147483648;
	shr.u32 	%r35, %r33, 5;
	mov.u64 	%rd160, 0;
	mov.u64 	%rd161, %rd160;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd160, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r108, [%rd65];
	mad.wide.u32 	%rd66, %r108, %r34, %rd161;
	shr.u64 	%rd161, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r109, %rd160;
	add.s32 	%r110, %r109, 1;
	cvt.s64.s32 	%rd160, %r110;
	setp.ne.s32 	%p28, %r110, 6;
	@%p28 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd161;
	mov.u32 	%r111, 4;
	sub.s32 	%r36, %r111, %r35;
	mov.u32 	%r112, 6;
	sub.s32 	%r113, %r112, %r35;
	mul.wide.s32 	%rd68, %r113, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r381, [%rd69];
	ld.local.u32 	%r382, [%rd69+-4];
	and.b32  	%r39, %r33, 31;
	setp.eq.s32 	%p29, %r39, 0;
	@%p29 bra 	$L__BB0_26;

	mov.u32 	%r114, 32;
	sub.s32 	%r115, %r114, %r39;
	shr.u32 	%r116, %r382, %r115;
	shl.b32 	%r117, %r381, %r39;
	add.s32 	%r381, %r116, %r117;
	mul.wide.s32 	%rd70, %r36, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r118, [%rd71];
	shr.u32 	%r119, %r118, %r115;
	shl.b32 	%r120, %r382, %r39;
	add.s32 	%r382, %r119, %r120;

$L__BB0_26:
	and.b32  	%r121, %r32, -2147483648;
	shr.u32 	%r122, %r382, 30;
	shl.b32 	%r123, %r381, 2;
	or.b32  	%r124, %r122, %r123;
	shr.u32 	%r125, %r124, 31;
	shr.u32 	%r126, %r381, 30;
	add.s32 	%r127, %r125, %r126;
	neg.s32 	%r128, %r127;
	setp.eq.s32 	%p30, %r121, 0;
	selp.b32 	%r383, %r127, %r128, %p30;
	setp.ne.s32 	%p31, %r125, 0;
	xor.b32  	%r129, %r121, -2147483648;
	selp.b32 	%r130, %r129, %r121, %p31;
	selp.b32 	%r131, -1, 0, %p31;
	xor.b32  	%r132, %r124, %r131;
	shl.b32 	%r133, %r382, 2;
	xor.b32  	%r134, %r133, %r131;
	cvt.u64.u32 	%rd72, %r132;
	cvt.u64.u32 	%rd73, %r134;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f466, %fd4;
	setp.eq.s32 	%p32, %r130, 0;
	neg.f32 	%f467, %f466;
	selp.f32 	%f1372, %f466, %f467, %p32;

$L__BB0_28:
	mul.f32 	%f105, %f88, %f1371;
	and.b32  	%r46, %r383, 1;
	setp.eq.s32 	%p33, %r46, 0;
	mul.rn.f32 	%f107, %f1372, %f1372;
	mov.f32 	%f1373, 0fB94D4153;
	@%p33 bra 	$L__BB0_30;

	mov.f32 	%f470, 0fBAB607ED;
	mov.f32 	%f471, 0f37CBAC00;
	fma.rn.f32 	%f1373, %f471, %f107, %f470;

$L__BB0_30:
	selp.f32 	%f1299, %f1372, 0f3F800000, %p33;
	selp.f32 	%f472, 0f3C0885E4, 0f3D2AAABB, %p33;
	fma.rn.f32 	%f473, %f1373, %f107, %f472;
	selp.f32 	%f474, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
	fma.rn.f32 	%f475, %f473, %f107, %f474;
	mov.f32 	%f476, 0f00000000;
	fma.rn.f32 	%f477, %f107, %f1299, %f476;
	fma.rn.f32 	%f1374, %f475, %f477, %f1299;
	and.b32  	%r136, %r383, 2;
	setp.eq.s32 	%p35, %r136, 0;
	@%p35 bra 	$L__BB0_32;

	mov.f32 	%f479, 0fBF800000;
	fma.rn.f32 	%f1374, %f1374, %f479, %f476;

$L__BB0_32:
	mul.f32 	%f489, %f88, %f1374;
	mul.f32 	%f490, %f16, %f489;
	mul.f32 	%f491, %f17, %f489;
	mul.f32 	%f492, %f18, %f489;
	fma.rn.f32 	%f493, %f25, %f105, %f490;
	fma.rn.f32 	%f494, %f24, %f105, %f491;
	fma.rn.f32 	%f495, %f23, %f105, %f492;
	fma.rn.f32 	%f483, %f1306, %f87, %f493;
	fma.rn.f32 	%f484, %f1307, %f87, %f494;
	fma.rn.f32 	%f485, %f1308, %f87, %f495;
	mov.f32 	%f501, 0f38D1B717;
	max.f32 	%f486, %f500, %f501;
	mov.f32 	%f487, 0f6C4ECB8F;
	mov.u32 	%r170, 1;
	mov.u32 	%r173, 2;
	mov.u32 	%r175, 3;
	mov.u32 	%r207, 0;
	// begin inline asm
	call(%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168),_optix_trace_typed_32,(%r207,%rd4,%f13,%f14,%f15,%f483,%f484,%f485,%f486,%f487,%f476,%r170,%r207,%r207,%r173,%r207,%r175,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207);
	// end inline asm
	mov.b32 	%f502, %r137;
	mov.b32 	%f503, %r138;
	mov.b32 	%f504, %r139;
	mul.f32 	%f505, %f1307, %f484;
	fma.rn.f32 	%f506, %f1306, %f483, %f505;
	fma.rn.f32 	%f507, %f1308, %f485, %f506;
	add.f32 	%f1344, %f1344, %f502;
	add.f32 	%f1343, %f1343, %f503;
	add.f32 	%f1342, %f1342, %f504;
	fma.rn.f32 	%f1347, %f484, %f502, %f1347;
	fma.rn.f32 	%f1346, %f484, %f503, %f1346;
	fma.rn.f32 	%f1345, %f484, %f504, %f1345;
	fma.rn.f32 	%f1350, %f485, %f502, %f1350;
	fma.rn.f32 	%f1349, %f485, %f503, %f1349;
	fma.rn.f32 	%f1348, %f485, %f504, %f1348;
	fma.rn.f32 	%f1353, %f483, %f502, %f1353;
	fma.rn.f32 	%f1352, %f483, %f503, %f1352;
	fma.rn.f32 	%f1351, %f483, %f504, %f1351;
	mul.f32 	%f508, %f483, %f484;
	fma.rn.f32 	%f1356, %f508, %f502, %f1356;
	fma.rn.f32 	%f1355, %f508, %f503, %f1355;
	fma.rn.f32 	%f1354, %f508, %f504, %f1354;
	mul.f32 	%f509, %f484, %f485;
	fma.rn.f32 	%f1359, %f509, %f502, %f1359;
	fma.rn.f32 	%f1358, %f509, %f503, %f1358;
	fma.rn.f32 	%f1357, %f509, %f504, %f1357;
	fma.rn.f32 	%f510, %f485, %f485, 0fBEAAAAAB;
	fma.rn.f32 	%f1362, %f510, %f502, %f1362;
	fma.rn.f32 	%f1361, %f510, %f503, %f1361;
	fma.rn.f32 	%f1360, %f510, %f504, %f1360;
	mul.f32 	%f511, %f483, %f485;
	fma.rn.f32 	%f1365, %f511, %f502, %f1365;
	fma.rn.f32 	%f1364, %f511, %f503, %f1364;
	fma.rn.f32 	%f1363, %f511, %f504, %f1363;
	mul.f32 	%f512, %f483, %f483;
	mul.f32 	%f513, %f484, %f484;
	sub.f32 	%f514, %f512, %f513;
	fma.rn.f32 	%f1368, %f514, %f502, %f1368;
	fma.rn.f32 	%f1367, %f514, %f503, %f1367;
	fma.rn.f32 	%f1366, %f514, %f504, %f1366;
	cvt.sat.f32.f32 	%f515, %f507;
	fma.rn.f32 	%f1341, %f515, %f502, %f1341;
	fma.rn.f32 	%f1340, %f515, %f503, %f1340;
	fma.rn.f32 	%f1339, %f515, %f504, %f1339;
	add.s32 	%r375, %r375, 1;
	setp.lt.s32 	%p36, %r375, %r4;
	@%p36 bra 	$L__BB0_8;

	add.s32 	%r373, %r373, 1;
	setp.lt.s32 	%p37, %r373, %r4;
	@%p37 bra 	$L__BB0_7;

$L__BB0_34:
	mov.f32 	%f1405, 0f00000000;
	mul.lo.s32 	%r208, %r4, %r4;
	cvt.rn.f32.s32 	%f519, %r208;
	rcp.rn.f32 	%f520, %f519;
	mul.f32 	%f521, %f520, %f1341;
	mul.f32 	%f522, %f520, %f1340;
	mul.f32 	%f523, %f520, %f1339;
	mul.f32 	%f173, %f520, %f1344;
	mul.f32 	%f174, %f520, %f1343;
	mul.f32 	%f175, %f520, %f1342;
	mul.f32 	%f176, %f520, %f1347;
	mul.f32 	%f177, %f520, %f1346;
	mul.f32 	%f178, %f520, %f1345;
	mul.f32 	%f179, %f520, %f1350;
	mul.f32 	%f180, %f520, %f1349;
	mul.f32 	%f181, %f520, %f1348;
	mul.f32 	%f182, %f520, %f1353;
	mul.f32 	%f183, %f520, %f1352;
	mul.f32 	%f184, %f520, %f1351;
	mul.f32 	%f185, %f520, %f1356;
	mul.f32 	%f186, %f520, %f1355;
	mul.f32 	%f187, %f520, %f1354;
	mul.f32 	%f188, %f520, %f1359;
	mul.f32 	%f189, %f520, %f1358;
	mul.f32 	%f190, %f520, %f1357;
	mul.f32 	%f191, %f520, %f1362;
	mul.f32 	%f192, %f520, %f1361;
	mul.f32 	%f193, %f520, %f1360;
	mul.f32 	%f194, %f520, %f1365;
	mul.f32 	%f195, %f520, %f1364;
	mul.f32 	%f196, %f520, %f1363;
	mul.f32 	%f197, %f520, %f1368;
	mul.f32 	%f198, %f520, %f1367;
	mul.f32 	%f199, %f520, %f1366;
	fma.rn.f32 	%f524, %f520, %f1341, %f521;
	fma.rn.f32 	%f525, %f520, %f1340, %f522;
	fma.rn.f32 	%f526, %f520, %f1339, %f523;
	ld.const.u64 	%rd76, [params+504];
	cvt.rn.f32.u32 	%f527, %r6;
	cvt.rn.f32.u32 	%f528, %r5;
	tex.2d.v4.f32.f32 	{%f529, %f530, %f531, %f532}, [%rd76, {%f528, %f527}];
	mul.f32 	%f200, %f524, %f529;
	mul.f32 	%f201, %f525, %f530;
	mul.f32 	%f202, %f526, %f531;
	add.f32 	%f203, %f332, %f200;
	add.f32 	%f204, %f333, %f201;
	add.f32 	%f205, %f334, %f202;
	abs.f32 	%f533, %f203;
	setp.gtu.f32 	%p38, %f533, 0f7F800000;
	mov.f32 	%f1406, %f1405;
	mov.f32 	%f1407, %f1405;
	@%p38 bra 	$L__BB0_38;

	mov.f32 	%f1405, 0f00000000;
	abs.f32 	%f537, %f204;
	setp.gtu.f32 	%p39, %f537, 0f7F800000;
	@%p39 bra 	$L__BB0_38;

	mov.f32 	%f1405, 0f00000000;
	abs.f32 	%f541, %f205;
	setp.gtu.f32 	%p40, %f541, 0f7F800000;
	mov.f32 	%f1406, %f1405;
	mov.f32 	%f1407, %f1405;
	@%p40 bra 	$L__BB0_38;

	mov.f32 	%f1405, %f203;
	mov.f32 	%f1406, %f204;
	mov.f32 	%f1407, %f205;

$L__BB0_38:
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r209, %r49, 1;
	setp.eq.b32 	%p41, %r209, 1;
	mov.pred 	%p42, 0;
	xor.pred  	%p43, %p41, %p42;
	not.pred 	%p44, %p43;
	@%p44 bra 	$L__BB0_112;

	mov.f32 	%f543, 0f3E666666;
	cvt.rzi.f32.f32 	%f544, %f543;
	add.f32 	%f545, %f544, %f544;
	mov.f32 	%f546, 0f3EE66666;
	sub.f32 	%f547, %f546, %f545;
	abs.f32 	%f215, %f547;
	abs.f32 	%f216, %f1405;
	setp.lt.f32 	%p45, %f216, 0f00800000;
	mul.f32 	%f548, %f216, 0f4B800000;
	selp.f32 	%f549, %f548, %f216, %p45;
	selp.f32 	%f550, 0fC3170000, 0fC2FE0000, %p45;
	mov.b32 	%r210, %f549;
	and.b32  	%r211, %r210, 8388607;
	or.b32  	%r212, %r211, 1065353216;
	mov.b32 	%f551, %r212;
	shr.u32 	%r213, %r210, 23;
	cvt.rn.f32.u32 	%f552, %r213;
	add.f32 	%f553, %f550, %f552;
	setp.gt.f32 	%p46, %f551, 0f3FB504F3;
	mul.f32 	%f554, %f551, 0f3F000000;
	add.f32 	%f555, %f553, 0f3F800000;
	selp.f32 	%f556, %f555, %f553, %p46;
	selp.f32 	%f557, %f554, %f551, %p46;
	add.f32 	%f558, %f557, 0fBF800000;
	add.f32 	%f559, %f557, 0f3F800000;
	rcp.approx.ftz.f32 	%f560, %f559;
	add.f32 	%f561, %f558, %f558;
	mul.f32 	%f562, %f561, %f560;
	mul.f32 	%f563, %f562, %f562;
	mov.f32 	%f564, 0f3C4CAF63;
	mov.f32 	%f565, 0f3B18F0FE;
	fma.rn.f32 	%f566, %f565, %f563, %f564;
	mov.f32 	%f567, 0f3DAAAABD;
	fma.rn.f32 	%f568, %f566, %f563, %f567;
	mul.rn.f32 	%f569, %f568, %f563;
	mul.rn.f32 	%f570, %f569, %f562;
	sub.f32 	%f571, %f558, %f562;
	add.f32 	%f572, %f571, %f571;
	neg.f32 	%f573, %f562;
	fma.rn.f32 	%f574, %f573, %f558, %f572;
	mul.rn.f32 	%f575, %f560, %f574;
	add.f32 	%f576, %f570, %f562;
	sub.f32 	%f577, %f562, %f576;
	add.f32 	%f578, %f570, %f577;
	add.f32 	%f579, %f575, %f578;
	add.f32 	%f580, %f576, %f579;
	sub.f32 	%f581, %f576, %f580;
	add.f32 	%f582, %f579, %f581;
	mov.f32 	%f583, 0f3F317200;
	mul.rn.f32 	%f584, %f556, %f583;
	mov.f32 	%f585, 0f35BFBE8E;
	mul.rn.f32 	%f586, %f556, %f585;
	add.f32 	%f587, %f584, %f580;
	sub.f32 	%f588, %f584, %f587;
	add.f32 	%f589, %f580, %f588;
	add.f32 	%f590, %f582, %f589;
	add.f32 	%f591, %f586, %f590;
	add.f32 	%f592, %f587, %f591;
	sub.f32 	%f593, %f587, %f592;
	add.f32 	%f594, %f591, %f593;
	mul.rn.f32 	%f595, %f546, %f592;
	neg.f32 	%f596, %f595;
	fma.rn.f32 	%f597, %f546, %f592, %f596;
	fma.rn.f32 	%f598, %f546, %f594, %f597;
	mov.f32 	%f599, 0f00000000;
	fma.rn.f32 	%f600, %f599, %f592, %f598;
	add.rn.f32 	%f601, %f595, %f600;
	neg.f32 	%f602, %f601;
	add.rn.f32 	%f603, %f595, %f602;
	add.rn.f32 	%f604, %f603, %f600;
	mov.b32 	%r214, %f601;
	setp.eq.s32 	%p47, %r214, 1118925336;
	add.s32 	%r215, %r214, -1;
	mov.b32 	%f605, %r215;
	add.f32 	%f606, %f604, 0f37000000;
	selp.f32 	%f217, %f606, %f604, %p47;
	selp.f32 	%f607, %f605, %f601, %p47;
	mov.f32 	%f608, 0f3FB8AA3B;
	mul.rn.f32 	%f609, %f607, %f608;
	cvt.rzi.f32.f32 	%f610, %f609;
	abs.f32 	%f611, %f610;
	setp.gt.f32 	%p48, %f611, 0f42FC0000;
	mov.b32 	%r216, %f610;
	and.b32  	%r217, %r216, -2147483648;
	or.b32  	%r218, %r217, 1123811328;
	mov.b32 	%f612, %r218;
	selp.f32 	%f613, %f612, %f610, %p48;
	mov.f32 	%f614, 0fBF317218;
	fma.rn.f32 	%f615, %f613, %f614, %f607;
	mov.f32 	%f616, 0f3102E308;
	fma.rn.f32 	%f617, %f613, %f616, %f615;
	mul.f32 	%f618, %f617, 0f3FB8AA3B;
	add.f32 	%f619, %f613, 0f4B40007F;
	mov.b32 	%r219, %f619;
	shl.b32 	%r220, %r219, 23;
	mov.b32 	%f620, %r220;
	ex2.approx.ftz.f32 	%f621, %f618;
	mul.f32 	%f218, %f621, %f620;
	setp.eq.f32 	%p49, %f218, 0f7F800000;
	mov.f32 	%f1408, 0f7F800000;
	@%p49 bra 	$L__BB0_41;

	fma.rn.f32 	%f1408, %f218, %f217, %f218;

$L__BB0_41:
	setp.lt.f32 	%p50, %f1405, 0f00000000;
	setp.eq.f32 	%p51, %f215, 0f3F800000;
	and.pred  	%p1, %p50, %p51;
	setp.eq.f32 	%p52, %f1405, 0f00000000;
	@%p52 bra 	$L__BB0_45;
	bra.uni 	$L__BB0_42;

$L__BB0_45:
	add.f32 	%f626, %f1405, %f1405;
	selp.f32 	%f1410, %f626, 0f00000000, %p51;
	bra.uni 	$L__BB0_46;

$L__BB0_151:
	mov.f32 	%f1218, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs192, %f1218;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs191, %f1218;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs190, %f1218;}

	// end inline asm
	mov.u16 	%rs193, 0;
	st.global.v4.u16 	[%rd27], {%rs190, %rs191, %rs192, %rs193};

$L__BB0_152:
	ld.const.u64 	%rd130, [params+272];
	cvta.to.global.u64 	%rd131, %rd130;
	ld.const.u32 	%r337, [params+264];
	mad.lo.s32 	%r338, %r337, %r6, %r5;
	mul.wide.u32 	%rd132, %r338, 8;
	add.s64 	%rd28, %rd131, %rd132;
	@%p155 bra 	$L__BB0_154;

	ld.global.v4.u16 	{%rs200, %rs201, %rs202, %rs203}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1219, %rs200;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1220, %rs201;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1221, %rs202;}

	// end inline asm
	add.f32 	%f1222, %f1219, 0f00000000;
	add.f32 	%f1223, %f1220, 0f00000000;
	add.f32 	%f1224, %f1221, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs199, %f1224;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs198, %f1223;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs197, %f1222;}

	// end inline asm
	mov.u16 	%rs204, 0;
	st.global.v4.u16 	[%rd28], {%rs197, %rs198, %rs199, %rs204};
	bra.uni 	$L__BB0_155;

$L__BB0_154:
	mov.f32 	%f1227, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs207, %f1227;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs206, %f1227;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs205, %f1227;}

	// end inline asm
	mov.u16 	%rs208, 0;
	st.global.v4.u16 	[%rd28], {%rs205, %rs206, %rs207, %rs208};

$L__BB0_155:
	ld.const.u64 	%rd133, [params+288];
	cvta.to.global.u64 	%rd134, %rd133;
	ld.const.u32 	%r339, [params+280];
	mad.lo.s32 	%r340, %r339, %r6, %r5;
	mul.wide.u32 	%rd135, %r340, 8;
	add.s64 	%rd29, %rd134, %rd135;
	@%p155 bra 	$L__BB0_157;

	ld.global.v4.u16 	{%rs215, %rs216, %rs217, %rs218}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1228, %rs215;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1229, %rs216;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1230, %rs217;}

	// end inline asm
	add.f32 	%f1231, %f1228, 0f00000000;
	add.f32 	%f1232, %f1229, 0f00000000;
	add.f32 	%f1233, %f1230, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs214, %f1233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs213, %f1232;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs212, %f1231;}

	// end inline asm
	mov.u16 	%rs219, 0;
	st.global.v4.u16 	[%rd29], {%rs212, %rs213, %rs214, %rs219};
	bra.uni 	$L__BB0_158;

$L__BB0_157:
	mov.f32 	%f1236, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs222, %f1236;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs221, %f1236;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs220, %f1236;}

	// end inline asm
	mov.u16 	%rs223, 0;
	st.global.v4.u16 	[%rd29], {%rs220, %rs221, %rs222, %rs223};

$L__BB0_158:
	ld.const.u64 	%rd136, [params+304];
	cvta.to.global.u64 	%rd137, %rd136;
	ld.const.u32 	%r341, [params+296];
	mad.lo.s32 	%r342, %r341, %r6, %r5;
	mul.wide.u32 	%rd138, %r342, 8;
	add.s64 	%rd30, %rd137, %rd138;
	@%p155 bra 	$L__BB0_160;

	ld.global.v4.u16 	{%rs230, %rs231, %rs232, %rs233}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1237, %rs230;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1238, %rs231;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1239, %rs232;}

	// end inline asm
	add.f32 	%f1240, %f1237, 0f00000000;
	add.f32 	%f1241, %f1238, 0f00000000;
	add.f32 	%f1242, %f1239, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs229, %f1242;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs228, %f1241;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs227, %f1240;}

	// end inline asm
	mov.u16 	%rs234, 0;
	st.global.v4.u16 	[%rd30], {%rs227, %rs228, %rs229, %rs234};
	bra.uni 	$L__BB0_161;

$L__BB0_160:
	mov.f32 	%f1245, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs237, %f1245;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs236, %f1245;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs235, %f1245;}

	// end inline asm
	mov.u16 	%rs238, 0;
	st.global.v4.u16 	[%rd30], {%rs235, %rs236, %rs237, %rs238};

$L__BB0_161:
	ld.const.u64 	%rd139, [params+320];
	cvta.to.global.u64 	%rd140, %rd139;
	ld.const.u32 	%r343, [params+312];
	mad.lo.s32 	%r344, %r343, %r6, %r5;
	mul.wide.u32 	%rd141, %r344, 8;
	add.s64 	%rd31, %rd140, %rd141;
	@%p155 bra 	$L__BB0_163;

	ld.global.v4.u16 	{%rs245, %rs246, %rs247, %rs248}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1246, %rs245;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1247, %rs246;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1248, %rs247;}

	// end inline asm
	add.f32 	%f1249, %f1246, 0f00000000;
	add.f32 	%f1250, %f1247, 0f00000000;
	add.f32 	%f1251, %f1248, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs244, %f1251;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs243, %f1250;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs242, %f1249;}

	// end inline asm
	mov.u16 	%rs249, 0;
	st.global.v4.u16 	[%rd31], {%rs242, %rs243, %rs244, %rs249};
	bra.uni 	$L__BB0_164;

$L__BB0_163:
	mov.f32 	%f1254, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs252, %f1254;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs251, %f1254;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs250, %f1254;}

	// end inline asm
	mov.u16 	%rs253, 0;
	st.global.v4.u16 	[%rd31], {%rs250, %rs251, %rs252, %rs253};

$L__BB0_164:
	ld.const.u64 	%rd142, [params+336];
	cvta.to.global.u64 	%rd143, %rd142;
	ld.const.u32 	%r345, [params+328];
	mad.lo.s32 	%r346, %r345, %r6, %r5;
	mul.wide.u32 	%rd144, %r346, 8;
	add.s64 	%rd32, %rd143, %rd144;
	@%p155 bra 	$L__BB0_166;

	ld.global.v4.u16 	{%rs260, %rs261, %rs262, %rs263}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1255, %rs260;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1256, %rs261;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1257, %rs262;}

	// end inline asm
	add.f32 	%f1258, %f1255, 0f00000000;
	add.f32 	%f1259, %f1256, 0f00000000;
	add.f32 	%f1260, %f1257, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs259, %f1260;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs258, %f1259;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs257, %f1258;}

	// end inline asm
	mov.u16 	%rs264, 0;
	st.global.v4.u16 	[%rd32], {%rs257, %rs258, %rs259, %rs264};
	bra.uni 	$L__BB0_167;

$L__BB0_166:
	mov.f32 	%f1263, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs267, %f1263;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs266, %f1263;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs265, %f1263;}

	// end inline asm
	mov.u16 	%rs268, 0;
	st.global.v4.u16 	[%rd32], {%rs265, %rs266, %rs267, %rs268};

$L__BB0_167:
	ld.const.u64 	%rd145, [params+352];
	cvta.to.global.u64 	%rd146, %rd145;
	ld.const.u32 	%r347, [params+344];
	mad.lo.s32 	%r348, %r347, %r6, %r5;
	mul.wide.u32 	%rd147, %r348, 8;
	add.s64 	%rd33, %rd146, %rd147;
	@%p155 bra 	$L__BB0_169;

	ld.global.v4.u16 	{%rs275, %rs276, %rs277, %rs278}, [%rd33];
	// begin inline asm
	{  cvt.f32.f16 %f1264, %rs275;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1265, %rs276;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1266, %rs277;}

	// end inline asm
	add.f32 	%f1267, %f1264, 0f00000000;
	add.f32 	%f1268, %f1265, 0f00000000;
	add.f32 	%f1269, %f1266, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs274, %f1269;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs273, %f1268;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs272, %f1267;}

	// end inline asm
	mov.u16 	%rs279, 0;
	st.global.v4.u16 	[%rd33], {%rs272, %rs273, %rs274, %rs279};
	bra.uni 	$L__BB0_170;

$L__BB0_169:
	mov.f32 	%f1272, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs282, %f1272;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs281, %f1272;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs280, %f1272;}

	// end inline asm
	mov.u16 	%rs283, 0;
	st.global.v4.u16 	[%rd33], {%rs280, %rs281, %rs282, %rs283};

$L__BB0_170:
	ld.const.u64 	%rd148, [params+368];
	cvta.to.global.u64 	%rd149, %rd148;
	ld.const.u32 	%r349, [params+360];
	mad.lo.s32 	%r350, %r349, %r6, %r5;
	mul.wide.u32 	%rd150, %r350, 8;
	add.s64 	%rd34, %rd149, %rd150;
	@%p155 bra 	$L__BB0_172;

	ld.global.v4.u16 	{%rs290, %rs291, %rs292, %rs293}, [%rd34];
	// begin inline asm
	{  cvt.f32.f16 %f1273, %rs290;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1274, %rs291;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1275, %rs292;}

	// end inline asm
	add.f32 	%f1276, %f1273, 0f00000000;
	add.f32 	%f1277, %f1274, 0f00000000;
	add.f32 	%f1278, %f1275, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs289, %f1278;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs288, %f1277;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs287, %f1276;}

	// end inline asm
	mov.u16 	%rs294, 0;
	st.global.v4.u16 	[%rd34], {%rs287, %rs288, %rs289, %rs294};
	bra.uni 	$L__BB0_173;

$L__BB0_172:
	mov.f32 	%f1281, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs297, %f1281;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs296, %f1281;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs295, %f1281;}

	// end inline asm
	mov.u16 	%rs298, 0;
	st.global.v4.u16 	[%rd34], {%rs295, %rs296, %rs297, %rs298};

$L__BB0_173:
	ld.const.u64 	%rd151, [params+384];
	cvta.to.global.u64 	%rd152, %rd151;
	ld.const.u32 	%r351, [params+376];
	mad.lo.s32 	%r352, %r351, %r6, %r5;
	mul.wide.u32 	%rd153, %r352, 8;
	add.s64 	%rd35, %rd152, %rd153;
	@%p155 bra 	$L__BB0_175;

	ld.global.v4.u16 	{%rs305, %rs306, %rs307, %rs308}, [%rd35];
	// begin inline asm
	{  cvt.f32.f16 %f1282, %rs305;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1283, %rs306;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1284, %rs307;}

	// end inline asm
	add.f32 	%f1285, %f1282, 0f00000000;
	add.f32 	%f1286, %f1283, 0f00000000;
	add.f32 	%f1287, %f1284, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs304, %f1287;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs303, %f1286;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs302, %f1285;}

	// end inline asm
	mov.u16 	%rs309, 0;
	st.global.v4.u16 	[%rd35], {%rs302, %rs303, %rs304, %rs309};
	bra.uni 	$L__BB0_176;

$L__BB0_175:
	mov.f32 	%f1290, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs312, %f1290;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs311, %f1290;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs310, %f1290;}

	// end inline asm
	mov.u16 	%rs313, 0;
	st.global.v4.u16 	[%rd35], {%rs310, %rs311, %rs312, %rs313};
	bra.uni 	$L__BB0_176;

$L__BB0_42:
	mov.b32 	%r221, %f1408;
	xor.b32  	%r222, %r221, -2147483648;
	mov.b32 	%f622, %r222;
	selp.f32 	%f1410, %f622, %f1408, %p1;
	setp.geu.f32 	%p53, %f1405, 0f00000000;
	@%p53 bra 	$L__BB0_46;

	mov.f32 	%f623, 0f3EE66666;
	cvt.rzi.f32.f32 	%f624, %f623;
	setp.eq.f32 	%p54, %f624, 0f3EE66666;
	@%p54 bra 	$L__BB0_46;

	mov.f32 	%f1410, 0f7FFFFFFF;

$L__BB0_46:
	add.f32 	%f627, %f216, 0f3EE66666;
	mov.b32 	%r223, %f627;
	setp.lt.s32 	%p56, %r223, 2139095040;
	@%p56 bra 	$L__BB0_51;

	setp.gtu.f32 	%p57, %f216, 0f7F800000;
	@%p57 bra 	$L__BB0_50;
	bra.uni 	$L__BB0_48;

$L__BB0_50:
	add.f32 	%f1410, %f1405, 0f3EE66666;
	bra.uni 	$L__BB0_51;

$L__BB0_48:
	setp.neu.f32 	%p58, %f216, 0f7F800000;
	@%p58 bra 	$L__BB0_51;

	selp.f32 	%f1410, 0fFF800000, 0f7F800000, %p1;

$L__BB0_51:
	setp.eq.f32 	%p59, %f1405, 0f3F800000;
	selp.f32 	%f227, 0f3F800000, %f1410, %p59;
	abs.f32 	%f228, %f1406;
	setp.lt.f32 	%p60, %f228, 0f00800000;
	mul.f32 	%f629, %f228, 0f4B800000;
	selp.f32 	%f630, %f629, %f228, %p60;
	selp.f32 	%f631, 0fC3170000, 0fC2FE0000, %p60;
	mov.b32 	%r224, %f630;
	and.b32  	%r225, %r224, 8388607;
	or.b32  	%r226, %r225, 1065353216;
	mov.b32 	%f632, %r226;
	shr.u32 	%r227, %r224, 23;
	cvt.rn.f32.u32 	%f633, %r227;
	add.f32 	%f634, %f631, %f633;
	setp.gt.f32 	%p61, %f632, 0f3FB504F3;
	mul.f32 	%f635, %f632, 0f3F000000;
	add.f32 	%f636, %f634, 0f3F800000;
	selp.f32 	%f637, %f636, %f634, %p61;
	selp.f32 	%f638, %f635, %f632, %p61;
	add.f32 	%f639, %f638, 0fBF800000;
	add.f32 	%f640, %f638, 0f3F800000;
	rcp.approx.ftz.f32 	%f641, %f640;
	add.f32 	%f642, %f639, %f639;
	mul.f32 	%f643, %f642, %f641;
	mul.f32 	%f644, %f643, %f643;
	mov.f32 	%f645, 0f3C4CAF63;
	mov.f32 	%f646, 0f3B18F0FE;
	fma.rn.f32 	%f647, %f646, %f644, %f645;
	mov.f32 	%f648, 0f3DAAAABD;
	fma.rn.f32 	%f649, %f647, %f644, %f648;
	mul.rn.f32 	%f650, %f649, %f644;
	mul.rn.f32 	%f651, %f650, %f643;
	sub.f32 	%f652, %f639, %f643;
	add.f32 	%f653, %f652, %f652;
	neg.f32 	%f654, %f643;
	fma.rn.f32 	%f655, %f654, %f639, %f653;
	mul.rn.f32 	%f656, %f641, %f655;
	add.f32 	%f657, %f651, %f643;
	sub.f32 	%f658, %f643, %f657;
	add.f32 	%f659, %f651, %f658;
	add.f32 	%f660, %f656, %f659;
	add.f32 	%f661, %f657, %f660;
	sub.f32 	%f662, %f657, %f661;
	add.f32 	%f663, %f660, %f662;
	mov.f32 	%f664, 0f3F317200;
	mul.rn.f32 	%f665, %f637, %f664;
	mov.f32 	%f666, 0f35BFBE8E;
	mul.rn.f32 	%f667, %f637, %f666;
	add.f32 	%f668, %f665, %f661;
	sub.f32 	%f669, %f665, %f668;
	add.f32 	%f670, %f661, %f669;
	add.f32 	%f671, %f663, %f670;
	add.f32 	%f672, %f667, %f671;
	add.f32 	%f673, %f668, %f672;
	sub.f32 	%f674, %f668, %f673;
	add.f32 	%f675, %f672, %f674;
	mov.f32 	%f676, 0f3EE66666;
	mul.rn.f32 	%f677, %f676, %f673;
	neg.f32 	%f678, %f677;
	fma.rn.f32 	%f679, %f676, %f673, %f678;
	fma.rn.f32 	%f680, %f676, %f675, %f679;
	mov.f32 	%f681, 0f00000000;
	fma.rn.f32 	%f682, %f681, %f673, %f680;
	add.rn.f32 	%f683, %f677, %f682;
	neg.f32 	%f684, %f683;
	add.rn.f32 	%f685, %f677, %f684;
	add.rn.f32 	%f686, %f685, %f682;
	mov.b32 	%r228, %f683;
	setp.eq.s32 	%p62, %r228, 1118925336;
	add.s32 	%r229, %r228, -1;
	mov.b32 	%f687, %r229;
	add.f32 	%f688, %f686, 0f37000000;
	selp.f32 	%f229, %f688, %f686, %p62;
	selp.f32 	%f689, %f687, %f683, %p62;
	mov.f32 	%f690, 0f3FB8AA3B;
	mul.rn.f32 	%f691, %f689, %f690;
	cvt.rzi.f32.f32 	%f692, %f691;
	abs.f32 	%f693, %f692;
	setp.gt.f32 	%p63, %f693, 0f42FC0000;
	mov.b32 	%r230, %f692;
	and.b32  	%r231, %r230, -2147483648;
	or.b32  	%r232, %r231, 1123811328;
	mov.b32 	%f694, %r232;
	selp.f32 	%f695, %f694, %f692, %p63;
	mov.f32 	%f696, 0fBF317218;
	fma.rn.f32 	%f697, %f695, %f696, %f689;
	mov.f32 	%f698, 0f3102E308;
	fma.rn.f32 	%f699, %f695, %f698, %f697;
	mul.f32 	%f700, %f699, 0f3FB8AA3B;
	add.f32 	%f701, %f695, 0f4B40007F;
	mov.b32 	%r233, %f701;
	shl.b32 	%r234, %r233, 23;
	mov.b32 	%f702, %r234;
	ex2.approx.ftz.f32 	%f703, %f700;
	mul.f32 	%f230, %f703, %f702;
	setp.eq.f32 	%p64, %f230, 0f7F800000;
	mov.f32 	%f1411, 0f7F800000;
	@%p64 bra 	$L__BB0_53;

	fma.rn.f32 	%f1411, %f230, %f229, %f230;

$L__BB0_53:
	setp.lt.f32 	%p65, %f1406, 0f00000000;
	and.pred  	%p2, %p65, %p51;
	setp.eq.f32 	%p67, %f1406, 0f00000000;
	@%p67 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f708, %f1406, %f1406;
	selp.f32 	%f1413, %f708, 0f00000000, %p51;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r235, %f1411;
	xor.b32  	%r236, %r235, -2147483648;
	mov.b32 	%f704, %r236;
	selp.f32 	%f1413, %f704, %f1411, %p2;
	setp.geu.f32 	%p68, %f1406, 0f00000000;
	@%p68 bra 	$L__BB0_58;

	mov.f32 	%f705, 0f3EE66666;
	cvt.rzi.f32.f32 	%f706, %f705;
	setp.eq.f32 	%p69, %f706, 0f3EE66666;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f1413, 0f7FFFFFFF;

$L__BB0_58:
	add.f32 	%f709, %f228, 0f3EE66666;
	mov.b32 	%r237, %f709;
	setp.lt.s32 	%p71, %r237, 2139095040;
	@%p71 bra 	$L__BB0_63;

	setp.gtu.f32 	%p72, %f228, 0f7F800000;
	@%p72 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1413, %f1406, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	setp.neu.f32 	%p73, %f228, 0f7F800000;
	@%p73 bra 	$L__BB0_63;

	selp.f32 	%f1413, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p74, %f1406, 0f3F800000;
	selp.f32 	%f239, 0f3F800000, %f1413, %p74;
	abs.f32 	%f240, %f1407;
	setp.lt.f32 	%p75, %f240, 0f00800000;
	mul.f32 	%f711, %f240, 0f4B800000;
	selp.f32 	%f712, %f711, %f240, %p75;
	selp.f32 	%f713, 0fC3170000, 0fC2FE0000, %p75;
	mov.b32 	%r238, %f712;
	and.b32  	%r239, %r238, 8388607;
	or.b32  	%r240, %r239, 1065353216;
	mov.b32 	%f714, %r240;
	shr.u32 	%r241, %r238, 23;
	cvt.rn.f32.u32 	%f715, %r241;
	add.f32 	%f716, %f713, %f715;
	setp.gt.f32 	%p76, %f714, 0f3FB504F3;
	mul.f32 	%f717, %f714, 0f3F000000;
	add.f32 	%f718, %f716, 0f3F800000;
	selp.f32 	%f719, %f718, %f716, %p76;
	selp.f32 	%f720, %f717, %f714, %p76;
	add.f32 	%f721, %f720, 0fBF800000;
	add.f32 	%f722, %f720, 0f3F800000;
	rcp.approx.ftz.f32 	%f723, %f722;
	add.f32 	%f724, %f721, %f721;
	mul.f32 	%f725, %f724, %f723;
	mul.f32 	%f726, %f725, %f725;
	mov.f32 	%f727, 0f3C4CAF63;
	mov.f32 	%f728, 0f3B18F0FE;
	fma.rn.f32 	%f729, %f728, %f726, %f727;
	mov.f32 	%f730, 0f3DAAAABD;
	fma.rn.f32 	%f731, %f729, %f726, %f730;
	mul.rn.f32 	%f732, %f731, %f726;
	mul.rn.f32 	%f733, %f732, %f725;
	sub.f32 	%f734, %f721, %f725;
	add.f32 	%f735, %f734, %f734;
	neg.f32 	%f736, %f725;
	fma.rn.f32 	%f737, %f736, %f721, %f735;
	mul.rn.f32 	%f738, %f723, %f737;
	add.f32 	%f739, %f733, %f725;
	sub.f32 	%f740, %f725, %f739;
	add.f32 	%f741, %f733, %f740;
	add.f32 	%f742, %f738, %f741;
	add.f32 	%f743, %f739, %f742;
	sub.f32 	%f744, %f739, %f743;
	add.f32 	%f745, %f742, %f744;
	mov.f32 	%f746, 0f3F317200;
	mul.rn.f32 	%f747, %f719, %f746;
	mov.f32 	%f748, 0f35BFBE8E;
	mul.rn.f32 	%f749, %f719, %f748;
	add.f32 	%f750, %f747, %f743;
	sub.f32 	%f751, %f747, %f750;
	add.f32 	%f752, %f743, %f751;
	add.f32 	%f753, %f745, %f752;
	add.f32 	%f754, %f749, %f753;
	add.f32 	%f755, %f750, %f754;
	sub.f32 	%f756, %f750, %f755;
	add.f32 	%f757, %f754, %f756;
	mov.f32 	%f758, 0f3EE66666;
	mul.rn.f32 	%f759, %f758, %f755;
	neg.f32 	%f760, %f759;
	fma.rn.f32 	%f761, %f758, %f755, %f760;
	fma.rn.f32 	%f762, %f758, %f757, %f761;
	mov.f32 	%f763, 0f00000000;
	fma.rn.f32 	%f764, %f763, %f755, %f762;
	add.rn.f32 	%f765, %f759, %f764;
	neg.f32 	%f766, %f765;
	add.rn.f32 	%f767, %f759, %f766;
	add.rn.f32 	%f768, %f767, %f764;
	mov.b32 	%r242, %f765;
	setp.eq.s32 	%p77, %r242, 1118925336;
	add.s32 	%r243, %r242, -1;
	mov.b32 	%f769, %r243;
	add.f32 	%f770, %f768, 0f37000000;
	selp.f32 	%f241, %f770, %f768, %p77;
	selp.f32 	%f771, %f769, %f765, %p77;
	mov.f32 	%f772, 0f3FB8AA3B;
	mul.rn.f32 	%f773, %f771, %f772;
	cvt.rzi.f32.f32 	%f774, %f773;
	abs.f32 	%f775, %f774;
	setp.gt.f32 	%p78, %f775, 0f42FC0000;
	mov.b32 	%r244, %f774;
	and.b32  	%r245, %r244, -2147483648;
	or.b32  	%r246, %r245, 1123811328;
	mov.b32 	%f776, %r246;
	selp.f32 	%f777, %f776, %f774, %p78;
	mov.f32 	%f778, 0fBF317218;
	fma.rn.f32 	%f779, %f777, %f778, %f771;
	mov.f32 	%f780, 0f3102E308;
	fma.rn.f32 	%f781, %f777, %f780, %f779;
	mul.f32 	%f782, %f781, 0f3FB8AA3B;
	add.f32 	%f783, %f777, 0f4B40007F;
	mov.b32 	%r247, %f783;
	shl.b32 	%r248, %r247, 23;
	mov.b32 	%f784, %r248;
	ex2.approx.ftz.f32 	%f785, %f782;
	mul.f32 	%f242, %f785, %f784;
	setp.eq.f32 	%p79, %f242, 0f7F800000;
	mov.f32 	%f1414, 0f7F800000;
	@%p79 bra 	$L__BB0_65;

	fma.rn.f32 	%f1414, %f242, %f241, %f242;

$L__BB0_65:
	setp.lt.f32 	%p80, %f1407, 0f00000000;
	and.pred  	%p3, %p80, %p51;
	setp.eq.f32 	%p82, %f1407, 0f00000000;
	@%p82 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f790, %f1407, %f1407;
	selp.f32 	%f1416, %f790, 0f00000000, %p51;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r249, %f1414;
	xor.b32  	%r250, %r249, -2147483648;
	mov.b32 	%f786, %r250;
	selp.f32 	%f1416, %f786, %f1414, %p3;
	setp.geu.f32 	%p83, %f1407, 0f00000000;
	@%p83 bra 	$L__BB0_70;

	mov.f32 	%f787, 0f3EE66666;
	cvt.rzi.f32.f32 	%f788, %f787;
	setp.eq.f32 	%p84, %f788, 0f3EE66666;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f1416, 0f7FFFFFFF;

$L__BB0_70:
	add.f32 	%f791, %f240, 0f3EE66666;
	mov.b32 	%r251, %f791;
	setp.lt.s32 	%p86, %r251, 2139095040;
	@%p86 bra 	$L__BB0_75;

	setp.gtu.f32 	%p87, %f240, 0f7F800000;
	@%p87 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1416, %f1407, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	setp.neu.f32 	%p88, %f240, 0f7F800000;
	@%p88 bra 	$L__BB0_75;

	selp.f32 	%f1416, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p89, %f1407, 0f3F800000;
	mov.f32 	%f793, 0f3F800000;
	selp.f32 	%f794, 0f3F800000, %f1416, %p89;
	min.f32 	%f795, %f227, %f793;
	mov.f32 	%f796, 0f00000000;
	max.f32 	%f251, %f796, %f795;
	min.f32 	%f797, %f239, %f793;
	max.f32 	%f252, %f796, %f797;
	min.f32 	%f798, %f794, %f793;
	max.f32 	%f253, %f796, %f798;
	mov.f32 	%f802, 0f3ED55555;
	abs.f32 	%f255, %f251;
	setp.lt.f32 	%p90, %f255, 0f00800000;
	mul.f32 	%f804, %f255, 0f4B800000;
	selp.f32 	%f805, %f804, %f255, %p90;
	selp.f32 	%f806, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r254, %f805;
	and.b32  	%r255, %r254, 8388607;
	or.b32  	%r256, %r255, 1065353216;
	mov.b32 	%f807, %r256;
	shr.u32 	%r257, %r254, 23;
	cvt.rn.f32.u32 	%f808, %r257;
	add.f32 	%f809, %f806, %f808;
	setp.gt.f32 	%p91, %f807, 0f3FB504F3;
	mul.f32 	%f810, %f807, 0f3F000000;
	add.f32 	%f811, %f809, 0f3F800000;
	selp.f32 	%f812, %f811, %f809, %p91;
	selp.f32 	%f813, %f810, %f807, %p91;
	add.f32 	%f814, %f813, 0fBF800000;
	add.f32 	%f815, %f813, 0f3F800000;
	rcp.approx.ftz.f32 	%f816, %f815;
	add.f32 	%f817, %f814, %f814;
	mul.f32 	%f818, %f817, %f816;
	mul.f32 	%f819, %f818, %f818;
	mov.f32 	%f820, 0f3C4CAF63;
	mov.f32 	%f821, 0f3B18F0FE;
	fma.rn.f32 	%f822, %f821, %f819, %f820;
	mov.f32 	%f823, 0f3DAAAABD;
	fma.rn.f32 	%f824, %f822, %f819, %f823;
	mul.rn.f32 	%f825, %f824, %f819;
	mul.rn.f32 	%f826, %f825, %f818;
	sub.f32 	%f827, %f814, %f818;
	add.f32 	%f828, %f827, %f827;
	neg.f32 	%f829, %f818;
	fma.rn.f32 	%f830, %f829, %f814, %f828;
	mul.rn.f32 	%f831, %f816, %f830;
	add.f32 	%f832, %f826, %f818;
	sub.f32 	%f833, %f818, %f832;
	add.f32 	%f834, %f826, %f833;
	add.f32 	%f835, %f831, %f834;
	add.f32 	%f836, %f832, %f835;
	sub.f32 	%f837, %f832, %f836;
	add.f32 	%f838, %f835, %f837;
	mov.f32 	%f839, 0f3F317200;
	mul.rn.f32 	%f840, %f812, %f839;
	mov.f32 	%f841, 0f35BFBE8E;
	mul.rn.f32 	%f842, %f812, %f841;
	add.f32 	%f843, %f840, %f836;
	sub.f32 	%f844, %f840, %f843;
	add.f32 	%f845, %f836, %f844;
	add.f32 	%f846, %f838, %f845;
	add.f32 	%f847, %f842, %f846;
	add.f32 	%f848, %f843, %f847;
	sub.f32 	%f849, %f843, %f848;
	add.f32 	%f850, %f847, %f849;
	mul.rn.f32 	%f851, %f802, %f848;
	neg.f32 	%f852, %f851;
	fma.rn.f32 	%f853, %f802, %f848, %f852;
	fma.rn.f32 	%f854, %f802, %f850, %f853;
	fma.rn.f32 	%f855, %f796, %f848, %f854;
	add.rn.f32 	%f856, %f851, %f855;
	neg.f32 	%f857, %f856;
	add.rn.f32 	%f858, %f851, %f857;
	add.rn.f32 	%f859, %f858, %f855;
	mov.b32 	%r258, %f856;
	setp.eq.s32 	%p92, %r258, 1118925336;
	add.s32 	%r259, %r258, -1;
	mov.b32 	%f860, %r259;
	add.f32 	%f861, %f859, 0f37000000;
	selp.f32 	%f256, %f861, %f859, %p92;
	selp.f32 	%f862, %f860, %f856, %p92;
	mov.f32 	%f863, 0f3FB8AA3B;
	mul.rn.f32 	%f864, %f862, %f863;
	cvt.rzi.f32.f32 	%f865, %f864;
	abs.f32 	%f866, %f865;
	setp.gt.f32 	%p93, %f866, 0f42FC0000;
	mov.b32 	%r260, %f865;
	and.b32  	%r261, %r260, -2147483648;
	or.b32  	%r262, %r261, 1123811328;
	mov.b32 	%f867, %r262;
	selp.f32 	%f868, %f867, %f865, %p93;
	mov.f32 	%f869, 0fBF317218;
	fma.rn.f32 	%f870, %f868, %f869, %f862;
	mov.f32 	%f871, 0f3102E308;
	fma.rn.f32 	%f872, %f868, %f871, %f870;
	mul.f32 	%f873, %f872, 0f3FB8AA3B;
	add.f32 	%f874, %f868, 0f4B40007F;
	mov.b32 	%r263, %f874;
	shl.b32 	%r264, %r263, 23;
	mov.b32 	%f875, %r264;
	ex2.approx.ftz.f32 	%f876, %f873;
	mul.f32 	%f257, %f876, %f875;
	setp.eq.f32 	%p94, %f257, 0f7F800000;
	mov.f32 	%f1417, 0f7F800000;
	@%p94 bra 	$L__BB0_77;

	fma.rn.f32 	%f1417, %f257, %f256, %f257;

$L__BB0_77:
	mov.f32 	%f1305, 0f3E555555;
	cvt.rzi.f32.f32 	%f1304, %f1305;
	add.f32 	%f1303, %f1304, %f1304;
	mov.f32 	%f1302, 0f3ED55555;
	sub.f32 	%f1301, %f1302, %f1303;
	abs.f32 	%f1300, %f1301;
	setp.lt.f32 	%p95, %f251, 0f00000000;
	setp.eq.f32 	%p96, %f1300, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f251, 0f00000000;
	@%p97 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f881, %f251, %f251;
	selp.f32 	%f1419, %f881, 0f00000000, %p96;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r265, %f1417;
	xor.b32  	%r266, %r265, -2147483648;
	mov.b32 	%f877, %r266;
	selp.f32 	%f1419, %f877, %f1417, %p4;
	setp.geu.f32 	%p98, %f251, 0f00000000;
	@%p98 bra 	$L__BB0_82;

	mov.f32 	%f878, 0f3ED55555;
	cvt.rzi.f32.f32 	%f879, %f878;
	setp.eq.f32 	%p99, %f879, 0f3ED55555;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f1419, 0f7FFFFFFF;

$L__BB0_82:
	add.f32 	%f882, %f255, 0f3ED55555;
	mov.b32 	%r267, %f882;
	setp.lt.s32 	%p101, %r267, 2139095040;
	@%p101 bra 	$L__BB0_87;

	setp.gtu.f32 	%p102, %f255, 0f7F800000;
	@%p102 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1419, %f251, 0f3ED55555;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	setp.neu.f32 	%p103, %f255, 0f7F800000;
	@%p103 bra 	$L__BB0_87;

	selp.f32 	%f1419, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	abs.f32 	%f266, %f252;
	setp.lt.f32 	%p104, %f266, 0f00800000;
	mul.f32 	%f884, %f266, 0f4B800000;
	selp.f32 	%f885, %f884, %f266, %p104;
	selp.f32 	%f886, 0fC3170000, 0fC2FE0000, %p104;
	mov.b32 	%r268, %f885;
	and.b32  	%r269, %r268, 8388607;
	or.b32  	%r270, %r269, 1065353216;
	mov.b32 	%f887, %r270;
	shr.u32 	%r271, %r268, 23;
	cvt.rn.f32.u32 	%f888, %r271;
	add.f32 	%f889, %f886, %f888;
	setp.gt.f32 	%p105, %f887, 0f3FB504F3;
	mul.f32 	%f890, %f887, 0f3F000000;
	add.f32 	%f891, %f889, 0f3F800000;
	selp.f32 	%f892, %f891, %f889, %p105;
	selp.f32 	%f893, %f890, %f887, %p105;
	add.f32 	%f894, %f893, 0fBF800000;
	add.f32 	%f895, %f893, 0f3F800000;
	rcp.approx.ftz.f32 	%f896, %f895;
	add.f32 	%f897, %f894, %f894;
	mul.f32 	%f898, %f897, %f896;
	mul.f32 	%f899, %f898, %f898;
	mov.f32 	%f900, 0f3C4CAF63;
	mov.f32 	%f901, 0f3B18F0FE;
	fma.rn.f32 	%f902, %f901, %f899, %f900;
	mov.f32 	%f903, 0f3DAAAABD;
	fma.rn.f32 	%f904, %f902, %f899, %f903;
	mul.rn.f32 	%f905, %f904, %f899;
	mul.rn.f32 	%f906, %f905, %f898;
	sub.f32 	%f907, %f894, %f898;
	add.f32 	%f908, %f907, %f907;
	neg.f32 	%f909, %f898;
	fma.rn.f32 	%f910, %f909, %f894, %f908;
	mul.rn.f32 	%f911, %f896, %f910;
	add.f32 	%f912, %f906, %f898;
	sub.f32 	%f913, %f898, %f912;
	add.f32 	%f914, %f906, %f913;
	add.f32 	%f915, %f911, %f914;
	add.f32 	%f916, %f912, %f915;
	sub.f32 	%f917, %f912, %f916;
	add.f32 	%f918, %f915, %f917;
	mov.f32 	%f919, 0f3F317200;
	mul.rn.f32 	%f920, %f892, %f919;
	mov.f32 	%f921, 0f35BFBE8E;
	mul.rn.f32 	%f922, %f892, %f921;
	add.f32 	%f923, %f920, %f916;
	sub.f32 	%f924, %f920, %f923;
	add.f32 	%f925, %f916, %f924;
	add.f32 	%f926, %f918, %f925;
	add.f32 	%f927, %f922, %f926;
	add.f32 	%f928, %f923, %f927;
	sub.f32 	%f929, %f923, %f928;
	add.f32 	%f930, %f927, %f929;
	mov.f32 	%f931, 0f3ED55555;
	mul.rn.f32 	%f932, %f931, %f928;
	neg.f32 	%f933, %f932;
	fma.rn.f32 	%f934, %f931, %f928, %f933;
	fma.rn.f32 	%f935, %f931, %f930, %f934;
	mov.f32 	%f936, 0f00000000;
	fma.rn.f32 	%f937, %f936, %f928, %f935;
	add.rn.f32 	%f938, %f932, %f937;
	neg.f32 	%f939, %f938;
	add.rn.f32 	%f940, %f932, %f939;
	add.rn.f32 	%f941, %f940, %f937;
	mov.b32 	%r272, %f938;
	setp.eq.s32 	%p106, %r272, 1118925336;
	add.s32 	%r273, %r272, -1;
	mov.b32 	%f942, %r273;
	add.f32 	%f943, %f941, 0f37000000;
	selp.f32 	%f267, %f943, %f941, %p106;
	selp.f32 	%f944, %f942, %f938, %p106;
	mov.f32 	%f945, 0f3FB8AA3B;
	mul.rn.f32 	%f946, %f944, %f945;
	cvt.rzi.f32.f32 	%f947, %f946;
	abs.f32 	%f948, %f947;
	setp.gt.f32 	%p107, %f948, 0f42FC0000;
	mov.b32 	%r274, %f947;
	and.b32  	%r275, %r274, -2147483648;
	or.b32  	%r276, %r275, 1123811328;
	mov.b32 	%f949, %r276;
	selp.f32 	%f950, %f949, %f947, %p107;
	mov.f32 	%f951, 0fBF317218;
	fma.rn.f32 	%f952, %f950, %f951, %f944;
	mov.f32 	%f953, 0f3102E308;
	fma.rn.f32 	%f954, %f950, %f953, %f952;
	mul.f32 	%f955, %f954, 0f3FB8AA3B;
	add.f32 	%f956, %f950, 0f4B40007F;
	mov.b32 	%r277, %f956;
	shl.b32 	%r278, %r277, 23;
	mov.b32 	%f957, %r278;
	ex2.approx.ftz.f32 	%f958, %f955;
	mul.f32 	%f268, %f958, %f957;
	setp.eq.f32 	%p108, %f268, 0f7F800000;
	mov.f32 	%f1420, 0f7F800000;
	@%p108 bra 	$L__BB0_89;

	fma.rn.f32 	%f1420, %f268, %f267, %f268;

$L__BB0_89:
	setp.lt.f32 	%p109, %f252, 0f00000000;
	and.pred  	%p5, %p109, %p96;
	setp.eq.f32 	%p111, %f252, 0f00000000;
	@%p111 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	add.f32 	%f963, %f252, %f252;
	selp.f32 	%f1422, %f963, 0f00000000, %p96;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.b32 	%r279, %f1420;
	xor.b32  	%r280, %r279, -2147483648;
	mov.b32 	%f959, %r280;
	selp.f32 	%f1422, %f959, %f1420, %p5;
	setp.geu.f32 	%p112, %f252, 0f00000000;
	@%p112 bra 	$L__BB0_94;

	mov.f32 	%f960, 0f3ED55555;
	cvt.rzi.f32.f32 	%f961, %f960;
	setp.eq.f32 	%p113, %f961, 0f3ED55555;
	@%p113 bra 	$L__BB0_94;

	mov.f32 	%f1422, 0f7FFFFFFF;

$L__BB0_94:
	add.f32 	%f964, %f266, 0f3ED55555;
	mov.b32 	%r281, %f964;
	setp.lt.s32 	%p115, %r281, 2139095040;
	@%p115 bra 	$L__BB0_99;

	setp.gtu.f32 	%p116, %f266, 0f7F800000;
	@%p116 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	add.f32 	%f1422, %f252, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	setp.neu.f32 	%p117, %f266, 0f7F800000;
	@%p117 bra 	$L__BB0_99;

	selp.f32 	%f1422, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f277, %f253;
	setp.lt.f32 	%p118, %f277, 0f00800000;
	mul.f32 	%f966, %f277, 0f4B800000;
	selp.f32 	%f967, %f966, %f277, %p118;
	selp.f32 	%f968, 0fC3170000, 0fC2FE0000, %p118;
	mov.b32 	%r282, %f967;
	and.b32  	%r283, %r282, 8388607;
	or.b32  	%r284, %r283, 1065353216;
	mov.b32 	%f969, %r284;
	shr.u32 	%r285, %r282, 23;
	cvt.rn.f32.u32 	%f970, %r285;
	add.f32 	%f971, %f968, %f970;
	setp.gt.f32 	%p119, %f969, 0f3FB504F3;
	mul.f32 	%f972, %f969, 0f3F000000;
	add.f32 	%f973, %f971, 0f3F800000;
	selp.f32 	%f974, %f973, %f971, %p119;
	selp.f32 	%f975, %f972, %f969, %p119;
	add.f32 	%f976, %f975, 0fBF800000;
	add.f32 	%f977, %f975, 0f3F800000;
	rcp.approx.ftz.f32 	%f978, %f977;
	add.f32 	%f979, %f976, %f976;
	mul.f32 	%f980, %f979, %f978;
	mul.f32 	%f981, %f980, %f980;
	mov.f32 	%f982, 0f3C4CAF63;
	mov.f32 	%f983, 0f3B18F0FE;
	fma.rn.f32 	%f984, %f983, %f981, %f982;
	mov.f32 	%f985, 0f3DAAAABD;
	fma.rn.f32 	%f986, %f984, %f981, %f985;
	mul.rn.f32 	%f987, %f986, %f981;
	mul.rn.f32 	%f988, %f987, %f980;
	sub.f32 	%f989, %f976, %f980;
	add.f32 	%f990, %f989, %f989;
	neg.f32 	%f991, %f980;
	fma.rn.f32 	%f992, %f991, %f976, %f990;
	mul.rn.f32 	%f993, %f978, %f992;
	add.f32 	%f994, %f988, %f980;
	sub.f32 	%f995, %f980, %f994;
	add.f32 	%f996, %f988, %f995;
	add.f32 	%f997, %f993, %f996;
	add.f32 	%f998, %f994, %f997;
	sub.f32 	%f999, %f994, %f998;
	add.f32 	%f1000, %f997, %f999;
	mov.f32 	%f1001, 0f3F317200;
	mul.rn.f32 	%f1002, %f974, %f1001;
	mov.f32 	%f1003, 0f35BFBE8E;
	mul.rn.f32 	%f1004, %f974, %f1003;
	add.f32 	%f1005, %f1002, %f998;
	sub.f32 	%f1006, %f1002, %f1005;
	add.f32 	%f1007, %f998, %f1006;
	add.f32 	%f1008, %f1000, %f1007;
	add.f32 	%f1009, %f1004, %f1008;
	add.f32 	%f1010, %f1005, %f1009;
	sub.f32 	%f1011, %f1005, %f1010;
	add.f32 	%f1012, %f1009, %f1011;
	mov.f32 	%f1013, 0f3ED55555;
	mul.rn.f32 	%f1014, %f1013, %f1010;
	neg.f32 	%f1015, %f1014;
	fma.rn.f32 	%f1016, %f1013, %f1010, %f1015;
	fma.rn.f32 	%f1017, %f1013, %f1012, %f1016;
	mov.f32 	%f1018, 0f00000000;
	fma.rn.f32 	%f1019, %f1018, %f1010, %f1017;
	add.rn.f32 	%f1020, %f1014, %f1019;
	neg.f32 	%f1021, %f1020;
	add.rn.f32 	%f1022, %f1014, %f1021;
	add.rn.f32 	%f1023, %f1022, %f1019;
	mov.b32 	%r286, %f1020;
	setp.eq.s32 	%p120, %r286, 1118925336;
	add.s32 	%r287, %r286, -1;
	mov.b32 	%f1024, %r287;
	add.f32 	%f1025, %f1023, 0f37000000;
	selp.f32 	%f278, %f1025, %f1023, %p120;
	selp.f32 	%f1026, %f1024, %f1020, %p120;
	mov.f32 	%f1027, 0f3FB8AA3B;
	mul.rn.f32 	%f1028, %f1026, %f1027;
	cvt.rzi.f32.f32 	%f1029, %f1028;
	abs.f32 	%f1030, %f1029;
	setp.gt.f32 	%p121, %f1030, 0f42FC0000;
	mov.b32 	%r288, %f1029;
	and.b32  	%r289, %r288, -2147483648;
	or.b32  	%r290, %r289, 1123811328;
	mov.b32 	%f1031, %r290;
	selp.f32 	%f1032, %f1031, %f1029, %p121;
	mov.f32 	%f1033, 0fBF317218;
	fma.rn.f32 	%f1034, %f1032, %f1033, %f1026;
	mov.f32 	%f1035, 0f3102E308;
	fma.rn.f32 	%f1036, %f1032, %f1035, %f1034;
	mul.f32 	%f1037, %f1036, 0f3FB8AA3B;
	add.f32 	%f1038, %f1032, 0f4B40007F;
	mov.b32 	%r291, %f1038;
	shl.b32 	%r292, %r291, 23;
	mov.b32 	%f1039, %r292;
	ex2.approx.ftz.f32 	%f1040, %f1037;
	mul.f32 	%f279, %f1040, %f1039;
	setp.eq.f32 	%p122, %f279, 0f7F800000;
	mov.f32 	%f1423, 0f7F800000;
	@%p122 bra 	$L__BB0_101;

	fma.rn.f32 	%f1423, %f279, %f278, %f279;

$L__BB0_101:
	setp.lt.f32 	%p123, %f253, 0f00000000;
	and.pred  	%p6, %p123, %p96;
	setp.eq.f32 	%p125, %f253, 0f00000000;
	@%p125 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f1045, %f253, %f253;
	selp.f32 	%f1425, %f1045, 0f00000000, %p96;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r293, %f1423;
	xor.b32  	%r294, %r293, -2147483648;
	mov.b32 	%f1041, %r294;
	selp.f32 	%f1425, %f1041, %f1423, %p6;
	setp.geu.f32 	%p126, %f253, 0f00000000;
	@%p126 bra 	$L__BB0_106;

	mov.f32 	%f1042, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1043, %f1042;
	setp.eq.f32 	%p127, %f1043, 0f3ED55555;
	@%p127 bra 	$L__BB0_106;

	mov.f32 	%f1425, 0f7FFFFFFF;

$L__BB0_106:
	add.f32 	%f1046, %f277, 0f3ED55555;
	mov.b32 	%r295, %f1046;
	setp.lt.s32 	%p129, %r295, 2139095040;
	@%p129 bra 	$L__BB0_111;

	setp.gtu.f32 	%p130, %f277, 0f7F800000;
	@%p130 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1425, %f253, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	setp.neu.f32 	%p131, %f277, 0f7F800000;
	@%p131 bra 	$L__BB0_111;

	selp.f32 	%f1425, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	ld.const.u64 	%rd156, [params+144];
	cvta.to.global.u64 	%rd155, %rd156;
	ld.const.u32 	%r370, [params+136];
	mad.lo.s32 	%r369, %r370, %r6, %r5;
	cvt.u64.u32 	%rd154, %r369;
	fma.rn.f32 	%f1047, %f1419, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p132, %f251, 0f3F800000;
	mov.f32 	%f1048, 0f3F800000;
	selp.f32 	%f1049, 0f3F7FFFFF, %f1047, %p132;
	mul.f32 	%f1050, %f251, 0f414EB852;
	setp.lt.f32 	%p133, %f251, 0f3B4D2E1C;
	selp.f32 	%f1051, %f1050, %f1049, %p133;
	fma.rn.f32 	%f1052, %f1422, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p134, %f252, 0f3F800000;
	selp.f32 	%f1053, 0f3F7FFFFF, %f1052, %p134;
	mul.f32 	%f1054, %f252, 0f414EB852;
	setp.lt.f32 	%p135, %f252, 0f3B4D2E1C;
	selp.f32 	%f1055, %f1054, %f1053, %p135;
	fma.rn.f32 	%f1056, %f1425, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p136, %f253, 0f3F800000;
	selp.f32 	%f1057, 0f3F7FFFFF, %f1056, %p136;
	mul.f32 	%f1058, %f253, 0f414EB852;
	setp.lt.f32 	%p137, %f253, 0f3B4D2E1C;
	selp.f32 	%f1059, %f1058, %f1057, %p137;
	min.f32 	%f1060, %f1051, %f1048;
	mov.f32 	%f1061, 0f00000000;
	max.f32 	%f1062, %f1061, %f1060;
	mul.f32 	%f1063, %f1062, 0f43800000;
	cvt.rzi.u32.f32 	%r296, %f1063;
	min.u32 	%r297, %r296, 255;
	min.f32 	%f1064, %f1055, %f1048;
	max.f32 	%f1065, %f1061, %f1064;
	mul.f32 	%f1066, %f1065, 0f43800000;
	cvt.rzi.u32.f32 	%r298, %f1066;
	min.u32 	%r299, %r298, 255;
	min.f32 	%f1067, %f1059, %f1048;
	max.f32 	%f1068, %f1061, %f1067;
	mul.f32 	%f1069, %f1068, 0f43800000;
	cvt.rzi.u32.f32 	%r300, %f1069;
	min.u32 	%r301, %r300, 255;
	shl.b64 	%rd78, %rd154, 2;
	add.s64 	%rd79, %rd155, %rd78;
	cvt.u16.u32 	%rs23, %r301;
	cvt.u16.u32 	%rs24, %r299;
	cvt.u16.u32 	%rs25, %r297;
	mov.u16 	%rs26, 255;
	st.global.v4.u8 	[%rd79], {%rs25, %rs24, %rs23, %rs26};

$L__BB0_112:
	ld.const.u32 	%r371, [params+104];
	and.b32  	%r302, %r371, 4;
	setp.eq.s32 	%p138, %r302, 0;
	@%p138 bra 	$L__BB0_114;

	ld.const.u64 	%rd80, [params+224];
	cvta.to.global.u64 	%rd81, %rd80;
	ld.const.u32 	%r303, [params+216];
	mad.lo.s32 	%r304, %r303, %r6, %r5;
	mov.f32 	%f1073, 0f3F800000;
	mul.wide.u32 	%rd82, %r304, 8;
	add.s64 	%rd83, %rd81, %rd82;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1073;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1407;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1406;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1405;}

	// end inline asm
	st.global.v4.u16 	[%rd83], {%rs27, %rs28, %rs29, %rs30};

$L__BB0_114:
	ld.const.u32 	%r372, [params+104];
	and.b32  	%r305, %r372, 16;
	setp.eq.s32 	%p139, %r305, 0;
	@%p139 bra 	$L__BB0_116;

	ld.const.u64 	%rd84, [params+240];
	cvta.to.global.u64 	%rd85, %rd84;
	ld.const.u32 	%r306, [params+232];
	mad.lo.s32 	%r307, %r306, %r6, %r5;
	mov.f32 	%f1077, 0f3F800000;
	mul.wide.u32 	%rd86, %r307, 8;
	add.s64 	%rd87, %rd85, %rd86;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f1077;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f202;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs31, %f200;}

	// end inline asm
	st.global.v4.u16 	[%rd87], {%rs31, %rs32, %rs33, %rs34};

$L__BB0_116:
	mul.f32 	%f1078, %f173, 0f40800000;
	mul.f32 	%f288, %f1078, 0f3F558750;
	mul.f32 	%f1079, %f174, 0f40800000;
	mul.f32 	%f289, %f1079, 0f3F558750;
	mul.f32 	%f1080, %f175, 0f40800000;
	mul.f32 	%f290, %f1080, 0f3F558750;
	ld.const.u32 	%r50, [params+108];
	setp.eq.s32 	%p140, %r50, 0;
	ld.const.u64 	%rd88, [params+256];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r308, [params+248];
	mad.lo.s32 	%r309, %r308, %r6, %r5;
	mul.wide.u32 	%rd90, %r309, 8;
	add.s64 	%rd18, %rd89, %rd90;
	@%p140 bra 	$L__BB0_118;

	ld.global.v4.u16 	{%rs42, %rs43, %rs44, %rs45}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f1081, %rs42;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1082, %rs43;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1083, %rs44;}

	// end inline asm
	add.f32 	%f1084, %f288, %f1081;
	add.f32 	%f1085, %f289, %f1082;
	add.f32 	%f1086, %f290, %f1083;
	mov.f32 	%f1087, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1086;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs39, %f1085;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1084;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1087;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs38, %rs39, %rs40, %rs41};
	bra.uni 	$L__BB0_119;

$L__BB0_118:
	mov.f32 	%f1091, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f1091;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f290;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs47, %f289;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f288;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs46, %rs47, %rs48, %rs49};

$L__BB0_119:
	mul.f32 	%f1092, %f176, 0f40800000;
	mul.f32 	%f291, %f1092, 0f3FB8EBD1;
	mul.f32 	%f1093, %f177, 0f40800000;
	mul.f32 	%f292, %f1093, 0f3FB8EBD1;
	mul.f32 	%f1094, %f178, 0f40800000;
	mul.f32 	%f293, %f1094, 0f3FB8EBD1;
	ld.const.u64 	%rd91, [params+272];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r310, [params+264];
	mad.lo.s32 	%r311, %r310, %r6, %r5;
	mul.wide.u32 	%rd93, %r311, 8;
	add.s64 	%rd19, %rd92, %rd93;
	@%p140 bra 	$L__BB0_121;

	ld.global.v4.u16 	{%rs57, %rs58, %rs59, %rs60}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1095, %rs57;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1096, %rs58;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1097, %rs59;}

	// end inline asm
	add.f32 	%f1098, %f291, %f1095;
	add.f32 	%f1099, %f292, %f1096;
	add.f32 	%f1100, %f293, %f1097;
	mov.f32 	%f1101, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1100;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f1099;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1098;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1101;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs53, %rs54, %rs55, %rs56};
	bra.uni 	$L__BB0_122;

$L__BB0_121:
	mov.f32 	%f1105, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f1105;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f293;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f292;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f291;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs61, %rs62, %rs63, %rs64};

$L__BB0_122:
	mul.f32 	%f1106, %f179, 0f40800000;
	mul.f32 	%f294, %f1106, 0f3FB8EBD1;
	mul.f32 	%f1107, %f180, 0f40800000;
	mul.f32 	%f295, %f1107, 0f3FB8EBD1;
	mul.f32 	%f1108, %f181, 0f40800000;
	mul.f32 	%f296, %f1108, 0f3FB8EBD1;
	ld.const.u64 	%rd94, [params+288];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r312, [params+280];
	mad.lo.s32 	%r313, %r312, %r6, %r5;
	mul.wide.u32 	%rd96, %r313, 8;
	add.s64 	%rd20, %rd95, %rd96;
	@%p140 bra 	$L__BB0_124;

	ld.global.v4.u16 	{%rs72, %rs73, %rs74, %rs75}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1109, %rs72;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1110, %rs73;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1111, %rs74;}

	// end inline asm
	add.f32 	%f1112, %f294, %f1109;
	add.f32 	%f1113, %f295, %f1110;
	add.f32 	%f1114, %f296, %f1111;
	mov.f32 	%f1115, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1114;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1113;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1112;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1115;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs68, %rs69, %rs70, %rs71};
	bra.uni 	$L__BB0_125;

$L__BB0_124:
	mov.f32 	%f1119, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f1119;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f296;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f295;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f294;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs76, %rs77, %rs78, %rs79};

$L__BB0_125:
	mul.f32 	%f1120, %f182, 0f40800000;
	mul.f32 	%f297, %f1120, 0f3FB8EBD1;
	mul.f32 	%f1121, %f183, 0f40800000;
	mul.f32 	%f298, %f1121, 0f3FB8EBD1;
	mul.f32 	%f1122, %f184, 0f40800000;
	mul.f32 	%f299, %f1122, 0f3FB8EBD1;
	ld.const.u64 	%rd97, [params+304];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r314, [params+296];
	mad.lo.s32 	%r315, %r314, %r6, %r5;
	mul.wide.u32 	%rd99, %r315, 8;
	add.s64 	%rd21, %rd98, %rd99;
	@%p140 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs87, %rs88, %rs89, %rs90}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1123, %rs87;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1124, %rs88;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1125, %rs89;}

	// end inline asm
	add.f32 	%f1126, %f297, %f1123;
	add.f32 	%f1127, %f298, %f1124;
	add.f32 	%f1128, %f299, %f1125;
	mov.f32 	%f1129, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1127;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1126;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1129;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs83, %rs84, %rs85, %rs86};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f1133, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f1133;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f299;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f298;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f297;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs91, %rs92, %rs93, %rs94};

$L__BB0_128:
	mul.f32 	%f1134, %f185, 0f40800000;
	mul.f32 	%f300, %f1134, 0f404EBF87;
	mul.f32 	%f1135, %f186, 0f40800000;
	mul.f32 	%f301, %f1135, 0f404EBF87;
	mul.f32 	%f1136, %f187, 0f40800000;
	mul.f32 	%f302, %f1136, 0f404EBF87;
	ld.const.u64 	%rd100, [params+320];
	cvta.to.global.u64 	%rd101, %rd100;
	ld.const.u32 	%r316, [params+312];
	mad.lo.s32 	%r317, %r316, %r6, %r5;
	mul.wide.u32 	%rd102, %r317, 8;
	add.s64 	%rd22, %rd101, %rd102;
	@%p140 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs102, %rs103, %rs104, %rs105}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1137, %rs102;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1138, %rs103;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1139, %rs104;}

	// end inline asm
	add.f32 	%f1140, %f300, %f1137;
	add.f32 	%f1141, %f301, %f1138;
	add.f32 	%f1142, %f302, %f1139;
	mov.f32 	%f1143, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1142;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1141;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1140;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs101, %f1143;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs98, %rs99, %rs100, %rs101};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f1147, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs109, %f1147;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f302;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f301;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f300;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs106, %rs107, %rs108, %rs109};

$L__BB0_131:
	mul.f32 	%f1148, %f188, 0f40800000;
	mul.f32 	%f303, %f1148, 0f404EBF87;
	mul.f32 	%f1149, %f189, 0f40800000;
	mul.f32 	%f304, %f1149, 0f404EBF87;
	mul.f32 	%f1150, %f190, 0f40800000;
	mul.f32 	%f305, %f1150, 0f404EBF87;
	ld.const.u64 	%rd103, [params+336];
	cvta.to.global.u64 	%rd104, %rd103;
	ld.const.u32 	%r318, [params+328];
	mad.lo.s32 	%r319, %r318, %r6, %r5;
	mul.wide.u32 	%rd105, %r319, 8;
	add.s64 	%rd23, %rd104, %rd105;
	@%p140 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs117, %rs118, %rs119, %rs120}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1151, %rs117;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1152, %rs118;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1153, %rs119;}

	// end inline asm
	add.f32 	%f1154, %f303, %f1151;
	add.f32 	%f1155, %f304, %f1152;
	add.f32 	%f1156, %f305, %f1153;
	mov.f32 	%f1157, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1156;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1155;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1154;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs116, %f1157;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs113, %rs114, %rs115, %rs116};
	bra.uni 	$L__BB0_134;

$L__BB0_133:
	mov.f32 	%f1161, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs124, %f1161;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f305;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f304;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f303;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs121, %rs122, %rs123, %rs124};

$L__BB0_134:
	mul.f32 	%f1162, %f191, 0f40800000;
	mul.f32 	%f306, %f1162, 0f40330C94;
	mul.f32 	%f1163, %f192, 0f40800000;
	mul.f32 	%f307, %f1163, 0f40330C94;
	mul.f32 	%f1164, %f193, 0f40800000;
	mul.f32 	%f308, %f1164, 0f40330C94;
	ld.const.u64 	%rd106, [params+352];
	cvta.to.global.u64 	%rd107, %rd106;
	ld.const.u32 	%r320, [params+344];
	mad.lo.s32 	%r321, %r320, %r6, %r5;
	mul.wide.u32 	%rd108, %r321, 8;
	add.s64 	%rd24, %rd107, %rd108;
	@%p140 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs132, %rs133, %rs134, %rs135}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1165, %rs132;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1166, %rs133;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1167, %rs134;}

	// end inline asm
	add.f32 	%f1168, %f306, %f1165;
	add.f32 	%f1169, %f307, %f1166;
	add.f32 	%f1170, %f308, %f1167;
	mov.f32 	%f1171, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1170;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1169;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs131, %f1171;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs128, %rs129, %rs130, %rs131};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1175, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs139, %f1175;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f308;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f307;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f306;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs136, %rs137, %rs138, %rs139};

$L__BB0_137:
	mul.f32 	%f1176, %f194, 0f40800000;
	mul.f32 	%f309, %f1176, 0f404EBF87;
	mul.f32 	%f1177, %f195, 0f40800000;
	mul.f32 	%f310, %f1177, 0f404EBF87;
	mul.f32 	%f1178, %f196, 0f40800000;
	mul.f32 	%f311, %f1178, 0f404EBF87;
	ld.const.u64 	%rd109, [params+368];
	cvta.to.global.u64 	%rd110, %rd109;
	ld.const.u32 	%r322, [params+360];
	mad.lo.s32 	%r323, %r322, %r6, %r5;
	mul.wide.u32 	%rd111, %r323, 8;
	add.s64 	%rd25, %rd110, %rd111;
	@%p140 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs147, %rs148, %rs149, %rs150}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1179, %rs147;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1180, %rs148;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1181, %rs149;}

	// end inline asm
	add.f32 	%f1182, %f309, %f1179;
	add.f32 	%f1183, %f310, %f1180;
	add.f32 	%f1184, %f311, %f1181;
	mov.f32 	%f1185, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1184;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1183;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1182;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs146, %f1185;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs143, %rs144, %rs145, %rs146};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1189, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs154, %f1189;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f311;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f310;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f309;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs151, %rs152, %rs153, %rs154};

$L__BB0_140:
	mul.f32 	%f1190, %f197, 0f40800000;
	mul.f32 	%f312, %f1190, 0f3FCEBF87;
	mul.f32 	%f1191, %f198, 0f40800000;
	mul.f32 	%f313, %f1191, 0f3FCEBF87;
	mul.f32 	%f1192, %f199, 0f40800000;
	mul.f32 	%f314, %f1192, 0f3FCEBF87;
	ld.const.u64 	%rd112, [params+384];
	cvta.to.global.u64 	%rd113, %rd112;
	ld.const.u32 	%r324, [params+376];
	mad.lo.s32 	%r325, %r324, %r6, %r5;
	mul.wide.u32 	%rd114, %r325, 8;
	add.s64 	%rd26, %rd113, %rd114;
	@%p140 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs162, %rs163, %rs164, %rs165}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1193, %rs162;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1194, %rs163;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1195, %rs164;}

	// end inline asm
	add.f32 	%f1196, %f312, %f1193;
	add.f32 	%f1197, %f313, %f1194;
	add.f32 	%f1198, %f314, %f1195;
	mov.f32 	%f1199, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1198;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1197;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1196;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs161, %f1199;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs158, %rs159, %rs160, %rs161};
	bra.uni 	$L__BB0_176;

$L__BB0_142:
	mov.f32 	%f1203, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs169, %f1203;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f314;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f313;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f312;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs166, %rs167, %rs168, %rs169};

$L__BB0_176:
	ret;

}