//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<89>;
	.reg .b16 	%rs<51>;
	.reg .f32 	%f<476>;
	.reg .b32 	%r<269>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<74>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r50), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r51), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.f32 	%f1, [params+700];
	ld.const.u64 	%rd21, [params+400];
	cvta.to.global.u64 	%rd22, %rd21;
	ld.const.u32 	%r56, [params+392];
	mad.lo.s32 	%r57, %r56, %r51, %r50;
	mul.wide.u32 	%rd23, %r57, 4;
	add.s64 	%rd2, %rd22, %rd23;
	ld.global.v2.u8 	{%rs7, %rs50}, [%rd2];
	or.b16  	%rs9, %rs7, %rs50;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p3, %rs10, 0;
	@%p3 bra 	$L__BB0_2;

	ld.global.u8 	%rs49, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs49, [%rd2+2];
	setp.eq.s16 	%p4, %rs49, 0;
	mov.f32 	%f447, 0f00000000;
	mov.u16 	%rs50, 0;
	mov.f32 	%f448, %f447;
	mov.f32 	%f449, %f447;
	@%p4 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f106, %rs7;
	div.rn.f32 	%f107, %f106, 0f437F0000;
	fma.rn.f32 	%f108, %f107, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs50, 255;
	cvt.rn.f32.u16 	%f109, %rs13;
	div.rn.f32 	%f110, %f109, 0f437F0000;
	fma.rn.f32 	%f111, %f110, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f112, %rs49;
	div.rn.f32 	%f113, %f112, 0f437F0000;
	fma.rn.f32 	%f114, %f113, 0f40000000, 0fBF800000;
	mul.f32 	%f115, %f111, %f111;
	fma.rn.f32 	%f116, %f108, %f108, %f115;
	fma.rn.f32 	%f117, %f114, %f114, %f116;
	sqrt.rn.f32 	%f118, %f117;
	rcp.rn.f32 	%f119, %f118;
	mul.f32 	%f449, %f119, %f114;
	mul.f32 	%f448, %f119, %f111;
	mul.f32 	%f447, %f108, %f119;

$L__BB0_4:
	ld.const.v2.u32 	{%r58, %r59}, [params];
	add.s32 	%r3, %r58, %r50;
	add.s32 	%r4, %r59, %r51;
	setp.eq.f32 	%p5, %f447, 0f00000000;
	setp.eq.f32 	%p6, %f448, 0f00000000;
	and.pred  	%p7, %p5, %p6;
	setp.eq.f32 	%p8, %f449, 0f00000000;
	and.pred  	%p9, %p8, %p7;
	@%p9 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_5;

$L__BB0_74:
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r250, %r49, 4;
	setp.eq.s32 	%p86, %r250, 0;
	@%p86 bra 	$L__BB0_78;

	ld.const.u32 	%r251, [params+108];
	setp.eq.s32 	%p87, %r251, 0;
	ld.const.u64 	%rd62, [params+224];
	cvta.to.global.u64 	%rd63, %rd62;
	ld.const.u32 	%r252, [params+216];
	mad.lo.s32 	%r253, %r252, %r4, %r3;
	mul.wide.u32 	%rd64, %r253, 8;
	add.s64 	%rd19, %rd63, %rd64;
	@%p87 bra 	$L__BB0_77;

	ld.global.v4.u16 	{%rs38, %rs39, %rs40, %rs41}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f434, %rs38;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f435, %rs39;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f436, %rs40;}

	// end inline asm
	add.f32 	%f437, %f434, 0f00000000;
	add.f32 	%f438, %f435, 0f00000000;
	add.f32 	%f439, %f436, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f439;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f438;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f437;}

	// end inline asm
	mov.u16 	%rs42, 0;
	st.global.v4.u16 	[%rd19], {%rs35, %rs36, %rs37, %rs42};
	bra.uni 	$L__BB0_78;

$L__BB0_5:
	ld.const.u64 	%rd24, [params+432];
	cvta.to.global.u64 	%rd25, %rd24;
	ld.const.u32 	%r62, [params+424];
	mad.lo.s32 	%r63, %r62, %r51, %r50;
	mul.wide.u32 	%rd26, %r63, 12;
	add.s64 	%rd27, %rd25, %rd26;
	ld.global.f32 	%f121, [%rd27];
	mul.f32 	%f122, %f121, 0f3456BF95;
	ld.global.f32 	%f123, [%rd27+4];
	mul.f32 	%f124, %f123, 0f3456BF95;
	ld.global.f32 	%f125, [%rd27+8];
	mul.f32 	%f126, %f125, 0f3456BF95;
	abs.f32 	%f127, %f447;
	div.rn.f32 	%f128, %f122, %f127;
	abs.f32 	%f129, %f448;
	div.rn.f32 	%f130, %f124, %f129;
	abs.f32 	%f131, %f449;
	div.rn.f32 	%f132, %f126, %f131;
	abs.f32 	%f133, %f128;
	abs.f32 	%f134, %f130;
	abs.f32 	%f135, %f132;
	mov.f32 	%f136, 0f38D1B717;
	max.f32 	%f137, %f133, %f136;
	max.f32 	%f138, %f134, %f136;
	max.f32 	%f139, %f135, %f136;
	fma.rn.f32 	%f465, %f447, %f137, %f121;
	fma.rn.f32 	%f466, %f448, %f138, %f123;
	fma.rn.f32 	%f467, %f449, %f139, %f125;
	setp.gt.f32 	%p10, %f127, %f131;
	neg.f32 	%f140, %f448;
	selp.f32 	%f141, %f140, 0f00000000, %p10;
	mov.f32 	%f457, 0f00000000;
	neg.f32 	%f142, %f449;
	selp.f32 	%f143, %f447, %f142, %p10;
	selp.f32 	%f144, 0f00000000, %f448, %p10;
	mul.f32 	%f145, %f143, %f143;
	fma.rn.f32 	%f146, %f141, %f141, %f145;
	fma.rn.f32 	%f147, %f144, %f144, %f146;
	sqrt.rn.f32 	%f148, %f147;
	rcp.rn.f32 	%f149, %f148;
	mul.f32 	%f14, %f141, %f149;
	mul.f32 	%f15, %f143, %f149;
	mul.f32 	%f16, %f144, %f149;
	ld.const.u64 	%rd28, [params+128];
	cvta.to.global.u64 	%rd29, %rd28;
	ld.const.u32 	%r64, [params+120];
	mad.lo.s32 	%r65, %r64, %r51, %r50;
	mul.wide.u32 	%rd30, %r65, 4;
	add.s64 	%rd3, %rd29, %rd30;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p11, %r5, 1;
	@%p11 bra 	$L__BB0_37;

	cvt.rn.f32.s32 	%f151, %r5;
	rcp.rn.f32 	%f17, %f151;
	ld.global.u32 	%r261, [%rd3];
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f152, %f447, %f15;
	mul.f32 	%f153, %f448, %f14;
	sub.f32 	%f18, %f153, %f152;
	mul.f32 	%f154, %f449, %f14;
	mul.f32 	%f155, %f447, %f16;
	sub.f32 	%f19, %f155, %f154;
	mul.f32 	%f156, %f448, %f16;
	mul.f32 	%f157, %f449, %f15;
	sub.f32 	%f20, %f157, %f156;
	mov.u32 	%r66, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd31, __cudart_i2opi_f;
	mov.u32 	%r258, %r66;

$L__BB0_7:
	mov.u32 	%r260, %r66;

$L__BB0_8:
	cvt.rn.f32.s32 	%f444, %r258;
	mad.lo.s32 	%r68, %r261, 1664525, 1013904223;
	and.b32  	%r69, %r68, 16777215;
	cvt.rn.f32.u32 	%f158, %r69;
	fma.rn.f32 	%f159, %f158, 0f33800000, %f444;
	mul.f32 	%f160, %f17, %f159;
	mad.lo.s32 	%r261, %r68, 1664525, 1013904223;
	and.b32  	%r70, %r261, 16777215;
	cvt.rn.f32.u32 	%f161, %r70;
	cvt.rn.f32.s32 	%f162, %r260;
	fma.rn.f32 	%f163, %f161, 0f33800000, %f162;
	mul.f32 	%f164, %f17, %f163;
	sqrt.rn.f32 	%f30, %f160;
	mul.f32 	%f31, %f164, 0f40C90FDB;
	mul.f32 	%f165, %f31, 0f3F22F983;
	cvt.rni.s32.f32 	%r268, %f165;
	cvt.rn.f32.s32 	%f166, %r268;
	mov.f32 	%f167, 0fBFC90FDA;
	fma.rn.f32 	%f168, %f166, %f167, %f31;
	mov.f32 	%f169, 0fB3A22168;
	fma.rn.f32 	%f170, %f166, %f169, %f168;
	mov.f32 	%f171, 0fA7C234C5;
	fma.rn.f32 	%f461, %f166, %f171, %f170;
	abs.f32 	%f33, %f31;
	setp.ltu.f32 	%p12, %f33, 0f47CE4780;
	mov.u32 	%r265, %r268;
	mov.f32 	%f458, %f461;
	@%p12 bra 	$L__BB0_16;

	setp.eq.f32 	%p13, %f33, 0f7F800000;
	@%p13 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f174, 0f00000000;
	mul.rn.f32 	%f458, %f31, %f174;
	mov.u32 	%r265, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f31;
	bfe.u32 	%r72, %r13, 23, 8;
	add.s32 	%r14, %r72, -128;
	shl.b32 	%r73, %r13, 8;
	or.b32  	%r15, %r73, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd71, 0;
	mov.u32 	%r262, 0;
	mov.u64 	%rd69, %rd1;
	mov.u64 	%rd70, %rd31;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r74, [%rd70];
	mad.wide.u32 	%rd33, %r74, %r15, %rd71;
	shr.u64 	%rd71, %rd33, 32;
	st.local.u32 	[%rd69], %rd33;
	add.s64 	%rd70, %rd70, 4;
	add.s64 	%rd69, %rd69, 4;
	add.s32 	%r262, %r262, 1;
	setp.ne.s32 	%p14, %r262, 6;
	@%p14 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd71;
	mov.u32 	%r75, 4;
	sub.s32 	%r19, %r75, %r16;
	mov.u32 	%r76, 6;
	sub.s32 	%r77, %r76, %r16;
	mul.wide.s32 	%rd34, %r77, 4;
	add.s64 	%rd35, %rd1, %rd34;
	ld.local.u32 	%r263, [%rd35];
	ld.local.u32 	%r264, [%rd35+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p15, %r22, 0;
	@%p15 bra 	$L__BB0_14;

	mov.u32 	%r78, 32;
	sub.s32 	%r79, %r78, %r22;
	shr.u32 	%r80, %r264, %r79;
	shl.b32 	%r81, %r263, %r22;
	add.s32 	%r263, %r80, %r81;
	mul.wide.s32 	%rd36, %r19, 4;
	add.s64 	%rd37, %rd1, %rd36;
	ld.local.u32 	%r82, [%rd37];
	shr.u32 	%r83, %r82, %r79;
	shl.b32 	%r84, %r264, %r22;
	add.s32 	%r264, %r83, %r84;

$L__BB0_14:
	and.b32  	%r85, %r13, -2147483648;
	shr.u32 	%r86, %r264, 30;
	shl.b32 	%r87, %r263, 2;
	or.b32  	%r88, %r86, %r87;
	shr.u32 	%r89, %r88, 31;
	shr.u32 	%r90, %r263, 30;
	add.s32 	%r91, %r89, %r90;
	neg.s32 	%r92, %r91;
	setp.eq.s32 	%p16, %r85, 0;
	selp.b32 	%r265, %r91, %r92, %p16;
	setp.ne.s32 	%p17, %r89, 0;
	xor.b32  	%r93, %r85, -2147483648;
	selp.b32 	%r94, %r93, %r85, %p17;
	selp.b32 	%r95, -1, 0, %p17;
	xor.b32  	%r96, %r88, %r95;
	shl.b32 	%r97, %r264, 2;
	xor.b32  	%r98, %r97, %r95;
	cvt.u64.u32 	%rd38, %r96;
	cvt.u64.u32 	%rd39, %r98;
	bfi.b64 	%rd40, %rd38, %rd39, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd40;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f172, %fd2;
	setp.eq.s32 	%p18, %r94, 0;
	neg.f32 	%f173, %f172;
	selp.f32 	%f458, %f172, %f173, %p18;

$L__BB0_16:
	add.s32 	%r29, %r265, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p19, %r30, 0;
	selp.f32 	%f37, %f458, 0f3F800000, %p19;
	mul.rn.f32 	%f38, %f458, %f458;
	mov.f32 	%f459, 0fB94D4153;
	@%p19 bra 	$L__BB0_18;

	mov.f32 	%f176, 0fBAB607ED;
	mov.f32 	%f177, 0f37CBAC00;
	fma.rn.f32 	%f459, %f177, %f38, %f176;

$L__BB0_18:
	selp.f32 	%f178, 0f3C0885E4, 0f3D2AAABB, %p19;
	fma.rn.f32 	%f179, %f459, %f38, %f178;
	selp.f32 	%f180, 0fBE2AAAA8, 0fBEFFFFFF, %p19;
	fma.rn.f32 	%f181, %f179, %f38, %f180;
	mov.f32 	%f182, 0f00000000;
	fma.rn.f32 	%f183, %f38, %f37, %f182;
	fma.rn.f32 	%f460, %f181, %f183, %f37;
	and.b32  	%r100, %r29, 2;
	setp.eq.s32 	%p21, %r100, 0;
	@%p21 bra 	$L__BB0_20;

	mov.f32 	%f185, 0fBF800000;
	fma.rn.f32 	%f460, %f460, %f185, %f182;

$L__BB0_20:
	@%p12 bra 	$L__BB0_28;

	setp.eq.f32 	%p23, %f33, 0f7F800000;
	@%p23 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f188, 0f00000000;
	mul.rn.f32 	%f461, %f31, %f188;
	mov.u32 	%r268, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f31;
	bfe.u32 	%r101, %r31, 23, 8;
	add.s32 	%r32, %r101, -128;
	shl.b32 	%r102, %r31, 8;
	or.b32  	%r33, %r102, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd72, 0;
	mov.u64 	%rd73, %rd72;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd43, %rd72, 2;
	mov.u64 	%rd44, __cudart_i2opi_f;
	add.s64 	%rd45, %rd44, %rd43;
	ld.global.nc.u32 	%r103, [%rd45];
	mad.wide.u32 	%rd46, %r103, %r33, %rd73;
	shr.u64 	%rd73, %rd46, 32;
	add.s64 	%rd47, %rd1, %rd43;
	st.local.u32 	[%rd47], %rd46;
	cvt.u32.u64 	%r104, %rd72;
	add.s32 	%r105, %r104, 1;
	cvt.s64.s32 	%rd72, %r105;
	setp.ne.s32 	%p24, %r105, 6;
	@%p24 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd73;
	mov.u32 	%r106, 4;
	sub.s32 	%r35, %r106, %r34;
	mov.u32 	%r107, 6;
	sub.s32 	%r108, %r107, %r34;
	mul.wide.s32 	%rd48, %r108, 4;
	add.s64 	%rd49, %rd1, %rd48;
	ld.local.u32 	%r266, [%rd49];
	ld.local.u32 	%r267, [%rd49+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p25, %r38, 0;
	@%p25 bra 	$L__BB0_26;

	mov.u32 	%r109, 32;
	sub.s32 	%r110, %r109, %r38;
	shr.u32 	%r111, %r267, %r110;
	shl.b32 	%r112, %r266, %r38;
	add.s32 	%r266, %r111, %r112;
	mul.wide.s32 	%rd50, %r35, 4;
	add.s64 	%rd51, %rd1, %rd50;
	ld.local.u32 	%r113, [%rd51];
	shr.u32 	%r114, %r113, %r110;
	shl.b32 	%r115, %r267, %r38;
	add.s32 	%r267, %r114, %r115;

$L__BB0_26:
	and.b32  	%r116, %r31, -2147483648;
	shr.u32 	%r117, %r267, 30;
	shl.b32 	%r118, %r266, 2;
	or.b32  	%r119, %r117, %r118;
	shr.u32 	%r120, %r119, 31;
	shr.u32 	%r121, %r266, 30;
	add.s32 	%r122, %r120, %r121;
	neg.s32 	%r123, %r122;
	setp.eq.s32 	%p26, %r116, 0;
	selp.b32 	%r268, %r122, %r123, %p26;
	setp.ne.s32 	%p27, %r120, 0;
	xor.b32  	%r124, %r116, -2147483648;
	selp.b32 	%r125, %r124, %r116, %p27;
	selp.b32 	%r126, -1, 0, %p27;
	xor.b32  	%r127, %r119, %r126;
	shl.b32 	%r128, %r267, 2;
	xor.b32  	%r129, %r128, %r126;
	cvt.u64.u32 	%rd52, %r127;
	cvt.u64.u32 	%rd53, %r129;
	bfi.b64 	%rd54, %rd52, %rd53, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd54;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f186, %fd4;
	setp.eq.s32 	%p28, %r125, 0;
	neg.f32 	%f187, %f186;
	selp.f32 	%f461, %f186, %f187, %p28;

$L__BB0_28:
	mul.f32 	%f47, %f30, %f460;
	and.b32  	%r45, %r268, 1;
	setp.eq.s32 	%p29, %r45, 0;
	selp.f32 	%f48, %f461, 0f3F800000, %p29;
	mul.rn.f32 	%f49, %f461, %f461;
	mov.f32 	%f462, 0fB94D4153;
	@%p29 bra 	$L__BB0_30;

	mov.f32 	%f190, 0fBAB607ED;
	mov.f32 	%f191, 0f37CBAC00;
	fma.rn.f32 	%f462, %f191, %f49, %f190;

$L__BB0_30:
	selp.f32 	%f192, 0f3C0885E4, 0f3D2AAABB, %p29;
	fma.rn.f32 	%f193, %f462, %f49, %f192;
	selp.f32 	%f194, 0fBE2AAAA8, 0fBEFFFFFF, %p29;
	fma.rn.f32 	%f195, %f193, %f49, %f194;
	mov.f32 	%f196, 0f00000000;
	fma.rn.f32 	%f197, %f49, %f48, %f196;
	fma.rn.f32 	%f463, %f195, %f197, %f48;
	and.b32  	%r131, %r268, 2;
	setp.eq.s32 	%p31, %r131, 0;
	@%p31 bra 	$L__BB0_32;

	mov.f32 	%f198, 0f00000000;
	mov.f32 	%f199, 0fBF800000;
	fma.rn.f32 	%f463, %f463, %f199, %f198;

$L__BB0_32:
	mov.f32 	%f464, 0f00000000;
	mul.f32 	%f210, %f47, %f47;
	mov.f32 	%f211, 0f3F800000;
	sub.f32 	%f212, %f211, %f210;
	mul.f32 	%f213, %f30, %f463;
	mul.f32 	%f214, %f213, %f213;
	sub.f32 	%f215, %f212, %f214;
	max.f32 	%f216, %f464, %f215;
	sqrt.rn.f32 	%f217, %f216;
	mul.f32 	%f218, %f14, %f213;
	mul.f32 	%f219, %f15, %f213;
	mul.f32 	%f220, %f16, %f213;
	fma.rn.f32 	%f221, %f20, %f47, %f218;
	fma.rn.f32 	%f222, %f19, %f47, %f219;
	fma.rn.f32 	%f223, %f18, %f47, %f220;
	fma.rn.f32 	%f55, %f447, %f217, %f221;
	fma.rn.f32 	%f56, %f448, %f217, %f222;
	fma.rn.f32 	%f57, %f449, %f217, %f223;
	mul.f32 	%f224, %f465, 0f3456BF95;
	abs.f32 	%f225, %f224;
	mul.f32 	%f226, %f466, 0f3456BF95;
	abs.f32 	%f227, %f226;
	mul.f32 	%f228, %f467, 0f3456BF95;
	abs.f32 	%f229, %f228;
	max.f32 	%f230, %f225, %f227;
	max.f32 	%f231, %f230, %f229;
	mov.f32 	%f232, 0f38D1B717;
	max.f32 	%f206, %f231, %f232;
	mov.u32 	%r165, 1;
	mov.u32 	%r168, 2;
	mov.u32 	%r170, 3;
	mov.u32 	%r173, -1027080192;
	mov.u32 	%r202, 0;
	// begin inline asm
	call(%r132,%r133,%r134,%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163),_optix_trace_typed_32,(%r202,%rd4,%f465,%f466,%f467,%f55,%f56,%f57,%f206,%f1,%f464,%r165,%r202,%r202,%r168,%r202,%r170,%r173,%r173,%r173,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202,%r202);
	// end inline asm
	mov.b32 	%f58, %r132;
	mov.b32 	%f59, %r133;
	mov.b32 	%f60, %r134;
	add.f32 	%f233, %f58, %f59;
	add.f32 	%f234, %f233, %f60;
	setp.eq.f32 	%p32, %f234, 0f00000000;
	@%p32 bra 	$L__BB0_35;

	setp.eq.f32 	%p33, %f58, 0fC2C80000;
	setp.eq.f32 	%p34, %f59, 0fC2C80000;
	or.pred  	%p35, %p33, %p34;
	setp.eq.f32 	%p36, %f60, 0fC2C80000;
	or.pred  	%p37, %p36, %p35;
	mov.f32 	%f464, %f211;
	@%p37 bra 	$L__BB0_35;

	mov.f32 	%f464, 0f00000000;
	mul.f32 	%f237, %f59, %f59;
	fma.rn.f32 	%f238, %f58, %f58, %f237;
	fma.rn.f32 	%f239, %f60, %f60, %f238;
	sqrt.rn.f32 	%f240, %f239;
	add.f32 	%f241, %f240, 0f3A83126F;
	fma.rn.f32 	%f465, %f55, %f241, %f465;
	fma.rn.f32 	%f466, %f56, %f241, %f466;
	fma.rn.f32 	%f467, %f57, %f241, %f467;

$L__BB0_35:
	add.f32 	%f457, %f457, %f464;
	add.s32 	%r260, %r260, 1;
	setp.lt.s32 	%p38, %r260, %r5;
	@%p38 bra 	$L__BB0_8;

	add.s32 	%r258, %r258, 1;
	setp.lt.s32 	%p39, %r258, %r5;
	@%p39 bra 	$L__BB0_7;

$L__BB0_37:
	mul.lo.s32 	%r203, %r5, %r5;
	cvt.rn.f32.s32 	%f242, %r203;
	div.rn.f32 	%f70, %f457, %f242;
	ld.const.f32 	%f71, [params+704];
	setp.lt.f32 	%p40, %f71, 0f00000000;
	@%p40 bra 	$L__BB0_39;
	bra.uni 	$L__BB0_38;

$L__BB0_39:
	neg.f32 	%f73, %f71;
	setp.lt.f32 	%p41, %f71, 0fBF800000;
	@%p41 bra 	$L__BB0_41;
	bra.uni 	$L__BB0_40;

$L__BB0_41:
	mul.f32 	%f248, %f71, 0fBF000000;
	cvt.rzi.f32.f32 	%f249, %f248;
	add.f32 	%f250, %f249, %f249;
	sub.f32 	%f251, %f73, %f250;
	abs.f32 	%f75, %f251;
	abs.f32 	%f76, %f70;
	setp.lt.f32 	%p42, %f76, 0f00800000;
	mul.f32 	%f252, %f76, 0f4B800000;
	selp.f32 	%f253, %f252, %f76, %p42;
	selp.f32 	%f254, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r204, %f253;
	and.b32  	%r205, %r204, 8388607;
	or.b32  	%r206, %r205, 1065353216;
	mov.b32 	%f255, %r206;
	shr.u32 	%r207, %r204, 23;
	cvt.rn.f32.u32 	%f256, %r207;
	add.f32 	%f257, %f254, %f256;
	setp.gt.f32 	%p43, %f255, 0f3FB504F3;
	mul.f32 	%f258, %f255, 0f3F000000;
	add.f32 	%f259, %f257, 0f3F800000;
	selp.f32 	%f260, %f259, %f257, %p43;
	selp.f32 	%f261, %f258, %f255, %p43;
	add.f32 	%f262, %f261, 0fBF800000;
	add.f32 	%f263, %f261, 0f3F800000;
	rcp.approx.ftz.f32 	%f264, %f263;
	add.f32 	%f265, %f262, %f262;
	mul.f32 	%f266, %f265, %f264;
	mul.f32 	%f267, %f266, %f266;
	mov.f32 	%f268, 0f3C4CAF63;
	mov.f32 	%f269, 0f3B18F0FE;
	fma.rn.f32 	%f270, %f269, %f267, %f268;
	mov.f32 	%f271, 0f3DAAAABD;
	fma.rn.f32 	%f272, %f270, %f267, %f271;
	mul.rn.f32 	%f273, %f272, %f267;
	mul.rn.f32 	%f274, %f273, %f266;
	sub.f32 	%f275, %f262, %f266;
	add.f32 	%f276, %f275, %f275;
	neg.f32 	%f277, %f266;
	fma.rn.f32 	%f278, %f277, %f262, %f276;
	mul.rn.f32 	%f279, %f264, %f278;
	add.f32 	%f280, %f274, %f266;
	sub.f32 	%f281, %f266, %f280;
	add.f32 	%f282, %f274, %f281;
	add.f32 	%f283, %f279, %f282;
	add.f32 	%f284, %f280, %f283;
	sub.f32 	%f285, %f280, %f284;
	add.f32 	%f286, %f283, %f285;
	mov.f32 	%f287, 0f3F317200;
	mul.rn.f32 	%f288, %f260, %f287;
	mov.f32 	%f289, 0f35BFBE8E;
	mul.rn.f32 	%f290, %f260, %f289;
	add.f32 	%f291, %f288, %f284;
	sub.f32 	%f292, %f288, %f291;
	add.f32 	%f293, %f284, %f292;
	add.f32 	%f294, %f286, %f293;
	add.f32 	%f295, %f290, %f294;
	add.f32 	%f296, %f291, %f295;
	sub.f32 	%f297, %f291, %f296;
	add.f32 	%f298, %f295, %f297;
	abs.f32 	%f77, %f73;
	setp.gt.f32 	%p44, %f77, 0f77F684DF;
	mul.f32 	%f299, %f71, 0fB9000000;
	selp.f32 	%f300, %f299, %f73, %p44;
	mul.rn.f32 	%f301, %f300, %f296;
	neg.f32 	%f302, %f301;
	fma.rn.f32 	%f303, %f300, %f296, %f302;
	fma.rn.f32 	%f304, %f300, %f298, %f303;
	mov.f32 	%f305, 0f00000000;
	fma.rn.f32 	%f306, %f305, %f296, %f304;
	add.rn.f32 	%f307, %f301, %f306;
	neg.f32 	%f308, %f307;
	add.rn.f32 	%f309, %f301, %f308;
	add.rn.f32 	%f310, %f309, %f306;
	mov.b32 	%r208, %f307;
	setp.eq.s32 	%p45, %r208, 1118925336;
	add.s32 	%r209, %r208, -1;
	mov.b32 	%f311, %r209;
	add.f32 	%f312, %f310, 0f37000000;
	selp.f32 	%f78, %f312, %f310, %p45;
	selp.f32 	%f313, %f311, %f307, %p45;
	mov.f32 	%f314, 0f3FB8AA3B;
	mul.rn.f32 	%f315, %f313, %f314;
	cvt.rzi.f32.f32 	%f316, %f315;
	abs.f32 	%f317, %f316;
	setp.gt.f32 	%p46, %f317, 0f42FC0000;
	mov.b32 	%r210, %f316;
	and.b32  	%r211, %r210, -2147483648;
	or.b32  	%r212, %r211, 1123811328;
	mov.b32 	%f318, %r212;
	selp.f32 	%f319, %f318, %f316, %p46;
	mov.f32 	%f320, 0fBF317218;
	fma.rn.f32 	%f321, %f319, %f320, %f313;
	mov.f32 	%f322, 0f3102E308;
	fma.rn.f32 	%f323, %f319, %f322, %f321;
	mul.f32 	%f324, %f323, 0f3FB8AA3B;
	add.f32 	%f325, %f319, 0f4B40007F;
	mov.b32 	%r213, %f325;
	shl.b32 	%r214, %r213, 23;
	mov.b32 	%f326, %r214;
	ex2.approx.ftz.f32 	%f327, %f324;
	mul.f32 	%f79, %f327, %f326;
	setp.eq.f32 	%p47, %f79, 0f7F800000;
	mov.f32 	%f469, 0f7F800000;
	@%p47 bra 	$L__BB0_43;

	fma.rn.f32 	%f469, %f79, %f78, %f79;

$L__BB0_43:
	setp.lt.f32 	%p48, %f70, 0f00000000;
	setp.eq.f32 	%p49, %f75, 0f3F800000;
	and.pred  	%p1, %p48, %p49;
	setp.eq.f32 	%p50, %f70, 0f00000000;
	@%p50 bra 	$L__BB0_47;
	bra.uni 	$L__BB0_44;

$L__BB0_47:
	add.f32 	%f331, %f70, %f70;
	mov.b32 	%r217, %f331;
	selp.b32 	%r218, %r217, 0, %p49;
	or.b32  	%r219, %r218, 2139095040;
	setp.gt.f32 	%p54, %f71, 0f80000000;
	selp.b32 	%r220, %r219, %r218, %p54;
	mov.b32 	%f471, %r220;
	bra.uni 	$L__BB0_48;

$L__BB0_38:
	add.f32 	%f243, %f70, 0fBF800000;
	fma.rn.f32 	%f244, %f71, %f243, 0f3F800000;
	cvt.sat.f32.f32 	%f472, %f244;
	bra.uni 	$L__BB0_56;

$L__BB0_40:
	add.f32 	%f245, %f70, 0fBF800000;
	fma.rn.f32 	%f246, %f245, %f73, 0f3F800000;
	cvt.sat.f32.f32 	%f472, %f246;
	bra.uni 	$L__BB0_56;

$L__BB0_77:
	mov.f32 	%f442, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f442;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f442;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f442;}

	// end inline asm
	mov.u16 	%rs46, 0;
	st.global.v4.u16 	[%rd19], {%rs43, %rs44, %rs45, %rs46};

$L__BB0_78:
	and.b32  	%r254, %r49, 8;
	setp.eq.s32 	%p88, %r254, 0;
	@%p88 bra 	$L__BB0_80;

	ld.const.u64 	%rd65, [params+192];
	cvta.to.global.u64 	%rd66, %rd65;
	ld.const.u32 	%r255, [params+184];
	mad.lo.s32 	%r256, %r255, %r4, %r3;
	mov.f32 	%f443, 0f00000000;
	cvt.rzi.u32.f32 	%r257, %f443;
	mul.wide.u32 	%rd67, %r256, 2;
	add.s64 	%rd68, %rd66, %rd67;
	mov.u16 	%rs47, 0;
	cvt.u16.u32 	%rs48, %r257;
	st.global.v2.u8 	[%rd68], {%rs48, %rs47};
	bra.uni 	$L__BB0_80;

$L__BB0_44:
	mov.b32 	%r215, %f469;
	xor.b32  	%r216, %r215, -2147483648;
	mov.b32 	%f328, %r216;
	selp.f32 	%f471, %f328, %f469, %p1;
	setp.geu.f32 	%p51, %f70, 0f00000000;
	@%p51 bra 	$L__BB0_48;

	cvt.rzi.f32.f32 	%f329, %f73;
	setp.eq.f32 	%p52, %f329, %f73;
	@%p52 bra 	$L__BB0_48;

	mov.f32 	%f471, 0f7FFFFFFF;

$L__BB0_48:
	add.f32 	%f332, %f76, %f77;
	mov.b32 	%r221, %f332;
	setp.lt.s32 	%p55, %r221, 2139095040;
	@%p55 bra 	$L__BB0_55;

	setp.gtu.f32 	%p56, %f76, 0f7F800000;
	setp.gtu.f32 	%p57, %f77, 0f7F800000;
	or.pred  	%p58, %p56, %p57;
	@%p58 bra 	$L__BB0_54;
	bra.uni 	$L__BB0_50;

$L__BB0_54:
	sub.f32 	%f471, %f70, %f71;
	bra.uni 	$L__BB0_55;

$L__BB0_50:
	setp.eq.f32 	%p59, %f77, 0f7F800000;
	@%p59 bra 	$L__BB0_53;
	bra.uni 	$L__BB0_51;

$L__BB0_53:
	setp.gt.f32 	%p62, %f76, 0f3F800000;
	selp.b32 	%r225, 2139095040, 0, %p62;
	xor.b32  	%r226, %r225, 2139095040;
	setp.gt.f32 	%p63, %f71, 0f80000000;
	selp.b32 	%r227, %r226, %r225, %p63;
	mov.b32 	%f333, %r227;
	setp.eq.f32 	%p64, %f70, 0fBF800000;
	selp.f32 	%f471, 0f3F800000, %f333, %p64;
	bra.uni 	$L__BB0_55;

$L__BB0_51:
	setp.neu.f32 	%p60, %f76, 0f7F800000;
	@%p60 bra 	$L__BB0_55;

	setp.le.f32 	%p61, %f71, 0f80000000;
	selp.b32 	%r222, 2139095040, 0, %p61;
	or.b32  	%r223, %r222, -2147483648;
	selp.b32 	%r224, %r223, %r222, %p1;
	mov.b32 	%f471, %r224;

$L__BB0_55:
	setp.eq.f32 	%p65, %f71, 0f80000000;
	setp.eq.f32 	%p66, %f70, 0f3F800000;
	or.pred  	%p67, %p65, %p66;
	selp.f32 	%f334, 0f3F800000, %f471, %p67;
	cvt.sat.f32.f32 	%f472, %f334;

$L__BB0_56:
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r228, %r48, 4;
	setp.eq.s32 	%p68, %r228, 0;
	@%p68 bra 	$L__BB0_60;

	ld.const.u32 	%r229, [params+108];
	setp.eq.s32 	%p69, %r229, 0;
	ld.const.u64 	%rd56, [params+224];
	cvta.to.global.u64 	%rd57, %rd56;
	ld.const.u32 	%r230, [params+216];
	mad.lo.s32 	%r231, %r230, %r4, %r3;
	mul.wide.u32 	%rd58, %r231, 8;
	add.s64 	%rd16, %rd57, %rd58;
	@%p69 bra 	$L__BB0_59;

	ld.global.v4.u16 	{%rs22, %rs23, %rs24, %rs25}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f335, %rs22;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f336, %rs23;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f337, %rs24;}

	// end inline asm
	add.f32 	%f338, %f472, %f335;
	add.f32 	%f339, %f472, %f336;
	add.f32 	%f340, %f472, %f337;
	mov.f32 	%f341, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs20, %f340;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs19, %f339;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs18, %f338;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs21, %f341;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs18, %rs19, %rs20, %rs21};
	bra.uni 	$L__BB0_60;

$L__BB0_59:
	mov.f32 	%f345, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f345;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f472;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f472;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f472;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs26, %rs27, %rs28, %rs29};

$L__BB0_60:
	and.b32  	%r232, %r48, 8;
	setp.eq.s32 	%p70, %r232, 0;
	@%p70 bra 	$L__BB0_80;

	ld.const.u64 	%rd59, [params+192];
	cvta.to.global.u64 	%rd17, %rd59;
	ld.const.u32 	%r233, [params+184];
	mad.lo.s32 	%r234, %r233, %r4, %r3;
	cvt.u64.u32 	%rd18, %r234;
	mov.f32 	%f347, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f348, %f347;
	add.f32 	%f349, %f348, %f348;
	mov.f32 	%f350, 0f3EE8BA2E;
	sub.f32 	%f351, %f350, %f349;
	abs.f32 	%f91, %f351;
	abs.f32 	%f92, %f472;
	setp.lt.f32 	%p71, %f92, 0f00800000;
	mul.f32 	%f352, %f92, 0f4B800000;
	selp.f32 	%f353, %f352, %f92, %p71;
	selp.f32 	%f354, 0fC3170000, 0fC2FE0000, %p71;
	mov.b32 	%r235, %f353;
	and.b32  	%r236, %r235, 8388607;
	or.b32  	%r237, %r236, 1065353216;
	mov.b32 	%f355, %r237;
	shr.u32 	%r238, %r235, 23;
	cvt.rn.f32.u32 	%f356, %r238;
	add.f32 	%f357, %f354, %f356;
	setp.gt.f32 	%p72, %f355, 0f3FB504F3;
	mul.f32 	%f358, %f355, 0f3F000000;
	add.f32 	%f359, %f357, 0f3F800000;
	selp.f32 	%f360, %f359, %f357, %p72;
	selp.f32 	%f361, %f358, %f355, %p72;
	add.f32 	%f362, %f361, 0fBF800000;
	add.f32 	%f363, %f361, 0f3F800000;
	rcp.approx.ftz.f32 	%f364, %f363;
	add.f32 	%f365, %f362, %f362;
	mul.f32 	%f366, %f365, %f364;
	mul.f32 	%f367, %f366, %f366;
	mov.f32 	%f368, 0f3C4CAF63;
	mov.f32 	%f369, 0f3B18F0FE;
	fma.rn.f32 	%f370, %f369, %f367, %f368;
	mov.f32 	%f371, 0f3DAAAABD;
	fma.rn.f32 	%f372, %f370, %f367, %f371;
	mul.rn.f32 	%f373, %f372, %f367;
	mul.rn.f32 	%f374, %f373, %f366;
	sub.f32 	%f375, %f362, %f366;
	add.f32 	%f376, %f375, %f375;
	neg.f32 	%f377, %f366;
	fma.rn.f32 	%f378, %f377, %f362, %f376;
	mul.rn.f32 	%f379, %f364, %f378;
	add.f32 	%f380, %f374, %f366;
	sub.f32 	%f381, %f366, %f380;
	add.f32 	%f382, %f374, %f381;
	add.f32 	%f383, %f379, %f382;
	add.f32 	%f384, %f380, %f383;
	sub.f32 	%f385, %f380, %f384;
	add.f32 	%f386, %f383, %f385;
	mov.f32 	%f387, 0f3F317200;
	mul.rn.f32 	%f388, %f360, %f387;
	mov.f32 	%f389, 0f35BFBE8E;
	mul.rn.f32 	%f390, %f360, %f389;
	add.f32 	%f391, %f388, %f384;
	sub.f32 	%f392, %f388, %f391;
	add.f32 	%f393, %f384, %f392;
	add.f32 	%f394, %f386, %f393;
	add.f32 	%f395, %f390, %f394;
	add.f32 	%f396, %f391, %f395;
	sub.f32 	%f397, %f391, %f396;
	add.f32 	%f398, %f395, %f397;
	mul.rn.f32 	%f399, %f350, %f396;
	neg.f32 	%f400, %f399;
	fma.rn.f32 	%f401, %f350, %f396, %f400;
	fma.rn.f32 	%f402, %f350, %f398, %f401;
	mov.f32 	%f403, 0f00000000;
	fma.rn.f32 	%f404, %f403, %f396, %f402;
	add.rn.f32 	%f405, %f399, %f404;
	neg.f32 	%f406, %f405;
	add.rn.f32 	%f407, %f399, %f406;
	add.rn.f32 	%f408, %f407, %f404;
	mov.b32 	%r239, %f405;
	setp.eq.s32 	%p73, %r239, 1118925336;
	add.s32 	%r240, %r239, -1;
	mov.b32 	%f409, %r240;
	add.f32 	%f410, %f408, 0f37000000;
	selp.f32 	%f93, %f410, %f408, %p73;
	selp.f32 	%f411, %f409, %f405, %p73;
	mov.f32 	%f412, 0f3FB8AA3B;
	mul.rn.f32 	%f413, %f411, %f412;
	cvt.rzi.f32.f32 	%f414, %f413;
	abs.f32 	%f415, %f414;
	setp.gt.f32 	%p74, %f415, 0f42FC0000;
	mov.b32 	%r241, %f414;
	and.b32  	%r242, %r241, -2147483648;
	or.b32  	%r243, %r242, 1123811328;
	mov.b32 	%f416, %r243;
	selp.f32 	%f417, %f416, %f414, %p74;
	mov.f32 	%f418, 0fBF317218;
	fma.rn.f32 	%f419, %f417, %f418, %f411;
	mov.f32 	%f420, 0f3102E308;
	fma.rn.f32 	%f421, %f417, %f420, %f419;
	mul.f32 	%f422, %f421, 0f3FB8AA3B;
	add.f32 	%f423, %f417, 0f4B40007F;
	mov.b32 	%r244, %f423;
	shl.b32 	%r245, %r244, 23;
	mov.b32 	%f424, %r245;
	ex2.approx.ftz.f32 	%f425, %f422;
	mul.f32 	%f94, %f425, %f424;
	setp.eq.f32 	%p75, %f94, 0f7F800000;
	mov.f32 	%f473, 0f7F800000;
	@%p75 bra 	$L__BB0_63;

	fma.rn.f32 	%f473, %f94, %f93, %f94;

$L__BB0_63:
	setp.lt.f32 	%p76, %f472, 0f00000000;
	setp.eq.f32 	%p77, %f91, 0f3F800000;
	and.pred  	%p2, %p76, %p77;
	setp.eq.f32 	%p78, %f472, 0f00000000;
	@%p78 bra 	$L__BB0_67;
	bra.uni 	$L__BB0_64;

$L__BB0_67:
	add.f32 	%f430, %f472, %f472;
	selp.f32 	%f475, %f430, 0f00000000, %p77;
	bra.uni 	$L__BB0_68;

$L__BB0_64:
	mov.b32 	%r246, %f473;
	xor.b32  	%r247, %r246, -2147483648;
	mov.b32 	%f426, %r247;
	selp.f32 	%f475, %f426, %f473, %p2;
	setp.geu.f32 	%p79, %f472, 0f00000000;
	@%p79 bra 	$L__BB0_68;

	mov.f32 	%f427, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f428, %f427;
	setp.eq.f32 	%p80, %f428, 0f3EE8BA2E;
	@%p80 bra 	$L__BB0_68;

	mov.f32 	%f475, 0f7FFFFFFF;

$L__BB0_68:
	add.f32 	%f431, %f92, 0f3EE8BA2E;
	mov.b32 	%r248, %f431;
	setp.lt.s32 	%p82, %r248, 2139095040;
	@%p82 bra 	$L__BB0_73;

	setp.gtu.f32 	%p83, %f92, 0f7F800000;
	@%p83 bra 	$L__BB0_72;
	bra.uni 	$L__BB0_70;

$L__BB0_72:
	add.f32 	%f475, %f472, 0f3EE8BA2E;
	bra.uni 	$L__BB0_73;

$L__BB0_70:
	setp.neu.f32 	%p84, %f92, 0f7F800000;
	@%p84 bra 	$L__BB0_73;

	selp.f32 	%f475, 0fFF800000, 0f7F800000, %p2;

$L__BB0_73:
	mul.f32 	%f432, %f475, 0f437F0000;
	setp.eq.f32 	%p85, %f472, 0f3F800000;
	selp.f32 	%f433, 0f437F0000, %f432, %p85;
	cvt.rzi.u32.f32 	%r249, %f433;
	shl.b64 	%rd60, %rd18, 1;
	add.s64 	%rd61, %rd17, %rd60;
	cvt.u16.u32 	%rs30, %r249;
	mov.u16 	%rs31, 255;
	st.global.v2.u8 	[%rd61], {%rs30, %rs31};

$L__BB0_80:
	ret;

}