//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];

.visible .entry __raygen__oxMain()
{
	.reg .pred 	%p<193>;
	.reg .b16 	%rs<330>;
	.reg .f32 	%f<1923>;
	.reg .b32 	%r<450>;
	.reg .b64 	%rd<118>;


	// begin inline asm
	call (%r26), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r27), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd31, [params+400];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r32, [params+392];
	mad.lo.s32 	%r33, %r32, %r27, %r26;
	mul.wide.u32 	%rd33, %r33, 4;
	add.s64 	%rd1, %rd32, %rd33;
	ld.global.v2.u8 	{%rs9, %rs328}, [%rd1];
	or.b16  	%rs11, %rs9, %rs328;
	and.b16  	%rs12, %rs11, 255;
	setp.eq.s16 	%p10, %rs12, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs327, [%rd1+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs327, [%rd1+2];
	setp.eq.s16 	%p11, %rs327, 0;
	mov.f32 	%f1749, 0f00000000;
	mov.u16 	%rs328, 0;
	mov.f32 	%f1750, %f1749;
	mov.f32 	%f1751, %f1749;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f405, %rs9;
	div.rn.f32 	%f406, %f405, 0f437F0000;
	fma.rn.f32 	%f407, %f406, 0f40000000, 0fBF800000;
	and.b16  	%rs15, %rs328, 255;
	cvt.rn.f32.u16 	%f408, %rs15;
	div.rn.f32 	%f409, %f408, 0f437F0000;
	fma.rn.f32 	%f410, %f409, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f411, %rs327;
	div.rn.f32 	%f412, %f411, 0f437F0000;
	fma.rn.f32 	%f413, %f412, 0f40000000, 0fBF800000;
	mul.f32 	%f414, %f410, %f410;
	fma.rn.f32 	%f415, %f407, %f407, %f414;
	fma.rn.f32 	%f416, %f413, %f413, %f415;
	sqrt.rn.f32 	%f417, %f416;
	rcp.rn.f32 	%f418, %f417;
	mul.f32 	%f1751, %f418, %f413;
	mul.f32 	%f1750, %f418, %f410;
	mul.f32 	%f1749, %f407, %f418;

$L__BB0_4:
	ld.const.v2.u32 	{%r34, %r35}, [params];
	add.s32 	%r3, %r34, %r26;
	add.s32 	%r4, %r35, %r27;
	setp.eq.f32 	%p12, %f1749, 0f00000000;
	setp.eq.f32 	%p13, %f1750, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1751, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_164;
	bra.uni 	$L__BB0_5;

$L__BB0_164:
	ld.const.u32 	%r23, [params+104];
	and.b32  	%r414, %r23, 1;
	setp.eq.b32 	%p176, %r414, 1;
	mov.pred 	%p177, 0;
	xor.pred  	%p178, %p176, %p177;
	not.pred 	%p179, %p178;
	@%p179 bra 	$L__BB0_166;

	ld.const.u64 	%rd79, [params+144];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r415, [params+136];
	mad.lo.s32 	%r416, %r415, %r4, %r3;
	mul.wide.u32 	%rd81, %r416, 4;
	add.s64 	%rd82, %rd80, %rd81;
	mov.u16 	%rs174, 0;
	st.global.v4.u8 	[%rd82], {%rs174, %rs174, %rs174, %rs174};

$L__BB0_166:
	and.b32  	%r417, %r23, 8;
	setp.eq.s32 	%p180, %r417, 0;
	@%p180 bra 	$L__BB0_168;

	ld.const.u64 	%rd83, [params+192];
	cvta.to.global.u64 	%rd84, %rd83;
	ld.const.u32 	%r418, [params+184];
	mad.lo.s32 	%r419, %r418, %r4, %r3;
	mov.f32 	%f1655, 0f00000000;
	cvt.rzi.u32.f32 	%r420, %f1655;
	mul.wide.u32 	%rd85, %r419, 2;
	add.s64 	%rd86, %rd84, %rd85;
	mov.u16 	%rs175, 0;
	cvt.u16.u32 	%rs176, %r420;
	st.global.v2.u8 	[%rd86], {%rs176, %rs175};

$L__BB0_168:
	and.b32  	%r421, %r23, 4;
	setp.eq.s32 	%p181, %r421, 0;
	ld.const.u32 	%r449, [params+108];
	@%p181 bra 	$L__BB0_172;

	setp.eq.s32 	%p182, %r449, 0;
	ld.const.u64 	%rd87, [params+224];
	cvta.to.global.u64 	%rd88, %rd87;
	ld.const.u32 	%r422, [params+216];
	mad.lo.s32 	%r423, %r422, %r4, %r3;
	mul.wide.u32 	%rd89, %r423, 8;
	add.s64 	%rd21, %rd88, %rd89;
	@%p182 bra 	$L__BB0_171;

	ld.global.v4.u16 	{%rs183, %rs184, %rs185, %rs186}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1656, %rs183;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1657, %rs184;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1658, %rs185;}

	// end inline asm
	add.f32 	%f1659, %f1656, 0f00000000;
	add.f32 	%f1660, %f1657, 0f00000000;
	add.f32 	%f1661, %f1658, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs182, %f1661;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs181, %f1660;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs180, %f1659;}

	// end inline asm
	mov.u16 	%rs187, 0;
	st.global.v4.u16 	[%rd21], {%rs180, %rs181, %rs182, %rs187};
	bra.uni 	$L__BB0_172;

$L__BB0_5:
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r38, [params+424];
	mad.lo.s32 	%r39, %r38, %r27, %r26;
	mul.wide.u32 	%rd36, %r39, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f10, [%rd37];
	mul.f32 	%f419, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd37+4];
	mul.f32 	%f420, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd37+8];
	mul.f32 	%f421, %f12, 0f3456BF95;
	abs.f32 	%f422, %f1749;
	div.rn.f32 	%f423, %f419, %f422;
	abs.f32 	%f424, %f1750;
	div.rn.f32 	%f425, %f420, %f424;
	abs.f32 	%f426, %f1751;
	div.rn.f32 	%f427, %f421, %f426;
	abs.f32 	%f428, %f423;
	abs.f32 	%f429, %f425;
	abs.f32 	%f430, %f427;
	mov.f32 	%f431, 0f38D1B717;
	max.f32 	%f432, %f428, %f431;
	max.f32 	%f433, %f429, %f431;
	max.f32 	%f434, %f430, %f431;
	fma.rn.f32 	%f13, %f1749, %f432, %f10;
	fma.rn.f32 	%f14, %f1750, %f433, %f11;
	fma.rn.f32 	%f15, %f1751, %f434, %f12;
	cvt.rn.f32.u32 	%f16, %r26;
	cvt.rn.f32.u32 	%f17, %r27;
	ld.const.u32 	%r5, [params+600];
	setp.eq.s32 	%p17, %r5, 0;
	@%p17 bra 	$L__BB0_44;

	ld.const.u64 	%rd38, [params+608];
	cvta.to.global.u64 	%rd2, %rd38;
	mov.f32 	%f466, 0f40000000;
	cvt.rzi.f32.f32 	%f467, %f466;
	add.f32 	%f468, %f467, %f467;
	mov.f32 	%f469, 0f40800000;
	sub.f32 	%f470, %f469, %f468;
	abs.f32 	%f18, %f470;
	ld.const.u32 	%r6, [params+544];
	ld.const.u32 	%r447, [params+104];
	mul.f32 	%f19, %f13, 0f3456BF95;
	mul.f32 	%f20, %f14, 0f3456BF95;
	mul.f32 	%f21, %f15, 0f3456BF95;
	mov.f32 	%f465, 0f00000000;
	mov.u32 	%r443, 0;
	ld.const.u64 	%rd3, [params+96];
	abs.f32 	%f696, %f19;
	abs.f32 	%f697, %f20;
	max.f32 	%f698, %f696, %f697;
	abs.f32 	%f699, %f21;
	max.f32 	%f700, %f698, %f699;
	mov.f32 	%f1870, %f465;
	mov.f32 	%f1869, %f465;
	mov.f32 	%f1868, %f465;
	mov.f32 	%f1867, %f465;
	mov.f32 	%f1866, %f465;
	mov.f32 	%f1865, %f465;
	mov.f32 	%f1864, %f465;
	mov.f32 	%f1863, %f465;
	mov.f32 	%f1862, %f465;
	mov.f32 	%f1861, %f465;
	mov.f32 	%f1860, %f465;
	mov.f32 	%f1859, %f465;
	mov.f32 	%f1858, %f465;
	mov.f32 	%f1857, %f465;
	mov.f32 	%f1856, %f465;
	mov.f32 	%f1855, %f465;
	mov.f32 	%f1854, %f465;
	mov.f32 	%f1853, %f465;
	mov.f32 	%f1852, %f465;
	mov.f32 	%f1851, %f465;
	mov.f32 	%f1850, %f465;
	mov.f32 	%f1849, %f465;
	mov.f32 	%f1848, %f465;
	mov.f32 	%f1847, %f465;
	mov.f32 	%f1846, %f465;
	mov.f32 	%f1845, %f465;
	mov.f32 	%f1844, %f465;
	mov.f32 	%f1843, %f465;
	mov.f32 	%f1842, %f465;
	mov.f32 	%f1841, %f465;
	mov.f32 	%f1840, %f465;

$L__BB0_7:
	mul.wide.u32 	%rd39, %r443, 112;
	add.s64 	%rd5, %rd2, %rd39;
	ld.global.v4.f32 	{%f472, %f473, %f474, %f475}, [%rd5];
	ld.global.v4.f32 	{%f479, %f480, %f481, %f482}, [%rd5+16];
	ld.global.v4.f32 	{%f485, %f1791, %f1792, %f488}, [%rd5+32];
	ld.global.v4.f32 	{%f489, %f490, %f491, %f1789}, [%rd5+48];
	ld.global.v4.f32 	{%f493, %f494, %f495, %f496}, [%rd5+64];
	ld.global.v4.u32 	{%r41, %r42, %r43, %r44}, [%rd5+80];
	mov.b32 	%f66, %r41;
	mov.b32 	%f67, %r42;
	mov.b32 	%f68, %r43;
	ld.global.u64 	%rd6, [%rd5+96];
	sub.f32 	%f69, %f473, %f10;
	sub.f32 	%f70, %f474, %f11;
	sub.f32 	%f71, %f475, %f12;
	mul.f32 	%f497, %f70, %f70;
	fma.rn.f32 	%f498, %f69, %f69, %f497;
	fma.rn.f32 	%f499, %f71, %f71, %f498;
	sqrt.rn.f32 	%f500, %f499;
	rcp.rn.f32 	%f501, %f500;
	mul.f32 	%f72, %f69, %f501;
	mul.f32 	%f73, %f70, %f501;
	mul.f32 	%f74, %f71, %f501;
	mul.f32 	%f75, %f500, %f480;
	mul.f32 	%f76, %f500, %f482;
	abs.f32 	%f77, %f76;
	setp.lt.f32 	%p18, %f77, 0f00800000;
	mul.f32 	%f502, %f77, 0f4B800000;
	selp.f32 	%f503, %f502, %f77, %p18;
	selp.f32 	%f504, 0fC3170000, 0fC2FE0000, %p18;
	mov.b32 	%r48, %f503;
	and.b32  	%r49, %r48, 8388607;
	or.b32  	%r50, %r49, 1065353216;
	mov.b32 	%f505, %r50;
	shr.u32 	%r51, %r48, 23;
	cvt.rn.f32.u32 	%f506, %r51;
	add.f32 	%f507, %f504, %f506;
	setp.gt.f32 	%p19, %f505, 0f3FB504F3;
	mul.f32 	%f508, %f505, 0f3F000000;
	add.f32 	%f509, %f507, 0f3F800000;
	selp.f32 	%f510, %f509, %f507, %p19;
	selp.f32 	%f511, %f508, %f505, %p19;
	add.f32 	%f512, %f511, 0fBF800000;
	add.f32 	%f513, %f511, 0f3F800000;
	rcp.approx.ftz.f32 	%f514, %f513;
	add.f32 	%f515, %f512, %f512;
	mul.f32 	%f516, %f515, %f514;
	mul.f32 	%f517, %f516, %f516;
	mov.f32 	%f518, 0f3C4CAF63;
	mov.f32 	%f519, 0f3B18F0FE;
	fma.rn.f32 	%f520, %f519, %f517, %f518;
	mov.f32 	%f521, 0f3DAAAABD;
	fma.rn.f32 	%f522, %f520, %f517, %f521;
	mul.rn.f32 	%f523, %f522, %f517;
	mul.rn.f32 	%f524, %f523, %f516;
	sub.f32 	%f525, %f512, %f516;
	add.f32 	%f526, %f525, %f525;
	neg.f32 	%f527, %f516;
	fma.rn.f32 	%f528, %f527, %f512, %f526;
	mul.rn.f32 	%f529, %f514, %f528;
	add.f32 	%f530, %f524, %f516;
	sub.f32 	%f531, %f516, %f530;
	add.f32 	%f532, %f524, %f531;
	add.f32 	%f533, %f529, %f532;
	add.f32 	%f534, %f530, %f533;
	sub.f32 	%f535, %f530, %f534;
	add.f32 	%f536, %f533, %f535;
	mov.f32 	%f537, 0f3F317200;
	mul.rn.f32 	%f538, %f510, %f537;
	mov.f32 	%f539, 0f35BFBE8E;
	mul.rn.f32 	%f540, %f510, %f539;
	add.f32 	%f541, %f538, %f534;
	sub.f32 	%f542, %f538, %f541;
	add.f32 	%f543, %f534, %f542;
	add.f32 	%f544, %f536, %f543;
	add.f32 	%f545, %f540, %f544;
	add.f32 	%f546, %f541, %f545;
	sub.f32 	%f547, %f541, %f546;
	add.f32 	%f548, %f545, %f547;
	mul.rn.f32 	%f550, %f469, %f546;
	neg.f32 	%f551, %f550;
	fma.rn.f32 	%f552, %f469, %f546, %f551;
	fma.rn.f32 	%f553, %f469, %f548, %f552;
	fma.rn.f32 	%f555, %f465, %f546, %f553;
	add.rn.f32 	%f556, %f550, %f555;
	neg.f32 	%f557, %f556;
	add.rn.f32 	%f558, %f550, %f557;
	add.rn.f32 	%f559, %f558, %f555;
	mov.b32 	%r52, %f556;
	setp.eq.s32 	%p20, %r52, 1118925336;
	add.s32 	%r53, %r52, -1;
	mov.b32 	%f560, %r53;
	add.f32 	%f561, %f559, 0f37000000;
	selp.f32 	%f78, %f561, %f559, %p20;
	selp.f32 	%f562, %f560, %f556, %p20;
	mov.f32 	%f563, 0f3FB8AA3B;
	mul.rn.f32 	%f564, %f562, %f563;
	cvt.rzi.f32.f32 	%f565, %f564;
	abs.f32 	%f566, %f565;
	setp.gt.f32 	%p21, %f566, 0f42FC0000;
	mov.b32 	%r54, %f565;
	and.b32  	%r55, %r54, -2147483648;
	or.b32  	%r56, %r55, 1123811328;
	mov.b32 	%f567, %r56;
	selp.f32 	%f568, %f567, %f565, %p21;
	mov.f32 	%f569, 0fBF317218;
	fma.rn.f32 	%f570, %f568, %f569, %f562;
	mov.f32 	%f571, 0f3102E308;
	fma.rn.f32 	%f572, %f568, %f571, %f570;
	mul.f32 	%f573, %f572, 0f3FB8AA3B;
	add.f32 	%f574, %f568, 0f4B40007F;
	mov.b32 	%r57, %f574;
	shl.b32 	%r58, %r57, 23;
	mov.b32 	%f575, %r58;
	ex2.approx.ftz.f32 	%f576, %f573;
	mul.f32 	%f79, %f576, %f575;
	setp.eq.f32 	%p22, %f79, 0f7F800000;
	mov.f32 	%f1783, 0f7F800000;
	@%p22 bra 	$L__BB0_9;

	fma.rn.f32 	%f1783, %f79, %f78, %f79;

$L__BB0_9:
	setp.lt.f32 	%p23, %f76, 0f00000000;
	setp.eq.f32 	%p24, %f18, 0f3F800000;
	and.pred  	%p1, %p23, %p24;
	setp.eq.f32 	%p25, %f76, 0f00000000;
	@%p25 bra 	$L__BB0_13;
	bra.uni 	$L__BB0_10;

$L__BB0_13:
	add.f32 	%f581, %f76, %f76;
	selp.f32 	%f1785, %f581, 0f00000000, %p24;
	bra.uni 	$L__BB0_14;

$L__BB0_10:
	mov.b32 	%r59, %f1783;
	xor.b32  	%r60, %r59, -2147483648;
	mov.b32 	%f577, %r60;
	selp.f32 	%f1785, %f577, %f1783, %p1;
	setp.geu.f32 	%p26, %f76, 0f00000000;
	@%p26 bra 	$L__BB0_14;

	mov.f32 	%f578, 0f40800000;
	cvt.rzi.f32.f32 	%f579, %f578;
	setp.eq.f32 	%p27, %f579, 0f40800000;
	@%p27 bra 	$L__BB0_14;

	mov.f32 	%f1785, 0f7FFFFFFF;

$L__BB0_14:
	abs.f32 	%f1746, %f76;
	add.f32 	%f582, %f1746, 0f40800000;
	mov.b32 	%r61, %f582;
	setp.lt.s32 	%p29, %r61, 2139095040;
	@%p29 bra 	$L__BB0_19;

	abs.f32 	%f1747, %f76;
	setp.gtu.f32 	%p30, %f1747, 0f7F800000;
	@%p30 bra 	$L__BB0_18;
	bra.uni 	$L__BB0_16;

$L__BB0_18:
	add.f32 	%f1785, %f76, 0f40800000;
	bra.uni 	$L__BB0_19;

$L__BB0_16:
	abs.f32 	%f1748, %f76;
	setp.neu.f32 	%p31, %f1748, 0f7F800000;
	@%p31 bra 	$L__BB0_19;

	selp.f32 	%f1785, 0fFF800000, 0f7F800000, %p1;

$L__BB0_19:
	mov.f32 	%f583, 0f3F800000;
	sub.f32 	%f584, %f583, %f1785;
	setp.eq.f32 	%p32, %f76, 0f3F800000;
	selp.f32 	%f585, 0f00000000, %f584, %p32;
	cvt.sat.f32.f32 	%f586, %f585;
	fma.rn.f32 	%f587, %f75, %f75, %f481;
	div.rn.f32 	%f88, %f586, %f587;
	mul.f32 	%f588, %f1750, %f73;
	fma.rn.f32 	%f589, %f1749, %f72, %f588;
	fma.rn.f32 	%f89, %f1751, %f74, %f589;
	setp.eq.f32 	%p33, %f472, 0f3F800000;
	@%p33 bra 	$L__BB0_25;
	bra.uni 	$L__BB0_20;

$L__BB0_25:
	setp.eq.s64 	%p37, %rd6, 0;
	mov.f32 	%f1790, %f485;
	mov.f32 	%f1793, %f88;
	@%p37 bra 	$L__BB0_29;

	setp.geu.f32 	%p38, %f1789, 0f00000000;
	mov.f32 	%f1786, %f72;
	mov.f32 	%f1787, %f73;
	mov.f32 	%f1788, %f74;
	@%p38 bra 	$L__BB0_28;

	mul.f32 	%f612, %f67, %f70;
	fma.rn.f32 	%f613, %f66, %f69, %f612;
	fma.rn.f32 	%f614, %f68, %f71, %f613;
	rcp.rn.f32 	%f615, %f614;
	mul.f32 	%f1786, %f69, %f615;
	mul.f32 	%f1787, %f70, %f615;
	mul.f32 	%f1788, %f71, %f615;
	neg.f32 	%f1789, %f1789;

$L__BB0_28:
	mul.f32 	%f616, %f68, %f74;
	mul.f32 	%f617, %f67, %f73;
	neg.f32 	%f618, %f617;
	mul.f32 	%f619, %f66, %f72;
	sub.f32 	%f620, %f618, %f619;
	sub.f32 	%f621, %f620, %f616;
	setp.gt.f32 	%p39, %f621, 0f00000000;
	selp.f32 	%f622, 0f3F800000, 0f00000000, %p39;
	mov.f32 	%f623, 0f3F800000;
	mul.f32 	%f624, %f490, %f1787;
	fma.rn.f32 	%f625, %f489, %f1786, %f624;
	mul.f32 	%f626, %f494, %f1787;
	fma.rn.f32 	%f627, %f493, %f1786, %f626;
	fma.rn.f32 	%f628, %f491, %f1788, %f625;
	fma.rn.f32 	%f629, %f495, %f1788, %f627;
	fma.rn.f32 	%f630, %f1789, %f628, 0f3F000000;
	sub.f32 	%f631, %f623, %f630;
	fma.rn.f32 	%f632, %f1789, %f629, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f633, %f634, %f635, %f636}, [%rd6, {%f631, %f632}];
	mul.f32 	%f637, %f622, %f633;
	mul.f32 	%f638, %f622, %f634;
	mul.f32 	%f639, %f622, %f635;
	mul.f32 	%f1790, %f485, %f637;
	mul.f32 	%f1791, %f1791, %f638;
	mul.f32 	%f1792, %f1792, %f639;
	mov.f32 	%f1793, %f88;
	bra.uni 	$L__BB0_29;

$L__BB0_20:
	setp.eq.f32 	%p34, %f472, 0f40000000;
	@%p34 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_21;

$L__BB0_23:
	setp.eq.s64 	%p36, %rd6, 0;
	mov.f32 	%f1790, %f485;
	mov.f32 	%f1793, %f88;
	@%p36 bra 	$L__BB0_29;

	mul.f32 	%f599, %f490, %f73;
	fma.rn.f32 	%f600, %f489, %f72, %f599;
	mul.f32 	%f601, %f494, %f73;
	fma.rn.f32 	%f602, %f493, %f72, %f601;
	mul.f32 	%f603, %f67, %f73;
	fma.rn.f32 	%f604, %f66, %f72, %f603;
	fma.rn.f32 	%f605, %f491, %f74, %f600;
	fma.rn.f32 	%f606, %f495, %f74, %f602;
	fma.rn.f32 	%f607, %f68, %f74, %f604;
	tex.cube.v4.f32.f32 	{%f608, %f609, %f610, %f611}, [%rd6, {%f605, %f606, %f607, %f607}];
	mul.f32 	%f1790, %f485, %f608;
	mul.f32 	%f1791, %f1791, %f609;
	mul.f32 	%f1792, %f1792, %f610;
	mov.f32 	%f1793, %f88;
	bra.uni 	$L__BB0_29;

$L__BB0_21:
	setp.neu.f32 	%p35, %f472, 0f40800000;
	mov.f32 	%f1790, %f485;
	mov.f32 	%f1793, %f88;
	@%p35 bra 	$L__BB0_29;

	mul.f32 	%f590, %f66, %f72;
	mul.f32 	%f591, %f67, %f73;
	neg.f32 	%f592, %f591;
	sub.f32 	%f593, %f592, %f590;
	mul.f32 	%f594, %f68, %f74;
	sub.f32 	%f595, %f593, %f594;
	fma.rn.f32 	%f596, %f488, %f595, %f1789;
	cvt.sat.f32.f32 	%f597, %f596;
	mul.f32 	%f598, %f597, %f597;
	mul.f32 	%f1793, %f88, %f598;
	mov.f32 	%f1790, %f485;

$L__BB0_29:
	max.f32 	%f670, %f1790, %f1791;
	max.f32 	%f671, %f670, %f1792;
	mul.f32 	%f672, %f1793, %f671;
	setp.lt.f32 	%p41, %f672, 0f3727C5AC;
	mov.pred 	%p192, -1;
	mov.f32 	%f1794, 0f00000000;
	mov.f32 	%f1795, %f1794;
	mov.f32 	%f1796, %f1794;
	mov.f32 	%f1797, %f1794;
	mov.f32 	%f1798, %f1794;
	mov.f32 	%f1799, %f1794;
	mov.f32 	%f1800, %f1794;
	mov.f32 	%f1801, %f1794;
	mov.f32 	%f1802, %f1794;
	mov.f32 	%f1803, %f1794;
	mov.f32 	%f1804, %f1794;
	mov.f32 	%f1805, %f1794;
	mov.f32 	%f1806, %f1794;
	mov.f32 	%f1807, %f1794;
	mov.f32 	%f1808, %f1794;
	mov.f32 	%f1809, %f1794;
	mov.f32 	%f1810, %f1794;
	mov.f32 	%f1811, %f1794;
	mov.f32 	%f1812, %f1794;
	mov.f32 	%f1813, %f1794;
	mov.f32 	%f1814, %f1794;
	mov.f32 	%f1815, %f1794;
	mov.f32 	%f1816, %f1794;
	mov.f32 	%f1817, %f1794;
	mov.f32 	%f1818, %f1794;
	mov.f32 	%f1819, %f1794;
	mov.f32 	%f1820, %f1794;
	mov.f32 	%f1821, %f1794;
	mov.f32 	%f1822, %f1794;
	mov.f32 	%f1823, %f1794;
	@%p41 bra 	$L__BB0_31;

	setp.eq.s32 	%p43, %r6, 0;
	selp.f32 	%f673, %f89, 0f3F800000, %p43;
	cvt.sat.f32.f32 	%f674, %f673;
	mul.f32 	%f675, %f1793, %f674;
	mul.f32 	%f1820, %f1790, %f675;
	mul.f32 	%f1819, %f1791, %f675;
	mul.f32 	%f1818, %f1792, %f675;
	mul.f32 	%f676, %f1790, %f1793;
	add.f32 	%f1817, %f676, 0f00000000;
	mul.f32 	%f677, %f1791, %f1793;
	add.f32 	%f1816, %f677, 0f00000000;
	mul.f32 	%f678, %f1792, %f1793;
	add.f32 	%f1815, %f678, 0f00000000;
	fma.rn.f32 	%f1814, %f73, %f676, 0f00000000;
	fma.rn.f32 	%f1813, %f73, %f677, 0f00000000;
	fma.rn.f32 	%f1812, %f73, %f678, 0f00000000;
	fma.rn.f32 	%f1811, %f74, %f676, 0f00000000;
	fma.rn.f32 	%f1810, %f74, %f677, 0f00000000;
	fma.rn.f32 	%f1809, %f74, %f678, 0f00000000;
	fma.rn.f32 	%f1808, %f72, %f676, 0f00000000;
	fma.rn.f32 	%f1807, %f72, %f677, 0f00000000;
	fma.rn.f32 	%f1806, %f72, %f678, 0f00000000;
	mul.f32 	%f679, %f72, %f73;
	fma.rn.f32 	%f1805, %f679, %f676, 0f00000000;
	fma.rn.f32 	%f1804, %f679, %f677, 0f00000000;
	fma.rn.f32 	%f1803, %f679, %f678, 0f00000000;
	mul.f32 	%f680, %f73, %f74;
	fma.rn.f32 	%f1802, %f680, %f676, 0f00000000;
	fma.rn.f32 	%f1801, %f680, %f677, 0f00000000;
	fma.rn.f32 	%f1800, %f680, %f678, 0f00000000;
	fma.rn.f32 	%f681, %f74, %f74, 0fBEAAAAAB;
	fma.rn.f32 	%f1799, %f681, %f676, 0f00000000;
	fma.rn.f32 	%f1798, %f681, %f677, 0f00000000;
	fma.rn.f32 	%f1797, %f681, %f678, 0f00000000;
	mul.f32 	%f682, %f72, %f74;
	fma.rn.f32 	%f1796, %f682, %f676, 0f00000000;
	fma.rn.f32 	%f1795, %f682, %f677, 0f00000000;
	fma.rn.f32 	%f1794, %f682, %f678, 0f00000000;
	mul.f32 	%f683, %f73, %f73;
	mul.f32 	%f684, %f72, %f72;
	sub.f32 	%f685, %f684, %f683;
	fma.rn.f32 	%f1821, %f685, %f676, 0f00000000;
	fma.rn.f32 	%f1822, %f685, %f677, 0f00000000;
	fma.rn.f32 	%f1823, %f685, %f678, 0f00000000;
	mov.pred 	%p192, 0;

$L__BB0_31:
	@%p192 bra 	$L__BB0_43;

	setp.eq.s32 	%p44, %r44, 0;
	mov.u16 	%rs329, 0;
	mov.f32 	%f1836, 0f3F800000;
	mov.f32 	%f1837, %f1836;
	mov.f32 	%f1839, %f1836;
	@%p44 bra 	$L__BB0_40;

	abs.s32 	%r10, %r44;
	setp.lt.s32 	%p45, %r10, 1;
	mov.f32 	%f1829, 0f00000000;
	mov.f32 	%f1828, %f1829;
	mov.f32 	%f1827, %f1829;
	@%p45 bra 	$L__BB0_39;

	mov.f32 	%f701, 0f38D1B717;
	max.f32 	%f702, %f700, %f701;
	and.b32  	%r63, %r447, 32;
	setp.eq.s32 	%p46, %r63, 0;
	mov.u32 	%r446, 0;
	selp.f32 	%f703, 0f3F800000, 0f41200000, %p46;
	mul.f32 	%f169, %f703, %f702;
	and.b32  	%r11, %r10, 1;
	setp.eq.s32 	%p47, %r10, 1;
	mov.f32 	%f1827, 0f00000000;
	mov.f32 	%f1828, %f1827;
	mov.f32 	%f1829, %f1827;
	@%p47 bra 	$L__BB0_37;

	sub.s32 	%r445, %r10, %r11;

$L__BB0_36:
	cvt.rn.f32.s32 	%f725, %r446;
	add.f32 	%f726, %f16, %f725;
	sub.f32 	%f727, %f17, %f725;
	mul.f32 	%f728, %f726, 0f3DD32618;
	cvt.rmi.f32.f32 	%f729, %f728;
	sub.f32 	%f730, %f728, %f729;
	mul.f32 	%f731, %f727, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f732, %f731;
	sub.f32 	%f733, %f731, %f732;
	mul.f32 	%f734, %f725, 0f3DC74539;
	cvt.rmi.f32.f32 	%f735, %f734;
	sub.f32 	%f736, %f734, %f735;
	add.f32 	%f737, %f733, 0f420551EC;
	add.f32 	%f738, %f730, 0f420551EC;
	add.f32 	%f739, %f736, 0f420551EC;
	mul.f32 	%f740, %f730, %f737;
	fma.rn.f32 	%f741, %f733, %f738, %f740;
	fma.rn.f32 	%f742, %f736, %f739, %f741;
	add.f32 	%f743, %f730, %f742;
	add.f32 	%f744, %f733, %f742;
	add.f32 	%f745, %f736, %f742;
	add.f32 	%f746, %f743, %f744;
	mul.f32 	%f747, %f745, %f746;
	cvt.rmi.f32.f32 	%f748, %f747;
	sub.f32 	%f749, %f747, %f748;
	add.f32 	%f750, %f743, %f743;
	mul.f32 	%f751, %f744, %f750;
	cvt.rmi.f32.f32 	%f752, %f751;
	sub.f32 	%f753, %f751, %f752;
	mul.f32 	%f754, %f743, %f746;
	cvt.rmi.f32.f32 	%f755, %f754;
	sub.f32 	%f756, %f754, %f755;
	fma.rn.f32 	%f757, %f749, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f758, %f753, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f759, %f756, 0f40000000, 0fBF800000;
	ld.global.f32 	%f760, [%rd5+16];
	ld.global.f32 	%f761, [%rd5+4];
	fma.rn.f32 	%f762, %f760, %f757, %f761;
	ld.global.f32 	%f763, [%rd5+8];
	fma.rn.f32 	%f764, %f760, %f758, %f763;
	ld.global.f32 	%f765, [%rd5+12];
	fma.rn.f32 	%f766, %f760, %f759, %f765;
	sub.f32 	%f767, %f762, %f10;
	sub.f32 	%f768, %f764, %f11;
	sub.f32 	%f769, %f766, %f12;
	mul.f32 	%f770, %f768, %f768;
	fma.rn.f32 	%f771, %f767, %f767, %f770;
	fma.rn.f32 	%f772, %f769, %f769, %f771;
	sqrt.rn.f32 	%f714, %f772;
	rcp.rn.f32 	%f773, %f714;
	mul.f32 	%f710, %f773, %f767;
	mul.f32 	%f711, %f773, %f768;
	mul.f32 	%f712, %f773, %f769;
	mov.f32 	%f724, 0f00000000;
	mov.u32 	%r172, 2;
	mov.u32 	%r173, 1;
	mov.u32 	%r174, 3;
	mov.u32 	%r177, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f710,%f711,%f712,%f169,%f714,%f724,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f774, %r65;
	mov.b32 	%f775, %r66;
	mov.b32 	%f776, %r67;
	add.f32 	%f777, %f1827, %f774;
	add.f32 	%f778, %f1828, %f775;
	add.f32 	%f779, %f1829, %f776;
	add.s32 	%r207, %r446, 1;
	cvt.rn.f32.s32 	%f780, %r207;
	add.f32 	%f781, %f16, %f780;
	sub.f32 	%f782, %f17, %f780;
	mul.f32 	%f783, %f781, 0f3DD32618;
	cvt.rmi.f32.f32 	%f784, %f783;
	sub.f32 	%f785, %f783, %f784;
	mul.f32 	%f786, %f782, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f787, %f786;
	sub.f32 	%f788, %f786, %f787;
	mul.f32 	%f789, %f780, 0f3DC74539;
	cvt.rmi.f32.f32 	%f790, %f789;
	sub.f32 	%f791, %f789, %f790;
	add.f32 	%f792, %f788, 0f420551EC;
	add.f32 	%f793, %f785, 0f420551EC;
	add.f32 	%f794, %f791, 0f420551EC;
	mul.f32 	%f795, %f785, %f792;
	fma.rn.f32 	%f796, %f788, %f793, %f795;
	fma.rn.f32 	%f797, %f791, %f794, %f796;
	add.f32 	%f798, %f785, %f797;
	add.f32 	%f799, %f788, %f797;
	add.f32 	%f800, %f791, %f797;
	add.f32 	%f801, %f798, %f799;
	mul.f32 	%f802, %f800, %f801;
	cvt.rmi.f32.f32 	%f803, %f802;
	sub.f32 	%f804, %f802, %f803;
	add.f32 	%f805, %f798, %f798;
	mul.f32 	%f806, %f799, %f805;
	cvt.rmi.f32.f32 	%f807, %f806;
	sub.f32 	%f808, %f806, %f807;
	mul.f32 	%f809, %f798, %f801;
	cvt.rmi.f32.f32 	%f810, %f809;
	sub.f32 	%f811, %f809, %f810;
	fma.rn.f32 	%f812, %f804, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f813, %f808, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f814, %f811, 0f40000000, 0fBF800000;
	ld.global.f32 	%f815, [%rd5+16];
	ld.global.f32 	%f816, [%rd5+4];
	fma.rn.f32 	%f817, %f815, %f812, %f816;
	ld.global.f32 	%f818, [%rd5+8];
	fma.rn.f32 	%f819, %f815, %f813, %f818;
	ld.global.f32 	%f820, [%rd5+12];
	fma.rn.f32 	%f821, %f815, %f814, %f820;
	sub.f32 	%f822, %f817, %f10;
	sub.f32 	%f823, %f819, %f11;
	sub.f32 	%f824, %f821, %f12;
	mul.f32 	%f825, %f823, %f823;
	fma.rn.f32 	%f826, %f822, %f822, %f825;
	fma.rn.f32 	%f827, %f824, %f824, %f826;
	sqrt.rn.f32 	%f723, %f827;
	rcp.rn.f32 	%f828, %f723;
	mul.f32 	%f719, %f828, %f822;
	mul.f32 	%f720, %f828, %f823;
	mul.f32 	%f721, %f828, %f824;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f719,%f720,%f721,%f169,%f723,%f724,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f829, %r136;
	mov.b32 	%f830, %r137;
	mov.b32 	%f831, %r138;
	add.f32 	%f1827, %f777, %f829;
	add.f32 	%f1828, %f778, %f830;
	add.f32 	%f1829, %f779, %f831;
	add.s32 	%r446, %r446, 2;
	add.s32 	%r445, %r445, -2;
	setp.ne.s32 	%p48, %r445, 0;
	@%p48 bra 	$L__BB0_36;

$L__BB0_37:
	setp.eq.s32 	%p49, %r11, 0;
	@%p49 bra 	$L__BB0_39;

	cvt.rn.f32.s32 	%f841, %r446;
	add.f32 	%f842, %f16, %f841;
	sub.f32 	%f843, %f17, %f841;
	mul.f32 	%f844, %f842, 0f3DD32618;
	cvt.rmi.f32.f32 	%f845, %f844;
	sub.f32 	%f846, %f844, %f845;
	mul.f32 	%f847, %f843, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f848, %f847;
	sub.f32 	%f849, %f847, %f848;
	mul.f32 	%f850, %f841, 0f3DC74539;
	cvt.rmi.f32.f32 	%f851, %f850;
	sub.f32 	%f852, %f850, %f851;
	add.f32 	%f853, %f849, 0f420551EC;
	add.f32 	%f854, %f846, 0f420551EC;
	add.f32 	%f855, %f852, 0f420551EC;
	mul.f32 	%f856, %f846, %f853;
	fma.rn.f32 	%f857, %f849, %f854, %f856;
	fma.rn.f32 	%f858, %f852, %f855, %f857;
	add.f32 	%f859, %f846, %f858;
	add.f32 	%f860, %f849, %f858;
	add.f32 	%f861, %f852, %f858;
	add.f32 	%f862, %f859, %f860;
	mul.f32 	%f863, %f861, %f862;
	cvt.rmi.f32.f32 	%f864, %f863;
	sub.f32 	%f865, %f863, %f864;
	add.f32 	%f866, %f859, %f859;
	mul.f32 	%f867, %f860, %f866;
	cvt.rmi.f32.f32 	%f868, %f867;
	sub.f32 	%f869, %f867, %f868;
	mul.f32 	%f870, %f859, %f862;
	cvt.rmi.f32.f32 	%f871, %f870;
	sub.f32 	%f872, %f870, %f871;
	fma.rn.f32 	%f873, %f865, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f874, %f869, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f875, %f872, 0f40000000, 0fBF800000;
	ld.global.f32 	%f876, [%rd5+16];
	ld.global.f32 	%f877, [%rd5+4];
	fma.rn.f32 	%f878, %f876, %f873, %f877;
	ld.global.f32 	%f879, [%rd5+8];
	fma.rn.f32 	%f880, %f876, %f874, %f879;
	ld.global.f32 	%f881, [%rd5+12];
	fma.rn.f32 	%f882, %f876, %f875, %f881;
	sub.f32 	%f883, %f878, %f10;
	sub.f32 	%f884, %f880, %f11;
	sub.f32 	%f885, %f882, %f12;
	mul.f32 	%f886, %f884, %f884;
	fma.rn.f32 	%f887, %f883, %f883, %f886;
	fma.rn.f32 	%f888, %f885, %f885, %f887;
	sqrt.rn.f32 	%f839, %f888;
	rcp.rn.f32 	%f889, %f839;
	mul.f32 	%f835, %f889, %f883;
	mul.f32 	%f836, %f889, %f884;
	mul.f32 	%f837, %f889, %f885;
	mov.f32 	%f840, 0f00000000;
	mov.u32 	%r244, 2;
	mov.u32 	%r245, 1;
	mov.u32 	%r246, 3;
	mov.u32 	%r249, 1065353216;
	mov.u32 	%r278, 0;
	// begin inline asm
	call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f835,%f836,%f837,%f169,%f839,%f840,%r245,%r278,%r245,%r244,%r245,%r246,%r249,%r249,%r249,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
	// end inline asm
	mov.b32 	%f890, %r208;
	mov.b32 	%f891, %r209;
	mov.b32 	%f892, %r210;
	add.f32 	%f1827, %f1827, %f890;
	add.f32 	%f1828, %f1828, %f891;
	add.f32 	%f1829, %f1829, %f892;

$L__BB0_39:
	cvt.rn.f32.s32 	%f893, %r10;
	rcp.rn.f32 	%f894, %f893;
	mul.f32 	%f1839, %f894, %f1827;
	mul.f32 	%f1837, %f894, %f1828;
	mul.f32 	%f1836, %f894, %f1829;
	shr.u32 	%r279, %r44, 31;
	cvt.u16.u32 	%rs329, %r279;

$L__BB0_40:
	fma.rn.f32 	%f1840, %f1820, %f1839, %f1840;
	fma.rn.f32 	%f1841, %f1819, %f1837, %f1841;
	fma.rn.f32 	%f1842, %f1818, %f1836, %f1842;
	fma.rn.f32 	%f1843, %f1817, %f1839, %f1843;
	fma.rn.f32 	%f1844, %f1816, %f1837, %f1844;
	fma.rn.f32 	%f1845, %f1815, %f1836, %f1845;
	fma.rn.f32 	%f1846, %f1814, %f1839, %f1846;
	fma.rn.f32 	%f1847, %f1813, %f1837, %f1847;
	fma.rn.f32 	%f1848, %f1812, %f1836, %f1848;
	fma.rn.f32 	%f1849, %f1811, %f1839, %f1849;
	fma.rn.f32 	%f1850, %f1810, %f1837, %f1850;
	fma.rn.f32 	%f1851, %f1809, %f1836, %f1851;
	fma.rn.f32 	%f1852, %f1808, %f1839, %f1852;
	fma.rn.f32 	%f1853, %f1807, %f1837, %f1853;
	fma.rn.f32 	%f1854, %f1806, %f1836, %f1854;
	fma.rn.f32 	%f1855, %f1805, %f1839, %f1855;
	fma.rn.f32 	%f1856, %f1804, %f1837, %f1856;
	fma.rn.f32 	%f1857, %f1803, %f1836, %f1857;
	fma.rn.f32 	%f1858, %f1802, %f1839, %f1858;
	fma.rn.f32 	%f1859, %f1801, %f1837, %f1859;
	fma.rn.f32 	%f1860, %f1800, %f1836, %f1860;
	fma.rn.f32 	%f1861, %f1799, %f1839, %f1861;
	fma.rn.f32 	%f1862, %f1798, %f1837, %f1862;
	fma.rn.f32 	%f1863, %f1797, %f1836, %f1863;
	fma.rn.f32 	%f1864, %f1796, %f1839, %f1864;
	fma.rn.f32 	%f1865, %f1795, %f1837, %f1865;
	fma.rn.f32 	%f1866, %f1794, %f1836, %f1866;
	fma.rn.f32 	%f1867, %f1821, %f1839, %f1867;
	fma.rn.f32 	%f1868, %f1822, %f1837, %f1868;
	fma.rn.f32 	%f1869, %f1823, %f1836, %f1869;
	setp.eq.s16 	%p50, %rs329, 0;
	@%p50 bra 	$L__BB0_42;

	div.rn.f32 	%f895, %f1820, %f485;
	div.rn.f32 	%f896, %f895, %f88;
	cvt.sat.f32.f32 	%f897, %f896;
	mul.f32 	%f1839, %f1839, %f897;

$L__BB0_42:
	add.f32 	%f1870, %f1870, %f1839;

$L__BB0_43:
	cvt.u64.u32 	%rd117, %r443;
	cvt.u32.u64 	%r280, %rd117;
	add.s32 	%r443, %r280, 1;
	setp.lt.u32 	%p51, %r443, %r5;
	@%p51 bra 	$L__BB0_7;
	bra.uni 	$L__BB0_45;

$L__BB0_44:
	mov.f32 	%f1840, 0f00000000;
	ld.const.u32 	%r447, [params+104];
	mov.f32 	%f1841, %f1840;
	mov.f32 	%f1842, %f1840;
	mov.f32 	%f1843, %f1840;
	mov.f32 	%f1844, %f1840;
	mov.f32 	%f1845, %f1840;
	mov.f32 	%f1846, %f1840;
	mov.f32 	%f1847, %f1840;
	mov.f32 	%f1848, %f1840;
	mov.f32 	%f1849, %f1840;
	mov.f32 	%f1850, %f1840;
	mov.f32 	%f1851, %f1840;
	mov.f32 	%f1852, %f1840;
	mov.f32 	%f1853, %f1840;
	mov.f32 	%f1854, %f1840;
	mov.f32 	%f1855, %f1840;
	mov.f32 	%f1856, %f1840;
	mov.f32 	%f1857, %f1840;
	mov.f32 	%f1858, %f1840;
	mov.f32 	%f1859, %f1840;
	mov.f32 	%f1860, %f1840;
	mov.f32 	%f1861, %f1840;
	mov.f32 	%f1862, %f1840;
	mov.f32 	%f1863, %f1840;
	mov.f32 	%f1864, %f1840;
	mov.f32 	%f1865, %f1840;
	mov.f32 	%f1866, %f1840;
	mov.f32 	%f1867, %f1840;
	mov.f32 	%f1868, %f1840;
	mov.f32 	%f1869, %f1840;
	mov.f32 	%f1870, %f1840;

$L__BB0_45:
	and.b32  	%r281, %r447, 8;
	setp.eq.s32 	%p52, %r281, 0;
	@%p52 bra 	$L__BB0_59;

	cvt.sat.f32.f32 	%f289, %f1870;
	ld.const.u64 	%rd43, [params+192];
	cvta.to.global.u64 	%rd7, %rd43;
	ld.const.u32 	%r282, [params+184];
	mad.lo.s32 	%r283, %r282, %r4, %r3;
	cvt.u64.u32 	%rd8, %r283;
	mov.f32 	%f930, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f931, %f930;
	add.f32 	%f932, %f931, %f931;
	mov.f32 	%f933, 0f3EE8BA2E;
	sub.f32 	%f934, %f933, %f932;
	abs.f32 	%f290, %f934;
	abs.f32 	%f291, %f289;
	setp.lt.f32 	%p53, %f291, 0f00800000;
	mul.f32 	%f935, %f291, 0f4B800000;
	selp.f32 	%f936, %f935, %f291, %p53;
	selp.f32 	%f937, 0fC3170000, 0fC2FE0000, %p53;
	mov.b32 	%r284, %f936;
	and.b32  	%r285, %r284, 8388607;
	or.b32  	%r286, %r285, 1065353216;
	mov.b32 	%f938, %r286;
	shr.u32 	%r287, %r284, 23;
	cvt.rn.f32.u32 	%f939, %r287;
	add.f32 	%f940, %f937, %f939;
	setp.gt.f32 	%p54, %f938, 0f3FB504F3;
	mul.f32 	%f941, %f938, 0f3F000000;
	add.f32 	%f942, %f940, 0f3F800000;
	selp.f32 	%f943, %f942, %f940, %p54;
	selp.f32 	%f944, %f941, %f938, %p54;
	add.f32 	%f945, %f944, 0fBF800000;
	add.f32 	%f946, %f944, 0f3F800000;
	rcp.approx.ftz.f32 	%f947, %f946;
	add.f32 	%f948, %f945, %f945;
	mul.f32 	%f949, %f948, %f947;
	mul.f32 	%f950, %f949, %f949;
	mov.f32 	%f951, 0f3C4CAF63;
	mov.f32 	%f952, 0f3B18F0FE;
	fma.rn.f32 	%f953, %f952, %f950, %f951;
	mov.f32 	%f954, 0f3DAAAABD;
	fma.rn.f32 	%f955, %f953, %f950, %f954;
	mul.rn.f32 	%f956, %f955, %f950;
	mul.rn.f32 	%f957, %f956, %f949;
	sub.f32 	%f958, %f945, %f949;
	add.f32 	%f959, %f958, %f958;
	neg.f32 	%f960, %f949;
	fma.rn.f32 	%f961, %f960, %f945, %f959;
	mul.rn.f32 	%f962, %f947, %f961;
	add.f32 	%f963, %f957, %f949;
	sub.f32 	%f964, %f949, %f963;
	add.f32 	%f965, %f957, %f964;
	add.f32 	%f966, %f962, %f965;
	add.f32 	%f967, %f963, %f966;
	sub.f32 	%f968, %f963, %f967;
	add.f32 	%f969, %f966, %f968;
	mov.f32 	%f970, 0f3F317200;
	mul.rn.f32 	%f971, %f943, %f970;
	mov.f32 	%f972, 0f35BFBE8E;
	mul.rn.f32 	%f973, %f943, %f972;
	add.f32 	%f974, %f971, %f967;
	sub.f32 	%f975, %f971, %f974;
	add.f32 	%f976, %f967, %f975;
	add.f32 	%f977, %f969, %f976;
	add.f32 	%f978, %f973, %f977;
	add.f32 	%f979, %f974, %f978;
	sub.f32 	%f980, %f974, %f979;
	add.f32 	%f981, %f978, %f980;
	mul.rn.f32 	%f982, %f933, %f979;
	neg.f32 	%f983, %f982;
	fma.rn.f32 	%f984, %f933, %f979, %f983;
	fma.rn.f32 	%f985, %f933, %f981, %f984;
	mov.f32 	%f986, 0f00000000;
	fma.rn.f32 	%f987, %f986, %f979, %f985;
	add.rn.f32 	%f988, %f982, %f987;
	neg.f32 	%f989, %f988;
	add.rn.f32 	%f990, %f982, %f989;
	add.rn.f32 	%f991, %f990, %f987;
	mov.b32 	%r288, %f988;
	setp.eq.s32 	%p55, %r288, 1118925336;
	add.s32 	%r289, %r288, -1;
	mov.b32 	%f992, %r289;
	add.f32 	%f993, %f991, 0f37000000;
	selp.f32 	%f292, %f993, %f991, %p55;
	selp.f32 	%f994, %f992, %f988, %p55;
	mov.f32 	%f995, 0f3FB8AA3B;
	mul.rn.f32 	%f996, %f994, %f995;
	cvt.rzi.f32.f32 	%f997, %f996;
	abs.f32 	%f998, %f997;
	setp.gt.f32 	%p56, %f998, 0f42FC0000;
	mov.b32 	%r290, %f997;
	and.b32  	%r291, %r290, -2147483648;
	or.b32  	%r292, %r291, 1123811328;
	mov.b32 	%f999, %r292;
	selp.f32 	%f1000, %f999, %f997, %p56;
	mov.f32 	%f1001, 0fBF317218;
	fma.rn.f32 	%f1002, %f1000, %f1001, %f994;
	mov.f32 	%f1003, 0f3102E308;
	fma.rn.f32 	%f1004, %f1000, %f1003, %f1002;
	mul.f32 	%f1005, %f1004, 0f3FB8AA3B;
	add.f32 	%f1006, %f1000, 0f4B40007F;
	mov.b32 	%r293, %f1006;
	shl.b32 	%r294, %r293, 23;
	mov.b32 	%f1007, %r294;
	ex2.approx.ftz.f32 	%f1008, %f1005;
	mul.f32 	%f293, %f1008, %f1007;
	setp.eq.f32 	%p57, %f293, 0f7F800000;
	mov.f32 	%f1902, 0f7F800000;
	@%p57 bra 	$L__BB0_48;

	fma.rn.f32 	%f1902, %f293, %f292, %f293;

$L__BB0_48:
	setp.lt.f32 	%p58, %f289, 0f00000000;
	setp.eq.f32 	%p59, %f290, 0f3F800000;
	and.pred  	%p3, %p58, %p59;
	setp.eq.f32 	%p60, %f289, 0f00000000;
	@%p60 bra 	$L__BB0_52;
	bra.uni 	$L__BB0_49;

$L__BB0_52:
	add.f32 	%f1013, %f289, %f289;
	selp.f32 	%f1904, %f1013, 0f00000000, %p59;
	bra.uni 	$L__BB0_53;

$L__BB0_171:
	mov.f32 	%f1664, 0f00000000;
	mov.u32 	%r449, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs190, %f1664;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs189, %f1664;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs188, %f1664;}

	// end inline asm
	mov.u16 	%rs191, 0;
	st.global.v4.u16 	[%rd21], {%rs188, %rs189, %rs190, %rs191};

$L__BB0_172:
	ld.const.u64 	%rd90, [params+256];
	cvta.to.global.u64 	%rd91, %rd90;
	ld.const.u32 	%r425, [params+248];
	mad.lo.s32 	%r426, %r425, %r4, %r3;
	mul.wide.u32 	%rd92, %r426, 8;
	add.s64 	%rd22, %rd91, %rd92;
	setp.eq.s32 	%p183, %r449, 0;
	@%p183 bra 	$L__BB0_174;

	ld.global.v4.u16 	{%rs198, %rs199, %rs200, %rs201}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1665, %rs198;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1666, %rs199;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1667, %rs200;}

	// end inline asm
	add.f32 	%f1668, %f1665, 0f00000000;
	add.f32 	%f1669, %f1666, 0f00000000;
	add.f32 	%f1670, %f1667, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs197, %f1670;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs196, %f1669;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs195, %f1668;}

	// end inline asm
	mov.u16 	%rs202, 0;
	st.global.v4.u16 	[%rd22], {%rs195, %rs196, %rs197, %rs202};
	bra.uni 	$L__BB0_175;

$L__BB0_174:
	mov.f32 	%f1673, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs205, %f1673;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs204, %f1673;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs203, %f1673;}

	// end inline asm
	mov.u16 	%rs206, 0;
	st.global.v4.u16 	[%rd22], {%rs203, %rs204, %rs205, %rs206};

$L__BB0_175:
	ld.const.u64 	%rd93, [params+272];
	cvta.to.global.u64 	%rd94, %rd93;
	ld.const.u32 	%r427, [params+264];
	mad.lo.s32 	%r428, %r427, %r4, %r3;
	mul.wide.u32 	%rd95, %r428, 8;
	add.s64 	%rd23, %rd94, %rd95;
	@%p183 bra 	$L__BB0_177;

	ld.global.v4.u16 	{%rs213, %rs214, %rs215, %rs216}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1674, %rs213;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1675, %rs214;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1676, %rs215;}

	// end inline asm
	add.f32 	%f1677, %f1674, 0f00000000;
	add.f32 	%f1678, %f1675, 0f00000000;
	add.f32 	%f1679, %f1676, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs212, %f1679;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs211, %f1678;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs210, %f1677;}

	// end inline asm
	mov.u16 	%rs217, 0;
	st.global.v4.u16 	[%rd23], {%rs210, %rs211, %rs212, %rs217};
	bra.uni 	$L__BB0_178;

$L__BB0_177:
	mov.f32 	%f1682, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs220, %f1682;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs219, %f1682;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs218, %f1682;}

	// end inline asm
	mov.u16 	%rs221, 0;
	st.global.v4.u16 	[%rd23], {%rs218, %rs219, %rs220, %rs221};

$L__BB0_178:
	ld.const.u64 	%rd96, [params+288];
	cvta.to.global.u64 	%rd97, %rd96;
	ld.const.u32 	%r429, [params+280];
	mad.lo.s32 	%r430, %r429, %r4, %r3;
	mul.wide.u32 	%rd98, %r430, 8;
	add.s64 	%rd24, %rd97, %rd98;
	@%p183 bra 	$L__BB0_180;

	ld.global.v4.u16 	{%rs228, %rs229, %rs230, %rs231}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1683, %rs228;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1684, %rs229;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1685, %rs230;}

	// end inline asm
	add.f32 	%f1686, %f1683, 0f00000000;
	add.f32 	%f1687, %f1684, 0f00000000;
	add.f32 	%f1688, %f1685, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs227, %f1688;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs226, %f1687;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs225, %f1686;}

	// end inline asm
	mov.u16 	%rs232, 0;
	st.global.v4.u16 	[%rd24], {%rs225, %rs226, %rs227, %rs232};
	bra.uni 	$L__BB0_181;

$L__BB0_180:
	mov.f32 	%f1691, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs235, %f1691;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs234, %f1691;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs233, %f1691;}

	// end inline asm
	mov.u16 	%rs236, 0;
	st.global.v4.u16 	[%rd24], {%rs233, %rs234, %rs235, %rs236};

$L__BB0_181:
	ld.const.u64 	%rd99, [params+304];
	cvta.to.global.u64 	%rd100, %rd99;
	ld.const.u32 	%r431, [params+296];
	mad.lo.s32 	%r432, %r431, %r4, %r3;
	mul.wide.u32 	%rd101, %r432, 8;
	add.s64 	%rd25, %rd100, %rd101;
	@%p183 bra 	$L__BB0_183;

	ld.global.v4.u16 	{%rs243, %rs244, %rs245, %rs246}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1692, %rs243;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1693, %rs244;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1694, %rs245;}

	// end inline asm
	add.f32 	%f1695, %f1692, 0f00000000;
	add.f32 	%f1696, %f1693, 0f00000000;
	add.f32 	%f1697, %f1694, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs242, %f1697;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs241, %f1696;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs240, %f1695;}

	// end inline asm
	mov.u16 	%rs247, 0;
	st.global.v4.u16 	[%rd25], {%rs240, %rs241, %rs242, %rs247};
	bra.uni 	$L__BB0_184;

$L__BB0_183:
	mov.f32 	%f1700, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs250, %f1700;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs249, %f1700;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs248, %f1700;}

	// end inline asm
	mov.u16 	%rs251, 0;
	st.global.v4.u16 	[%rd25], {%rs248, %rs249, %rs250, %rs251};

$L__BB0_184:
	ld.const.u64 	%rd102, [params+320];
	cvta.to.global.u64 	%rd103, %rd102;
	ld.const.u32 	%r433, [params+312];
	mad.lo.s32 	%r434, %r433, %r4, %r3;
	mul.wide.u32 	%rd104, %r434, 8;
	add.s64 	%rd26, %rd103, %rd104;
	@%p183 bra 	$L__BB0_186;

	ld.global.v4.u16 	{%rs258, %rs259, %rs260, %rs261}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1701, %rs258;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1702, %rs259;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1703, %rs260;}

	// end inline asm
	add.f32 	%f1704, %f1701, 0f00000000;
	add.f32 	%f1705, %f1702, 0f00000000;
	add.f32 	%f1706, %f1703, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs257, %f1706;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs256, %f1705;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs255, %f1704;}

	// end inline asm
	mov.u16 	%rs262, 0;
	st.global.v4.u16 	[%rd26], {%rs255, %rs256, %rs257, %rs262};
	bra.uni 	$L__BB0_187;

$L__BB0_186:
	mov.f32 	%f1709, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs265, %f1709;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs264, %f1709;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs263, %f1709;}

	// end inline asm
	mov.u16 	%rs266, 0;
	st.global.v4.u16 	[%rd26], {%rs263, %rs264, %rs265, %rs266};

$L__BB0_187:
	ld.const.u64 	%rd105, [params+336];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r435, [params+328];
	mad.lo.s32 	%r436, %r435, %r4, %r3;
	mul.wide.u32 	%rd107, %r436, 8;
	add.s64 	%rd27, %rd106, %rd107;
	@%p183 bra 	$L__BB0_189;

	ld.global.v4.u16 	{%rs273, %rs274, %rs275, %rs276}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1710, %rs273;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1711, %rs274;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1712, %rs275;}

	// end inline asm
	add.f32 	%f1713, %f1710, 0f00000000;
	add.f32 	%f1714, %f1711, 0f00000000;
	add.f32 	%f1715, %f1712, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs272, %f1715;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs271, %f1714;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs270, %f1713;}

	// end inline asm
	mov.u16 	%rs277, 0;
	st.global.v4.u16 	[%rd27], {%rs270, %rs271, %rs272, %rs277};
	bra.uni 	$L__BB0_190;

$L__BB0_189:
	mov.f32 	%f1718, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs280, %f1718;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs279, %f1718;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs278, %f1718;}

	// end inline asm
	mov.u16 	%rs281, 0;
	st.global.v4.u16 	[%rd27], {%rs278, %rs279, %rs280, %rs281};

$L__BB0_190:
	ld.const.u64 	%rd108, [params+352];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r437, [params+344];
	mad.lo.s32 	%r438, %r437, %r4, %r3;
	mul.wide.u32 	%rd110, %r438, 8;
	add.s64 	%rd28, %rd109, %rd110;
	@%p183 bra 	$L__BB0_192;

	ld.global.v4.u16 	{%rs288, %rs289, %rs290, %rs291}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1719, %rs288;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1720, %rs289;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1721, %rs290;}

	// end inline asm
	add.f32 	%f1722, %f1719, 0f00000000;
	add.f32 	%f1723, %f1720, 0f00000000;
	add.f32 	%f1724, %f1721, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs287, %f1724;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs286, %f1723;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs285, %f1722;}

	// end inline asm
	mov.u16 	%rs292, 0;
	st.global.v4.u16 	[%rd28], {%rs285, %rs286, %rs287, %rs292};
	bra.uni 	$L__BB0_193;

$L__BB0_192:
	mov.f32 	%f1727, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs295, %f1727;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs294, %f1727;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs293, %f1727;}

	// end inline asm
	mov.u16 	%rs296, 0;
	st.global.v4.u16 	[%rd28], {%rs293, %rs294, %rs295, %rs296};

$L__BB0_193:
	ld.const.u64 	%rd111, [params+368];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r439, [params+360];
	mad.lo.s32 	%r440, %r439, %r4, %r3;
	mul.wide.u32 	%rd113, %r440, 8;
	add.s64 	%rd29, %rd112, %rd113;
	@%p183 bra 	$L__BB0_195;

	ld.global.v4.u16 	{%rs303, %rs304, %rs305, %rs306}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1728, %rs303;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1729, %rs304;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1730, %rs305;}

	// end inline asm
	add.f32 	%f1731, %f1728, 0f00000000;
	add.f32 	%f1732, %f1729, 0f00000000;
	add.f32 	%f1733, %f1730, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs302, %f1733;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs301, %f1732;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs300, %f1731;}

	// end inline asm
	mov.u16 	%rs307, 0;
	st.global.v4.u16 	[%rd29], {%rs300, %rs301, %rs302, %rs307};
	bra.uni 	$L__BB0_196;

$L__BB0_195:
	mov.f32 	%f1736, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs310, %f1736;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs309, %f1736;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs308, %f1736;}

	// end inline asm
	mov.u16 	%rs311, 0;
	st.global.v4.u16 	[%rd29], {%rs308, %rs309, %rs310, %rs311};

$L__BB0_196:
	ld.const.u64 	%rd114, [params+384];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r441, [params+376];
	mad.lo.s32 	%r442, %r441, %r4, %r3;
	mul.wide.u32 	%rd116, %r442, 8;
	add.s64 	%rd30, %rd115, %rd116;
	@%p183 bra 	$L__BB0_198;

	ld.global.v4.u16 	{%rs318, %rs319, %rs320, %rs321}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1737, %rs318;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1738, %rs319;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1739, %rs320;}

	// end inline asm
	add.f32 	%f1740, %f1737, 0f00000000;
	add.f32 	%f1741, %f1738, 0f00000000;
	add.f32 	%f1742, %f1739, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs317, %f1742;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs316, %f1741;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs315, %f1740;}

	// end inline asm
	mov.u16 	%rs322, 0;
	st.global.v4.u16 	[%rd30], {%rs315, %rs316, %rs317, %rs322};
	bra.uni 	$L__BB0_199;

$L__BB0_198:
	mov.f32 	%f1745, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs325, %f1745;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs324, %f1745;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs323, %f1745;}

	// end inline asm
	mov.u16 	%rs326, 0;
	st.global.v4.u16 	[%rd30], {%rs323, %rs324, %rs325, %rs326};
	bra.uni 	$L__BB0_199;

$L__BB0_49:
	mov.b32 	%r295, %f1902;
	xor.b32  	%r296, %r295, -2147483648;
	mov.b32 	%f1009, %r296;
	selp.f32 	%f1904, %f1009, %f1902, %p3;
	setp.geu.f32 	%p61, %f289, 0f00000000;
	@%p61 bra 	$L__BB0_53;

	mov.f32 	%f1010, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f1011, %f1010;
	setp.eq.f32 	%p62, %f1011, 0f3EE8BA2E;
	@%p62 bra 	$L__BB0_53;

	mov.f32 	%f1904, 0f7FFFFFFF;

$L__BB0_53:
	add.f32 	%f1014, %f291, 0f3EE8BA2E;
	mov.b32 	%r297, %f1014;
	setp.lt.s32 	%p64, %r297, 2139095040;
	@%p64 bra 	$L__BB0_58;

	setp.gtu.f32 	%p65, %f291, 0f7F800000;
	@%p65 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_55;

$L__BB0_57:
	add.f32 	%f1904, %f289, 0f3EE8BA2E;
	bra.uni 	$L__BB0_58;

$L__BB0_55:
	setp.neu.f32 	%p66, %f291, 0f7F800000;
	@%p66 bra 	$L__BB0_58;

	selp.f32 	%f1904, 0fFF800000, 0f7F800000, %p3;

$L__BB0_58:
	mul.f32 	%f1015, %f1904, 0f437F0000;
	setp.eq.f32 	%p67, %f289, 0f3F800000;
	selp.f32 	%f1016, 0f437F0000, %f1015, %p67;
	cvt.rzi.u32.f32 	%r298, %f1016;
	shl.b64 	%rd44, %rd8, 1;
	add.s64 	%rd45, %rd7, %rd44;
	cvt.u16.u32 	%rs18, %r298;
	mov.u16 	%rs19, 255;
	st.global.v2.u8 	[%rd45], {%rs18, %rs19};

$L__BB0_59:
	and.b32  	%r299, %r447, 1;
	setp.eq.b32 	%p68, %r299, 1;
	mov.pred 	%p69, 0;
	xor.pred  	%p70, %p68, %p69;
	not.pred 	%p71, %p70;
	@%p71 bra 	$L__BB0_133;

	mov.f32 	%f1018, 0f3E666666;
	cvt.rzi.f32.f32 	%f1019, %f1018;
	add.f32 	%f1020, %f1019, %f1019;
	mov.f32 	%f1021, 0f3EE66666;
	sub.f32 	%f1022, %f1021, %f1020;
	abs.f32 	%f302, %f1022;
	abs.f32 	%f303, %f1840;
	setp.lt.f32 	%p72, %f303, 0f00800000;
	mul.f32 	%f1023, %f303, 0f4B800000;
	selp.f32 	%f1024, %f1023, %f303, %p72;
	selp.f32 	%f1025, 0fC3170000, 0fC2FE0000, %p72;
	mov.b32 	%r300, %f1024;
	and.b32  	%r301, %r300, 8388607;
	or.b32  	%r302, %r301, 1065353216;
	mov.b32 	%f1026, %r302;
	shr.u32 	%r303, %r300, 23;
	cvt.rn.f32.u32 	%f1027, %r303;
	add.f32 	%f1028, %f1025, %f1027;
	setp.gt.f32 	%p73, %f1026, 0f3FB504F3;
	mul.f32 	%f1029, %f1026, 0f3F000000;
	add.f32 	%f1030, %f1028, 0f3F800000;
	selp.f32 	%f1031, %f1030, %f1028, %p73;
	selp.f32 	%f1032, %f1029, %f1026, %p73;
	add.f32 	%f1033, %f1032, 0fBF800000;
	add.f32 	%f1034, %f1032, 0f3F800000;
	rcp.approx.ftz.f32 	%f1035, %f1034;
	add.f32 	%f1036, %f1033, %f1033;
	mul.f32 	%f1037, %f1036, %f1035;
	mul.f32 	%f1038, %f1037, %f1037;
	mov.f32 	%f1039, 0f3C4CAF63;
	mov.f32 	%f1040, 0f3B18F0FE;
	fma.rn.f32 	%f1041, %f1040, %f1038, %f1039;
	mov.f32 	%f1042, 0f3DAAAABD;
	fma.rn.f32 	%f1043, %f1041, %f1038, %f1042;
	mul.rn.f32 	%f1044, %f1043, %f1038;
	mul.rn.f32 	%f1045, %f1044, %f1037;
	sub.f32 	%f1046, %f1033, %f1037;
	add.f32 	%f1047, %f1046, %f1046;
	neg.f32 	%f1048, %f1037;
	fma.rn.f32 	%f1049, %f1048, %f1033, %f1047;
	mul.rn.f32 	%f1050, %f1035, %f1049;
	add.f32 	%f1051, %f1045, %f1037;
	sub.f32 	%f1052, %f1037, %f1051;
	add.f32 	%f1053, %f1045, %f1052;
	add.f32 	%f1054, %f1050, %f1053;
	add.f32 	%f1055, %f1051, %f1054;
	sub.f32 	%f1056, %f1051, %f1055;
	add.f32 	%f1057, %f1054, %f1056;
	mov.f32 	%f1058, 0f3F317200;
	mul.rn.f32 	%f1059, %f1031, %f1058;
	mov.f32 	%f1060, 0f35BFBE8E;
	mul.rn.f32 	%f1061, %f1031, %f1060;
	add.f32 	%f1062, %f1059, %f1055;
	sub.f32 	%f1063, %f1059, %f1062;
	add.f32 	%f1064, %f1055, %f1063;
	add.f32 	%f1065, %f1057, %f1064;
	add.f32 	%f1066, %f1061, %f1065;
	add.f32 	%f1067, %f1062, %f1066;
	sub.f32 	%f1068, %f1062, %f1067;
	add.f32 	%f1069, %f1066, %f1068;
	mul.rn.f32 	%f1070, %f1021, %f1067;
	neg.f32 	%f1071, %f1070;
	fma.rn.f32 	%f1072, %f1021, %f1067, %f1071;
	fma.rn.f32 	%f1073, %f1021, %f1069, %f1072;
	mov.f32 	%f1074, 0f00000000;
	fma.rn.f32 	%f1075, %f1074, %f1067, %f1073;
	add.rn.f32 	%f1076, %f1070, %f1075;
	neg.f32 	%f1077, %f1076;
	add.rn.f32 	%f1078, %f1070, %f1077;
	add.rn.f32 	%f1079, %f1078, %f1075;
	mov.b32 	%r304, %f1076;
	setp.eq.s32 	%p74, %r304, 1118925336;
	add.s32 	%r305, %r304, -1;
	mov.b32 	%f1080, %r305;
	add.f32 	%f1081, %f1079, 0f37000000;
	selp.f32 	%f304, %f1081, %f1079, %p74;
	selp.f32 	%f1082, %f1080, %f1076, %p74;
	mov.f32 	%f1083, 0f3FB8AA3B;
	mul.rn.f32 	%f1084, %f1082, %f1083;
	cvt.rzi.f32.f32 	%f1085, %f1084;
	abs.f32 	%f1086, %f1085;
	setp.gt.f32 	%p75, %f1086, 0f42FC0000;
	mov.b32 	%r306, %f1085;
	and.b32  	%r307, %r306, -2147483648;
	or.b32  	%r308, %r307, 1123811328;
	mov.b32 	%f1087, %r308;
	selp.f32 	%f1088, %f1087, %f1085, %p75;
	mov.f32 	%f1089, 0fBF317218;
	fma.rn.f32 	%f1090, %f1088, %f1089, %f1082;
	mov.f32 	%f1091, 0f3102E308;
	fma.rn.f32 	%f1092, %f1088, %f1091, %f1090;
	mul.f32 	%f1093, %f1092, 0f3FB8AA3B;
	add.f32 	%f1094, %f1088, 0f4B40007F;
	mov.b32 	%r309, %f1094;
	shl.b32 	%r310, %r309, 23;
	mov.b32 	%f1095, %r310;
	ex2.approx.ftz.f32 	%f1096, %f1093;
	mul.f32 	%f305, %f1096, %f1095;
	setp.eq.f32 	%p76, %f305, 0f7F800000;
	mov.f32 	%f1905, 0f7F800000;
	@%p76 bra 	$L__BB0_62;

	fma.rn.f32 	%f1905, %f305, %f304, %f305;

$L__BB0_62:
	setp.lt.f32 	%p77, %f1840, 0f00000000;
	setp.eq.f32 	%p78, %f302, 0f3F800000;
	and.pred  	%p4, %p77, %p78;
	setp.eq.f32 	%p79, %f1840, 0f00000000;
	@%p79 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_63;

$L__BB0_66:
	add.f32 	%f1101, %f1840, %f1840;
	selp.f32 	%f1907, %f1101, 0f00000000, %p78;
	bra.uni 	$L__BB0_67;

$L__BB0_63:
	mov.b32 	%r311, %f1905;
	xor.b32  	%r312, %r311, -2147483648;
	mov.b32 	%f1097, %r312;
	selp.f32 	%f1907, %f1097, %f1905, %p4;
	setp.geu.f32 	%p80, %f1840, 0f00000000;
	@%p80 bra 	$L__BB0_67;

	mov.f32 	%f1098, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1099, %f1098;
	setp.eq.f32 	%p81, %f1099, 0f3EE66666;
	@%p81 bra 	$L__BB0_67;

	mov.f32 	%f1907, 0f7FFFFFFF;

$L__BB0_67:
	add.f32 	%f1102, %f303, 0f3EE66666;
	mov.b32 	%r313, %f1102;
	setp.lt.s32 	%p83, %r313, 2139095040;
	@%p83 bra 	$L__BB0_72;

	setp.gtu.f32 	%p84, %f303, 0f7F800000;
	@%p84 bra 	$L__BB0_71;
	bra.uni 	$L__BB0_69;

$L__BB0_71:
	add.f32 	%f1907, %f1840, 0f3EE66666;
	bra.uni 	$L__BB0_72;

$L__BB0_69:
	setp.neu.f32 	%p85, %f303, 0f7F800000;
	@%p85 bra 	$L__BB0_72;

	selp.f32 	%f1907, 0fFF800000, 0f7F800000, %p4;

$L__BB0_72:
	setp.eq.f32 	%p86, %f1840, 0f3F800000;
	selp.f32 	%f314, 0f3F800000, %f1907, %p86;
	abs.f32 	%f315, %f1841;
	setp.lt.f32 	%p87, %f315, 0f00800000;
	mul.f32 	%f1104, %f315, 0f4B800000;
	selp.f32 	%f1105, %f1104, %f315, %p87;
	selp.f32 	%f1106, 0fC3170000, 0fC2FE0000, %p87;
	mov.b32 	%r314, %f1105;
	and.b32  	%r315, %r314, 8388607;
	or.b32  	%r316, %r315, 1065353216;
	mov.b32 	%f1107, %r316;
	shr.u32 	%r317, %r314, 23;
	cvt.rn.f32.u32 	%f1108, %r317;
	add.f32 	%f1109, %f1106, %f1108;
	setp.gt.f32 	%p88, %f1107, 0f3FB504F3;
	mul.f32 	%f1110, %f1107, 0f3F000000;
	add.f32 	%f1111, %f1109, 0f3F800000;
	selp.f32 	%f1112, %f1111, %f1109, %p88;
	selp.f32 	%f1113, %f1110, %f1107, %p88;
	add.f32 	%f1114, %f1113, 0fBF800000;
	add.f32 	%f1115, %f1113, 0f3F800000;
	rcp.approx.ftz.f32 	%f1116, %f1115;
	add.f32 	%f1117, %f1114, %f1114;
	mul.f32 	%f1118, %f1117, %f1116;
	mul.f32 	%f1119, %f1118, %f1118;
	mov.f32 	%f1120, 0f3C4CAF63;
	mov.f32 	%f1121, 0f3B18F0FE;
	fma.rn.f32 	%f1122, %f1121, %f1119, %f1120;
	mov.f32 	%f1123, 0f3DAAAABD;
	fma.rn.f32 	%f1124, %f1122, %f1119, %f1123;
	mul.rn.f32 	%f1125, %f1124, %f1119;
	mul.rn.f32 	%f1126, %f1125, %f1118;
	sub.f32 	%f1127, %f1114, %f1118;
	add.f32 	%f1128, %f1127, %f1127;
	neg.f32 	%f1129, %f1118;
	fma.rn.f32 	%f1130, %f1129, %f1114, %f1128;
	mul.rn.f32 	%f1131, %f1116, %f1130;
	add.f32 	%f1132, %f1126, %f1118;
	sub.f32 	%f1133, %f1118, %f1132;
	add.f32 	%f1134, %f1126, %f1133;
	add.f32 	%f1135, %f1131, %f1134;
	add.f32 	%f1136, %f1132, %f1135;
	sub.f32 	%f1137, %f1132, %f1136;
	add.f32 	%f1138, %f1135, %f1137;
	mov.f32 	%f1139, 0f3F317200;
	mul.rn.f32 	%f1140, %f1112, %f1139;
	mov.f32 	%f1141, 0f35BFBE8E;
	mul.rn.f32 	%f1142, %f1112, %f1141;
	add.f32 	%f1143, %f1140, %f1136;
	sub.f32 	%f1144, %f1140, %f1143;
	add.f32 	%f1145, %f1136, %f1144;
	add.f32 	%f1146, %f1138, %f1145;
	add.f32 	%f1147, %f1142, %f1146;
	add.f32 	%f1148, %f1143, %f1147;
	sub.f32 	%f1149, %f1143, %f1148;
	add.f32 	%f1150, %f1147, %f1149;
	mov.f32 	%f1151, 0f3EE66666;
	mul.rn.f32 	%f1152, %f1151, %f1148;
	neg.f32 	%f1153, %f1152;
	fma.rn.f32 	%f1154, %f1151, %f1148, %f1153;
	fma.rn.f32 	%f1155, %f1151, %f1150, %f1154;
	mov.f32 	%f1156, 0f00000000;
	fma.rn.f32 	%f1157, %f1156, %f1148, %f1155;
	add.rn.f32 	%f1158, %f1152, %f1157;
	neg.f32 	%f1159, %f1158;
	add.rn.f32 	%f1160, %f1152, %f1159;
	add.rn.f32 	%f1161, %f1160, %f1157;
	mov.b32 	%r318, %f1158;
	setp.eq.s32 	%p89, %r318, 1118925336;
	add.s32 	%r319, %r318, -1;
	mov.b32 	%f1162, %r319;
	add.f32 	%f1163, %f1161, 0f37000000;
	selp.f32 	%f316, %f1163, %f1161, %p89;
	selp.f32 	%f1164, %f1162, %f1158, %p89;
	mov.f32 	%f1165, 0f3FB8AA3B;
	mul.rn.f32 	%f1166, %f1164, %f1165;
	cvt.rzi.f32.f32 	%f1167, %f1166;
	abs.f32 	%f1168, %f1167;
	setp.gt.f32 	%p90, %f1168, 0f42FC0000;
	mov.b32 	%r320, %f1167;
	and.b32  	%r321, %r320, -2147483648;
	or.b32  	%r322, %r321, 1123811328;
	mov.b32 	%f1169, %r322;
	selp.f32 	%f1170, %f1169, %f1167, %p90;
	mov.f32 	%f1171, 0fBF317218;
	fma.rn.f32 	%f1172, %f1170, %f1171, %f1164;
	mov.f32 	%f1173, 0f3102E308;
	fma.rn.f32 	%f1174, %f1170, %f1173, %f1172;
	mul.f32 	%f1175, %f1174, 0f3FB8AA3B;
	add.f32 	%f1176, %f1170, 0f4B40007F;
	mov.b32 	%r323, %f1176;
	shl.b32 	%r324, %r323, 23;
	mov.b32 	%f1177, %r324;
	ex2.approx.ftz.f32 	%f1178, %f1175;
	mul.f32 	%f317, %f1178, %f1177;
	setp.eq.f32 	%p91, %f317, 0f7F800000;
	mov.f32 	%f1908, 0f7F800000;
	@%p91 bra 	$L__BB0_74;

	fma.rn.f32 	%f1908, %f317, %f316, %f317;

$L__BB0_74:
	setp.lt.f32 	%p92, %f1841, 0f00000000;
	and.pred  	%p5, %p92, %p78;
	setp.eq.f32 	%p94, %f1841, 0f00000000;
	@%p94 bra 	$L__BB0_78;
	bra.uni 	$L__BB0_75;

$L__BB0_78:
	add.f32 	%f1183, %f1841, %f1841;
	selp.f32 	%f1910, %f1183, 0f00000000, %p78;
	bra.uni 	$L__BB0_79;

$L__BB0_75:
	mov.b32 	%r325, %f1908;
	xor.b32  	%r326, %r325, -2147483648;
	mov.b32 	%f1179, %r326;
	selp.f32 	%f1910, %f1179, %f1908, %p5;
	setp.geu.f32 	%p95, %f1841, 0f00000000;
	@%p95 bra 	$L__BB0_79;

	mov.f32 	%f1180, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1181, %f1180;
	setp.eq.f32 	%p96, %f1181, 0f3EE66666;
	@%p96 bra 	$L__BB0_79;

	mov.f32 	%f1910, 0f7FFFFFFF;

$L__BB0_79:
	add.f32 	%f1184, %f315, 0f3EE66666;
	mov.b32 	%r327, %f1184;
	setp.lt.s32 	%p98, %r327, 2139095040;
	@%p98 bra 	$L__BB0_84;

	setp.gtu.f32 	%p99, %f315, 0f7F800000;
	@%p99 bra 	$L__BB0_83;
	bra.uni 	$L__BB0_81;

$L__BB0_83:
	add.f32 	%f1910, %f1841, 0f3EE66666;
	bra.uni 	$L__BB0_84;

$L__BB0_81:
	setp.neu.f32 	%p100, %f315, 0f7F800000;
	@%p100 bra 	$L__BB0_84;

	selp.f32 	%f1910, 0fFF800000, 0f7F800000, %p5;

$L__BB0_84:
	setp.eq.f32 	%p101, %f1841, 0f3F800000;
	selp.f32 	%f326, 0f3F800000, %f1910, %p101;
	abs.f32 	%f327, %f1842;
	setp.lt.f32 	%p102, %f327, 0f00800000;
	mul.f32 	%f1186, %f327, 0f4B800000;
	selp.f32 	%f1187, %f1186, %f327, %p102;
	selp.f32 	%f1188, 0fC3170000, 0fC2FE0000, %p102;
	mov.b32 	%r328, %f1187;
	and.b32  	%r329, %r328, 8388607;
	or.b32  	%r330, %r329, 1065353216;
	mov.b32 	%f1189, %r330;
	shr.u32 	%r331, %r328, 23;
	cvt.rn.f32.u32 	%f1190, %r331;
	add.f32 	%f1191, %f1188, %f1190;
	setp.gt.f32 	%p103, %f1189, 0f3FB504F3;
	mul.f32 	%f1192, %f1189, 0f3F000000;
	add.f32 	%f1193, %f1191, 0f3F800000;
	selp.f32 	%f1194, %f1193, %f1191, %p103;
	selp.f32 	%f1195, %f1192, %f1189, %p103;
	add.f32 	%f1196, %f1195, 0fBF800000;
	add.f32 	%f1197, %f1195, 0f3F800000;
	rcp.approx.ftz.f32 	%f1198, %f1197;
	add.f32 	%f1199, %f1196, %f1196;
	mul.f32 	%f1200, %f1199, %f1198;
	mul.f32 	%f1201, %f1200, %f1200;
	mov.f32 	%f1202, 0f3C4CAF63;
	mov.f32 	%f1203, 0f3B18F0FE;
	fma.rn.f32 	%f1204, %f1203, %f1201, %f1202;
	mov.f32 	%f1205, 0f3DAAAABD;
	fma.rn.f32 	%f1206, %f1204, %f1201, %f1205;
	mul.rn.f32 	%f1207, %f1206, %f1201;
	mul.rn.f32 	%f1208, %f1207, %f1200;
	sub.f32 	%f1209, %f1196, %f1200;
	add.f32 	%f1210, %f1209, %f1209;
	neg.f32 	%f1211, %f1200;
	fma.rn.f32 	%f1212, %f1211, %f1196, %f1210;
	mul.rn.f32 	%f1213, %f1198, %f1212;
	add.f32 	%f1214, %f1208, %f1200;
	sub.f32 	%f1215, %f1200, %f1214;
	add.f32 	%f1216, %f1208, %f1215;
	add.f32 	%f1217, %f1213, %f1216;
	add.f32 	%f1218, %f1214, %f1217;
	sub.f32 	%f1219, %f1214, %f1218;
	add.f32 	%f1220, %f1217, %f1219;
	mov.f32 	%f1221, 0f3F317200;
	mul.rn.f32 	%f1222, %f1194, %f1221;
	mov.f32 	%f1223, 0f35BFBE8E;
	mul.rn.f32 	%f1224, %f1194, %f1223;
	add.f32 	%f1225, %f1222, %f1218;
	sub.f32 	%f1226, %f1222, %f1225;
	add.f32 	%f1227, %f1218, %f1226;
	add.f32 	%f1228, %f1220, %f1227;
	add.f32 	%f1229, %f1224, %f1228;
	add.f32 	%f1230, %f1225, %f1229;
	sub.f32 	%f1231, %f1225, %f1230;
	add.f32 	%f1232, %f1229, %f1231;
	mov.f32 	%f1233, 0f3EE66666;
	mul.rn.f32 	%f1234, %f1233, %f1230;
	neg.f32 	%f1235, %f1234;
	fma.rn.f32 	%f1236, %f1233, %f1230, %f1235;
	fma.rn.f32 	%f1237, %f1233, %f1232, %f1236;
	mov.f32 	%f1238, 0f00000000;
	fma.rn.f32 	%f1239, %f1238, %f1230, %f1237;
	add.rn.f32 	%f1240, %f1234, %f1239;
	neg.f32 	%f1241, %f1240;
	add.rn.f32 	%f1242, %f1234, %f1241;
	add.rn.f32 	%f1243, %f1242, %f1239;
	mov.b32 	%r332, %f1240;
	setp.eq.s32 	%p104, %r332, 1118925336;
	add.s32 	%r333, %r332, -1;
	mov.b32 	%f1244, %r333;
	add.f32 	%f1245, %f1243, 0f37000000;
	selp.f32 	%f328, %f1245, %f1243, %p104;
	selp.f32 	%f1246, %f1244, %f1240, %p104;
	mov.f32 	%f1247, 0f3FB8AA3B;
	mul.rn.f32 	%f1248, %f1246, %f1247;
	cvt.rzi.f32.f32 	%f1249, %f1248;
	abs.f32 	%f1250, %f1249;
	setp.gt.f32 	%p105, %f1250, 0f42FC0000;
	mov.b32 	%r334, %f1249;
	and.b32  	%r335, %r334, -2147483648;
	or.b32  	%r336, %r335, 1123811328;
	mov.b32 	%f1251, %r336;
	selp.f32 	%f1252, %f1251, %f1249, %p105;
	mov.f32 	%f1253, 0fBF317218;
	fma.rn.f32 	%f1254, %f1252, %f1253, %f1246;
	mov.f32 	%f1255, 0f3102E308;
	fma.rn.f32 	%f1256, %f1252, %f1255, %f1254;
	mul.f32 	%f1257, %f1256, 0f3FB8AA3B;
	add.f32 	%f1258, %f1252, 0f4B40007F;
	mov.b32 	%r337, %f1258;
	shl.b32 	%r338, %r337, 23;
	mov.b32 	%f1259, %r338;
	ex2.approx.ftz.f32 	%f1260, %f1257;
	mul.f32 	%f329, %f1260, %f1259;
	setp.eq.f32 	%p106, %f329, 0f7F800000;
	mov.f32 	%f1911, 0f7F800000;
	@%p106 bra 	$L__BB0_86;

	fma.rn.f32 	%f1911, %f329, %f328, %f329;

$L__BB0_86:
	setp.lt.f32 	%p107, %f1842, 0f00000000;
	and.pred  	%p6, %p107, %p78;
	setp.eq.f32 	%p109, %f1842, 0f00000000;
	@%p109 bra 	$L__BB0_90;
	bra.uni 	$L__BB0_87;

$L__BB0_90:
	add.f32 	%f1265, %f1842, %f1842;
	selp.f32 	%f1913, %f1265, 0f00000000, %p78;
	bra.uni 	$L__BB0_91;

$L__BB0_87:
	mov.b32 	%r339, %f1911;
	xor.b32  	%r340, %r339, -2147483648;
	mov.b32 	%f1261, %r340;
	selp.f32 	%f1913, %f1261, %f1911, %p6;
	setp.geu.f32 	%p110, %f1842, 0f00000000;
	@%p110 bra 	$L__BB0_91;

	mov.f32 	%f1262, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1263, %f1262;
	setp.eq.f32 	%p111, %f1263, 0f3EE66666;
	@%p111 bra 	$L__BB0_91;

	mov.f32 	%f1913, 0f7FFFFFFF;

$L__BB0_91:
	add.f32 	%f1266, %f327, 0f3EE66666;
	mov.b32 	%r341, %f1266;
	setp.lt.s32 	%p113, %r341, 2139095040;
	@%p113 bra 	$L__BB0_96;

	setp.gtu.f32 	%p114, %f327, 0f7F800000;
	@%p114 bra 	$L__BB0_95;
	bra.uni 	$L__BB0_93;

$L__BB0_95:
	add.f32 	%f1913, %f1842, 0f3EE66666;
	bra.uni 	$L__BB0_96;

$L__BB0_93:
	setp.neu.f32 	%p115, %f327, 0f7F800000;
	@%p115 bra 	$L__BB0_96;

	selp.f32 	%f1913, 0fFF800000, 0f7F800000, %p6;

$L__BB0_96:
	setp.eq.f32 	%p116, %f1842, 0f3F800000;
	mov.f32 	%f1268, 0f3F800000;
	selp.f32 	%f1269, 0f3F800000, %f1913, %p116;
	ld.const.u64 	%rd46, [params+144];
	cvta.to.global.u64 	%rd9, %rd46;
	ld.const.u32 	%r342, [params+136];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	cvt.u64.u32 	%rd10, %r343;
	min.f32 	%f1270, %f314, %f1268;
	mov.f32 	%f1271, 0f00000000;
	max.f32 	%f338, %f1271, %f1270;
	min.f32 	%f1272, %f326, %f1268;
	max.f32 	%f339, %f1271, %f1272;
	min.f32 	%f1273, %f1269, %f1268;
	max.f32 	%f340, %f1271, %f1273;
	mov.f32 	%f1274, 0f3E555555;
	cvt.rzi.f32.f32 	%f1275, %f1274;
	add.f32 	%f1276, %f1275, %f1275;
	mov.f32 	%f1277, 0f3ED55555;
	sub.f32 	%f1278, %f1277, %f1276;
	abs.f32 	%f341, %f1278;
	abs.f32 	%f342, %f338;
	setp.lt.f32 	%p117, %f342, 0f00800000;
	mul.f32 	%f1279, %f342, 0f4B800000;
	selp.f32 	%f1280, %f1279, %f342, %p117;
	selp.f32 	%f1281, 0fC3170000, 0fC2FE0000, %p117;
	mov.b32 	%r344, %f1280;
	and.b32  	%r345, %r344, 8388607;
	or.b32  	%r346, %r345, 1065353216;
	mov.b32 	%f1282, %r346;
	shr.u32 	%r347, %r344, 23;
	cvt.rn.f32.u32 	%f1283, %r347;
	add.f32 	%f1284, %f1281, %f1283;
	setp.gt.f32 	%p118, %f1282, 0f3FB504F3;
	mul.f32 	%f1285, %f1282, 0f3F000000;
	add.f32 	%f1286, %f1284, 0f3F800000;
	selp.f32 	%f1287, %f1286, %f1284, %p118;
	selp.f32 	%f1288, %f1285, %f1282, %p118;
	add.f32 	%f1289, %f1288, 0fBF800000;
	add.f32 	%f1290, %f1288, 0f3F800000;
	rcp.approx.ftz.f32 	%f1291, %f1290;
	add.f32 	%f1292, %f1289, %f1289;
	mul.f32 	%f1293, %f1292, %f1291;
	mul.f32 	%f1294, %f1293, %f1293;
	mov.f32 	%f1295, 0f3C4CAF63;
	mov.f32 	%f1296, 0f3B18F0FE;
	fma.rn.f32 	%f1297, %f1296, %f1294, %f1295;
	mov.f32 	%f1298, 0f3DAAAABD;
	fma.rn.f32 	%f1299, %f1297, %f1294, %f1298;
	mul.rn.f32 	%f1300, %f1299, %f1294;
	mul.rn.f32 	%f1301, %f1300, %f1293;
	sub.f32 	%f1302, %f1289, %f1293;
	add.f32 	%f1303, %f1302, %f1302;
	neg.f32 	%f1304, %f1293;
	fma.rn.f32 	%f1305, %f1304, %f1289, %f1303;
	mul.rn.f32 	%f1306, %f1291, %f1305;
	add.f32 	%f1307, %f1301, %f1293;
	sub.f32 	%f1308, %f1293, %f1307;
	add.f32 	%f1309, %f1301, %f1308;
	add.f32 	%f1310, %f1306, %f1309;
	add.f32 	%f1311, %f1307, %f1310;
	sub.f32 	%f1312, %f1307, %f1311;
	add.f32 	%f1313, %f1310, %f1312;
	mov.f32 	%f1314, 0f3F317200;
	mul.rn.f32 	%f1315, %f1287, %f1314;
	mov.f32 	%f1316, 0f35BFBE8E;
	mul.rn.f32 	%f1317, %f1287, %f1316;
	add.f32 	%f1318, %f1315, %f1311;
	sub.f32 	%f1319, %f1315, %f1318;
	add.f32 	%f1320, %f1311, %f1319;
	add.f32 	%f1321, %f1313, %f1320;
	add.f32 	%f1322, %f1317, %f1321;
	add.f32 	%f1323, %f1318, %f1322;
	sub.f32 	%f1324, %f1318, %f1323;
	add.f32 	%f1325, %f1322, %f1324;
	mul.rn.f32 	%f1326, %f1277, %f1323;
	neg.f32 	%f1327, %f1326;
	fma.rn.f32 	%f1328, %f1277, %f1323, %f1327;
	fma.rn.f32 	%f1329, %f1277, %f1325, %f1328;
	fma.rn.f32 	%f1330, %f1271, %f1323, %f1329;
	add.rn.f32 	%f1331, %f1326, %f1330;
	neg.f32 	%f1332, %f1331;
	add.rn.f32 	%f1333, %f1326, %f1332;
	add.rn.f32 	%f1334, %f1333, %f1330;
	mov.b32 	%r348, %f1331;
	setp.eq.s32 	%p119, %r348, 1118925336;
	add.s32 	%r349, %r348, -1;
	mov.b32 	%f1335, %r349;
	add.f32 	%f1336, %f1334, 0f37000000;
	selp.f32 	%f343, %f1336, %f1334, %p119;
	selp.f32 	%f1337, %f1335, %f1331, %p119;
	mov.f32 	%f1338, 0f3FB8AA3B;
	mul.rn.f32 	%f1339, %f1337, %f1338;
	cvt.rzi.f32.f32 	%f1340, %f1339;
	abs.f32 	%f1341, %f1340;
	setp.gt.f32 	%p120, %f1341, 0f42FC0000;
	mov.b32 	%r350, %f1340;
	and.b32  	%r351, %r350, -2147483648;
	or.b32  	%r352, %r351, 1123811328;
	mov.b32 	%f1342, %r352;
	selp.f32 	%f1343, %f1342, %f1340, %p120;
	mov.f32 	%f1344, 0fBF317218;
	fma.rn.f32 	%f1345, %f1343, %f1344, %f1337;
	mov.f32 	%f1346, 0f3102E308;
	fma.rn.f32 	%f1347, %f1343, %f1346, %f1345;
	mul.f32 	%f1348, %f1347, 0f3FB8AA3B;
	add.f32 	%f1349, %f1343, 0f4B40007F;
	mov.b32 	%r353, %f1349;
	shl.b32 	%r354, %r353, 23;
	mov.b32 	%f1350, %r354;
	ex2.approx.ftz.f32 	%f1351, %f1348;
	mul.f32 	%f344, %f1351, %f1350;
	setp.eq.f32 	%p121, %f344, 0f7F800000;
	mov.f32 	%f1914, 0f7F800000;
	@%p121 bra 	$L__BB0_98;

	fma.rn.f32 	%f1914, %f344, %f343, %f344;

$L__BB0_98:
	setp.lt.f32 	%p122, %f338, 0f00000000;
	setp.eq.f32 	%p123, %f341, 0f3F800000;
	and.pred  	%p7, %p122, %p123;
	setp.eq.f32 	%p124, %f338, 0f00000000;
	@%p124 bra 	$L__BB0_102;
	bra.uni 	$L__BB0_99;

$L__BB0_102:
	add.f32 	%f1356, %f338, %f338;
	selp.f32 	%f1916, %f1356, 0f00000000, %p123;
	bra.uni 	$L__BB0_103;

$L__BB0_99:
	mov.b32 	%r355, %f1914;
	xor.b32  	%r356, %r355, -2147483648;
	mov.b32 	%f1352, %r356;
	selp.f32 	%f1916, %f1352, %f1914, %p7;
	setp.geu.f32 	%p125, %f338, 0f00000000;
	@%p125 bra 	$L__BB0_103;

	mov.f32 	%f1353, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1354, %f1353;
	setp.eq.f32 	%p126, %f1354, 0f3ED55555;
	@%p126 bra 	$L__BB0_103;

	mov.f32 	%f1916, 0f7FFFFFFF;

$L__BB0_103:
	add.f32 	%f1357, %f342, 0f3ED55555;
	mov.b32 	%r357, %f1357;
	setp.lt.s32 	%p128, %r357, 2139095040;
	@%p128 bra 	$L__BB0_108;

	setp.gtu.f32 	%p129, %f342, 0f7F800000;
	@%p129 bra 	$L__BB0_107;
	bra.uni 	$L__BB0_105;

$L__BB0_107:
	add.f32 	%f1916, %f338, 0f3ED55555;
	bra.uni 	$L__BB0_108;

$L__BB0_105:
	setp.neu.f32 	%p130, %f342, 0f7F800000;
	@%p130 bra 	$L__BB0_108;

	selp.f32 	%f1916, 0fFF800000, 0f7F800000, %p7;

$L__BB0_108:
	abs.f32 	%f353, %f339;
	setp.lt.f32 	%p131, %f353, 0f00800000;
	mul.f32 	%f1359, %f353, 0f4B800000;
	selp.f32 	%f1360, %f1359, %f353, %p131;
	selp.f32 	%f1361, 0fC3170000, 0fC2FE0000, %p131;
	mov.b32 	%r358, %f1360;
	and.b32  	%r359, %r358, 8388607;
	or.b32  	%r360, %r359, 1065353216;
	mov.b32 	%f1362, %r360;
	shr.u32 	%r361, %r358, 23;
	cvt.rn.f32.u32 	%f1363, %r361;
	add.f32 	%f1364, %f1361, %f1363;
	setp.gt.f32 	%p132, %f1362, 0f3FB504F3;
	mul.f32 	%f1365, %f1362, 0f3F000000;
	add.f32 	%f1366, %f1364, 0f3F800000;
	selp.f32 	%f1367, %f1366, %f1364, %p132;
	selp.f32 	%f1368, %f1365, %f1362, %p132;
	add.f32 	%f1369, %f1368, 0fBF800000;
	add.f32 	%f1370, %f1368, 0f3F800000;
	rcp.approx.ftz.f32 	%f1371, %f1370;
	add.f32 	%f1372, %f1369, %f1369;
	mul.f32 	%f1373, %f1372, %f1371;
	mul.f32 	%f1374, %f1373, %f1373;
	mov.f32 	%f1375, 0f3C4CAF63;
	mov.f32 	%f1376, 0f3B18F0FE;
	fma.rn.f32 	%f1377, %f1376, %f1374, %f1375;
	mov.f32 	%f1378, 0f3DAAAABD;
	fma.rn.f32 	%f1379, %f1377, %f1374, %f1378;
	mul.rn.f32 	%f1380, %f1379, %f1374;
	mul.rn.f32 	%f1381, %f1380, %f1373;
	sub.f32 	%f1382, %f1369, %f1373;
	add.f32 	%f1383, %f1382, %f1382;
	neg.f32 	%f1384, %f1373;
	fma.rn.f32 	%f1385, %f1384, %f1369, %f1383;
	mul.rn.f32 	%f1386, %f1371, %f1385;
	add.f32 	%f1387, %f1381, %f1373;
	sub.f32 	%f1388, %f1373, %f1387;
	add.f32 	%f1389, %f1381, %f1388;
	add.f32 	%f1390, %f1386, %f1389;
	add.f32 	%f1391, %f1387, %f1390;
	sub.f32 	%f1392, %f1387, %f1391;
	add.f32 	%f1393, %f1390, %f1392;
	mov.f32 	%f1394, 0f3F317200;
	mul.rn.f32 	%f1395, %f1367, %f1394;
	mov.f32 	%f1396, 0f35BFBE8E;
	mul.rn.f32 	%f1397, %f1367, %f1396;
	add.f32 	%f1398, %f1395, %f1391;
	sub.f32 	%f1399, %f1395, %f1398;
	add.f32 	%f1400, %f1391, %f1399;
	add.f32 	%f1401, %f1393, %f1400;
	add.f32 	%f1402, %f1397, %f1401;
	add.f32 	%f1403, %f1398, %f1402;
	sub.f32 	%f1404, %f1398, %f1403;
	add.f32 	%f1405, %f1402, %f1404;
	mov.f32 	%f1406, 0f3ED55555;
	mul.rn.f32 	%f1407, %f1406, %f1403;
	neg.f32 	%f1408, %f1407;
	fma.rn.f32 	%f1409, %f1406, %f1403, %f1408;
	fma.rn.f32 	%f1410, %f1406, %f1405, %f1409;
	mov.f32 	%f1411, 0f00000000;
	fma.rn.f32 	%f1412, %f1411, %f1403, %f1410;
	add.rn.f32 	%f1413, %f1407, %f1412;
	neg.f32 	%f1414, %f1413;
	add.rn.f32 	%f1415, %f1407, %f1414;
	add.rn.f32 	%f1416, %f1415, %f1412;
	mov.b32 	%r362, %f1413;
	setp.eq.s32 	%p133, %r362, 1118925336;
	add.s32 	%r363, %r362, -1;
	mov.b32 	%f1417, %r363;
	add.f32 	%f1418, %f1416, 0f37000000;
	selp.f32 	%f354, %f1418, %f1416, %p133;
	selp.f32 	%f1419, %f1417, %f1413, %p133;
	mov.f32 	%f1420, 0f3FB8AA3B;
	mul.rn.f32 	%f1421, %f1419, %f1420;
	cvt.rzi.f32.f32 	%f1422, %f1421;
	abs.f32 	%f1423, %f1422;
	setp.gt.f32 	%p134, %f1423, 0f42FC0000;
	mov.b32 	%r364, %f1422;
	and.b32  	%r365, %r364, -2147483648;
	or.b32  	%r366, %r365, 1123811328;
	mov.b32 	%f1424, %r366;
	selp.f32 	%f1425, %f1424, %f1422, %p134;
	mov.f32 	%f1426, 0fBF317218;
	fma.rn.f32 	%f1427, %f1425, %f1426, %f1419;
	mov.f32 	%f1428, 0f3102E308;
	fma.rn.f32 	%f1429, %f1425, %f1428, %f1427;
	mul.f32 	%f1430, %f1429, 0f3FB8AA3B;
	add.f32 	%f1431, %f1425, 0f4B40007F;
	mov.b32 	%r367, %f1431;
	shl.b32 	%r368, %r367, 23;
	mov.b32 	%f1432, %r368;
	ex2.approx.ftz.f32 	%f1433, %f1430;
	mul.f32 	%f355, %f1433, %f1432;
	setp.eq.f32 	%p135, %f355, 0f7F800000;
	mov.f32 	%f1917, 0f7F800000;
	@%p135 bra 	$L__BB0_110;

	fma.rn.f32 	%f1917, %f355, %f354, %f355;

$L__BB0_110:
	setp.lt.f32 	%p136, %f339, 0f00000000;
	and.pred  	%p8, %p136, %p123;
	setp.eq.f32 	%p138, %f339, 0f00000000;
	@%p138 bra 	$L__BB0_114;
	bra.uni 	$L__BB0_111;

$L__BB0_114:
	add.f32 	%f1438, %f339, %f339;
	selp.f32 	%f1919, %f1438, 0f00000000, %p123;
	bra.uni 	$L__BB0_115;

$L__BB0_111:
	mov.b32 	%r369, %f1917;
	xor.b32  	%r370, %r369, -2147483648;
	mov.b32 	%f1434, %r370;
	selp.f32 	%f1919, %f1434, %f1917, %p8;
	setp.geu.f32 	%p139, %f339, 0f00000000;
	@%p139 bra 	$L__BB0_115;

	mov.f32 	%f1435, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1436, %f1435;
	setp.eq.f32 	%p140, %f1436, 0f3ED55555;
	@%p140 bra 	$L__BB0_115;

	mov.f32 	%f1919, 0f7FFFFFFF;

$L__BB0_115:
	add.f32 	%f1439, %f353, 0f3ED55555;
	mov.b32 	%r371, %f1439;
	setp.lt.s32 	%p142, %r371, 2139095040;
	@%p142 bra 	$L__BB0_120;

	setp.gtu.f32 	%p143, %f353, 0f7F800000;
	@%p143 bra 	$L__BB0_119;
	bra.uni 	$L__BB0_117;

$L__BB0_119:
	add.f32 	%f1919, %f339, 0f3ED55555;
	bra.uni 	$L__BB0_120;

$L__BB0_117:
	setp.neu.f32 	%p144, %f353, 0f7F800000;
	@%p144 bra 	$L__BB0_120;

	selp.f32 	%f1919, 0fFF800000, 0f7F800000, %p8;

$L__BB0_120:
	abs.f32 	%f364, %f340;
	setp.lt.f32 	%p145, %f364, 0f00800000;
	mul.f32 	%f1441, %f364, 0f4B800000;
	selp.f32 	%f1442, %f1441, %f364, %p145;
	selp.f32 	%f1443, 0fC3170000, 0fC2FE0000, %p145;
	mov.b32 	%r372, %f1442;
	and.b32  	%r373, %r372, 8388607;
	or.b32  	%r374, %r373, 1065353216;
	mov.b32 	%f1444, %r374;
	shr.u32 	%r375, %r372, 23;
	cvt.rn.f32.u32 	%f1445, %r375;
	add.f32 	%f1446, %f1443, %f1445;
	setp.gt.f32 	%p146, %f1444, 0f3FB504F3;
	mul.f32 	%f1447, %f1444, 0f3F000000;
	add.f32 	%f1448, %f1446, 0f3F800000;
	selp.f32 	%f1449, %f1448, %f1446, %p146;
	selp.f32 	%f1450, %f1447, %f1444, %p146;
	add.f32 	%f1451, %f1450, 0fBF800000;
	add.f32 	%f1452, %f1450, 0f3F800000;
	rcp.approx.ftz.f32 	%f1453, %f1452;
	add.f32 	%f1454, %f1451, %f1451;
	mul.f32 	%f1455, %f1454, %f1453;
	mul.f32 	%f1456, %f1455, %f1455;
	mov.f32 	%f1457, 0f3C4CAF63;
	mov.f32 	%f1458, 0f3B18F0FE;
	fma.rn.f32 	%f1459, %f1458, %f1456, %f1457;
	mov.f32 	%f1460, 0f3DAAAABD;
	fma.rn.f32 	%f1461, %f1459, %f1456, %f1460;
	mul.rn.f32 	%f1462, %f1461, %f1456;
	mul.rn.f32 	%f1463, %f1462, %f1455;
	sub.f32 	%f1464, %f1451, %f1455;
	add.f32 	%f1465, %f1464, %f1464;
	neg.f32 	%f1466, %f1455;
	fma.rn.f32 	%f1467, %f1466, %f1451, %f1465;
	mul.rn.f32 	%f1468, %f1453, %f1467;
	add.f32 	%f1469, %f1463, %f1455;
	sub.f32 	%f1470, %f1455, %f1469;
	add.f32 	%f1471, %f1463, %f1470;
	add.f32 	%f1472, %f1468, %f1471;
	add.f32 	%f1473, %f1469, %f1472;
	sub.f32 	%f1474, %f1469, %f1473;
	add.f32 	%f1475, %f1472, %f1474;
	mov.f32 	%f1476, 0f3F317200;
	mul.rn.f32 	%f1477, %f1449, %f1476;
	mov.f32 	%f1478, 0f35BFBE8E;
	mul.rn.f32 	%f1479, %f1449, %f1478;
	add.f32 	%f1480, %f1477, %f1473;
	sub.f32 	%f1481, %f1477, %f1480;
	add.f32 	%f1482, %f1473, %f1481;
	add.f32 	%f1483, %f1475, %f1482;
	add.f32 	%f1484, %f1479, %f1483;
	add.f32 	%f1485, %f1480, %f1484;
	sub.f32 	%f1486, %f1480, %f1485;
	add.f32 	%f1487, %f1484, %f1486;
	mov.f32 	%f1488, 0f3ED55555;
	mul.rn.f32 	%f1489, %f1488, %f1485;
	neg.f32 	%f1490, %f1489;
	fma.rn.f32 	%f1491, %f1488, %f1485, %f1490;
	fma.rn.f32 	%f1492, %f1488, %f1487, %f1491;
	mov.f32 	%f1493, 0f00000000;
	fma.rn.f32 	%f1494, %f1493, %f1485, %f1492;
	add.rn.f32 	%f1495, %f1489, %f1494;
	neg.f32 	%f1496, %f1495;
	add.rn.f32 	%f1497, %f1489, %f1496;
	add.rn.f32 	%f1498, %f1497, %f1494;
	mov.b32 	%r376, %f1495;
	setp.eq.s32 	%p147, %r376, 1118925336;
	add.s32 	%r377, %r376, -1;
	mov.b32 	%f1499, %r377;
	add.f32 	%f1500, %f1498, 0f37000000;
	selp.f32 	%f365, %f1500, %f1498, %p147;
	selp.f32 	%f1501, %f1499, %f1495, %p147;
	mov.f32 	%f1502, 0f3FB8AA3B;
	mul.rn.f32 	%f1503, %f1501, %f1502;
	cvt.rzi.f32.f32 	%f1504, %f1503;
	abs.f32 	%f1505, %f1504;
	setp.gt.f32 	%p148, %f1505, 0f42FC0000;
	mov.b32 	%r378, %f1504;
	and.b32  	%r379, %r378, -2147483648;
	or.b32  	%r380, %r379, 1123811328;
	mov.b32 	%f1506, %r380;
	selp.f32 	%f1507, %f1506, %f1504, %p148;
	mov.f32 	%f1508, 0fBF317218;
	fma.rn.f32 	%f1509, %f1507, %f1508, %f1501;
	mov.f32 	%f1510, 0f3102E308;
	fma.rn.f32 	%f1511, %f1507, %f1510, %f1509;
	mul.f32 	%f1512, %f1511, 0f3FB8AA3B;
	add.f32 	%f1513, %f1507, 0f4B40007F;
	mov.b32 	%r381, %f1513;
	shl.b32 	%r382, %r381, 23;
	mov.b32 	%f1514, %r382;
	ex2.approx.ftz.f32 	%f1515, %f1512;
	mul.f32 	%f366, %f1515, %f1514;
	setp.eq.f32 	%p149, %f366, 0f7F800000;
	mov.f32 	%f1920, 0f7F800000;
	@%p149 bra 	$L__BB0_122;

	fma.rn.f32 	%f1920, %f366, %f365, %f366;

$L__BB0_122:
	setp.lt.f32 	%p150, %f340, 0f00000000;
	and.pred  	%p9, %p150, %p123;
	setp.eq.f32 	%p152, %f340, 0f00000000;
	@%p152 bra 	$L__BB0_126;
	bra.uni 	$L__BB0_123;

$L__BB0_126:
	add.f32 	%f1520, %f340, %f340;
	selp.f32 	%f1922, %f1520, 0f00000000, %p123;
	bra.uni 	$L__BB0_127;

$L__BB0_123:
	mov.b32 	%r383, %f1920;
	xor.b32  	%r384, %r383, -2147483648;
	mov.b32 	%f1516, %r384;
	selp.f32 	%f1922, %f1516, %f1920, %p9;
	setp.geu.f32 	%p153, %f340, 0f00000000;
	@%p153 bra 	$L__BB0_127;

	mov.f32 	%f1517, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1518, %f1517;
	setp.eq.f32 	%p154, %f1518, 0f3ED55555;
	@%p154 bra 	$L__BB0_127;

	mov.f32 	%f1922, 0f7FFFFFFF;

$L__BB0_127:
	add.f32 	%f1521, %f364, 0f3ED55555;
	mov.b32 	%r385, %f1521;
	setp.lt.s32 	%p156, %r385, 2139095040;
	@%p156 bra 	$L__BB0_132;

	setp.gtu.f32 	%p157, %f364, 0f7F800000;
	@%p157 bra 	$L__BB0_131;
	bra.uni 	$L__BB0_129;

$L__BB0_131:
	add.f32 	%f1922, %f340, 0f3ED55555;
	bra.uni 	$L__BB0_132;

$L__BB0_129:
	setp.neu.f32 	%p158, %f364, 0f7F800000;
	@%p158 bra 	$L__BB0_132;

	selp.f32 	%f1922, 0fFF800000, 0f7F800000, %p9;

$L__BB0_132:
	fma.rn.f32 	%f1522, %f1916, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p159, %f338, 0f3F800000;
	mov.f32 	%f1523, 0f3F800000;
	selp.f32 	%f1524, 0f3F7FFFFF, %f1522, %p159;
	mul.f32 	%f1525, %f338, 0f414EB852;
	setp.lt.f32 	%p160, %f338, 0f3B4D2E1C;
	selp.f32 	%f1526, %f1525, %f1524, %p160;
	fma.rn.f32 	%f1527, %f1919, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p161, %f339, 0f3F800000;
	selp.f32 	%f1528, 0f3F7FFFFF, %f1527, %p161;
	mul.f32 	%f1529, %f339, 0f414EB852;
	setp.lt.f32 	%p162, %f339, 0f3B4D2E1C;
	selp.f32 	%f1530, %f1529, %f1528, %p162;
	fma.rn.f32 	%f1531, %f1922, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p163, %f340, 0f3F800000;
	selp.f32 	%f1532, 0f3F7FFFFF, %f1531, %p163;
	mul.f32 	%f1533, %f340, 0f414EB852;
	setp.lt.f32 	%p164, %f340, 0f3B4D2E1C;
	selp.f32 	%f1534, %f1533, %f1532, %p164;
	min.f32 	%f1535, %f1526, %f1523;
	mov.f32 	%f1536, 0f00000000;
	max.f32 	%f1537, %f1536, %f1535;
	mul.f32 	%f1538, %f1537, 0f43800000;
	cvt.rzi.u32.f32 	%r386, %f1538;
	min.u32 	%r387, %r386, 255;
	min.f32 	%f1539, %f1530, %f1523;
	max.f32 	%f1540, %f1536, %f1539;
	mul.f32 	%f1541, %f1540, 0f43800000;
	cvt.rzi.u32.f32 	%r388, %f1541;
	min.u32 	%r389, %r388, 255;
	min.f32 	%f1542, %f1534, %f1523;
	max.f32 	%f1543, %f1536, %f1542;
	mul.f32 	%f1544, %f1543, 0f43800000;
	cvt.rzi.u32.f32 	%r390, %f1544;
	min.u32 	%r391, %r390, 255;
	shl.b64 	%rd47, %rd10, 2;
	add.s64 	%rd48, %rd9, %rd47;
	cvt.u16.u32 	%rs20, %r391;
	cvt.u16.u32 	%rs21, %r389;
	cvt.u16.u32 	%rs22, %r387;
	mov.u16 	%rs23, 255;
	st.global.v4.u8 	[%rd48], {%rs22, %rs21, %rs20, %rs23};

$L__BB0_133:
	and.b32  	%r392, %r447, 4;
	setp.eq.s32 	%p165, %r392, 0;
	ld.const.u32 	%r448, [params+108];
	@%p165 bra 	$L__BB0_137;

	setp.eq.s32 	%p166, %r448, 0;
	ld.const.u64 	%rd49, [params+224];
	cvta.to.global.u64 	%rd50, %rd49;
	ld.const.u32 	%r393, [params+216];
	mad.lo.s32 	%r394, %r393, %r4, %r3;
	mul.wide.u32 	%rd51, %r394, 8;
	add.s64 	%rd11, %rd50, %rd51;
	@%p166 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs31, %rs32, %rs33, %rs34}, [%rd11];
	// begin inline asm
	{  cvt.f32.f16 %f1545, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1546, %rs32;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1547, %rs33;}

	// end inline asm
	add.f32 	%f1548, %f1840, %f1545;
	add.f32 	%f1549, %f1841, %f1546;
	add.f32 	%f1550, %f1842, %f1547;
	mov.f32 	%f1551, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1550;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1549;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1548;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1551;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs27, %rs28, %rs29, %rs30};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1555, 0f3F800000;
	mov.u32 	%r448, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1555;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f1842;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1841;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f1840;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs35, %rs36, %rs37, %rs38};

$L__BB0_137:
	mul.f32 	%f375, %f1843, 0f3F558750;
	mul.f32 	%f376, %f1844, 0f3F558750;
	mul.f32 	%f377, %f1845, 0f3F558750;
	ld.const.u64 	%rd52, [params+256];
	cvta.to.global.u64 	%rd53, %rd52;
	ld.const.u32 	%r396, [params+248];
	mad.lo.s32 	%r397, %r396, %r4, %r3;
	mul.wide.u32 	%rd54, %r397, 8;
	add.s64 	%rd12, %rd53, %rd54;
	setp.eq.s32 	%p167, %r448, 0;
	@%p167 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs46, %rs47, %rs48, %rs49}, [%rd12];
	// begin inline asm
	{  cvt.f32.f16 %f1556, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1557, %rs47;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1558, %rs48;}

	// end inline asm
	add.f32 	%f1559, %f375, %f1556;
	add.f32 	%f1560, %f376, %f1557;
	add.f32 	%f1561, %f377, %f1558;
	mov.f32 	%f1562, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1561;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1560;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1559;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f1562;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs42, %rs43, %rs44, %rs45};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1566, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1566;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f377;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f376;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f375;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs50, %rs51, %rs52, %rs53};

$L__BB0_140:
	mul.f32 	%f378, %f1846, 0f3FB8EBD1;
	mul.f32 	%f379, %f1847, 0f3FB8EBD1;
	mul.f32 	%f380, %f1848, 0f3FB8EBD1;
	ld.const.u64 	%rd55, [params+272];
	cvta.to.global.u64 	%rd56, %rd55;
	ld.const.u32 	%r398, [params+264];
	mad.lo.s32 	%r399, %r398, %r4, %r3;
	mul.wide.u32 	%rd57, %r399, 8;
	add.s64 	%rd13, %rd56, %rd57;
	@%p167 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs61, %rs62, %rs63, %rs64}, [%rd13];
	// begin inline asm
	{  cvt.f32.f16 %f1567, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1568, %rs62;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1569, %rs63;}

	// end inline asm
	add.f32 	%f1570, %f378, %f1567;
	add.f32 	%f1571, %f379, %f1568;
	add.f32 	%f1572, %f380, %f1569;
	mov.f32 	%f1573, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1572;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1571;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1570;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1573;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs57, %rs58, %rs59, %rs60};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1577, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1577;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f380;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f379;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f378;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs65, %rs66, %rs67, %rs68};

$L__BB0_143:
	mul.f32 	%f381, %f1849, 0f3FB8EBD1;
	mul.f32 	%f382, %f1850, 0f3FB8EBD1;
	mul.f32 	%f383, %f1851, 0f3FB8EBD1;
	ld.const.u64 	%rd58, [params+288];
	cvta.to.global.u64 	%rd59, %rd58;
	ld.const.u32 	%r400, [params+280];
	mad.lo.s32 	%r401, %r400, %r4, %r3;
	mul.wide.u32 	%rd60, %r401, 8;
	add.s64 	%rd14, %rd59, %rd60;
	@%p167 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs76, %rs77, %rs78, %rs79}, [%rd14];
	// begin inline asm
	{  cvt.f32.f16 %f1578, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1579, %rs77;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1580, %rs78;}

	// end inline asm
	add.f32 	%f1581, %f381, %f1578;
	add.f32 	%f1582, %f382, %f1579;
	add.f32 	%f1583, %f383, %f1580;
	mov.f32 	%f1584, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1583;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1582;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1581;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f1584;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs72, %rs73, %rs74, %rs75};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1588, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1588;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f383;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f382;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f381;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs80, %rs81, %rs82, %rs83};

$L__BB0_146:
	mul.f32 	%f384, %f1852, 0f3FB8EBD1;
	mul.f32 	%f385, %f1853, 0f3FB8EBD1;
	mul.f32 	%f386, %f1854, 0f3FB8EBD1;
	ld.const.u64 	%rd61, [params+304];
	cvta.to.global.u64 	%rd62, %rd61;
	ld.const.u32 	%r402, [params+296];
	mad.lo.s32 	%r403, %r402, %r4, %r3;
	mul.wide.u32 	%rd63, %r403, 8;
	add.s64 	%rd15, %rd62, %rd63;
	@%p167 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs91, %rs92, %rs93, %rs94}, [%rd15];
	// begin inline asm
	{  cvt.f32.f16 %f1589, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1590, %rs92;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1591, %rs93;}

	// end inline asm
	add.f32 	%f1592, %f384, %f1589;
	add.f32 	%f1593, %f385, %f1590;
	add.f32 	%f1594, %f386, %f1591;
	mov.f32 	%f1595, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1594;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1593;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1592;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f1595;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs87, %rs88, %rs89, %rs90};
	bra.uni 	$L__BB0_149;

$L__BB0_148:
	mov.f32 	%f1599, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1599;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f386;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f385;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f384;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs95, %rs96, %rs97, %rs98};

$L__BB0_149:
	mul.f32 	%f387, %f1855, 0f404EBF87;
	mul.f32 	%f388, %f1856, 0f404EBF87;
	mul.f32 	%f389, %f1857, 0f404EBF87;
	ld.const.u64 	%rd64, [params+320];
	cvta.to.global.u64 	%rd65, %rd64;
	ld.const.u32 	%r404, [params+312];
	mad.lo.s32 	%r405, %r404, %r4, %r3;
	mul.wide.u32 	%rd66, %r405, 8;
	add.s64 	%rd16, %rd65, %rd66;
	@%p167 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f1600, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1601, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1602, %rs108;}

	// end inline asm
	add.f32 	%f1603, %f387, %f1600;
	add.f32 	%f1604, %f388, %f1601;
	add.f32 	%f1605, %f389, %f1602;
	mov.f32 	%f1606, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1605;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1604;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs102, %f1603;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1606;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs102, %rs103, %rs104, %rs105};
	bra.uni 	$L__BB0_152;

$L__BB0_151:
	mov.f32 	%f1610, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1610;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f389;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f388;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs110, %f387;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs110, %rs111, %rs112, %rs113};

$L__BB0_152:
	mul.f32 	%f390, %f1858, 0f404EBF87;
	mul.f32 	%f391, %f1859, 0f404EBF87;
	mul.f32 	%f392, %f1860, 0f404EBF87;
	ld.const.u64 	%rd67, [params+336];
	cvta.to.global.u64 	%rd68, %rd67;
	ld.const.u32 	%r406, [params+328];
	mad.lo.s32 	%r407, %r406, %r4, %r3;
	mul.wide.u32 	%rd69, %r407, 8;
	add.s64 	%rd17, %rd68, %rd69;
	@%p167 bra 	$L__BB0_154;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd17];
	// begin inline asm
	{  cvt.f32.f16 %f1611, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1612, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1613, %rs123;}

	// end inline asm
	add.f32 	%f1614, %f390, %f1611;
	add.f32 	%f1615, %f391, %f1612;
	add.f32 	%f1616, %f392, %f1613;
	mov.f32 	%f1617, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1616;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1615;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs117, %f1614;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1617;}

	// end inline asm
	st.global.v4.u16 	[%rd17], {%rs117, %rs118, %rs119, %rs120};
	bra.uni 	$L__BB0_155;

$L__BB0_154:
	mov.f32 	%f1621, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1621;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f392;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f391;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs125, %f390;}

	// end inline asm
	st.global.v4.u16 	[%rd17], {%rs125, %rs126, %rs127, %rs128};

$L__BB0_155:
	mul.f32 	%f393, %f1861, 0f40330C94;
	mul.f32 	%f394, %f1862, 0f40330C94;
	mul.f32 	%f395, %f1863, 0f40330C94;
	ld.const.u64 	%rd70, [params+352];
	cvta.to.global.u64 	%rd71, %rd70;
	ld.const.u32 	%r408, [params+344];
	mad.lo.s32 	%r409, %r408, %r4, %r3;
	mul.wide.u32 	%rd72, %r409, 8;
	add.s64 	%rd18, %rd71, %rd72;
	@%p167 bra 	$L__BB0_157;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f1622, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1623, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1624, %rs138;}

	// end inline asm
	add.f32 	%f1625, %f393, %f1622;
	add.f32 	%f1626, %f394, %f1623;
	add.f32 	%f1627, %f395, %f1624;
	mov.f32 	%f1628, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1627;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1626;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs132, %f1625;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1628;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs132, %rs133, %rs134, %rs135};
	bra.uni 	$L__BB0_158;

$L__BB0_157:
	mov.f32 	%f1632, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1632;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f395;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f394;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs140, %f393;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs140, %rs141, %rs142, %rs143};

$L__BB0_158:
	mul.f32 	%f396, %f1864, 0f404EBF87;
	mul.f32 	%f397, %f1865, 0f404EBF87;
	mul.f32 	%f398, %f1866, 0f404EBF87;
	ld.const.u64 	%rd73, [params+368];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r410, [params+360];
	mad.lo.s32 	%r411, %r410, %r4, %r3;
	mul.wide.u32 	%rd75, %r411, 8;
	add.s64 	%rd19, %rd74, %rd75;
	@%p167 bra 	$L__BB0_160;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1633, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1634, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1635, %rs153;}

	// end inline asm
	add.f32 	%f1636, %f396, %f1633;
	add.f32 	%f1637, %f397, %f1634;
	add.f32 	%f1638, %f398, %f1635;
	mov.f32 	%f1639, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1638;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1637;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs147, %f1636;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1639;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs147, %rs148, %rs149, %rs150};
	bra.uni 	$L__BB0_161;

$L__BB0_160:
	mov.f32 	%f1643, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1643;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f398;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f397;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs155, %f396;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs155, %rs156, %rs157, %rs158};

$L__BB0_161:
	mul.f32 	%f399, %f1867, 0f3FCEBF87;
	mul.f32 	%f400, %f1868, 0f3FCEBF87;
	mul.f32 	%f401, %f1869, 0f3FCEBF87;
	ld.const.u64 	%rd76, [params+384];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r412, [params+376];
	mad.lo.s32 	%r413, %r412, %r4, %r3;
	mul.wide.u32 	%rd78, %r413, 8;
	add.s64 	%rd20, %rd77, %rd78;
	@%p167 bra 	$L__BB0_163;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1644, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1645, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1646, %rs168;}

	// end inline asm
	add.f32 	%f1647, %f399, %f1644;
	add.f32 	%f1648, %f400, %f1645;
	add.f32 	%f1649, %f401, %f1646;
	mov.f32 	%f1650, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1649;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1648;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs162, %f1647;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1650;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs162, %rs163, %rs164, %rs165};
	bra.uni 	$L__BB0_199;

$L__BB0_163:
	mov.f32 	%f1654, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1654;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f401;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f400;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs170, %f399;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs170, %rs171, %rs172, %rs173};

$L__BB0_199:
	ret;

}