//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];

.visible .entry __raygen__oxMain()
{
	.reg .pred 	%p<183>;
	.reg .b16 	%rs<180>;
	.reg .f32 	%f<1584>;
	.reg .b32 	%r<430>;
	.reg .b64 	%rd<78>;


	// begin inline asm
	call (%r26), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r27), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd21, [params+400];
	cvta.to.global.u64 	%rd22, %rd21;
	ld.const.u32 	%r32, [params+392];
	mad.lo.s32 	%r33, %r32, %r27, %r26;
	mul.wide.u32 	%rd23, %r33, 4;
	add.s64 	%rd1, %rd22, %rd23;
	ld.global.v2.u8 	{%rs9, %rs178}, [%rd1];
	or.b16  	%rs11, %rs9, %rs178;
	and.b16  	%rs12, %rs11, 255;
	setp.eq.s16 	%p10, %rs12, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs177, [%rd1+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs177, [%rd1+2];
	setp.eq.s16 	%p11, %rs177, 0;
	mov.f32 	%f1480, 0f00000000;
	mov.u16 	%rs178, 0;
	mov.f32 	%f1481, %f1480;
	mov.f32 	%f1482, %f1480;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f294, %rs9;
	div.rn.f32 	%f295, %f294, 0f437F0000;
	fma.rn.f32 	%f296, %f295, 0f40000000, 0fBF800000;
	and.b16  	%rs15, %rs178, 255;
	cvt.rn.f32.u16 	%f297, %rs15;
	div.rn.f32 	%f298, %f297, 0f437F0000;
	fma.rn.f32 	%f299, %f298, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f300, %rs177;
	div.rn.f32 	%f301, %f300, 0f437F0000;
	fma.rn.f32 	%f302, %f301, 0f40000000, 0fBF800000;
	mul.f32 	%f303, %f299, %f299;
	fma.rn.f32 	%f304, %f296, %f296, %f303;
	fma.rn.f32 	%f305, %f302, %f302, %f304;
	sqrt.rn.f32 	%f306, %f305;
	rcp.rn.f32 	%f307, %f306;
	mul.f32 	%f1482, %f307, %f302;
	mul.f32 	%f1481, %f307, %f299;
	mul.f32 	%f1480, %f296, %f307;

$L__BB0_4:
	ld.const.v2.u32 	{%r34, %r35}, [params];
	add.s32 	%r3, %r34, %r26;
	add.s32 	%r4, %r35, %r27;
	setp.eq.f32 	%p12, %f1480, 0f00000000;
	setp.eq.f32 	%p13, %f1481, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1482, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_149;
	bra.uni 	$L__BB0_5;

$L__BB0_149:
	ld.const.u32 	%r23, [params+104];
	and.b32  	%r404, %r23, 1;
	setp.eq.b32 	%p171, %r404, 1;
	mov.pred 	%p172, 0;
	xor.pred  	%p173, %p171, %p172;
	not.pred 	%p174, %p173;
	@%p174 bra 	$L__BB0_151;

	ld.const.u64 	%rd54, [params+144];
	cvta.to.global.u64 	%rd55, %rd54;
	ld.const.u32 	%r405, [params+136];
	mad.lo.s32 	%r406, %r405, %r4, %r3;
	mul.wide.u32 	%rd56, %r406, 4;
	add.s64 	%rd57, %rd55, %rd56;
	mov.u16 	%rs99, 0;
	st.global.v4.u8 	[%rd57], {%rs99, %rs99, %rs99, %rs99};

$L__BB0_151:
	and.b32  	%r407, %r23, 8;
	setp.eq.s32 	%p175, %r407, 0;
	@%p175 bra 	$L__BB0_153;

	ld.const.u64 	%rd58, [params+192];
	cvta.to.global.u64 	%rd59, %rd58;
	ld.const.u32 	%r408, [params+184];
	mad.lo.s32 	%r409, %r408, %r4, %r3;
	mov.f32 	%f1431, 0f00000000;
	cvt.rzi.u32.f32 	%r410, %f1431;
	mul.wide.u32 	%rd60, %r409, 2;
	add.s64 	%rd61, %rd59, %rd60;
	mov.u16 	%rs100, 0;
	cvt.u16.u32 	%rs101, %r410;
	st.global.v2.u8 	[%rd61], {%rs101, %rs100};

$L__BB0_153:
	and.b32  	%r411, %r23, 4;
	setp.eq.s32 	%p176, %r411, 0;
	ld.const.u32 	%r429, [params+108];
	@%p176 bra 	$L__BB0_157;

	setp.eq.s32 	%p177, %r429, 0;
	ld.const.u64 	%rd62, [params+224];
	cvta.to.global.u64 	%rd63, %rd62;
	ld.const.u32 	%r412, [params+216];
	mad.lo.s32 	%r413, %r412, %r4, %r3;
	mul.wide.u32 	%rd64, %r413, 8;
	add.s64 	%rd16, %rd63, %rd64;
	@%p177 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs108, %rs109, %rs110, %rs111}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f1432, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1433, %rs109;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1434, %rs110;}

	// end inline asm
	add.f32 	%f1435, %f1432, 0f00000000;
	add.f32 	%f1436, %f1433, 0f00000000;
	add.f32 	%f1437, %f1434, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1437;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1436;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1435;}

	// end inline asm
	mov.u16 	%rs112, 0;
	st.global.v4.u16 	[%rd16], {%rs105, %rs106, %rs107, %rs112};
	bra.uni 	$L__BB0_157;

$L__BB0_5:
	ld.const.u64 	%rd24, [params+432];
	cvta.to.global.u64 	%rd25, %rd24;
	ld.const.u32 	%r38, [params+424];
	mad.lo.s32 	%r39, %r38, %r27, %r26;
	mul.wide.u32 	%rd26, %r39, 12;
	add.s64 	%rd27, %rd25, %rd26;
	ld.global.f32 	%f10, [%rd27];
	mul.f32 	%f308, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd27+4];
	mul.f32 	%f309, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd27+8];
	mul.f32 	%f310, %f12, 0f3456BF95;
	abs.f32 	%f311, %f1480;
	div.rn.f32 	%f312, %f308, %f311;
	abs.f32 	%f313, %f1481;
	div.rn.f32 	%f314, %f309, %f313;
	abs.f32 	%f315, %f1482;
	div.rn.f32 	%f316, %f310, %f315;
	abs.f32 	%f317, %f312;
	abs.f32 	%f318, %f314;
	abs.f32 	%f319, %f316;
	mov.f32 	%f320, 0f38D1B717;
	max.f32 	%f321, %f317, %f320;
	max.f32 	%f322, %f318, %f320;
	max.f32 	%f323, %f319, %f320;
	fma.rn.f32 	%f13, %f1480, %f321, %f10;
	fma.rn.f32 	%f14, %f1481, %f322, %f11;
	fma.rn.f32 	%f15, %f1482, %f323, %f12;
	ld.const.u32 	%r5, [params+600];
	setp.eq.s32 	%p17, %r5, 0;
	@%p17 bra 	$L__BB0_44;

	ld.const.u64 	%rd28, [params+608];
	cvta.to.global.u64 	%rd2, %rd28;
	mov.f32 	%f340, 0f40000000;
	cvt.rzi.f32.f32 	%f341, %f340;
	add.f32 	%f342, %f341, %f341;
	mov.f32 	%f343, 0f40800000;
	sub.f32 	%f344, %f343, %f342;
	abs.f32 	%f16, %f344;
	ld.const.u32 	%r6, [params+544];
	ld.const.u32 	%r427, [params+104];
	mul.f32 	%f17, %f13, 0f3456BF95;
	mul.f32 	%f18, %f14, 0f3456BF95;
	mul.f32 	%f19, %f15, 0f3456BF95;
	mov.f32 	%f339, 0f00000000;
	mov.u32 	%r423, 0;
	ld.const.u64 	%rd3, [params+96];
	abs.f32 	%f543, %f17;
	abs.f32 	%f544, %f18;
	max.f32 	%f545, %f543, %f544;
	abs.f32 	%f546, %f19;
	max.f32 	%f547, %f545, %f546;
	mov.f32 	%f1546, %f339;
	mov.f32 	%f1545, %f339;
	mov.f32 	%f1544, %f339;
	mov.f32 	%f1543, %f339;
	mov.f32 	%f1542, %f339;
	mov.f32 	%f1541, %f339;
	mov.f32 	%f1540, %f339;
	mov.f32 	%f1539, %f339;
	mov.f32 	%f1538, %f339;
	mov.f32 	%f1537, %f339;
	mov.f32 	%f1536, %f339;
	mov.f32 	%f1535, %f339;
	mov.f32 	%f1534, %f339;
	mov.f32 	%f1533, %f339;
	mov.f32 	%f1532, %f339;
	mov.f32 	%f1531, %f339;

$L__BB0_7:
	mul.wide.u32 	%rd29, %r423, 112;
	add.s64 	%rd5, %rd2, %rd29;
	ld.global.v4.f32 	{%f346, %f347, %f348, %f349}, [%rd5];
	ld.global.v4.f32 	{%f350, %f351, %f352, %f353}, [%rd5+16];
	ld.global.v4.f32 	{%f356, %f1507, %f1508, %f359}, [%rd5+32];
	ld.global.v4.f32 	{%f360, %f361, %f362, %f1505}, [%rd5+48];
	ld.global.v4.f32 	{%f364, %f365, %f366, %f367}, [%rd5+64];
	ld.global.v4.u32 	{%r41, %r42, %r43, %r44}, [%rd5+80];
	mov.b32 	%f55, %r43;
	mov.b32 	%f54, %r42;
	mov.b32 	%f53, %r41;
	ld.global.u64 	%rd6, [%rd5+96];
	sub.f32 	%f368, %f347, %f10;
	sub.f32 	%f369, %f348, %f11;
	sub.f32 	%f370, %f349, %f12;
	mul.f32 	%f371, %f369, %f369;
	fma.rn.f32 	%f372, %f368, %f368, %f371;
	fma.rn.f32 	%f373, %f370, %f370, %f372;
	sqrt.rn.f32 	%f374, %f373;
	rcp.rn.f32 	%f375, %f374;
	mul.f32 	%f57, %f368, %f375;
	mul.f32 	%f58, %f369, %f375;
	mul.f32 	%f59, %f370, %f375;
	mul.f32 	%f60, %f374, %f351;
	mul.f32 	%f61, %f374, %f353;
	abs.f32 	%f62, %f61;
	setp.lt.f32 	%p18, %f62, 0f00800000;
	mul.f32 	%f376, %f62, 0f4B800000;
	selp.f32 	%f377, %f376, %f62, %p18;
	selp.f32 	%f378, 0fC3170000, 0fC2FE0000, %p18;
	mov.b32 	%r48, %f377;
	and.b32  	%r49, %r48, 8388607;
	or.b32  	%r50, %r49, 1065353216;
	mov.b32 	%f379, %r50;
	shr.u32 	%r51, %r48, 23;
	cvt.rn.f32.u32 	%f380, %r51;
	add.f32 	%f381, %f378, %f380;
	setp.gt.f32 	%p19, %f379, 0f3FB504F3;
	mul.f32 	%f382, %f379, 0f3F000000;
	add.f32 	%f383, %f381, 0f3F800000;
	selp.f32 	%f384, %f383, %f381, %p19;
	selp.f32 	%f385, %f382, %f379, %p19;
	add.f32 	%f386, %f385, 0fBF800000;
	add.f32 	%f387, %f385, 0f3F800000;
	rcp.approx.ftz.f32 	%f388, %f387;
	add.f32 	%f389, %f386, %f386;
	mul.f32 	%f390, %f389, %f388;
	mul.f32 	%f391, %f390, %f390;
	mov.f32 	%f392, 0f3C4CAF63;
	mov.f32 	%f393, 0f3B18F0FE;
	fma.rn.f32 	%f394, %f393, %f391, %f392;
	mov.f32 	%f395, 0f3DAAAABD;
	fma.rn.f32 	%f396, %f394, %f391, %f395;
	mul.rn.f32 	%f397, %f396, %f391;
	mul.rn.f32 	%f398, %f397, %f390;
	sub.f32 	%f399, %f386, %f390;
	add.f32 	%f400, %f399, %f399;
	neg.f32 	%f401, %f390;
	fma.rn.f32 	%f402, %f401, %f386, %f400;
	mul.rn.f32 	%f403, %f388, %f402;
	add.f32 	%f404, %f398, %f390;
	sub.f32 	%f405, %f390, %f404;
	add.f32 	%f406, %f398, %f405;
	add.f32 	%f407, %f403, %f406;
	add.f32 	%f408, %f404, %f407;
	sub.f32 	%f409, %f404, %f408;
	add.f32 	%f410, %f407, %f409;
	mov.f32 	%f411, 0f3F317200;
	mul.rn.f32 	%f412, %f384, %f411;
	mov.f32 	%f413, 0f35BFBE8E;
	mul.rn.f32 	%f414, %f384, %f413;
	add.f32 	%f415, %f412, %f408;
	sub.f32 	%f416, %f412, %f415;
	add.f32 	%f417, %f408, %f416;
	add.f32 	%f418, %f410, %f417;
	add.f32 	%f419, %f414, %f418;
	add.f32 	%f420, %f415, %f419;
	sub.f32 	%f421, %f415, %f420;
	add.f32 	%f422, %f419, %f421;
	mul.rn.f32 	%f424, %f343, %f420;
	neg.f32 	%f425, %f424;
	fma.rn.f32 	%f426, %f343, %f420, %f425;
	fma.rn.f32 	%f427, %f343, %f422, %f426;
	fma.rn.f32 	%f429, %f339, %f420, %f427;
	add.rn.f32 	%f430, %f424, %f429;
	neg.f32 	%f431, %f430;
	add.rn.f32 	%f432, %f424, %f431;
	add.rn.f32 	%f433, %f432, %f429;
	mov.b32 	%r52, %f430;
	setp.eq.s32 	%p20, %r52, 1118925336;
	add.s32 	%r53, %r52, -1;
	mov.b32 	%f434, %r53;
	add.f32 	%f435, %f433, 0f37000000;
	selp.f32 	%f63, %f435, %f433, %p20;
	selp.f32 	%f436, %f434, %f430, %p20;
	mov.f32 	%f437, 0f3FB8AA3B;
	mul.rn.f32 	%f438, %f436, %f437;
	cvt.rzi.f32.f32 	%f439, %f438;
	abs.f32 	%f440, %f439;
	setp.gt.f32 	%p21, %f440, 0f42FC0000;
	mov.b32 	%r54, %f439;
	and.b32  	%r55, %r54, -2147483648;
	or.b32  	%r56, %r55, 1123811328;
	mov.b32 	%f441, %r56;
	selp.f32 	%f442, %f441, %f439, %p21;
	mov.f32 	%f443, 0fBF317218;
	fma.rn.f32 	%f444, %f442, %f443, %f436;
	mov.f32 	%f445, 0f3102E308;
	fma.rn.f32 	%f446, %f442, %f445, %f444;
	mul.f32 	%f447, %f446, 0f3FB8AA3B;
	add.f32 	%f448, %f442, 0f4B40007F;
	mov.b32 	%r57, %f448;
	shl.b32 	%r58, %r57, 23;
	mov.b32 	%f449, %r58;
	ex2.approx.ftz.f32 	%f450, %f447;
	mul.f32 	%f64, %f450, %f449;
	setp.eq.f32 	%p22, %f64, 0f7F800000;
	mov.f32 	%f1499, 0f7F800000;
	@%p22 bra 	$L__BB0_9;

	fma.rn.f32 	%f1499, %f64, %f63, %f64;

$L__BB0_9:
	setp.lt.f32 	%p23, %f61, 0f00000000;
	setp.eq.f32 	%p24, %f16, 0f3F800000;
	and.pred  	%p1, %p23, %p24;
	setp.eq.f32 	%p25, %f61, 0f00000000;
	@%p25 bra 	$L__BB0_13;
	bra.uni 	$L__BB0_10;

$L__BB0_13:
	add.f32 	%f455, %f61, %f61;
	selp.f32 	%f1501, %f455, 0f00000000, %p24;
	bra.uni 	$L__BB0_14;

$L__BB0_10:
	mov.b32 	%r59, %f1499;
	xor.b32  	%r60, %r59, -2147483648;
	mov.b32 	%f451, %r60;
	selp.f32 	%f1501, %f451, %f1499, %p1;
	setp.geu.f32 	%p26, %f61, 0f00000000;
	@%p26 bra 	$L__BB0_14;

	mov.f32 	%f452, 0f40800000;
	cvt.rzi.f32.f32 	%f453, %f452;
	setp.eq.f32 	%p27, %f453, 0f40800000;
	@%p27 bra 	$L__BB0_14;

	mov.f32 	%f1501, 0f7FFFFFFF;

$L__BB0_14:
	abs.f32 	%f1477, %f61;
	add.f32 	%f456, %f1477, 0f40800000;
	mov.b32 	%r61, %f456;
	setp.lt.s32 	%p29, %r61, 2139095040;
	@%p29 bra 	$L__BB0_19;

	abs.f32 	%f1478, %f61;
	setp.gtu.f32 	%p30, %f1478, 0f7F800000;
	@%p30 bra 	$L__BB0_18;
	bra.uni 	$L__BB0_16;

$L__BB0_18:
	add.f32 	%f1501, %f61, 0f40800000;
	bra.uni 	$L__BB0_19;

$L__BB0_16:
	abs.f32 	%f1479, %f61;
	setp.neu.f32 	%p31, %f1479, 0f7F800000;
	@%p31 bra 	$L__BB0_19;

	selp.f32 	%f1501, 0fFF800000, 0f7F800000, %p1;

$L__BB0_19:
	mov.f32 	%f457, 0f3F800000;
	sub.f32 	%f458, %f457, %f1501;
	setp.eq.f32 	%p32, %f61, 0f3F800000;
	selp.f32 	%f459, 0f00000000, %f458, %p32;
	cvt.sat.f32.f32 	%f460, %f459;
	fma.rn.f32 	%f461, %f60, %f60, %f352;
	div.rn.f32 	%f73, %f460, %f461;
	mul.f32 	%f462, %f1481, %f58;
	fma.rn.f32 	%f463, %f1480, %f57, %f462;
	fma.rn.f32 	%f74, %f1482, %f59, %f463;
	setp.eq.f32 	%p33, %f346, 0f3F800000;
	@%p33 bra 	$L__BB0_25;
	bra.uni 	$L__BB0_20;

$L__BB0_25:
	setp.eq.s64 	%p37, %rd6, 0;
	mov.f32 	%f1506, %f356;
	mov.f32 	%f1509, %f73;
	@%p37 bra 	$L__BB0_29;

	setp.geu.f32 	%p38, %f1505, 0f00000000;
	mov.f32 	%f1502, %f57;
	mov.f32 	%f1503, %f58;
	mov.f32 	%f1504, %f59;
	@%p38 bra 	$L__BB0_28;

	mul.f32 	%f488, %f54, %f369;
	fma.rn.f32 	%f489, %f53, %f368, %f488;
	fma.rn.f32 	%f491, %f55, %f370, %f489;
	rcp.rn.f32 	%f492, %f491;
	mul.f32 	%f1502, %f368, %f492;
	mul.f32 	%f1503, %f369, %f492;
	mul.f32 	%f1504, %f370, %f492;
	neg.f32 	%f1505, %f1505;

$L__BB0_28:
	mul.f32 	%f493, %f55, %f59;
	mul.f32 	%f494, %f54, %f58;
	neg.f32 	%f495, %f494;
	mul.f32 	%f496, %f53, %f57;
	sub.f32 	%f497, %f495, %f496;
	sub.f32 	%f498, %f497, %f493;
	setp.gt.f32 	%p39, %f498, 0f00000000;
	selp.f32 	%f499, 0f3F800000, 0f00000000, %p39;
	mov.f32 	%f500, 0f3F800000;
	mul.f32 	%f501, %f361, %f1503;
	mul.f32 	%f502, %f365, %f1503;
	fma.rn.f32 	%f503, %f360, %f1502, %f501;
	fma.rn.f32 	%f504, %f364, %f1502, %f502;
	fma.rn.f32 	%f505, %f362, %f1504, %f503;
	fma.rn.f32 	%f506, %f366, %f1504, %f504;
	fma.rn.f32 	%f507, %f1505, %f505, 0f3F000000;
	sub.f32 	%f508, %f500, %f507;
	fma.rn.f32 	%f509, %f1505, %f506, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f510, %f511, %f512, %f513}, [%rd6, {%f508, %f509}];
	mul.f32 	%f514, %f499, %f510;
	mul.f32 	%f515, %f499, %f511;
	mul.f32 	%f516, %f499, %f512;
	mul.f32 	%f1506, %f356, %f514;
	mul.f32 	%f1507, %f1507, %f515;
	mul.f32 	%f1508, %f1508, %f516;
	mov.f32 	%f1509, %f73;
	bra.uni 	$L__BB0_29;

$L__BB0_20:
	setp.eq.f32 	%p34, %f346, 0f40000000;
	@%p34 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_21;

$L__BB0_23:
	setp.eq.s64 	%p36, %rd6, 0;
	mov.f32 	%f1506, %f356;
	mov.f32 	%f1509, %f73;
	@%p36 bra 	$L__BB0_29;

	mul.f32 	%f473, %f361, %f58;
	mul.f32 	%f474, %f365, %f58;
	mul.f32 	%f475, %f54, %f58;
	fma.rn.f32 	%f476, %f360, %f57, %f473;
	fma.rn.f32 	%f477, %f364, %f57, %f474;
	fma.rn.f32 	%f478, %f53, %f57, %f475;
	fma.rn.f32 	%f479, %f362, %f59, %f476;
	fma.rn.f32 	%f480, %f366, %f59, %f477;
	fma.rn.f32 	%f481, %f55, %f59, %f478;
	tex.cube.v4.f32.f32 	{%f482, %f483, %f484, %f485}, [%rd6, {%f479, %f480, %f481, %f481}];
	mul.f32 	%f1506, %f356, %f482;
	mul.f32 	%f1507, %f1507, %f483;
	mul.f32 	%f1508, %f1508, %f484;
	mov.f32 	%f1509, %f73;
	bra.uni 	$L__BB0_29;

$L__BB0_21:
	setp.neu.f32 	%p35, %f346, 0f40800000;
	mov.f32 	%f1506, %f356;
	mov.f32 	%f1509, %f73;
	@%p35 bra 	$L__BB0_29;

	mul.f32 	%f464, %f53, %f57;
	mul.f32 	%f465, %f54, %f58;
	neg.f32 	%f466, %f465;
	sub.f32 	%f467, %f466, %f464;
	mul.f32 	%f468, %f55, %f59;
	sub.f32 	%f469, %f467, %f468;
	fma.rn.f32 	%f470, %f359, %f469, %f1505;
	cvt.sat.f32.f32 	%f471, %f470;
	mul.f32 	%f472, %f471, %f471;
	mul.f32 	%f1509, %f73, %f472;
	mov.f32 	%f1506, %f356;

$L__BB0_29:
	max.f32 	%f532, %f1506, %f1507;
	max.f32 	%f533, %f532, %f1508;
	mul.f32 	%f534, %f1509, %f533;
	setp.lt.f32 	%p41, %f534, 0f3727C5AC;
	mov.pred 	%p182, -1;
	mov.f32 	%f1510, 0f00000000;
	mov.f32 	%f1511, %f1510;
	mov.f32 	%f1512, %f1510;
	mov.f32 	%f1513, %f1510;
	mov.f32 	%f1514, %f1510;
	mov.f32 	%f1515, %f1510;
	mov.f32 	%f1516, %f1510;
	mov.f32 	%f1517, %f1510;
	mov.f32 	%f1518, %f1510;
	mov.f32 	%f1519, %f1510;
	mov.f32 	%f1520, %f1510;
	mov.f32 	%f1521, %f1510;
	mov.f32 	%f1522, %f1510;
	mov.f32 	%f1523, %f1510;
	mov.f32 	%f1524, %f1510;
	@%p41 bra 	$L__BB0_31;

	setp.eq.s32 	%p43, %r6, 0;
	selp.f32 	%f535, %f74, 0f3F800000, %p43;
	cvt.sat.f32.f32 	%f536, %f535;
	mul.f32 	%f537, %f1509, %f536;
	mul.f32 	%f1511, %f1506, %f537;
	mul.f32 	%f1510, %f1507, %f537;
	mul.f32 	%f1512, %f1508, %f537;
	mul.f32 	%f538, %f1509, 0f3E800000;
	mul.f32 	%f1513, %f1506, %f538;
	mul.f32 	%f1514, %f1507, %f538;
	mul.f32 	%f1515, %f1508, %f538;
	mul.f32 	%f1516, %f57, %f1513;
	mul.f32 	%f1517, %f57, %f1514;
	mul.f32 	%f1518, %f57, %f1515;
	mul.f32 	%f1519, %f58, %f1513;
	mul.f32 	%f1520, %f58, %f1514;
	mul.f32 	%f1521, %f58, %f1515;
	mul.f32 	%f1522, %f59, %f1513;
	mul.f32 	%f1523, %f59, %f1514;
	mul.f32 	%f1524, %f59, %f1515;
	mov.pred 	%p182, 0;

$L__BB0_31:
	@%p182 bra 	$L__BB0_43;

	setp.eq.s32 	%p44, %r44, 0;
	mov.u16 	%rs179, 0;
	mov.f32 	%f1530, 0f3F800000;
	@%p44 bra 	$L__BB0_40;

	abs.s32 	%r10, %r44;
	setp.lt.s32 	%p45, %r10, 1;
	mov.f32 	%f1526, 0f00000000;
	@%p45 bra 	$L__BB0_39;

	mov.f32 	%f548, 0f38D1B717;
	max.f32 	%f549, %f547, %f548;
	and.b32  	%r63, %r427, 32;
	setp.eq.s32 	%p46, %r63, 0;
	mov.u32 	%r426, 0;
	selp.f32 	%f550, 0f3F800000, 0f41200000, %p46;
	mul.f32 	%f137, %f550, %f549;
	and.b32  	%r11, %r10, 1;
	setp.eq.s32 	%p47, %r10, 1;
	mov.f32 	%f1526, 0f00000000;
	@%p47 bra 	$L__BB0_37;

	sub.s32 	%r425, %r10, %r11;

$L__BB0_36:
	cvt.rn.f32.s32 	%f570, %r426;
	mul.f32 	%f571, %f570, 0f3DD32618;
	cvt.rmi.f32.f32 	%f572, %f571;
	sub.f32 	%f573, %f571, %f572;
	mul.f32 	%f574, %f570, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f575, %f574;
	sub.f32 	%f576, %f574, %f575;
	mul.f32 	%f577, %f570, 0f3DC74539;
	cvt.rmi.f32.f32 	%f578, %f577;
	sub.f32 	%f579, %f577, %f578;
	add.f32 	%f580, %f576, 0f4199851F;
	add.f32 	%f581, %f579, 0f4199851F;
	add.f32 	%f582, %f573, 0f4199851F;
	mul.f32 	%f583, %f576, %f581;
	fma.rn.f32 	%f584, %f573, %f580, %f583;
	fma.rn.f32 	%f585, %f582, %f579, %f584;
	add.f32 	%f586, %f573, %f585;
	add.f32 	%f587, %f576, %f585;
	add.f32 	%f588, %f579, %f585;
	add.f32 	%f589, %f586, %f587;
	mul.f32 	%f590, %f588, %f589;
	cvt.rmi.f32.f32 	%f591, %f590;
	sub.f32 	%f592, %f590, %f591;
	add.f32 	%f593, %f586, %f588;
	mul.f32 	%f594, %f587, %f593;
	cvt.rmi.f32.f32 	%f595, %f594;
	sub.f32 	%f596, %f594, %f595;
	add.f32 	%f597, %f587, %f588;
	mul.f32 	%f598, %f586, %f597;
	cvt.rmi.f32.f32 	%f599, %f598;
	sub.f32 	%f600, %f598, %f599;
	fma.rn.f32 	%f601, %f592, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f602, %f596, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f603, %f600, 0f40000000, 0fBF800000;
	ld.global.f32 	%f604, [%rd5+16];
	ld.global.f32 	%f605, [%rd5+4];
	fma.rn.f32 	%f606, %f604, %f601, %f605;
	ld.global.f32 	%f607, [%rd5+8];
	fma.rn.f32 	%f608, %f604, %f602, %f607;
	ld.global.f32 	%f609, [%rd5+12];
	fma.rn.f32 	%f610, %f604, %f603, %f609;
	sub.f32 	%f611, %f606, %f10;
	sub.f32 	%f612, %f608, %f11;
	sub.f32 	%f613, %f610, %f12;
	mul.f32 	%f614, %f612, %f612;
	fma.rn.f32 	%f615, %f611, %f611, %f614;
	fma.rn.f32 	%f616, %f613, %f613, %f615;
	sqrt.rn.f32 	%f559, %f616;
	rcp.rn.f32 	%f617, %f559;
	mul.f32 	%f555, %f617, %f611;
	mul.f32 	%f556, %f617, %f612;
	mul.f32 	%f557, %f617, %f613;
	mov.f32 	%f569, 0f00000000;
	mov.u32 	%r172, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f555,%f556,%f557,%f137,%f559,%f569,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f618, %r65;
	add.f32 	%f619, %f1526, %f618;
	add.s32 	%r207, %r426, 1;
	cvt.rn.f32.s32 	%f620, %r207;
	mul.f32 	%f621, %f620, 0f3DD32618;
	cvt.rmi.f32.f32 	%f622, %f621;
	sub.f32 	%f623, %f621, %f622;
	mul.f32 	%f624, %f620, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f625, %f624;
	sub.f32 	%f626, %f624, %f625;
	mul.f32 	%f627, %f620, 0f3DC74539;
	cvt.rmi.f32.f32 	%f628, %f627;
	sub.f32 	%f629, %f627, %f628;
	add.f32 	%f630, %f626, 0f4199851F;
	add.f32 	%f631, %f629, 0f4199851F;
	add.f32 	%f632, %f623, 0f4199851F;
	mul.f32 	%f633, %f626, %f631;
	fma.rn.f32 	%f634, %f623, %f630, %f633;
	fma.rn.f32 	%f635, %f632, %f629, %f634;
	add.f32 	%f636, %f623, %f635;
	add.f32 	%f637, %f626, %f635;
	add.f32 	%f638, %f629, %f635;
	add.f32 	%f639, %f636, %f637;
	mul.f32 	%f640, %f638, %f639;
	cvt.rmi.f32.f32 	%f641, %f640;
	sub.f32 	%f642, %f640, %f641;
	add.f32 	%f643, %f636, %f638;
	mul.f32 	%f644, %f637, %f643;
	cvt.rmi.f32.f32 	%f645, %f644;
	sub.f32 	%f646, %f644, %f645;
	add.f32 	%f647, %f637, %f638;
	mul.f32 	%f648, %f636, %f647;
	cvt.rmi.f32.f32 	%f649, %f648;
	sub.f32 	%f650, %f648, %f649;
	fma.rn.f32 	%f651, %f642, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f652, %f646, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f653, %f650, 0f40000000, 0fBF800000;
	ld.global.f32 	%f654, [%rd5+16];
	ld.global.f32 	%f655, [%rd5+4];
	fma.rn.f32 	%f656, %f654, %f651, %f655;
	ld.global.f32 	%f657, [%rd5+8];
	fma.rn.f32 	%f658, %f654, %f652, %f657;
	ld.global.f32 	%f659, [%rd5+12];
	fma.rn.f32 	%f660, %f654, %f653, %f659;
	sub.f32 	%f661, %f656, %f10;
	sub.f32 	%f662, %f658, %f11;
	sub.f32 	%f663, %f660, %f12;
	mul.f32 	%f664, %f662, %f662;
	fma.rn.f32 	%f665, %f661, %f661, %f664;
	fma.rn.f32 	%f666, %f663, %f663, %f665;
	sqrt.rn.f32 	%f568, %f666;
	rcp.rn.f32 	%f667, %f568;
	mul.f32 	%f564, %f667, %f661;
	mul.f32 	%f565, %f667, %f662;
	mul.f32 	%f566, %f667, %f663;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f564,%f565,%f566,%f137,%f568,%f569,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f668, %r136;
	add.f32 	%f1526, %f619, %f668;
	add.s32 	%r426, %r426, 2;
	add.s32 	%r425, %r425, -2;
	setp.ne.s32 	%p48, %r425, 0;
	@%p48 bra 	$L__BB0_36;

$L__BB0_37:
	setp.eq.s32 	%p49, %r11, 0;
	@%p49 bra 	$L__BB0_39;

	cvt.rn.f32.s32 	%f678, %r426;
	mul.f32 	%f679, %f678, 0f3DD32618;
	cvt.rmi.f32.f32 	%f680, %f679;
	sub.f32 	%f681, %f679, %f680;
	mul.f32 	%f682, %f678, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f683, %f682;
	sub.f32 	%f684, %f682, %f683;
	mul.f32 	%f685, %f678, 0f3DC74539;
	cvt.rmi.f32.f32 	%f686, %f685;
	sub.f32 	%f687, %f685, %f686;
	add.f32 	%f688, %f684, 0f4199851F;
	add.f32 	%f689, %f687, 0f4199851F;
	add.f32 	%f690, %f681, 0f4199851F;
	mul.f32 	%f691, %f684, %f689;
	fma.rn.f32 	%f692, %f681, %f688, %f691;
	fma.rn.f32 	%f693, %f690, %f687, %f692;
	add.f32 	%f694, %f681, %f693;
	add.f32 	%f695, %f684, %f693;
	add.f32 	%f696, %f687, %f693;
	add.f32 	%f697, %f694, %f695;
	mul.f32 	%f698, %f696, %f697;
	cvt.rmi.f32.f32 	%f699, %f698;
	sub.f32 	%f700, %f698, %f699;
	add.f32 	%f701, %f694, %f696;
	mul.f32 	%f702, %f695, %f701;
	cvt.rmi.f32.f32 	%f703, %f702;
	sub.f32 	%f704, %f702, %f703;
	add.f32 	%f705, %f695, %f696;
	mul.f32 	%f706, %f694, %f705;
	cvt.rmi.f32.f32 	%f707, %f706;
	sub.f32 	%f708, %f706, %f707;
	fma.rn.f32 	%f709, %f700, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f710, %f704, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f711, %f708, 0f40000000, 0fBF800000;
	ld.global.f32 	%f712, [%rd5+16];
	ld.global.f32 	%f713, [%rd5+4];
	fma.rn.f32 	%f714, %f712, %f709, %f713;
	ld.global.f32 	%f715, [%rd5+8];
	fma.rn.f32 	%f716, %f712, %f710, %f715;
	ld.global.f32 	%f717, [%rd5+12];
	fma.rn.f32 	%f718, %f712, %f711, %f717;
	sub.f32 	%f719, %f714, %f10;
	sub.f32 	%f720, %f716, %f11;
	sub.f32 	%f721, %f718, %f12;
	mul.f32 	%f722, %f720, %f720;
	fma.rn.f32 	%f723, %f719, %f719, %f722;
	fma.rn.f32 	%f724, %f721, %f721, %f723;
	sqrt.rn.f32 	%f676, %f724;
	rcp.rn.f32 	%f725, %f676;
	mul.f32 	%f672, %f725, %f719;
	mul.f32 	%f673, %f725, %f720;
	mul.f32 	%f674, %f725, %f721;
	mov.f32 	%f677, 0f00000000;
	mov.u32 	%r244, 2;
	mov.u32 	%r246, 1;
	mov.u32 	%r247, 1065353216;
	mov.u32 	%r278, 0;
	// begin inline asm
	call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f672,%f673,%f674,%f137,%f676,%f677,%r246,%r278,%r246,%r244,%r246,%r246,%r247,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
	// end inline asm
	mov.b32 	%f726, %r208;
	add.f32 	%f1526, %f1526, %f726;

$L__BB0_39:
	cvt.rn.f32.s32 	%f727, %r10;
	div.rn.f32 	%f1530, %f1526, %f727;
	shr.u32 	%r279, %r44, 31;
	cvt.u16.u32 	%rs179, %r279;

$L__BB0_40:
	fma.rn.f32 	%f1531, %f1511, %f1530, %f1531;
	fma.rn.f32 	%f1532, %f1510, %f1530, %f1532;
	fma.rn.f32 	%f1533, %f1512, %f1530, %f1533;
	fma.rn.f32 	%f1534, %f1513, %f1530, %f1534;
	fma.rn.f32 	%f1535, %f1514, %f1530, %f1535;
	fma.rn.f32 	%f1536, %f1515, %f1530, %f1536;
	fma.rn.f32 	%f1537, %f1516, %f1530, %f1537;
	fma.rn.f32 	%f1538, %f1517, %f1530, %f1538;
	fma.rn.f32 	%f1539, %f1518, %f1530, %f1539;
	fma.rn.f32 	%f1540, %f1519, %f1530, %f1540;
	fma.rn.f32 	%f1541, %f1520, %f1530, %f1541;
	fma.rn.f32 	%f1542, %f1521, %f1530, %f1542;
	fma.rn.f32 	%f1543, %f1522, %f1530, %f1543;
	fma.rn.f32 	%f1544, %f1523, %f1530, %f1544;
	fma.rn.f32 	%f1545, %f1524, %f1530, %f1545;
	setp.eq.s16 	%p50, %rs179, 0;
	@%p50 bra 	$L__BB0_42;

	div.rn.f32 	%f728, %f1511, %f356;
	div.rn.f32 	%f729, %f728, %f73;
	cvt.sat.f32.f32 	%f730, %f729;
	mul.f32 	%f1530, %f1530, %f730;

$L__BB0_42:
	add.f32 	%f1546, %f1546, %f1530;

$L__BB0_43:
	cvt.u64.u32 	%rd77, %r423;
	cvt.u32.u64 	%r280, %rd77;
	add.s32 	%r423, %r280, 1;
	setp.lt.u32 	%p51, %r423, %r5;
	@%p51 bra 	$L__BB0_7;
	bra.uni 	$L__BB0_45;

$L__BB0_44:
	mov.f32 	%f1531, 0f00000000;
	ld.const.u32 	%r427, [params+104];
	mov.f32 	%f1532, %f1531;
	mov.f32 	%f1533, %f1531;
	mov.f32 	%f1534, %f1531;
	mov.f32 	%f1535, %f1531;
	mov.f32 	%f1536, %f1531;
	mov.f32 	%f1537, %f1531;
	mov.f32 	%f1538, %f1531;
	mov.f32 	%f1539, %f1531;
	mov.f32 	%f1540, %f1531;
	mov.f32 	%f1541, %f1531;
	mov.f32 	%f1542, %f1531;
	mov.f32 	%f1543, %f1531;
	mov.f32 	%f1544, %f1531;
	mov.f32 	%f1545, %f1531;
	mov.f32 	%f1546, %f1531;

$L__BB0_45:
	and.b32  	%r281, %r427, 8;
	setp.eq.s32 	%p52, %r281, 0;
	@%p52 bra 	$L__BB0_59;

	cvt.sat.f32.f32 	%f196, %f1546;
	ld.const.u64 	%rd33, [params+192];
	cvta.to.global.u64 	%rd7, %rd33;
	ld.const.u32 	%r282, [params+184];
	mad.lo.s32 	%r283, %r282, %r4, %r3;
	cvt.u64.u32 	%rd8, %r283;
	mov.f32 	%f748, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f749, %f748;
	add.f32 	%f750, %f749, %f749;
	mov.f32 	%f751, 0f3EE8BA2E;
	sub.f32 	%f752, %f751, %f750;
	abs.f32 	%f197, %f752;
	abs.f32 	%f198, %f196;
	setp.lt.f32 	%p53, %f198, 0f00800000;
	mul.f32 	%f753, %f198, 0f4B800000;
	selp.f32 	%f754, %f753, %f198, %p53;
	selp.f32 	%f755, 0fC3170000, 0fC2FE0000, %p53;
	mov.b32 	%r284, %f754;
	and.b32  	%r285, %r284, 8388607;
	or.b32  	%r286, %r285, 1065353216;
	mov.b32 	%f756, %r286;
	shr.u32 	%r287, %r284, 23;
	cvt.rn.f32.u32 	%f757, %r287;
	add.f32 	%f758, %f755, %f757;
	setp.gt.f32 	%p54, %f756, 0f3FB504F3;
	mul.f32 	%f759, %f756, 0f3F000000;
	add.f32 	%f760, %f758, 0f3F800000;
	selp.f32 	%f761, %f760, %f758, %p54;
	selp.f32 	%f762, %f759, %f756, %p54;
	add.f32 	%f763, %f762, 0fBF800000;
	add.f32 	%f764, %f762, 0f3F800000;
	rcp.approx.ftz.f32 	%f765, %f764;
	add.f32 	%f766, %f763, %f763;
	mul.f32 	%f767, %f766, %f765;
	mul.f32 	%f768, %f767, %f767;
	mov.f32 	%f769, 0f3C4CAF63;
	mov.f32 	%f770, 0f3B18F0FE;
	fma.rn.f32 	%f771, %f770, %f768, %f769;
	mov.f32 	%f772, 0f3DAAAABD;
	fma.rn.f32 	%f773, %f771, %f768, %f772;
	mul.rn.f32 	%f774, %f773, %f768;
	mul.rn.f32 	%f775, %f774, %f767;
	sub.f32 	%f776, %f763, %f767;
	add.f32 	%f777, %f776, %f776;
	neg.f32 	%f778, %f767;
	fma.rn.f32 	%f779, %f778, %f763, %f777;
	mul.rn.f32 	%f780, %f765, %f779;
	add.f32 	%f781, %f775, %f767;
	sub.f32 	%f782, %f767, %f781;
	add.f32 	%f783, %f775, %f782;
	add.f32 	%f784, %f780, %f783;
	add.f32 	%f785, %f781, %f784;
	sub.f32 	%f786, %f781, %f785;
	add.f32 	%f787, %f784, %f786;
	mov.f32 	%f788, 0f3F317200;
	mul.rn.f32 	%f789, %f761, %f788;
	mov.f32 	%f790, 0f35BFBE8E;
	mul.rn.f32 	%f791, %f761, %f790;
	add.f32 	%f792, %f789, %f785;
	sub.f32 	%f793, %f789, %f792;
	add.f32 	%f794, %f785, %f793;
	add.f32 	%f795, %f787, %f794;
	add.f32 	%f796, %f791, %f795;
	add.f32 	%f797, %f792, %f796;
	sub.f32 	%f798, %f792, %f797;
	add.f32 	%f799, %f796, %f798;
	mul.rn.f32 	%f800, %f751, %f797;
	neg.f32 	%f801, %f800;
	fma.rn.f32 	%f802, %f751, %f797, %f801;
	fma.rn.f32 	%f803, %f751, %f799, %f802;
	mov.f32 	%f804, 0f00000000;
	fma.rn.f32 	%f805, %f804, %f797, %f803;
	add.rn.f32 	%f806, %f800, %f805;
	neg.f32 	%f807, %f806;
	add.rn.f32 	%f808, %f800, %f807;
	add.rn.f32 	%f809, %f808, %f805;
	mov.b32 	%r288, %f806;
	setp.eq.s32 	%p55, %r288, 1118925336;
	add.s32 	%r289, %r288, -1;
	mov.b32 	%f810, %r289;
	add.f32 	%f811, %f809, 0f37000000;
	selp.f32 	%f199, %f811, %f809, %p55;
	selp.f32 	%f812, %f810, %f806, %p55;
	mov.f32 	%f813, 0f3FB8AA3B;
	mul.rn.f32 	%f814, %f812, %f813;
	cvt.rzi.f32.f32 	%f815, %f814;
	abs.f32 	%f816, %f815;
	setp.gt.f32 	%p56, %f816, 0f42FC0000;
	mov.b32 	%r290, %f815;
	and.b32  	%r291, %r290, -2147483648;
	or.b32  	%r292, %r291, 1123811328;
	mov.b32 	%f817, %r292;
	selp.f32 	%f818, %f817, %f815, %p56;
	mov.f32 	%f819, 0fBF317218;
	fma.rn.f32 	%f820, %f818, %f819, %f812;
	mov.f32 	%f821, 0f3102E308;
	fma.rn.f32 	%f822, %f818, %f821, %f820;
	mul.f32 	%f823, %f822, 0f3FB8AA3B;
	add.f32 	%f824, %f818, 0f4B40007F;
	mov.b32 	%r293, %f824;
	shl.b32 	%r294, %r293, 23;
	mov.b32 	%f825, %r294;
	ex2.approx.ftz.f32 	%f826, %f823;
	mul.f32 	%f200, %f826, %f825;
	setp.eq.f32 	%p57, %f200, 0f7F800000;
	mov.f32 	%f1563, 0f7F800000;
	@%p57 bra 	$L__BB0_48;

	fma.rn.f32 	%f1563, %f200, %f199, %f200;

$L__BB0_48:
	setp.lt.f32 	%p58, %f196, 0f00000000;
	setp.eq.f32 	%p59, %f197, 0f3F800000;
	and.pred  	%p3, %p58, %p59;
	setp.eq.f32 	%p60, %f196, 0f00000000;
	@%p60 bra 	$L__BB0_52;
	bra.uni 	$L__BB0_49;

$L__BB0_52:
	add.f32 	%f831, %f196, %f196;
	selp.f32 	%f1565, %f831, 0f00000000, %p59;
	bra.uni 	$L__BB0_53;

$L__BB0_156:
	mov.f32 	%f1440, 0f00000000;
	mov.u32 	%r429, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1440;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1440;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1440;}

	// end inline asm
	mov.u16 	%rs116, 0;
	st.global.v4.u16 	[%rd16], {%rs113, %rs114, %rs115, %rs116};

$L__BB0_157:
	ld.const.u64 	%rd65, [params+256];
	cvta.to.global.u64 	%rd66, %rd65;
	ld.const.u32 	%r415, [params+248];
	mad.lo.s32 	%r416, %r415, %r4, %r3;
	mul.wide.u32 	%rd67, %r416, 8;
	add.s64 	%rd17, %rd66, %rd67;
	setp.eq.s32 	%p178, %r429, 0;
	@%p178 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs123, %rs124, %rs125, %rs126}, [%rd17];
	// begin inline asm
	{  cvt.f32.f16 %f1441, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1442, %rs124;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1443, %rs125;}

	// end inline asm
	add.f32 	%f1444, %f1441, 0f00000000;
	add.f32 	%f1445, %f1442, 0f00000000;
	add.f32 	%f1446, %f1443, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1446;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1445;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1444;}

	// end inline asm
	mov.u16 	%rs127, 0;
	st.global.v4.u16 	[%rd17], {%rs120, %rs121, %rs122, %rs127};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1449, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1449;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1449;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1449;}

	// end inline asm
	mov.u16 	%rs131, 0;
	st.global.v4.u16 	[%rd17], {%rs128, %rs129, %rs130, %rs131};

$L__BB0_160:
	ld.const.u64 	%rd68, [params+272];
	cvta.to.global.u64 	%rd69, %rd68;
	ld.const.u32 	%r417, [params+264];
	mad.lo.s32 	%r418, %r417, %r4, %r3;
	mul.wide.u32 	%rd70, %r418, 8;
	add.s64 	%rd18, %rd69, %rd70;
	@%p178 bra 	$L__BB0_162;

	ld.global.v4.u16 	{%rs138, %rs139, %rs140, %rs141}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f1450, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1451, %rs139;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1452, %rs140;}

	// end inline asm
	add.f32 	%f1453, %f1450, 0f00000000;
	add.f32 	%f1454, %f1451, 0f00000000;
	add.f32 	%f1455, %f1452, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1455;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1454;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1453;}

	// end inline asm
	mov.u16 	%rs142, 0;
	st.global.v4.u16 	[%rd18], {%rs135, %rs136, %rs137, %rs142};
	bra.uni 	$L__BB0_163;

$L__BB0_162:
	mov.f32 	%f1458, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1458;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1458;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1458;}

	// end inline asm
	mov.u16 	%rs146, 0;
	st.global.v4.u16 	[%rd18], {%rs143, %rs144, %rs145, %rs146};

$L__BB0_163:
	ld.const.u64 	%rd71, [params+288];
	cvta.to.global.u64 	%rd72, %rd71;
	ld.const.u32 	%r419, [params+280];
	mad.lo.s32 	%r420, %r419, %r4, %r3;
	mul.wide.u32 	%rd73, %r420, 8;
	add.s64 	%rd19, %rd72, %rd73;
	@%p178 bra 	$L__BB0_165;

	ld.global.v4.u16 	{%rs153, %rs154, %rs155, %rs156}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1459, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1460, %rs154;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1461, %rs155;}

	// end inline asm
	add.f32 	%f1462, %f1459, 0f00000000;
	add.f32 	%f1463, %f1460, 0f00000000;
	add.f32 	%f1464, %f1461, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1464;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1463;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1462;}

	// end inline asm
	mov.u16 	%rs157, 0;
	st.global.v4.u16 	[%rd19], {%rs150, %rs151, %rs152, %rs157};
	bra.uni 	$L__BB0_166;

$L__BB0_165:
	mov.f32 	%f1467, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1467;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1467;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1467;}

	// end inline asm
	mov.u16 	%rs161, 0;
	st.global.v4.u16 	[%rd19], {%rs158, %rs159, %rs160, %rs161};

$L__BB0_166:
	ld.const.u64 	%rd74, [params+304];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r421, [params+296];
	mad.lo.s32 	%r422, %r421, %r4, %r3;
	mul.wide.u32 	%rd76, %r422, 8;
	add.s64 	%rd20, %rd75, %rd76;
	@%p178 bra 	$L__BB0_168;

	ld.global.v4.u16 	{%rs168, %rs169, %rs170, %rs171}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1468, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1469, %rs169;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1470, %rs170;}

	// end inline asm
	add.f32 	%f1471, %f1468, 0f00000000;
	add.f32 	%f1472, %f1469, 0f00000000;
	add.f32 	%f1473, %f1470, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1473;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1472;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1471;}

	// end inline asm
	mov.u16 	%rs172, 0;
	st.global.v4.u16 	[%rd20], {%rs165, %rs166, %rs167, %rs172};
	bra.uni 	$L__BB0_169;

$L__BB0_168:
	mov.f32 	%f1476, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1476;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1476;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1476;}

	// end inline asm
	mov.u16 	%rs176, 0;
	st.global.v4.u16 	[%rd20], {%rs173, %rs174, %rs175, %rs176};
	bra.uni 	$L__BB0_169;

$L__BB0_49:
	mov.b32 	%r295, %f1563;
	xor.b32  	%r296, %r295, -2147483648;
	mov.b32 	%f827, %r296;
	selp.f32 	%f1565, %f827, %f1563, %p3;
	setp.geu.f32 	%p61, %f196, 0f00000000;
	@%p61 bra 	$L__BB0_53;

	mov.f32 	%f828, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f829, %f828;
	setp.eq.f32 	%p62, %f829, 0f3EE8BA2E;
	@%p62 bra 	$L__BB0_53;

	mov.f32 	%f1565, 0f7FFFFFFF;

$L__BB0_53:
	add.f32 	%f832, %f198, 0f3EE8BA2E;
	mov.b32 	%r297, %f832;
	setp.lt.s32 	%p64, %r297, 2139095040;
	@%p64 bra 	$L__BB0_58;

	setp.gtu.f32 	%p65, %f198, 0f7F800000;
	@%p65 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_55;

$L__BB0_57:
	add.f32 	%f1565, %f196, 0f3EE8BA2E;
	bra.uni 	$L__BB0_58;

$L__BB0_55:
	setp.neu.f32 	%p66, %f198, 0f7F800000;
	@%p66 bra 	$L__BB0_58;

	selp.f32 	%f1565, 0fFF800000, 0f7F800000, %p3;

$L__BB0_58:
	mul.f32 	%f833, %f1565, 0f437F0000;
	setp.eq.f32 	%p67, %f196, 0f3F800000;
	selp.f32 	%f834, 0f437F0000, %f833, %p67;
	cvt.rzi.u32.f32 	%r298, %f834;
	shl.b64 	%rd34, %rd8, 1;
	add.s64 	%rd35, %rd7, %rd34;
	cvt.u16.u32 	%rs18, %r298;
	mov.u16 	%rs19, 255;
	st.global.v2.u8 	[%rd35], {%rs18, %rs19};

$L__BB0_59:
	and.b32  	%r299, %r427, 1;
	setp.eq.b32 	%p68, %r299, 1;
	mov.pred 	%p69, 0;
	xor.pred  	%p70, %p68, %p69;
	not.pred 	%p71, %p70;
	@%p71 bra 	$L__BB0_133;

	mov.f32 	%f836, 0f3E666666;
	cvt.rzi.f32.f32 	%f837, %f836;
	add.f32 	%f838, %f837, %f837;
	mov.f32 	%f839, 0f3EE66666;
	sub.f32 	%f840, %f839, %f838;
	abs.f32 	%f209, %f840;
	abs.f32 	%f210, %f1531;
	setp.lt.f32 	%p72, %f210, 0f00800000;
	mul.f32 	%f841, %f210, 0f4B800000;
	selp.f32 	%f842, %f841, %f210, %p72;
	selp.f32 	%f843, 0fC3170000, 0fC2FE0000, %p72;
	mov.b32 	%r300, %f842;
	and.b32  	%r301, %r300, 8388607;
	or.b32  	%r302, %r301, 1065353216;
	mov.b32 	%f844, %r302;
	shr.u32 	%r303, %r300, 23;
	cvt.rn.f32.u32 	%f845, %r303;
	add.f32 	%f846, %f843, %f845;
	setp.gt.f32 	%p73, %f844, 0f3FB504F3;
	mul.f32 	%f847, %f844, 0f3F000000;
	add.f32 	%f848, %f846, 0f3F800000;
	selp.f32 	%f849, %f848, %f846, %p73;
	selp.f32 	%f850, %f847, %f844, %p73;
	add.f32 	%f851, %f850, 0fBF800000;
	add.f32 	%f852, %f850, 0f3F800000;
	rcp.approx.ftz.f32 	%f853, %f852;
	add.f32 	%f854, %f851, %f851;
	mul.f32 	%f855, %f854, %f853;
	mul.f32 	%f856, %f855, %f855;
	mov.f32 	%f857, 0f3C4CAF63;
	mov.f32 	%f858, 0f3B18F0FE;
	fma.rn.f32 	%f859, %f858, %f856, %f857;
	mov.f32 	%f860, 0f3DAAAABD;
	fma.rn.f32 	%f861, %f859, %f856, %f860;
	mul.rn.f32 	%f862, %f861, %f856;
	mul.rn.f32 	%f863, %f862, %f855;
	sub.f32 	%f864, %f851, %f855;
	add.f32 	%f865, %f864, %f864;
	neg.f32 	%f866, %f855;
	fma.rn.f32 	%f867, %f866, %f851, %f865;
	mul.rn.f32 	%f868, %f853, %f867;
	add.f32 	%f869, %f863, %f855;
	sub.f32 	%f870, %f855, %f869;
	add.f32 	%f871, %f863, %f870;
	add.f32 	%f872, %f868, %f871;
	add.f32 	%f873, %f869, %f872;
	sub.f32 	%f874, %f869, %f873;
	add.f32 	%f875, %f872, %f874;
	mov.f32 	%f876, 0f3F317200;
	mul.rn.f32 	%f877, %f849, %f876;
	mov.f32 	%f878, 0f35BFBE8E;
	mul.rn.f32 	%f879, %f849, %f878;
	add.f32 	%f880, %f877, %f873;
	sub.f32 	%f881, %f877, %f880;
	add.f32 	%f882, %f873, %f881;
	add.f32 	%f883, %f875, %f882;
	add.f32 	%f884, %f879, %f883;
	add.f32 	%f885, %f880, %f884;
	sub.f32 	%f886, %f880, %f885;
	add.f32 	%f887, %f884, %f886;
	mul.rn.f32 	%f888, %f839, %f885;
	neg.f32 	%f889, %f888;
	fma.rn.f32 	%f890, %f839, %f885, %f889;
	fma.rn.f32 	%f891, %f839, %f887, %f890;
	mov.f32 	%f892, 0f00000000;
	fma.rn.f32 	%f893, %f892, %f885, %f891;
	add.rn.f32 	%f894, %f888, %f893;
	neg.f32 	%f895, %f894;
	add.rn.f32 	%f896, %f888, %f895;
	add.rn.f32 	%f897, %f896, %f893;
	mov.b32 	%r304, %f894;
	setp.eq.s32 	%p74, %r304, 1118925336;
	add.s32 	%r305, %r304, -1;
	mov.b32 	%f898, %r305;
	add.f32 	%f899, %f897, 0f37000000;
	selp.f32 	%f211, %f899, %f897, %p74;
	selp.f32 	%f900, %f898, %f894, %p74;
	mov.f32 	%f901, 0f3FB8AA3B;
	mul.rn.f32 	%f902, %f900, %f901;
	cvt.rzi.f32.f32 	%f903, %f902;
	abs.f32 	%f904, %f903;
	setp.gt.f32 	%p75, %f904, 0f42FC0000;
	mov.b32 	%r306, %f903;
	and.b32  	%r307, %r306, -2147483648;
	or.b32  	%r308, %r307, 1123811328;
	mov.b32 	%f905, %r308;
	selp.f32 	%f906, %f905, %f903, %p75;
	mov.f32 	%f907, 0fBF317218;
	fma.rn.f32 	%f908, %f906, %f907, %f900;
	mov.f32 	%f909, 0f3102E308;
	fma.rn.f32 	%f910, %f906, %f909, %f908;
	mul.f32 	%f911, %f910, 0f3FB8AA3B;
	add.f32 	%f912, %f906, 0f4B40007F;
	mov.b32 	%r309, %f912;
	shl.b32 	%r310, %r309, 23;
	mov.b32 	%f913, %r310;
	ex2.approx.ftz.f32 	%f914, %f911;
	mul.f32 	%f212, %f914, %f913;
	setp.eq.f32 	%p76, %f212, 0f7F800000;
	mov.f32 	%f1566, 0f7F800000;
	@%p76 bra 	$L__BB0_62;

	fma.rn.f32 	%f1566, %f212, %f211, %f212;

$L__BB0_62:
	setp.lt.f32 	%p77, %f1531, 0f00000000;
	setp.eq.f32 	%p78, %f209, 0f3F800000;
	and.pred  	%p4, %p77, %p78;
	setp.eq.f32 	%p79, %f1531, 0f00000000;
	@%p79 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_63;

$L__BB0_66:
	add.f32 	%f919, %f1531, %f1531;
	selp.f32 	%f1568, %f919, 0f00000000, %p78;
	bra.uni 	$L__BB0_67;

$L__BB0_63:
	mov.b32 	%r311, %f1566;
	xor.b32  	%r312, %r311, -2147483648;
	mov.b32 	%f915, %r312;
	selp.f32 	%f1568, %f915, %f1566, %p4;
	setp.geu.f32 	%p80, %f1531, 0f00000000;
	@%p80 bra 	$L__BB0_67;

	mov.f32 	%f916, 0f3EE66666;
	cvt.rzi.f32.f32 	%f917, %f916;
	setp.eq.f32 	%p81, %f917, 0f3EE66666;
	@%p81 bra 	$L__BB0_67;

	mov.f32 	%f1568, 0f7FFFFFFF;

$L__BB0_67:
	add.f32 	%f920, %f210, 0f3EE66666;
	mov.b32 	%r313, %f920;
	setp.lt.s32 	%p83, %r313, 2139095040;
	@%p83 bra 	$L__BB0_72;

	setp.gtu.f32 	%p84, %f210, 0f7F800000;
	@%p84 bra 	$L__BB0_71;
	bra.uni 	$L__BB0_69;

$L__BB0_71:
	add.f32 	%f1568, %f1531, 0f3EE66666;
	bra.uni 	$L__BB0_72;

$L__BB0_69:
	setp.neu.f32 	%p85, %f210, 0f7F800000;
	@%p85 bra 	$L__BB0_72;

	selp.f32 	%f1568, 0fFF800000, 0f7F800000, %p4;

$L__BB0_72:
	setp.eq.f32 	%p86, %f1531, 0f3F800000;
	selp.f32 	%f221, 0f3F800000, %f1568, %p86;
	abs.f32 	%f222, %f1532;
	setp.lt.f32 	%p87, %f222, 0f00800000;
	mul.f32 	%f922, %f222, 0f4B800000;
	selp.f32 	%f923, %f922, %f222, %p87;
	selp.f32 	%f924, 0fC3170000, 0fC2FE0000, %p87;
	mov.b32 	%r314, %f923;
	and.b32  	%r315, %r314, 8388607;
	or.b32  	%r316, %r315, 1065353216;
	mov.b32 	%f925, %r316;
	shr.u32 	%r317, %r314, 23;
	cvt.rn.f32.u32 	%f926, %r317;
	add.f32 	%f927, %f924, %f926;
	setp.gt.f32 	%p88, %f925, 0f3FB504F3;
	mul.f32 	%f928, %f925, 0f3F000000;
	add.f32 	%f929, %f927, 0f3F800000;
	selp.f32 	%f930, %f929, %f927, %p88;
	selp.f32 	%f931, %f928, %f925, %p88;
	add.f32 	%f932, %f931, 0fBF800000;
	add.f32 	%f933, %f931, 0f3F800000;
	rcp.approx.ftz.f32 	%f934, %f933;
	add.f32 	%f935, %f932, %f932;
	mul.f32 	%f936, %f935, %f934;
	mul.f32 	%f937, %f936, %f936;
	mov.f32 	%f938, 0f3C4CAF63;
	mov.f32 	%f939, 0f3B18F0FE;
	fma.rn.f32 	%f940, %f939, %f937, %f938;
	mov.f32 	%f941, 0f3DAAAABD;
	fma.rn.f32 	%f942, %f940, %f937, %f941;
	mul.rn.f32 	%f943, %f942, %f937;
	mul.rn.f32 	%f944, %f943, %f936;
	sub.f32 	%f945, %f932, %f936;
	add.f32 	%f946, %f945, %f945;
	neg.f32 	%f947, %f936;
	fma.rn.f32 	%f948, %f947, %f932, %f946;
	mul.rn.f32 	%f949, %f934, %f948;
	add.f32 	%f950, %f944, %f936;
	sub.f32 	%f951, %f936, %f950;
	add.f32 	%f952, %f944, %f951;
	add.f32 	%f953, %f949, %f952;
	add.f32 	%f954, %f950, %f953;
	sub.f32 	%f955, %f950, %f954;
	add.f32 	%f956, %f953, %f955;
	mov.f32 	%f957, 0f3F317200;
	mul.rn.f32 	%f958, %f930, %f957;
	mov.f32 	%f959, 0f35BFBE8E;
	mul.rn.f32 	%f960, %f930, %f959;
	add.f32 	%f961, %f958, %f954;
	sub.f32 	%f962, %f958, %f961;
	add.f32 	%f963, %f954, %f962;
	add.f32 	%f964, %f956, %f963;
	add.f32 	%f965, %f960, %f964;
	add.f32 	%f966, %f961, %f965;
	sub.f32 	%f967, %f961, %f966;
	add.f32 	%f968, %f965, %f967;
	mov.f32 	%f969, 0f3EE66666;
	mul.rn.f32 	%f970, %f969, %f966;
	neg.f32 	%f971, %f970;
	fma.rn.f32 	%f972, %f969, %f966, %f971;
	fma.rn.f32 	%f973, %f969, %f968, %f972;
	mov.f32 	%f974, 0f00000000;
	fma.rn.f32 	%f975, %f974, %f966, %f973;
	add.rn.f32 	%f976, %f970, %f975;
	neg.f32 	%f977, %f976;
	add.rn.f32 	%f978, %f970, %f977;
	add.rn.f32 	%f979, %f978, %f975;
	mov.b32 	%r318, %f976;
	setp.eq.s32 	%p89, %r318, 1118925336;
	add.s32 	%r319, %r318, -1;
	mov.b32 	%f980, %r319;
	add.f32 	%f981, %f979, 0f37000000;
	selp.f32 	%f223, %f981, %f979, %p89;
	selp.f32 	%f982, %f980, %f976, %p89;
	mov.f32 	%f983, 0f3FB8AA3B;
	mul.rn.f32 	%f984, %f982, %f983;
	cvt.rzi.f32.f32 	%f985, %f984;
	abs.f32 	%f986, %f985;
	setp.gt.f32 	%p90, %f986, 0f42FC0000;
	mov.b32 	%r320, %f985;
	and.b32  	%r321, %r320, -2147483648;
	or.b32  	%r322, %r321, 1123811328;
	mov.b32 	%f987, %r322;
	selp.f32 	%f988, %f987, %f985, %p90;
	mov.f32 	%f989, 0fBF317218;
	fma.rn.f32 	%f990, %f988, %f989, %f982;
	mov.f32 	%f991, 0f3102E308;
	fma.rn.f32 	%f992, %f988, %f991, %f990;
	mul.f32 	%f993, %f992, 0f3FB8AA3B;
	add.f32 	%f994, %f988, 0f4B40007F;
	mov.b32 	%r323, %f994;
	shl.b32 	%r324, %r323, 23;
	mov.b32 	%f995, %r324;
	ex2.approx.ftz.f32 	%f996, %f993;
	mul.f32 	%f224, %f996, %f995;
	setp.eq.f32 	%p91, %f224, 0f7F800000;
	mov.f32 	%f1569, 0f7F800000;
	@%p91 bra 	$L__BB0_74;

	fma.rn.f32 	%f1569, %f224, %f223, %f224;

$L__BB0_74:
	setp.lt.f32 	%p92, %f1532, 0f00000000;
	and.pred  	%p5, %p92, %p78;
	setp.eq.f32 	%p94, %f1532, 0f00000000;
	@%p94 bra 	$L__BB0_78;
	bra.uni 	$L__BB0_75;

$L__BB0_78:
	add.f32 	%f1001, %f1532, %f1532;
	selp.f32 	%f1571, %f1001, 0f00000000, %p78;
	bra.uni 	$L__BB0_79;

$L__BB0_75:
	mov.b32 	%r325, %f1569;
	xor.b32  	%r326, %r325, -2147483648;
	mov.b32 	%f997, %r326;
	selp.f32 	%f1571, %f997, %f1569, %p5;
	setp.geu.f32 	%p95, %f1532, 0f00000000;
	@%p95 bra 	$L__BB0_79;

	mov.f32 	%f998, 0f3EE66666;
	cvt.rzi.f32.f32 	%f999, %f998;
	setp.eq.f32 	%p96, %f999, 0f3EE66666;
	@%p96 bra 	$L__BB0_79;

	mov.f32 	%f1571, 0f7FFFFFFF;

$L__BB0_79:
	add.f32 	%f1002, %f222, 0f3EE66666;
	mov.b32 	%r327, %f1002;
	setp.lt.s32 	%p98, %r327, 2139095040;
	@%p98 bra 	$L__BB0_84;

	setp.gtu.f32 	%p99, %f222, 0f7F800000;
	@%p99 bra 	$L__BB0_83;
	bra.uni 	$L__BB0_81;

$L__BB0_83:
	add.f32 	%f1571, %f1532, 0f3EE66666;
	bra.uni 	$L__BB0_84;

$L__BB0_81:
	setp.neu.f32 	%p100, %f222, 0f7F800000;
	@%p100 bra 	$L__BB0_84;

	selp.f32 	%f1571, 0fFF800000, 0f7F800000, %p5;

$L__BB0_84:
	setp.eq.f32 	%p101, %f1532, 0f3F800000;
	selp.f32 	%f233, 0f3F800000, %f1571, %p101;
	abs.f32 	%f234, %f1533;
	setp.lt.f32 	%p102, %f234, 0f00800000;
	mul.f32 	%f1004, %f234, 0f4B800000;
	selp.f32 	%f1005, %f1004, %f234, %p102;
	selp.f32 	%f1006, 0fC3170000, 0fC2FE0000, %p102;
	mov.b32 	%r328, %f1005;
	and.b32  	%r329, %r328, 8388607;
	or.b32  	%r330, %r329, 1065353216;
	mov.b32 	%f1007, %r330;
	shr.u32 	%r331, %r328, 23;
	cvt.rn.f32.u32 	%f1008, %r331;
	add.f32 	%f1009, %f1006, %f1008;
	setp.gt.f32 	%p103, %f1007, 0f3FB504F3;
	mul.f32 	%f1010, %f1007, 0f3F000000;
	add.f32 	%f1011, %f1009, 0f3F800000;
	selp.f32 	%f1012, %f1011, %f1009, %p103;
	selp.f32 	%f1013, %f1010, %f1007, %p103;
	add.f32 	%f1014, %f1013, 0fBF800000;
	add.f32 	%f1015, %f1013, 0f3F800000;
	rcp.approx.ftz.f32 	%f1016, %f1015;
	add.f32 	%f1017, %f1014, %f1014;
	mul.f32 	%f1018, %f1017, %f1016;
	mul.f32 	%f1019, %f1018, %f1018;
	mov.f32 	%f1020, 0f3C4CAF63;
	mov.f32 	%f1021, 0f3B18F0FE;
	fma.rn.f32 	%f1022, %f1021, %f1019, %f1020;
	mov.f32 	%f1023, 0f3DAAAABD;
	fma.rn.f32 	%f1024, %f1022, %f1019, %f1023;
	mul.rn.f32 	%f1025, %f1024, %f1019;
	mul.rn.f32 	%f1026, %f1025, %f1018;
	sub.f32 	%f1027, %f1014, %f1018;
	add.f32 	%f1028, %f1027, %f1027;
	neg.f32 	%f1029, %f1018;
	fma.rn.f32 	%f1030, %f1029, %f1014, %f1028;
	mul.rn.f32 	%f1031, %f1016, %f1030;
	add.f32 	%f1032, %f1026, %f1018;
	sub.f32 	%f1033, %f1018, %f1032;
	add.f32 	%f1034, %f1026, %f1033;
	add.f32 	%f1035, %f1031, %f1034;
	add.f32 	%f1036, %f1032, %f1035;
	sub.f32 	%f1037, %f1032, %f1036;
	add.f32 	%f1038, %f1035, %f1037;
	mov.f32 	%f1039, 0f3F317200;
	mul.rn.f32 	%f1040, %f1012, %f1039;
	mov.f32 	%f1041, 0f35BFBE8E;
	mul.rn.f32 	%f1042, %f1012, %f1041;
	add.f32 	%f1043, %f1040, %f1036;
	sub.f32 	%f1044, %f1040, %f1043;
	add.f32 	%f1045, %f1036, %f1044;
	add.f32 	%f1046, %f1038, %f1045;
	add.f32 	%f1047, %f1042, %f1046;
	add.f32 	%f1048, %f1043, %f1047;
	sub.f32 	%f1049, %f1043, %f1048;
	add.f32 	%f1050, %f1047, %f1049;
	mov.f32 	%f1051, 0f3EE66666;
	mul.rn.f32 	%f1052, %f1051, %f1048;
	neg.f32 	%f1053, %f1052;
	fma.rn.f32 	%f1054, %f1051, %f1048, %f1053;
	fma.rn.f32 	%f1055, %f1051, %f1050, %f1054;
	mov.f32 	%f1056, 0f00000000;
	fma.rn.f32 	%f1057, %f1056, %f1048, %f1055;
	add.rn.f32 	%f1058, %f1052, %f1057;
	neg.f32 	%f1059, %f1058;
	add.rn.f32 	%f1060, %f1052, %f1059;
	add.rn.f32 	%f1061, %f1060, %f1057;
	mov.b32 	%r332, %f1058;
	setp.eq.s32 	%p104, %r332, 1118925336;
	add.s32 	%r333, %r332, -1;
	mov.b32 	%f1062, %r333;
	add.f32 	%f1063, %f1061, 0f37000000;
	selp.f32 	%f235, %f1063, %f1061, %p104;
	selp.f32 	%f1064, %f1062, %f1058, %p104;
	mov.f32 	%f1065, 0f3FB8AA3B;
	mul.rn.f32 	%f1066, %f1064, %f1065;
	cvt.rzi.f32.f32 	%f1067, %f1066;
	abs.f32 	%f1068, %f1067;
	setp.gt.f32 	%p105, %f1068, 0f42FC0000;
	mov.b32 	%r334, %f1067;
	and.b32  	%r335, %r334, -2147483648;
	or.b32  	%r336, %r335, 1123811328;
	mov.b32 	%f1069, %r336;
	selp.f32 	%f1070, %f1069, %f1067, %p105;
	mov.f32 	%f1071, 0fBF317218;
	fma.rn.f32 	%f1072, %f1070, %f1071, %f1064;
	mov.f32 	%f1073, 0f3102E308;
	fma.rn.f32 	%f1074, %f1070, %f1073, %f1072;
	mul.f32 	%f1075, %f1074, 0f3FB8AA3B;
	add.f32 	%f1076, %f1070, 0f4B40007F;
	mov.b32 	%r337, %f1076;
	shl.b32 	%r338, %r337, 23;
	mov.b32 	%f1077, %r338;
	ex2.approx.ftz.f32 	%f1078, %f1075;
	mul.f32 	%f236, %f1078, %f1077;
	setp.eq.f32 	%p106, %f236, 0f7F800000;
	mov.f32 	%f1572, 0f7F800000;
	@%p106 bra 	$L__BB0_86;

	fma.rn.f32 	%f1572, %f236, %f235, %f236;

$L__BB0_86:
	setp.lt.f32 	%p107, %f1533, 0f00000000;
	and.pred  	%p6, %p107, %p78;
	setp.eq.f32 	%p109, %f1533, 0f00000000;
	@%p109 bra 	$L__BB0_90;
	bra.uni 	$L__BB0_87;

$L__BB0_90:
	add.f32 	%f1083, %f1533, %f1533;
	selp.f32 	%f1574, %f1083, 0f00000000, %p78;
	bra.uni 	$L__BB0_91;

$L__BB0_87:
	mov.b32 	%r339, %f1572;
	xor.b32  	%r340, %r339, -2147483648;
	mov.b32 	%f1079, %r340;
	selp.f32 	%f1574, %f1079, %f1572, %p6;
	setp.geu.f32 	%p110, %f1533, 0f00000000;
	@%p110 bra 	$L__BB0_91;

	mov.f32 	%f1080, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1081, %f1080;
	setp.eq.f32 	%p111, %f1081, 0f3EE66666;
	@%p111 bra 	$L__BB0_91;

	mov.f32 	%f1574, 0f7FFFFFFF;

$L__BB0_91:
	add.f32 	%f1084, %f234, 0f3EE66666;
	mov.b32 	%r341, %f1084;
	setp.lt.s32 	%p113, %r341, 2139095040;
	@%p113 bra 	$L__BB0_96;

	setp.gtu.f32 	%p114, %f234, 0f7F800000;
	@%p114 bra 	$L__BB0_95;
	bra.uni 	$L__BB0_93;

$L__BB0_95:
	add.f32 	%f1574, %f1533, 0f3EE66666;
	bra.uni 	$L__BB0_96;

$L__BB0_93:
	setp.neu.f32 	%p115, %f234, 0f7F800000;
	@%p115 bra 	$L__BB0_96;

	selp.f32 	%f1574, 0fFF800000, 0f7F800000, %p6;

$L__BB0_96:
	setp.eq.f32 	%p116, %f1533, 0f3F800000;
	mov.f32 	%f1086, 0f3F800000;
	selp.f32 	%f1087, 0f3F800000, %f1574, %p116;
	ld.const.u64 	%rd36, [params+144];
	cvta.to.global.u64 	%rd9, %rd36;
	ld.const.u32 	%r342, [params+136];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	cvt.u64.u32 	%rd10, %r343;
	min.f32 	%f1088, %f221, %f1086;
	mov.f32 	%f1089, 0f00000000;
	max.f32 	%f245, %f1089, %f1088;
	min.f32 	%f1090, %f233, %f1086;
	max.f32 	%f246, %f1089, %f1090;
	min.f32 	%f1091, %f1087, %f1086;
	max.f32 	%f247, %f1089, %f1091;
	mov.f32 	%f1092, 0f3E555555;
	cvt.rzi.f32.f32 	%f1093, %f1092;
	add.f32 	%f1094, %f1093, %f1093;
	mov.f32 	%f1095, 0f3ED55555;
	sub.f32 	%f1096, %f1095, %f1094;
	abs.f32 	%f248, %f1096;
	abs.f32 	%f249, %f245;
	setp.lt.f32 	%p117, %f249, 0f00800000;
	mul.f32 	%f1097, %f249, 0f4B800000;
	selp.f32 	%f1098, %f1097, %f249, %p117;
	selp.f32 	%f1099, 0fC3170000, 0fC2FE0000, %p117;
	mov.b32 	%r344, %f1098;
	and.b32  	%r345, %r344, 8388607;
	or.b32  	%r346, %r345, 1065353216;
	mov.b32 	%f1100, %r346;
	shr.u32 	%r347, %r344, 23;
	cvt.rn.f32.u32 	%f1101, %r347;
	add.f32 	%f1102, %f1099, %f1101;
	setp.gt.f32 	%p118, %f1100, 0f3FB504F3;
	mul.f32 	%f1103, %f1100, 0f3F000000;
	add.f32 	%f1104, %f1102, 0f3F800000;
	selp.f32 	%f1105, %f1104, %f1102, %p118;
	selp.f32 	%f1106, %f1103, %f1100, %p118;
	add.f32 	%f1107, %f1106, 0fBF800000;
	add.f32 	%f1108, %f1106, 0f3F800000;
	rcp.approx.ftz.f32 	%f1109, %f1108;
	add.f32 	%f1110, %f1107, %f1107;
	mul.f32 	%f1111, %f1110, %f1109;
	mul.f32 	%f1112, %f1111, %f1111;
	mov.f32 	%f1113, 0f3C4CAF63;
	mov.f32 	%f1114, 0f3B18F0FE;
	fma.rn.f32 	%f1115, %f1114, %f1112, %f1113;
	mov.f32 	%f1116, 0f3DAAAABD;
	fma.rn.f32 	%f1117, %f1115, %f1112, %f1116;
	mul.rn.f32 	%f1118, %f1117, %f1112;
	mul.rn.f32 	%f1119, %f1118, %f1111;
	sub.f32 	%f1120, %f1107, %f1111;
	add.f32 	%f1121, %f1120, %f1120;
	neg.f32 	%f1122, %f1111;
	fma.rn.f32 	%f1123, %f1122, %f1107, %f1121;
	mul.rn.f32 	%f1124, %f1109, %f1123;
	add.f32 	%f1125, %f1119, %f1111;
	sub.f32 	%f1126, %f1111, %f1125;
	add.f32 	%f1127, %f1119, %f1126;
	add.f32 	%f1128, %f1124, %f1127;
	add.f32 	%f1129, %f1125, %f1128;
	sub.f32 	%f1130, %f1125, %f1129;
	add.f32 	%f1131, %f1128, %f1130;
	mov.f32 	%f1132, 0f3F317200;
	mul.rn.f32 	%f1133, %f1105, %f1132;
	mov.f32 	%f1134, 0f35BFBE8E;
	mul.rn.f32 	%f1135, %f1105, %f1134;
	add.f32 	%f1136, %f1133, %f1129;
	sub.f32 	%f1137, %f1133, %f1136;
	add.f32 	%f1138, %f1129, %f1137;
	add.f32 	%f1139, %f1131, %f1138;
	add.f32 	%f1140, %f1135, %f1139;
	add.f32 	%f1141, %f1136, %f1140;
	sub.f32 	%f1142, %f1136, %f1141;
	add.f32 	%f1143, %f1140, %f1142;
	mul.rn.f32 	%f1144, %f1095, %f1141;
	neg.f32 	%f1145, %f1144;
	fma.rn.f32 	%f1146, %f1095, %f1141, %f1145;
	fma.rn.f32 	%f1147, %f1095, %f1143, %f1146;
	fma.rn.f32 	%f1148, %f1089, %f1141, %f1147;
	add.rn.f32 	%f1149, %f1144, %f1148;
	neg.f32 	%f1150, %f1149;
	add.rn.f32 	%f1151, %f1144, %f1150;
	add.rn.f32 	%f1152, %f1151, %f1148;
	mov.b32 	%r348, %f1149;
	setp.eq.s32 	%p119, %r348, 1118925336;
	add.s32 	%r349, %r348, -1;
	mov.b32 	%f1153, %r349;
	add.f32 	%f1154, %f1152, 0f37000000;
	selp.f32 	%f250, %f1154, %f1152, %p119;
	selp.f32 	%f1155, %f1153, %f1149, %p119;
	mov.f32 	%f1156, 0f3FB8AA3B;
	mul.rn.f32 	%f1157, %f1155, %f1156;
	cvt.rzi.f32.f32 	%f1158, %f1157;
	abs.f32 	%f1159, %f1158;
	setp.gt.f32 	%p120, %f1159, 0f42FC0000;
	mov.b32 	%r350, %f1158;
	and.b32  	%r351, %r350, -2147483648;
	or.b32  	%r352, %r351, 1123811328;
	mov.b32 	%f1160, %r352;
	selp.f32 	%f1161, %f1160, %f1158, %p120;
	mov.f32 	%f1162, 0fBF317218;
	fma.rn.f32 	%f1163, %f1161, %f1162, %f1155;
	mov.f32 	%f1164, 0f3102E308;
	fma.rn.f32 	%f1165, %f1161, %f1164, %f1163;
	mul.f32 	%f1166, %f1165, 0f3FB8AA3B;
	add.f32 	%f1167, %f1161, 0f4B40007F;
	mov.b32 	%r353, %f1167;
	shl.b32 	%r354, %r353, 23;
	mov.b32 	%f1168, %r354;
	ex2.approx.ftz.f32 	%f1169, %f1166;
	mul.f32 	%f251, %f1169, %f1168;
	setp.eq.f32 	%p121, %f251, 0f7F800000;
	mov.f32 	%f1575, 0f7F800000;
	@%p121 bra 	$L__BB0_98;

	fma.rn.f32 	%f1575, %f251, %f250, %f251;

$L__BB0_98:
	setp.lt.f32 	%p122, %f245, 0f00000000;
	setp.eq.f32 	%p123, %f248, 0f3F800000;
	and.pred  	%p7, %p122, %p123;
	setp.eq.f32 	%p124, %f245, 0f00000000;
	@%p124 bra 	$L__BB0_102;
	bra.uni 	$L__BB0_99;

$L__BB0_102:
	add.f32 	%f1174, %f245, %f245;
	selp.f32 	%f1577, %f1174, 0f00000000, %p123;
	bra.uni 	$L__BB0_103;

$L__BB0_99:
	mov.b32 	%r355, %f1575;
	xor.b32  	%r356, %r355, -2147483648;
	mov.b32 	%f1170, %r356;
	selp.f32 	%f1577, %f1170, %f1575, %p7;
	setp.geu.f32 	%p125, %f245, 0f00000000;
	@%p125 bra 	$L__BB0_103;

	mov.f32 	%f1171, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1172, %f1171;
	setp.eq.f32 	%p126, %f1172, 0f3ED55555;
	@%p126 bra 	$L__BB0_103;

	mov.f32 	%f1577, 0f7FFFFFFF;

$L__BB0_103:
	add.f32 	%f1175, %f249, 0f3ED55555;
	mov.b32 	%r357, %f1175;
	setp.lt.s32 	%p128, %r357, 2139095040;
	@%p128 bra 	$L__BB0_108;

	setp.gtu.f32 	%p129, %f249, 0f7F800000;
	@%p129 bra 	$L__BB0_107;
	bra.uni 	$L__BB0_105;

$L__BB0_107:
	add.f32 	%f1577, %f245, 0f3ED55555;
	bra.uni 	$L__BB0_108;

$L__BB0_105:
	setp.neu.f32 	%p130, %f249, 0f7F800000;
	@%p130 bra 	$L__BB0_108;

	selp.f32 	%f1577, 0fFF800000, 0f7F800000, %p7;

$L__BB0_108:
	abs.f32 	%f260, %f246;
	setp.lt.f32 	%p131, %f260, 0f00800000;
	mul.f32 	%f1177, %f260, 0f4B800000;
	selp.f32 	%f1178, %f1177, %f260, %p131;
	selp.f32 	%f1179, 0fC3170000, 0fC2FE0000, %p131;
	mov.b32 	%r358, %f1178;
	and.b32  	%r359, %r358, 8388607;
	or.b32  	%r360, %r359, 1065353216;
	mov.b32 	%f1180, %r360;
	shr.u32 	%r361, %r358, 23;
	cvt.rn.f32.u32 	%f1181, %r361;
	add.f32 	%f1182, %f1179, %f1181;
	setp.gt.f32 	%p132, %f1180, 0f3FB504F3;
	mul.f32 	%f1183, %f1180, 0f3F000000;
	add.f32 	%f1184, %f1182, 0f3F800000;
	selp.f32 	%f1185, %f1184, %f1182, %p132;
	selp.f32 	%f1186, %f1183, %f1180, %p132;
	add.f32 	%f1187, %f1186, 0fBF800000;
	add.f32 	%f1188, %f1186, 0f3F800000;
	rcp.approx.ftz.f32 	%f1189, %f1188;
	add.f32 	%f1190, %f1187, %f1187;
	mul.f32 	%f1191, %f1190, %f1189;
	mul.f32 	%f1192, %f1191, %f1191;
	mov.f32 	%f1193, 0f3C4CAF63;
	mov.f32 	%f1194, 0f3B18F0FE;
	fma.rn.f32 	%f1195, %f1194, %f1192, %f1193;
	mov.f32 	%f1196, 0f3DAAAABD;
	fma.rn.f32 	%f1197, %f1195, %f1192, %f1196;
	mul.rn.f32 	%f1198, %f1197, %f1192;
	mul.rn.f32 	%f1199, %f1198, %f1191;
	sub.f32 	%f1200, %f1187, %f1191;
	add.f32 	%f1201, %f1200, %f1200;
	neg.f32 	%f1202, %f1191;
	fma.rn.f32 	%f1203, %f1202, %f1187, %f1201;
	mul.rn.f32 	%f1204, %f1189, %f1203;
	add.f32 	%f1205, %f1199, %f1191;
	sub.f32 	%f1206, %f1191, %f1205;
	add.f32 	%f1207, %f1199, %f1206;
	add.f32 	%f1208, %f1204, %f1207;
	add.f32 	%f1209, %f1205, %f1208;
	sub.f32 	%f1210, %f1205, %f1209;
	add.f32 	%f1211, %f1208, %f1210;
	mov.f32 	%f1212, 0f3F317200;
	mul.rn.f32 	%f1213, %f1185, %f1212;
	mov.f32 	%f1214, 0f35BFBE8E;
	mul.rn.f32 	%f1215, %f1185, %f1214;
	add.f32 	%f1216, %f1213, %f1209;
	sub.f32 	%f1217, %f1213, %f1216;
	add.f32 	%f1218, %f1209, %f1217;
	add.f32 	%f1219, %f1211, %f1218;
	add.f32 	%f1220, %f1215, %f1219;
	add.f32 	%f1221, %f1216, %f1220;
	sub.f32 	%f1222, %f1216, %f1221;
	add.f32 	%f1223, %f1220, %f1222;
	mov.f32 	%f1224, 0f3ED55555;
	mul.rn.f32 	%f1225, %f1224, %f1221;
	neg.f32 	%f1226, %f1225;
	fma.rn.f32 	%f1227, %f1224, %f1221, %f1226;
	fma.rn.f32 	%f1228, %f1224, %f1223, %f1227;
	mov.f32 	%f1229, 0f00000000;
	fma.rn.f32 	%f1230, %f1229, %f1221, %f1228;
	add.rn.f32 	%f1231, %f1225, %f1230;
	neg.f32 	%f1232, %f1231;
	add.rn.f32 	%f1233, %f1225, %f1232;
	add.rn.f32 	%f1234, %f1233, %f1230;
	mov.b32 	%r362, %f1231;
	setp.eq.s32 	%p133, %r362, 1118925336;
	add.s32 	%r363, %r362, -1;
	mov.b32 	%f1235, %r363;
	add.f32 	%f1236, %f1234, 0f37000000;
	selp.f32 	%f261, %f1236, %f1234, %p133;
	selp.f32 	%f1237, %f1235, %f1231, %p133;
	mov.f32 	%f1238, 0f3FB8AA3B;
	mul.rn.f32 	%f1239, %f1237, %f1238;
	cvt.rzi.f32.f32 	%f1240, %f1239;
	abs.f32 	%f1241, %f1240;
	setp.gt.f32 	%p134, %f1241, 0f42FC0000;
	mov.b32 	%r364, %f1240;
	and.b32  	%r365, %r364, -2147483648;
	or.b32  	%r366, %r365, 1123811328;
	mov.b32 	%f1242, %r366;
	selp.f32 	%f1243, %f1242, %f1240, %p134;
	mov.f32 	%f1244, 0fBF317218;
	fma.rn.f32 	%f1245, %f1243, %f1244, %f1237;
	mov.f32 	%f1246, 0f3102E308;
	fma.rn.f32 	%f1247, %f1243, %f1246, %f1245;
	mul.f32 	%f1248, %f1247, 0f3FB8AA3B;
	add.f32 	%f1249, %f1243, 0f4B40007F;
	mov.b32 	%r367, %f1249;
	shl.b32 	%r368, %r367, 23;
	mov.b32 	%f1250, %r368;
	ex2.approx.ftz.f32 	%f1251, %f1248;
	mul.f32 	%f262, %f1251, %f1250;
	setp.eq.f32 	%p135, %f262, 0f7F800000;
	mov.f32 	%f1578, 0f7F800000;
	@%p135 bra 	$L__BB0_110;

	fma.rn.f32 	%f1578, %f262, %f261, %f262;

$L__BB0_110:
	setp.lt.f32 	%p136, %f246, 0f00000000;
	and.pred  	%p8, %p136, %p123;
	setp.eq.f32 	%p138, %f246, 0f00000000;
	@%p138 bra 	$L__BB0_114;
	bra.uni 	$L__BB0_111;

$L__BB0_114:
	add.f32 	%f1256, %f246, %f246;
	selp.f32 	%f1580, %f1256, 0f00000000, %p123;
	bra.uni 	$L__BB0_115;

$L__BB0_111:
	mov.b32 	%r369, %f1578;
	xor.b32  	%r370, %r369, -2147483648;
	mov.b32 	%f1252, %r370;
	selp.f32 	%f1580, %f1252, %f1578, %p8;
	setp.geu.f32 	%p139, %f246, 0f00000000;
	@%p139 bra 	$L__BB0_115;

	mov.f32 	%f1253, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1254, %f1253;
	setp.eq.f32 	%p140, %f1254, 0f3ED55555;
	@%p140 bra 	$L__BB0_115;

	mov.f32 	%f1580, 0f7FFFFFFF;

$L__BB0_115:
	add.f32 	%f1257, %f260, 0f3ED55555;
	mov.b32 	%r371, %f1257;
	setp.lt.s32 	%p142, %r371, 2139095040;
	@%p142 bra 	$L__BB0_120;

	setp.gtu.f32 	%p143, %f260, 0f7F800000;
	@%p143 bra 	$L__BB0_119;
	bra.uni 	$L__BB0_117;

$L__BB0_119:
	add.f32 	%f1580, %f246, 0f3ED55555;
	bra.uni 	$L__BB0_120;

$L__BB0_117:
	setp.neu.f32 	%p144, %f260, 0f7F800000;
	@%p144 bra 	$L__BB0_120;

	selp.f32 	%f1580, 0fFF800000, 0f7F800000, %p8;

$L__BB0_120:
	abs.f32 	%f271, %f247;
	setp.lt.f32 	%p145, %f271, 0f00800000;
	mul.f32 	%f1259, %f271, 0f4B800000;
	selp.f32 	%f1260, %f1259, %f271, %p145;
	selp.f32 	%f1261, 0fC3170000, 0fC2FE0000, %p145;
	mov.b32 	%r372, %f1260;
	and.b32  	%r373, %r372, 8388607;
	or.b32  	%r374, %r373, 1065353216;
	mov.b32 	%f1262, %r374;
	shr.u32 	%r375, %r372, 23;
	cvt.rn.f32.u32 	%f1263, %r375;
	add.f32 	%f1264, %f1261, %f1263;
	setp.gt.f32 	%p146, %f1262, 0f3FB504F3;
	mul.f32 	%f1265, %f1262, 0f3F000000;
	add.f32 	%f1266, %f1264, 0f3F800000;
	selp.f32 	%f1267, %f1266, %f1264, %p146;
	selp.f32 	%f1268, %f1265, %f1262, %p146;
	add.f32 	%f1269, %f1268, 0fBF800000;
	add.f32 	%f1270, %f1268, 0f3F800000;
	rcp.approx.ftz.f32 	%f1271, %f1270;
	add.f32 	%f1272, %f1269, %f1269;
	mul.f32 	%f1273, %f1272, %f1271;
	mul.f32 	%f1274, %f1273, %f1273;
	mov.f32 	%f1275, 0f3C4CAF63;
	mov.f32 	%f1276, 0f3B18F0FE;
	fma.rn.f32 	%f1277, %f1276, %f1274, %f1275;
	mov.f32 	%f1278, 0f3DAAAABD;
	fma.rn.f32 	%f1279, %f1277, %f1274, %f1278;
	mul.rn.f32 	%f1280, %f1279, %f1274;
	mul.rn.f32 	%f1281, %f1280, %f1273;
	sub.f32 	%f1282, %f1269, %f1273;
	add.f32 	%f1283, %f1282, %f1282;
	neg.f32 	%f1284, %f1273;
	fma.rn.f32 	%f1285, %f1284, %f1269, %f1283;
	mul.rn.f32 	%f1286, %f1271, %f1285;
	add.f32 	%f1287, %f1281, %f1273;
	sub.f32 	%f1288, %f1273, %f1287;
	add.f32 	%f1289, %f1281, %f1288;
	add.f32 	%f1290, %f1286, %f1289;
	add.f32 	%f1291, %f1287, %f1290;
	sub.f32 	%f1292, %f1287, %f1291;
	add.f32 	%f1293, %f1290, %f1292;
	mov.f32 	%f1294, 0f3F317200;
	mul.rn.f32 	%f1295, %f1267, %f1294;
	mov.f32 	%f1296, 0f35BFBE8E;
	mul.rn.f32 	%f1297, %f1267, %f1296;
	add.f32 	%f1298, %f1295, %f1291;
	sub.f32 	%f1299, %f1295, %f1298;
	add.f32 	%f1300, %f1291, %f1299;
	add.f32 	%f1301, %f1293, %f1300;
	add.f32 	%f1302, %f1297, %f1301;
	add.f32 	%f1303, %f1298, %f1302;
	sub.f32 	%f1304, %f1298, %f1303;
	add.f32 	%f1305, %f1302, %f1304;
	mov.f32 	%f1306, 0f3ED55555;
	mul.rn.f32 	%f1307, %f1306, %f1303;
	neg.f32 	%f1308, %f1307;
	fma.rn.f32 	%f1309, %f1306, %f1303, %f1308;
	fma.rn.f32 	%f1310, %f1306, %f1305, %f1309;
	mov.f32 	%f1311, 0f00000000;
	fma.rn.f32 	%f1312, %f1311, %f1303, %f1310;
	add.rn.f32 	%f1313, %f1307, %f1312;
	neg.f32 	%f1314, %f1313;
	add.rn.f32 	%f1315, %f1307, %f1314;
	add.rn.f32 	%f1316, %f1315, %f1312;
	mov.b32 	%r376, %f1313;
	setp.eq.s32 	%p147, %r376, 1118925336;
	add.s32 	%r377, %r376, -1;
	mov.b32 	%f1317, %r377;
	add.f32 	%f1318, %f1316, 0f37000000;
	selp.f32 	%f272, %f1318, %f1316, %p147;
	selp.f32 	%f1319, %f1317, %f1313, %p147;
	mov.f32 	%f1320, 0f3FB8AA3B;
	mul.rn.f32 	%f1321, %f1319, %f1320;
	cvt.rzi.f32.f32 	%f1322, %f1321;
	abs.f32 	%f1323, %f1322;
	setp.gt.f32 	%p148, %f1323, 0f42FC0000;
	mov.b32 	%r378, %f1322;
	and.b32  	%r379, %r378, -2147483648;
	or.b32  	%r380, %r379, 1123811328;
	mov.b32 	%f1324, %r380;
	selp.f32 	%f1325, %f1324, %f1322, %p148;
	mov.f32 	%f1326, 0fBF317218;
	fma.rn.f32 	%f1327, %f1325, %f1326, %f1319;
	mov.f32 	%f1328, 0f3102E308;
	fma.rn.f32 	%f1329, %f1325, %f1328, %f1327;
	mul.f32 	%f1330, %f1329, 0f3FB8AA3B;
	add.f32 	%f1331, %f1325, 0f4B40007F;
	mov.b32 	%r381, %f1331;
	shl.b32 	%r382, %r381, 23;
	mov.b32 	%f1332, %r382;
	ex2.approx.ftz.f32 	%f1333, %f1330;
	mul.f32 	%f273, %f1333, %f1332;
	setp.eq.f32 	%p149, %f273, 0f7F800000;
	mov.f32 	%f1581, 0f7F800000;
	@%p149 bra 	$L__BB0_122;

	fma.rn.f32 	%f1581, %f273, %f272, %f273;

$L__BB0_122:
	setp.lt.f32 	%p150, %f247, 0f00000000;
	and.pred  	%p9, %p150, %p123;
	setp.eq.f32 	%p152, %f247, 0f00000000;
	@%p152 bra 	$L__BB0_126;
	bra.uni 	$L__BB0_123;

$L__BB0_126:
	add.f32 	%f1338, %f247, %f247;
	selp.f32 	%f1583, %f1338, 0f00000000, %p123;
	bra.uni 	$L__BB0_127;

$L__BB0_123:
	mov.b32 	%r383, %f1581;
	xor.b32  	%r384, %r383, -2147483648;
	mov.b32 	%f1334, %r384;
	selp.f32 	%f1583, %f1334, %f1581, %p9;
	setp.geu.f32 	%p153, %f247, 0f00000000;
	@%p153 bra 	$L__BB0_127;

	mov.f32 	%f1335, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1336, %f1335;
	setp.eq.f32 	%p154, %f1336, 0f3ED55555;
	@%p154 bra 	$L__BB0_127;

	mov.f32 	%f1583, 0f7FFFFFFF;

$L__BB0_127:
	add.f32 	%f1339, %f271, 0f3ED55555;
	mov.b32 	%r385, %f1339;
	setp.lt.s32 	%p156, %r385, 2139095040;
	@%p156 bra 	$L__BB0_132;

	setp.gtu.f32 	%p157, %f271, 0f7F800000;
	@%p157 bra 	$L__BB0_131;
	bra.uni 	$L__BB0_129;

$L__BB0_131:
	add.f32 	%f1583, %f247, 0f3ED55555;
	bra.uni 	$L__BB0_132;

$L__BB0_129:
	setp.neu.f32 	%p158, %f271, 0f7F800000;
	@%p158 bra 	$L__BB0_132;

	selp.f32 	%f1583, 0fFF800000, 0f7F800000, %p9;

$L__BB0_132:
	fma.rn.f32 	%f1340, %f1577, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p159, %f245, 0f3F800000;
	mov.f32 	%f1341, 0f3F800000;
	selp.f32 	%f1342, 0f3F7FFFFF, %f1340, %p159;
	mul.f32 	%f1343, %f245, 0f414EB852;
	setp.lt.f32 	%p160, %f245, 0f3B4D2E1C;
	selp.f32 	%f1344, %f1343, %f1342, %p160;
	fma.rn.f32 	%f1345, %f1580, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p161, %f246, 0f3F800000;
	selp.f32 	%f1346, 0f3F7FFFFF, %f1345, %p161;
	mul.f32 	%f1347, %f246, 0f414EB852;
	setp.lt.f32 	%p162, %f246, 0f3B4D2E1C;
	selp.f32 	%f1348, %f1347, %f1346, %p162;
	fma.rn.f32 	%f1349, %f1583, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p163, %f247, 0f3F800000;
	selp.f32 	%f1350, 0f3F7FFFFF, %f1349, %p163;
	mul.f32 	%f1351, %f247, 0f414EB852;
	setp.lt.f32 	%p164, %f247, 0f3B4D2E1C;
	selp.f32 	%f1352, %f1351, %f1350, %p164;
	min.f32 	%f1353, %f1344, %f1341;
	mov.f32 	%f1354, 0f00000000;
	max.f32 	%f1355, %f1354, %f1353;
	mul.f32 	%f1356, %f1355, 0f43800000;
	cvt.rzi.u32.f32 	%r386, %f1356;
	min.u32 	%r387, %r386, 255;
	min.f32 	%f1357, %f1348, %f1341;
	max.f32 	%f1358, %f1354, %f1357;
	mul.f32 	%f1359, %f1358, 0f43800000;
	cvt.rzi.u32.f32 	%r388, %f1359;
	min.u32 	%r389, %r388, 255;
	min.f32 	%f1360, %f1352, %f1341;
	max.f32 	%f1361, %f1354, %f1360;
	mul.f32 	%f1362, %f1361, 0f43800000;
	cvt.rzi.u32.f32 	%r390, %f1362;
	min.u32 	%r391, %r390, 255;
	shl.b64 	%rd37, %rd10, 2;
	add.s64 	%rd38, %rd9, %rd37;
	cvt.u16.u32 	%rs20, %r391;
	cvt.u16.u32 	%rs21, %r389;
	cvt.u16.u32 	%rs22, %r387;
	mov.u16 	%rs23, 255;
	st.global.v4.u8 	[%rd38], {%rs22, %rs21, %rs20, %rs23};

$L__BB0_133:
	and.b32  	%r392, %r427, 4;
	setp.eq.s32 	%p165, %r392, 0;
	ld.const.u32 	%r428, [params+108];
	@%p165 bra 	$L__BB0_137;

	setp.eq.s32 	%p166, %r428, 0;
	ld.const.u64 	%rd39, [params+224];
	cvta.to.global.u64 	%rd40, %rd39;
	ld.const.u32 	%r393, [params+216];
	mad.lo.s32 	%r394, %r393, %r4, %r3;
	mul.wide.u32 	%rd41, %r394, 8;
	add.s64 	%rd11, %rd40, %rd41;
	@%p166 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs31, %rs32, %rs33, %rs34}, [%rd11];
	// begin inline asm
	{  cvt.f32.f16 %f1363, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1364, %rs32;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1365, %rs33;}

	// end inline asm
	add.f32 	%f1366, %f1531, %f1363;
	add.f32 	%f1367, %f1532, %f1364;
	add.f32 	%f1368, %f1533, %f1365;
	mov.f32 	%f1369, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1368;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1367;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1366;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1369;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs27, %rs28, %rs29, %rs30};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1373, 0f3F800000;
	mov.u32 	%r428, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1373;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f1533;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1532;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f1531;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs35, %rs36, %rs37, %rs38};

$L__BB0_137:
	mov.f32 	%f1374, 0f34000000;
	max.f32 	%f1375, %f1534, %f1374;
	div.rn.f32 	%f1376, %f1537, %f1375;
	max.f32 	%f1377, %f1535, %f1374;
	div.rn.f32 	%f1378, %f1538, %f1377;
	max.f32 	%f1379, %f1536, %f1374;
	div.rn.f32 	%f1380, %f1539, %f1379;
	fma.rn.f32 	%f282, %f1376, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f283, %f1378, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f284, %f1380, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1381, %f1540, %f1375;
	div.rn.f32 	%f1382, %f1541, %f1377;
	div.rn.f32 	%f1383, %f1542, %f1379;
	fma.rn.f32 	%f285, %f1381, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f286, %f1382, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f287, %f1383, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1384, %f1543, %f1375;
	div.rn.f32 	%f1385, %f1544, %f1377;
	div.rn.f32 	%f1386, %f1545, %f1379;
	fma.rn.f32 	%f288, %f1384, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f289, %f1385, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f290, %f1386, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd42, [params+256];
	cvta.to.global.u64 	%rd43, %rd42;
	ld.const.u32 	%r396, [params+248];
	mad.lo.s32 	%r397, %r396, %r4, %r3;
	mul.wide.u32 	%rd44, %r397, 8;
	add.s64 	%rd12, %rd43, %rd44;
	setp.eq.s32 	%p167, %r428, 0;
	@%p167 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs46, %rs47, %rs48, %rs49}, [%rd12];
	// begin inline asm
	{  cvt.f32.f16 %f1387, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1388, %rs47;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1389, %rs48;}

	// end inline asm
	add.f32 	%f1390, %f1534, %f1387;
	add.f32 	%f1391, %f1535, %f1388;
	add.f32 	%f1392, %f1536, %f1389;
	mov.f32 	%f1393, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1392;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1391;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1390;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f1393;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs42, %rs43, %rs44, %rs45};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1397, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1397;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f1536;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1535;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f1534;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs50, %rs51, %rs52, %rs53};

$L__BB0_140:
	ld.const.u64 	%rd45, [params+272];
	cvta.to.global.u64 	%rd46, %rd45;
	ld.const.u32 	%r398, [params+264];
	mad.lo.s32 	%r399, %r398, %r4, %r3;
	mul.wide.u32 	%rd47, %r399, 8;
	add.s64 	%rd13, %rd46, %rd47;
	@%p167 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs61, %rs62, %rs63, %rs64}, [%rd13];
	// begin inline asm
	{  cvt.f32.f16 %f1398, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1399, %rs62;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1400, %rs63;}

	// end inline asm
	add.f32 	%f1401, %f282, %f1398;
	add.f32 	%f1402, %f283, %f1399;
	add.f32 	%f1403, %f284, %f1400;
	mov.f32 	%f1404, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1403;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1402;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1401;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1404;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs57, %rs58, %rs59, %rs60};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1408, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1408;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f284;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f283;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f282;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs65, %rs66, %rs67, %rs68};

$L__BB0_143:
	ld.const.u64 	%rd48, [params+288];
	cvta.to.global.u64 	%rd49, %rd48;
	ld.const.u32 	%r400, [params+280];
	mad.lo.s32 	%r401, %r400, %r4, %r3;
	mul.wide.u32 	%rd50, %r401, 8;
	add.s64 	%rd14, %rd49, %rd50;
	@%p167 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs76, %rs77, %rs78, %rs79}, [%rd14];
	// begin inline asm
	{  cvt.f32.f16 %f1409, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1410, %rs77;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1411, %rs78;}

	// end inline asm
	add.f32 	%f1412, %f285, %f1409;
	add.f32 	%f1413, %f286, %f1410;
	add.f32 	%f1414, %f287, %f1411;
	mov.f32 	%f1415, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1414;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1413;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1412;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f1415;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs72, %rs73, %rs74, %rs75};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1419, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1419;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f287;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f286;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f285;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs80, %rs81, %rs82, %rs83};

$L__BB0_146:
	ld.const.u64 	%rd51, [params+304];
	cvta.to.global.u64 	%rd52, %rd51;
	ld.const.u32 	%r402, [params+296];
	mad.lo.s32 	%r403, %r402, %r4, %r3;
	mul.wide.u32 	%rd53, %r403, 8;
	add.s64 	%rd15, %rd52, %rd53;
	@%p167 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs91, %rs92, %rs93, %rs94}, [%rd15];
	// begin inline asm
	{  cvt.f32.f16 %f1420, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1421, %rs92;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1422, %rs93;}

	// end inline asm
	add.f32 	%f1423, %f288, %f1420;
	add.f32 	%f1424, %f289, %f1421;
	add.f32 	%f1425, %f290, %f1422;
	mov.f32 	%f1426, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1425;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1424;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1423;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f1426;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs87, %rs88, %rs89, %rs90};
	bra.uni 	$L__BB0_169;

$L__BB0_148:
	mov.f32 	%f1430, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1430;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f290;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f289;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f288;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs95, %rs96, %rs97, %rs98};

$L__BB0_169:
	ret;

}