//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<199>;
	.reg .b16 	%rs<177>;
	.reg .f32 	%f<1577>;
	.reg .b32 	%r<497>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<127>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r92), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r93), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+616];
	abs.s32 	%r4, %r3;
	ld.const.u32 	%r5, [params+540];
	shl.b32 	%r6, %r5, 1;
	ld.const.u64 	%rd34, [params+400];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r98, [params+392];
	mad.lo.s32 	%r99, %r98, %r93, %r92;
	mul.wide.u32 	%rd36, %r99, 4;
	add.s64 	%rd2, %rd35, %rd36;
	ld.global.v2.u8 	{%rs7, %rs176}, [%rd2];
	or.b16  	%rs9, %rs7, %rs176;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p10, %rs10, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs175, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs175, [%rd2+2];
	setp.eq.s16 	%p11, %rs175, 0;
	mov.f32 	%f1429, 0f00000000;
	mov.u16 	%rs176, 0;
	mov.f32 	%f1430, %f1429;
	mov.f32 	%f1431, %f1429;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f375, %rs7;
	div.rn.f32 	%f376, %f375, 0f437F0000;
	fma.rn.f32 	%f377, %f376, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs176, 255;
	cvt.rn.f32.u16 	%f378, %rs13;
	div.rn.f32 	%f379, %f378, 0f437F0000;
	fma.rn.f32 	%f380, %f379, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f381, %rs175;
	div.rn.f32 	%f382, %f381, 0f437F0000;
	fma.rn.f32 	%f383, %f382, 0f40000000, 0fBF800000;
	mul.f32 	%f384, %f380, %f380;
	fma.rn.f32 	%f385, %f377, %f377, %f384;
	fma.rn.f32 	%f386, %f383, %f383, %f385;
	sqrt.rn.f32 	%f387, %f386;
	rcp.rn.f32 	%f388, %f387;
	mul.f32 	%f1431, %f388, %f383;
	mul.f32 	%f1430, %f388, %f380;
	mul.f32 	%f1429, %f377, %f388;

$L__BB0_4:
	ld.const.v2.u32 	{%r100, %r101}, [params];
	add.s32 	%r7, %r100, %r92;
	add.s32 	%r8, %r101, %r93;
	setp.eq.f32 	%p12, %f1429, 0f00000000;
	setp.eq.f32 	%p13, %f1430, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1431, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_160;
	bra.uni 	$L__BB0_5;

$L__BB0_160:
	ld.const.u32 	%r89, [params+104];
	and.b32  	%r461, %r89, 1;
	setp.eq.b32 	%p187, %r461, 1;
	mov.pred 	%p188, 0;
	xor.pred  	%p189, %p187, %p188;
	not.pred 	%p190, %p189;
	@%p190 bra 	$L__BB0_162;

	ld.const.u64 	%rd97, [params+144];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r462, [params+136];
	mad.lo.s32 	%r463, %r462, %r8, %r7;
	mul.wide.u32 	%rd99, %r463, 4;
	add.s64 	%rd100, %rd98, %rd99;
	mov.u16 	%rs97, 0;
	st.global.v4.u8 	[%rd100], {%rs97, %rs97, %rs97, %rs97};

$L__BB0_162:
	and.b32  	%r464, %r89, 8;
	setp.eq.s32 	%p191, %r464, 0;
	@%p191 bra 	$L__BB0_164;

	ld.const.u64 	%rd101, [params+192];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r465, [params+184];
	mad.lo.s32 	%r466, %r465, %r8, %r7;
	mov.f32 	%f1377, 0f00000000;
	cvt.rzi.u32.f32 	%r467, %f1377;
	mul.wide.u32 	%rd103, %r466, 2;
	add.s64 	%rd104, %rd102, %rd103;
	mov.u16 	%rs98, 0;
	cvt.u16.u32 	%rs99, %r467;
	st.global.v2.u8 	[%rd104], {%rs99, %rs98};

$L__BB0_164:
	and.b32  	%r468, %r89, 4;
	setp.eq.s32 	%p192, %r468, 0;
	ld.const.u32 	%r496, [params+108];
	@%p192 bra 	$L__BB0_168;

	setp.eq.s32 	%p193, %r496, 0;
	ld.const.u64 	%rd105, [params+224];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r469, [params+216];
	mad.lo.s32 	%r470, %r469, %r8, %r7;
	mul.wide.u32 	%rd107, %r470, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p193 bra 	$L__BB0_167;

	ld.global.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1378, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1379, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1380, %rs108;}

	// end inline asm
	add.f32 	%f1381, %f1378, 0f00000000;
	add.f32 	%f1382, %f1379, 0f00000000;
	add.f32 	%f1383, %f1380, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1383;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1382;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1381;}

	// end inline asm
	mov.u16 	%rs110, 0;
	st.global.v4.u16 	[%rd28], {%rs103, %rs104, %rs105, %rs110};
	bra.uni 	$L__BB0_168;

$L__BB0_5:
	ld.const.u64 	%rd37, [params+432];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r105, [params+424];
	mad.lo.s32 	%r106, %r105, %r93, %r92;
	mul.wide.u32 	%rd39, %r106, 12;
	add.s64 	%rd40, %rd38, %rd39;
	ld.global.f32 	%f10, [%rd40];
	mul.f32 	%f405, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd40+4];
	mul.f32 	%f406, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd40+8];
	mul.f32 	%f407, %f12, 0f3456BF95;
	abs.f32 	%f408, %f1429;
	div.rn.f32 	%f409, %f405, %f408;
	abs.f32 	%f410, %f1430;
	div.rn.f32 	%f411, %f406, %f410;
	abs.f32 	%f412, %f1431;
	div.rn.f32 	%f413, %f407, %f412;
	abs.f32 	%f414, %f409;
	abs.f32 	%f415, %f411;
	abs.f32 	%f416, %f413;
	mov.f32 	%f417, 0f38D1B717;
	max.f32 	%f418, %f414, %f417;
	max.f32 	%f419, %f415, %f417;
	max.f32 	%f420, %f416, %f417;
	fma.rn.f32 	%f13, %f1429, %f418, %f10;
	fma.rn.f32 	%f14, %f1430, %f419, %f11;
	fma.rn.f32 	%f15, %f1431, %f420, %f12;
	ld.const.u64 	%rd41, [params+128];
	cvta.to.global.u64 	%rd42, %rd41;
	ld.const.u32 	%r107, [params+120];
	mad.lo.s32 	%r108, %r107, %r93, %r92;
	mul.wide.u32 	%rd43, %r108, 4;
	add.s64 	%rd44, %rd42, %rd43;
	ld.global.u32 	%r487, [%rd44];
	setp.lt.s32 	%p18, %r4, 1;
	mov.pred 	%p17, 0;
	mov.f32 	%f1451, 0f00000000;
	mov.u32 	%r483, 0;
	mov.f32 	%f1452, %f1451;
	mov.f32 	%f1453, %f1451;
	mov.f32 	%f1454, %f1451;
	mov.f32 	%f1455, %f1451;
	mov.f32 	%f1456, %f1451;
	mov.f32 	%f1457, %f1451;
	mov.f32 	%f1458, %f1451;
	mov.f32 	%f1459, %f1451;
	mov.f32 	%f1460, %f1451;
	mov.f32 	%f1461, %f1451;
	mov.f32 	%f1462, %f1451;
	mov.f32 	%f1463, %f1451;
	mov.f32 	%f1464, %f1451;
	mov.f32 	%f1465, %f1451;
	mov.f32 	%f1466, %f1451;
	mov.pred 	%p198, %p17;
	@%p18 bra 	$L__BB0_23;

	ld.const.f32 	%f16, [params+620];
	ld.const.u64 	%rd45, [params+624];
	cvta.to.global.u64 	%rd3, %rd45;
	ld.const.u64 	%rd46, [params+640];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r110, [params+632];
	and.b32  	%r111, %r93, 255;
	and.b32  	%r112, %r92, 255;
	mad.lo.s32 	%r113, %r110, %r111, %r112;
	mul.wide.u32 	%rd48, %r113, 3;
	add.s64 	%rd4, %rd47, %rd48;
	ld.const.f32 	%f17, [params+660];
	mul.f32 	%f18, %f13, 0f3456BF95;
	mul.f32 	%f19, %f14, 0f3456BF95;
	mul.f32 	%f20, %f15, 0f3456BF95;
	ld.const.u64 	%rd5, [params+96];
	abs.f32 	%f564, %f19;
	abs.f32 	%f565, %f18;
	max.f32 	%f566, %f565, %f564;
	abs.f32 	%f567, %f20;
	max.f32 	%f568, %f566, %f567;

$L__BB0_7:
	shl.b32 	%r114, %r483, 1;
	mul.wide.s32 	%rd49, %r114, 12;
	add.s64 	%rd6, %rd3, %rd49;
	ld.global.f32 	%f437, [%rd6];
	sub.f32 	%f438, %f437, %f10;
	ld.global.f32 	%f439, [%rd6+4];
	sub.f32 	%f440, %f439, %f11;
	ld.global.f32 	%f441, [%rd6+8];
	sub.f32 	%f442, %f441, %f12;
	mul.f32 	%f443, %f440, %f440;
	fma.rn.f32 	%f444, %f438, %f438, %f443;
	fma.rn.f32 	%f445, %f442, %f442, %f444;
	sqrt.rn.f32 	%f37, %f445;
	rcp.rn.f32 	%f446, %f37;
	mul.f32 	%f38, %f438, %f446;
	mul.f32 	%f39, %f440, %f446;
	mul.f32 	%f40, %f442, %f446;
	mul.f32 	%f447, %f37, %f37;
	div.rn.f32 	%f41, %f16, %f447;
	ld.global.u8 	%rs15, [%rd4];
	cvt.rn.f32.u16 	%f448, %rs15;
	div.rn.f32 	%f449, %f448, 0fC37F0000;
	fma.rn.f32 	%f450, %f449, 0f3F333333, 0f3F800000;
	setp.gt.f32 	%p20, %f41, %f450;
	setp.ne.s32 	%p21, %r5, 0;
	and.pred  	%p22, %p21, %p20;
	mov.pred 	%p198, -1;
	@%p22 bra 	$L__BB0_23;

	mul.f32 	%f42, %f37, %f17;
	mov.f32 	%f455, 0f40800000;
	abs.f32 	%f44, %f42;
	setp.lt.f32 	%p23, %f44, 0f00800000;
	mul.f32 	%f457, %f44, 0f4B800000;
	selp.f32 	%f458, %f457, %f44, %p23;
	selp.f32 	%f459, 0fC3170000, 0fC2FE0000, %p23;
	mov.b32 	%r115, %f458;
	and.b32  	%r116, %r115, 8388607;
	or.b32  	%r117, %r116, 1065353216;
	mov.b32 	%f460, %r117;
	shr.u32 	%r118, %r115, 23;
	cvt.rn.f32.u32 	%f461, %r118;
	add.f32 	%f462, %f459, %f461;
	setp.gt.f32 	%p24, %f460, 0f3FB504F3;
	mul.f32 	%f463, %f460, 0f3F000000;
	add.f32 	%f464, %f462, 0f3F800000;
	selp.f32 	%f465, %f464, %f462, %p24;
	selp.f32 	%f466, %f463, %f460, %p24;
	add.f32 	%f467, %f466, 0fBF800000;
	add.f32 	%f468, %f466, 0f3F800000;
	rcp.approx.ftz.f32 	%f469, %f468;
	add.f32 	%f470, %f467, %f467;
	mul.f32 	%f471, %f470, %f469;
	mul.f32 	%f472, %f471, %f471;
	mov.f32 	%f473, 0f3C4CAF63;
	mov.f32 	%f474, 0f3B18F0FE;
	fma.rn.f32 	%f475, %f474, %f472, %f473;
	mov.f32 	%f476, 0f3DAAAABD;
	fma.rn.f32 	%f477, %f475, %f472, %f476;
	mul.rn.f32 	%f478, %f477, %f472;
	mul.rn.f32 	%f479, %f478, %f471;
	sub.f32 	%f480, %f467, %f471;
	add.f32 	%f481, %f480, %f480;
	neg.f32 	%f482, %f471;
	fma.rn.f32 	%f483, %f482, %f467, %f481;
	mul.rn.f32 	%f484, %f469, %f483;
	add.f32 	%f485, %f479, %f471;
	sub.f32 	%f486, %f471, %f485;
	add.f32 	%f487, %f479, %f486;
	add.f32 	%f488, %f484, %f487;
	add.f32 	%f489, %f485, %f488;
	sub.f32 	%f490, %f485, %f489;
	add.f32 	%f491, %f488, %f490;
	mov.f32 	%f492, 0f3F317200;
	mul.rn.f32 	%f493, %f465, %f492;
	mov.f32 	%f494, 0f35BFBE8E;
	mul.rn.f32 	%f495, %f465, %f494;
	add.f32 	%f496, %f493, %f489;
	sub.f32 	%f497, %f493, %f496;
	add.f32 	%f498, %f489, %f497;
	add.f32 	%f499, %f491, %f498;
	add.f32 	%f500, %f495, %f499;
	add.f32 	%f501, %f496, %f500;
	sub.f32 	%f502, %f496, %f501;
	add.f32 	%f503, %f500, %f502;
	mul.rn.f32 	%f504, %f455, %f501;
	neg.f32 	%f505, %f504;
	fma.rn.f32 	%f506, %f455, %f501, %f505;
	fma.rn.f32 	%f507, %f455, %f503, %f506;
	mov.f32 	%f508, 0f00000000;
	fma.rn.f32 	%f509, %f508, %f501, %f507;
	add.rn.f32 	%f510, %f504, %f509;
	neg.f32 	%f511, %f510;
	add.rn.f32 	%f512, %f504, %f511;
	add.rn.f32 	%f513, %f512, %f509;
	mov.b32 	%r119, %f510;
	setp.eq.s32 	%p25, %r119, 1118925336;
	add.s32 	%r120, %r119, -1;
	mov.b32 	%f514, %r120;
	add.f32 	%f515, %f513, 0f37000000;
	selp.f32 	%f45, %f515, %f513, %p25;
	selp.f32 	%f516, %f514, %f510, %p25;
	mov.f32 	%f517, 0f3FB8AA3B;
	mul.rn.f32 	%f518, %f516, %f517;
	cvt.rzi.f32.f32 	%f519, %f518;
	abs.f32 	%f520, %f519;
	setp.gt.f32 	%p26, %f520, 0f42FC0000;
	mov.b32 	%r121, %f519;
	and.b32  	%r122, %r121, -2147483648;
	or.b32  	%r123, %r122, 1123811328;
	mov.b32 	%f521, %r123;
	selp.f32 	%f522, %f521, %f519, %p26;
	mov.f32 	%f523, 0fBF317218;
	fma.rn.f32 	%f524, %f522, %f523, %f516;
	mov.f32 	%f525, 0f3102E308;
	fma.rn.f32 	%f526, %f522, %f525, %f524;
	mul.f32 	%f527, %f526, 0f3FB8AA3B;
	add.f32 	%f528, %f522, 0f4B40007F;
	mov.b32 	%r124, %f528;
	shl.b32 	%r125, %r124, 23;
	mov.b32 	%f529, %r125;
	ex2.approx.ftz.f32 	%f530, %f527;
	mul.f32 	%f46, %f530, %f529;
	setp.eq.f32 	%p27, %f46, 0f7F800000;
	mov.f32 	%f1448, 0f7F800000;
	@%p27 bra 	$L__BB0_10;

	fma.rn.f32 	%f1448, %f46, %f45, %f46;

$L__BB0_10:
	mov.f32 	%f1428, 0f40000000;
	cvt.rzi.f32.f32 	%f1427, %f1428;
	add.f32 	%f1426, %f1427, %f1427;
	mov.f32 	%f1425, 0f40800000;
	sub.f32 	%f1424, %f1425, %f1426;
	abs.f32 	%f1423, %f1424;
	setp.lt.f32 	%p28, %f42, 0f00000000;
	setp.eq.f32 	%p29, %f1423, 0f3F800000;
	and.pred  	%p1, %p28, %p29;
	setp.eq.f32 	%p30, %f42, 0f00000000;
	@%p30 bra 	$L__BB0_14;
	bra.uni 	$L__BB0_11;

$L__BB0_14:
	add.f32 	%f535, %f42, %f42;
	selp.f32 	%f1450, %f535, 0f00000000, %p29;
	bra.uni 	$L__BB0_15;

$L__BB0_11:
	mov.b32 	%r126, %f1448;
	xor.b32  	%r127, %r126, -2147483648;
	mov.b32 	%f531, %r127;
	selp.f32 	%f1450, %f531, %f1448, %p1;
	setp.geu.f32 	%p31, %f42, 0f00000000;
	@%p31 bra 	$L__BB0_15;

	mov.f32 	%f532, 0f40800000;
	cvt.rzi.f32.f32 	%f533, %f532;
	setp.eq.f32 	%p32, %f533, 0f40800000;
	@%p32 bra 	$L__BB0_15;

	mov.f32 	%f1450, 0f7FFFFFFF;

$L__BB0_15:
	add.f32 	%f536, %f44, 0f40800000;
	mov.b32 	%r128, %f536;
	setp.lt.s32 	%p34, %r128, 2139095040;
	@%p34 bra 	$L__BB0_20;

	setp.gtu.f32 	%p35, %f44, 0f7F800000;
	@%p35 bra 	$L__BB0_19;
	bra.uni 	$L__BB0_17;

$L__BB0_19:
	add.f32 	%f1450, %f42, 0f40800000;
	bra.uni 	$L__BB0_20;

$L__BB0_17:
	setp.neu.f32 	%p36, %f44, 0f7F800000;
	@%p36 bra 	$L__BB0_20;

	selp.f32 	%f1450, 0fFF800000, 0f7F800000, %p1;

$L__BB0_20:
	shl.b32 	%r480, %r483, 1;
	mul.wide.s32 	%rd121, %r480, 12;
	add.s64 	%rd120, %rd3, %rd121;
	mov.f32 	%f537, 0f3F800000;
	sub.f32 	%f538, %f537, %f1450;
	setp.eq.f32 	%p37, %f42, 0f3F800000;
	selp.f32 	%f539, 0f00000000, %f538, %p37;
	cvt.sat.f32.f32 	%f540, %f539;
	mul.f32 	%f541, %f41, %f540;
	ld.global.f32 	%f542, [%rd120+12];
	mul.f32 	%f543, %f38, %f542;
	ld.global.f32 	%f544, [%rd120+16];
	mul.f32 	%f545, %f39, %f544;
	neg.f32 	%f546, %f545;
	sub.f32 	%f547, %f546, %f543;
	ld.global.f32 	%f548, [%rd120+20];
	mul.f32 	%f549, %f40, %f548;
	sub.f32 	%f550, %f547, %f549;
	cvt.sat.f32.f32 	%f551, %f550;
	mul.f32 	%f55, %f541, %f551;
	mul.f32 	%f552, %f1430, %f39;
	fma.rn.f32 	%f553, %f1429, %f38, %f552;
	fma.rn.f32 	%f56, %f1431, %f40, %f553;
	setp.leu.f32 	%p38, %f55, 0f3727C5AC;
	@%p38 bra 	$L__BB0_22;

	cvt.sat.f32.f32 	%f563, %f56;
	mov.f32 	%f569, 0f38D1B717;
	max.f32 	%f560, %f568, %f569;
	sub.f32 	%f561, %f37, %f560;
	mov.f32 	%f562, 0f00000000;
	mov.u32 	%r165, 2;
	mov.u32 	%r166, 1;
	mov.u32 	%r167, 3;
	mov.u32 	%r170, 1065353216;
	mov.u32 	%r199, 0;
	// begin inline asm
	call(%r129,%r130,%r131,%r132,%r133,%r134,%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160),_optix_trace_typed_32,(%r199,%rd5,%f13,%f14,%f15,%f38,%f39,%f40,%f560,%f561,%f562,%r166,%r199,%r166,%r165,%r166,%r167,%r170,%r170,%r170,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199,%r199);
	// end inline asm
	mov.b32 	%f570, %r129;
	mov.b32 	%f571, %r130;
	mov.b32 	%f572, %r131;
	mul.f32 	%f573, %f55, 0f3EA2F983;
	mul.f32 	%f574, %f573, %f570;
	mul.f32 	%f575, %f573, %f571;
	mul.f32 	%f576, %f573, %f572;
	fma.rn.f32 	%f1463, %f563, %f574, %f1463;
	fma.rn.f32 	%f1464, %f563, %f575, %f1464;
	fma.rn.f32 	%f1465, %f563, %f576, %f1465;
	fma.rn.f32 	%f1457, %f38, %f574, %f1457;
	fma.rn.f32 	%f1458, %f38, %f575, %f1458;
	fma.rn.f32 	%f1459, %f38, %f576, %f1459;
	fma.rn.f32 	%f1454, %f39, %f574, %f1454;
	fma.rn.f32 	%f1455, %f39, %f575, %f1455;
	fma.rn.f32 	%f1456, %f39, %f576, %f1456;
	fma.rn.f32 	%f1451, %f40, %f574, %f1451;
	fma.rn.f32 	%f1452, %f40, %f575, %f1452;
	fma.rn.f32 	%f1453, %f40, %f576, %f1453;
	add.f32 	%f1460, %f1460, %f574;
	add.f32 	%f1461, %f1461, %f575;
	add.f32 	%f1462, %f1462, %f576;
	add.f32 	%f1466, %f1466, %f570;

$L__BB0_22:
	add.s32 	%r483, %r483, 1;
	setp.lt.s32 	%p40, %r483, %r4;
	mov.pred 	%p198, %p17;
	@%p40 bra 	$L__BB0_7;

$L__BB0_23:
	cvt.rn.f32.s32 	%f577, %r483;
	mov.f32 	%f578, 0f3F800000;
	max.f32 	%f579, %f577, %f578;
	rcp.rn.f32 	%f580, %f579;
	mul.f32 	%f1552, %f1463, %f580;
	mul.f32 	%f1553, %f1464, %f580;
	mul.f32 	%f1554, %f1465, %f580;
	div.rn.f32 	%f1555, %f1466, %f579;
	mul.f32 	%f1549, %f1460, %f580;
	mul.f32 	%f1550, %f1461, %f580;
	mul.f32 	%f1551, %f1462, %f580;
	mul.f32 	%f1546, %f1457, %f580;
	mul.f32 	%f1547, %f1458, %f580;
	mul.f32 	%f1548, %f1459, %f580;
	mul.f32 	%f1543, %f1454, %f580;
	mul.f32 	%f1544, %f1455, %f580;
	mul.f32 	%f1545, %f1456, %f580;
	mul.f32 	%f1540, %f1451, %f580;
	mul.f32 	%f1541, %f1452, %f580;
	mul.f32 	%f1542, %f1453, %f580;
	not.pred 	%p41, %p198;
	@%p41 bra 	$L__BB0_56;

	setp.lt.s32 	%p42, %r5, 1;
	mov.f32 	%f1514, 0f00000000;
	mov.f32 	%f1513, %f1514;
	mov.f32 	%f1512, %f1514;
	mov.f32 	%f1511, %f1514;
	mov.f32 	%f1510, %f1514;
	mov.f32 	%f1509, %f1514;
	mov.f32 	%f1508, %f1514;
	mov.f32 	%f1507, %f1514;
	mov.f32 	%f1506, %f1514;
	mov.f32 	%f1505, %f1514;
	mov.f32 	%f1504, %f1514;
	mov.f32 	%f1503, %f1514;
	mov.f32 	%f1502, %f1514;
	mov.f32 	%f1501, %f1514;
	mov.f32 	%f1500, %f1514;
	mov.f32 	%f1499, %f1514;
	@%p42 bra 	$L__BB0_55;

	cvt.rn.f32.s32 	%f613, %r6;
	rcp.rn.f32 	%f121, %f613;
	mul.f32 	%f122, %f13, 0f3456BF95;
	mul.f32 	%f123, %f14, 0f3456BF95;
	mul.f32 	%f124, %f15, 0f3456BF95;
	mov.u32 	%r200, 0;
	ld.const.u64 	%rd7, [params+96];
	add.s64 	%rd8, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f674, %f123;
	abs.f32 	%f675, %f122;
	max.f32 	%f676, %f675, %f674;
	abs.f32 	%f677, %f124;
	max.f32 	%f678, %f676, %f677;
	mov.u32 	%r484, %r200;

$L__BB0_26:
	cvt.rn.f32.s32 	%f141, %r484;
	mov.u32 	%r486, %r200;

$L__BB0_27:
	mad.lo.s32 	%r202, %r487, 1664525, 1013904223;
	and.b32  	%r203, %r202, 16777215;
	cvt.rn.f32.u32 	%f614, %r203;
	fma.rn.f32 	%f615, %f614, 0f33800000, %f141;
	mul.f32 	%f616, %f121, %f615;
	mad.lo.s32 	%r487, %r202, 1664525, 1013904223;
	and.b32  	%r204, %r487, 16777215;
	cvt.rn.f32.u32 	%f617, %r204;
	cvt.rn.f32.s32 	%f618, %r486;
	fma.rn.f32 	%f619, %f617, 0f33800000, %f618;
	mul.f32 	%f620, %f121, %f619;
	fma.rn.f32 	%f621, %f121, %f615, %f616;
	mov.f32 	%f622, 0f3F800000;
	sub.f32 	%f158, %f622, %f621;
	mul.f32 	%f623, %f158, %f158;
	sub.f32 	%f624, %f622, %f623;
	mov.f32 	%f625, 0f00000000;
	max.f32 	%f626, %f625, %f624;
	sqrt.rn.f32 	%f159, %f626;
	mul.f32 	%f160, %f620, 0f40C90FDB;
	mul.f32 	%f627, %f160, 0f3F22F983;
	cvt.rni.s32.f32 	%r494, %f627;
	cvt.rn.f32.s32 	%f628, %r494;
	mov.f32 	%f629, 0fBFC90FDA;
	fma.rn.f32 	%f630, %f628, %f629, %f160;
	mov.f32 	%f631, 0fB3A22168;
	fma.rn.f32 	%f632, %f628, %f631, %f630;
	mov.f32 	%f633, 0fA7C234C5;
	fma.rn.f32 	%f1518, %f628, %f633, %f632;
	abs.f32 	%f162, %f160;
	setp.ltu.f32 	%p43, %f162, 0f47CE4780;
	mov.u32 	%r491, %r494;
	mov.f32 	%f1515, %f1518;
	@%p43 bra 	$L__BB0_35;

	setp.eq.f32 	%p44, %f162, 0f7F800000;
	@%p44 bra 	$L__BB0_34;
	bra.uni 	$L__BB0_29;

$L__BB0_34:
	mov.f32 	%f636, 0f00000000;
	mul.rn.f32 	%f1515, %f160, %f636;
	mov.u32 	%r491, 0;
	bra.uni 	$L__BB0_35;

$L__BB0_29:
	mov.b32 	%r19, %f160;
	bfe.u32 	%r206, %r19, 23, 8;
	add.s32 	%r20, %r206, -128;
	shl.b32 	%r207, %r19, 8;
	or.b32  	%r21, %r207, -2147483648;
	shr.u32 	%r22, %r20, 5;
	mov.u64 	%rd124, 0;
	mov.u32 	%r488, 0;
	mov.u64 	%rd122, %rd1;
	mov.u64 	%rd123, %rd51;

$L__BB0_30:
	.pragma "nounroll";
	ld.global.nc.u32 	%r208, [%rd123];
	mad.wide.u32 	%rd53, %r208, %r21, %rd124;
	shr.u64 	%rd124, %rd53, 32;
	st.local.u32 	[%rd122], %rd53;
	add.s64 	%rd123, %rd123, 4;
	add.s64 	%rd122, %rd122, 4;
	add.s32 	%r488, %r488, 1;
	setp.ne.s32 	%p45, %r488, 6;
	@%p45 bra 	$L__BB0_30;

	st.local.u32 	[%rd8], %rd124;
	mov.u32 	%r209, 4;
	sub.s32 	%r25, %r209, %r22;
	mov.u32 	%r210, 6;
	sub.s32 	%r211, %r210, %r22;
	mul.wide.s32 	%rd54, %r211, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r489, [%rd55];
	ld.local.u32 	%r490, [%rd55+-4];
	and.b32  	%r28, %r20, 31;
	setp.eq.s32 	%p46, %r28, 0;
	@%p46 bra 	$L__BB0_33;

	mov.u32 	%r212, 32;
	sub.s32 	%r213, %r212, %r28;
	shr.u32 	%r214, %r490, %r213;
	shl.b32 	%r215, %r489, %r28;
	add.s32 	%r489, %r214, %r215;
	mul.wide.s32 	%rd56, %r25, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r216, [%rd57];
	shr.u32 	%r217, %r216, %r213;
	shl.b32 	%r218, %r490, %r28;
	add.s32 	%r490, %r217, %r218;

$L__BB0_33:
	and.b32  	%r219, %r19, -2147483648;
	shr.u32 	%r220, %r490, 30;
	shl.b32 	%r221, %r489, 2;
	or.b32  	%r222, %r220, %r221;
	shr.u32 	%r223, %r222, 31;
	shr.u32 	%r224, %r489, 30;
	add.s32 	%r225, %r223, %r224;
	neg.s32 	%r226, %r225;
	setp.eq.s32 	%p47, %r219, 0;
	selp.b32 	%r491, %r225, %r226, %p47;
	setp.ne.s32 	%p48, %r223, 0;
	xor.b32  	%r227, %r219, -2147483648;
	selp.b32 	%r228, %r227, %r219, %p48;
	selp.b32 	%r229, -1, 0, %p48;
	xor.b32  	%r230, %r222, %r229;
	shl.b32 	%r231, %r490, 2;
	xor.b32  	%r232, %r231, %r229;
	cvt.u64.u32 	%rd58, %r230;
	cvt.u64.u32 	%rd59, %r232;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f634, %fd2;
	setp.eq.s32 	%p49, %r228, 0;
	neg.f32 	%f635, %f634;
	selp.f32 	%f1515, %f634, %f635, %p49;

$L__BB0_35:
	add.s32 	%r35, %r491, 1;
	and.b32  	%r36, %r35, 1;
	setp.eq.s32 	%p50, %r36, 0;
	selp.f32 	%f166, %f1515, 0f3F800000, %p50;
	mul.rn.f32 	%f167, %f1515, %f1515;
	mov.f32 	%f1516, 0fB94D4153;
	@%p50 bra 	$L__BB0_37;

	mov.f32 	%f638, 0fBAB607ED;
	mov.f32 	%f639, 0f37CBAC00;
	fma.rn.f32 	%f1516, %f639, %f167, %f638;

$L__BB0_37:
	selp.f32 	%f640, 0f3C0885E4, 0f3D2AAABB, %p50;
	fma.rn.f32 	%f641, %f1516, %f167, %f640;
	selp.f32 	%f642, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
	fma.rn.f32 	%f643, %f641, %f167, %f642;
	mov.f32 	%f644, 0f00000000;
	fma.rn.f32 	%f645, %f167, %f166, %f644;
	fma.rn.f32 	%f1517, %f643, %f645, %f166;
	and.b32  	%r234, %r35, 2;
	setp.eq.s32 	%p52, %r234, 0;
	@%p52 bra 	$L__BB0_39;

	mov.f32 	%f647, 0fBF800000;
	fma.rn.f32 	%f1517, %f1517, %f647, %f644;

$L__BB0_39:
	mul.f32 	%f173, %f159, %f1517;
	@%p43 bra 	$L__BB0_47;

	setp.eq.f32 	%p54, %f162, 0f7F800000;
	@%p54 bra 	$L__BB0_46;
	bra.uni 	$L__BB0_41;

$L__BB0_46:
	mov.f32 	%f650, 0f00000000;
	mul.rn.f32 	%f1518, %f160, %f650;
	mov.u32 	%r494, 0;
	bra.uni 	$L__BB0_47;

$L__BB0_41:
	mov.b32 	%r37, %f160;
	bfe.u32 	%r235, %r37, 23, 8;
	add.s32 	%r38, %r235, -128;
	shl.b32 	%r236, %r37, 8;
	or.b32  	%r39, %r236, -2147483648;
	shr.u32 	%r40, %r38, 5;
	mov.u64 	%rd125, 0;
	mov.u64 	%rd126, %rd125;

$L__BB0_42:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd125, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r237, [%rd65];
	mad.wide.u32 	%rd66, %r237, %r39, %rd126;
	shr.u64 	%rd126, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r238, %rd125;
	add.s32 	%r239, %r238, 1;
	cvt.s64.s32 	%rd125, %r239;
	setp.ne.s32 	%p55, %r239, 6;
	@%p55 bra 	$L__BB0_42;

	st.local.u32 	[%rd8], %rd126;
	mov.u32 	%r240, 4;
	sub.s32 	%r41, %r240, %r40;
	mov.u32 	%r241, 6;
	sub.s32 	%r242, %r241, %r40;
	mul.wide.s32 	%rd68, %r242, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r492, [%rd69];
	ld.local.u32 	%r493, [%rd69+-4];
	and.b32  	%r44, %r38, 31;
	setp.eq.s32 	%p56, %r44, 0;
	@%p56 bra 	$L__BB0_45;

	mov.u32 	%r243, 32;
	sub.s32 	%r244, %r243, %r44;
	shr.u32 	%r245, %r493, %r244;
	shl.b32 	%r246, %r492, %r44;
	add.s32 	%r492, %r245, %r246;
	mul.wide.s32 	%rd70, %r41, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r247, [%rd71];
	shr.u32 	%r248, %r247, %r244;
	shl.b32 	%r249, %r493, %r44;
	add.s32 	%r493, %r248, %r249;

$L__BB0_45:
	and.b32  	%r250, %r37, -2147483648;
	shr.u32 	%r251, %r493, 30;
	shl.b32 	%r252, %r492, 2;
	or.b32  	%r253, %r251, %r252;
	shr.u32 	%r254, %r253, 31;
	shr.u32 	%r255, %r492, 30;
	add.s32 	%r256, %r254, %r255;
	neg.s32 	%r257, %r256;
	setp.eq.s32 	%p57, %r250, 0;
	selp.b32 	%r494, %r256, %r257, %p57;
	setp.ne.s32 	%p58, %r254, 0;
	xor.b32  	%r258, %r250, -2147483648;
	selp.b32 	%r259, %r258, %r250, %p58;
	selp.b32 	%r260, -1, 0, %p58;
	xor.b32  	%r261, %r253, %r260;
	shl.b32 	%r262, %r493, 2;
	xor.b32  	%r263, %r262, %r260;
	cvt.u64.u32 	%rd72, %r261;
	cvt.u64.u32 	%rd73, %r263;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f648, %fd4;
	setp.eq.s32 	%p59, %r259, 0;
	neg.f32 	%f649, %f648;
	selp.f32 	%f1518, %f648, %f649, %p59;

$L__BB0_47:
	and.b32  	%r51, %r494, 1;
	setp.eq.s32 	%p60, %r51, 0;
	selp.f32 	%f177, %f1518, 0f3F800000, %p60;
	mul.rn.f32 	%f178, %f1518, %f1518;
	mov.f32 	%f1519, 0fB94D4153;
	@%p60 bra 	$L__BB0_49;

	mov.f32 	%f652, 0fBAB607ED;
	mov.f32 	%f653, 0f37CBAC00;
	fma.rn.f32 	%f1519, %f653, %f178, %f652;

$L__BB0_49:
	selp.f32 	%f654, 0f3C0885E4, 0f3D2AAABB, %p60;
	fma.rn.f32 	%f655, %f1519, %f178, %f654;
	selp.f32 	%f656, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
	fma.rn.f32 	%f657, %f655, %f178, %f656;
	mov.f32 	%f1521, 0f00000000;
	fma.rn.f32 	%f659, %f178, %f177, %f1521;
	fma.rn.f32 	%f1520, %f657, %f659, %f177;
	and.b32  	%r265, %r494, 2;
	setp.eq.s32 	%p62, %r265, 0;
	@%p62 bra 	$L__BB0_51;

	mov.f32 	%f660, 0f00000000;
	mov.f32 	%f661, 0fBF800000;
	fma.rn.f32 	%f1520, %f1520, %f661, %f660;

$L__BB0_51:
	mov.f32 	%f679, 0f38D1B717;
	max.f32 	%f668, %f678, %f679;
	mul.f32 	%f666, %f159, %f1520;
	mov.f32 	%f669, 0f6C4ECB8F;
	mov.u32 	%r299, 1;
	mov.u32 	%r302, 2;
	mov.u32 	%r304, 4;
	mov.u32 	%r307, 1065353216;
	mov.u32 	%r308, 2139095039;
	mov.u32 	%r336, 0;
	// begin inline asm
	call(%r266,%r267,%r268,%r269,%r270,%r271,%r272,%r273,%r274,%r275,%r276,%r277,%r278,%r279,%r280,%r281,%r282,%r283,%r284,%r285,%r286,%r287,%r288,%r289,%r290,%r291,%r292,%r293,%r294,%r295,%r296,%r297),_optix_trace_typed_32,(%r336,%rd7,%f13,%f14,%f15,%f173,%f666,%f158,%f668,%f669,%f1521,%r299,%r336,%r336,%r302,%r336,%r304,%r307,%r307,%r307,%r308,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336,%r336);
	// end inline asm
	mov.b32 	%f185, %r269;
	setp.ge.f32 	%p63, %f185, 0f00000000;
	mov.f32 	%f1522, %f1521;
	mov.f32 	%f1523, %f1521;
	@%p63 bra 	$L__BB0_53;

	mov.b32 	%f1523, %r266;
	mov.b32 	%f1522, %r267;
	mov.b32 	%f1521, %r268;

$L__BB0_53:
	setp.ltu.f32 	%p64, %f185, 0f00000000;
	selp.f32 	%f680, 0f3F800000, 0f00000000, %p64;
	add.f32 	%f1499, %f1499, %f680;
	fma.rn.f32 	%f1508, %f173, %f1523, %f1508;
	fma.rn.f32 	%f1507, %f173, %f1522, %f1507;
	fma.rn.f32 	%f1506, %f173, %f1521, %f1506;
	fma.rn.f32 	%f1511, %f666, %f1523, %f1511;
	fma.rn.f32 	%f1510, %f666, %f1522, %f1510;
	fma.rn.f32 	%f1509, %f666, %f1521, %f1509;
	fma.rn.f32 	%f1514, %f158, %f1523, %f1514;
	fma.rn.f32 	%f1513, %f158, %f1522, %f1513;
	fma.rn.f32 	%f1512, %f158, %f1521, %f1512;
	add.f32 	%f1505, %f1505, %f1523;
	add.f32 	%f1504, %f1504, %f1522;
	add.f32 	%f1503, %f1503, %f1521;
	mul.f32 	%f681, %f1430, %f666;
	fma.rn.f32 	%f682, %f1429, %f173, %f681;
	fma.rn.f32 	%f683, %f1431, %f158, %f682;
	cvt.sat.f32.f32 	%f684, %f683;
	fma.rn.f32 	%f1502, %f1523, %f684, %f1502;
	fma.rn.f32 	%f1501, %f1522, %f684, %f1501;
	fma.rn.f32 	%f1500, %f1521, %f684, %f1500;
	add.s32 	%r486, %r486, 1;
	setp.lt.s32 	%p65, %r486, %r6;
	@%p65 bra 	$L__BB0_27;

	add.s32 	%r484, %r484, 1;
	setp.lt.s32 	%p66, %r484, %r6;
	@%p66 bra 	$L__BB0_26;

$L__BB0_55:
	mul.lo.s32 	%r337, %r6, %r6;
	cvt.rn.f32.s32 	%f685, %r337;
	rcp.rn.f32 	%f686, %f685;
	mul.f32 	%f687, %f686, %f1502;
	mul.f32 	%f688, %f686, %f1501;
	mul.f32 	%f689, %f686, %f1500;
	div.rn.f32 	%f1555, %f1499, %f685;
	mul.f32 	%f1549, %f686, %f1505;
	mul.f32 	%f1550, %f686, %f1504;
	mul.f32 	%f1551, %f686, %f1503;
	mul.f32 	%f1546, %f686, %f1508;
	mul.f32 	%f1547, %f686, %f1507;
	mul.f32 	%f1548, %f686, %f1506;
	mul.f32 	%f1543, %f686, %f1511;
	mul.f32 	%f1544, %f686, %f1510;
	mul.f32 	%f1545, %f686, %f1509;
	mul.f32 	%f1540, %f686, %f1514;
	mul.f32 	%f1541, %f686, %f1513;
	mul.f32 	%f1542, %f686, %f1512;
	fma.rn.f32 	%f1552, %f686, %f1502, %f687;
	fma.rn.f32 	%f1553, %f686, %f1501, %f688;
	fma.rn.f32 	%f1554, %f686, %f1500, %f689;

$L__BB0_56:
	ld.const.u32 	%r481, [params+616];
	setp.lt.s32 	%p67, %r481, 0;
	selp.f32 	%f256, %f1552, %f1555, %p67;
	ld.const.u32 	%r86, [params+104];
	and.b32  	%r338, %r86, 8;
	setp.eq.s32 	%p68, %r338, 0;
	@%p68 bra 	$L__BB0_70;

	ld.const.u64 	%rd76, [params+192];
	cvta.to.global.u64 	%rd19, %rd76;
	ld.const.u32 	%r339, [params+184];
	mad.lo.s32 	%r340, %r339, %r8, %r7;
	cvt.u64.u32 	%rd20, %r340;
	mov.f32 	%f691, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f692, %f691;
	add.f32 	%f693, %f692, %f692;
	mov.f32 	%f694, 0f3EE8BA2E;
	sub.f32 	%f695, %f694, %f693;
	abs.f32 	%f257, %f695;
	abs.f32 	%f258, %f256;
	setp.lt.f32 	%p69, %f258, 0f00800000;
	mul.f32 	%f696, %f258, 0f4B800000;
	selp.f32 	%f697, %f696, %f258, %p69;
	selp.f32 	%f698, 0fC3170000, 0fC2FE0000, %p69;
	mov.b32 	%r341, %f697;
	and.b32  	%r342, %r341, 8388607;
	or.b32  	%r343, %r342, 1065353216;
	mov.b32 	%f699, %r343;
	shr.u32 	%r344, %r341, 23;
	cvt.rn.f32.u32 	%f700, %r344;
	add.f32 	%f701, %f698, %f700;
	setp.gt.f32 	%p70, %f699, 0f3FB504F3;
	mul.f32 	%f702, %f699, 0f3F000000;
	add.f32 	%f703, %f701, 0f3F800000;
	selp.f32 	%f704, %f703, %f701, %p70;
	selp.f32 	%f705, %f702, %f699, %p70;
	add.f32 	%f706, %f705, 0fBF800000;
	add.f32 	%f707, %f705, 0f3F800000;
	rcp.approx.ftz.f32 	%f708, %f707;
	add.f32 	%f709, %f706, %f706;
	mul.f32 	%f710, %f709, %f708;
	mul.f32 	%f711, %f710, %f710;
	mov.f32 	%f712, 0f3C4CAF63;
	mov.f32 	%f713, 0f3B18F0FE;
	fma.rn.f32 	%f714, %f713, %f711, %f712;
	mov.f32 	%f715, 0f3DAAAABD;
	fma.rn.f32 	%f716, %f714, %f711, %f715;
	mul.rn.f32 	%f717, %f716, %f711;
	mul.rn.f32 	%f718, %f717, %f710;
	sub.f32 	%f719, %f706, %f710;
	add.f32 	%f720, %f719, %f719;
	neg.f32 	%f721, %f710;
	fma.rn.f32 	%f722, %f721, %f706, %f720;
	mul.rn.f32 	%f723, %f708, %f722;
	add.f32 	%f724, %f718, %f710;
	sub.f32 	%f725, %f710, %f724;
	add.f32 	%f726, %f718, %f725;
	add.f32 	%f727, %f723, %f726;
	add.f32 	%f728, %f724, %f727;
	sub.f32 	%f729, %f724, %f728;
	add.f32 	%f730, %f727, %f729;
	mov.f32 	%f731, 0f3F317200;
	mul.rn.f32 	%f732, %f704, %f731;
	mov.f32 	%f733, 0f35BFBE8E;
	mul.rn.f32 	%f734, %f704, %f733;
	add.f32 	%f735, %f732, %f728;
	sub.f32 	%f736, %f732, %f735;
	add.f32 	%f737, %f728, %f736;
	add.f32 	%f738, %f730, %f737;
	add.f32 	%f739, %f734, %f738;
	add.f32 	%f740, %f735, %f739;
	sub.f32 	%f741, %f735, %f740;
	add.f32 	%f742, %f739, %f741;
	mul.rn.f32 	%f743, %f694, %f740;
	neg.f32 	%f744, %f743;
	fma.rn.f32 	%f745, %f694, %f740, %f744;
	fma.rn.f32 	%f746, %f694, %f742, %f745;
	mov.f32 	%f747, 0f00000000;
	fma.rn.f32 	%f748, %f747, %f740, %f746;
	add.rn.f32 	%f749, %f743, %f748;
	neg.f32 	%f750, %f749;
	add.rn.f32 	%f751, %f743, %f750;
	add.rn.f32 	%f752, %f751, %f748;
	mov.b32 	%r345, %f749;
	setp.eq.s32 	%p71, %r345, 1118925336;
	add.s32 	%r346, %r345, -1;
	mov.b32 	%f753, %r346;
	add.f32 	%f754, %f752, 0f37000000;
	selp.f32 	%f259, %f754, %f752, %p71;
	selp.f32 	%f755, %f753, %f749, %p71;
	mov.f32 	%f756, 0f3FB8AA3B;
	mul.rn.f32 	%f757, %f755, %f756;
	cvt.rzi.f32.f32 	%f758, %f757;
	abs.f32 	%f759, %f758;
	setp.gt.f32 	%p72, %f759, 0f42FC0000;
	mov.b32 	%r347, %f758;
	and.b32  	%r348, %r347, -2147483648;
	or.b32  	%r349, %r348, 1123811328;
	mov.b32 	%f760, %r349;
	selp.f32 	%f761, %f760, %f758, %p72;
	mov.f32 	%f762, 0fBF317218;
	fma.rn.f32 	%f763, %f761, %f762, %f755;
	mov.f32 	%f764, 0f3102E308;
	fma.rn.f32 	%f765, %f761, %f764, %f763;
	mul.f32 	%f766, %f765, 0f3FB8AA3B;
	add.f32 	%f767, %f761, 0f4B40007F;
	mov.b32 	%r350, %f767;
	shl.b32 	%r351, %r350, 23;
	mov.b32 	%f768, %r351;
	ex2.approx.ftz.f32 	%f769, %f766;
	mul.f32 	%f260, %f769, %f768;
	setp.eq.f32 	%p73, %f260, 0f7F800000;
	mov.f32 	%f1556, 0f7F800000;
	@%p73 bra 	$L__BB0_59;

	fma.rn.f32 	%f1556, %f260, %f259, %f260;

$L__BB0_59:
	setp.lt.f32 	%p74, %f256, 0f00000000;
	setp.eq.f32 	%p75, %f257, 0f3F800000;
	and.pred  	%p3, %p74, %p75;
	setp.eq.f32 	%p76, %f256, 0f00000000;
	@%p76 bra 	$L__BB0_63;
	bra.uni 	$L__BB0_60;

$L__BB0_63:
	add.f32 	%f774, %f256, %f256;
	selp.f32 	%f1558, %f774, 0f00000000, %p75;
	bra.uni 	$L__BB0_64;

$L__BB0_167:
	mov.f32 	%f1386, 0f00000000;
	mov.u32 	%r496, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1386;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1386;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1386;}

	// end inline asm
	mov.u16 	%rs114, 0;
	st.global.v4.u16 	[%rd28], {%rs111, %rs112, %rs113, %rs114};

$L__BB0_168:
	ld.const.u64 	%rd108, [params+256];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r472, [params+248];
	mad.lo.s32 	%r473, %r472, %r8, %r7;
	mul.wide.u32 	%rd110, %r473, 8;
	add.s64 	%rd29, %rd109, %rd110;
	setp.eq.s32 	%p194, %r496, 0;
	@%p194 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1387, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1388, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1389, %rs123;}

	// end inline asm
	add.f32 	%f1390, %f1387, 0f00000000;
	add.f32 	%f1391, %f1388, 0f00000000;
	add.f32 	%f1392, %f1389, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1392;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1391;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1390;}

	// end inline asm
	mov.u16 	%rs125, 0;
	st.global.v4.u16 	[%rd29], {%rs118, %rs119, %rs120, %rs125};
	bra.uni 	$L__BB0_171;

$L__BB0_170:
	mov.f32 	%f1395, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1395;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1395;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1395;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd29], {%rs126, %rs127, %rs128, %rs129};

$L__BB0_171:
	ld.const.u64 	%rd111, [params+272];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r474, [params+264];
	mad.lo.s32 	%r475, %r474, %r8, %r7;
	mul.wide.u32 	%rd113, %r475, 8;
	add.s64 	%rd30, %rd112, %rd113;
	@%p194 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1396, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1397, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1398, %rs138;}

	// end inline asm
	add.f32 	%f1399, %f1396, 0f00000000;
	add.f32 	%f1400, %f1397, 0f00000000;
	add.f32 	%f1401, %f1398, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1401;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1400;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1399;}

	// end inline asm
	mov.u16 	%rs140, 0;
	st.global.v4.u16 	[%rd30], {%rs133, %rs134, %rs135, %rs140};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1404, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1404;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1404;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1404;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd30], {%rs141, %rs142, %rs143, %rs144};

$L__BB0_174:
	ld.const.u64 	%rd114, [params+288];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r476, [params+280];
	mad.lo.s32 	%r477, %r476, %r8, %r7;
	mul.wide.u32 	%rd116, %r477, 8;
	add.s64 	%rd31, %rd115, %rd116;
	@%p194 bra 	$L__BB0_176;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1405, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1406, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1407, %rs153;}

	// end inline asm
	add.f32 	%f1408, %f1405, 0f00000000;
	add.f32 	%f1409, %f1406, 0f00000000;
	add.f32 	%f1410, %f1407, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1410;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1409;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1408;}

	// end inline asm
	mov.u16 	%rs155, 0;
	st.global.v4.u16 	[%rd31], {%rs148, %rs149, %rs150, %rs155};
	bra.uni 	$L__BB0_177;

$L__BB0_176:
	mov.f32 	%f1413, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1413;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1413;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1413;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd31], {%rs156, %rs157, %rs158, %rs159};

$L__BB0_177:
	ld.const.u64 	%rd117, [params+304];
	cvta.to.global.u64 	%rd118, %rd117;
	ld.const.u32 	%r478, [params+296];
	mad.lo.s32 	%r479, %r478, %r8, %r7;
	mul.wide.u32 	%rd119, %r479, 8;
	add.s64 	%rd32, %rd118, %rd119;
	@%p194 bra 	$L__BB0_179;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1414, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1415, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1416, %rs168;}

	// end inline asm
	add.f32 	%f1417, %f1414, 0f00000000;
	add.f32 	%f1418, %f1415, 0f00000000;
	add.f32 	%f1419, %f1416, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1419;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1418;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1417;}

	// end inline asm
	mov.u16 	%rs170, 0;
	st.global.v4.u16 	[%rd32], {%rs163, %rs164, %rs165, %rs170};
	bra.uni 	$L__BB0_180;

$L__BB0_179:
	mov.f32 	%f1422, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1422;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1422;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1422;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd32], {%rs171, %rs172, %rs173, %rs174};
	bra.uni 	$L__BB0_180;

$L__BB0_60:
	mov.b32 	%r352, %f1556;
	xor.b32  	%r353, %r352, -2147483648;
	mov.b32 	%f770, %r353;
	selp.f32 	%f1558, %f770, %f1556, %p3;
	setp.geu.f32 	%p77, %f256, 0f00000000;
	@%p77 bra 	$L__BB0_64;

	mov.f32 	%f771, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f772, %f771;
	setp.eq.f32 	%p78, %f772, 0f3EE8BA2E;
	@%p78 bra 	$L__BB0_64;

	mov.f32 	%f1558, 0f7FFFFFFF;

$L__BB0_64:
	add.f32 	%f775, %f258, 0f3EE8BA2E;
	mov.b32 	%r354, %f775;
	setp.lt.s32 	%p80, %r354, 2139095040;
	@%p80 bra 	$L__BB0_69;

	setp.gtu.f32 	%p81, %f258, 0f7F800000;
	@%p81 bra 	$L__BB0_68;
	bra.uni 	$L__BB0_66;

$L__BB0_68:
	add.f32 	%f1558, %f256, 0f3EE8BA2E;
	bra.uni 	$L__BB0_69;

$L__BB0_66:
	setp.neu.f32 	%p82, %f258, 0f7F800000;
	@%p82 bra 	$L__BB0_69;

	selp.f32 	%f1558, 0fFF800000, 0f7F800000, %p3;

$L__BB0_69:
	mul.f32 	%f776, %f1558, 0f437F0000;
	setp.eq.f32 	%p83, %f256, 0f3F800000;
	selp.f32 	%f777, 0f437F0000, %f776, %p83;
	cvt.rzi.u32.f32 	%r355, %f777;
	shl.b64 	%rd77, %rd20, 1;
	add.s64 	%rd78, %rd19, %rd77;
	cvt.u16.u32 	%rs16, %r355;
	mov.u16 	%rs17, 255;
	st.global.v2.u8 	[%rd78], {%rs16, %rs17};

$L__BB0_70:
	ld.const.v2.f32 	{%f778, %f779}, [params+648];
	mul.f32 	%f271, %f1552, %f778;
	mul.f32 	%f272, %f1553, %f779;
	ld.const.f32 	%f273, [params+656];
	mul.f32 	%f274, %f1554, %f273;
	and.b32  	%r356, %r86, 1;
	setp.eq.b32 	%p84, %r356, 1;
	mov.pred 	%p85, 0;
	xor.pred  	%p86, %p84, %p85;
	not.pred 	%p87, %p86;
	@%p87 bra 	$L__BB0_144;

	mov.f32 	%f781, 0f3E666666;
	cvt.rzi.f32.f32 	%f782, %f781;
	add.f32 	%f783, %f782, %f782;
	mov.f32 	%f784, 0f3EE66666;
	sub.f32 	%f785, %f784, %f783;
	abs.f32 	%f275, %f785;
	abs.f32 	%f276, %f271;
	setp.lt.f32 	%p88, %f276, 0f00800000;
	mul.f32 	%f786, %f276, 0f4B800000;
	selp.f32 	%f787, %f786, %f276, %p88;
	selp.f32 	%f788, 0fC3170000, 0fC2FE0000, %p88;
	mov.b32 	%r357, %f787;
	and.b32  	%r358, %r357, 8388607;
	or.b32  	%r359, %r358, 1065353216;
	mov.b32 	%f789, %r359;
	shr.u32 	%r360, %r357, 23;
	cvt.rn.f32.u32 	%f790, %r360;
	add.f32 	%f791, %f788, %f790;
	setp.gt.f32 	%p89, %f789, 0f3FB504F3;
	mul.f32 	%f792, %f789, 0f3F000000;
	add.f32 	%f793, %f791, 0f3F800000;
	selp.f32 	%f794, %f793, %f791, %p89;
	selp.f32 	%f795, %f792, %f789, %p89;
	add.f32 	%f796, %f795, 0fBF800000;
	add.f32 	%f797, %f795, 0f3F800000;
	rcp.approx.ftz.f32 	%f798, %f797;
	add.f32 	%f799, %f796, %f796;
	mul.f32 	%f800, %f799, %f798;
	mul.f32 	%f801, %f800, %f800;
	mov.f32 	%f802, 0f3C4CAF63;
	mov.f32 	%f803, 0f3B18F0FE;
	fma.rn.f32 	%f804, %f803, %f801, %f802;
	mov.f32 	%f805, 0f3DAAAABD;
	fma.rn.f32 	%f806, %f804, %f801, %f805;
	mul.rn.f32 	%f807, %f806, %f801;
	mul.rn.f32 	%f808, %f807, %f800;
	sub.f32 	%f809, %f796, %f800;
	add.f32 	%f810, %f809, %f809;
	neg.f32 	%f811, %f800;
	fma.rn.f32 	%f812, %f811, %f796, %f810;
	mul.rn.f32 	%f813, %f798, %f812;
	add.f32 	%f814, %f808, %f800;
	sub.f32 	%f815, %f800, %f814;
	add.f32 	%f816, %f808, %f815;
	add.f32 	%f817, %f813, %f816;
	add.f32 	%f818, %f814, %f817;
	sub.f32 	%f819, %f814, %f818;
	add.f32 	%f820, %f817, %f819;
	mov.f32 	%f821, 0f3F317200;
	mul.rn.f32 	%f822, %f794, %f821;
	mov.f32 	%f823, 0f35BFBE8E;
	mul.rn.f32 	%f824, %f794, %f823;
	add.f32 	%f825, %f822, %f818;
	sub.f32 	%f826, %f822, %f825;
	add.f32 	%f827, %f818, %f826;
	add.f32 	%f828, %f820, %f827;
	add.f32 	%f829, %f824, %f828;
	add.f32 	%f830, %f825, %f829;
	sub.f32 	%f831, %f825, %f830;
	add.f32 	%f832, %f829, %f831;
	mul.rn.f32 	%f833, %f784, %f830;
	neg.f32 	%f834, %f833;
	fma.rn.f32 	%f835, %f784, %f830, %f834;
	fma.rn.f32 	%f836, %f784, %f832, %f835;
	mov.f32 	%f837, 0f00000000;
	fma.rn.f32 	%f838, %f837, %f830, %f836;
	add.rn.f32 	%f839, %f833, %f838;
	neg.f32 	%f840, %f839;
	add.rn.f32 	%f841, %f833, %f840;
	add.rn.f32 	%f842, %f841, %f838;
	mov.b32 	%r361, %f839;
	setp.eq.s32 	%p90, %r361, 1118925336;
	add.s32 	%r362, %r361, -1;
	mov.b32 	%f843, %r362;
	add.f32 	%f844, %f842, 0f37000000;
	selp.f32 	%f277, %f844, %f842, %p90;
	selp.f32 	%f845, %f843, %f839, %p90;
	mov.f32 	%f846, 0f3FB8AA3B;
	mul.rn.f32 	%f847, %f845, %f846;
	cvt.rzi.f32.f32 	%f848, %f847;
	abs.f32 	%f849, %f848;
	setp.gt.f32 	%p91, %f849, 0f42FC0000;
	mov.b32 	%r363, %f848;
	and.b32  	%r364, %r363, -2147483648;
	or.b32  	%r365, %r364, 1123811328;
	mov.b32 	%f850, %r365;
	selp.f32 	%f851, %f850, %f848, %p91;
	mov.f32 	%f852, 0fBF317218;
	fma.rn.f32 	%f853, %f851, %f852, %f845;
	mov.f32 	%f854, 0f3102E308;
	fma.rn.f32 	%f855, %f851, %f854, %f853;
	mul.f32 	%f856, %f855, 0f3FB8AA3B;
	add.f32 	%f857, %f851, 0f4B40007F;
	mov.b32 	%r366, %f857;
	shl.b32 	%r367, %r366, 23;
	mov.b32 	%f858, %r367;
	ex2.approx.ftz.f32 	%f859, %f856;
	mul.f32 	%f278, %f859, %f858;
	setp.eq.f32 	%p92, %f278, 0f7F800000;
	mov.f32 	%f1559, 0f7F800000;
	@%p92 bra 	$L__BB0_73;

	fma.rn.f32 	%f1559, %f278, %f277, %f278;

$L__BB0_73:
	setp.lt.f32 	%p93, %f271, 0f00000000;
	setp.eq.f32 	%p94, %f275, 0f3F800000;
	and.pred  	%p4, %p93, %p94;
	setp.eq.f32 	%p95, %f271, 0f00000000;
	@%p95 bra 	$L__BB0_77;
	bra.uni 	$L__BB0_74;

$L__BB0_77:
	add.f32 	%f864, %f271, %f271;
	selp.f32 	%f1561, %f864, 0f00000000, %p94;
	bra.uni 	$L__BB0_78;

$L__BB0_74:
	mov.b32 	%r368, %f1559;
	xor.b32  	%r369, %r368, -2147483648;
	mov.b32 	%f860, %r369;
	selp.f32 	%f1561, %f860, %f1559, %p4;
	setp.geu.f32 	%p96, %f271, 0f00000000;
	@%p96 bra 	$L__BB0_78;

	mov.f32 	%f861, 0f3EE66666;
	cvt.rzi.f32.f32 	%f862, %f861;
	setp.eq.f32 	%p97, %f862, 0f3EE66666;
	@%p97 bra 	$L__BB0_78;

	mov.f32 	%f1561, 0f7FFFFFFF;

$L__BB0_78:
	add.f32 	%f865, %f276, 0f3EE66666;
	mov.b32 	%r370, %f865;
	setp.lt.s32 	%p99, %r370, 2139095040;
	@%p99 bra 	$L__BB0_83;

	setp.gtu.f32 	%p100, %f276, 0f7F800000;
	@%p100 bra 	$L__BB0_82;
	bra.uni 	$L__BB0_80;

$L__BB0_82:
	add.f32 	%f1561, %f271, 0f3EE66666;
	bra.uni 	$L__BB0_83;

$L__BB0_80:
	setp.neu.f32 	%p101, %f276, 0f7F800000;
	@%p101 bra 	$L__BB0_83;

	selp.f32 	%f1561, 0fFF800000, 0f7F800000, %p4;

$L__BB0_83:
	setp.eq.f32 	%p102, %f271, 0f3F800000;
	selp.f32 	%f287, 0f3F800000, %f1561, %p102;
	abs.f32 	%f288, %f272;
	setp.lt.f32 	%p103, %f288, 0f00800000;
	mul.f32 	%f867, %f288, 0f4B800000;
	selp.f32 	%f868, %f867, %f288, %p103;
	selp.f32 	%f869, 0fC3170000, 0fC2FE0000, %p103;
	mov.b32 	%r371, %f868;
	and.b32  	%r372, %r371, 8388607;
	or.b32  	%r373, %r372, 1065353216;
	mov.b32 	%f870, %r373;
	shr.u32 	%r374, %r371, 23;
	cvt.rn.f32.u32 	%f871, %r374;
	add.f32 	%f872, %f869, %f871;
	setp.gt.f32 	%p104, %f870, 0f3FB504F3;
	mul.f32 	%f873, %f870, 0f3F000000;
	add.f32 	%f874, %f872, 0f3F800000;
	selp.f32 	%f875, %f874, %f872, %p104;
	selp.f32 	%f876, %f873, %f870, %p104;
	add.f32 	%f877, %f876, 0fBF800000;
	add.f32 	%f878, %f876, 0f3F800000;
	rcp.approx.ftz.f32 	%f879, %f878;
	add.f32 	%f880, %f877, %f877;
	mul.f32 	%f881, %f880, %f879;
	mul.f32 	%f882, %f881, %f881;
	mov.f32 	%f883, 0f3C4CAF63;
	mov.f32 	%f884, 0f3B18F0FE;
	fma.rn.f32 	%f885, %f884, %f882, %f883;
	mov.f32 	%f886, 0f3DAAAABD;
	fma.rn.f32 	%f887, %f885, %f882, %f886;
	mul.rn.f32 	%f888, %f887, %f882;
	mul.rn.f32 	%f889, %f888, %f881;
	sub.f32 	%f890, %f877, %f881;
	add.f32 	%f891, %f890, %f890;
	neg.f32 	%f892, %f881;
	fma.rn.f32 	%f893, %f892, %f877, %f891;
	mul.rn.f32 	%f894, %f879, %f893;
	add.f32 	%f895, %f889, %f881;
	sub.f32 	%f896, %f881, %f895;
	add.f32 	%f897, %f889, %f896;
	add.f32 	%f898, %f894, %f897;
	add.f32 	%f899, %f895, %f898;
	sub.f32 	%f900, %f895, %f899;
	add.f32 	%f901, %f898, %f900;
	mov.f32 	%f902, 0f3F317200;
	mul.rn.f32 	%f903, %f875, %f902;
	mov.f32 	%f904, 0f35BFBE8E;
	mul.rn.f32 	%f905, %f875, %f904;
	add.f32 	%f906, %f903, %f899;
	sub.f32 	%f907, %f903, %f906;
	add.f32 	%f908, %f899, %f907;
	add.f32 	%f909, %f901, %f908;
	add.f32 	%f910, %f905, %f909;
	add.f32 	%f911, %f906, %f910;
	sub.f32 	%f912, %f906, %f911;
	add.f32 	%f913, %f910, %f912;
	mov.f32 	%f914, 0f3EE66666;
	mul.rn.f32 	%f915, %f914, %f911;
	neg.f32 	%f916, %f915;
	fma.rn.f32 	%f917, %f914, %f911, %f916;
	fma.rn.f32 	%f918, %f914, %f913, %f917;
	mov.f32 	%f919, 0f00000000;
	fma.rn.f32 	%f920, %f919, %f911, %f918;
	add.rn.f32 	%f921, %f915, %f920;
	neg.f32 	%f922, %f921;
	add.rn.f32 	%f923, %f915, %f922;
	add.rn.f32 	%f924, %f923, %f920;
	mov.b32 	%r375, %f921;
	setp.eq.s32 	%p105, %r375, 1118925336;
	add.s32 	%r376, %r375, -1;
	mov.b32 	%f925, %r376;
	add.f32 	%f926, %f924, 0f37000000;
	selp.f32 	%f289, %f926, %f924, %p105;
	selp.f32 	%f927, %f925, %f921, %p105;
	mov.f32 	%f928, 0f3FB8AA3B;
	mul.rn.f32 	%f929, %f927, %f928;
	cvt.rzi.f32.f32 	%f930, %f929;
	abs.f32 	%f931, %f930;
	setp.gt.f32 	%p106, %f931, 0f42FC0000;
	mov.b32 	%r377, %f930;
	and.b32  	%r378, %r377, -2147483648;
	or.b32  	%r379, %r378, 1123811328;
	mov.b32 	%f932, %r379;
	selp.f32 	%f933, %f932, %f930, %p106;
	mov.f32 	%f934, 0fBF317218;
	fma.rn.f32 	%f935, %f933, %f934, %f927;
	mov.f32 	%f936, 0f3102E308;
	fma.rn.f32 	%f937, %f933, %f936, %f935;
	mul.f32 	%f938, %f937, 0f3FB8AA3B;
	add.f32 	%f939, %f933, 0f4B40007F;
	mov.b32 	%r380, %f939;
	shl.b32 	%r381, %r380, 23;
	mov.b32 	%f940, %r381;
	ex2.approx.ftz.f32 	%f941, %f938;
	mul.f32 	%f290, %f941, %f940;
	setp.eq.f32 	%p107, %f290, 0f7F800000;
	mov.f32 	%f1562, 0f7F800000;
	@%p107 bra 	$L__BB0_85;

	fma.rn.f32 	%f1562, %f290, %f289, %f290;

$L__BB0_85:
	setp.lt.f32 	%p108, %f272, 0f00000000;
	and.pred  	%p5, %p108, %p94;
	setp.eq.f32 	%p110, %f272, 0f00000000;
	@%p110 bra 	$L__BB0_89;
	bra.uni 	$L__BB0_86;

$L__BB0_89:
	add.f32 	%f946, %f272, %f272;
	selp.f32 	%f1564, %f946, 0f00000000, %p94;
	bra.uni 	$L__BB0_90;

$L__BB0_86:
	mov.b32 	%r382, %f1562;
	xor.b32  	%r383, %r382, -2147483648;
	mov.b32 	%f942, %r383;
	selp.f32 	%f1564, %f942, %f1562, %p5;
	setp.geu.f32 	%p111, %f272, 0f00000000;
	@%p111 bra 	$L__BB0_90;

	mov.f32 	%f943, 0f3EE66666;
	cvt.rzi.f32.f32 	%f944, %f943;
	setp.eq.f32 	%p112, %f944, 0f3EE66666;
	@%p112 bra 	$L__BB0_90;

	mov.f32 	%f1564, 0f7FFFFFFF;

$L__BB0_90:
	add.f32 	%f947, %f288, 0f3EE66666;
	mov.b32 	%r384, %f947;
	setp.lt.s32 	%p114, %r384, 2139095040;
	@%p114 bra 	$L__BB0_95;

	setp.gtu.f32 	%p115, %f288, 0f7F800000;
	@%p115 bra 	$L__BB0_94;
	bra.uni 	$L__BB0_92;

$L__BB0_94:
	add.f32 	%f1564, %f272, 0f3EE66666;
	bra.uni 	$L__BB0_95;

$L__BB0_92:
	setp.neu.f32 	%p116, %f288, 0f7F800000;
	@%p116 bra 	$L__BB0_95;

	selp.f32 	%f1564, 0fFF800000, 0f7F800000, %p5;

$L__BB0_95:
	setp.eq.f32 	%p117, %f272, 0f3F800000;
	selp.f32 	%f299, 0f3F800000, %f1564, %p117;
	abs.f32 	%f300, %f274;
	setp.lt.f32 	%p118, %f300, 0f00800000;
	mul.f32 	%f949, %f300, 0f4B800000;
	selp.f32 	%f950, %f949, %f300, %p118;
	selp.f32 	%f951, 0fC3170000, 0fC2FE0000, %p118;
	mov.b32 	%r385, %f950;
	and.b32  	%r386, %r385, 8388607;
	or.b32  	%r387, %r386, 1065353216;
	mov.b32 	%f952, %r387;
	shr.u32 	%r388, %r385, 23;
	cvt.rn.f32.u32 	%f953, %r388;
	add.f32 	%f954, %f951, %f953;
	setp.gt.f32 	%p119, %f952, 0f3FB504F3;
	mul.f32 	%f955, %f952, 0f3F000000;
	add.f32 	%f956, %f954, 0f3F800000;
	selp.f32 	%f957, %f956, %f954, %p119;
	selp.f32 	%f958, %f955, %f952, %p119;
	add.f32 	%f959, %f958, 0fBF800000;
	add.f32 	%f960, %f958, 0f3F800000;
	rcp.approx.ftz.f32 	%f961, %f960;
	add.f32 	%f962, %f959, %f959;
	mul.f32 	%f963, %f962, %f961;
	mul.f32 	%f964, %f963, %f963;
	mov.f32 	%f965, 0f3C4CAF63;
	mov.f32 	%f966, 0f3B18F0FE;
	fma.rn.f32 	%f967, %f966, %f964, %f965;
	mov.f32 	%f968, 0f3DAAAABD;
	fma.rn.f32 	%f969, %f967, %f964, %f968;
	mul.rn.f32 	%f970, %f969, %f964;
	mul.rn.f32 	%f971, %f970, %f963;
	sub.f32 	%f972, %f959, %f963;
	add.f32 	%f973, %f972, %f972;
	neg.f32 	%f974, %f963;
	fma.rn.f32 	%f975, %f974, %f959, %f973;
	mul.rn.f32 	%f976, %f961, %f975;
	add.f32 	%f977, %f971, %f963;
	sub.f32 	%f978, %f963, %f977;
	add.f32 	%f979, %f971, %f978;
	add.f32 	%f980, %f976, %f979;
	add.f32 	%f981, %f977, %f980;
	sub.f32 	%f982, %f977, %f981;
	add.f32 	%f983, %f980, %f982;
	mov.f32 	%f984, 0f3F317200;
	mul.rn.f32 	%f985, %f957, %f984;
	mov.f32 	%f986, 0f35BFBE8E;
	mul.rn.f32 	%f987, %f957, %f986;
	add.f32 	%f988, %f985, %f981;
	sub.f32 	%f989, %f985, %f988;
	add.f32 	%f990, %f981, %f989;
	add.f32 	%f991, %f983, %f990;
	add.f32 	%f992, %f987, %f991;
	add.f32 	%f993, %f988, %f992;
	sub.f32 	%f994, %f988, %f993;
	add.f32 	%f995, %f992, %f994;
	mov.f32 	%f996, 0f3EE66666;
	mul.rn.f32 	%f997, %f996, %f993;
	neg.f32 	%f998, %f997;
	fma.rn.f32 	%f999, %f996, %f993, %f998;
	fma.rn.f32 	%f1000, %f996, %f995, %f999;
	mov.f32 	%f1001, 0f00000000;
	fma.rn.f32 	%f1002, %f1001, %f993, %f1000;
	add.rn.f32 	%f1003, %f997, %f1002;
	neg.f32 	%f1004, %f1003;
	add.rn.f32 	%f1005, %f997, %f1004;
	add.rn.f32 	%f1006, %f1005, %f1002;
	mov.b32 	%r389, %f1003;
	setp.eq.s32 	%p120, %r389, 1118925336;
	add.s32 	%r390, %r389, -1;
	mov.b32 	%f1007, %r390;
	add.f32 	%f1008, %f1006, 0f37000000;
	selp.f32 	%f301, %f1008, %f1006, %p120;
	selp.f32 	%f1009, %f1007, %f1003, %p120;
	mov.f32 	%f1010, 0f3FB8AA3B;
	mul.rn.f32 	%f1011, %f1009, %f1010;
	cvt.rzi.f32.f32 	%f1012, %f1011;
	abs.f32 	%f1013, %f1012;
	setp.gt.f32 	%p121, %f1013, 0f42FC0000;
	mov.b32 	%r391, %f1012;
	and.b32  	%r392, %r391, -2147483648;
	or.b32  	%r393, %r392, 1123811328;
	mov.b32 	%f1014, %r393;
	selp.f32 	%f1015, %f1014, %f1012, %p121;
	mov.f32 	%f1016, 0fBF317218;
	fma.rn.f32 	%f1017, %f1015, %f1016, %f1009;
	mov.f32 	%f1018, 0f3102E308;
	fma.rn.f32 	%f1019, %f1015, %f1018, %f1017;
	mul.f32 	%f1020, %f1019, 0f3FB8AA3B;
	add.f32 	%f1021, %f1015, 0f4B40007F;
	mov.b32 	%r394, %f1021;
	shl.b32 	%r395, %r394, 23;
	mov.b32 	%f1022, %r395;
	ex2.approx.ftz.f32 	%f1023, %f1020;
	mul.f32 	%f302, %f1023, %f1022;
	setp.eq.f32 	%p122, %f302, 0f7F800000;
	mov.f32 	%f1565, 0f7F800000;
	@%p122 bra 	$L__BB0_97;

	fma.rn.f32 	%f1565, %f302, %f301, %f302;

$L__BB0_97:
	setp.lt.f32 	%p123, %f274, 0f00000000;
	and.pred  	%p6, %p123, %p94;
	setp.eq.f32 	%p125, %f274, 0f00000000;
	@%p125 bra 	$L__BB0_101;
	bra.uni 	$L__BB0_98;

$L__BB0_101:
	add.f32 	%f1028, %f274, %f274;
	selp.f32 	%f1567, %f1028, 0f00000000, %p94;
	bra.uni 	$L__BB0_102;

$L__BB0_98:
	mov.b32 	%r396, %f1565;
	xor.b32  	%r397, %r396, -2147483648;
	mov.b32 	%f1024, %r397;
	selp.f32 	%f1567, %f1024, %f1565, %p6;
	setp.geu.f32 	%p126, %f274, 0f00000000;
	@%p126 bra 	$L__BB0_102;

	mov.f32 	%f1025, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1026, %f1025;
	setp.eq.f32 	%p127, %f1026, 0f3EE66666;
	@%p127 bra 	$L__BB0_102;

	mov.f32 	%f1567, 0f7FFFFFFF;

$L__BB0_102:
	add.f32 	%f1029, %f300, 0f3EE66666;
	mov.b32 	%r398, %f1029;
	setp.lt.s32 	%p129, %r398, 2139095040;
	@%p129 bra 	$L__BB0_107;

	setp.gtu.f32 	%p130, %f300, 0f7F800000;
	@%p130 bra 	$L__BB0_106;
	bra.uni 	$L__BB0_104;

$L__BB0_106:
	add.f32 	%f1567, %f274, 0f3EE66666;
	bra.uni 	$L__BB0_107;

$L__BB0_104:
	setp.neu.f32 	%p131, %f300, 0f7F800000;
	@%p131 bra 	$L__BB0_107;

	selp.f32 	%f1567, 0fFF800000, 0f7F800000, %p6;

$L__BB0_107:
	setp.eq.f32 	%p132, %f274, 0f3F800000;
	mov.f32 	%f1031, 0f3F800000;
	selp.f32 	%f1032, 0f3F800000, %f1567, %p132;
	ld.const.u64 	%rd79, [params+144];
	cvta.to.global.u64 	%rd21, %rd79;
	ld.const.u32 	%r399, [params+136];
	mad.lo.s32 	%r400, %r399, %r8, %r7;
	cvt.u64.u32 	%rd22, %r400;
	min.f32 	%f1033, %f287, %f1031;
	mov.f32 	%f1034, 0f00000000;
	max.f32 	%f311, %f1034, %f1033;
	min.f32 	%f1035, %f299, %f1031;
	max.f32 	%f312, %f1034, %f1035;
	min.f32 	%f1036, %f1032, %f1031;
	max.f32 	%f313, %f1034, %f1036;
	mov.f32 	%f1037, 0f3E555555;
	cvt.rzi.f32.f32 	%f1038, %f1037;
	add.f32 	%f1039, %f1038, %f1038;
	mov.f32 	%f1040, 0f3ED55555;
	sub.f32 	%f1041, %f1040, %f1039;
	abs.f32 	%f314, %f1041;
	abs.f32 	%f315, %f311;
	setp.lt.f32 	%p133, %f315, 0f00800000;
	mul.f32 	%f1042, %f315, 0f4B800000;
	selp.f32 	%f1043, %f1042, %f315, %p133;
	selp.f32 	%f1044, 0fC3170000, 0fC2FE0000, %p133;
	mov.b32 	%r401, %f1043;
	and.b32  	%r402, %r401, 8388607;
	or.b32  	%r403, %r402, 1065353216;
	mov.b32 	%f1045, %r403;
	shr.u32 	%r404, %r401, 23;
	cvt.rn.f32.u32 	%f1046, %r404;
	add.f32 	%f1047, %f1044, %f1046;
	setp.gt.f32 	%p134, %f1045, 0f3FB504F3;
	mul.f32 	%f1048, %f1045, 0f3F000000;
	add.f32 	%f1049, %f1047, 0f3F800000;
	selp.f32 	%f1050, %f1049, %f1047, %p134;
	selp.f32 	%f1051, %f1048, %f1045, %p134;
	add.f32 	%f1052, %f1051, 0fBF800000;
	add.f32 	%f1053, %f1051, 0f3F800000;
	rcp.approx.ftz.f32 	%f1054, %f1053;
	add.f32 	%f1055, %f1052, %f1052;
	mul.f32 	%f1056, %f1055, %f1054;
	mul.f32 	%f1057, %f1056, %f1056;
	mov.f32 	%f1058, 0f3C4CAF63;
	mov.f32 	%f1059, 0f3B18F0FE;
	fma.rn.f32 	%f1060, %f1059, %f1057, %f1058;
	mov.f32 	%f1061, 0f3DAAAABD;
	fma.rn.f32 	%f1062, %f1060, %f1057, %f1061;
	mul.rn.f32 	%f1063, %f1062, %f1057;
	mul.rn.f32 	%f1064, %f1063, %f1056;
	sub.f32 	%f1065, %f1052, %f1056;
	add.f32 	%f1066, %f1065, %f1065;
	neg.f32 	%f1067, %f1056;
	fma.rn.f32 	%f1068, %f1067, %f1052, %f1066;
	mul.rn.f32 	%f1069, %f1054, %f1068;
	add.f32 	%f1070, %f1064, %f1056;
	sub.f32 	%f1071, %f1056, %f1070;
	add.f32 	%f1072, %f1064, %f1071;
	add.f32 	%f1073, %f1069, %f1072;
	add.f32 	%f1074, %f1070, %f1073;
	sub.f32 	%f1075, %f1070, %f1074;
	add.f32 	%f1076, %f1073, %f1075;
	mov.f32 	%f1077, 0f3F317200;
	mul.rn.f32 	%f1078, %f1050, %f1077;
	mov.f32 	%f1079, 0f35BFBE8E;
	mul.rn.f32 	%f1080, %f1050, %f1079;
	add.f32 	%f1081, %f1078, %f1074;
	sub.f32 	%f1082, %f1078, %f1081;
	add.f32 	%f1083, %f1074, %f1082;
	add.f32 	%f1084, %f1076, %f1083;
	add.f32 	%f1085, %f1080, %f1084;
	add.f32 	%f1086, %f1081, %f1085;
	sub.f32 	%f1087, %f1081, %f1086;
	add.f32 	%f1088, %f1085, %f1087;
	mul.rn.f32 	%f1089, %f1040, %f1086;
	neg.f32 	%f1090, %f1089;
	fma.rn.f32 	%f1091, %f1040, %f1086, %f1090;
	fma.rn.f32 	%f1092, %f1040, %f1088, %f1091;
	fma.rn.f32 	%f1093, %f1034, %f1086, %f1092;
	add.rn.f32 	%f1094, %f1089, %f1093;
	neg.f32 	%f1095, %f1094;
	add.rn.f32 	%f1096, %f1089, %f1095;
	add.rn.f32 	%f1097, %f1096, %f1093;
	mov.b32 	%r405, %f1094;
	setp.eq.s32 	%p135, %r405, 1118925336;
	add.s32 	%r406, %r405, -1;
	mov.b32 	%f1098, %r406;
	add.f32 	%f1099, %f1097, 0f37000000;
	selp.f32 	%f316, %f1099, %f1097, %p135;
	selp.f32 	%f1100, %f1098, %f1094, %p135;
	mov.f32 	%f1101, 0f3FB8AA3B;
	mul.rn.f32 	%f1102, %f1100, %f1101;
	cvt.rzi.f32.f32 	%f1103, %f1102;
	abs.f32 	%f1104, %f1103;
	setp.gt.f32 	%p136, %f1104, 0f42FC0000;
	mov.b32 	%r407, %f1103;
	and.b32  	%r408, %r407, -2147483648;
	or.b32  	%r409, %r408, 1123811328;
	mov.b32 	%f1105, %r409;
	selp.f32 	%f1106, %f1105, %f1103, %p136;
	mov.f32 	%f1107, 0fBF317218;
	fma.rn.f32 	%f1108, %f1106, %f1107, %f1100;
	mov.f32 	%f1109, 0f3102E308;
	fma.rn.f32 	%f1110, %f1106, %f1109, %f1108;
	mul.f32 	%f1111, %f1110, 0f3FB8AA3B;
	add.f32 	%f1112, %f1106, 0f4B40007F;
	mov.b32 	%r410, %f1112;
	shl.b32 	%r411, %r410, 23;
	mov.b32 	%f1113, %r411;
	ex2.approx.ftz.f32 	%f1114, %f1111;
	mul.f32 	%f317, %f1114, %f1113;
	setp.eq.f32 	%p137, %f317, 0f7F800000;
	mov.f32 	%f1568, 0f7F800000;
	@%p137 bra 	$L__BB0_109;

	fma.rn.f32 	%f1568, %f317, %f316, %f317;

$L__BB0_109:
	setp.lt.f32 	%p138, %f311, 0f00000000;
	setp.eq.f32 	%p139, %f314, 0f3F800000;
	and.pred  	%p7, %p138, %p139;
	setp.eq.f32 	%p140, %f311, 0f00000000;
	@%p140 bra 	$L__BB0_113;
	bra.uni 	$L__BB0_110;

$L__BB0_113:
	add.f32 	%f1119, %f311, %f311;
	selp.f32 	%f1570, %f1119, 0f00000000, %p139;
	bra.uni 	$L__BB0_114;

$L__BB0_110:
	mov.b32 	%r412, %f1568;
	xor.b32  	%r413, %r412, -2147483648;
	mov.b32 	%f1115, %r413;
	selp.f32 	%f1570, %f1115, %f1568, %p7;
	setp.geu.f32 	%p141, %f311, 0f00000000;
	@%p141 bra 	$L__BB0_114;

	mov.f32 	%f1116, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1117, %f1116;
	setp.eq.f32 	%p142, %f1117, 0f3ED55555;
	@%p142 bra 	$L__BB0_114;

	mov.f32 	%f1570, 0f7FFFFFFF;

$L__BB0_114:
	add.f32 	%f1120, %f315, 0f3ED55555;
	mov.b32 	%r414, %f1120;
	setp.lt.s32 	%p144, %r414, 2139095040;
	@%p144 bra 	$L__BB0_119;

	setp.gtu.f32 	%p145, %f315, 0f7F800000;
	@%p145 bra 	$L__BB0_118;
	bra.uni 	$L__BB0_116;

$L__BB0_118:
	add.f32 	%f1570, %f311, 0f3ED55555;
	bra.uni 	$L__BB0_119;

$L__BB0_116:
	setp.neu.f32 	%p146, %f315, 0f7F800000;
	@%p146 bra 	$L__BB0_119;

	selp.f32 	%f1570, 0fFF800000, 0f7F800000, %p7;

$L__BB0_119:
	abs.f32 	%f326, %f312;
	setp.lt.f32 	%p147, %f326, 0f00800000;
	mul.f32 	%f1122, %f326, 0f4B800000;
	selp.f32 	%f1123, %f1122, %f326, %p147;
	selp.f32 	%f1124, 0fC3170000, 0fC2FE0000, %p147;
	mov.b32 	%r415, %f1123;
	and.b32  	%r416, %r415, 8388607;
	or.b32  	%r417, %r416, 1065353216;
	mov.b32 	%f1125, %r417;
	shr.u32 	%r418, %r415, 23;
	cvt.rn.f32.u32 	%f1126, %r418;
	add.f32 	%f1127, %f1124, %f1126;
	setp.gt.f32 	%p148, %f1125, 0f3FB504F3;
	mul.f32 	%f1128, %f1125, 0f3F000000;
	add.f32 	%f1129, %f1127, 0f3F800000;
	selp.f32 	%f1130, %f1129, %f1127, %p148;
	selp.f32 	%f1131, %f1128, %f1125, %p148;
	add.f32 	%f1132, %f1131, 0fBF800000;
	add.f32 	%f1133, %f1131, 0f3F800000;
	rcp.approx.ftz.f32 	%f1134, %f1133;
	add.f32 	%f1135, %f1132, %f1132;
	mul.f32 	%f1136, %f1135, %f1134;
	mul.f32 	%f1137, %f1136, %f1136;
	mov.f32 	%f1138, 0f3C4CAF63;
	mov.f32 	%f1139, 0f3B18F0FE;
	fma.rn.f32 	%f1140, %f1139, %f1137, %f1138;
	mov.f32 	%f1141, 0f3DAAAABD;
	fma.rn.f32 	%f1142, %f1140, %f1137, %f1141;
	mul.rn.f32 	%f1143, %f1142, %f1137;
	mul.rn.f32 	%f1144, %f1143, %f1136;
	sub.f32 	%f1145, %f1132, %f1136;
	add.f32 	%f1146, %f1145, %f1145;
	neg.f32 	%f1147, %f1136;
	fma.rn.f32 	%f1148, %f1147, %f1132, %f1146;
	mul.rn.f32 	%f1149, %f1134, %f1148;
	add.f32 	%f1150, %f1144, %f1136;
	sub.f32 	%f1151, %f1136, %f1150;
	add.f32 	%f1152, %f1144, %f1151;
	add.f32 	%f1153, %f1149, %f1152;
	add.f32 	%f1154, %f1150, %f1153;
	sub.f32 	%f1155, %f1150, %f1154;
	add.f32 	%f1156, %f1153, %f1155;
	mov.f32 	%f1157, 0f3F317200;
	mul.rn.f32 	%f1158, %f1130, %f1157;
	mov.f32 	%f1159, 0f35BFBE8E;
	mul.rn.f32 	%f1160, %f1130, %f1159;
	add.f32 	%f1161, %f1158, %f1154;
	sub.f32 	%f1162, %f1158, %f1161;
	add.f32 	%f1163, %f1154, %f1162;
	add.f32 	%f1164, %f1156, %f1163;
	add.f32 	%f1165, %f1160, %f1164;
	add.f32 	%f1166, %f1161, %f1165;
	sub.f32 	%f1167, %f1161, %f1166;
	add.f32 	%f1168, %f1165, %f1167;
	mov.f32 	%f1169, 0f3ED55555;
	mul.rn.f32 	%f1170, %f1169, %f1166;
	neg.f32 	%f1171, %f1170;
	fma.rn.f32 	%f1172, %f1169, %f1166, %f1171;
	fma.rn.f32 	%f1173, %f1169, %f1168, %f1172;
	mov.f32 	%f1174, 0f00000000;
	fma.rn.f32 	%f1175, %f1174, %f1166, %f1173;
	add.rn.f32 	%f1176, %f1170, %f1175;
	neg.f32 	%f1177, %f1176;
	add.rn.f32 	%f1178, %f1170, %f1177;
	add.rn.f32 	%f1179, %f1178, %f1175;
	mov.b32 	%r419, %f1176;
	setp.eq.s32 	%p149, %r419, 1118925336;
	add.s32 	%r420, %r419, -1;
	mov.b32 	%f1180, %r420;
	add.f32 	%f1181, %f1179, 0f37000000;
	selp.f32 	%f327, %f1181, %f1179, %p149;
	selp.f32 	%f1182, %f1180, %f1176, %p149;
	mov.f32 	%f1183, 0f3FB8AA3B;
	mul.rn.f32 	%f1184, %f1182, %f1183;
	cvt.rzi.f32.f32 	%f1185, %f1184;
	abs.f32 	%f1186, %f1185;
	setp.gt.f32 	%p150, %f1186, 0f42FC0000;
	mov.b32 	%r421, %f1185;
	and.b32  	%r422, %r421, -2147483648;
	or.b32  	%r423, %r422, 1123811328;
	mov.b32 	%f1187, %r423;
	selp.f32 	%f1188, %f1187, %f1185, %p150;
	mov.f32 	%f1189, 0fBF317218;
	fma.rn.f32 	%f1190, %f1188, %f1189, %f1182;
	mov.f32 	%f1191, 0f3102E308;
	fma.rn.f32 	%f1192, %f1188, %f1191, %f1190;
	mul.f32 	%f1193, %f1192, 0f3FB8AA3B;
	add.f32 	%f1194, %f1188, 0f4B40007F;
	mov.b32 	%r424, %f1194;
	shl.b32 	%r425, %r424, 23;
	mov.b32 	%f1195, %r425;
	ex2.approx.ftz.f32 	%f1196, %f1193;
	mul.f32 	%f328, %f1196, %f1195;
	setp.eq.f32 	%p151, %f328, 0f7F800000;
	mov.f32 	%f1571, 0f7F800000;
	@%p151 bra 	$L__BB0_121;

	fma.rn.f32 	%f1571, %f328, %f327, %f328;

$L__BB0_121:
	setp.lt.f32 	%p152, %f312, 0f00000000;
	and.pred  	%p8, %p152, %p139;
	setp.eq.f32 	%p154, %f312, 0f00000000;
	@%p154 bra 	$L__BB0_125;
	bra.uni 	$L__BB0_122;

$L__BB0_125:
	add.f32 	%f1201, %f312, %f312;
	selp.f32 	%f1573, %f1201, 0f00000000, %p139;
	bra.uni 	$L__BB0_126;

$L__BB0_122:
	mov.b32 	%r426, %f1571;
	xor.b32  	%r427, %r426, -2147483648;
	mov.b32 	%f1197, %r427;
	selp.f32 	%f1573, %f1197, %f1571, %p8;
	setp.geu.f32 	%p155, %f312, 0f00000000;
	@%p155 bra 	$L__BB0_126;

	mov.f32 	%f1198, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1199, %f1198;
	setp.eq.f32 	%p156, %f1199, 0f3ED55555;
	@%p156 bra 	$L__BB0_126;

	mov.f32 	%f1573, 0f7FFFFFFF;

$L__BB0_126:
	add.f32 	%f1202, %f326, 0f3ED55555;
	mov.b32 	%r428, %f1202;
	setp.lt.s32 	%p158, %r428, 2139095040;
	@%p158 bra 	$L__BB0_131;

	setp.gtu.f32 	%p159, %f326, 0f7F800000;
	@%p159 bra 	$L__BB0_130;
	bra.uni 	$L__BB0_128;

$L__BB0_130:
	add.f32 	%f1573, %f312, 0f3ED55555;
	bra.uni 	$L__BB0_131;

$L__BB0_128:
	setp.neu.f32 	%p160, %f326, 0f7F800000;
	@%p160 bra 	$L__BB0_131;

	selp.f32 	%f1573, 0fFF800000, 0f7F800000, %p8;

$L__BB0_131:
	abs.f32 	%f337, %f313;
	setp.lt.f32 	%p161, %f337, 0f00800000;
	mul.f32 	%f1204, %f337, 0f4B800000;
	selp.f32 	%f1205, %f1204, %f337, %p161;
	selp.f32 	%f1206, 0fC3170000, 0fC2FE0000, %p161;
	mov.b32 	%r429, %f1205;
	and.b32  	%r430, %r429, 8388607;
	or.b32  	%r431, %r430, 1065353216;
	mov.b32 	%f1207, %r431;
	shr.u32 	%r432, %r429, 23;
	cvt.rn.f32.u32 	%f1208, %r432;
	add.f32 	%f1209, %f1206, %f1208;
	setp.gt.f32 	%p162, %f1207, 0f3FB504F3;
	mul.f32 	%f1210, %f1207, 0f3F000000;
	add.f32 	%f1211, %f1209, 0f3F800000;
	selp.f32 	%f1212, %f1211, %f1209, %p162;
	selp.f32 	%f1213, %f1210, %f1207, %p162;
	add.f32 	%f1214, %f1213, 0fBF800000;
	add.f32 	%f1215, %f1213, 0f3F800000;
	rcp.approx.ftz.f32 	%f1216, %f1215;
	add.f32 	%f1217, %f1214, %f1214;
	mul.f32 	%f1218, %f1217, %f1216;
	mul.f32 	%f1219, %f1218, %f1218;
	mov.f32 	%f1220, 0f3C4CAF63;
	mov.f32 	%f1221, 0f3B18F0FE;
	fma.rn.f32 	%f1222, %f1221, %f1219, %f1220;
	mov.f32 	%f1223, 0f3DAAAABD;
	fma.rn.f32 	%f1224, %f1222, %f1219, %f1223;
	mul.rn.f32 	%f1225, %f1224, %f1219;
	mul.rn.f32 	%f1226, %f1225, %f1218;
	sub.f32 	%f1227, %f1214, %f1218;
	add.f32 	%f1228, %f1227, %f1227;
	neg.f32 	%f1229, %f1218;
	fma.rn.f32 	%f1230, %f1229, %f1214, %f1228;
	mul.rn.f32 	%f1231, %f1216, %f1230;
	add.f32 	%f1232, %f1226, %f1218;
	sub.f32 	%f1233, %f1218, %f1232;
	add.f32 	%f1234, %f1226, %f1233;
	add.f32 	%f1235, %f1231, %f1234;
	add.f32 	%f1236, %f1232, %f1235;
	sub.f32 	%f1237, %f1232, %f1236;
	add.f32 	%f1238, %f1235, %f1237;
	mov.f32 	%f1239, 0f3F317200;
	mul.rn.f32 	%f1240, %f1212, %f1239;
	mov.f32 	%f1241, 0f35BFBE8E;
	mul.rn.f32 	%f1242, %f1212, %f1241;
	add.f32 	%f1243, %f1240, %f1236;
	sub.f32 	%f1244, %f1240, %f1243;
	add.f32 	%f1245, %f1236, %f1244;
	add.f32 	%f1246, %f1238, %f1245;
	add.f32 	%f1247, %f1242, %f1246;
	add.f32 	%f1248, %f1243, %f1247;
	sub.f32 	%f1249, %f1243, %f1248;
	add.f32 	%f1250, %f1247, %f1249;
	mov.f32 	%f1251, 0f3ED55555;
	mul.rn.f32 	%f1252, %f1251, %f1248;
	neg.f32 	%f1253, %f1252;
	fma.rn.f32 	%f1254, %f1251, %f1248, %f1253;
	fma.rn.f32 	%f1255, %f1251, %f1250, %f1254;
	mov.f32 	%f1256, 0f00000000;
	fma.rn.f32 	%f1257, %f1256, %f1248, %f1255;
	add.rn.f32 	%f1258, %f1252, %f1257;
	neg.f32 	%f1259, %f1258;
	add.rn.f32 	%f1260, %f1252, %f1259;
	add.rn.f32 	%f1261, %f1260, %f1257;
	mov.b32 	%r433, %f1258;
	setp.eq.s32 	%p163, %r433, 1118925336;
	add.s32 	%r434, %r433, -1;
	mov.b32 	%f1262, %r434;
	add.f32 	%f1263, %f1261, 0f37000000;
	selp.f32 	%f338, %f1263, %f1261, %p163;
	selp.f32 	%f1264, %f1262, %f1258, %p163;
	mov.f32 	%f1265, 0f3FB8AA3B;
	mul.rn.f32 	%f1266, %f1264, %f1265;
	cvt.rzi.f32.f32 	%f1267, %f1266;
	abs.f32 	%f1268, %f1267;
	setp.gt.f32 	%p164, %f1268, 0f42FC0000;
	mov.b32 	%r435, %f1267;
	and.b32  	%r436, %r435, -2147483648;
	or.b32  	%r437, %r436, 1123811328;
	mov.b32 	%f1269, %r437;
	selp.f32 	%f1270, %f1269, %f1267, %p164;
	mov.f32 	%f1271, 0fBF317218;
	fma.rn.f32 	%f1272, %f1270, %f1271, %f1264;
	mov.f32 	%f1273, 0f3102E308;
	fma.rn.f32 	%f1274, %f1270, %f1273, %f1272;
	mul.f32 	%f1275, %f1274, 0f3FB8AA3B;
	add.f32 	%f1276, %f1270, 0f4B40007F;
	mov.b32 	%r438, %f1276;
	shl.b32 	%r439, %r438, 23;
	mov.b32 	%f1277, %r439;
	ex2.approx.ftz.f32 	%f1278, %f1275;
	mul.f32 	%f339, %f1278, %f1277;
	setp.eq.f32 	%p165, %f339, 0f7F800000;
	mov.f32 	%f1574, 0f7F800000;
	@%p165 bra 	$L__BB0_133;

	fma.rn.f32 	%f1574, %f339, %f338, %f339;

$L__BB0_133:
	setp.lt.f32 	%p166, %f313, 0f00000000;
	and.pred  	%p9, %p166, %p139;
	setp.eq.f32 	%p168, %f313, 0f00000000;
	@%p168 bra 	$L__BB0_137;
	bra.uni 	$L__BB0_134;

$L__BB0_137:
	add.f32 	%f1283, %f313, %f313;
	selp.f32 	%f1576, %f1283, 0f00000000, %p139;
	bra.uni 	$L__BB0_138;

$L__BB0_134:
	mov.b32 	%r440, %f1574;
	xor.b32  	%r441, %r440, -2147483648;
	mov.b32 	%f1279, %r441;
	selp.f32 	%f1576, %f1279, %f1574, %p9;
	setp.geu.f32 	%p169, %f313, 0f00000000;
	@%p169 bra 	$L__BB0_138;

	mov.f32 	%f1280, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1281, %f1280;
	setp.eq.f32 	%p170, %f1281, 0f3ED55555;
	@%p170 bra 	$L__BB0_138;

	mov.f32 	%f1576, 0f7FFFFFFF;

$L__BB0_138:
	add.f32 	%f1284, %f337, 0f3ED55555;
	mov.b32 	%r442, %f1284;
	setp.lt.s32 	%p172, %r442, 2139095040;
	@%p172 bra 	$L__BB0_143;

	setp.gtu.f32 	%p173, %f337, 0f7F800000;
	@%p173 bra 	$L__BB0_142;
	bra.uni 	$L__BB0_140;

$L__BB0_142:
	add.f32 	%f1576, %f313, 0f3ED55555;
	bra.uni 	$L__BB0_143;

$L__BB0_140:
	setp.neu.f32 	%p174, %f337, 0f7F800000;
	@%p174 bra 	$L__BB0_143;

	selp.f32 	%f1576, 0fFF800000, 0f7F800000, %p9;

$L__BB0_143:
	fma.rn.f32 	%f1285, %f1570, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p175, %f311, 0f3F800000;
	mov.f32 	%f1286, 0f3F800000;
	selp.f32 	%f1287, 0f3F7FFFFF, %f1285, %p175;
	mul.f32 	%f1288, %f311, 0f414EB852;
	setp.lt.f32 	%p176, %f311, 0f3B4D2E1C;
	selp.f32 	%f1289, %f1288, %f1287, %p176;
	fma.rn.f32 	%f1290, %f1573, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p177, %f312, 0f3F800000;
	selp.f32 	%f1291, 0f3F7FFFFF, %f1290, %p177;
	mul.f32 	%f1292, %f312, 0f414EB852;
	setp.lt.f32 	%p178, %f312, 0f3B4D2E1C;
	selp.f32 	%f1293, %f1292, %f1291, %p178;
	fma.rn.f32 	%f1294, %f1576, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p179, %f313, 0f3F800000;
	selp.f32 	%f1295, 0f3F7FFFFF, %f1294, %p179;
	mul.f32 	%f1296, %f313, 0f414EB852;
	setp.lt.f32 	%p180, %f313, 0f3B4D2E1C;
	selp.f32 	%f1297, %f1296, %f1295, %p180;
	min.f32 	%f1298, %f1289, %f1286;
	mov.f32 	%f1299, 0f00000000;
	max.f32 	%f1300, %f1299, %f1298;
	mul.f32 	%f1301, %f1300, 0f43800000;
	cvt.rzi.u32.f32 	%r443, %f1301;
	min.u32 	%r444, %r443, 255;
	min.f32 	%f1302, %f1293, %f1286;
	max.f32 	%f1303, %f1299, %f1302;
	mul.f32 	%f1304, %f1303, 0f43800000;
	cvt.rzi.u32.f32 	%r445, %f1304;
	min.u32 	%r446, %r445, 255;
	min.f32 	%f1305, %f1297, %f1286;
	max.f32 	%f1306, %f1299, %f1305;
	mul.f32 	%f1307, %f1306, 0f43800000;
	cvt.rzi.u32.f32 	%r447, %f1307;
	min.u32 	%r448, %r447, 255;
	shl.b64 	%rd80, %rd22, 2;
	add.s64 	%rd81, %rd21, %rd80;
	cvt.u16.u32 	%rs18, %r448;
	cvt.u16.u32 	%rs19, %r446;
	cvt.u16.u32 	%rs20, %r444;
	mov.u16 	%rs21, 255;
	st.global.v4.u8 	[%rd81], {%rs20, %rs19, %rs18, %rs21};

$L__BB0_144:
	and.b32  	%r449, %r86, 4;
	setp.eq.s32 	%p181, %r449, 0;
	ld.const.u32 	%r495, [params+108];
	@%p181 bra 	$L__BB0_148;

	setp.eq.s32 	%p182, %r495, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r450, [params+216];
	mad.lo.s32 	%r451, %r450, %r8, %r7;
	mul.wide.u32 	%rd84, %r451, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p182 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs29, %rs30, %rs31, %rs32}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1308, %rs29;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1309, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1310, %rs31;}

	// end inline asm
	add.f32 	%f1311, %f271, %f1308;
	add.f32 	%f1312, %f272, %f1309;
	add.f32 	%f1313, %f274, %f1310;
	mov.f32 	%f1314, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1313;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f1312;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f1311;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1314;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs25, %rs26, %rs27, %rs28};
	bra.uni 	$L__BB0_148;

$L__BB0_147:
	mov.f32 	%f1318, 0f3F800000;
	mov.u32 	%r495, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1318;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f274;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f272;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f271;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs33, %rs34, %rs35, %rs36};

$L__BB0_148:
	selp.f32 	%f1319, 0f3F800000, 0f3E800000, %p198;
	mul.f32 	%f348, %f1319, %f1549;
	mul.f32 	%f349, %f1319, %f1550;
	mul.f32 	%f350, %f1319, %f1551;
	mul.f32 	%f351, %f1319, %f1546;
	mul.f32 	%f352, %f1319, %f1547;
	mul.f32 	%f353, %f1319, %f1548;
	mul.f32 	%f354, %f1319, %f1543;
	mul.f32 	%f355, %f1319, %f1544;
	mul.f32 	%f356, %f1319, %f1545;
	mul.f32 	%f357, %f1319, %f1540;
	mul.f32 	%f358, %f1319, %f1541;
	mul.f32 	%f359, %f1319, %f1542;
	mul.f32 	%f360, %f348, %f778;
	mul.f32 	%f361, %f349, %f779;
	mul.f32 	%f362, %f350, %f273;
	ld.const.u64 	%rd85, [params+256];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r453, [params+248];
	mad.lo.s32 	%r454, %r453, %r8, %r7;
	mul.wide.u32 	%rd87, %r454, 8;
	add.s64 	%rd24, %rd86, %rd87;
	setp.eq.s32 	%p183, %r495, 0;
	@%p183 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs44, %rs45, %rs46, %rs47}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1320, %rs44;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1321, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1322, %rs46;}

	// end inline asm
	add.f32 	%f1323, %f360, %f1320;
	add.f32 	%f1324, %f361, %f1321;
	add.f32 	%f1325, %f362, %f1322;
	mov.f32 	%f1326, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1325;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1324;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1323;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1326;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs40, %rs41, %rs42, %rs43};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1330, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1330;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f362;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f361;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f360;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs48, %rs49, %rs50, %rs51};

$L__BB0_151:
	mov.f32 	%f1331, 0f34000000;
	max.f32 	%f1332, %f348, %f1331;
	div.rn.f32 	%f1333, %f351, %f1332;
	max.f32 	%f1334, %f349, %f1331;
	div.rn.f32 	%f1335, %f352, %f1334;
	max.f32 	%f1336, %f350, %f1331;
	div.rn.f32 	%f1337, %f353, %f1336;
	fma.rn.f32 	%f363, %f1333, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f364, %f1335, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f365, %f1337, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1338, %f354, %f1332;
	div.rn.f32 	%f1339, %f355, %f1334;
	div.rn.f32 	%f1340, %f356, %f1336;
	fma.rn.f32 	%f366, %f1338, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f367, %f1339, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f368, %f1340, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1341, %f357, %f1332;
	div.rn.f32 	%f1342, %f358, %f1334;
	div.rn.f32 	%f1343, %f359, %f1336;
	fma.rn.f32 	%f369, %f1341, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f370, %f1342, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f371, %f1343, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd88, [params+272];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r455, [params+264];
	mad.lo.s32 	%r456, %r455, %r8, %r7;
	mul.wide.u32 	%rd90, %r456, 8;
	add.s64 	%rd25, %rd89, %rd90;
	@%p183 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs59, %rs60, %rs61, %rs62}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1344, %rs59;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1345, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1346, %rs61;}

	// end inline asm
	add.f32 	%f1347, %f363, %f1344;
	add.f32 	%f1348, %f364, %f1345;
	add.f32 	%f1349, %f365, %f1346;
	mov.f32 	%f1350, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1349;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1348;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1347;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1350;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs55, %rs56, %rs57, %rs58};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1354, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1354;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f365;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f364;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f363;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs63, %rs64, %rs65, %rs66};

$L__BB0_154:
	ld.const.u64 	%rd91, [params+288];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r457, [params+280];
	mad.lo.s32 	%r458, %r457, %r8, %r7;
	mul.wide.u32 	%rd93, %r458, 8;
	add.s64 	%rd26, %rd92, %rd93;
	@%p183 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1355, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1356, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1357, %rs76;}

	// end inline asm
	add.f32 	%f1358, %f366, %f1355;
	add.f32 	%f1359, %f367, %f1356;
	add.f32 	%f1360, %f368, %f1357;
	mov.f32 	%f1361, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1360;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1359;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1358;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1361;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1365, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1365;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f368;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f367;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f366;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_157:
	ld.const.u64 	%rd94, [params+304];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r459, [params+296];
	mad.lo.s32 	%r460, %r459, %r8, %r7;
	mul.wide.u32 	%rd96, %r460, 8;
	add.s64 	%rd27, %rd95, %rd96;
	@%p183 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1366, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1367, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1368, %rs91;}

	// end inline asm
	add.f32 	%f1369, %f369, %f1366;
	add.f32 	%f1370, %f370, %f1367;
	add.f32 	%f1371, %f371, %f1368;
	mov.f32 	%f1372, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1371;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1370;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1369;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1372;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_180;

$L__BB0_159:
	mov.f32 	%f1376, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1376;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f371;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f370;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f369;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_180:
	ret;

}