//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<207>;
	.reg .b16 	%rs<327>;
	.reg .f32 	%f<2052>;
	.reg .b32 	%r<487>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<179>;


	mov.u64 	%SPL, __local_depot0;
	cvta.local.u64 	%SP, %SPL;
	// begin inline asm
	call (%r59), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r60), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+616];
	ld.const.u32 	%r4, [params+540];
	shl.b32 	%r5, %r4, 1;
	ld.const.u64 	%rd43, [params+400];
	cvta.to.global.u64 	%rd44, %rd43;
	ld.const.u32 	%r65, [params+392];
	mad.lo.s32 	%r66, %r65, %r60, %r59;
	mul.wide.u32 	%rd45, %r66, 4;
	add.s64 	%rd1, %rd44, %rd45;
	ld.global.v2.u8 	{%rs7, %rs326}, [%rd1];
	or.b16  	%rs9, %rs7, %rs326;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p10, %rs10, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs325, [%rd1+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs325, [%rd1+2];
	setp.eq.s16 	%p11, %rs325, 0;
	mov.f32 	%f1805, 0f00000000;
	mov.u16 	%rs326, 0;
	mov.f32 	%f1806, %f1805;
	mov.f32 	%f1807, %f1805;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f556, %rs7;
	div.rn.f32 	%f557, %f556, 0f437F0000;
	fma.rn.f32 	%f558, %f557, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs326, 255;
	cvt.rn.f32.u16 	%f559, %rs13;
	div.rn.f32 	%f560, %f559, 0f437F0000;
	fma.rn.f32 	%f561, %f560, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f562, %rs325;
	div.rn.f32 	%f563, %f562, 0f437F0000;
	fma.rn.f32 	%f564, %f563, 0f40000000, 0fBF800000;
	mul.f32 	%f565, %f561, %f561;
	fma.rn.f32 	%f566, %f558, %f558, %f565;
	fma.rn.f32 	%f567, %f564, %f564, %f566;
	sqrt.rn.f32 	%f568, %f567;
	rcp.rn.f32 	%f569, %f568;
	mul.f32 	%f1807, %f569, %f564;
	mul.f32 	%f1806, %f569, %f561;
	mul.f32 	%f1805, %f558, %f569;

$L__BB0_4:
	ld.const.v2.u32 	{%r67, %r68}, [params];
	add.s32 	%r6, %r67, %r59;
	add.s32 	%r7, %r68, %r60;
	setp.eq.f32 	%p12, %f1805, 0f00000000;
	setp.eq.f32 	%p13, %f1806, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1807, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_173;
	bra.uni 	$L__BB0_5;

$L__BB0_173:
	ld.const.u32 	%r56, [params+104];
	and.b32  	%r442, %r56, 1;
	setp.eq.b32 	%p190, %r442, 1;
	mov.pred 	%p191, 0;
	xor.pred  	%p192, %p190, %p191;
	not.pred 	%p193, %p192;
	@%p193 bra 	$L__BB0_175;

	ld.const.u64 	%rd136, [params+144];
	cvta.to.global.u64 	%rd137, %rd136;
	ld.const.u32 	%r443, [params+136];
	mad.lo.s32 	%r444, %r443, %r7, %r6;
	mul.wide.u32 	%rd138, %r444, 4;
	add.s64 	%rd139, %rd137, %rd138;
	mov.u16 	%rs172, 0;
	st.global.v4.u8 	[%rd139], {%rs172, %rs172, %rs172, %rs172};

$L__BB0_175:
	and.b32  	%r445, %r56, 8;
	setp.eq.s32 	%p194, %r445, 0;
	@%p194 bra 	$L__BB0_177;

	ld.const.u64 	%rd140, [params+192];
	cvta.to.global.u64 	%rd141, %rd140;
	ld.const.u32 	%r446, [params+184];
	mad.lo.s32 	%r447, %r446, %r7, %r6;
	mov.f32 	%f1708, 0f00000000;
	cvt.rzi.u32.f32 	%r448, %f1708;
	mul.wide.u32 	%rd142, %r447, 2;
	add.s64 	%rd143, %rd141, %rd142;
	mov.u16 	%rs173, 0;
	cvt.u16.u32 	%rs174, %r448;
	st.global.v2.u8 	[%rd143], {%rs174, %rs173};

$L__BB0_177:
	and.b32  	%r449, %r56, 4;
	setp.eq.s32 	%p195, %r449, 0;
	ld.const.u32 	%r486, [params+108];
	@%p195 bra 	$L__BB0_181;

	setp.eq.s32 	%p196, %r486, 0;
	ld.const.u64 	%rd144, [params+224];
	cvta.to.global.u64 	%rd145, %rd144;
	ld.const.u32 	%r450, [params+216];
	mad.lo.s32 	%r451, %r450, %r7, %r6;
	mul.wide.u32 	%rd146, %r451, 8;
	add.s64 	%rd33, %rd145, %rd146;
	@%p196 bra 	$L__BB0_180;

	ld.global.v4.u16 	{%rs181, %rs182, %rs183, %rs184}, [%rd33];
	// begin inline asm
	{  cvt.f32.f16 %f1709, %rs181;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1710, %rs182;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1711, %rs183;}

	// end inline asm
	add.f32 	%f1712, %f1709, 0f00000000;
	add.f32 	%f1713, %f1710, 0f00000000;
	add.f32 	%f1714, %f1711, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs180, %f1714;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs179, %f1713;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs178, %f1712;}

	// end inline asm
	mov.u16 	%rs185, 0;
	st.global.v4.u16 	[%rd33], {%rs178, %rs179, %rs180, %rs185};
	bra.uni 	$L__BB0_181;

$L__BB0_5:
	ld.const.u64 	%rd46, [params+432];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r72, [params+424];
	mad.lo.s32 	%r73, %r72, %r60, %r59;
	mul.wide.u32 	%rd48, %r73, 12;
	add.s64 	%rd49, %rd47, %rd48;
	ld.global.f32 	%f10, [%rd49];
	mul.f32 	%f601, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd49+4];
	mul.f32 	%f602, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd49+8];
	mul.f32 	%f603, %f12, 0f3456BF95;
	abs.f32 	%f604, %f1805;
	div.rn.f32 	%f605, %f601, %f604;
	abs.f32 	%f606, %f1806;
	div.rn.f32 	%f607, %f602, %f606;
	abs.f32 	%f608, %f1807;
	div.rn.f32 	%f609, %f603, %f608;
	abs.f32 	%f610, %f605;
	abs.f32 	%f611, %f607;
	abs.f32 	%f612, %f609;
	mov.f32 	%f613, 0f38D1B717;
	max.f32 	%f614, %f610, %f613;
	max.f32 	%f615, %f611, %f613;
	max.f32 	%f616, %f612, %f613;
	fma.rn.f32 	%f13, %f1805, %f614, %f10;
	fma.rn.f32 	%f14, %f1806, %f615, %f11;
	fma.rn.f32 	%f15, %f1807, %f616, %f12;
	ld.const.u64 	%rd50, [params+128];
	cvta.to.global.u64 	%rd51, %rd50;
	ld.const.u32 	%r74, [params+120];
	mad.lo.s32 	%r75, %r74, %r60, %r59;
	mul.wide.u32 	%rd52, %r75, 4;
	add.s64 	%rd53, %rd51, %rd52;
	ld.global.u32 	%r477, [%rd53];
	mov.u32 	%r473, 0;
	abs.s32 	%r76, %r3;
	setp.lt.s32 	%p18, %r76, 1;
	mov.pred 	%p17, 0;
	mov.f32 	%f1842, 0f00000000;
	mov.f32 	%f1843, %f1842;
	mov.f32 	%f1844, %f1842;
	mov.f32 	%f1845, %f1842;
	mov.f32 	%f1846, %f1842;
	mov.f32 	%f1847, %f1842;
	mov.f32 	%f1848, %f1842;
	mov.f32 	%f1849, %f1842;
	mov.f32 	%f1850, %f1842;
	mov.f32 	%f1851, %f1842;
	mov.f32 	%f1852, %f1842;
	mov.f32 	%f1853, %f1842;
	mov.f32 	%f1854, %f1842;
	mov.f32 	%f1855, %f1842;
	mov.f32 	%f1856, %f1842;
	mov.f32 	%f1857, %f1842;
	mov.f32 	%f1858, %f1842;
	mov.f32 	%f1859, %f1842;
	mov.f32 	%f1860, %f1842;
	mov.f32 	%f1861, %f1842;
	mov.f32 	%f1862, %f1842;
	mov.f32 	%f1863, %f1842;
	mov.f32 	%f1864, %f1842;
	mov.f32 	%f1865, %f1842;
	mov.f32 	%f1866, %f1842;
	mov.f32 	%f1867, %f1842;
	mov.f32 	%f1868, %f1842;
	mov.f32 	%f1869, %f1842;
	mov.f32 	%f1870, %f1842;
	mov.f32 	%f1871, %f1842;
	mov.f32 	%f1872, %f1842;
	mov.pred 	%p206, %p17;
	@%p18 bra 	$L__BB0_23;

	ld.const.f32 	%f16, [params+620];
	ld.const.u64 	%rd54, [params+624];
	cvta.to.global.u64 	%rd2, %rd54;
	ld.const.u64 	%rd55, [params+640];
	cvta.to.global.u64 	%rd56, %rd55;
	ld.const.u32 	%r78, [params+632];
	and.b32  	%r79, %r60, 255;
	and.b32  	%r80, %r59, 255;
	mad.lo.s32 	%r81, %r78, %r79, %r80;
	mul.wide.u32 	%rd57, %r81, 3;
	add.s64 	%rd3, %rd56, %rd57;
	ld.const.f32 	%f17, [params+660];
	mul.f32 	%f18, %f13, 0f3456BF95;
	mul.f32 	%f19, %f14, 0f3456BF95;
	mul.f32 	%f20, %f15, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	abs.f32 	%f775, %f19;
	abs.f32 	%f776, %f18;
	max.f32 	%f777, %f776, %f775;
	abs.f32 	%f778, %f20;
	max.f32 	%f779, %f777, %f778;

$L__BB0_7:
	mul.lo.s32 	%r82, %r473, 3;
	mul.wide.s32 	%rd58, %r82, 12;
	add.s64 	%rd59, %rd2, %rd58;
	ld.global.f32 	%f648, [%rd59];
	sub.f32 	%f649, %f648, %f10;
	ld.global.f32 	%f650, [%rd59+4];
	sub.f32 	%f651, %f650, %f11;
	ld.global.f32 	%f652, [%rd59+8];
	sub.f32 	%f653, %f652, %f12;
	mul.f32 	%f654, %f651, %f651;
	fma.rn.f32 	%f655, %f649, %f649, %f654;
	fma.rn.f32 	%f656, %f653, %f653, %f655;
	sqrt.rn.f32 	%f52, %f656;
	rcp.rn.f32 	%f657, %f52;
	mul.f32 	%f53, %f649, %f657;
	mul.f32 	%f54, %f651, %f657;
	mul.f32 	%f55, %f653, %f657;
	mul.f32 	%f658, %f52, %f52;
	div.rn.f32 	%f56, %f16, %f658;
	ld.global.u8 	%rs15, [%rd3];
	cvt.rn.f32.u16 	%f659, %rs15;
	div.rn.f32 	%f660, %f659, 0fC37F0000;
	fma.rn.f32 	%f661, %f660, 0f3F333333, 0f3F800000;
	setp.gt.f32 	%p20, %f56, %f661;
	setp.ne.s32 	%p21, %r4, 0;
	and.pred  	%p22, %p21, %p20;
	mov.pred 	%p206, -1;
	@%p22 bra 	$L__BB0_23;

	mul.f32 	%f57, %f52, %f17;
	mov.f32 	%f666, 0f40800000;
	abs.f32 	%f59, %f57;
	setp.lt.f32 	%p23, %f59, 0f00800000;
	mul.f32 	%f668, %f59, 0f4B800000;
	selp.f32 	%f669, %f668, %f59, %p23;
	selp.f32 	%f670, 0fC3170000, 0fC2FE0000, %p23;
	mov.b32 	%r83, %f669;
	and.b32  	%r84, %r83, 8388607;
	or.b32  	%r85, %r84, 1065353216;
	mov.b32 	%f671, %r85;
	shr.u32 	%r86, %r83, 23;
	cvt.rn.f32.u32 	%f672, %r86;
	add.f32 	%f673, %f670, %f672;
	setp.gt.f32 	%p24, %f671, 0f3FB504F3;
	mul.f32 	%f674, %f671, 0f3F000000;
	add.f32 	%f675, %f673, 0f3F800000;
	selp.f32 	%f676, %f675, %f673, %p24;
	selp.f32 	%f677, %f674, %f671, %p24;
	add.f32 	%f678, %f677, 0fBF800000;
	add.f32 	%f679, %f677, 0f3F800000;
	rcp.approx.ftz.f32 	%f680, %f679;
	add.f32 	%f681, %f678, %f678;
	mul.f32 	%f682, %f681, %f680;
	mul.f32 	%f683, %f682, %f682;
	mov.f32 	%f684, 0f3C4CAF63;
	mov.f32 	%f685, 0f3B18F0FE;
	fma.rn.f32 	%f686, %f685, %f683, %f684;
	mov.f32 	%f687, 0f3DAAAABD;
	fma.rn.f32 	%f688, %f686, %f683, %f687;
	mul.rn.f32 	%f689, %f688, %f683;
	mul.rn.f32 	%f690, %f689, %f682;
	sub.f32 	%f691, %f678, %f682;
	add.f32 	%f692, %f691, %f691;
	neg.f32 	%f693, %f682;
	fma.rn.f32 	%f694, %f693, %f678, %f692;
	mul.rn.f32 	%f695, %f680, %f694;
	add.f32 	%f696, %f690, %f682;
	sub.f32 	%f697, %f682, %f696;
	add.f32 	%f698, %f690, %f697;
	add.f32 	%f699, %f695, %f698;
	add.f32 	%f700, %f696, %f699;
	sub.f32 	%f701, %f696, %f700;
	add.f32 	%f702, %f699, %f701;
	mov.f32 	%f703, 0f3F317200;
	mul.rn.f32 	%f704, %f676, %f703;
	mov.f32 	%f705, 0f35BFBE8E;
	mul.rn.f32 	%f706, %f676, %f705;
	add.f32 	%f707, %f704, %f700;
	sub.f32 	%f708, %f704, %f707;
	add.f32 	%f709, %f700, %f708;
	add.f32 	%f710, %f702, %f709;
	add.f32 	%f711, %f706, %f710;
	add.f32 	%f712, %f707, %f711;
	sub.f32 	%f713, %f707, %f712;
	add.f32 	%f714, %f711, %f713;
	mul.rn.f32 	%f715, %f666, %f712;
	neg.f32 	%f716, %f715;
	fma.rn.f32 	%f717, %f666, %f712, %f716;
	fma.rn.f32 	%f718, %f666, %f714, %f717;
	mov.f32 	%f719, 0f00000000;
	fma.rn.f32 	%f720, %f719, %f712, %f718;
	add.rn.f32 	%f721, %f715, %f720;
	neg.f32 	%f722, %f721;
	add.rn.f32 	%f723, %f715, %f722;
	add.rn.f32 	%f724, %f723, %f720;
	mov.b32 	%r87, %f721;
	setp.eq.s32 	%p25, %r87, 1118925336;
	add.s32 	%r88, %r87, -1;
	mov.b32 	%f725, %r88;
	add.f32 	%f726, %f724, 0f37000000;
	selp.f32 	%f60, %f726, %f724, %p25;
	selp.f32 	%f727, %f725, %f721, %p25;
	mov.f32 	%f728, 0f3FB8AA3B;
	mul.rn.f32 	%f729, %f727, %f728;
	cvt.rzi.f32.f32 	%f730, %f729;
	abs.f32 	%f731, %f730;
	setp.gt.f32 	%p26, %f731, 0f42FC0000;
	mov.b32 	%r89, %f730;
	and.b32  	%r90, %r89, -2147483648;
	or.b32  	%r91, %r90, 1123811328;
	mov.b32 	%f732, %r91;
	selp.f32 	%f733, %f732, %f730, %p26;
	mov.f32 	%f734, 0fBF317218;
	fma.rn.f32 	%f735, %f733, %f734, %f727;
	mov.f32 	%f736, 0f3102E308;
	fma.rn.f32 	%f737, %f733, %f736, %f735;
	mul.f32 	%f738, %f737, 0f3FB8AA3B;
	add.f32 	%f739, %f733, 0f4B40007F;
	mov.b32 	%r92, %f739;
	shl.b32 	%r93, %r92, 23;
	mov.b32 	%f740, %r93;
	ex2.approx.ftz.f32 	%f741, %f738;
	mul.f32 	%f61, %f741, %f740;
	setp.eq.f32 	%p27, %f61, 0f7F800000;
	mov.f32 	%f1839, 0f7F800000;
	@%p27 bra 	$L__BB0_10;

	fma.rn.f32 	%f1839, %f61, %f60, %f61;

$L__BB0_10:
	mov.f32 	%f1804, 0f40000000;
	cvt.rzi.f32.f32 	%f1803, %f1804;
	add.f32 	%f1802, %f1803, %f1803;
	mov.f32 	%f1801, 0f40800000;
	sub.f32 	%f1800, %f1801, %f1802;
	abs.f32 	%f1799, %f1800;
	setp.lt.f32 	%p28, %f57, 0f00000000;
	setp.eq.f32 	%p29, %f1799, 0f3F800000;
	and.pred  	%p1, %p28, %p29;
	setp.eq.f32 	%p30, %f57, 0f00000000;
	@%p30 bra 	$L__BB0_14;
	bra.uni 	$L__BB0_11;

$L__BB0_14:
	add.f32 	%f746, %f57, %f57;
	selp.f32 	%f1841, %f746, 0f00000000, %p29;
	bra.uni 	$L__BB0_15;

$L__BB0_11:
	mov.b32 	%r94, %f1839;
	xor.b32  	%r95, %r94, -2147483648;
	mov.b32 	%f742, %r95;
	selp.f32 	%f1841, %f742, %f1839, %p1;
	setp.geu.f32 	%p31, %f57, 0f00000000;
	@%p31 bra 	$L__BB0_15;

	mov.f32 	%f743, 0f40800000;
	cvt.rzi.f32.f32 	%f744, %f743;
	setp.eq.f32 	%p32, %f744, 0f40800000;
	@%p32 bra 	$L__BB0_15;

	mov.f32 	%f1841, 0f7FFFFFFF;

$L__BB0_15:
	add.f32 	%f747, %f59, 0f40800000;
	mov.b32 	%r96, %f747;
	setp.lt.s32 	%p34, %r96, 2139095040;
	@%p34 bra 	$L__BB0_20;

	setp.gtu.f32 	%p35, %f59, 0f7F800000;
	@%p35 bra 	$L__BB0_19;
	bra.uni 	$L__BB0_17;

$L__BB0_19:
	add.f32 	%f1841, %f57, 0f40800000;
	bra.uni 	$L__BB0_20;

$L__BB0_17:
	setp.neu.f32 	%p36, %f59, 0f7F800000;
	@%p36 bra 	$L__BB0_20;

	selp.f32 	%f1841, 0fFF800000, 0f7F800000, %p1;

$L__BB0_20:
	mov.f32 	%f748, 0f3F800000;
	sub.f32 	%f749, %f748, %f1841;
	setp.eq.f32 	%p37, %f57, 0f3F800000;
	selp.f32 	%f750, 0f00000000, %f749, %p37;
	cvt.sat.f32.f32 	%f751, %f750;
	mul.f32 	%f752, %f56, %f751;
	ld.global.f32 	%f753, [%rd59+12];
	mul.f32 	%f754, %f53, %f753;
	ld.global.f32 	%f755, [%rd59+16];
	mul.f32 	%f756, %f54, %f755;
	neg.f32 	%f757, %f756;
	sub.f32 	%f758, %f757, %f754;
	ld.global.f32 	%f759, [%rd59+20];
	mul.f32 	%f760, %f55, %f759;
	sub.f32 	%f761, %f758, %f760;
	cvt.sat.f32.f32 	%f762, %f761;
	mul.f32 	%f70, %f752, %f762;
	mul.f32 	%f763, %f1806, %f54;
	fma.rn.f32 	%f764, %f1805, %f53, %f763;
	fma.rn.f32 	%f71, %f1807, %f55, %f764;
	setp.leu.f32 	%p38, %f70, 0f3727C5AC;
	@%p38 bra 	$L__BB0_22;

	cvt.sat.f32.f32 	%f774, %f71;
	mov.f32 	%f780, 0f38D1B717;
	max.f32 	%f771, %f779, %f780;
	sub.f32 	%f772, %f52, %f771;
	mov.f32 	%f773, 0f00000000;
	mov.u32 	%r134, 2;
	mov.u32 	%r136, 1;
	mov.u32 	%r137, 1065353216;
	mov.u32 	%r168, 0;
	// begin inline asm
	call(%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128,%r129),_optix_trace_typed_32,(%r168,%rd4,%f13,%f14,%f15,%f53,%f54,%f55,%f771,%f772,%f773,%r136,%r168,%r136,%r134,%r136,%r136,%r137,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168);
	// end inline asm
	mov.b32 	%f781, %r98;
	ld.global.f32 	%f782, [%rd59+24];
	mul.f32 	%f783, %f782, %f781;
	ld.global.f32 	%f784, [%rd59+28];
	mul.f32 	%f785, %f784, %f781;
	ld.global.f32 	%f786, [%rd59+32];
	mul.f32 	%f787, %f786, %f781;
	mul.f32 	%f788, %f70, 0f3EA2F983;
	mul.f32 	%f789, %f788, %f783;
	mul.f32 	%f790, %f788, %f785;
	mul.f32 	%f791, %f788, %f787;
	fma.rn.f32 	%f1869, %f774, %f789, %f1869;
	fma.rn.f32 	%f1870, %f774, %f790, %f1870;
	fma.rn.f32 	%f1871, %f774, %f791, %f1871;
	add.f32 	%f1866, %f1866, %f789;
	add.f32 	%f1867, %f1867, %f790;
	add.f32 	%f1868, %f1868, %f791;
	fma.rn.f32 	%f1863, %f54, %f789, %f1863;
	fma.rn.f32 	%f1864, %f54, %f790, %f1864;
	fma.rn.f32 	%f1865, %f54, %f791, %f1865;
	fma.rn.f32 	%f1860, %f55, %f789, %f1860;
	fma.rn.f32 	%f1861, %f55, %f790, %f1861;
	fma.rn.f32 	%f1862, %f55, %f791, %f1862;
	fma.rn.f32 	%f1857, %f53, %f789, %f1857;
	fma.rn.f32 	%f1858, %f53, %f790, %f1858;
	fma.rn.f32 	%f1859, %f53, %f791, %f1859;
	mul.f32 	%f792, %f53, %f54;
	fma.rn.f32 	%f1854, %f792, %f789, %f1854;
	fma.rn.f32 	%f1855, %f792, %f790, %f1855;
	fma.rn.f32 	%f1856, %f792, %f791, %f1856;
	mul.f32 	%f793, %f54, %f55;
	fma.rn.f32 	%f1851, %f793, %f789, %f1851;
	fma.rn.f32 	%f1852, %f793, %f790, %f1852;
	fma.rn.f32 	%f1853, %f793, %f791, %f1853;
	fma.rn.f32 	%f794, %f55, %f55, 0fBEAAAAAB;
	fma.rn.f32 	%f1848, %f794, %f789, %f1848;
	fma.rn.f32 	%f1849, %f794, %f790, %f1849;
	fma.rn.f32 	%f1850, %f794, %f791, %f1850;
	mul.f32 	%f795, %f53, %f55;
	fma.rn.f32 	%f1845, %f795, %f789, %f1845;
	fma.rn.f32 	%f1846, %f795, %f790, %f1846;
	fma.rn.f32 	%f1847, %f795, %f791, %f1847;
	mul.f32 	%f796, %f54, %f54;
	mul.f32 	%f797, %f53, %f53;
	sub.f32 	%f798, %f797, %f796;
	fma.rn.f32 	%f1842, %f798, %f789, %f1842;
	fma.rn.f32 	%f1843, %f798, %f790, %f1843;
	fma.rn.f32 	%f1844, %f798, %f791, %f1844;
	add.f32 	%f1872, %f1872, %f781;

$L__BB0_22:
	add.s32 	%r473, %r473, 1;
	setp.lt.s32 	%p40, %r473, %r76;
	mov.pred 	%p206, %p17;
	@%p40 bra 	$L__BB0_7;

$L__BB0_23:
	cvt.rn.f32.s32 	%f799, %r473;
	mov.f32 	%f800, 0f3F800000;
	max.f32 	%f801, %f799, %f800;
	rcp.rn.f32 	%f802, %f801;
	mul.f32 	%f2027, %f1869, %f802;
	mul.f32 	%f2028, %f1870, %f802;
	mul.f32 	%f2029, %f1871, %f802;
	div.rn.f32 	%f2030, %f1872, %f801;
	mul.f32 	%f2024, %f1866, %f802;
	mul.f32 	%f2025, %f1867, %f802;
	mul.f32 	%f2026, %f1868, %f802;
	mul.f32 	%f2021, %f1863, %f802;
	mul.f32 	%f2022, %f1864, %f802;
	mul.f32 	%f2023, %f1865, %f802;
	mul.f32 	%f2018, %f1860, %f802;
	mul.f32 	%f2019, %f1861, %f802;
	mul.f32 	%f2020, %f1862, %f802;
	mul.f32 	%f2015, %f1857, %f802;
	mul.f32 	%f2016, %f1858, %f802;
	mul.f32 	%f2017, %f1859, %f802;
	mul.f32 	%f2012, %f1854, %f802;
	mul.f32 	%f2013, %f1855, %f802;
	mul.f32 	%f2014, %f1856, %f802;
	mul.f32 	%f2009, %f1851, %f802;
	mul.f32 	%f2010, %f1852, %f802;
	mul.f32 	%f2011, %f1853, %f802;
	mul.f32 	%f2006, %f1848, %f802;
	mul.f32 	%f2007, %f1849, %f802;
	mul.f32 	%f2008, %f1850, %f802;
	mul.f32 	%f2003, %f1845, %f802;
	mul.f32 	%f2004, %f1846, %f802;
	mul.f32 	%f2005, %f1847, %f802;
	mul.f32 	%f2000, %f1842, %f802;
	mul.f32 	%f2001, %f1843, %f802;
	mul.f32 	%f2002, %f1844, %f802;
	not.pred 	%p41, %p206;
	@%p41 bra 	$L__BB0_54;

	setp.lt.s32 	%p42, %r4, 1;
	mov.f32 	%f832, 0f00000000;
	mov.f32 	%f1963, %f832;
	mov.f32 	%f1962, %f832;
	mov.f32 	%f1961, %f832;
	mov.f32 	%f1960, %f832;
	mov.f32 	%f1959, %f832;
	mov.f32 	%f1958, %f832;
	mov.f32 	%f1957, %f832;
	mov.f32 	%f1956, %f832;
	mov.f32 	%f1955, %f832;
	mov.f32 	%f1954, %f832;
	mov.f32 	%f1953, %f832;
	mov.f32 	%f1952, %f832;
	mov.f32 	%f1951, %f832;
	mov.f32 	%f1950, %f832;
	mov.f32 	%f1949, %f832;
	mov.f32 	%f1948, %f832;
	mov.f32 	%f1947, %f832;
	mov.f32 	%f1946, %f832;
	mov.f32 	%f1945, %f832;
	mov.f32 	%f1944, %f832;
	mov.f32 	%f1943, %f832;
	mov.f32 	%f1942, %f832;
	mov.f32 	%f1941, %f832;
	mov.f32 	%f1940, %f832;
	mov.f32 	%f1939, %f832;
	mov.f32 	%f1938, %f832;
	mov.f32 	%f1937, %f832;
	mov.f32 	%f1936, %f832;
	mov.f32 	%f1935, %f832;
	mov.f32 	%f1934, %f832;
	@%p42 bra 	$L__BB0_53;

	cvt.rn.f32.s32 	%f863, %r5;
	rcp.rn.f32 	%f196, %f863;
	mul.f32 	%f197, %f13, 0f3456BF95;
	mul.f32 	%f198, %f14, 0f3456BF95;
	mul.f32 	%f199, %f15, 0f3456BF95;
	ld.const.u64 	%rd5, [params+96];
	add.u64 	%rd65, %SP, 0;
	add.u64 	%rd6, %SPL, 0;
	mov.u32 	%r171, 0;
	add.s64 	%rd7, %rd6, 24;
	mov.u64 	%rd66, __cudart_i2opi_f;
	abs.f32 	%f920, %f198;
	abs.f32 	%f921, %f197;
	max.f32 	%f922, %f921, %f920;
	abs.f32 	%f923, %f199;
	max.f32 	%f924, %f922, %f923;
	mov.u32 	%r474, %r171;

$L__BB0_26:
	cvt.rn.f32.s32 	%f230, %r474;
	mov.u32 	%r476, %r171;

$L__BB0_27:
	mad.lo.s32 	%r173, %r477, 1664525, 1013904223;
	and.b32  	%r174, %r173, 16777215;
	cvt.rn.f32.u32 	%f864, %r174;
	fma.rn.f32 	%f865, %f864, 0f33800000, %f230;
	mul.f32 	%f866, %f196, %f865;
	mad.lo.s32 	%r477, %r173, 1664525, 1013904223;
	and.b32  	%r175, %r477, 16777215;
	cvt.rn.f32.u32 	%f867, %r175;
	cvt.rn.f32.s32 	%f868, %r476;
	fma.rn.f32 	%f869, %f867, 0f33800000, %f868;
	mul.f32 	%f870, %f196, %f869;
	fma.rn.f32 	%f871, %f196, %f865, %f866;
	mov.f32 	%f872, 0f3F800000;
	sub.f32 	%f261, %f872, %f871;
	mul.f32 	%f262, %f261, %f261;
	sub.f32 	%f873, %f872, %f262;
	mov.f32 	%f874, 0f00000000;
	max.f32 	%f875, %f874, %f873;
	sqrt.rn.f32 	%f263, %f875;
	mul.f32 	%f264, %f870, 0f40C90FDB;
	mul.f32 	%f876, %f264, 0f3F22F983;
	cvt.rni.s32.f32 	%r484, %f876;
	cvt.rn.f32.s32 	%f877, %r484;
	mov.f32 	%f878, 0fBFC90FDA;
	fma.rn.f32 	%f879, %f877, %f878, %f264;
	mov.f32 	%f880, 0fB3A22168;
	fma.rn.f32 	%f881, %f877, %f880, %f879;
	mov.f32 	%f882, 0fA7C234C5;
	fma.rn.f32 	%f1967, %f877, %f882, %f881;
	abs.f32 	%f266, %f264;
	setp.ltu.f32 	%p43, %f266, 0f47CE4780;
	mov.u32 	%r481, %r484;
	mov.f32 	%f1964, %f1967;
	@%p43 bra 	$L__BB0_35;

	setp.eq.f32 	%p44, %f266, 0f7F800000;
	@%p44 bra 	$L__BB0_34;
	bra.uni 	$L__BB0_29;

$L__BB0_34:
	mov.f32 	%f885, 0f00000000;
	mul.rn.f32 	%f1964, %f264, %f885;
	mov.u32 	%r481, 0;
	bra.uni 	$L__BB0_35;

$L__BB0_29:
	mov.b32 	%r18, %f264;
	bfe.u32 	%r177, %r18, 23, 8;
	add.s32 	%r19, %r177, -128;
	shl.b32 	%r178, %r18, 8;
	or.b32  	%r20, %r178, -2147483648;
	shr.u32 	%r21, %r19, 5;
	mov.u64 	%rd176, 0;
	mov.u32 	%r478, 0;
	mov.u64 	%rd174, %rd6;
	mov.u64 	%rd175, %rd66;

$L__BB0_30:
	.pragma "nounroll";
	ld.global.nc.u32 	%r179, [%rd175];
	mad.wide.u32 	%rd69, %r179, %r20, %rd176;
	shr.u64 	%rd176, %rd69, 32;
	st.local.u32 	[%rd174], %rd69;
	add.s64 	%rd175, %rd175, 4;
	add.s64 	%rd174, %rd174, 4;
	add.s32 	%r478, %r478, 1;
	setp.ne.s32 	%p45, %r478, 6;
	@%p45 bra 	$L__BB0_30;

	st.local.u32 	[%rd7], %rd176;
	mov.u32 	%r180, 4;
	sub.s32 	%r24, %r180, %r21;
	mov.u32 	%r181, 6;
	sub.s32 	%r182, %r181, %r21;
	cvta.to.local.u64 	%rd71, %rd65;
	mul.wide.s32 	%rd72, %r182, 4;
	add.s64 	%rd73, %rd71, %rd72;
	ld.local.u32 	%r479, [%rd73];
	ld.local.u32 	%r480, [%rd73+-4];
	and.b32  	%r27, %r19, 31;
	setp.eq.s32 	%p46, %r27, 0;
	@%p46 bra 	$L__BB0_33;

	mov.u32 	%r183, 32;
	sub.s32 	%r184, %r183, %r27;
	shr.u32 	%r185, %r480, %r184;
	shl.b32 	%r186, %r479, %r27;
	add.s32 	%r479, %r185, %r186;
	mul.wide.s32 	%rd76, %r24, 4;
	add.s64 	%rd77, %rd71, %rd76;
	ld.local.u32 	%r187, [%rd77];
	shr.u32 	%r188, %r187, %r184;
	shl.b32 	%r189, %r480, %r27;
	add.s32 	%r480, %r188, %r189;

$L__BB0_33:
	and.b32  	%r190, %r18, -2147483648;
	shr.u32 	%r191, %r480, 30;
	shl.b32 	%r192, %r479, 2;
	or.b32  	%r193, %r191, %r192;
	shr.u32 	%r194, %r193, 31;
	shr.u32 	%r195, %r479, 30;
	add.s32 	%r196, %r194, %r195;
	neg.s32 	%r197, %r196;
	setp.eq.s32 	%p47, %r190, 0;
	selp.b32 	%r481, %r196, %r197, %p47;
	setp.ne.s32 	%p48, %r194, 0;
	xor.b32  	%r198, %r190, -2147483648;
	selp.b32 	%r199, %r198, %r190, %p48;
	selp.b32 	%r200, -1, 0, %p48;
	xor.b32  	%r201, %r193, %r200;
	shl.b32 	%r202, %r480, 2;
	xor.b32  	%r203, %r202, %r200;
	cvt.u64.u32 	%rd78, %r201;
	cvt.u64.u32 	%rd79, %r203;
	bfi.b64 	%rd80, %rd78, %rd79, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd80;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f883, %fd2;
	setp.eq.s32 	%p49, %r199, 0;
	neg.f32 	%f884, %f883;
	selp.f32 	%f1964, %f883, %f884, %p49;

$L__BB0_35:
	add.s32 	%r34, %r481, 1;
	and.b32  	%r35, %r34, 1;
	setp.eq.s32 	%p50, %r35, 0;
	selp.f32 	%f270, %f1964, 0f3F800000, %p50;
	mul.rn.f32 	%f271, %f1964, %f1964;
	mov.f32 	%f1965, 0fB94D4153;
	@%p50 bra 	$L__BB0_37;

	mov.f32 	%f887, 0fBAB607ED;
	mov.f32 	%f888, 0f37CBAC00;
	fma.rn.f32 	%f1965, %f888, %f271, %f887;

$L__BB0_37:
	selp.f32 	%f889, 0f3C0885E4, 0f3D2AAABB, %p50;
	fma.rn.f32 	%f890, %f1965, %f271, %f889;
	selp.f32 	%f891, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
	fma.rn.f32 	%f892, %f890, %f271, %f891;
	mov.f32 	%f893, 0f00000000;
	fma.rn.f32 	%f894, %f271, %f270, %f893;
	fma.rn.f32 	%f1966, %f892, %f894, %f270;
	and.b32  	%r205, %r34, 2;
	setp.eq.s32 	%p52, %r205, 0;
	@%p52 bra 	$L__BB0_39;

	mov.f32 	%f896, 0fBF800000;
	fma.rn.f32 	%f1966, %f1966, %f896, %f893;

$L__BB0_39:
	@%p43 bra 	$L__BB0_47;

	setp.eq.f32 	%p54, %f266, 0f7F800000;
	@%p54 bra 	$L__BB0_46;
	bra.uni 	$L__BB0_41;

$L__BB0_46:
	mov.f32 	%f899, 0f00000000;
	mul.rn.f32 	%f1967, %f264, %f899;
	mov.u32 	%r484, 0;
	bra.uni 	$L__BB0_47;

$L__BB0_41:
	mov.b32 	%r36, %f264;
	bfe.u32 	%r206, %r36, 23, 8;
	add.s32 	%r37, %r206, -128;
	shl.b32 	%r207, %r36, 8;
	or.b32  	%r38, %r207, -2147483648;
	shr.u32 	%r39, %r37, 5;
	mov.u64 	%rd177, 0;
	mov.u64 	%rd178, %rd177;

$L__BB0_42:
	.pragma "nounroll";
	shl.b64 	%rd83, %rd177, 2;
	mov.u64 	%rd84, __cudart_i2opi_f;
	add.s64 	%rd85, %rd84, %rd83;
	ld.global.nc.u32 	%r208, [%rd85];
	mad.wide.u32 	%rd86, %r208, %r38, %rd178;
	shr.u64 	%rd178, %rd86, 32;
	add.s64 	%rd87, %rd6, %rd83;
	st.local.u32 	[%rd87], %rd86;
	cvt.u32.u64 	%r209, %rd177;
	add.s32 	%r210, %r209, 1;
	cvt.s64.s32 	%rd177, %r210;
	setp.ne.s32 	%p55, %r210, 6;
	@%p55 bra 	$L__BB0_42;

	st.local.u32 	[%rd7], %rd178;
	mov.u32 	%r211, 4;
	sub.s32 	%r40, %r211, %r39;
	mov.u32 	%r212, 6;
	sub.s32 	%r213, %r212, %r39;
	cvta.to.local.u64 	%rd89, %rd65;
	mul.wide.s32 	%rd90, %r213, 4;
	add.s64 	%rd91, %rd89, %rd90;
	ld.local.u32 	%r482, [%rd91];
	ld.local.u32 	%r483, [%rd91+-4];
	and.b32  	%r43, %r37, 31;
	setp.eq.s32 	%p56, %r43, 0;
	@%p56 bra 	$L__BB0_45;

	mov.u32 	%r214, 32;
	sub.s32 	%r215, %r214, %r43;
	shr.u32 	%r216, %r483, %r215;
	shl.b32 	%r217, %r482, %r43;
	add.s32 	%r482, %r216, %r217;
	mul.wide.s32 	%rd94, %r40, 4;
	add.s64 	%rd95, %rd89, %rd94;
	ld.local.u32 	%r218, [%rd95];
	shr.u32 	%r219, %r218, %r215;
	shl.b32 	%r220, %r483, %r43;
	add.s32 	%r483, %r219, %r220;

$L__BB0_45:
	and.b32  	%r221, %r36, -2147483648;
	shr.u32 	%r222, %r483, 30;
	shl.b32 	%r223, %r482, 2;
	or.b32  	%r224, %r222, %r223;
	shr.u32 	%r225, %r224, 31;
	shr.u32 	%r226, %r482, 30;
	add.s32 	%r227, %r225, %r226;
	neg.s32 	%r228, %r227;
	setp.eq.s32 	%p57, %r221, 0;
	selp.b32 	%r484, %r227, %r228, %p57;
	setp.ne.s32 	%p58, %r225, 0;
	xor.b32  	%r229, %r221, -2147483648;
	selp.b32 	%r230, %r229, %r221, %p58;
	selp.b32 	%r231, -1, 0, %p58;
	xor.b32  	%r232, %r224, %r231;
	shl.b32 	%r233, %r483, 2;
	xor.b32  	%r234, %r233, %r231;
	cvt.u64.u32 	%rd96, %r232;
	cvt.u64.u32 	%rd97, %r234;
	bfi.b64 	%rd98, %rd96, %rd97, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd98;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f897, %fd4;
	setp.eq.s32 	%p59, %r230, 0;
	neg.f32 	%f898, %f897;
	selp.f32 	%f1967, %f897, %f898, %p59;

$L__BB0_47:
	mul.f32 	%f280, %f263, %f1966;
	and.b32  	%r50, %r484, 1;
	setp.eq.s32 	%p60, %r50, 0;
	selp.f32 	%f281, %f1967, 0f3F800000, %p60;
	mul.rn.f32 	%f282, %f1967, %f1967;
	mov.f32 	%f1968, 0fB94D4153;
	@%p60 bra 	$L__BB0_49;

	mov.f32 	%f901, 0fBAB607ED;
	mov.f32 	%f902, 0f37CBAC00;
	fma.rn.f32 	%f1968, %f902, %f282, %f901;

$L__BB0_49:
	selp.f32 	%f903, 0f3C0885E4, 0f3D2AAABB, %p60;
	fma.rn.f32 	%f904, %f1968, %f282, %f903;
	selp.f32 	%f905, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
	fma.rn.f32 	%f906, %f904, %f282, %f905;
	mov.f32 	%f907, 0f00000000;
	fma.rn.f32 	%f908, %f282, %f281, %f907;
	fma.rn.f32 	%f1969, %f906, %f908, %f281;
	and.b32  	%r236, %r484, 2;
	setp.eq.s32 	%p62, %r236, 0;
	@%p62 bra 	$L__BB0_51;

	mov.f32 	%f910, 0fBF800000;
	fma.rn.f32 	%f1969, %f1969, %f910, %f907;

$L__BB0_51:
	mov.f32 	%f925, 0f38D1B717;
	max.f32 	%f917, %f924, %f925;
	mul.f32 	%f915, %f263, %f1969;
	mov.f32 	%f918, 0f6C4ECB8F;
	mov.u32 	%r270, 1;
	mov.u32 	%r273, 2;
	mov.u32 	%r275, 3;
	mov.u32 	%r307, 0;
	// begin inline asm
	call(%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268),_optix_trace_typed_32,(%r307,%rd5,%f13,%f14,%f15,%f280,%f915,%f261,%f917,%f918,%f907,%r270,%r307,%r307,%r273,%r307,%r275,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307);
	// end inline asm
	mov.b32 	%f926, %r237;
	mov.b32 	%f927, %r238;
	mov.b32 	%f928, %r239;
	max.f32 	%f929, %f926, %f907;
	max.f32 	%f930, %f927, %f907;
	max.f32 	%f931, %f928, %f907;
	add.f32 	%f1939, %f1939, %f929;
	add.f32 	%f1938, %f1938, %f930;
	add.f32 	%f1937, %f1937, %f931;
	fma.rn.f32 	%f1942, %f915, %f929, %f1942;
	fma.rn.f32 	%f1941, %f915, %f930, %f1941;
	fma.rn.f32 	%f1940, %f915, %f931, %f1940;
	fma.rn.f32 	%f1945, %f261, %f929, %f1945;
	fma.rn.f32 	%f1944, %f261, %f930, %f1944;
	fma.rn.f32 	%f1943, %f261, %f931, %f1943;
	fma.rn.f32 	%f1948, %f280, %f929, %f1948;
	fma.rn.f32 	%f1947, %f280, %f930, %f1947;
	fma.rn.f32 	%f1946, %f280, %f931, %f1946;
	mul.f32 	%f932, %f280, %f915;
	fma.rn.f32 	%f1951, %f932, %f929, %f1951;
	fma.rn.f32 	%f1950, %f932, %f930, %f1950;
	fma.rn.f32 	%f1949, %f932, %f931, %f1949;
	mul.f32 	%f933, %f261, %f915;
	fma.rn.f32 	%f1954, %f933, %f929, %f1954;
	fma.rn.f32 	%f1953, %f933, %f930, %f1953;
	fma.rn.f32 	%f1952, %f933, %f931, %f1952;
	add.f32 	%f934, %f262, 0fBEAAAAAB;
	fma.rn.f32 	%f1957, %f934, %f929, %f1957;
	fma.rn.f32 	%f1956, %f934, %f930, %f1956;
	fma.rn.f32 	%f1955, %f934, %f931, %f1955;
	mul.f32 	%f935, %f261, %f280;
	fma.rn.f32 	%f1960, %f935, %f929, %f1960;
	fma.rn.f32 	%f1959, %f935, %f930, %f1959;
	fma.rn.f32 	%f1958, %f935, %f931, %f1958;
	mul.f32 	%f936, %f915, %f915;
	mul.f32 	%f937, %f280, %f280;
	sub.f32 	%f938, %f937, %f936;
	fma.rn.f32 	%f1963, %f938, %f929, %f1963;
	fma.rn.f32 	%f1962, %f938, %f930, %f1962;
	fma.rn.f32 	%f1961, %f938, %f931, %f1961;
	mul.f32 	%f939, %f1806, %f915;
	fma.rn.f32 	%f940, %f1805, %f280, %f939;
	fma.rn.f32 	%f941, %f1807, %f261, %f940;
	cvt.sat.f32.f32 	%f942, %f941;
	fma.rn.f32 	%f1936, %f929, %f942, %f1936;
	fma.rn.f32 	%f1935, %f930, %f942, %f1935;
	fma.rn.f32 	%f1934, %f931, %f942, %f1934;
	add.s32 	%r476, %r476, 1;
	setp.lt.s32 	%p63, %r476, %r5;
	@%p63 bra 	$L__BB0_27;

	add.s32 	%r474, %r474, 1;
	setp.lt.s32 	%p64, %r474, %r5;
	@%p64 bra 	$L__BB0_26;

$L__BB0_53:
	mul.lo.s32 	%r308, %r5, %r5;
	cvt.rn.f32.s32 	%f943, %r308;
	rcp.rn.f32 	%f944, %f943;
	mul.f32 	%f945, %f944, %f1936;
	mul.f32 	%f946, %f944, %f1935;
	mul.f32 	%f947, %f944, %f1934;
	div.rn.f32 	%f2030, %f832, %f943;
	mul.f32 	%f2024, %f944, %f1939;
	mul.f32 	%f2025, %f944, %f1938;
	mul.f32 	%f2026, %f944, %f1937;
	mul.f32 	%f2021, %f944, %f1942;
	mul.f32 	%f2022, %f944, %f1941;
	mul.f32 	%f2023, %f944, %f1940;
	mul.f32 	%f2018, %f944, %f1945;
	mul.f32 	%f2019, %f944, %f1944;
	mul.f32 	%f2020, %f944, %f1943;
	mul.f32 	%f2015, %f944, %f1948;
	mul.f32 	%f2016, %f944, %f1947;
	mul.f32 	%f2017, %f944, %f1946;
	mul.f32 	%f2012, %f944, %f1951;
	mul.f32 	%f2013, %f944, %f1950;
	mul.f32 	%f2014, %f944, %f1949;
	mul.f32 	%f2009, %f944, %f1954;
	mul.f32 	%f2010, %f944, %f1953;
	mul.f32 	%f2011, %f944, %f1952;
	mul.f32 	%f2006, %f944, %f1957;
	mul.f32 	%f2007, %f944, %f1956;
	mul.f32 	%f2008, %f944, %f1955;
	mul.f32 	%f2003, %f944, %f1960;
	mul.f32 	%f2004, %f944, %f1959;
	mul.f32 	%f2005, %f944, %f1958;
	mul.f32 	%f2000, %f944, %f1963;
	mul.f32 	%f2001, %f944, %f1962;
	mul.f32 	%f2002, %f944, %f1961;
	fma.rn.f32 	%f2027, %f944, %f1936, %f945;
	fma.rn.f32 	%f2028, %f944, %f1935, %f946;
	fma.rn.f32 	%f2029, %f944, %f1934, %f947;

$L__BB0_54:
	ld.const.u32 	%r471, [params+616];
	setp.lt.s32 	%p65, %r471, 0;
	selp.f32 	%f410, %f2027, %f2030, %p65;
	ld.const.u32 	%r53, [params+104];
	and.b32  	%r309, %r53, 8;
	setp.eq.s32 	%p66, %r309, 0;
	@%p66 bra 	$L__BB0_68;

	ld.const.u64 	%rd100, [params+192];
	cvta.to.global.u64 	%rd19, %rd100;
	ld.const.u32 	%r310, [params+184];
	mad.lo.s32 	%r311, %r310, %r7, %r6;
	cvt.u64.u32 	%rd20, %r311;
	mov.f32 	%f950, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f951, %f950;
	add.f32 	%f952, %f951, %f951;
	mov.f32 	%f953, 0f3EE8BA2E;
	sub.f32 	%f954, %f953, %f952;
	abs.f32 	%f411, %f954;
	abs.f32 	%f412, %f410;
	setp.lt.f32 	%p67, %f412, 0f00800000;
	mul.f32 	%f955, %f412, 0f4B800000;
	selp.f32 	%f956, %f955, %f412, %p67;
	selp.f32 	%f957, 0fC3170000, 0fC2FE0000, %p67;
	mov.b32 	%r312, %f956;
	and.b32  	%r313, %r312, 8388607;
	or.b32  	%r314, %r313, 1065353216;
	mov.b32 	%f958, %r314;
	shr.u32 	%r315, %r312, 23;
	cvt.rn.f32.u32 	%f959, %r315;
	add.f32 	%f960, %f957, %f959;
	setp.gt.f32 	%p68, %f958, 0f3FB504F3;
	mul.f32 	%f961, %f958, 0f3F000000;
	add.f32 	%f962, %f960, 0f3F800000;
	selp.f32 	%f963, %f962, %f960, %p68;
	selp.f32 	%f964, %f961, %f958, %p68;
	add.f32 	%f965, %f964, 0fBF800000;
	add.f32 	%f966, %f964, 0f3F800000;
	rcp.approx.ftz.f32 	%f967, %f966;
	add.f32 	%f968, %f965, %f965;
	mul.f32 	%f969, %f968, %f967;
	mul.f32 	%f970, %f969, %f969;
	mov.f32 	%f971, 0f3C4CAF63;
	mov.f32 	%f972, 0f3B18F0FE;
	fma.rn.f32 	%f973, %f972, %f970, %f971;
	mov.f32 	%f974, 0f3DAAAABD;
	fma.rn.f32 	%f975, %f973, %f970, %f974;
	mul.rn.f32 	%f976, %f975, %f970;
	mul.rn.f32 	%f977, %f976, %f969;
	sub.f32 	%f978, %f965, %f969;
	add.f32 	%f979, %f978, %f978;
	neg.f32 	%f980, %f969;
	fma.rn.f32 	%f981, %f980, %f965, %f979;
	mul.rn.f32 	%f982, %f967, %f981;
	add.f32 	%f983, %f977, %f969;
	sub.f32 	%f984, %f969, %f983;
	add.f32 	%f985, %f977, %f984;
	add.f32 	%f986, %f982, %f985;
	add.f32 	%f987, %f983, %f986;
	sub.f32 	%f988, %f983, %f987;
	add.f32 	%f989, %f986, %f988;
	mov.f32 	%f990, 0f3F317200;
	mul.rn.f32 	%f991, %f963, %f990;
	mov.f32 	%f992, 0f35BFBE8E;
	mul.rn.f32 	%f993, %f963, %f992;
	add.f32 	%f994, %f991, %f987;
	sub.f32 	%f995, %f991, %f994;
	add.f32 	%f996, %f987, %f995;
	add.f32 	%f997, %f989, %f996;
	add.f32 	%f998, %f993, %f997;
	add.f32 	%f999, %f994, %f998;
	sub.f32 	%f1000, %f994, %f999;
	add.f32 	%f1001, %f998, %f1000;
	mul.rn.f32 	%f1002, %f953, %f999;
	neg.f32 	%f1003, %f1002;
	fma.rn.f32 	%f1004, %f953, %f999, %f1003;
	fma.rn.f32 	%f1005, %f953, %f1001, %f1004;
	mov.f32 	%f1006, 0f00000000;
	fma.rn.f32 	%f1007, %f1006, %f999, %f1005;
	add.rn.f32 	%f1008, %f1002, %f1007;
	neg.f32 	%f1009, %f1008;
	add.rn.f32 	%f1010, %f1002, %f1009;
	add.rn.f32 	%f1011, %f1010, %f1007;
	mov.b32 	%r316, %f1008;
	setp.eq.s32 	%p69, %r316, 1118925336;
	add.s32 	%r317, %r316, -1;
	mov.b32 	%f1012, %r317;
	add.f32 	%f1013, %f1011, 0f37000000;
	selp.f32 	%f413, %f1013, %f1011, %p69;
	selp.f32 	%f1014, %f1012, %f1008, %p69;
	mov.f32 	%f1015, 0f3FB8AA3B;
	mul.rn.f32 	%f1016, %f1014, %f1015;
	cvt.rzi.f32.f32 	%f1017, %f1016;
	abs.f32 	%f1018, %f1017;
	setp.gt.f32 	%p70, %f1018, 0f42FC0000;
	mov.b32 	%r318, %f1017;
	and.b32  	%r319, %r318, -2147483648;
	or.b32  	%r320, %r319, 1123811328;
	mov.b32 	%f1019, %r320;
	selp.f32 	%f1020, %f1019, %f1017, %p70;
	mov.f32 	%f1021, 0fBF317218;
	fma.rn.f32 	%f1022, %f1020, %f1021, %f1014;
	mov.f32 	%f1023, 0f3102E308;
	fma.rn.f32 	%f1024, %f1020, %f1023, %f1022;
	mul.f32 	%f1025, %f1024, 0f3FB8AA3B;
	add.f32 	%f1026, %f1020, 0f4B40007F;
	mov.b32 	%r321, %f1026;
	shl.b32 	%r322, %r321, 23;
	mov.b32 	%f1027, %r322;
	ex2.approx.ftz.f32 	%f1028, %f1025;
	mul.f32 	%f414, %f1028, %f1027;
	setp.eq.f32 	%p71, %f414, 0f7F800000;
	mov.f32 	%f2031, 0f7F800000;
	@%p71 bra 	$L__BB0_57;

	fma.rn.f32 	%f2031, %f414, %f413, %f414;

$L__BB0_57:
	setp.lt.f32 	%p72, %f410, 0f00000000;
	setp.eq.f32 	%p73, %f411, 0f3F800000;
	and.pred  	%p3, %p72, %p73;
	setp.eq.f32 	%p74, %f410, 0f00000000;
	@%p74 bra 	$L__BB0_61;
	bra.uni 	$L__BB0_58;

$L__BB0_61:
	add.f32 	%f1033, %f410, %f410;
	selp.f32 	%f2033, %f1033, 0f00000000, %p73;
	bra.uni 	$L__BB0_62;

$L__BB0_180:
	mov.f32 	%f1717, 0f00000000;
	mov.u32 	%r486, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs188, %f1717;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs187, %f1717;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs186, %f1717;}

	// end inline asm
	mov.u16 	%rs189, 0;
	st.global.v4.u16 	[%rd33], {%rs186, %rs187, %rs188, %rs189};

$L__BB0_181:
	ld.const.u64 	%rd147, [params+256];
	cvta.to.global.u64 	%rd148, %rd147;
	ld.const.u32 	%r453, [params+248];
	mad.lo.s32 	%r454, %r453, %r7, %r6;
	mul.wide.u32 	%rd149, %r454, 8;
	add.s64 	%rd34, %rd148, %rd149;
	setp.eq.s32 	%p197, %r486, 0;
	@%p197 bra 	$L__BB0_183;

	ld.global.v4.u16 	{%rs196, %rs197, %rs198, %rs199}, [%rd34];
	// begin inline asm
	{  cvt.f32.f16 %f1718, %rs196;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1719, %rs197;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1720, %rs198;}

	// end inline asm
	add.f32 	%f1721, %f1718, 0f00000000;
	add.f32 	%f1722, %f1719, 0f00000000;
	add.f32 	%f1723, %f1720, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs195, %f1723;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs194, %f1722;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs193, %f1721;}

	// end inline asm
	mov.u16 	%rs200, 0;
	st.global.v4.u16 	[%rd34], {%rs193, %rs194, %rs195, %rs200};
	bra.uni 	$L__BB0_184;

$L__BB0_183:
	mov.f32 	%f1726, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs203, %f1726;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs202, %f1726;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs201, %f1726;}

	// end inline asm
	mov.u16 	%rs204, 0;
	st.global.v4.u16 	[%rd34], {%rs201, %rs202, %rs203, %rs204};

$L__BB0_184:
	ld.const.u64 	%rd150, [params+272];
	cvta.to.global.u64 	%rd151, %rd150;
	ld.const.u32 	%r455, [params+264];
	mad.lo.s32 	%r456, %r455, %r7, %r6;
	mul.wide.u32 	%rd152, %r456, 8;
	add.s64 	%rd35, %rd151, %rd152;
	@%p197 bra 	$L__BB0_186;

	ld.global.v4.u16 	{%rs211, %rs212, %rs213, %rs214}, [%rd35];
	// begin inline asm
	{  cvt.f32.f16 %f1727, %rs211;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1728, %rs212;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1729, %rs213;}

	// end inline asm
	add.f32 	%f1730, %f1727, 0f00000000;
	add.f32 	%f1731, %f1728, 0f00000000;
	add.f32 	%f1732, %f1729, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs210, %f1732;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs209, %f1731;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs208, %f1730;}

	// end inline asm
	mov.u16 	%rs215, 0;
	st.global.v4.u16 	[%rd35], {%rs208, %rs209, %rs210, %rs215};
	bra.uni 	$L__BB0_187;

$L__BB0_186:
	mov.f32 	%f1735, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs218, %f1735;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs217, %f1735;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs216, %f1735;}

	// end inline asm
	mov.u16 	%rs219, 0;
	st.global.v4.u16 	[%rd35], {%rs216, %rs217, %rs218, %rs219};

$L__BB0_187:
	ld.const.u64 	%rd153, [params+288];
	cvta.to.global.u64 	%rd154, %rd153;
	ld.const.u32 	%r457, [params+280];
	mad.lo.s32 	%r458, %r457, %r7, %r6;
	mul.wide.u32 	%rd155, %r458, 8;
	add.s64 	%rd36, %rd154, %rd155;
	@%p197 bra 	$L__BB0_189;

	ld.global.v4.u16 	{%rs226, %rs227, %rs228, %rs229}, [%rd36];
	// begin inline asm
	{  cvt.f32.f16 %f1736, %rs226;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1737, %rs227;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1738, %rs228;}

	// end inline asm
	add.f32 	%f1739, %f1736, 0f00000000;
	add.f32 	%f1740, %f1737, 0f00000000;
	add.f32 	%f1741, %f1738, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs225, %f1741;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs224, %f1740;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs223, %f1739;}

	// end inline asm
	mov.u16 	%rs230, 0;
	st.global.v4.u16 	[%rd36], {%rs223, %rs224, %rs225, %rs230};
	bra.uni 	$L__BB0_190;

$L__BB0_189:
	mov.f32 	%f1744, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs233, %f1744;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs232, %f1744;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs231, %f1744;}

	// end inline asm
	mov.u16 	%rs234, 0;
	st.global.v4.u16 	[%rd36], {%rs231, %rs232, %rs233, %rs234};

$L__BB0_190:
	ld.const.u64 	%rd156, [params+304];
	cvta.to.global.u64 	%rd157, %rd156;
	ld.const.u32 	%r459, [params+296];
	mad.lo.s32 	%r460, %r459, %r7, %r6;
	mul.wide.u32 	%rd158, %r460, 8;
	add.s64 	%rd37, %rd157, %rd158;
	@%p197 bra 	$L__BB0_192;

	ld.global.v4.u16 	{%rs241, %rs242, %rs243, %rs244}, [%rd37];
	// begin inline asm
	{  cvt.f32.f16 %f1745, %rs241;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1746, %rs242;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1747, %rs243;}

	// end inline asm
	add.f32 	%f1748, %f1745, 0f00000000;
	add.f32 	%f1749, %f1746, 0f00000000;
	add.f32 	%f1750, %f1747, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs240, %f1750;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs239, %f1749;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs238, %f1748;}

	// end inline asm
	mov.u16 	%rs245, 0;
	st.global.v4.u16 	[%rd37], {%rs238, %rs239, %rs240, %rs245};
	bra.uni 	$L__BB0_193;

$L__BB0_192:
	mov.f32 	%f1753, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs248, %f1753;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs247, %f1753;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs246, %f1753;}

	// end inline asm
	mov.u16 	%rs249, 0;
	st.global.v4.u16 	[%rd37], {%rs246, %rs247, %rs248, %rs249};

$L__BB0_193:
	ld.const.u64 	%rd159, [params+320];
	cvta.to.global.u64 	%rd160, %rd159;
	ld.const.u32 	%r461, [params+312];
	mad.lo.s32 	%r462, %r461, %r7, %r6;
	mul.wide.u32 	%rd161, %r462, 8;
	add.s64 	%rd38, %rd160, %rd161;
	@%p197 bra 	$L__BB0_195;

	ld.global.v4.u16 	{%rs256, %rs257, %rs258, %rs259}, [%rd38];
	// begin inline asm
	{  cvt.f32.f16 %f1754, %rs256;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1755, %rs257;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1756, %rs258;}

	// end inline asm
	add.f32 	%f1757, %f1754, 0f00000000;
	add.f32 	%f1758, %f1755, 0f00000000;
	add.f32 	%f1759, %f1756, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs255, %f1759;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs254, %f1758;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs253, %f1757;}

	// end inline asm
	mov.u16 	%rs260, 0;
	st.global.v4.u16 	[%rd38], {%rs253, %rs254, %rs255, %rs260};
	bra.uni 	$L__BB0_196;

$L__BB0_195:
	mov.f32 	%f1762, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs263, %f1762;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs262, %f1762;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs261, %f1762;}

	// end inline asm
	mov.u16 	%rs264, 0;
	st.global.v4.u16 	[%rd38], {%rs261, %rs262, %rs263, %rs264};

$L__BB0_196:
	ld.const.u64 	%rd162, [params+336];
	cvta.to.global.u64 	%rd163, %rd162;
	ld.const.u32 	%r463, [params+328];
	mad.lo.s32 	%r464, %r463, %r7, %r6;
	mul.wide.u32 	%rd164, %r464, 8;
	add.s64 	%rd39, %rd163, %rd164;
	@%p197 bra 	$L__BB0_198;

	ld.global.v4.u16 	{%rs271, %rs272, %rs273, %rs274}, [%rd39];
	// begin inline asm
	{  cvt.f32.f16 %f1763, %rs271;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1764, %rs272;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1765, %rs273;}

	// end inline asm
	add.f32 	%f1766, %f1763, 0f00000000;
	add.f32 	%f1767, %f1764, 0f00000000;
	add.f32 	%f1768, %f1765, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs270, %f1768;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs269, %f1767;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs268, %f1766;}

	// end inline asm
	mov.u16 	%rs275, 0;
	st.global.v4.u16 	[%rd39], {%rs268, %rs269, %rs270, %rs275};
	bra.uni 	$L__BB0_199;

$L__BB0_198:
	mov.f32 	%f1771, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs278, %f1771;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs277, %f1771;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs276, %f1771;}

	// end inline asm
	mov.u16 	%rs279, 0;
	st.global.v4.u16 	[%rd39], {%rs276, %rs277, %rs278, %rs279};

$L__BB0_199:
	ld.const.u64 	%rd165, [params+352];
	cvta.to.global.u64 	%rd166, %rd165;
	ld.const.u32 	%r465, [params+344];
	mad.lo.s32 	%r466, %r465, %r7, %r6;
	mul.wide.u32 	%rd167, %r466, 8;
	add.s64 	%rd40, %rd166, %rd167;
	@%p197 bra 	$L__BB0_201;

	ld.global.v4.u16 	{%rs286, %rs287, %rs288, %rs289}, [%rd40];
	// begin inline asm
	{  cvt.f32.f16 %f1772, %rs286;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1773, %rs287;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1774, %rs288;}

	// end inline asm
	add.f32 	%f1775, %f1772, 0f00000000;
	add.f32 	%f1776, %f1773, 0f00000000;
	add.f32 	%f1777, %f1774, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs285, %f1777;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs284, %f1776;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs283, %f1775;}

	// end inline asm
	mov.u16 	%rs290, 0;
	st.global.v4.u16 	[%rd40], {%rs283, %rs284, %rs285, %rs290};
	bra.uni 	$L__BB0_202;

$L__BB0_201:
	mov.f32 	%f1780, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs293, %f1780;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs292, %f1780;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs291, %f1780;}

	// end inline asm
	mov.u16 	%rs294, 0;
	st.global.v4.u16 	[%rd40], {%rs291, %rs292, %rs293, %rs294};

$L__BB0_202:
	ld.const.u64 	%rd168, [params+368];
	cvta.to.global.u64 	%rd169, %rd168;
	ld.const.u32 	%r467, [params+360];
	mad.lo.s32 	%r468, %r467, %r7, %r6;
	mul.wide.u32 	%rd170, %r468, 8;
	add.s64 	%rd41, %rd169, %rd170;
	@%p197 bra 	$L__BB0_204;

	ld.global.v4.u16 	{%rs301, %rs302, %rs303, %rs304}, [%rd41];
	// begin inline asm
	{  cvt.f32.f16 %f1781, %rs301;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1782, %rs302;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1783, %rs303;}

	// end inline asm
	add.f32 	%f1784, %f1781, 0f00000000;
	add.f32 	%f1785, %f1782, 0f00000000;
	add.f32 	%f1786, %f1783, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs300, %f1786;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs299, %f1785;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs298, %f1784;}

	// end inline asm
	mov.u16 	%rs305, 0;
	st.global.v4.u16 	[%rd41], {%rs298, %rs299, %rs300, %rs305};
	bra.uni 	$L__BB0_205;

$L__BB0_204:
	mov.f32 	%f1789, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs308, %f1789;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs307, %f1789;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs306, %f1789;}

	// end inline asm
	mov.u16 	%rs309, 0;
	st.global.v4.u16 	[%rd41], {%rs306, %rs307, %rs308, %rs309};

$L__BB0_205:
	ld.const.u64 	%rd171, [params+384];
	cvta.to.global.u64 	%rd172, %rd171;
	ld.const.u32 	%r469, [params+376];
	mad.lo.s32 	%r470, %r469, %r7, %r6;
	mul.wide.u32 	%rd173, %r470, 8;
	add.s64 	%rd42, %rd172, %rd173;
	@%p197 bra 	$L__BB0_207;

	ld.global.v4.u16 	{%rs316, %rs317, %rs318, %rs319}, [%rd42];
	// begin inline asm
	{  cvt.f32.f16 %f1790, %rs316;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1791, %rs317;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1792, %rs318;}

	// end inline asm
	add.f32 	%f1793, %f1790, 0f00000000;
	add.f32 	%f1794, %f1791, 0f00000000;
	add.f32 	%f1795, %f1792, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs315, %f1795;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs314, %f1794;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs313, %f1793;}

	// end inline asm
	mov.u16 	%rs320, 0;
	st.global.v4.u16 	[%rd42], {%rs313, %rs314, %rs315, %rs320};
	bra.uni 	$L__BB0_208;

$L__BB0_207:
	mov.f32 	%f1798, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs323, %f1798;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs322, %f1798;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs321, %f1798;}

	// end inline asm
	mov.u16 	%rs324, 0;
	st.global.v4.u16 	[%rd42], {%rs321, %rs322, %rs323, %rs324};
	bra.uni 	$L__BB0_208;

$L__BB0_58:
	mov.b32 	%r323, %f2031;
	xor.b32  	%r324, %r323, -2147483648;
	mov.b32 	%f1029, %r324;
	selp.f32 	%f2033, %f1029, %f2031, %p3;
	setp.geu.f32 	%p75, %f410, 0f00000000;
	@%p75 bra 	$L__BB0_62;

	mov.f32 	%f1030, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f1031, %f1030;
	setp.eq.f32 	%p76, %f1031, 0f3EE8BA2E;
	@%p76 bra 	$L__BB0_62;

	mov.f32 	%f2033, 0f7FFFFFFF;

$L__BB0_62:
	add.f32 	%f1034, %f412, 0f3EE8BA2E;
	mov.b32 	%r325, %f1034;
	setp.lt.s32 	%p78, %r325, 2139095040;
	@%p78 bra 	$L__BB0_67;

	setp.gtu.f32 	%p79, %f412, 0f7F800000;
	@%p79 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_64;

$L__BB0_66:
	add.f32 	%f2033, %f410, 0f3EE8BA2E;
	bra.uni 	$L__BB0_67;

$L__BB0_64:
	setp.neu.f32 	%p80, %f412, 0f7F800000;
	@%p80 bra 	$L__BB0_67;

	selp.f32 	%f2033, 0fFF800000, 0f7F800000, %p3;

$L__BB0_67:
	mul.f32 	%f1035, %f2033, 0f437F0000;
	setp.eq.f32 	%p81, %f410, 0f3F800000;
	selp.f32 	%f1036, 0f437F0000, %f1035, %p81;
	cvt.rzi.u32.f32 	%r326, %f1036;
	shl.b64 	%rd101, %rd20, 1;
	add.s64 	%rd102, %rd19, %rd101;
	cvt.u16.u32 	%rs16, %r326;
	mov.u16 	%rs17, 255;
	st.global.v2.u8 	[%rd102], {%rs16, %rs17};

$L__BB0_68:
	ld.const.v2.f32 	{%f1037, %f1038}, [params+648];
	mul.f32 	%f425, %f2027, %f1037;
	mul.f32 	%f426, %f2028, %f1038;
	ld.const.f32 	%f427, [params+656];
	mul.f32 	%f428, %f2029, %f427;
	and.b32  	%r327, %r53, 1;
	setp.eq.b32 	%p82, %r327, 1;
	mov.pred 	%p83, 0;
	xor.pred  	%p84, %p82, %p83;
	not.pred 	%p85, %p84;
	@%p85 bra 	$L__BB0_142;

	mov.f32 	%f1040, 0f3E666666;
	cvt.rzi.f32.f32 	%f1041, %f1040;
	add.f32 	%f1042, %f1041, %f1041;
	mov.f32 	%f1043, 0f3EE66666;
	sub.f32 	%f1044, %f1043, %f1042;
	abs.f32 	%f429, %f1044;
	abs.f32 	%f430, %f425;
	setp.lt.f32 	%p86, %f430, 0f00800000;
	mul.f32 	%f1045, %f430, 0f4B800000;
	selp.f32 	%f1046, %f1045, %f430, %p86;
	selp.f32 	%f1047, 0fC3170000, 0fC2FE0000, %p86;
	mov.b32 	%r328, %f1046;
	and.b32  	%r329, %r328, 8388607;
	or.b32  	%r330, %r329, 1065353216;
	mov.b32 	%f1048, %r330;
	shr.u32 	%r331, %r328, 23;
	cvt.rn.f32.u32 	%f1049, %r331;
	add.f32 	%f1050, %f1047, %f1049;
	setp.gt.f32 	%p87, %f1048, 0f3FB504F3;
	mul.f32 	%f1051, %f1048, 0f3F000000;
	add.f32 	%f1052, %f1050, 0f3F800000;
	selp.f32 	%f1053, %f1052, %f1050, %p87;
	selp.f32 	%f1054, %f1051, %f1048, %p87;
	add.f32 	%f1055, %f1054, 0fBF800000;
	add.f32 	%f1056, %f1054, 0f3F800000;
	rcp.approx.ftz.f32 	%f1057, %f1056;
	add.f32 	%f1058, %f1055, %f1055;
	mul.f32 	%f1059, %f1058, %f1057;
	mul.f32 	%f1060, %f1059, %f1059;
	mov.f32 	%f1061, 0f3C4CAF63;
	mov.f32 	%f1062, 0f3B18F0FE;
	fma.rn.f32 	%f1063, %f1062, %f1060, %f1061;
	mov.f32 	%f1064, 0f3DAAAABD;
	fma.rn.f32 	%f1065, %f1063, %f1060, %f1064;
	mul.rn.f32 	%f1066, %f1065, %f1060;
	mul.rn.f32 	%f1067, %f1066, %f1059;
	sub.f32 	%f1068, %f1055, %f1059;
	add.f32 	%f1069, %f1068, %f1068;
	neg.f32 	%f1070, %f1059;
	fma.rn.f32 	%f1071, %f1070, %f1055, %f1069;
	mul.rn.f32 	%f1072, %f1057, %f1071;
	add.f32 	%f1073, %f1067, %f1059;
	sub.f32 	%f1074, %f1059, %f1073;
	add.f32 	%f1075, %f1067, %f1074;
	add.f32 	%f1076, %f1072, %f1075;
	add.f32 	%f1077, %f1073, %f1076;
	sub.f32 	%f1078, %f1073, %f1077;
	add.f32 	%f1079, %f1076, %f1078;
	mov.f32 	%f1080, 0f3F317200;
	mul.rn.f32 	%f1081, %f1053, %f1080;
	mov.f32 	%f1082, 0f35BFBE8E;
	mul.rn.f32 	%f1083, %f1053, %f1082;
	add.f32 	%f1084, %f1081, %f1077;
	sub.f32 	%f1085, %f1081, %f1084;
	add.f32 	%f1086, %f1077, %f1085;
	add.f32 	%f1087, %f1079, %f1086;
	add.f32 	%f1088, %f1083, %f1087;
	add.f32 	%f1089, %f1084, %f1088;
	sub.f32 	%f1090, %f1084, %f1089;
	add.f32 	%f1091, %f1088, %f1090;
	mul.rn.f32 	%f1092, %f1043, %f1089;
	neg.f32 	%f1093, %f1092;
	fma.rn.f32 	%f1094, %f1043, %f1089, %f1093;
	fma.rn.f32 	%f1095, %f1043, %f1091, %f1094;
	mov.f32 	%f1096, 0f00000000;
	fma.rn.f32 	%f1097, %f1096, %f1089, %f1095;
	add.rn.f32 	%f1098, %f1092, %f1097;
	neg.f32 	%f1099, %f1098;
	add.rn.f32 	%f1100, %f1092, %f1099;
	add.rn.f32 	%f1101, %f1100, %f1097;
	mov.b32 	%r332, %f1098;
	setp.eq.s32 	%p88, %r332, 1118925336;
	add.s32 	%r333, %r332, -1;
	mov.b32 	%f1102, %r333;
	add.f32 	%f1103, %f1101, 0f37000000;
	selp.f32 	%f431, %f1103, %f1101, %p88;
	selp.f32 	%f1104, %f1102, %f1098, %p88;
	mov.f32 	%f1105, 0f3FB8AA3B;
	mul.rn.f32 	%f1106, %f1104, %f1105;
	cvt.rzi.f32.f32 	%f1107, %f1106;
	abs.f32 	%f1108, %f1107;
	setp.gt.f32 	%p89, %f1108, 0f42FC0000;
	mov.b32 	%r334, %f1107;
	and.b32  	%r335, %r334, -2147483648;
	or.b32  	%r336, %r335, 1123811328;
	mov.b32 	%f1109, %r336;
	selp.f32 	%f1110, %f1109, %f1107, %p89;
	mov.f32 	%f1111, 0fBF317218;
	fma.rn.f32 	%f1112, %f1110, %f1111, %f1104;
	mov.f32 	%f1113, 0f3102E308;
	fma.rn.f32 	%f1114, %f1110, %f1113, %f1112;
	mul.f32 	%f1115, %f1114, 0f3FB8AA3B;
	add.f32 	%f1116, %f1110, 0f4B40007F;
	mov.b32 	%r337, %f1116;
	shl.b32 	%r338, %r337, 23;
	mov.b32 	%f1117, %r338;
	ex2.approx.ftz.f32 	%f1118, %f1115;
	mul.f32 	%f432, %f1118, %f1117;
	setp.eq.f32 	%p90, %f432, 0f7F800000;
	mov.f32 	%f2034, 0f7F800000;
	@%p90 bra 	$L__BB0_71;

	fma.rn.f32 	%f2034, %f432, %f431, %f432;

$L__BB0_71:
	setp.lt.f32 	%p91, %f425, 0f00000000;
	setp.eq.f32 	%p92, %f429, 0f3F800000;
	and.pred  	%p4, %p91, %p92;
	setp.eq.f32 	%p93, %f425, 0f00000000;
	@%p93 bra 	$L__BB0_75;
	bra.uni 	$L__BB0_72;

$L__BB0_75:
	add.f32 	%f1123, %f425, %f425;
	selp.f32 	%f2036, %f1123, 0f00000000, %p92;
	bra.uni 	$L__BB0_76;

$L__BB0_72:
	mov.b32 	%r339, %f2034;
	xor.b32  	%r340, %r339, -2147483648;
	mov.b32 	%f1119, %r340;
	selp.f32 	%f2036, %f1119, %f2034, %p4;
	setp.geu.f32 	%p94, %f425, 0f00000000;
	@%p94 bra 	$L__BB0_76;

	mov.f32 	%f1120, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1121, %f1120;
	setp.eq.f32 	%p95, %f1121, 0f3EE66666;
	@%p95 bra 	$L__BB0_76;

	mov.f32 	%f2036, 0f7FFFFFFF;

$L__BB0_76:
	add.f32 	%f1124, %f430, 0f3EE66666;
	mov.b32 	%r341, %f1124;
	setp.lt.s32 	%p97, %r341, 2139095040;
	@%p97 bra 	$L__BB0_81;

	setp.gtu.f32 	%p98, %f430, 0f7F800000;
	@%p98 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_78;

$L__BB0_80:
	add.f32 	%f2036, %f425, 0f3EE66666;
	bra.uni 	$L__BB0_81;

$L__BB0_78:
	setp.neu.f32 	%p99, %f430, 0f7F800000;
	@%p99 bra 	$L__BB0_81;

	selp.f32 	%f2036, 0fFF800000, 0f7F800000, %p4;

$L__BB0_81:
	setp.eq.f32 	%p100, %f425, 0f3F800000;
	selp.f32 	%f441, 0f3F800000, %f2036, %p100;
	abs.f32 	%f442, %f426;
	setp.lt.f32 	%p101, %f442, 0f00800000;
	mul.f32 	%f1126, %f442, 0f4B800000;
	selp.f32 	%f1127, %f1126, %f442, %p101;
	selp.f32 	%f1128, 0fC3170000, 0fC2FE0000, %p101;
	mov.b32 	%r342, %f1127;
	and.b32  	%r343, %r342, 8388607;
	or.b32  	%r344, %r343, 1065353216;
	mov.b32 	%f1129, %r344;
	shr.u32 	%r345, %r342, 23;
	cvt.rn.f32.u32 	%f1130, %r345;
	add.f32 	%f1131, %f1128, %f1130;
	setp.gt.f32 	%p102, %f1129, 0f3FB504F3;
	mul.f32 	%f1132, %f1129, 0f3F000000;
	add.f32 	%f1133, %f1131, 0f3F800000;
	selp.f32 	%f1134, %f1133, %f1131, %p102;
	selp.f32 	%f1135, %f1132, %f1129, %p102;
	add.f32 	%f1136, %f1135, 0fBF800000;
	add.f32 	%f1137, %f1135, 0f3F800000;
	rcp.approx.ftz.f32 	%f1138, %f1137;
	add.f32 	%f1139, %f1136, %f1136;
	mul.f32 	%f1140, %f1139, %f1138;
	mul.f32 	%f1141, %f1140, %f1140;
	mov.f32 	%f1142, 0f3C4CAF63;
	mov.f32 	%f1143, 0f3B18F0FE;
	fma.rn.f32 	%f1144, %f1143, %f1141, %f1142;
	mov.f32 	%f1145, 0f3DAAAABD;
	fma.rn.f32 	%f1146, %f1144, %f1141, %f1145;
	mul.rn.f32 	%f1147, %f1146, %f1141;
	mul.rn.f32 	%f1148, %f1147, %f1140;
	sub.f32 	%f1149, %f1136, %f1140;
	add.f32 	%f1150, %f1149, %f1149;
	neg.f32 	%f1151, %f1140;
	fma.rn.f32 	%f1152, %f1151, %f1136, %f1150;
	mul.rn.f32 	%f1153, %f1138, %f1152;
	add.f32 	%f1154, %f1148, %f1140;
	sub.f32 	%f1155, %f1140, %f1154;
	add.f32 	%f1156, %f1148, %f1155;
	add.f32 	%f1157, %f1153, %f1156;
	add.f32 	%f1158, %f1154, %f1157;
	sub.f32 	%f1159, %f1154, %f1158;
	add.f32 	%f1160, %f1157, %f1159;
	mov.f32 	%f1161, 0f3F317200;
	mul.rn.f32 	%f1162, %f1134, %f1161;
	mov.f32 	%f1163, 0f35BFBE8E;
	mul.rn.f32 	%f1164, %f1134, %f1163;
	add.f32 	%f1165, %f1162, %f1158;
	sub.f32 	%f1166, %f1162, %f1165;
	add.f32 	%f1167, %f1158, %f1166;
	add.f32 	%f1168, %f1160, %f1167;
	add.f32 	%f1169, %f1164, %f1168;
	add.f32 	%f1170, %f1165, %f1169;
	sub.f32 	%f1171, %f1165, %f1170;
	add.f32 	%f1172, %f1169, %f1171;
	mov.f32 	%f1173, 0f3EE66666;
	mul.rn.f32 	%f1174, %f1173, %f1170;
	neg.f32 	%f1175, %f1174;
	fma.rn.f32 	%f1176, %f1173, %f1170, %f1175;
	fma.rn.f32 	%f1177, %f1173, %f1172, %f1176;
	mov.f32 	%f1178, 0f00000000;
	fma.rn.f32 	%f1179, %f1178, %f1170, %f1177;
	add.rn.f32 	%f1180, %f1174, %f1179;
	neg.f32 	%f1181, %f1180;
	add.rn.f32 	%f1182, %f1174, %f1181;
	add.rn.f32 	%f1183, %f1182, %f1179;
	mov.b32 	%r346, %f1180;
	setp.eq.s32 	%p103, %r346, 1118925336;
	add.s32 	%r347, %r346, -1;
	mov.b32 	%f1184, %r347;
	add.f32 	%f1185, %f1183, 0f37000000;
	selp.f32 	%f443, %f1185, %f1183, %p103;
	selp.f32 	%f1186, %f1184, %f1180, %p103;
	mov.f32 	%f1187, 0f3FB8AA3B;
	mul.rn.f32 	%f1188, %f1186, %f1187;
	cvt.rzi.f32.f32 	%f1189, %f1188;
	abs.f32 	%f1190, %f1189;
	setp.gt.f32 	%p104, %f1190, 0f42FC0000;
	mov.b32 	%r348, %f1189;
	and.b32  	%r349, %r348, -2147483648;
	or.b32  	%r350, %r349, 1123811328;
	mov.b32 	%f1191, %r350;
	selp.f32 	%f1192, %f1191, %f1189, %p104;
	mov.f32 	%f1193, 0fBF317218;
	fma.rn.f32 	%f1194, %f1192, %f1193, %f1186;
	mov.f32 	%f1195, 0f3102E308;
	fma.rn.f32 	%f1196, %f1192, %f1195, %f1194;
	mul.f32 	%f1197, %f1196, 0f3FB8AA3B;
	add.f32 	%f1198, %f1192, 0f4B40007F;
	mov.b32 	%r351, %f1198;
	shl.b32 	%r352, %r351, 23;
	mov.b32 	%f1199, %r352;
	ex2.approx.ftz.f32 	%f1200, %f1197;
	mul.f32 	%f444, %f1200, %f1199;
	setp.eq.f32 	%p105, %f444, 0f7F800000;
	mov.f32 	%f2037, 0f7F800000;
	@%p105 bra 	$L__BB0_83;

	fma.rn.f32 	%f2037, %f444, %f443, %f444;

$L__BB0_83:
	setp.lt.f32 	%p106, %f426, 0f00000000;
	and.pred  	%p5, %p106, %p92;
	setp.eq.f32 	%p108, %f426, 0f00000000;
	@%p108 bra 	$L__BB0_87;
	bra.uni 	$L__BB0_84;

$L__BB0_87:
	add.f32 	%f1205, %f426, %f426;
	selp.f32 	%f2039, %f1205, 0f00000000, %p92;
	bra.uni 	$L__BB0_88;

$L__BB0_84:
	mov.b32 	%r353, %f2037;
	xor.b32  	%r354, %r353, -2147483648;
	mov.b32 	%f1201, %r354;
	selp.f32 	%f2039, %f1201, %f2037, %p5;
	setp.geu.f32 	%p109, %f426, 0f00000000;
	@%p109 bra 	$L__BB0_88;

	mov.f32 	%f1202, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1203, %f1202;
	setp.eq.f32 	%p110, %f1203, 0f3EE66666;
	@%p110 bra 	$L__BB0_88;

	mov.f32 	%f2039, 0f7FFFFFFF;

$L__BB0_88:
	add.f32 	%f1206, %f442, 0f3EE66666;
	mov.b32 	%r355, %f1206;
	setp.lt.s32 	%p112, %r355, 2139095040;
	@%p112 bra 	$L__BB0_93;

	setp.gtu.f32 	%p113, %f442, 0f7F800000;
	@%p113 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_90;

$L__BB0_92:
	add.f32 	%f2039, %f426, 0f3EE66666;
	bra.uni 	$L__BB0_93;

$L__BB0_90:
	setp.neu.f32 	%p114, %f442, 0f7F800000;
	@%p114 bra 	$L__BB0_93;

	selp.f32 	%f2039, 0fFF800000, 0f7F800000, %p5;

$L__BB0_93:
	setp.eq.f32 	%p115, %f426, 0f3F800000;
	selp.f32 	%f453, 0f3F800000, %f2039, %p115;
	abs.f32 	%f454, %f428;
	setp.lt.f32 	%p116, %f454, 0f00800000;
	mul.f32 	%f1208, %f454, 0f4B800000;
	selp.f32 	%f1209, %f1208, %f454, %p116;
	selp.f32 	%f1210, 0fC3170000, 0fC2FE0000, %p116;
	mov.b32 	%r356, %f1209;
	and.b32  	%r357, %r356, 8388607;
	or.b32  	%r358, %r357, 1065353216;
	mov.b32 	%f1211, %r358;
	shr.u32 	%r359, %r356, 23;
	cvt.rn.f32.u32 	%f1212, %r359;
	add.f32 	%f1213, %f1210, %f1212;
	setp.gt.f32 	%p117, %f1211, 0f3FB504F3;
	mul.f32 	%f1214, %f1211, 0f3F000000;
	add.f32 	%f1215, %f1213, 0f3F800000;
	selp.f32 	%f1216, %f1215, %f1213, %p117;
	selp.f32 	%f1217, %f1214, %f1211, %p117;
	add.f32 	%f1218, %f1217, 0fBF800000;
	add.f32 	%f1219, %f1217, 0f3F800000;
	rcp.approx.ftz.f32 	%f1220, %f1219;
	add.f32 	%f1221, %f1218, %f1218;
	mul.f32 	%f1222, %f1221, %f1220;
	mul.f32 	%f1223, %f1222, %f1222;
	mov.f32 	%f1224, 0f3C4CAF63;
	mov.f32 	%f1225, 0f3B18F0FE;
	fma.rn.f32 	%f1226, %f1225, %f1223, %f1224;
	mov.f32 	%f1227, 0f3DAAAABD;
	fma.rn.f32 	%f1228, %f1226, %f1223, %f1227;
	mul.rn.f32 	%f1229, %f1228, %f1223;
	mul.rn.f32 	%f1230, %f1229, %f1222;
	sub.f32 	%f1231, %f1218, %f1222;
	add.f32 	%f1232, %f1231, %f1231;
	neg.f32 	%f1233, %f1222;
	fma.rn.f32 	%f1234, %f1233, %f1218, %f1232;
	mul.rn.f32 	%f1235, %f1220, %f1234;
	add.f32 	%f1236, %f1230, %f1222;
	sub.f32 	%f1237, %f1222, %f1236;
	add.f32 	%f1238, %f1230, %f1237;
	add.f32 	%f1239, %f1235, %f1238;
	add.f32 	%f1240, %f1236, %f1239;
	sub.f32 	%f1241, %f1236, %f1240;
	add.f32 	%f1242, %f1239, %f1241;
	mov.f32 	%f1243, 0f3F317200;
	mul.rn.f32 	%f1244, %f1216, %f1243;
	mov.f32 	%f1245, 0f35BFBE8E;
	mul.rn.f32 	%f1246, %f1216, %f1245;
	add.f32 	%f1247, %f1244, %f1240;
	sub.f32 	%f1248, %f1244, %f1247;
	add.f32 	%f1249, %f1240, %f1248;
	add.f32 	%f1250, %f1242, %f1249;
	add.f32 	%f1251, %f1246, %f1250;
	add.f32 	%f1252, %f1247, %f1251;
	sub.f32 	%f1253, %f1247, %f1252;
	add.f32 	%f1254, %f1251, %f1253;
	mov.f32 	%f1255, 0f3EE66666;
	mul.rn.f32 	%f1256, %f1255, %f1252;
	neg.f32 	%f1257, %f1256;
	fma.rn.f32 	%f1258, %f1255, %f1252, %f1257;
	fma.rn.f32 	%f1259, %f1255, %f1254, %f1258;
	mov.f32 	%f1260, 0f00000000;
	fma.rn.f32 	%f1261, %f1260, %f1252, %f1259;
	add.rn.f32 	%f1262, %f1256, %f1261;
	neg.f32 	%f1263, %f1262;
	add.rn.f32 	%f1264, %f1256, %f1263;
	add.rn.f32 	%f1265, %f1264, %f1261;
	mov.b32 	%r360, %f1262;
	setp.eq.s32 	%p118, %r360, 1118925336;
	add.s32 	%r361, %r360, -1;
	mov.b32 	%f1266, %r361;
	add.f32 	%f1267, %f1265, 0f37000000;
	selp.f32 	%f455, %f1267, %f1265, %p118;
	selp.f32 	%f1268, %f1266, %f1262, %p118;
	mov.f32 	%f1269, 0f3FB8AA3B;
	mul.rn.f32 	%f1270, %f1268, %f1269;
	cvt.rzi.f32.f32 	%f1271, %f1270;
	abs.f32 	%f1272, %f1271;
	setp.gt.f32 	%p119, %f1272, 0f42FC0000;
	mov.b32 	%r362, %f1271;
	and.b32  	%r363, %r362, -2147483648;
	or.b32  	%r364, %r363, 1123811328;
	mov.b32 	%f1273, %r364;
	selp.f32 	%f1274, %f1273, %f1271, %p119;
	mov.f32 	%f1275, 0fBF317218;
	fma.rn.f32 	%f1276, %f1274, %f1275, %f1268;
	mov.f32 	%f1277, 0f3102E308;
	fma.rn.f32 	%f1278, %f1274, %f1277, %f1276;
	mul.f32 	%f1279, %f1278, 0f3FB8AA3B;
	add.f32 	%f1280, %f1274, 0f4B40007F;
	mov.b32 	%r365, %f1280;
	shl.b32 	%r366, %r365, 23;
	mov.b32 	%f1281, %r366;
	ex2.approx.ftz.f32 	%f1282, %f1279;
	mul.f32 	%f456, %f1282, %f1281;
	setp.eq.f32 	%p120, %f456, 0f7F800000;
	mov.f32 	%f2040, 0f7F800000;
	@%p120 bra 	$L__BB0_95;

	fma.rn.f32 	%f2040, %f456, %f455, %f456;

$L__BB0_95:
	setp.lt.f32 	%p121, %f428, 0f00000000;
	and.pred  	%p6, %p121, %p92;
	setp.eq.f32 	%p123, %f428, 0f00000000;
	@%p123 bra 	$L__BB0_99;
	bra.uni 	$L__BB0_96;

$L__BB0_99:
	add.f32 	%f1287, %f428, %f428;
	selp.f32 	%f2042, %f1287, 0f00000000, %p92;
	bra.uni 	$L__BB0_100;

$L__BB0_96:
	mov.b32 	%r367, %f2040;
	xor.b32  	%r368, %r367, -2147483648;
	mov.b32 	%f1283, %r368;
	selp.f32 	%f2042, %f1283, %f2040, %p6;
	setp.geu.f32 	%p124, %f428, 0f00000000;
	@%p124 bra 	$L__BB0_100;

	mov.f32 	%f1284, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1285, %f1284;
	setp.eq.f32 	%p125, %f1285, 0f3EE66666;
	@%p125 bra 	$L__BB0_100;

	mov.f32 	%f2042, 0f7FFFFFFF;

$L__BB0_100:
	add.f32 	%f1288, %f454, 0f3EE66666;
	mov.b32 	%r369, %f1288;
	setp.lt.s32 	%p127, %r369, 2139095040;
	@%p127 bra 	$L__BB0_105;

	setp.gtu.f32 	%p128, %f454, 0f7F800000;
	@%p128 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_102;

$L__BB0_104:
	add.f32 	%f2042, %f428, 0f3EE66666;
	bra.uni 	$L__BB0_105;

$L__BB0_102:
	setp.neu.f32 	%p129, %f454, 0f7F800000;
	@%p129 bra 	$L__BB0_105;

	selp.f32 	%f2042, 0fFF800000, 0f7F800000, %p6;

$L__BB0_105:
	setp.eq.f32 	%p130, %f428, 0f3F800000;
	mov.f32 	%f1290, 0f3F800000;
	selp.f32 	%f1291, 0f3F800000, %f2042, %p130;
	ld.const.u64 	%rd103, [params+144];
	cvta.to.global.u64 	%rd21, %rd103;
	ld.const.u32 	%r370, [params+136];
	mad.lo.s32 	%r371, %r370, %r7, %r6;
	cvt.u64.u32 	%rd22, %r371;
	min.f32 	%f1292, %f441, %f1290;
	mov.f32 	%f1293, 0f00000000;
	max.f32 	%f465, %f1293, %f1292;
	min.f32 	%f1294, %f453, %f1290;
	max.f32 	%f466, %f1293, %f1294;
	min.f32 	%f1295, %f1291, %f1290;
	max.f32 	%f467, %f1293, %f1295;
	mov.f32 	%f1296, 0f3E555555;
	cvt.rzi.f32.f32 	%f1297, %f1296;
	add.f32 	%f1298, %f1297, %f1297;
	mov.f32 	%f1299, 0f3ED55555;
	sub.f32 	%f1300, %f1299, %f1298;
	abs.f32 	%f468, %f1300;
	abs.f32 	%f469, %f465;
	setp.lt.f32 	%p131, %f469, 0f00800000;
	mul.f32 	%f1301, %f469, 0f4B800000;
	selp.f32 	%f1302, %f1301, %f469, %p131;
	selp.f32 	%f1303, 0fC3170000, 0fC2FE0000, %p131;
	mov.b32 	%r372, %f1302;
	and.b32  	%r373, %r372, 8388607;
	or.b32  	%r374, %r373, 1065353216;
	mov.b32 	%f1304, %r374;
	shr.u32 	%r375, %r372, 23;
	cvt.rn.f32.u32 	%f1305, %r375;
	add.f32 	%f1306, %f1303, %f1305;
	setp.gt.f32 	%p132, %f1304, 0f3FB504F3;
	mul.f32 	%f1307, %f1304, 0f3F000000;
	add.f32 	%f1308, %f1306, 0f3F800000;
	selp.f32 	%f1309, %f1308, %f1306, %p132;
	selp.f32 	%f1310, %f1307, %f1304, %p132;
	add.f32 	%f1311, %f1310, 0fBF800000;
	add.f32 	%f1312, %f1310, 0f3F800000;
	rcp.approx.ftz.f32 	%f1313, %f1312;
	add.f32 	%f1314, %f1311, %f1311;
	mul.f32 	%f1315, %f1314, %f1313;
	mul.f32 	%f1316, %f1315, %f1315;
	mov.f32 	%f1317, 0f3C4CAF63;
	mov.f32 	%f1318, 0f3B18F0FE;
	fma.rn.f32 	%f1319, %f1318, %f1316, %f1317;
	mov.f32 	%f1320, 0f3DAAAABD;
	fma.rn.f32 	%f1321, %f1319, %f1316, %f1320;
	mul.rn.f32 	%f1322, %f1321, %f1316;
	mul.rn.f32 	%f1323, %f1322, %f1315;
	sub.f32 	%f1324, %f1311, %f1315;
	add.f32 	%f1325, %f1324, %f1324;
	neg.f32 	%f1326, %f1315;
	fma.rn.f32 	%f1327, %f1326, %f1311, %f1325;
	mul.rn.f32 	%f1328, %f1313, %f1327;
	add.f32 	%f1329, %f1323, %f1315;
	sub.f32 	%f1330, %f1315, %f1329;
	add.f32 	%f1331, %f1323, %f1330;
	add.f32 	%f1332, %f1328, %f1331;
	add.f32 	%f1333, %f1329, %f1332;
	sub.f32 	%f1334, %f1329, %f1333;
	add.f32 	%f1335, %f1332, %f1334;
	mov.f32 	%f1336, 0f3F317200;
	mul.rn.f32 	%f1337, %f1309, %f1336;
	mov.f32 	%f1338, 0f35BFBE8E;
	mul.rn.f32 	%f1339, %f1309, %f1338;
	add.f32 	%f1340, %f1337, %f1333;
	sub.f32 	%f1341, %f1337, %f1340;
	add.f32 	%f1342, %f1333, %f1341;
	add.f32 	%f1343, %f1335, %f1342;
	add.f32 	%f1344, %f1339, %f1343;
	add.f32 	%f1345, %f1340, %f1344;
	sub.f32 	%f1346, %f1340, %f1345;
	add.f32 	%f1347, %f1344, %f1346;
	mul.rn.f32 	%f1348, %f1299, %f1345;
	neg.f32 	%f1349, %f1348;
	fma.rn.f32 	%f1350, %f1299, %f1345, %f1349;
	fma.rn.f32 	%f1351, %f1299, %f1347, %f1350;
	fma.rn.f32 	%f1352, %f1293, %f1345, %f1351;
	add.rn.f32 	%f1353, %f1348, %f1352;
	neg.f32 	%f1354, %f1353;
	add.rn.f32 	%f1355, %f1348, %f1354;
	add.rn.f32 	%f1356, %f1355, %f1352;
	mov.b32 	%r376, %f1353;
	setp.eq.s32 	%p133, %r376, 1118925336;
	add.s32 	%r377, %r376, -1;
	mov.b32 	%f1357, %r377;
	add.f32 	%f1358, %f1356, 0f37000000;
	selp.f32 	%f470, %f1358, %f1356, %p133;
	selp.f32 	%f1359, %f1357, %f1353, %p133;
	mov.f32 	%f1360, 0f3FB8AA3B;
	mul.rn.f32 	%f1361, %f1359, %f1360;
	cvt.rzi.f32.f32 	%f1362, %f1361;
	abs.f32 	%f1363, %f1362;
	setp.gt.f32 	%p134, %f1363, 0f42FC0000;
	mov.b32 	%r378, %f1362;
	and.b32  	%r379, %r378, -2147483648;
	or.b32  	%r380, %r379, 1123811328;
	mov.b32 	%f1364, %r380;
	selp.f32 	%f1365, %f1364, %f1362, %p134;
	mov.f32 	%f1366, 0fBF317218;
	fma.rn.f32 	%f1367, %f1365, %f1366, %f1359;
	mov.f32 	%f1368, 0f3102E308;
	fma.rn.f32 	%f1369, %f1365, %f1368, %f1367;
	mul.f32 	%f1370, %f1369, 0f3FB8AA3B;
	add.f32 	%f1371, %f1365, 0f4B40007F;
	mov.b32 	%r381, %f1371;
	shl.b32 	%r382, %r381, 23;
	mov.b32 	%f1372, %r382;
	ex2.approx.ftz.f32 	%f1373, %f1370;
	mul.f32 	%f471, %f1373, %f1372;
	setp.eq.f32 	%p135, %f471, 0f7F800000;
	mov.f32 	%f2043, 0f7F800000;
	@%p135 bra 	$L__BB0_107;

	fma.rn.f32 	%f2043, %f471, %f470, %f471;

$L__BB0_107:
	setp.lt.f32 	%p136, %f465, 0f00000000;
	setp.eq.f32 	%p137, %f468, 0f3F800000;
	and.pred  	%p7, %p136, %p137;
	setp.eq.f32 	%p138, %f465, 0f00000000;
	@%p138 bra 	$L__BB0_111;
	bra.uni 	$L__BB0_108;

$L__BB0_111:
	add.f32 	%f1378, %f465, %f465;
	selp.f32 	%f2045, %f1378, 0f00000000, %p137;
	bra.uni 	$L__BB0_112;

$L__BB0_108:
	mov.b32 	%r383, %f2043;
	xor.b32  	%r384, %r383, -2147483648;
	mov.b32 	%f1374, %r384;
	selp.f32 	%f2045, %f1374, %f2043, %p7;
	setp.geu.f32 	%p139, %f465, 0f00000000;
	@%p139 bra 	$L__BB0_112;

	mov.f32 	%f1375, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1376, %f1375;
	setp.eq.f32 	%p140, %f1376, 0f3ED55555;
	@%p140 bra 	$L__BB0_112;

	mov.f32 	%f2045, 0f7FFFFFFF;

$L__BB0_112:
	add.f32 	%f1379, %f469, 0f3ED55555;
	mov.b32 	%r385, %f1379;
	setp.lt.s32 	%p142, %r385, 2139095040;
	@%p142 bra 	$L__BB0_117;

	setp.gtu.f32 	%p143, %f469, 0f7F800000;
	@%p143 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_114;

$L__BB0_116:
	add.f32 	%f2045, %f465, 0f3ED55555;
	bra.uni 	$L__BB0_117;

$L__BB0_114:
	setp.neu.f32 	%p144, %f469, 0f7F800000;
	@%p144 bra 	$L__BB0_117;

	selp.f32 	%f2045, 0fFF800000, 0f7F800000, %p7;

$L__BB0_117:
	abs.f32 	%f480, %f466;
	setp.lt.f32 	%p145, %f480, 0f00800000;
	mul.f32 	%f1381, %f480, 0f4B800000;
	selp.f32 	%f1382, %f1381, %f480, %p145;
	selp.f32 	%f1383, 0fC3170000, 0fC2FE0000, %p145;
	mov.b32 	%r386, %f1382;
	and.b32  	%r387, %r386, 8388607;
	or.b32  	%r388, %r387, 1065353216;
	mov.b32 	%f1384, %r388;
	shr.u32 	%r389, %r386, 23;
	cvt.rn.f32.u32 	%f1385, %r389;
	add.f32 	%f1386, %f1383, %f1385;
	setp.gt.f32 	%p146, %f1384, 0f3FB504F3;
	mul.f32 	%f1387, %f1384, 0f3F000000;
	add.f32 	%f1388, %f1386, 0f3F800000;
	selp.f32 	%f1389, %f1388, %f1386, %p146;
	selp.f32 	%f1390, %f1387, %f1384, %p146;
	add.f32 	%f1391, %f1390, 0fBF800000;
	add.f32 	%f1392, %f1390, 0f3F800000;
	rcp.approx.ftz.f32 	%f1393, %f1392;
	add.f32 	%f1394, %f1391, %f1391;
	mul.f32 	%f1395, %f1394, %f1393;
	mul.f32 	%f1396, %f1395, %f1395;
	mov.f32 	%f1397, 0f3C4CAF63;
	mov.f32 	%f1398, 0f3B18F0FE;
	fma.rn.f32 	%f1399, %f1398, %f1396, %f1397;
	mov.f32 	%f1400, 0f3DAAAABD;
	fma.rn.f32 	%f1401, %f1399, %f1396, %f1400;
	mul.rn.f32 	%f1402, %f1401, %f1396;
	mul.rn.f32 	%f1403, %f1402, %f1395;
	sub.f32 	%f1404, %f1391, %f1395;
	add.f32 	%f1405, %f1404, %f1404;
	neg.f32 	%f1406, %f1395;
	fma.rn.f32 	%f1407, %f1406, %f1391, %f1405;
	mul.rn.f32 	%f1408, %f1393, %f1407;
	add.f32 	%f1409, %f1403, %f1395;
	sub.f32 	%f1410, %f1395, %f1409;
	add.f32 	%f1411, %f1403, %f1410;
	add.f32 	%f1412, %f1408, %f1411;
	add.f32 	%f1413, %f1409, %f1412;
	sub.f32 	%f1414, %f1409, %f1413;
	add.f32 	%f1415, %f1412, %f1414;
	mov.f32 	%f1416, 0f3F317200;
	mul.rn.f32 	%f1417, %f1389, %f1416;
	mov.f32 	%f1418, 0f35BFBE8E;
	mul.rn.f32 	%f1419, %f1389, %f1418;
	add.f32 	%f1420, %f1417, %f1413;
	sub.f32 	%f1421, %f1417, %f1420;
	add.f32 	%f1422, %f1413, %f1421;
	add.f32 	%f1423, %f1415, %f1422;
	add.f32 	%f1424, %f1419, %f1423;
	add.f32 	%f1425, %f1420, %f1424;
	sub.f32 	%f1426, %f1420, %f1425;
	add.f32 	%f1427, %f1424, %f1426;
	mov.f32 	%f1428, 0f3ED55555;
	mul.rn.f32 	%f1429, %f1428, %f1425;
	neg.f32 	%f1430, %f1429;
	fma.rn.f32 	%f1431, %f1428, %f1425, %f1430;
	fma.rn.f32 	%f1432, %f1428, %f1427, %f1431;
	mov.f32 	%f1433, 0f00000000;
	fma.rn.f32 	%f1434, %f1433, %f1425, %f1432;
	add.rn.f32 	%f1435, %f1429, %f1434;
	neg.f32 	%f1436, %f1435;
	add.rn.f32 	%f1437, %f1429, %f1436;
	add.rn.f32 	%f1438, %f1437, %f1434;
	mov.b32 	%r390, %f1435;
	setp.eq.s32 	%p147, %r390, 1118925336;
	add.s32 	%r391, %r390, -1;
	mov.b32 	%f1439, %r391;
	add.f32 	%f1440, %f1438, 0f37000000;
	selp.f32 	%f481, %f1440, %f1438, %p147;
	selp.f32 	%f1441, %f1439, %f1435, %p147;
	mov.f32 	%f1442, 0f3FB8AA3B;
	mul.rn.f32 	%f1443, %f1441, %f1442;
	cvt.rzi.f32.f32 	%f1444, %f1443;
	abs.f32 	%f1445, %f1444;
	setp.gt.f32 	%p148, %f1445, 0f42FC0000;
	mov.b32 	%r392, %f1444;
	and.b32  	%r393, %r392, -2147483648;
	or.b32  	%r394, %r393, 1123811328;
	mov.b32 	%f1446, %r394;
	selp.f32 	%f1447, %f1446, %f1444, %p148;
	mov.f32 	%f1448, 0fBF317218;
	fma.rn.f32 	%f1449, %f1447, %f1448, %f1441;
	mov.f32 	%f1450, 0f3102E308;
	fma.rn.f32 	%f1451, %f1447, %f1450, %f1449;
	mul.f32 	%f1452, %f1451, 0f3FB8AA3B;
	add.f32 	%f1453, %f1447, 0f4B40007F;
	mov.b32 	%r395, %f1453;
	shl.b32 	%r396, %r395, 23;
	mov.b32 	%f1454, %r396;
	ex2.approx.ftz.f32 	%f1455, %f1452;
	mul.f32 	%f482, %f1455, %f1454;
	setp.eq.f32 	%p149, %f482, 0f7F800000;
	mov.f32 	%f2046, 0f7F800000;
	@%p149 bra 	$L__BB0_119;

	fma.rn.f32 	%f2046, %f482, %f481, %f482;

$L__BB0_119:
	setp.lt.f32 	%p150, %f466, 0f00000000;
	and.pred  	%p8, %p150, %p137;
	setp.eq.f32 	%p152, %f466, 0f00000000;
	@%p152 bra 	$L__BB0_123;
	bra.uni 	$L__BB0_120;

$L__BB0_123:
	add.f32 	%f1460, %f466, %f466;
	selp.f32 	%f2048, %f1460, 0f00000000, %p137;
	bra.uni 	$L__BB0_124;

$L__BB0_120:
	mov.b32 	%r397, %f2046;
	xor.b32  	%r398, %r397, -2147483648;
	mov.b32 	%f1456, %r398;
	selp.f32 	%f2048, %f1456, %f2046, %p8;
	setp.geu.f32 	%p153, %f466, 0f00000000;
	@%p153 bra 	$L__BB0_124;

	mov.f32 	%f1457, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1458, %f1457;
	setp.eq.f32 	%p154, %f1458, 0f3ED55555;
	@%p154 bra 	$L__BB0_124;

	mov.f32 	%f2048, 0f7FFFFFFF;

$L__BB0_124:
	add.f32 	%f1461, %f480, 0f3ED55555;
	mov.b32 	%r399, %f1461;
	setp.lt.s32 	%p156, %r399, 2139095040;
	@%p156 bra 	$L__BB0_129;

	setp.gtu.f32 	%p157, %f480, 0f7F800000;
	@%p157 bra 	$L__BB0_128;
	bra.uni 	$L__BB0_126;

$L__BB0_128:
	add.f32 	%f2048, %f466, 0f3ED55555;
	bra.uni 	$L__BB0_129;

$L__BB0_126:
	setp.neu.f32 	%p158, %f480, 0f7F800000;
	@%p158 bra 	$L__BB0_129;

	selp.f32 	%f2048, 0fFF800000, 0f7F800000, %p8;

$L__BB0_129:
	abs.f32 	%f491, %f467;
	setp.lt.f32 	%p159, %f491, 0f00800000;
	mul.f32 	%f1463, %f491, 0f4B800000;
	selp.f32 	%f1464, %f1463, %f491, %p159;
	selp.f32 	%f1465, 0fC3170000, 0fC2FE0000, %p159;
	mov.b32 	%r400, %f1464;
	and.b32  	%r401, %r400, 8388607;
	or.b32  	%r402, %r401, 1065353216;
	mov.b32 	%f1466, %r402;
	shr.u32 	%r403, %r400, 23;
	cvt.rn.f32.u32 	%f1467, %r403;
	add.f32 	%f1468, %f1465, %f1467;
	setp.gt.f32 	%p160, %f1466, 0f3FB504F3;
	mul.f32 	%f1469, %f1466, 0f3F000000;
	add.f32 	%f1470, %f1468, 0f3F800000;
	selp.f32 	%f1471, %f1470, %f1468, %p160;
	selp.f32 	%f1472, %f1469, %f1466, %p160;
	add.f32 	%f1473, %f1472, 0fBF800000;
	add.f32 	%f1474, %f1472, 0f3F800000;
	rcp.approx.ftz.f32 	%f1475, %f1474;
	add.f32 	%f1476, %f1473, %f1473;
	mul.f32 	%f1477, %f1476, %f1475;
	mul.f32 	%f1478, %f1477, %f1477;
	mov.f32 	%f1479, 0f3C4CAF63;
	mov.f32 	%f1480, 0f3B18F0FE;
	fma.rn.f32 	%f1481, %f1480, %f1478, %f1479;
	mov.f32 	%f1482, 0f3DAAAABD;
	fma.rn.f32 	%f1483, %f1481, %f1478, %f1482;
	mul.rn.f32 	%f1484, %f1483, %f1478;
	mul.rn.f32 	%f1485, %f1484, %f1477;
	sub.f32 	%f1486, %f1473, %f1477;
	add.f32 	%f1487, %f1486, %f1486;
	neg.f32 	%f1488, %f1477;
	fma.rn.f32 	%f1489, %f1488, %f1473, %f1487;
	mul.rn.f32 	%f1490, %f1475, %f1489;
	add.f32 	%f1491, %f1485, %f1477;
	sub.f32 	%f1492, %f1477, %f1491;
	add.f32 	%f1493, %f1485, %f1492;
	add.f32 	%f1494, %f1490, %f1493;
	add.f32 	%f1495, %f1491, %f1494;
	sub.f32 	%f1496, %f1491, %f1495;
	add.f32 	%f1497, %f1494, %f1496;
	mov.f32 	%f1498, 0f3F317200;
	mul.rn.f32 	%f1499, %f1471, %f1498;
	mov.f32 	%f1500, 0f35BFBE8E;
	mul.rn.f32 	%f1501, %f1471, %f1500;
	add.f32 	%f1502, %f1499, %f1495;
	sub.f32 	%f1503, %f1499, %f1502;
	add.f32 	%f1504, %f1495, %f1503;
	add.f32 	%f1505, %f1497, %f1504;
	add.f32 	%f1506, %f1501, %f1505;
	add.f32 	%f1507, %f1502, %f1506;
	sub.f32 	%f1508, %f1502, %f1507;
	add.f32 	%f1509, %f1506, %f1508;
	mov.f32 	%f1510, 0f3ED55555;
	mul.rn.f32 	%f1511, %f1510, %f1507;
	neg.f32 	%f1512, %f1511;
	fma.rn.f32 	%f1513, %f1510, %f1507, %f1512;
	fma.rn.f32 	%f1514, %f1510, %f1509, %f1513;
	mov.f32 	%f1515, 0f00000000;
	fma.rn.f32 	%f1516, %f1515, %f1507, %f1514;
	add.rn.f32 	%f1517, %f1511, %f1516;
	neg.f32 	%f1518, %f1517;
	add.rn.f32 	%f1519, %f1511, %f1518;
	add.rn.f32 	%f1520, %f1519, %f1516;
	mov.b32 	%r404, %f1517;
	setp.eq.s32 	%p161, %r404, 1118925336;
	add.s32 	%r405, %r404, -1;
	mov.b32 	%f1521, %r405;
	add.f32 	%f1522, %f1520, 0f37000000;
	selp.f32 	%f492, %f1522, %f1520, %p161;
	selp.f32 	%f1523, %f1521, %f1517, %p161;
	mov.f32 	%f1524, 0f3FB8AA3B;
	mul.rn.f32 	%f1525, %f1523, %f1524;
	cvt.rzi.f32.f32 	%f1526, %f1525;
	abs.f32 	%f1527, %f1526;
	setp.gt.f32 	%p162, %f1527, 0f42FC0000;
	mov.b32 	%r406, %f1526;
	and.b32  	%r407, %r406, -2147483648;
	or.b32  	%r408, %r407, 1123811328;
	mov.b32 	%f1528, %r408;
	selp.f32 	%f1529, %f1528, %f1526, %p162;
	mov.f32 	%f1530, 0fBF317218;
	fma.rn.f32 	%f1531, %f1529, %f1530, %f1523;
	mov.f32 	%f1532, 0f3102E308;
	fma.rn.f32 	%f1533, %f1529, %f1532, %f1531;
	mul.f32 	%f1534, %f1533, 0f3FB8AA3B;
	add.f32 	%f1535, %f1529, 0f4B40007F;
	mov.b32 	%r409, %f1535;
	shl.b32 	%r410, %r409, 23;
	mov.b32 	%f1536, %r410;
	ex2.approx.ftz.f32 	%f1537, %f1534;
	mul.f32 	%f493, %f1537, %f1536;
	setp.eq.f32 	%p163, %f493, 0f7F800000;
	mov.f32 	%f2049, 0f7F800000;
	@%p163 bra 	$L__BB0_131;

	fma.rn.f32 	%f2049, %f493, %f492, %f493;

$L__BB0_131:
	setp.lt.f32 	%p164, %f467, 0f00000000;
	and.pred  	%p9, %p164, %p137;
	setp.eq.f32 	%p166, %f467, 0f00000000;
	@%p166 bra 	$L__BB0_135;
	bra.uni 	$L__BB0_132;

$L__BB0_135:
	add.f32 	%f1542, %f467, %f467;
	selp.f32 	%f2051, %f1542, 0f00000000, %p137;
	bra.uni 	$L__BB0_136;

$L__BB0_132:
	mov.b32 	%r411, %f2049;
	xor.b32  	%r412, %r411, -2147483648;
	mov.b32 	%f1538, %r412;
	selp.f32 	%f2051, %f1538, %f2049, %p9;
	setp.geu.f32 	%p167, %f467, 0f00000000;
	@%p167 bra 	$L__BB0_136;

	mov.f32 	%f1539, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1540, %f1539;
	setp.eq.f32 	%p168, %f1540, 0f3ED55555;
	@%p168 bra 	$L__BB0_136;

	mov.f32 	%f2051, 0f7FFFFFFF;

$L__BB0_136:
	add.f32 	%f1543, %f491, 0f3ED55555;
	mov.b32 	%r413, %f1543;
	setp.lt.s32 	%p170, %r413, 2139095040;
	@%p170 bra 	$L__BB0_141;

	setp.gtu.f32 	%p171, %f491, 0f7F800000;
	@%p171 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_138;

$L__BB0_140:
	add.f32 	%f2051, %f467, 0f3ED55555;
	bra.uni 	$L__BB0_141;

$L__BB0_138:
	setp.neu.f32 	%p172, %f491, 0f7F800000;
	@%p172 bra 	$L__BB0_141;

	selp.f32 	%f2051, 0fFF800000, 0f7F800000, %p9;

$L__BB0_141:
	fma.rn.f32 	%f1544, %f2045, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p173, %f465, 0f3F800000;
	mov.f32 	%f1545, 0f3F800000;
	selp.f32 	%f1546, 0f3F7FFFFF, %f1544, %p173;
	mul.f32 	%f1547, %f465, 0f414EB852;
	setp.lt.f32 	%p174, %f465, 0f3B4D2E1C;
	selp.f32 	%f1548, %f1547, %f1546, %p174;
	fma.rn.f32 	%f1549, %f2048, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p175, %f466, 0f3F800000;
	selp.f32 	%f1550, 0f3F7FFFFF, %f1549, %p175;
	mul.f32 	%f1551, %f466, 0f414EB852;
	setp.lt.f32 	%p176, %f466, 0f3B4D2E1C;
	selp.f32 	%f1552, %f1551, %f1550, %p176;
	fma.rn.f32 	%f1553, %f2051, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p177, %f467, 0f3F800000;
	selp.f32 	%f1554, 0f3F7FFFFF, %f1553, %p177;
	mul.f32 	%f1555, %f467, 0f414EB852;
	setp.lt.f32 	%p178, %f467, 0f3B4D2E1C;
	selp.f32 	%f1556, %f1555, %f1554, %p178;
	min.f32 	%f1557, %f1548, %f1545;
	mov.f32 	%f1558, 0f00000000;
	max.f32 	%f1559, %f1558, %f1557;
	mul.f32 	%f1560, %f1559, 0f43800000;
	cvt.rzi.u32.f32 	%r414, %f1560;
	min.u32 	%r415, %r414, 255;
	min.f32 	%f1561, %f1552, %f1545;
	max.f32 	%f1562, %f1558, %f1561;
	mul.f32 	%f1563, %f1562, 0f43800000;
	cvt.rzi.u32.f32 	%r416, %f1563;
	min.u32 	%r417, %r416, 255;
	min.f32 	%f1564, %f1556, %f1545;
	max.f32 	%f1565, %f1558, %f1564;
	mul.f32 	%f1566, %f1565, 0f43800000;
	cvt.rzi.u32.f32 	%r418, %f1566;
	min.u32 	%r419, %r418, 255;
	shl.b64 	%rd104, %rd22, 2;
	add.s64 	%rd105, %rd21, %rd104;
	cvt.u16.u32 	%rs18, %r419;
	cvt.u16.u32 	%rs19, %r417;
	cvt.u16.u32 	%rs20, %r415;
	mov.u16 	%rs21, 255;
	st.global.v4.u8 	[%rd105], {%rs20, %rs19, %rs18, %rs21};

$L__BB0_142:
	and.b32  	%r420, %r53, 4;
	setp.eq.s32 	%p179, %r420, 0;
	ld.const.u32 	%r485, [params+108];
	@%p179 bra 	$L__BB0_146;

	setp.eq.s32 	%p180, %r485, 0;
	ld.const.u64 	%rd106, [params+224];
	cvta.to.global.u64 	%rd107, %rd106;
	ld.const.u32 	%r421, [params+216];
	mad.lo.s32 	%r422, %r421, %r7, %r6;
	mul.wide.u32 	%rd108, %r422, 8;
	add.s64 	%rd23, %rd107, %rd108;
	@%p180 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs29, %rs30, %rs31, %rs32}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1567, %rs29;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1568, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1569, %rs31;}

	// end inline asm
	add.f32 	%f1570, %f425, %f1567;
	add.f32 	%f1571, %f426, %f1568;
	add.f32 	%f1572, %f428, %f1569;
	mov.f32 	%f1573, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1572;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f1571;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f1570;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1573;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs25, %rs26, %rs27, %rs28};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1577, 0f3F800000;
	mov.u32 	%r485, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1577;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f428;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f426;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f425;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs33, %rs34, %rs35, %rs36};

$L__BB0_146:
	selp.f32 	%f1578, 0f40800000, 0f3F800000, %p206;
	mul.f32 	%f1579, %f1578, %f2024;
	mul.f32 	%f1580, %f1578, %f2025;
	mul.f32 	%f1581, %f1578, %f2026;
	mul.f32 	%f1582, %f1578, %f2021;
	mul.f32 	%f1583, %f1578, %f2022;
	mul.f32 	%f1584, %f1578, %f2023;
	mul.f32 	%f1585, %f1578, %f2018;
	mul.f32 	%f1586, %f1578, %f2019;
	mul.f32 	%f1587, %f1578, %f2020;
	mul.f32 	%f1588, %f1578, %f2015;
	mul.f32 	%f1589, %f1578, %f2016;
	mul.f32 	%f1590, %f1578, %f2017;
	mul.f32 	%f1591, %f1578, %f2012;
	mul.f32 	%f1592, %f1578, %f2013;
	mul.f32 	%f1593, %f1578, %f2014;
	mul.f32 	%f1594, %f1578, %f2009;
	mul.f32 	%f1595, %f1578, %f2010;
	mul.f32 	%f1596, %f1578, %f2011;
	mul.f32 	%f1597, %f1578, %f2006;
	mul.f32 	%f1598, %f1578, %f2007;
	mul.f32 	%f1599, %f1578, %f2008;
	mul.f32 	%f1600, %f1578, %f2003;
	mul.f32 	%f1601, %f1578, %f2004;
	mul.f32 	%f1602, %f1578, %f2005;
	mul.f32 	%f1603, %f1578, %f2000;
	mul.f32 	%f1604, %f1578, %f2001;
	mul.f32 	%f1605, %f1578, %f2002;
	mul.f32 	%f1606, %f1579, %f1037;
	mul.f32 	%f1607, %f1580, %f1038;
	mul.f32 	%f1608, %f1581, %f427;
	mul.f32 	%f502, %f1582, %f1037;
	mul.f32 	%f503, %f1583, %f1038;
	mul.f32 	%f504, %f1584, %f427;
	mul.f32 	%f505, %f1585, %f1037;
	mul.f32 	%f506, %f1586, %f1038;
	mul.f32 	%f507, %f1587, %f427;
	mul.f32 	%f508, %f1588, %f1037;
	mul.f32 	%f509, %f1589, %f1038;
	mul.f32 	%f510, %f1590, %f427;
	mul.f32 	%f511, %f1591, %f1037;
	mul.f32 	%f512, %f1592, %f1038;
	mul.f32 	%f513, %f1593, %f427;
	mul.f32 	%f514, %f1594, %f1037;
	mul.f32 	%f515, %f1595, %f1038;
	mul.f32 	%f516, %f1596, %f427;
	mul.f32 	%f517, %f1597, %f1037;
	mul.f32 	%f518, %f1598, %f1038;
	mul.f32 	%f519, %f1599, %f427;
	mul.f32 	%f520, %f1600, %f1037;
	mul.f32 	%f521, %f1601, %f1038;
	mul.f32 	%f522, %f1602, %f427;
	mul.f32 	%f523, %f1603, %f1037;
	mul.f32 	%f524, %f1604, %f1038;
	mul.f32 	%f525, %f1605, %f427;
	mul.f32 	%f526, %f1606, 0f3F558750;
	mul.f32 	%f527, %f1607, 0f3F558750;
	mul.f32 	%f528, %f1608, 0f3F558750;
	ld.const.u64 	%rd109, [params+256];
	cvta.to.global.u64 	%rd110, %rd109;
	ld.const.u32 	%r424, [params+248];
	mad.lo.s32 	%r425, %r424, %r7, %r6;
	mul.wide.u32 	%rd111, %r425, 8;
	add.s64 	%rd24, %rd110, %rd111;
	setp.eq.s32 	%p181, %r485, 0;
	@%p181 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs44, %rs45, %rs46, %rs47}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1609, %rs44;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1610, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1611, %rs46;}

	// end inline asm
	add.f32 	%f1612, %f526, %f1609;
	add.f32 	%f1613, %f527, %f1610;
	add.f32 	%f1614, %f528, %f1611;
	mov.f32 	%f1615, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1614;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1613;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1612;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1615;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs40, %rs41, %rs42, %rs43};
	bra.uni 	$L__BB0_149;

$L__BB0_148:
	mov.f32 	%f1619, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1619;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f528;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f527;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f526;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs48, %rs49, %rs50, %rs51};

$L__BB0_149:
	mul.f32 	%f529, %f502, 0f3FB8EBD1;
	mul.f32 	%f530, %f503, 0f3FB8EBD1;
	mul.f32 	%f531, %f504, 0f3FB8EBD1;
	ld.const.u64 	%rd112, [params+272];
	cvta.to.global.u64 	%rd113, %rd112;
	ld.const.u32 	%r426, [params+264];
	mad.lo.s32 	%r427, %r426, %r7, %r6;
	mul.wide.u32 	%rd114, %r427, 8;
	add.s64 	%rd25, %rd113, %rd114;
	@%p181 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs59, %rs60, %rs61, %rs62}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1620, %rs59;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1621, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1622, %rs61;}

	// end inline asm
	add.f32 	%f1623, %f529, %f1620;
	add.f32 	%f1624, %f530, %f1621;
	add.f32 	%f1625, %f531, %f1622;
	mov.f32 	%f1626, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1625;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1624;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1623;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1626;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs55, %rs56, %rs57, %rs58};
	bra.uni 	$L__BB0_152;

$L__BB0_151:
	mov.f32 	%f1630, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1630;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f531;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f530;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f529;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs63, %rs64, %rs65, %rs66};

$L__BB0_152:
	mul.f32 	%f532, %f505, 0f3FB8EBD1;
	mul.f32 	%f533, %f506, 0f3FB8EBD1;
	mul.f32 	%f534, %f507, 0f3FB8EBD1;
	ld.const.u64 	%rd115, [params+288];
	cvta.to.global.u64 	%rd116, %rd115;
	ld.const.u32 	%r428, [params+280];
	mad.lo.s32 	%r429, %r428, %r7, %r6;
	mul.wide.u32 	%rd117, %r429, 8;
	add.s64 	%rd26, %rd116, %rd117;
	@%p181 bra 	$L__BB0_154;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1631, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1632, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1633, %rs76;}

	// end inline asm
	add.f32 	%f1634, %f532, %f1631;
	add.f32 	%f1635, %f533, %f1632;
	add.f32 	%f1636, %f534, %f1633;
	mov.f32 	%f1637, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1636;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1635;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1634;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1637;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_155;

$L__BB0_154:
	mov.f32 	%f1641, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1641;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f534;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f533;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f532;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_155:
	mul.f32 	%f535, %f508, 0f3FB8EBD1;
	mul.f32 	%f536, %f509, 0f3FB8EBD1;
	mul.f32 	%f537, %f510, 0f3FB8EBD1;
	ld.const.u64 	%rd118, [params+304];
	cvta.to.global.u64 	%rd119, %rd118;
	ld.const.u32 	%r430, [params+296];
	mad.lo.s32 	%r431, %r430, %r7, %r6;
	mul.wide.u32 	%rd120, %r431, 8;
	add.s64 	%rd27, %rd119, %rd120;
	@%p181 bra 	$L__BB0_157;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1642, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1643, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1644, %rs91;}

	// end inline asm
	add.f32 	%f1645, %f535, %f1642;
	add.f32 	%f1646, %f536, %f1643;
	add.f32 	%f1647, %f537, %f1644;
	mov.f32 	%f1648, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1647;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1646;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1645;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1648;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_158;

$L__BB0_157:
	mov.f32 	%f1652, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1652;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f537;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f536;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f535;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_158:
	mul.f32 	%f538, %f511, 0f404EBF87;
	mul.f32 	%f539, %f512, 0f404EBF87;
	mul.f32 	%f540, %f513, 0f404EBF87;
	ld.const.u64 	%rd121, [params+320];
	cvta.to.global.u64 	%rd122, %rd121;
	ld.const.u32 	%r432, [params+312];
	mad.lo.s32 	%r433, %r432, %r7, %r6;
	mul.wide.u32 	%rd123, %r433, 8;
	add.s64 	%rd28, %rd122, %rd123;
	@%p181 bra 	$L__BB0_160;

	ld.global.v4.u16 	{%rs104, %rs105, %rs106, %rs107}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1653, %rs104;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1654, %rs105;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1655, %rs106;}

	// end inline asm
	add.f32 	%f1656, %f538, %f1653;
	add.f32 	%f1657, %f539, %f1654;
	add.f32 	%f1658, %f540, %f1655;
	mov.f32 	%f1659, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs102, %f1658;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs101, %f1657;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1656;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1659;}

	// end inline asm
	st.global.v4.u16 	[%rd28], {%rs100, %rs101, %rs102, %rs103};
	bra.uni 	$L__BB0_161;

$L__BB0_160:
	mov.f32 	%f1663, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1663;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs110, %f540;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs109, %f539;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f538;}

	// end inline asm
	st.global.v4.u16 	[%rd28], {%rs108, %rs109, %rs110, %rs111};

$L__BB0_161:
	mul.f32 	%f541, %f514, 0f404EBF87;
	mul.f32 	%f542, %f515, 0f404EBF87;
	mul.f32 	%f543, %f516, 0f404EBF87;
	ld.const.u64 	%rd124, [params+336];
	cvta.to.global.u64 	%rd125, %rd124;
	ld.const.u32 	%r434, [params+328];
	mad.lo.s32 	%r435, %r434, %r7, %r6;
	mul.wide.u32 	%rd126, %r435, 8;
	add.s64 	%rd29, %rd125, %rd126;
	@%p181 bra 	$L__BB0_163;

	ld.global.v4.u16 	{%rs119, %rs120, %rs121, %rs122}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1664, %rs119;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1665, %rs120;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1666, %rs121;}

	// end inline asm
	add.f32 	%f1667, %f541, %f1664;
	add.f32 	%f1668, %f542, %f1665;
	add.f32 	%f1669, %f543, %f1666;
	mov.f32 	%f1670, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs117, %f1669;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs116, %f1668;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1667;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1670;}

	// end inline asm
	st.global.v4.u16 	[%rd29], {%rs115, %rs116, %rs117, %rs118};
	bra.uni 	$L__BB0_164;

$L__BB0_163:
	mov.f32 	%f1674, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1674;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs125, %f543;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs124, %f542;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f541;}

	// end inline asm
	st.global.v4.u16 	[%rd29], {%rs123, %rs124, %rs125, %rs126};

$L__BB0_164:
	mul.f32 	%f544, %f517, 0f40330C94;
	mul.f32 	%f545, %f518, 0f40330C94;
	mul.f32 	%f546, %f519, 0f40330C94;
	ld.const.u64 	%rd127, [params+352];
	cvta.to.global.u64 	%rd128, %rd127;
	ld.const.u32 	%r436, [params+344];
	mad.lo.s32 	%r437, %r436, %r7, %r6;
	mul.wide.u32 	%rd129, %r437, 8;
	add.s64 	%rd30, %rd128, %rd129;
	@%p181 bra 	$L__BB0_166;

	ld.global.v4.u16 	{%rs134, %rs135, %rs136, %rs137}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1675, %rs134;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1676, %rs135;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1677, %rs136;}

	// end inline asm
	add.f32 	%f1678, %f544, %f1675;
	add.f32 	%f1679, %f545, %f1676;
	add.f32 	%f1680, %f546, %f1677;
	mov.f32 	%f1681, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs132, %f1680;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs131, %f1679;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1678;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1681;}

	// end inline asm
	st.global.v4.u16 	[%rd30], {%rs130, %rs131, %rs132, %rs133};
	bra.uni 	$L__BB0_167;

$L__BB0_166:
	mov.f32 	%f1685, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1685;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs140, %f546;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs139, %f545;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f544;}

	// end inline asm
	st.global.v4.u16 	[%rd30], {%rs138, %rs139, %rs140, %rs141};

$L__BB0_167:
	mul.f32 	%f547, %f520, 0f404EBF87;
	mul.f32 	%f548, %f521, 0f404EBF87;
	mul.f32 	%f549, %f522, 0f404EBF87;
	ld.const.u64 	%rd130, [params+368];
	cvta.to.global.u64 	%rd131, %rd130;
	ld.const.u32 	%r438, [params+360];
	mad.lo.s32 	%r439, %r438, %r7, %r6;
	mul.wide.u32 	%rd132, %r439, 8;
	add.s64 	%rd31, %rd131, %rd132;
	@%p181 bra 	$L__BB0_169;

	ld.global.v4.u16 	{%rs149, %rs150, %rs151, %rs152}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1686, %rs149;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1687, %rs150;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1688, %rs151;}

	// end inline asm
	add.f32 	%f1689, %f547, %f1686;
	add.f32 	%f1690, %f548, %f1687;
	add.f32 	%f1691, %f549, %f1688;
	mov.f32 	%f1692, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs147, %f1691;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs146, %f1690;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1689;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1692;}

	// end inline asm
	st.global.v4.u16 	[%rd31], {%rs145, %rs146, %rs147, %rs148};
	bra.uni 	$L__BB0_170;

$L__BB0_169:
	mov.f32 	%f1696, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1696;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs155, %f549;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs154, %f548;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f547;}

	// end inline asm
	st.global.v4.u16 	[%rd31], {%rs153, %rs154, %rs155, %rs156};

$L__BB0_170:
	mul.f32 	%f550, %f523, 0f3FCEBF87;
	mul.f32 	%f551, %f524, 0f3FCEBF87;
	mul.f32 	%f552, %f525, 0f3FCEBF87;
	ld.const.u64 	%rd133, [params+384];
	cvta.to.global.u64 	%rd134, %rd133;
	ld.const.u32 	%r440, [params+376];
	mad.lo.s32 	%r441, %r440, %r7, %r6;
	mul.wide.u32 	%rd135, %r441, 8;
	add.s64 	%rd32, %rd134, %rd135;
	@%p181 bra 	$L__BB0_172;

	ld.global.v4.u16 	{%rs164, %rs165, %rs166, %rs167}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1697, %rs164;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1698, %rs165;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1699, %rs166;}

	// end inline asm
	add.f32 	%f1700, %f550, %f1697;
	add.f32 	%f1701, %f551, %f1698;
	add.f32 	%f1702, %f552, %f1699;
	mov.f32 	%f1703, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs162, %f1702;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs161, %f1701;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1700;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1703;}

	// end inline asm
	st.global.v4.u16 	[%rd32], {%rs160, %rs161, %rs162, %rs163};
	bra.uni 	$L__BB0_208;

$L__BB0_172:
	mov.f32 	%f1707, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1707;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs170, %f552;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs169, %f551;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f550;}

	// end inline asm
	st.global.v4.u16 	[%rd32], {%rs168, %rs169, %rs170, %rs171};

$L__BB0_208:
	ret;

}