//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<193>;
	.reg .b16 	%rs<181>;
	.reg .f32 	%f<1453>;
	.reg .b32 	%r<375>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<116>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r53), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r54), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd29, [params+400];
	cvta.to.global.u64 	%rd30, %rd29;
	ld.const.u32 	%r59, [params+392];
	mad.lo.s32 	%r60, %r59, %r54, %r53;
	mul.wide.u32 	%rd31, %r60, 4;
	add.s64 	%rd2, %rd30, %rd31;
	ld.global.v2.u8 	{%rs16, %rs176}, [%rd2];
	or.b16  	%rs18, %rs16, %rs176;
	and.b16  	%rs19, %rs18, 255;
	setp.eq.s16 	%p9, %rs19, 0;
	@%p9 bra 	$L__BB0_2;

	ld.global.u8 	%rs175, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs175, [%rd2+2];
	setp.eq.s16 	%p10, %rs175, 0;
	mov.f32 	%f1407, 0f00000000;
	mov.u16 	%rs176, 0;
	mov.f32 	%f1408, %f1407;
	mov.f32 	%f1409, %f1407;
	@%p10 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f212, %rs16;
	div.rn.f32 	%f213, %f212, 0f437F0000;
	fma.rn.f32 	%f214, %f213, 0f40000000, 0fBF800000;
	and.b16  	%rs22, %rs176, 255;
	cvt.rn.f32.u16 	%f215, %rs22;
	div.rn.f32 	%f216, %f215, 0f437F0000;
	fma.rn.f32 	%f217, %f216, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f218, %rs175;
	div.rn.f32 	%f219, %f218, 0f437F0000;
	fma.rn.f32 	%f220, %f219, 0f40000000, 0fBF800000;
	mul.f32 	%f221, %f217, %f217;
	fma.rn.f32 	%f222, %f214, %f214, %f221;
	fma.rn.f32 	%f223, %f220, %f220, %f222;
	sqrt.rn.f32 	%f224, %f223;
	rcp.rn.f32 	%f225, %f224;
	mul.f32 	%f1409, %f225, %f220;
	mul.f32 	%f1408, %f225, %f217;
	mul.f32 	%f1407, %f214, %f225;

$L__BB0_4:
	ld.const.v2.u32 	{%r61, %r62}, [params];
	add.s32 	%r3, %r61, %r53;
	add.s32 	%r4, %r62, %r54;
	setp.eq.f32 	%p11, %f1407, 0f00000000;
	setp.eq.f32 	%p12, %f1408, 0f00000000;
	and.pred  	%p13, %p11, %p12;
	setp.eq.f32 	%p14, %f1409, 0f00000000;
	and.pred  	%p15, %p14, %p13;
	@%p15 bra 	$L__BB0_157;
	bra.uni 	$L__BB0_5;

$L__BB0_157:
	ld.const.u32 	%r50, [params+104];
	and.b32  	%r344, %r50, 1;
	setp.eq.b32 	%p183, %r344, 1;
	mov.pred 	%p184, 0;
	xor.pred  	%p185, %p183, %p184;
	not.pred 	%p186, %p185;
	@%p186 bra 	$L__BB0_159;

	ld.const.u64 	%rd87, [params+144];
	cvta.to.global.u64 	%rd88, %rd87;
	ld.const.u32 	%r345, [params+136];
	mad.lo.s32 	%r346, %r345, %r4, %r3;
	mul.wide.u32 	%rd89, %r346, 4;
	add.s64 	%rd90, %rd88, %rd89;
	mov.u16 	%rs112, 0;
	st.global.v4.u8 	[%rd90], {%rs112, %rs112, %rs112, %rs112};

$L__BB0_159:
	and.b32  	%r347, %r50, 8;
	setp.eq.s32 	%p187, %r347, 0;
	@%p187 bra 	$L__BB0_161;

	ld.const.u64 	%rd91, [params+192];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r348, [params+184];
	mad.lo.s32 	%r349, %r348, %r4, %r3;
	mov.f32 	%f1303, 0f00000000;
	cvt.rzi.u32.f32 	%r350, %f1303;
	mul.wide.u32 	%rd93, %r349, 2;
	add.s64 	%rd94, %rd92, %rd93;
	mov.u16 	%rs113, 0;
	cvt.u16.u32 	%rs114, %r350;
	st.global.v2.u8 	[%rd94], {%rs114, %rs113};

$L__BB0_161:
	and.b32  	%r351, %r50, 4;
	setp.eq.s32 	%p188, %r351, 0;
	ld.const.u32 	%r374, [params+108];
	@%p188 bra 	$L__BB0_165;

	setp.eq.s32 	%p189, %r374, 0;
	ld.const.u64 	%rd95, [params+224];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r352, [params+216];
	mad.lo.s32 	%r353, %r352, %r4, %r3;
	mul.wide.u32 	%rd97, %r353, 8;
	add.s64 	%rd24, %rd96, %rd97;
	@%p189 bra 	$L__BB0_164;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1304, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1305, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1306, %rs123;}

	// end inline asm
	add.f32 	%f1307, %f1304, 0f00000000;
	add.f32 	%f1308, %f1305, 0f00000000;
	add.f32 	%f1309, %f1306, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1309;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1308;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1307;}

	// end inline asm
	mov.u16 	%rs125, 0;
	st.global.v4.u16 	[%rd24], {%rs118, %rs119, %rs120, %rs125};
	bra.uni 	$L__BB0_165;

$L__BB0_5:
	ld.const.v4.f32 	{%f227, %f228, %f229, %f230}, [params+512];
	neg.f32 	%f231, %f228;
	neg.f32 	%f232, %f229;
	mul.f32 	%f233, %f1407, %f227;
	mul.f32 	%f234, %f1408, %f231;
	sub.f32 	%f235, %f234, %f233;
	mul.f32 	%f236, %f1409, %f229;
	sub.f32 	%f13, %f235, %f236;
	ld.const.u64 	%rd32, [params+432];
	cvta.to.global.u64 	%rd33, %rd32;
	ld.const.u32 	%r65, [params+424];
	mad.lo.s32 	%r66, %r65, %r54, %r53;
	mul.wide.u32 	%rd34, %r66, 12;
	add.s64 	%rd35, %rd33, %rd34;
	ld.global.f32 	%f14, [%rd35];
	mul.f32 	%f237, %f14, 0f3456BF95;
	ld.global.f32 	%f15, [%rd35+4];
	mul.f32 	%f238, %f15, 0f3456BF95;
	ld.global.f32 	%f16, [%rd35+8];
	mul.f32 	%f239, %f16, 0f3456BF95;
	abs.f32 	%f240, %f1407;
	div.rn.f32 	%f241, %f237, %f240;
	abs.f32 	%f242, %f1408;
	div.rn.f32 	%f243, %f238, %f242;
	abs.f32 	%f244, %f1409;
	div.rn.f32 	%f245, %f239, %f244;
	abs.f32 	%f246, %f241;
	abs.f32 	%f247, %f243;
	abs.f32 	%f248, %f245;
	mov.f32 	%f249, 0f38D1B717;
	max.f32 	%f250, %f246, %f249;
	max.f32 	%f251, %f247, %f249;
	max.f32 	%f252, %f248, %f249;
	fma.rn.f32 	%f17, %f1407, %f250, %f14;
	fma.rn.f32 	%f18, %f1408, %f251, %f15;
	fma.rn.f32 	%f19, %f1409, %f252, %f16;
	abs.f32 	%f253, %f227;
	abs.f32 	%f254, %f229;
	setp.gt.f32 	%p16, %f253, %f254;
	selp.f32 	%f255, %f231, 0f00000000, %p16;
	mov.f32 	%f1411, 0f00000000;
	selp.f32 	%f256, %f227, %f232, %p16;
	selp.f32 	%f257, 0f00000000, %f228, %p16;
	mul.f32 	%f258, %f256, %f256;
	fma.rn.f32 	%f259, %f255, %f255, %f258;
	fma.rn.f32 	%f260, %f257, %f257, %f259;
	sqrt.rn.f32 	%f261, %f260;
	rcp.rn.f32 	%f262, %f261;
	mul.f32 	%f20, %f255, %f262;
	mul.f32 	%f21, %f256, %f262;
	mul.f32 	%f22, %f257, %f262;
	mul.f32 	%f263, %f229, %f21;
	mul.f32 	%f264, %f228, %f22;
	sub.f32 	%f23, %f263, %f264;
	mul.f32 	%f265, %f227, %f22;
	mul.f32 	%f266, %f229, %f20;
	sub.f32 	%f24, %f265, %f266;
	mul.f32 	%f267, %f228, %f20;
	mul.f32 	%f268, %f227, %f21;
	sub.f32 	%f25, %f267, %f268;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p17, %r5, 1;
	@%p17 bra 	$L__BB0_34;

	ld.const.u64 	%rd36, [params+128];
	ld.const.u32 	%r68, [params+120];
	cvt.rn.f32.s32 	%f270, %r5;
	rcp.rn.f32 	%f26, %f270;
	mad.lo.s32 	%r69, %r68, %r54, %r53;
	cvta.to.global.u64 	%rd37, %rd36;
	mul.wide.u32 	%rd38, %r69, 4;
	add.s64 	%rd39, %rd37, %rd38;
	ld.global.u32 	%r366, [%rd39];
	ld.const.f32 	%f27, [params+536];
	ld.const.u8 	%rs24, [params+104];
	and.b16  	%rs25, %rs24, 32;
	setp.eq.s16 	%p18, %rs25, 0;
	mov.u32 	%r67, 0;
	selp.f32 	%f28, 0f3F800000, 0f41200000, %p18;
	mul.f32 	%f29, %f17, 0f3456BF95;
	mul.f32 	%f30, %f18, 0f3456BF95;
	mul.f32 	%f31, %f19, 0f3456BF95;
	ld.const.u64 	%rd3, [params+96];
	add.s64 	%rd4, %rd1, 24;
	mov.u64 	%rd40, __cudart_i2opi_f;
	abs.f32 	%f353, %f30;
	abs.f32 	%f354, %f29;
	max.f32 	%f355, %f354, %f353;
	abs.f32 	%f356, %f31;
	max.f32 	%f357, %f355, %f356;
	mov.u32 	%r363, %r67;

$L__BB0_7:
	mov.u32 	%r365, %r67;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1355, %r363;
	mad.lo.s32 	%r71, %r366, 1664525, 1013904223;
	and.b32  	%r72, %r71, 16777215;
	cvt.rn.f32.u32 	%f271, %r72;
	fma.rn.f32 	%f272, %f271, 0f33800000, %f1355;
	mul.f32 	%f273, %f26, %f272;
	mad.lo.s32 	%r366, %r71, 1664525, 1013904223;
	and.b32  	%r73, %r366, 16777215;
	cvt.rn.f32.u32 	%f274, %r73;
	cvt.rn.f32.s32 	%f275, %r365;
	fma.rn.f32 	%f276, %f274, 0f33800000, %f275;
	mul.f32 	%f277, %f26, %f276;
	sqrt.rn.f32 	%f35, %f273;
	mul.f32 	%f36, %f277, 0f40C90FDB;
	mul.f32 	%f278, %f36, 0f3F22F983;
	cvt.rni.s32.f32 	%r373, %f278;
	cvt.rn.f32.s32 	%f279, %r373;
	mov.f32 	%f280, 0fBFC90FDA;
	fma.rn.f32 	%f281, %f279, %f280, %f36;
	mov.f32 	%f282, 0fB3A22168;
	fma.rn.f32 	%f283, %f279, %f282, %f281;
	mov.f32 	%f284, 0fA7C234C5;
	fma.rn.f32 	%f1415, %f279, %f284, %f283;
	abs.f32 	%f38, %f36;
	setp.ltu.f32 	%p19, %f38, 0f47CE4780;
	mov.u32 	%r370, %r373;
	mov.f32 	%f1412, %f1415;
	@%p19 bra 	$L__BB0_16;

	setp.eq.f32 	%p20, %f38, 0f7F800000;
	@%p20 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f287, 0f00000000;
	mul.rn.f32 	%f1412, %f36, %f287;
	mov.u32 	%r370, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f36;
	bfe.u32 	%r75, %r13, 23, 8;
	add.s32 	%r14, %r75, -128;
	shl.b32 	%r76, %r13, 8;
	or.b32  	%r15, %r76, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd113, 0;
	mov.u32 	%r367, 0;
	mov.u64 	%rd111, %rd1;
	mov.u64 	%rd112, %rd40;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r77, [%rd112];
	mad.wide.u32 	%rd42, %r77, %r15, %rd113;
	shr.u64 	%rd113, %rd42, 32;
	st.local.u32 	[%rd111], %rd42;
	add.s64 	%rd112, %rd112, 4;
	add.s64 	%rd111, %rd111, 4;
	add.s32 	%r367, %r367, 1;
	setp.ne.s32 	%p21, %r367, 6;
	@%p21 bra 	$L__BB0_11;

	st.local.u32 	[%rd4], %rd113;
	mov.u32 	%r78, 4;
	sub.s32 	%r19, %r78, %r16;
	mov.u32 	%r79, 6;
	sub.s32 	%r80, %r79, %r16;
	mul.wide.s32 	%rd43, %r80, 4;
	add.s64 	%rd44, %rd1, %rd43;
	ld.local.u32 	%r368, [%rd44];
	ld.local.u32 	%r369, [%rd44+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p22, %r22, 0;
	@%p22 bra 	$L__BB0_14;

	mov.u32 	%r81, 32;
	sub.s32 	%r82, %r81, %r22;
	shr.u32 	%r83, %r369, %r82;
	shl.b32 	%r84, %r368, %r22;
	add.s32 	%r368, %r83, %r84;
	mul.wide.s32 	%rd45, %r19, 4;
	add.s64 	%rd46, %rd1, %rd45;
	ld.local.u32 	%r85, [%rd46];
	shr.u32 	%r86, %r85, %r82;
	shl.b32 	%r87, %r369, %r22;
	add.s32 	%r369, %r86, %r87;

$L__BB0_14:
	and.b32  	%r88, %r13, -2147483648;
	shr.u32 	%r89, %r369, 30;
	shl.b32 	%r90, %r368, 2;
	or.b32  	%r91, %r89, %r90;
	shr.u32 	%r92, %r91, 31;
	shr.u32 	%r93, %r368, 30;
	add.s32 	%r94, %r92, %r93;
	neg.s32 	%r95, %r94;
	setp.eq.s32 	%p23, %r88, 0;
	selp.b32 	%r370, %r94, %r95, %p23;
	setp.ne.s32 	%p24, %r92, 0;
	xor.b32  	%r96, %r88, -2147483648;
	selp.b32 	%r97, %r96, %r88, %p24;
	selp.b32 	%r98, -1, 0, %p24;
	xor.b32  	%r99, %r91, %r98;
	shl.b32 	%r100, %r369, 2;
	xor.b32  	%r101, %r100, %r98;
	cvt.u64.u32 	%rd47, %r99;
	cvt.u64.u32 	%rd48, %r101;
	bfi.b64 	%rd49, %rd47, %rd48, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd49;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f285, %fd2;
	setp.eq.s32 	%p25, %r97, 0;
	neg.f32 	%f286, %f285;
	selp.f32 	%f1412, %f285, %f286, %p25;

$L__BB0_16:
	add.s32 	%r29, %r370, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p26, %r30, 0;
	selp.f32 	%f42, %f1412, 0f3F800000, %p26;
	mul.rn.f32 	%f43, %f1412, %f1412;
	mov.f32 	%f1413, 0fB94D4153;
	@%p26 bra 	$L__BB0_18;

	mov.f32 	%f289, 0fBAB607ED;
	mov.f32 	%f290, 0f37CBAC00;
	fma.rn.f32 	%f1413, %f290, %f43, %f289;

$L__BB0_18:
	selp.f32 	%f291, 0f3C0885E4, 0f3D2AAABB, %p26;
	fma.rn.f32 	%f292, %f1413, %f43, %f291;
	selp.f32 	%f293, 0fBE2AAAA8, 0fBEFFFFFF, %p26;
	fma.rn.f32 	%f294, %f292, %f43, %f293;
	mov.f32 	%f295, 0f00000000;
	fma.rn.f32 	%f296, %f43, %f42, %f295;
	fma.rn.f32 	%f1414, %f294, %f296, %f42;
	and.b32  	%r103, %r29, 2;
	setp.eq.s32 	%p28, %r103, 0;
	@%p28 bra 	$L__BB0_20;

	mov.f32 	%f298, 0fBF800000;
	fma.rn.f32 	%f1414, %f1414, %f298, %f295;

$L__BB0_20:
	@%p19 bra 	$L__BB0_28;

	setp.eq.f32 	%p30, %f38, 0f7F800000;
	@%p30 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f301, 0f00000000;
	mul.rn.f32 	%f1415, %f36, %f301;
	mov.u32 	%r373, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f36;
	bfe.u32 	%r104, %r31, 23, 8;
	add.s32 	%r32, %r104, -128;
	shl.b32 	%r105, %r31, 8;
	or.b32  	%r33, %r105, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd114, 0;
	mov.u64 	%rd115, %rd114;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd52, %rd114, 2;
	mov.u64 	%rd53, __cudart_i2opi_f;
	add.s64 	%rd54, %rd53, %rd52;
	ld.global.nc.u32 	%r106, [%rd54];
	mad.wide.u32 	%rd55, %r106, %r33, %rd115;
	shr.u64 	%rd115, %rd55, 32;
	add.s64 	%rd56, %rd1, %rd52;
	st.local.u32 	[%rd56], %rd55;
	cvt.u32.u64 	%r107, %rd114;
	add.s32 	%r108, %r107, 1;
	cvt.s64.s32 	%rd114, %r108;
	setp.ne.s32 	%p31, %r108, 6;
	@%p31 bra 	$L__BB0_23;

	st.local.u32 	[%rd4], %rd115;
	mov.u32 	%r109, 4;
	sub.s32 	%r35, %r109, %r34;
	mov.u32 	%r110, 6;
	sub.s32 	%r111, %r110, %r34;
	mul.wide.s32 	%rd57, %r111, 4;
	add.s64 	%rd58, %rd1, %rd57;
	ld.local.u32 	%r371, [%rd58];
	ld.local.u32 	%r372, [%rd58+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p32, %r38, 0;
	@%p32 bra 	$L__BB0_26;

	mov.u32 	%r112, 32;
	sub.s32 	%r113, %r112, %r38;
	shr.u32 	%r114, %r372, %r113;
	shl.b32 	%r115, %r371, %r38;
	add.s32 	%r371, %r114, %r115;
	mul.wide.s32 	%rd59, %r35, 4;
	add.s64 	%rd60, %rd1, %rd59;
	ld.local.u32 	%r116, [%rd60];
	shr.u32 	%r117, %r116, %r113;
	shl.b32 	%r118, %r372, %r38;
	add.s32 	%r372, %r117, %r118;

$L__BB0_26:
	and.b32  	%r119, %r31, -2147483648;
	shr.u32 	%r120, %r372, 30;
	shl.b32 	%r121, %r371, 2;
	or.b32  	%r122, %r120, %r121;
	shr.u32 	%r123, %r122, 31;
	shr.u32 	%r124, %r371, 30;
	add.s32 	%r125, %r123, %r124;
	neg.s32 	%r126, %r125;
	setp.eq.s32 	%p33, %r119, 0;
	selp.b32 	%r373, %r125, %r126, %p33;
	setp.ne.s32 	%p34, %r123, 0;
	xor.b32  	%r127, %r119, -2147483648;
	selp.b32 	%r128, %r127, %r119, %p34;
	selp.b32 	%r129, -1, 0, %p34;
	xor.b32  	%r130, %r122, %r129;
	shl.b32 	%r131, %r372, 2;
	xor.b32  	%r132, %r131, %r129;
	cvt.u64.u32 	%rd61, %r130;
	cvt.u64.u32 	%rd62, %r132;
	bfi.b64 	%rd63, %rd61, %rd62, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd63;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f299, %fd4;
	setp.eq.s32 	%p35, %r128, 0;
	neg.f32 	%f300, %f299;
	selp.f32 	%f1415, %f299, %f300, %p35;

$L__BB0_28:
	mul.f32 	%f52, %f35, %f1414;
	and.b32  	%r45, %r373, 1;
	setp.eq.s32 	%p36, %r45, 0;
	selp.f32 	%f53, %f1415, 0f3F800000, %p36;
	mul.rn.f32 	%f54, %f1415, %f1415;
	mov.f32 	%f1416, 0fB94D4153;
	@%p36 bra 	$L__BB0_30;

	mov.f32 	%f303, 0fBAB607ED;
	mov.f32 	%f304, 0f37CBAC00;
	fma.rn.f32 	%f1416, %f304, %f54, %f303;

$L__BB0_30:
	selp.f32 	%f305, 0f3C0885E4, 0f3D2AAABB, %p36;
	fma.rn.f32 	%f306, %f1416, %f54, %f305;
	selp.f32 	%f307, 0fBE2AAAA8, 0fBEFFFFFF, %p36;
	fma.rn.f32 	%f308, %f306, %f54, %f307;
	mov.f32 	%f309, 0f00000000;
	fma.rn.f32 	%f310, %f54, %f53, %f309;
	fma.rn.f32 	%f1417, %f308, %f310, %f53;
	and.b32  	%r134, %r373, 2;
	setp.eq.s32 	%p38, %r134, 0;
	@%p38 bra 	$L__BB0_32;

	mov.f32 	%f312, 0fBF800000;
	fma.rn.f32 	%f1417, %f1417, %f312, %f309;

$L__BB0_32:
	mul.f32 	%f322, %f52, %f52;
	mov.f32 	%f323, 0f3F800000;
	sub.f32 	%f324, %f323, %f322;
	mul.f32 	%f325, %f35, %f1417;
	mul.f32 	%f326, %f325, %f325;
	sub.f32 	%f327, %f324, %f326;
	max.f32 	%f328, %f309, %f327;
	sqrt.rn.f32 	%f329, %f328;
	mul.f32 	%f330, %f20, %f325;
	mul.f32 	%f331, %f21, %f325;
	mul.f32 	%f332, %f22, %f325;
	fma.rn.f32 	%f333, %f23, %f52, %f330;
	fma.rn.f32 	%f334, %f24, %f52, %f331;
	fma.rn.f32 	%f335, %f25, %f52, %f332;
	fma.rn.f32 	%f336, %f227, %f329, %f333;
	fma.rn.f32 	%f337, %f228, %f329, %f334;
	fma.rn.f32 	%f338, %f229, %f329, %f335;
	add.f32 	%f339, %f227, %f336;
	add.f32 	%f340, %f228, %f337;
	add.f32 	%f341, %f229, %f338;
	mul.f32 	%f342, %f27, %f339;
	mul.f32 	%f343, %f27, %f340;
	mul.f32 	%f344, %f27, %f341;
	sub.f32 	%f345, %f342, %f227;
	sub.f32 	%f346, %f343, %f228;
	sub.f32 	%f347, %f344, %f229;
	mul.f32 	%f348, %f346, %f346;
	fma.rn.f32 	%f349, %f345, %f345, %f348;
	fma.rn.f32 	%f350, %f347, %f347, %f349;
	sqrt.rn.f32 	%f351, %f350;
	rcp.rn.f32 	%f352, %f351;
	mul.f32 	%f316, %f352, %f345;
	mul.f32 	%f317, %f352, %f346;
	mul.f32 	%f318, %f352, %f347;
	mov.f32 	%f358, 0f38D1B717;
	max.f32 	%f359, %f357, %f358;
	mul.f32 	%f319, %f28, %f359;
	mov.f32 	%f320, 0f6C4ECB8F;
	mov.u32 	%r171, 2;
	mov.u32 	%r173, 1;
	mov.u32 	%r174, 1065353216;
	mov.u32 	%r205, 0;
	// begin inline asm
	call(%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166),_optix_trace_typed_32,(%r205,%rd3,%f17,%f18,%f19,%f316,%f317,%f318,%f319,%f320,%f309,%r173,%r205,%r173,%r171,%r173,%r173,%r174,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205);
	// end inline asm
	mov.b32 	%f360, %r135;
	add.f32 	%f1411, %f1411, %f360;
	add.s32 	%r365, %r365, 1;
	setp.lt.s32 	%p39, %r365, %r5;
	@%p39 bra 	$L__BB0_8;

	add.s32 	%r363, %r363, 1;
	setp.lt.s32 	%p40, %r363, %r5;
	@%p40 bra 	$L__BB0_7;

$L__BB0_34:
	setp.eq.s32 	%p41, %r5, 0;
	mov.f32 	%f1419, 0f3F800000;
	@%p41 bra 	$L__BB0_36;

	mul.lo.s32 	%r206, %r5, %r5;
	cvt.rn.f32.s32 	%f362, %r206;
	div.rn.f32 	%f1419, %f1411, %f362;

$L__BB0_36:
	mul.f32 	%f364, %f15, %f24;
	fma.rn.f32 	%f365, %f14, %f23, %f364;
	fma.rn.f32 	%f366, %f16, %f25, %f365;
	ld.const.v4.f32 	{%f367, %f368, %f369, %f370}, [params+560];
	fma.rn.f32 	%f375, %f366, %f367, %f369;
	mul.f32 	%f376, %f15, %f21;
	fma.rn.f32 	%f377, %f14, %f20, %f376;
	fma.rn.f32 	%f378, %f16, %f22, %f377;
	fma.rn.f32 	%f379, %f378, %f368, %f370;
	ld.const.u64 	%rd65, [params+552];
	tex.2d.v4.f32.f32 	{%f380, %f381, %f382, %f383}, [%rd65, {%f375, %f379}];
	min.f32 	%f384, %f380, %f381;
	min.f32 	%f385, %f384, %f382;
	mul.f32 	%f64, %f1419, %f385;
	ld.const.f32 	%f386, [params+524];
	mul.f32 	%f387, %f1419, %f386;
	ld.const.v2.f32 	{%f388, %f389}, [params+528];
	mul.f32 	%f392, %f1419, %f388;
	mul.f32 	%f393, %f1419, %f389;
	mul.f32 	%f65, %f380, %f387;
	mul.f32 	%f66, %f381, %f392;
	mul.f32 	%f67, %f382, %f393;
	cvt.sat.f32.f32 	%f394, %f13;
	mul.f32 	%f68, %f65, %f394;
	mul.f32 	%f69, %f66, %f394;
	mul.f32 	%f70, %f394, %f67;
	fma.rn.f32 	%f395, %f13, 0f3F000000, 0f3F000000;
	cvt.sat.f32.f32 	%f396, %f395;
	add.f32 	%f71, %f396, %f396;
	mov.f32 	%f400, 0f41A00000;
	abs.f32 	%f73, %f71;
	setp.lt.f32 	%p42, %f73, 0f00800000;
	mul.f32 	%f402, %f73, 0f4B800000;
	selp.f32 	%f403, %f402, %f73, %p42;
	selp.f32 	%f404, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r207, %f403;
	and.b32  	%r208, %r207, 8388607;
	or.b32  	%r209, %r208, 1065353216;
	mov.b32 	%f405, %r209;
	shr.u32 	%r210, %r207, 23;
	cvt.rn.f32.u32 	%f406, %r210;
	add.f32 	%f407, %f404, %f406;
	setp.gt.f32 	%p43, %f405, 0f3FB504F3;
	mul.f32 	%f408, %f405, 0f3F000000;
	add.f32 	%f409, %f407, 0f3F800000;
	selp.f32 	%f410, %f409, %f407, %p43;
	selp.f32 	%f411, %f408, %f405, %p43;
	add.f32 	%f412, %f411, 0fBF800000;
	add.f32 	%f413, %f411, 0f3F800000;
	rcp.approx.ftz.f32 	%f414, %f413;
	add.f32 	%f415, %f412, %f412;
	mul.f32 	%f416, %f415, %f414;
	mul.f32 	%f417, %f416, %f416;
	mov.f32 	%f418, 0f3C4CAF63;
	mov.f32 	%f419, 0f3B18F0FE;
	fma.rn.f32 	%f420, %f419, %f417, %f418;
	mov.f32 	%f421, 0f3DAAAABD;
	fma.rn.f32 	%f422, %f420, %f417, %f421;
	mul.rn.f32 	%f423, %f422, %f417;
	mul.rn.f32 	%f424, %f423, %f416;
	sub.f32 	%f425, %f412, %f416;
	add.f32 	%f426, %f425, %f425;
	neg.f32 	%f427, %f416;
	fma.rn.f32 	%f428, %f427, %f412, %f426;
	mul.rn.f32 	%f429, %f414, %f428;
	add.f32 	%f430, %f424, %f416;
	sub.f32 	%f431, %f416, %f430;
	add.f32 	%f432, %f424, %f431;
	add.f32 	%f433, %f429, %f432;
	add.f32 	%f434, %f430, %f433;
	sub.f32 	%f435, %f430, %f434;
	add.f32 	%f436, %f433, %f435;
	mov.f32 	%f437, 0f3F317200;
	mul.rn.f32 	%f438, %f410, %f437;
	mov.f32 	%f439, 0f35BFBE8E;
	mul.rn.f32 	%f440, %f410, %f439;
	add.f32 	%f441, %f438, %f434;
	sub.f32 	%f442, %f438, %f441;
	add.f32 	%f443, %f434, %f442;
	add.f32 	%f444, %f436, %f443;
	add.f32 	%f445, %f440, %f444;
	add.f32 	%f446, %f441, %f445;
	sub.f32 	%f447, %f441, %f446;
	add.f32 	%f448, %f445, %f447;
	mul.rn.f32 	%f449, %f400, %f446;
	neg.f32 	%f450, %f449;
	fma.rn.f32 	%f451, %f400, %f446, %f450;
	fma.rn.f32 	%f452, %f400, %f448, %f451;
	mov.f32 	%f453, 0f00000000;
	fma.rn.f32 	%f454, %f453, %f446, %f452;
	add.rn.f32 	%f455, %f449, %f454;
	neg.f32 	%f456, %f455;
	add.rn.f32 	%f457, %f449, %f456;
	add.rn.f32 	%f458, %f457, %f454;
	mov.b32 	%r211, %f455;
	setp.eq.s32 	%p44, %r211, 1118925336;
	add.s32 	%r212, %r211, -1;
	mov.b32 	%f459, %r212;
	add.f32 	%f460, %f458, 0f37000000;
	selp.f32 	%f74, %f460, %f458, %p44;
	selp.f32 	%f461, %f459, %f455, %p44;
	mov.f32 	%f462, 0f3FB8AA3B;
	mul.rn.f32 	%f463, %f461, %f462;
	cvt.rzi.f32.f32 	%f464, %f463;
	abs.f32 	%f465, %f464;
	setp.gt.f32 	%p45, %f465, 0f42FC0000;
	mov.b32 	%r213, %f464;
	and.b32  	%r214, %r213, -2147483648;
	or.b32  	%r215, %r214, 1123811328;
	mov.b32 	%f466, %r215;
	selp.f32 	%f467, %f466, %f464, %p45;
	mov.f32 	%f468, 0fBF317218;
	fma.rn.f32 	%f469, %f467, %f468, %f461;
	mov.f32 	%f470, 0f3102E308;
	fma.rn.f32 	%f471, %f467, %f470, %f469;
	mul.f32 	%f472, %f471, 0f3FB8AA3B;
	add.f32 	%f473, %f467, 0f4B40007F;
	mov.b32 	%r216, %f473;
	shl.b32 	%r217, %r216, 23;
	mov.b32 	%f474, %r217;
	ex2.approx.ftz.f32 	%f475, %f472;
	mul.f32 	%f75, %f475, %f474;
	setp.eq.f32 	%p46, %f75, 0f7F800000;
	mov.f32 	%f1420, 0f7F800000;
	@%p46 bra 	$L__BB0_38;

	fma.rn.f32 	%f1420, %f75, %f74, %f75;

$L__BB0_38:
	mov.f32 	%f1361, 0f41200000;
	cvt.rzi.f32.f32 	%f1360, %f1361;
	add.f32 	%f1359, %f1360, %f1360;
	mov.f32 	%f1358, 0f41A00000;
	sub.f32 	%f1357, %f1358, %f1359;
	abs.f32 	%f1356, %f1357;
	setp.lt.f32 	%p47, %f71, 0f00000000;
	setp.eq.f32 	%p48, %f1356, 0f3F800000;
	and.pred  	%p1, %p47, %p48;
	setp.eq.f32 	%p49, %f71, 0f00000000;
	@%p49 bra 	$L__BB0_42;
	bra.uni 	$L__BB0_39;

$L__BB0_42:
	add.f32 	%f480, %f71, %f71;
	selp.f32 	%f1422, %f480, 0f00000000, %p48;
	bra.uni 	$L__BB0_43;

$L__BB0_39:
	mov.b32 	%r218, %f1420;
	xor.b32  	%r219, %r218, -2147483648;
	mov.b32 	%f476, %r219;
	selp.f32 	%f1422, %f476, %f1420, %p1;
	setp.geu.f32 	%p50, %f71, 0f00000000;
	@%p50 bra 	$L__BB0_43;

	mov.f32 	%f477, 0f41A00000;
	cvt.rzi.f32.f32 	%f478, %f477;
	setp.eq.f32 	%p51, %f478, 0f41A00000;
	@%p51 bra 	$L__BB0_43;

	mov.f32 	%f1422, 0f7FFFFFFF;

$L__BB0_43:
	abs.f32 	%f1362, %f71;
	add.f32 	%f481, %f1362, 0f41A00000;
	mov.b32 	%r220, %f481;
	setp.lt.s32 	%p53, %r220, 2139095040;
	@%p53 bra 	$L__BB0_48;

	abs.f32 	%f1363, %f71;
	setp.gtu.f32 	%p54, %f1363, 0f7F800000;
	@%p54 bra 	$L__BB0_47;
	bra.uni 	$L__BB0_45;

$L__BB0_47:
	add.f32 	%f1422, %f71, 0f41A00000;
	bra.uni 	$L__BB0_48;

$L__BB0_45:
	abs.f32 	%f1364, %f71;
	setp.neu.f32 	%p55, %f1364, 0f7F800000;
	@%p55 bra 	$L__BB0_48;

	selp.f32 	%f1422, 0fFF800000, 0f7F800000, %p1;

$L__BB0_48:
	setp.eq.f32 	%p56, %f71, 0f3F800000;
	selp.f32 	%f482, 0f3F800000, %f1422, %p56;
	cvt.sat.f32.f32 	%f483, %f482;
	mul.f32 	%f84, %f65, %f483;
	mul.f32 	%f85, %f66, %f483;
	mul.f32 	%f86, %f67, %f483;
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r221, %r48, 8;
	setp.eq.s32 	%p57, %r221, 0;
	@%p57 bra 	$L__BB0_62;

	ld.const.u32 	%r222, [params+184];
	mad.lo.s32 	%r223, %r222, %r4, %r3;
	cvt.u64.u32 	%rd16, %r223;
	mov.f32 	%f488, 0f3EE8BA2E;
	abs.f32 	%f88, %f64;
	setp.lt.f32 	%p58, %f88, 0f00800000;
	mul.f32 	%f490, %f88, 0f4B800000;
	selp.f32 	%f491, %f490, %f88, %p58;
	selp.f32 	%f492, 0fC3170000, 0fC2FE0000, %p58;
	mov.b32 	%r224, %f491;
	and.b32  	%r225, %r224, 8388607;
	or.b32  	%r226, %r225, 1065353216;
	mov.b32 	%f493, %r226;
	shr.u32 	%r227, %r224, 23;
	cvt.rn.f32.u32 	%f494, %r227;
	add.f32 	%f495, %f492, %f494;
	setp.gt.f32 	%p59, %f493, 0f3FB504F3;
	mul.f32 	%f496, %f493, 0f3F000000;
	add.f32 	%f497, %f495, 0f3F800000;
	selp.f32 	%f498, %f497, %f495, %p59;
	selp.f32 	%f499, %f496, %f493, %p59;
	add.f32 	%f500, %f499, 0fBF800000;
	add.f32 	%f501, %f499, 0f3F800000;
	rcp.approx.ftz.f32 	%f502, %f501;
	add.f32 	%f503, %f500, %f500;
	mul.f32 	%f504, %f503, %f502;
	mul.f32 	%f505, %f504, %f504;
	mov.f32 	%f506, 0f3C4CAF63;
	mov.f32 	%f507, 0f3B18F0FE;
	fma.rn.f32 	%f508, %f507, %f505, %f506;
	mov.f32 	%f509, 0f3DAAAABD;
	fma.rn.f32 	%f510, %f508, %f505, %f509;
	mul.rn.f32 	%f511, %f510, %f505;
	mul.rn.f32 	%f512, %f511, %f504;
	sub.f32 	%f513, %f500, %f504;
	add.f32 	%f514, %f513, %f513;
	neg.f32 	%f515, %f504;
	fma.rn.f32 	%f516, %f515, %f500, %f514;
	mul.rn.f32 	%f517, %f502, %f516;
	add.f32 	%f518, %f512, %f504;
	sub.f32 	%f519, %f504, %f518;
	add.f32 	%f520, %f512, %f519;
	add.f32 	%f521, %f517, %f520;
	add.f32 	%f522, %f518, %f521;
	sub.f32 	%f523, %f518, %f522;
	add.f32 	%f524, %f521, %f523;
	mov.f32 	%f525, 0f3F317200;
	mul.rn.f32 	%f526, %f498, %f525;
	mov.f32 	%f527, 0f35BFBE8E;
	mul.rn.f32 	%f528, %f498, %f527;
	add.f32 	%f529, %f526, %f522;
	sub.f32 	%f530, %f526, %f529;
	add.f32 	%f531, %f522, %f530;
	add.f32 	%f532, %f524, %f531;
	add.f32 	%f533, %f528, %f532;
	add.f32 	%f534, %f529, %f533;
	sub.f32 	%f535, %f529, %f534;
	add.f32 	%f536, %f533, %f535;
	mul.rn.f32 	%f537, %f488, %f534;
	neg.f32 	%f538, %f537;
	fma.rn.f32 	%f539, %f488, %f534, %f538;
	fma.rn.f32 	%f540, %f488, %f536, %f539;
	mov.f32 	%f541, 0f00000000;
	fma.rn.f32 	%f542, %f541, %f534, %f540;
	add.rn.f32 	%f543, %f537, %f542;
	neg.f32 	%f544, %f543;
	add.rn.f32 	%f545, %f537, %f544;
	add.rn.f32 	%f546, %f545, %f542;
	mov.b32 	%r228, %f543;
	setp.eq.s32 	%p60, %r228, 1118925336;
	add.s32 	%r229, %r228, -1;
	mov.b32 	%f547, %r229;
	add.f32 	%f548, %f546, 0f37000000;
	selp.f32 	%f89, %f548, %f546, %p60;
	selp.f32 	%f549, %f547, %f543, %p60;
	mov.f32 	%f550, 0f3FB8AA3B;
	mul.rn.f32 	%f551, %f549, %f550;
	cvt.rzi.f32.f32 	%f552, %f551;
	abs.f32 	%f553, %f552;
	setp.gt.f32 	%p61, %f553, 0f42FC0000;
	mov.b32 	%r230, %f552;
	and.b32  	%r231, %r230, -2147483648;
	or.b32  	%r232, %r231, 1123811328;
	mov.b32 	%f554, %r232;
	selp.f32 	%f555, %f554, %f552, %p61;
	mov.f32 	%f556, 0fBF317218;
	fma.rn.f32 	%f557, %f555, %f556, %f549;
	mov.f32 	%f558, 0f3102E308;
	fma.rn.f32 	%f559, %f555, %f558, %f557;
	mul.f32 	%f560, %f559, 0f3FB8AA3B;
	add.f32 	%f561, %f555, 0f4B40007F;
	mov.b32 	%r233, %f561;
	shl.b32 	%r234, %r233, 23;
	mov.b32 	%f562, %r234;
	ex2.approx.ftz.f32 	%f563, %f560;
	mul.f32 	%f90, %f563, %f562;
	setp.eq.f32 	%p62, %f90, 0f7F800000;
	mov.f32 	%f1423, 0f7F800000;
	@%p62 bra 	$L__BB0_51;

	fma.rn.f32 	%f1423, %f90, %f89, %f90;

$L__BB0_51:
	mov.f32 	%f1406, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1405, %f1406;
	add.f32 	%f1404, %f1405, %f1405;
	mov.f32 	%f1403, 0f3EE8BA2E;
	sub.f32 	%f1402, %f1403, %f1404;
	abs.f32 	%f1401, %f1402;
	setp.lt.f32 	%p63, %f64, 0f00000000;
	setp.eq.f32 	%p64, %f1401, 0f3F800000;
	and.pred  	%p2, %p63, %p64;
	setp.eq.f32 	%p65, %f64, 0f00000000;
	@%p65 bra 	$L__BB0_55;
	bra.uni 	$L__BB0_52;

$L__BB0_55:
	add.f32 	%f568, %f64, %f64;
	selp.f32 	%f1425, %f568, 0f00000000, %p64;
	bra.uni 	$L__BB0_56;

$L__BB0_164:
	mov.f32 	%f1312, 0f00000000;
	mov.u32 	%r374, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1312;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1312;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1312;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd24], {%rs126, %rs127, %rs128, %rs129};

$L__BB0_165:
	ld.const.u64 	%rd98, [params+256];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r355, [params+248];
	mad.lo.s32 	%r356, %r355, %r4, %r3;
	mul.wide.u32 	%rd100, %r356, 8;
	add.s64 	%rd25, %rd99, %rd100;
	setp.eq.s32 	%p190, %r374, 0;
	@%p190 bra 	$L__BB0_167;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1313, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1314, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1315, %rs138;}

	// end inline asm
	add.f32 	%f1316, %f1313, 0f00000000;
	add.f32 	%f1317, %f1314, 0f00000000;
	add.f32 	%f1318, %f1315, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1318;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1317;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1316;}

	// end inline asm
	mov.u16 	%rs140, 0;
	st.global.v4.u16 	[%rd25], {%rs133, %rs134, %rs135, %rs140};
	bra.uni 	$L__BB0_168;

$L__BB0_167:
	mov.f32 	%f1321, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1321;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1321;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1321;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd25], {%rs141, %rs142, %rs143, %rs144};

$L__BB0_168:
	ld.const.u64 	%rd101, [params+272];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r357, [params+264];
	mad.lo.s32 	%r358, %r357, %r4, %r3;
	mul.wide.u32 	%rd103, %r358, 8;
	add.s64 	%rd26, %rd102, %rd103;
	@%p190 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1322, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1323, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1324, %rs153;}

	// end inline asm
	add.f32 	%f1325, %f1322, 0f00000000;
	add.f32 	%f1326, %f1323, 0f00000000;
	add.f32 	%f1327, %f1324, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1327;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1326;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1325;}

	// end inline asm
	mov.u16 	%rs155, 0;
	st.global.v4.u16 	[%rd26], {%rs148, %rs149, %rs150, %rs155};
	bra.uni 	$L__BB0_171;

$L__BB0_170:
	mov.f32 	%f1330, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1330;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1330;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1330;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd26], {%rs156, %rs157, %rs158, %rs159};

$L__BB0_171:
	ld.const.u64 	%rd104, [params+288];
	cvta.to.global.u64 	%rd105, %rd104;
	ld.const.u32 	%r359, [params+280];
	mad.lo.s32 	%r360, %r359, %r4, %r3;
	mul.wide.u32 	%rd106, %r360, 8;
	add.s64 	%rd27, %rd105, %rd106;
	@%p190 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1331, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1332, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1333, %rs168;}

	// end inline asm
	add.f32 	%f1334, %f1331, 0f00000000;
	add.f32 	%f1335, %f1332, 0f00000000;
	add.f32 	%f1336, %f1333, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1336;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1335;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1334;}

	// end inline asm
	mov.u16 	%rs170, 0;
	st.global.v4.u16 	[%rd27], {%rs163, %rs164, %rs165, %rs170};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1339, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1339;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1339;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1339;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd27], {%rs171, %rs172, %rs173, %rs174};
	bra.uni 	$L__BB0_174;

$L__BB0_52:
	mov.b32 	%r235, %f1423;
	xor.b32  	%r236, %r235, -2147483648;
	mov.b32 	%f564, %r236;
	selp.f32 	%f1425, %f564, %f1423, %p2;
	setp.geu.f32 	%p66, %f64, 0f00000000;
	@%p66 bra 	$L__BB0_56;

	mov.f32 	%f565, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f566, %f565;
	setp.eq.f32 	%p67, %f566, 0f3EE8BA2E;
	@%p67 bra 	$L__BB0_56;

	mov.f32 	%f1425, 0f7FFFFFFF;

$L__BB0_56:
	abs.f32 	%f1365, %f64;
	add.f32 	%f569, %f1365, 0f3EE8BA2E;
	mov.b32 	%r237, %f569;
	setp.lt.s32 	%p69, %r237, 2139095040;
	@%p69 bra 	$L__BB0_61;

	abs.f32 	%f1366, %f64;
	setp.gtu.f32 	%p70, %f1366, 0f7F800000;
	@%p70 bra 	$L__BB0_60;
	bra.uni 	$L__BB0_58;

$L__BB0_60:
	add.f32 	%f1425, %f64, 0f3EE8BA2E;
	bra.uni 	$L__BB0_61;

$L__BB0_58:
	abs.f32 	%f1367, %f64;
	setp.neu.f32 	%p71, %f1367, 0f7F800000;
	@%p71 bra 	$L__BB0_61;

	selp.f32 	%f1425, 0fFF800000, 0f7F800000, %p2;

$L__BB0_61:
	ld.const.u64 	%rd110, [params+192];
	cvta.to.global.u64 	%rd109, %rd110;
	mul.f32 	%f570, %f1425, 0f437F0000;
	setp.eq.f32 	%p72, %f64, 0f3F800000;
	selp.f32 	%f571, 0f437F0000, %f570, %p72;
	cvt.rzi.u32.f32 	%r238, %f571;
	shl.b64 	%rd67, %rd16, 1;
	add.s64 	%rd68, %rd109, %rd67;
	cvt.u16.u32 	%rs26, %r238;
	mov.u16 	%rs27, 255;
	st.global.v2.u8 	[%rd68], {%rs26, %rs27};

$L__BB0_62:
	ld.const.u32 	%r362, [params+104];
	and.b32  	%r239, %r362, 1;
	setp.eq.b32 	%p73, %r239, 1;
	mov.pred 	%p74, 0;
	xor.pred  	%p75, %p73, %p74;
	not.pred 	%p76, %p75;
	@%p76 bra 	$L__BB0_136;

	mov.f32 	%f576, 0f3EE66666;
	abs.f32 	%f100, %f68;
	setp.lt.f32 	%p77, %f100, 0f00800000;
	mul.f32 	%f578, %f100, 0f4B800000;
	selp.f32 	%f579, %f578, %f100, %p77;
	selp.f32 	%f580, 0fC3170000, 0fC2FE0000, %p77;
	mov.b32 	%r240, %f579;
	and.b32  	%r241, %r240, 8388607;
	or.b32  	%r242, %r241, 1065353216;
	mov.b32 	%f581, %r242;
	shr.u32 	%r243, %r240, 23;
	cvt.rn.f32.u32 	%f582, %r243;
	add.f32 	%f583, %f580, %f582;
	setp.gt.f32 	%p78, %f581, 0f3FB504F3;
	mul.f32 	%f584, %f581, 0f3F000000;
	add.f32 	%f585, %f583, 0f3F800000;
	selp.f32 	%f586, %f585, %f583, %p78;
	selp.f32 	%f587, %f584, %f581, %p78;
	add.f32 	%f588, %f587, 0fBF800000;
	add.f32 	%f589, %f587, 0f3F800000;
	rcp.approx.ftz.f32 	%f590, %f589;
	add.f32 	%f591, %f588, %f588;
	mul.f32 	%f592, %f591, %f590;
	mul.f32 	%f593, %f592, %f592;
	mov.f32 	%f594, 0f3C4CAF63;
	mov.f32 	%f595, 0f3B18F0FE;
	fma.rn.f32 	%f596, %f595, %f593, %f594;
	mov.f32 	%f597, 0f3DAAAABD;
	fma.rn.f32 	%f598, %f596, %f593, %f597;
	mul.rn.f32 	%f599, %f598, %f593;
	mul.rn.f32 	%f600, %f599, %f592;
	sub.f32 	%f601, %f588, %f592;
	add.f32 	%f602, %f601, %f601;
	neg.f32 	%f603, %f592;
	fma.rn.f32 	%f604, %f603, %f588, %f602;
	mul.rn.f32 	%f605, %f590, %f604;
	add.f32 	%f606, %f600, %f592;
	sub.f32 	%f607, %f592, %f606;
	add.f32 	%f608, %f600, %f607;
	add.f32 	%f609, %f605, %f608;
	add.f32 	%f610, %f606, %f609;
	sub.f32 	%f611, %f606, %f610;
	add.f32 	%f612, %f609, %f611;
	mov.f32 	%f613, 0f3F317200;
	mul.rn.f32 	%f614, %f586, %f613;
	mov.f32 	%f615, 0f35BFBE8E;
	mul.rn.f32 	%f616, %f586, %f615;
	add.f32 	%f617, %f614, %f610;
	sub.f32 	%f618, %f614, %f617;
	add.f32 	%f619, %f610, %f618;
	add.f32 	%f620, %f612, %f619;
	add.f32 	%f621, %f616, %f620;
	add.f32 	%f622, %f617, %f621;
	sub.f32 	%f623, %f617, %f622;
	add.f32 	%f624, %f621, %f623;
	mul.rn.f32 	%f625, %f576, %f622;
	neg.f32 	%f626, %f625;
	fma.rn.f32 	%f627, %f576, %f622, %f626;
	fma.rn.f32 	%f628, %f576, %f624, %f627;
	mov.f32 	%f629, 0f00000000;
	fma.rn.f32 	%f630, %f629, %f622, %f628;
	add.rn.f32 	%f631, %f625, %f630;
	neg.f32 	%f632, %f631;
	add.rn.f32 	%f633, %f625, %f632;
	add.rn.f32 	%f634, %f633, %f630;
	mov.b32 	%r244, %f631;
	setp.eq.s32 	%p79, %r244, 1118925336;
	add.s32 	%r245, %r244, -1;
	mov.b32 	%f635, %r245;
	add.f32 	%f636, %f634, 0f37000000;
	selp.f32 	%f101, %f636, %f634, %p79;
	selp.f32 	%f637, %f635, %f631, %p79;
	mov.f32 	%f638, 0f3FB8AA3B;
	mul.rn.f32 	%f639, %f637, %f638;
	cvt.rzi.f32.f32 	%f640, %f639;
	abs.f32 	%f641, %f640;
	setp.gt.f32 	%p80, %f641, 0f42FC0000;
	mov.b32 	%r246, %f640;
	and.b32  	%r247, %r246, -2147483648;
	or.b32  	%r248, %r247, 1123811328;
	mov.b32 	%f642, %r248;
	selp.f32 	%f643, %f642, %f640, %p80;
	mov.f32 	%f644, 0fBF317218;
	fma.rn.f32 	%f645, %f643, %f644, %f637;
	mov.f32 	%f646, 0f3102E308;
	fma.rn.f32 	%f647, %f643, %f646, %f645;
	mul.f32 	%f648, %f647, 0f3FB8AA3B;
	add.f32 	%f649, %f643, 0f4B40007F;
	mov.b32 	%r249, %f649;
	shl.b32 	%r250, %r249, 23;
	mov.b32 	%f650, %r250;
	ex2.approx.ftz.f32 	%f651, %f648;
	mul.f32 	%f102, %f651, %f650;
	setp.eq.f32 	%p81, %f102, 0f7F800000;
	mov.f32 	%f1426, 0f7F800000;
	@%p81 bra 	$L__BB0_65;

	fma.rn.f32 	%f1426, %f102, %f101, %f102;

$L__BB0_65:
	mov.f32 	%f1373, 0f3E666666;
	cvt.rzi.f32.f32 	%f1372, %f1373;
	add.f32 	%f1371, %f1372, %f1372;
	mov.f32 	%f1370, 0f3EE66666;
	sub.f32 	%f1369, %f1370, %f1371;
	abs.f32 	%f1368, %f1369;
	setp.lt.f32 	%p82, %f68, 0f00000000;
	setp.eq.f32 	%p83, %f1368, 0f3F800000;
	and.pred  	%p3, %p82, %p83;
	setp.eq.f32 	%p84, %f68, 0f00000000;
	@%p84 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f656, %f68, %f68;
	selp.f32 	%f1428, %f656, 0f00000000, %p83;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r251, %f1426;
	xor.b32  	%r252, %r251, -2147483648;
	mov.b32 	%f652, %r252;
	selp.f32 	%f1428, %f652, %f1426, %p3;
	setp.geu.f32 	%p85, %f68, 0f00000000;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f653, 0f3EE66666;
	cvt.rzi.f32.f32 	%f654, %f653;
	setp.eq.f32 	%p86, %f654, 0f3EE66666;
	@%p86 bra 	$L__BB0_70;

	mov.f32 	%f1428, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1374, %f68;
	add.f32 	%f657, %f1374, 0f3EE66666;
	mov.b32 	%r253, %f657;
	setp.lt.s32 	%p88, %r253, 2139095040;
	@%p88 bra 	$L__BB0_75;

	abs.f32 	%f1375, %f68;
	setp.gtu.f32 	%p89, %f1375, 0f7F800000;
	@%p89 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1428, %f68, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1376, %f68;
	setp.neu.f32 	%p90, %f1376, 0f7F800000;
	@%p90 bra 	$L__BB0_75;

	selp.f32 	%f1428, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p91, %f68, 0f3F800000;
	selp.f32 	%f111, 0f3F800000, %f1428, %p91;
	abs.f32 	%f112, %f69;
	setp.lt.f32 	%p92, %f112, 0f00800000;
	mul.f32 	%f659, %f112, 0f4B800000;
	selp.f32 	%f660, %f659, %f112, %p92;
	selp.f32 	%f661, 0fC3170000, 0fC2FE0000, %p92;
	mov.b32 	%r254, %f660;
	and.b32  	%r255, %r254, 8388607;
	or.b32  	%r256, %r255, 1065353216;
	mov.b32 	%f662, %r256;
	shr.u32 	%r257, %r254, 23;
	cvt.rn.f32.u32 	%f663, %r257;
	add.f32 	%f664, %f661, %f663;
	setp.gt.f32 	%p93, %f662, 0f3FB504F3;
	mul.f32 	%f665, %f662, 0f3F000000;
	add.f32 	%f666, %f664, 0f3F800000;
	selp.f32 	%f667, %f666, %f664, %p93;
	selp.f32 	%f668, %f665, %f662, %p93;
	add.f32 	%f669, %f668, 0fBF800000;
	add.f32 	%f670, %f668, 0f3F800000;
	rcp.approx.ftz.f32 	%f671, %f670;
	add.f32 	%f672, %f669, %f669;
	mul.f32 	%f673, %f672, %f671;
	mul.f32 	%f674, %f673, %f673;
	mov.f32 	%f675, 0f3C4CAF63;
	mov.f32 	%f676, 0f3B18F0FE;
	fma.rn.f32 	%f677, %f676, %f674, %f675;
	mov.f32 	%f678, 0f3DAAAABD;
	fma.rn.f32 	%f679, %f677, %f674, %f678;
	mul.rn.f32 	%f680, %f679, %f674;
	mul.rn.f32 	%f681, %f680, %f673;
	sub.f32 	%f682, %f669, %f673;
	add.f32 	%f683, %f682, %f682;
	neg.f32 	%f684, %f673;
	fma.rn.f32 	%f685, %f684, %f669, %f683;
	mul.rn.f32 	%f686, %f671, %f685;
	add.f32 	%f687, %f681, %f673;
	sub.f32 	%f688, %f673, %f687;
	add.f32 	%f689, %f681, %f688;
	add.f32 	%f690, %f686, %f689;
	add.f32 	%f691, %f687, %f690;
	sub.f32 	%f692, %f687, %f691;
	add.f32 	%f693, %f690, %f692;
	mov.f32 	%f694, 0f3F317200;
	mul.rn.f32 	%f695, %f667, %f694;
	mov.f32 	%f696, 0f35BFBE8E;
	mul.rn.f32 	%f697, %f667, %f696;
	add.f32 	%f698, %f695, %f691;
	sub.f32 	%f699, %f695, %f698;
	add.f32 	%f700, %f691, %f699;
	add.f32 	%f701, %f693, %f700;
	add.f32 	%f702, %f697, %f701;
	add.f32 	%f703, %f698, %f702;
	sub.f32 	%f704, %f698, %f703;
	add.f32 	%f705, %f702, %f704;
	mov.f32 	%f706, 0f3EE66666;
	mul.rn.f32 	%f707, %f706, %f703;
	neg.f32 	%f708, %f707;
	fma.rn.f32 	%f709, %f706, %f703, %f708;
	fma.rn.f32 	%f710, %f706, %f705, %f709;
	mov.f32 	%f711, 0f00000000;
	fma.rn.f32 	%f712, %f711, %f703, %f710;
	add.rn.f32 	%f713, %f707, %f712;
	neg.f32 	%f714, %f713;
	add.rn.f32 	%f715, %f707, %f714;
	add.rn.f32 	%f716, %f715, %f712;
	mov.b32 	%r258, %f713;
	setp.eq.s32 	%p94, %r258, 1118925336;
	add.s32 	%r259, %r258, -1;
	mov.b32 	%f717, %r259;
	add.f32 	%f718, %f716, 0f37000000;
	selp.f32 	%f113, %f718, %f716, %p94;
	selp.f32 	%f719, %f717, %f713, %p94;
	mov.f32 	%f720, 0f3FB8AA3B;
	mul.rn.f32 	%f721, %f719, %f720;
	cvt.rzi.f32.f32 	%f722, %f721;
	abs.f32 	%f723, %f722;
	setp.gt.f32 	%p95, %f723, 0f42FC0000;
	mov.b32 	%r260, %f722;
	and.b32  	%r261, %r260, -2147483648;
	or.b32  	%r262, %r261, 1123811328;
	mov.b32 	%f724, %r262;
	selp.f32 	%f725, %f724, %f722, %p95;
	mov.f32 	%f726, 0fBF317218;
	fma.rn.f32 	%f727, %f725, %f726, %f719;
	mov.f32 	%f728, 0f3102E308;
	fma.rn.f32 	%f729, %f725, %f728, %f727;
	mul.f32 	%f730, %f729, 0f3FB8AA3B;
	add.f32 	%f731, %f725, 0f4B40007F;
	mov.b32 	%r263, %f731;
	shl.b32 	%r264, %r263, 23;
	mov.b32 	%f732, %r264;
	ex2.approx.ftz.f32 	%f733, %f730;
	mul.f32 	%f114, %f733, %f732;
	setp.eq.f32 	%p96, %f114, 0f7F800000;
	mov.f32 	%f1429, 0f7F800000;
	@%p96 bra 	$L__BB0_77;

	fma.rn.f32 	%f1429, %f114, %f113, %f114;

$L__BB0_77:
	setp.lt.f32 	%p97, %f69, 0f00000000;
	and.pred  	%p4, %p97, %p83;
	setp.eq.f32 	%p99, %f69, 0f00000000;
	@%p99 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f738, %f69, %f69;
	selp.f32 	%f1431, %f738, 0f00000000, %p83;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r265, %f1429;
	xor.b32  	%r266, %r265, -2147483648;
	mov.b32 	%f734, %r266;
	selp.f32 	%f1431, %f734, %f1429, %p4;
	setp.geu.f32 	%p100, %f69, 0f00000000;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f735, 0f3EE66666;
	cvt.rzi.f32.f32 	%f736, %f735;
	setp.eq.f32 	%p101, %f736, 0f3EE66666;
	@%p101 bra 	$L__BB0_82;

	mov.f32 	%f1431, 0f7FFFFFFF;

$L__BB0_82:
	abs.f32 	%f1377, %f69;
	add.f32 	%f739, %f1377, 0f3EE66666;
	mov.b32 	%r267, %f739;
	setp.lt.s32 	%p103, %r267, 2139095040;
	@%p103 bra 	$L__BB0_87;

	abs.f32 	%f1378, %f69;
	setp.gtu.f32 	%p104, %f1378, 0f7F800000;
	@%p104 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1431, %f69, 0f3EE66666;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	abs.f32 	%f1379, %f69;
	setp.neu.f32 	%p105, %f1379, 0f7F800000;
	@%p105 bra 	$L__BB0_87;

	selp.f32 	%f1431, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	setp.eq.f32 	%p106, %f69, 0f3F800000;
	selp.f32 	%f123, 0f3F800000, %f1431, %p106;
	abs.f32 	%f124, %f70;
	setp.lt.f32 	%p107, %f124, 0f00800000;
	mul.f32 	%f741, %f124, 0f4B800000;
	selp.f32 	%f742, %f741, %f124, %p107;
	selp.f32 	%f743, 0fC3170000, 0fC2FE0000, %p107;
	mov.b32 	%r268, %f742;
	and.b32  	%r269, %r268, 8388607;
	or.b32  	%r270, %r269, 1065353216;
	mov.b32 	%f744, %r270;
	shr.u32 	%r271, %r268, 23;
	cvt.rn.f32.u32 	%f745, %r271;
	add.f32 	%f746, %f743, %f745;
	setp.gt.f32 	%p108, %f744, 0f3FB504F3;
	mul.f32 	%f747, %f744, 0f3F000000;
	add.f32 	%f748, %f746, 0f3F800000;
	selp.f32 	%f749, %f748, %f746, %p108;
	selp.f32 	%f750, %f747, %f744, %p108;
	add.f32 	%f751, %f750, 0fBF800000;
	add.f32 	%f752, %f750, 0f3F800000;
	rcp.approx.ftz.f32 	%f753, %f752;
	add.f32 	%f754, %f751, %f751;
	mul.f32 	%f755, %f754, %f753;
	mul.f32 	%f756, %f755, %f755;
	mov.f32 	%f757, 0f3C4CAF63;
	mov.f32 	%f758, 0f3B18F0FE;
	fma.rn.f32 	%f759, %f758, %f756, %f757;
	mov.f32 	%f760, 0f3DAAAABD;
	fma.rn.f32 	%f761, %f759, %f756, %f760;
	mul.rn.f32 	%f762, %f761, %f756;
	mul.rn.f32 	%f763, %f762, %f755;
	sub.f32 	%f764, %f751, %f755;
	add.f32 	%f765, %f764, %f764;
	neg.f32 	%f766, %f755;
	fma.rn.f32 	%f767, %f766, %f751, %f765;
	mul.rn.f32 	%f768, %f753, %f767;
	add.f32 	%f769, %f763, %f755;
	sub.f32 	%f770, %f755, %f769;
	add.f32 	%f771, %f763, %f770;
	add.f32 	%f772, %f768, %f771;
	add.f32 	%f773, %f769, %f772;
	sub.f32 	%f774, %f769, %f773;
	add.f32 	%f775, %f772, %f774;
	mov.f32 	%f776, 0f3F317200;
	mul.rn.f32 	%f777, %f749, %f776;
	mov.f32 	%f778, 0f35BFBE8E;
	mul.rn.f32 	%f779, %f749, %f778;
	add.f32 	%f780, %f777, %f773;
	sub.f32 	%f781, %f777, %f780;
	add.f32 	%f782, %f773, %f781;
	add.f32 	%f783, %f775, %f782;
	add.f32 	%f784, %f779, %f783;
	add.f32 	%f785, %f780, %f784;
	sub.f32 	%f786, %f780, %f785;
	add.f32 	%f787, %f784, %f786;
	mov.f32 	%f788, 0f3EE66666;
	mul.rn.f32 	%f789, %f788, %f785;
	neg.f32 	%f790, %f789;
	fma.rn.f32 	%f791, %f788, %f785, %f790;
	fma.rn.f32 	%f792, %f788, %f787, %f791;
	mov.f32 	%f793, 0f00000000;
	fma.rn.f32 	%f794, %f793, %f785, %f792;
	add.rn.f32 	%f795, %f789, %f794;
	neg.f32 	%f796, %f795;
	add.rn.f32 	%f797, %f789, %f796;
	add.rn.f32 	%f798, %f797, %f794;
	mov.b32 	%r272, %f795;
	setp.eq.s32 	%p109, %r272, 1118925336;
	add.s32 	%r273, %r272, -1;
	mov.b32 	%f799, %r273;
	add.f32 	%f800, %f798, 0f37000000;
	selp.f32 	%f125, %f800, %f798, %p109;
	selp.f32 	%f801, %f799, %f795, %p109;
	mov.f32 	%f802, 0f3FB8AA3B;
	mul.rn.f32 	%f803, %f801, %f802;
	cvt.rzi.f32.f32 	%f804, %f803;
	abs.f32 	%f805, %f804;
	setp.gt.f32 	%p110, %f805, 0f42FC0000;
	mov.b32 	%r274, %f804;
	and.b32  	%r275, %r274, -2147483648;
	or.b32  	%r276, %r275, 1123811328;
	mov.b32 	%f806, %r276;
	selp.f32 	%f807, %f806, %f804, %p110;
	mov.f32 	%f808, 0fBF317218;
	fma.rn.f32 	%f809, %f807, %f808, %f801;
	mov.f32 	%f810, 0f3102E308;
	fma.rn.f32 	%f811, %f807, %f810, %f809;
	mul.f32 	%f812, %f811, 0f3FB8AA3B;
	add.f32 	%f813, %f807, 0f4B40007F;
	mov.b32 	%r277, %f813;
	shl.b32 	%r278, %r277, 23;
	mov.b32 	%f814, %r278;
	ex2.approx.ftz.f32 	%f815, %f812;
	mul.f32 	%f126, %f815, %f814;
	setp.eq.f32 	%p111, %f126, 0f7F800000;
	mov.f32 	%f1432, 0f7F800000;
	@%p111 bra 	$L__BB0_89;

	fma.rn.f32 	%f1432, %f126, %f125, %f126;

$L__BB0_89:
	setp.lt.f32 	%p112, %f70, 0f00000000;
	and.pred  	%p5, %p112, %p83;
	setp.eq.f32 	%p114, %f70, 0f00000000;
	@%p114 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	add.f32 	%f820, %f70, %f70;
	selp.f32 	%f1434, %f820, 0f00000000, %p83;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.b32 	%r279, %f1432;
	xor.b32  	%r280, %r279, -2147483648;
	mov.b32 	%f816, %r280;
	selp.f32 	%f1434, %f816, %f1432, %p5;
	setp.geu.f32 	%p115, %f70, 0f00000000;
	@%p115 bra 	$L__BB0_94;

	mov.f32 	%f817, 0f3EE66666;
	cvt.rzi.f32.f32 	%f818, %f817;
	setp.eq.f32 	%p116, %f818, 0f3EE66666;
	@%p116 bra 	$L__BB0_94;

	mov.f32 	%f1434, 0f7FFFFFFF;

$L__BB0_94:
	abs.f32 	%f1380, %f70;
	add.f32 	%f821, %f1380, 0f3EE66666;
	mov.b32 	%r281, %f821;
	setp.lt.s32 	%p118, %r281, 2139095040;
	@%p118 bra 	$L__BB0_99;

	abs.f32 	%f1381, %f70;
	setp.gtu.f32 	%p119, %f1381, 0f7F800000;
	@%p119 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	add.f32 	%f1434, %f70, 0f3EE66666;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	abs.f32 	%f1382, %f70;
	setp.neu.f32 	%p120, %f1382, 0f7F800000;
	@%p120 bra 	$L__BB0_99;

	selp.f32 	%f1434, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	setp.eq.f32 	%p121, %f70, 0f3F800000;
	mov.f32 	%f823, 0f3F800000;
	selp.f32 	%f824, 0f3F800000, %f1434, %p121;
	ld.const.u32 	%r282, [params+136];
	mad.lo.s32 	%r283, %r282, %r4, %r3;
	cvt.u64.u32 	%rd18, %r283;
	min.f32 	%f825, %f111, %f823;
	mov.f32 	%f826, 0f00000000;
	max.f32 	%f135, %f826, %f825;
	min.f32 	%f827, %f123, %f823;
	max.f32 	%f136, %f826, %f827;
	min.f32 	%f828, %f824, %f823;
	max.f32 	%f137, %f826, %f828;
	mov.f32 	%f832, 0f3ED55555;
	abs.f32 	%f139, %f135;
	setp.lt.f32 	%p122, %f139, 0f00800000;
	mul.f32 	%f834, %f139, 0f4B800000;
	selp.f32 	%f835, %f834, %f139, %p122;
	selp.f32 	%f836, 0fC3170000, 0fC2FE0000, %p122;
	mov.b32 	%r284, %f835;
	and.b32  	%r285, %r284, 8388607;
	or.b32  	%r286, %r285, 1065353216;
	mov.b32 	%f837, %r286;
	shr.u32 	%r287, %r284, 23;
	cvt.rn.f32.u32 	%f838, %r287;
	add.f32 	%f839, %f836, %f838;
	setp.gt.f32 	%p123, %f837, 0f3FB504F3;
	mul.f32 	%f840, %f837, 0f3F000000;
	add.f32 	%f841, %f839, 0f3F800000;
	selp.f32 	%f842, %f841, %f839, %p123;
	selp.f32 	%f843, %f840, %f837, %p123;
	add.f32 	%f844, %f843, 0fBF800000;
	add.f32 	%f845, %f843, 0f3F800000;
	rcp.approx.ftz.f32 	%f846, %f845;
	add.f32 	%f847, %f844, %f844;
	mul.f32 	%f848, %f847, %f846;
	mul.f32 	%f849, %f848, %f848;
	mov.f32 	%f850, 0f3C4CAF63;
	mov.f32 	%f851, 0f3B18F0FE;
	fma.rn.f32 	%f852, %f851, %f849, %f850;
	mov.f32 	%f853, 0f3DAAAABD;
	fma.rn.f32 	%f854, %f852, %f849, %f853;
	mul.rn.f32 	%f855, %f854, %f849;
	mul.rn.f32 	%f856, %f855, %f848;
	sub.f32 	%f857, %f844, %f848;
	add.f32 	%f858, %f857, %f857;
	neg.f32 	%f859, %f848;
	fma.rn.f32 	%f860, %f859, %f844, %f858;
	mul.rn.f32 	%f861, %f846, %f860;
	add.f32 	%f862, %f856, %f848;
	sub.f32 	%f863, %f848, %f862;
	add.f32 	%f864, %f856, %f863;
	add.f32 	%f865, %f861, %f864;
	add.f32 	%f866, %f862, %f865;
	sub.f32 	%f867, %f862, %f866;
	add.f32 	%f868, %f865, %f867;
	mov.f32 	%f869, 0f3F317200;
	mul.rn.f32 	%f870, %f842, %f869;
	mov.f32 	%f871, 0f35BFBE8E;
	mul.rn.f32 	%f872, %f842, %f871;
	add.f32 	%f873, %f870, %f866;
	sub.f32 	%f874, %f870, %f873;
	add.f32 	%f875, %f866, %f874;
	add.f32 	%f876, %f868, %f875;
	add.f32 	%f877, %f872, %f876;
	add.f32 	%f878, %f873, %f877;
	sub.f32 	%f879, %f873, %f878;
	add.f32 	%f880, %f877, %f879;
	mul.rn.f32 	%f881, %f832, %f878;
	neg.f32 	%f882, %f881;
	fma.rn.f32 	%f883, %f832, %f878, %f882;
	fma.rn.f32 	%f884, %f832, %f880, %f883;
	fma.rn.f32 	%f885, %f826, %f878, %f884;
	add.rn.f32 	%f886, %f881, %f885;
	neg.f32 	%f887, %f886;
	add.rn.f32 	%f888, %f881, %f887;
	add.rn.f32 	%f889, %f888, %f885;
	mov.b32 	%r288, %f886;
	setp.eq.s32 	%p124, %r288, 1118925336;
	add.s32 	%r289, %r288, -1;
	mov.b32 	%f890, %r289;
	add.f32 	%f891, %f889, 0f37000000;
	selp.f32 	%f140, %f891, %f889, %p124;
	selp.f32 	%f892, %f890, %f886, %p124;
	mov.f32 	%f893, 0f3FB8AA3B;
	mul.rn.f32 	%f894, %f892, %f893;
	cvt.rzi.f32.f32 	%f895, %f894;
	abs.f32 	%f896, %f895;
	setp.gt.f32 	%p125, %f896, 0f42FC0000;
	mov.b32 	%r290, %f895;
	and.b32  	%r291, %r290, -2147483648;
	or.b32  	%r292, %r291, 1123811328;
	mov.b32 	%f897, %r292;
	selp.f32 	%f898, %f897, %f895, %p125;
	mov.f32 	%f899, 0fBF317218;
	fma.rn.f32 	%f900, %f898, %f899, %f892;
	mov.f32 	%f901, 0f3102E308;
	fma.rn.f32 	%f902, %f898, %f901, %f900;
	mul.f32 	%f903, %f902, 0f3FB8AA3B;
	add.f32 	%f904, %f898, 0f4B40007F;
	mov.b32 	%r293, %f904;
	shl.b32 	%r294, %r293, 23;
	mov.b32 	%f905, %r294;
	ex2.approx.ftz.f32 	%f906, %f903;
	mul.f32 	%f141, %f906, %f905;
	setp.eq.f32 	%p126, %f141, 0f7F800000;
	mov.f32 	%f1435, 0f7F800000;
	@%p126 bra 	$L__BB0_101;

	fma.rn.f32 	%f1435, %f141, %f140, %f141;

$L__BB0_101:
	mov.f32 	%f1345, 0f3E555555;
	cvt.rzi.f32.f32 	%f1344, %f1345;
	add.f32 	%f1343, %f1344, %f1344;
	mov.f32 	%f1342, 0f3ED55555;
	sub.f32 	%f1341, %f1342, %f1343;
	abs.f32 	%f1340, %f1341;
	setp.lt.f32 	%p127, %f135, 0f00000000;
	setp.eq.f32 	%p128, %f1340, 0f3F800000;
	and.pred  	%p6, %p127, %p128;
	setp.eq.f32 	%p129, %f135, 0f00000000;
	@%p129 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f911, %f135, %f135;
	selp.f32 	%f1437, %f911, 0f00000000, %p128;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r295, %f1435;
	xor.b32  	%r296, %r295, -2147483648;
	mov.b32 	%f907, %r296;
	selp.f32 	%f1437, %f907, %f1435, %p6;
	setp.geu.f32 	%p130, %f135, 0f00000000;
	@%p130 bra 	$L__BB0_106;

	mov.f32 	%f908, 0f3ED55555;
	cvt.rzi.f32.f32 	%f909, %f908;
	setp.eq.f32 	%p131, %f909, 0f3ED55555;
	@%p131 bra 	$L__BB0_106;

	mov.f32 	%f1437, 0f7FFFFFFF;

$L__BB0_106:
	mov.f32 	%f1348, 0f00000000;
	max.f32 	%f1347, %f1348, %f825;
	abs.f32 	%f1346, %f1347;
	add.f32 	%f912, %f1346, 0f3ED55555;
	mov.b32 	%r297, %f912;
	setp.lt.s32 	%p133, %r297, 2139095040;
	@%p133 bra 	$L__BB0_111;

	mov.f32 	%f1351, 0f00000000;
	max.f32 	%f1350, %f1351, %f825;
	abs.f32 	%f1349, %f1350;
	setp.gtu.f32 	%p134, %f1349, 0f7F800000;
	@%p134 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1437, %f135, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	mov.f32 	%f1354, 0f00000000;
	max.f32 	%f1353, %f1354, %f825;
	abs.f32 	%f1352, %f1353;
	setp.neu.f32 	%p135, %f1352, 0f7F800000;
	@%p135 bra 	$L__BB0_111;

	selp.f32 	%f1437, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	abs.f32 	%f150, %f136;
	setp.lt.f32 	%p136, %f150, 0f00800000;
	mul.f32 	%f914, %f150, 0f4B800000;
	selp.f32 	%f915, %f914, %f150, %p136;
	selp.f32 	%f916, 0fC3170000, 0fC2FE0000, %p136;
	mov.b32 	%r298, %f915;
	and.b32  	%r299, %r298, 8388607;
	or.b32  	%r300, %r299, 1065353216;
	mov.b32 	%f917, %r300;
	shr.u32 	%r301, %r298, 23;
	cvt.rn.f32.u32 	%f918, %r301;
	add.f32 	%f919, %f916, %f918;
	setp.gt.f32 	%p137, %f917, 0f3FB504F3;
	mul.f32 	%f920, %f917, 0f3F000000;
	add.f32 	%f921, %f919, 0f3F800000;
	selp.f32 	%f922, %f921, %f919, %p137;
	selp.f32 	%f923, %f920, %f917, %p137;
	add.f32 	%f924, %f923, 0fBF800000;
	add.f32 	%f925, %f923, 0f3F800000;
	rcp.approx.ftz.f32 	%f926, %f925;
	add.f32 	%f927, %f924, %f924;
	mul.f32 	%f928, %f927, %f926;
	mul.f32 	%f929, %f928, %f928;
	mov.f32 	%f930, 0f3C4CAF63;
	mov.f32 	%f931, 0f3B18F0FE;
	fma.rn.f32 	%f932, %f931, %f929, %f930;
	mov.f32 	%f933, 0f3DAAAABD;
	fma.rn.f32 	%f934, %f932, %f929, %f933;
	mul.rn.f32 	%f935, %f934, %f929;
	mul.rn.f32 	%f936, %f935, %f928;
	sub.f32 	%f937, %f924, %f928;
	add.f32 	%f938, %f937, %f937;
	neg.f32 	%f939, %f928;
	fma.rn.f32 	%f940, %f939, %f924, %f938;
	mul.rn.f32 	%f941, %f926, %f940;
	add.f32 	%f942, %f936, %f928;
	sub.f32 	%f943, %f928, %f942;
	add.f32 	%f944, %f936, %f943;
	add.f32 	%f945, %f941, %f944;
	add.f32 	%f946, %f942, %f945;
	sub.f32 	%f947, %f942, %f946;
	add.f32 	%f948, %f945, %f947;
	mov.f32 	%f949, 0f3F317200;
	mul.rn.f32 	%f950, %f922, %f949;
	mov.f32 	%f951, 0f35BFBE8E;
	mul.rn.f32 	%f952, %f922, %f951;
	add.f32 	%f953, %f950, %f946;
	sub.f32 	%f954, %f950, %f953;
	add.f32 	%f955, %f946, %f954;
	add.f32 	%f956, %f948, %f955;
	add.f32 	%f957, %f952, %f956;
	add.f32 	%f958, %f953, %f957;
	sub.f32 	%f959, %f953, %f958;
	add.f32 	%f960, %f957, %f959;
	mov.f32 	%f961, 0f3ED55555;
	mul.rn.f32 	%f962, %f961, %f958;
	neg.f32 	%f963, %f962;
	fma.rn.f32 	%f964, %f961, %f958, %f963;
	fma.rn.f32 	%f965, %f961, %f960, %f964;
	mov.f32 	%f966, 0f00000000;
	fma.rn.f32 	%f967, %f966, %f958, %f965;
	add.rn.f32 	%f968, %f962, %f967;
	neg.f32 	%f969, %f968;
	add.rn.f32 	%f970, %f962, %f969;
	add.rn.f32 	%f971, %f970, %f967;
	mov.b32 	%r302, %f968;
	setp.eq.s32 	%p138, %r302, 1118925336;
	add.s32 	%r303, %r302, -1;
	mov.b32 	%f972, %r303;
	add.f32 	%f973, %f971, 0f37000000;
	selp.f32 	%f151, %f973, %f971, %p138;
	selp.f32 	%f974, %f972, %f968, %p138;
	mov.f32 	%f975, 0f3FB8AA3B;
	mul.rn.f32 	%f976, %f974, %f975;
	cvt.rzi.f32.f32 	%f977, %f976;
	abs.f32 	%f978, %f977;
	setp.gt.f32 	%p139, %f978, 0f42FC0000;
	mov.b32 	%r304, %f977;
	and.b32  	%r305, %r304, -2147483648;
	or.b32  	%r306, %r305, 1123811328;
	mov.b32 	%f979, %r306;
	selp.f32 	%f980, %f979, %f977, %p139;
	mov.f32 	%f981, 0fBF317218;
	fma.rn.f32 	%f982, %f980, %f981, %f974;
	mov.f32 	%f983, 0f3102E308;
	fma.rn.f32 	%f984, %f980, %f983, %f982;
	mul.f32 	%f985, %f984, 0f3FB8AA3B;
	add.f32 	%f986, %f980, 0f4B40007F;
	mov.b32 	%r307, %f986;
	shl.b32 	%r308, %r307, 23;
	mov.b32 	%f987, %r308;
	ex2.approx.ftz.f32 	%f988, %f985;
	mul.f32 	%f152, %f988, %f987;
	setp.eq.f32 	%p140, %f152, 0f7F800000;
	mov.f32 	%f1438, 0f7F800000;
	@%p140 bra 	$L__BB0_113;

	fma.rn.f32 	%f1438, %f152, %f151, %f152;

$L__BB0_113:
	setp.lt.f32 	%p141, %f136, 0f00000000;
	and.pred  	%p7, %p141, %p128;
	setp.eq.f32 	%p143, %f136, 0f00000000;
	@%p143 bra 	$L__BB0_117;
	bra.uni 	$L__BB0_114;

$L__BB0_117:
	add.f32 	%f993, %f136, %f136;
	selp.f32 	%f1440, %f993, 0f00000000, %p128;
	bra.uni 	$L__BB0_118;

$L__BB0_114:
	mov.b32 	%r309, %f1438;
	xor.b32  	%r310, %r309, -2147483648;
	mov.b32 	%f989, %r310;
	selp.f32 	%f1440, %f989, %f1438, %p7;
	setp.geu.f32 	%p144, %f136, 0f00000000;
	@%p144 bra 	$L__BB0_118;

	mov.f32 	%f990, 0f3ED55555;
	cvt.rzi.f32.f32 	%f991, %f990;
	setp.eq.f32 	%p145, %f991, 0f3ED55555;
	@%p145 bra 	$L__BB0_118;

	mov.f32 	%f1440, 0f7FFFFFFF;

$L__BB0_118:
	mov.f32 	%f1385, 0f00000000;
	max.f32 	%f1384, %f1385, %f827;
	abs.f32 	%f1383, %f1384;
	add.f32 	%f994, %f1383, 0f3ED55555;
	mov.b32 	%r311, %f994;
	setp.lt.s32 	%p147, %r311, 2139095040;
	@%p147 bra 	$L__BB0_123;

	mov.f32 	%f1388, 0f00000000;
	max.f32 	%f1387, %f1388, %f827;
	abs.f32 	%f1386, %f1387;
	setp.gtu.f32 	%p148, %f1386, 0f7F800000;
	@%p148 bra 	$L__BB0_122;
	bra.uni 	$L__BB0_120;

$L__BB0_122:
	add.f32 	%f1440, %f136, 0f3ED55555;
	bra.uni 	$L__BB0_123;

$L__BB0_120:
	mov.f32 	%f1391, 0f00000000;
	max.f32 	%f1390, %f1391, %f827;
	abs.f32 	%f1389, %f1390;
	setp.neu.f32 	%p149, %f1389, 0f7F800000;
	@%p149 bra 	$L__BB0_123;

	selp.f32 	%f1440, 0fFF800000, 0f7F800000, %p7;

$L__BB0_123:
	abs.f32 	%f161, %f137;
	setp.lt.f32 	%p150, %f161, 0f00800000;
	mul.f32 	%f996, %f161, 0f4B800000;
	selp.f32 	%f997, %f996, %f161, %p150;
	selp.f32 	%f998, 0fC3170000, 0fC2FE0000, %p150;
	mov.b32 	%r312, %f997;
	and.b32  	%r313, %r312, 8388607;
	or.b32  	%r314, %r313, 1065353216;
	mov.b32 	%f999, %r314;
	shr.u32 	%r315, %r312, 23;
	cvt.rn.f32.u32 	%f1000, %r315;
	add.f32 	%f1001, %f998, %f1000;
	setp.gt.f32 	%p151, %f999, 0f3FB504F3;
	mul.f32 	%f1002, %f999, 0f3F000000;
	add.f32 	%f1003, %f1001, 0f3F800000;
	selp.f32 	%f1004, %f1003, %f1001, %p151;
	selp.f32 	%f1005, %f1002, %f999, %p151;
	add.f32 	%f1006, %f1005, 0fBF800000;
	add.f32 	%f1007, %f1005, 0f3F800000;
	rcp.approx.ftz.f32 	%f1008, %f1007;
	add.f32 	%f1009, %f1006, %f1006;
	mul.f32 	%f1010, %f1009, %f1008;
	mul.f32 	%f1011, %f1010, %f1010;
	mov.f32 	%f1012, 0f3C4CAF63;
	mov.f32 	%f1013, 0f3B18F0FE;
	fma.rn.f32 	%f1014, %f1013, %f1011, %f1012;
	mov.f32 	%f1015, 0f3DAAAABD;
	fma.rn.f32 	%f1016, %f1014, %f1011, %f1015;
	mul.rn.f32 	%f1017, %f1016, %f1011;
	mul.rn.f32 	%f1018, %f1017, %f1010;
	sub.f32 	%f1019, %f1006, %f1010;
	add.f32 	%f1020, %f1019, %f1019;
	neg.f32 	%f1021, %f1010;
	fma.rn.f32 	%f1022, %f1021, %f1006, %f1020;
	mul.rn.f32 	%f1023, %f1008, %f1022;
	add.f32 	%f1024, %f1018, %f1010;
	sub.f32 	%f1025, %f1010, %f1024;
	add.f32 	%f1026, %f1018, %f1025;
	add.f32 	%f1027, %f1023, %f1026;
	add.f32 	%f1028, %f1024, %f1027;
	sub.f32 	%f1029, %f1024, %f1028;
	add.f32 	%f1030, %f1027, %f1029;
	mov.f32 	%f1031, 0f3F317200;
	mul.rn.f32 	%f1032, %f1004, %f1031;
	mov.f32 	%f1033, 0f35BFBE8E;
	mul.rn.f32 	%f1034, %f1004, %f1033;
	add.f32 	%f1035, %f1032, %f1028;
	sub.f32 	%f1036, %f1032, %f1035;
	add.f32 	%f1037, %f1028, %f1036;
	add.f32 	%f1038, %f1030, %f1037;
	add.f32 	%f1039, %f1034, %f1038;
	add.f32 	%f1040, %f1035, %f1039;
	sub.f32 	%f1041, %f1035, %f1040;
	add.f32 	%f1042, %f1039, %f1041;
	mov.f32 	%f1043, 0f3ED55555;
	mul.rn.f32 	%f1044, %f1043, %f1040;
	neg.f32 	%f1045, %f1044;
	fma.rn.f32 	%f1046, %f1043, %f1040, %f1045;
	fma.rn.f32 	%f1047, %f1043, %f1042, %f1046;
	mov.f32 	%f1048, 0f00000000;
	fma.rn.f32 	%f1049, %f1048, %f1040, %f1047;
	add.rn.f32 	%f1050, %f1044, %f1049;
	neg.f32 	%f1051, %f1050;
	add.rn.f32 	%f1052, %f1044, %f1051;
	add.rn.f32 	%f1053, %f1052, %f1049;
	mov.b32 	%r316, %f1050;
	setp.eq.s32 	%p152, %r316, 1118925336;
	add.s32 	%r317, %r316, -1;
	mov.b32 	%f1054, %r317;
	add.f32 	%f1055, %f1053, 0f37000000;
	selp.f32 	%f162, %f1055, %f1053, %p152;
	selp.f32 	%f1056, %f1054, %f1050, %p152;
	mov.f32 	%f1057, 0f3FB8AA3B;
	mul.rn.f32 	%f1058, %f1056, %f1057;
	cvt.rzi.f32.f32 	%f1059, %f1058;
	abs.f32 	%f1060, %f1059;
	setp.gt.f32 	%p153, %f1060, 0f42FC0000;
	mov.b32 	%r318, %f1059;
	and.b32  	%r319, %r318, -2147483648;
	or.b32  	%r320, %r319, 1123811328;
	mov.b32 	%f1061, %r320;
	selp.f32 	%f1062, %f1061, %f1059, %p153;
	mov.f32 	%f1063, 0fBF317218;
	fma.rn.f32 	%f1064, %f1062, %f1063, %f1056;
	mov.f32 	%f1065, 0f3102E308;
	fma.rn.f32 	%f1066, %f1062, %f1065, %f1064;
	mul.f32 	%f1067, %f1066, 0f3FB8AA3B;
	add.f32 	%f1068, %f1062, 0f4B40007F;
	mov.b32 	%r321, %f1068;
	shl.b32 	%r322, %r321, 23;
	mov.b32 	%f1069, %r322;
	ex2.approx.ftz.f32 	%f1070, %f1067;
	mul.f32 	%f163, %f1070, %f1069;
	setp.eq.f32 	%p154, %f163, 0f7F800000;
	mov.f32 	%f1441, 0f7F800000;
	@%p154 bra 	$L__BB0_125;

	fma.rn.f32 	%f1441, %f163, %f162, %f163;

$L__BB0_125:
	setp.lt.f32 	%p155, %f137, 0f00000000;
	and.pred  	%p8, %p155, %p128;
	setp.eq.f32 	%p157, %f137, 0f00000000;
	@%p157 bra 	$L__BB0_129;
	bra.uni 	$L__BB0_126;

$L__BB0_129:
	add.f32 	%f1075, %f137, %f137;
	selp.f32 	%f1443, %f1075, 0f00000000, %p128;
	bra.uni 	$L__BB0_130;

$L__BB0_126:
	mov.b32 	%r323, %f1441;
	xor.b32  	%r324, %r323, -2147483648;
	mov.b32 	%f1071, %r324;
	selp.f32 	%f1443, %f1071, %f1441, %p8;
	setp.geu.f32 	%p158, %f137, 0f00000000;
	@%p158 bra 	$L__BB0_130;

	mov.f32 	%f1072, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1073, %f1072;
	setp.eq.f32 	%p159, %f1073, 0f3ED55555;
	@%p159 bra 	$L__BB0_130;

	mov.f32 	%f1443, 0f7FFFFFFF;

$L__BB0_130:
	mov.f32 	%f1394, 0f00000000;
	max.f32 	%f1393, %f1394, %f828;
	abs.f32 	%f1392, %f1393;
	add.f32 	%f1076, %f1392, 0f3ED55555;
	mov.b32 	%r325, %f1076;
	setp.lt.s32 	%p161, %r325, 2139095040;
	@%p161 bra 	$L__BB0_135;

	mov.f32 	%f1397, 0f00000000;
	max.f32 	%f1396, %f1397, %f828;
	abs.f32 	%f1395, %f1396;
	setp.gtu.f32 	%p162, %f1395, 0f7F800000;
	@%p162 bra 	$L__BB0_134;
	bra.uni 	$L__BB0_132;

$L__BB0_134:
	add.f32 	%f1443, %f137, 0f3ED55555;
	bra.uni 	$L__BB0_135;

$L__BB0_132:
	mov.f32 	%f1400, 0f00000000;
	max.f32 	%f1399, %f1400, %f828;
	abs.f32 	%f1398, %f1399;
	setp.neu.f32 	%p163, %f1398, 0f7F800000;
	@%p163 bra 	$L__BB0_135;

	selp.f32 	%f1443, 0fFF800000, 0f7F800000, %p8;

$L__BB0_135:
	ld.const.u64 	%rd108, [params+144];
	cvta.to.global.u64 	%rd107, %rd108;
	fma.rn.f32 	%f1077, %f1437, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p164, %f135, 0f3F800000;
	mov.f32 	%f1078, 0f3F800000;
	selp.f32 	%f1079, 0f3F7FFFFF, %f1077, %p164;
	mul.f32 	%f1080, %f135, 0f414EB852;
	setp.lt.f32 	%p165, %f135, 0f3B4D2E1C;
	selp.f32 	%f1081, %f1080, %f1079, %p165;
	fma.rn.f32 	%f1082, %f1440, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p166, %f136, 0f3F800000;
	selp.f32 	%f1083, 0f3F7FFFFF, %f1082, %p166;
	mul.f32 	%f1084, %f136, 0f414EB852;
	setp.lt.f32 	%p167, %f136, 0f3B4D2E1C;
	selp.f32 	%f1085, %f1084, %f1083, %p167;
	fma.rn.f32 	%f1086, %f1443, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p168, %f137, 0f3F800000;
	selp.f32 	%f1087, 0f3F7FFFFF, %f1086, %p168;
	mul.f32 	%f1088, %f137, 0f414EB852;
	setp.lt.f32 	%p169, %f137, 0f3B4D2E1C;
	selp.f32 	%f1089, %f1088, %f1087, %p169;
	min.f32 	%f1090, %f1081, %f1078;
	mov.f32 	%f1091, 0f00000000;
	max.f32 	%f1092, %f1091, %f1090;
	mul.f32 	%f1093, %f1092, 0f43800000;
	cvt.rzi.u32.f32 	%r326, %f1093;
	min.u32 	%r327, %r326, 255;
	min.f32 	%f1094, %f1085, %f1078;
	max.f32 	%f1095, %f1091, %f1094;
	mul.f32 	%f1096, %f1095, 0f43800000;
	cvt.rzi.u32.f32 	%r328, %f1096;
	min.u32 	%r329, %r328, 255;
	min.f32 	%f1097, %f1089, %f1078;
	max.f32 	%f1098, %f1091, %f1097;
	mul.f32 	%f1099, %f1098, 0f43800000;
	cvt.rzi.u32.f32 	%r330, %f1099;
	min.u32 	%r331, %r330, 255;
	shl.b64 	%rd70, %rd18, 2;
	add.s64 	%rd71, %rd107, %rd70;
	cvt.u16.u32 	%rs28, %r331;
	cvt.u16.u32 	%rs29, %r329;
	cvt.u16.u32 	%rs30, %r327;
	mov.u16 	%rs31, 255;
	st.global.v4.u8 	[%rd71], {%rs30, %rs29, %rs28, %rs31};

$L__BB0_136:
	ld.const.u32 	%r361, [params+104];
	and.b32  	%r332, %r361, 4;
	setp.eq.s32 	%p170, %r332, 0;
	@%p170 bra 	$L__BB0_140;

	ld.const.u32 	%r333, [params+108];
	setp.eq.s32 	%p171, %r333, 0;
	ld.const.u64 	%rd72, [params+224];
	cvta.to.global.u64 	%rd73, %rd72;
	ld.const.u32 	%r334, [params+216];
	mad.lo.s32 	%r335, %r334, %r4, %r3;
	mul.wide.u32 	%rd74, %r335, 8;
	add.s64 	%rd19, %rd73, %rd74;
	@%p171 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs39, %rs40, %rs41, %rs42}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1100, %rs39;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1101, %rs40;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1102, %rs41;}

	// end inline asm
	add.f32 	%f1103, %f68, %f1100;
	add.f32 	%f1104, %f69, %f1101;
	add.f32 	%f1105, %f70, %f1102;
	mov.f32 	%f1106, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f1105;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1104;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f1103;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1106;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs35, %rs36, %rs37, %rs38};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1110, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f1110;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f70;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f69;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f68;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs43, %rs44, %rs45, %rs46};

$L__BB0_140:
	ld.const.u64 	%rd75, [params+464];
	cvta.to.global.u64 	%rd76, %rd75;
	ld.const.u32 	%r336, [params+456];
	mad.lo.s32 	%r337, %r336, %r54, %r53;
	mul.wide.u32 	%rd77, %r337, 4;
	add.s64 	%rd20, %rd76, %rd77;
	ld.global.v2.u8 	{%rs47, %rs179}, [%rd20];
	or.b16  	%rs49, %rs47, %rs179;
	and.b16  	%rs50, %rs49, 255;
	setp.eq.s16 	%p172, %rs50, 0;
	@%p172 bra 	$L__BB0_142;

	ld.global.u8 	%rs177, [%rd20+2];
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	ld.global.u8 	%rs177, [%rd20+2];
	setp.eq.s16 	%p173, %rs177, 0;
	mov.f32 	%f1444, 0f00000000;
	mov.u16 	%rs179, 0;
	mov.u16 	%rs180, %rs179;
	mov.f32 	%f1445, %f1444;
	mov.f32 	%f1446, %f1444;
	@%p173 bra 	$L__BB0_144;

$L__BB0_143:
	mov.u16 	%rs180, %rs179;
	cvt.rn.f32.u16 	%f1114, %rs47;
	div.rn.f32 	%f1115, %f1114, 0f437F0000;
	fma.rn.f32 	%f1116, %f1115, 0f40000000, 0fBF800000;
	and.b16  	%rs55, %rs180, 255;
	cvt.rn.f32.u16 	%f1117, %rs55;
	div.rn.f32 	%f1118, %f1117, 0f437F0000;
	fma.rn.f32 	%f1119, %f1118, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f1120, %rs177;
	div.rn.f32 	%f1121, %f1120, 0f437F0000;
	fma.rn.f32 	%f1122, %f1121, 0f40000000, 0fBF800000;
	mul.f32 	%f1123, %f1119, %f1119;
	fma.rn.f32 	%f1124, %f1116, %f1116, %f1123;
	fma.rn.f32 	%f1125, %f1122, %f1122, %f1124;
	sqrt.rn.f32 	%f1126, %f1125;
	rcp.rn.f32 	%f1127, %f1126;
	mul.f32 	%f1446, %f1127, %f1122;
	mul.f32 	%f1445, %f1127, %f1119;
	mul.f32 	%f1444, %f1116, %f1127;
	mov.u16 	%rs179, %rs177;

$L__BB0_144:
	mul.f32 	%f1131, %f1408, %f1446;
	mul.f32 	%f1132, %f1409, %f1445;
	sub.f32 	%f1133, %f1131, %f1132;
	mul.f32 	%f1134, %f1409, %f1444;
	mul.f32 	%f1135, %f1407, %f1446;
	sub.f32 	%f1136, %f1134, %f1135;
	mul.f32 	%f1137, %f1407, %f1445;
	mul.f32 	%f1138, %f1408, %f1444;
	sub.f32 	%f1139, %f1137, %f1138;
	ld.global.u8 	%rs57, [%rd20+3];
	setp.eq.s16 	%p174, %rs57, 0;
	selp.f32 	%f178, 0fBF800000, 0f3F800000, %p174;
	mul.f32 	%f1140, %f1133, %f178;
	mul.f32 	%f1141, %f1136, %f178;
	mul.f32 	%f1142, %f1139, %f178;
	mul.f32 	%f1143, %f1140, 0f00000000;
	mul.f32 	%f1144, %f1141, 0f00000000;
	mul.f32 	%f1145, %f1142, 0f00000000;
	fma.rn.f32 	%f1146, %f1444, 0f3F5105EC, %f1143;
	fma.rn.f32 	%f1147, %f1445, 0f3F5105EC, %f1144;
	fma.rn.f32 	%f1148, %f1446, 0f3F5105EC, %f1145;
	mul.f32 	%f179, %f1407, 0f3F13CD3A;
	add.f32 	%f180, %f179, %f1146;
	mul.f32 	%f181, %f1408, 0f3F13CD3A;
	add.f32 	%f182, %f181, %f1147;
	mul.f32 	%f183, %f1409, 0f3F13CD3A;
	add.f32 	%f184, %f183, %f1148;
	or.b16  	%rs58, %rs47, %rs180;
	or.b16  	%rs15, %rs58, %rs179;
	and.b16  	%rs59, %rs15, 255;
	setp.eq.s16 	%p175, %rs59, 0;
	mov.f32 	%f1450, 0f00000000;
	mov.f32 	%f1447, %f1450;
	mov.f32 	%f1448, %f1450;
	mov.f32 	%f1449, %f1450;
	@%p175 bra 	$L__BB0_146;

	cvt.rn.f32.u16 	%f1149, %rs47;
	div.rn.f32 	%f1150, %f1149, 0f437F0000;
	fma.rn.f32 	%f1151, %f1150, 0f40000000, 0fBF800000;
	and.b16  	%rs61, %rs180, 255;
	cvt.rn.f32.u16 	%f1152, %rs61;
	div.rn.f32 	%f1153, %f1152, 0f437F0000;
	fma.rn.f32 	%f1154, %f1153, 0f40000000, 0fBF800000;
	and.b16  	%rs62, %rs179, 255;
	cvt.rn.f32.u16 	%f1155, %rs62;
	div.rn.f32 	%f1156, %f1155, 0f437F0000;
	fma.rn.f32 	%f1157, %f1156, 0f40000000, 0fBF800000;
	mul.f32 	%f1158, %f1154, %f1154;
	fma.rn.f32 	%f1159, %f1151, %f1151, %f1158;
	fma.rn.f32 	%f1160, %f1157, %f1157, %f1159;
	sqrt.rn.f32 	%f1161, %f1160;
	rcp.rn.f32 	%f1162, %f1161;
	mul.f32 	%f1449, %f1162, %f1157;
	mul.f32 	%f1448, %f1162, %f1154;
	mul.f32 	%f1447, %f1151, %f1162;

$L__BB0_146:
	mul.f32 	%f1166, %f1408, %f1449;
	mul.f32 	%f1167, %f1409, %f1448;
	sub.f32 	%f1168, %f1166, %f1167;
	mul.f32 	%f1169, %f1409, %f1447;
	mul.f32 	%f1170, %f1407, %f1449;
	sub.f32 	%f1171, %f1169, %f1170;
	mul.f32 	%f1172, %f1407, %f1448;
	mul.f32 	%f1173, %f1408, %f1447;
	sub.f32 	%f1174, %f1172, %f1173;
	mul.f32 	%f1175, %f1168, %f178;
	mul.f32 	%f1176, %f1171, %f178;
	mul.f32 	%f1177, %f1174, %f178;
	mul.f32 	%f1178, %f1447, 0f3ED105EC;
	mul.f32 	%f1179, %f1448, 0f3ED105EC;
	mul.f32 	%f1180, %f1449, 0f3ED105EC;
	mul.f32 	%f1181, %f1175, 0f3F3504F3;
	mul.f32 	%f1182, %f1176, 0f3F3504F3;
	mul.f32 	%f1183, %f1177, 0f3F3504F3;
	sub.f32 	%f1184, %f1181, %f1178;
	sub.f32 	%f1185, %f1182, %f1179;
	sub.f32 	%f1186, %f1183, %f1180;
	add.f32 	%f191, %f179, %f1184;
	add.f32 	%f192, %f181, %f1185;
	add.f32 	%f193, %f183, %f1186;
	mov.f32 	%f1451, %f1450;
	mov.f32 	%f1452, %f1450;
	@%p175 bra 	$L__BB0_148;

	cvt.rn.f32.u16 	%f1187, %rs47;
	div.rn.f32 	%f1188, %f1187, 0f437F0000;
	fma.rn.f32 	%f1189, %f1188, 0f40000000, 0fBF800000;
	and.b16  	%rs65, %rs180, 255;
	cvt.rn.f32.u16 	%f1190, %rs65;
	div.rn.f32 	%f1191, %f1190, 0f437F0000;
	fma.rn.f32 	%f1192, %f1191, 0f40000000, 0fBF800000;
	and.b16  	%rs66, %rs179, 255;
	cvt.rn.f32.u16 	%f1193, %rs66;
	div.rn.f32 	%f1194, %f1193, 0f437F0000;
	fma.rn.f32 	%f1195, %f1194, 0f40000000, 0fBF800000;
	mul.f32 	%f1196, %f1192, %f1192;
	fma.rn.f32 	%f1197, %f1189, %f1189, %f1196;
	fma.rn.f32 	%f1198, %f1195, %f1195, %f1197;
	sqrt.rn.f32 	%f1199, %f1198;
	rcp.rn.f32 	%f1200, %f1199;
	mul.f32 	%f1452, %f1200, %f1195;
	mul.f32 	%f1451, %f1200, %f1192;
	mul.f32 	%f1450, %f1189, %f1200;

$L__BB0_148:
	mul.f32 	%f1201, %f1408, %f1452;
	mul.f32 	%f1202, %f1409, %f1451;
	sub.f32 	%f1203, %f1201, %f1202;
	mul.f32 	%f1204, %f1409, %f1450;
	mul.f32 	%f1205, %f1407, %f1452;
	sub.f32 	%f1206, %f1204, %f1205;
	mul.f32 	%f1207, %f1407, %f1451;
	mul.f32 	%f1208, %f1408, %f1450;
	sub.f32 	%f1209, %f1207, %f1208;
	mul.f32 	%f1210, %f1203, %f178;
	mul.f32 	%f1211, %f1206, %f178;
	mul.f32 	%f1212, %f1209, %f178;
	mul.f32 	%f1213, %f1450, 0f3ED105EC;
	mul.f32 	%f1214, %f1451, 0f3ED105EC;
	mul.f32 	%f1215, %f1452, 0f3ED105EC;
	mul.f32 	%f1216, %f1210, 0fBF3504F3;
	mul.f32 	%f1217, %f1211, 0fBF3504F3;
	mul.f32 	%f1218, %f1212, 0fBF3504F3;
	sub.f32 	%f1219, %f1216, %f1213;
	sub.f32 	%f1220, %f1217, %f1214;
	sub.f32 	%f1221, %f1218, %f1215;
	add.f32 	%f1222, %f179, %f1219;
	add.f32 	%f1223, %f181, %f1220;
	add.f32 	%f1224, %f183, %f1221;
	mul.f32 	%f1225, %f182, %f228;
	neg.f32 	%f1226, %f1225;
	mul.f32 	%f1227, %f180, %f227;
	sub.f32 	%f1228, %f1226, %f1227;
	mul.f32 	%f1229, %f184, %f229;
	sub.f32 	%f1230, %f1228, %f1229;
	cvt.sat.f32.f32 	%f1231, %f1230;
	mul.f32 	%f1232, %f84, %f1231;
	mul.f32 	%f1233, %f85, %f1231;
	mul.f32 	%f1234, %f86, %f1231;
	mul.f32 	%f1235, %f192, %f228;
	neg.f32 	%f1236, %f1235;
	mul.f32 	%f1237, %f191, %f227;
	sub.f32 	%f1238, %f1236, %f1237;
	mul.f32 	%f1239, %f193, %f229;
	sub.f32 	%f1240, %f1238, %f1239;
	cvt.sat.f32.f32 	%f1241, %f1240;
	mul.f32 	%f1242, %f84, %f1241;
	mul.f32 	%f1243, %f85, %f1241;
	mul.f32 	%f1244, %f86, %f1241;
	mul.f32 	%f1245, %f1222, %f227;
	mul.f32 	%f1246, %f1223, %f228;
	neg.f32 	%f1247, %f1246;
	sub.f32 	%f1248, %f1247, %f1245;
	mul.f32 	%f1249, %f1224, %f229;
	sub.f32 	%f1250, %f1248, %f1249;
	cvt.sat.f32.f32 	%f1251, %f1250;
	mul.f32 	%f1252, %f84, %f1251;
	mul.f32 	%f1253, %f85, %f1251;
	mul.f32 	%f1254, %f86, %f1251;
	add.f32 	%f1255, %f1232, %f1242;
	add.f32 	%f1256, %f1233, %f1243;
	add.f32 	%f1257, %f1234, %f1244;
	add.f32 	%f1258, %f1255, %f1252;
	add.f32 	%f1259, %f1256, %f1253;
	add.f32 	%f1260, %f1257, %f1254;
	mul.f32 	%f1261, %f1258, 0f3F13CD3A;
	mul.f32 	%f1262, %f1259, 0f3F13CD3A;
	mul.f32 	%f1263, %f1260, 0f3F13CD3A;
	div.rn.f32 	%f1264, %f68, %f1261;
	div.rn.f32 	%f1265, %f69, %f1262;
	div.rn.f32 	%f1266, %f70, %f1263;
	setp.eq.f32 	%p177, %f68, 0f00000000;
	selp.f32 	%f1267, 0f00000000, %f1264, %p177;
	setp.eq.f32 	%p178, %f69, 0f00000000;
	selp.f32 	%f1268, 0f00000000, %f1265, %p178;
	setp.eq.f32 	%p179, %f70, 0f00000000;
	selp.f32 	%f1269, 0f00000000, %f1266, %p179;
	mul.f32 	%f200, %f1232, %f1267;
	mul.f32 	%f201, %f1233, %f1268;
	mul.f32 	%f202, %f1234, %f1269;
	mul.f32 	%f203, %f1242, %f1267;
	mul.f32 	%f204, %f1243, %f1268;
	mul.f32 	%f205, %f1244, %f1269;
	mul.f32 	%f206, %f1252, %f1267;
	mul.f32 	%f207, %f1253, %f1268;
	mul.f32 	%f208, %f1254, %f1269;
	ld.const.u32 	%r49, [params+108];
	setp.eq.s32 	%p180, %r49, 0;
	ld.const.u64 	%rd78, [params+256];
	cvta.to.global.u64 	%rd79, %rd78;
	ld.const.u32 	%r338, [params+248];
	mad.lo.s32 	%r339, %r338, %r4, %r3;
	mul.wide.u32 	%rd80, %r339, 8;
	add.s64 	%rd21, %rd79, %rd80;
	@%p180 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1270, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1271, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1272, %rs76;}

	// end inline asm
	add.f32 	%f1273, %f200, %f1270;
	add.f32 	%f1274, %f201, %f1271;
	add.f32 	%f1275, %f202, %f1272;
	mov.f32 	%f1276, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1275;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1274;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1273;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1276;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1280, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1280;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f202;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f200;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_151:
	ld.const.u64 	%rd81, [params+272];
	cvta.to.global.u64 	%rd82, %rd81;
	ld.const.u32 	%r340, [params+264];
	mad.lo.s32 	%r341, %r340, %r4, %r3;
	mul.wide.u32 	%rd83, %r341, 8;
	add.s64 	%rd22, %rd82, %rd83;
	@%p180 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1281, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1282, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1283, %rs91;}

	// end inline asm
	add.f32 	%f1284, %f203, %f1281;
	add.f32 	%f1285, %f204, %f1282;
	add.f32 	%f1286, %f205, %f1283;
	mov.f32 	%f1287, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1286;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1285;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1284;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1287;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1291, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1291;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f205;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f204;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f203;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_154:
	ld.const.u64 	%rd84, [params+288];
	cvta.to.global.u64 	%rd85, %rd84;
	ld.const.u32 	%r342, [params+280];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	mul.wide.u32 	%rd86, %r343, 8;
	add.s64 	%rd23, %rd85, %rd86;
	@%p180 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs104, %rs105, %rs106, %rs107}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1292, %rs104;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1293, %rs105;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1294, %rs106;}

	// end inline asm
	add.f32 	%f1295, %f206, %f1292;
	add.f32 	%f1296, %f207, %f1293;
	add.f32 	%f1297, %f208, %f1294;
	mov.f32 	%f1298, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs102, %f1297;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs101, %f1296;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1295;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1298;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs100, %rs101, %rs102, %rs103};
	bra.uni 	$L__BB0_174;

$L__BB0_156:
	mov.f32 	%f1302, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1302;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs110, %f208;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs109, %f207;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f206;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs108, %rs109, %rs110, %rs111};

$L__BB0_174:
	ret;

}