//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<171>;
	.reg .b16 	%rs<178>;
	.reg .f32 	%f<1124>;
	.reg .b32 	%r<369>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<121>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r54), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r55), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd31, [params+400];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r60, [params+392];
	mad.lo.s32 	%r61, %r60, %r55, %r54;
	mul.wide.u32 	%rd33, %r61, 4;
	add.s64 	%rd2, %rd32, %rd33;
	ld.global.v2.u8 	{%rs7, %rs177}, [%rd2];
	or.b16  	%rs9, %rs7, %rs177;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p8, %rs10, 0;
	@%p8 bra 	$L__BB0_2;

	ld.global.u8 	%rs176, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs176, [%rd2+2];
	setp.eq.s16 	%p9, %rs176, 0;
	mov.f32 	%f1090, 0f00000000;
	mov.u16 	%rs177, 0;
	mov.f32 	%f1091, %f1090;
	mov.f32 	%f1092, %f1090;
	@%p9 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f158, %rs7;
	div.rn.f32 	%f159, %f158, 0f437F0000;
	fma.rn.f32 	%f160, %f159, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs177, 255;
	cvt.rn.f32.u16 	%f161, %rs13;
	div.rn.f32 	%f162, %f161, 0f437F0000;
	fma.rn.f32 	%f163, %f162, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f164, %rs176;
	div.rn.f32 	%f165, %f164, 0f437F0000;
	fma.rn.f32 	%f166, %f165, 0f40000000, 0fBF800000;
	mul.f32 	%f167, %f163, %f163;
	fma.rn.f32 	%f168, %f160, %f160, %f167;
	fma.rn.f32 	%f169, %f166, %f166, %f168;
	sqrt.rn.f32 	%f170, %f169;
	rcp.rn.f32 	%f171, %f170;
	mul.f32 	%f1092, %f171, %f166;
	mul.f32 	%f1091, %f171, %f163;
	mul.f32 	%f1090, %f160, %f171;

$L__BB0_4:
	ld.const.v2.u32 	{%r62, %r63}, [params];
	add.s32 	%r3, %r62, %r54;
	add.s32 	%r4, %r63, %r55;
	setp.eq.f32 	%p10, %f1090, 0f00000000;
	setp.eq.f32 	%p11, %f1091, 0f00000000;
	and.pred  	%p12, %p10, %p11;
	setp.eq.f32 	%p13, %f1092, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	@%p14 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_5;

$L__BB0_140:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r331, %r51, 1;
	setp.eq.b32 	%p160, %r331, 1;
	mov.pred 	%p161, 0;
	xor.pred  	%p162, %p160, %p161;
	not.pred 	%p163, %p162;
	@%p163 bra 	$L__BB0_142;

	ld.const.u64 	%rd87, [params+144];
	cvta.to.global.u64 	%rd88, %rd87;
	ld.const.u32 	%r332, [params+136];
	mad.lo.s32 	%r333, %r332, %r4, %r3;
	mul.wide.u32 	%rd89, %r333, 4;
	add.s64 	%rd90, %rd88, %rd89;
	mov.u16 	%rs98, 0;
	st.global.v4.u8 	[%rd90], {%rs98, %rs98, %rs98, %rs98};

$L__BB0_142:
	and.b32  	%r334, %r51, 8;
	setp.eq.s32 	%p164, %r334, 0;
	@%p164 bra 	$L__BB0_144;

	ld.const.u64 	%rd91, [params+192];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r335, [params+184];
	mad.lo.s32 	%r336, %r335, %r4, %r3;
	mov.f32 	%f996, 0f00000000;
	cvt.rzi.u32.f32 	%r337, %f996;
	mul.wide.u32 	%rd93, %r336, 2;
	add.s64 	%rd94, %rd92, %rd93;
	mov.u16 	%rs99, 0;
	cvt.u16.u32 	%rs100, %r337;
	st.global.v2.u8 	[%rd94], {%rs100, %rs99};

$L__BB0_144:
	and.b32  	%r338, %r51, 4;
	setp.eq.s32 	%p165, %r338, 0;
	ld.const.u32 	%r368, [params+108];
	@%p165 bra 	$L__BB0_148;

	setp.eq.s32 	%p166, %r368, 0;
	ld.const.u64 	%rd95, [params+224];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r339, [params+216];
	mad.lo.s32 	%r340, %r339, %r4, %r3;
	mul.wide.u32 	%rd97, %r340, 8;
	add.s64 	%rd25, %rd96, %rd97;
	@%p166 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs107, %rs108, %rs109, %rs110}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f997, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f998, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f999, %rs109;}

	// end inline asm
	add.f32 	%f1000, %f997, 0f00000000;
	add.f32 	%f1001, %f998, 0f00000000;
	add.f32 	%f1002, %f999, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1002;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1001;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1000;}

	// end inline asm
	mov.u16 	%rs111, 0;
	st.global.v4.u16 	[%rd25], {%rs104, %rs105, %rs106, %rs111};
	bra.uni 	$L__BB0_148;

$L__BB0_5:
	ld.const.v4.f32 	{%f173, %f174, %f175, %f176}, [params+512];
	neg.f32 	%f177, %f174;
	neg.f32 	%f178, %f175;
	mul.f32 	%f179, %f1090, %f173;
	mul.f32 	%f180, %f1091, %f177;
	sub.f32 	%f181, %f180, %f179;
	mul.f32 	%f182, %f1092, %f175;
	sub.f32 	%f13, %f181, %f182;
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r66, [params+424];
	mad.lo.s32 	%r67, %r66, %r55, %r54;
	mul.wide.u32 	%rd36, %r67, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f183, [%rd37];
	mul.f32 	%f184, %f183, 0f3456BF95;
	ld.global.f32 	%f185, [%rd37+4];
	mul.f32 	%f186, %f185, 0f3456BF95;
	ld.global.f32 	%f187, [%rd37+8];
	mul.f32 	%f188, %f187, 0f3456BF95;
	abs.f32 	%f189, %f1090;
	div.rn.f32 	%f190, %f184, %f189;
	abs.f32 	%f191, %f1091;
	div.rn.f32 	%f192, %f186, %f191;
	abs.f32 	%f193, %f1092;
	div.rn.f32 	%f194, %f188, %f193;
	abs.f32 	%f195, %f190;
	abs.f32 	%f196, %f192;
	abs.f32 	%f197, %f194;
	mov.f32 	%f198, 0f38D1B717;
	max.f32 	%f199, %f195, %f198;
	max.f32 	%f200, %f196, %f198;
	max.f32 	%f201, %f197, %f198;
	fma.rn.f32 	%f14, %f1090, %f199, %f183;
	fma.rn.f32 	%f15, %f1091, %f200, %f185;
	fma.rn.f32 	%f16, %f1092, %f201, %f187;
	abs.f32 	%f202, %f173;
	abs.f32 	%f203, %f175;
	setp.gt.f32 	%p15, %f202, %f203;
	selp.f32 	%f204, %f177, 0f00000000, %p15;
	mov.f32 	%f1094, 0f00000000;
	selp.f32 	%f205, %f173, %f178, %p15;
	selp.f32 	%f206, 0f00000000, %f174, %p15;
	mul.f32 	%f207, %f205, %f205;
	fma.rn.f32 	%f208, %f204, %f204, %f207;
	fma.rn.f32 	%f209, %f206, %f206, %f208;
	sqrt.rn.f32 	%f210, %f209;
	rcp.rn.f32 	%f211, %f210;
	mul.f32 	%f17, %f204, %f211;
	mul.f32 	%f18, %f205, %f211;
	mul.f32 	%f19, %f206, %f211;
	ld.const.u64 	%rd38, [params+128];
	cvta.to.global.u64 	%rd39, %rd38;
	ld.const.u32 	%r68, [params+120];
	mad.lo.s32 	%r69, %r68, %r55, %r54;
	mul.wide.u32 	%rd40, %r69, 4;
	add.s64 	%rd3, %rd39, %rd40;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p16, %r5, 1;
	@%p16 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f213, %r5;
	rcp.rn.f32 	%f20, %f213;
	ld.global.u32 	%r359, [%rd3];
	ld.const.f32 	%f21, [params+536];
	ld.const.u8 	%rs15, [params+104];
	and.b16  	%rs16, %rs15, 32;
	setp.eq.s16 	%p17, %rs16, 0;
	mov.u32 	%r70, 0;
	selp.f32 	%f22, 0f3F800000, 0f41200000, %p17;
	mul.f32 	%f23, %f14, 0f3456BF95;
	mul.f32 	%f24, %f15, 0f3456BF95;
	mul.f32 	%f25, %f16, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f214, %f173, %f18;
	mul.f32 	%f215, %f174, %f17;
	sub.f32 	%f26, %f215, %f214;
	mul.f32 	%f216, %f175, %f17;
	mul.f32 	%f217, %f173, %f19;
	sub.f32 	%f27, %f217, %f216;
	mul.f32 	%f218, %f174, %f19;
	mul.f32 	%f219, %f175, %f18;
	sub.f32 	%f28, %f219, %f218;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd41, __cudart_i2opi_f;
	abs.f32 	%f302, %f24;
	abs.f32 	%f303, %f23;
	max.f32 	%f304, %f303, %f302;
	abs.f32 	%f305, %f25;
	max.f32 	%f306, %f304, %f305;
	mov.u32 	%r356, %r70;

$L__BB0_7:
	cvt.rn.f32.s32 	%f30, %r356;
	mov.u32 	%r358, %r70;

$L__BB0_8:
	mad.lo.s32 	%r72, %r359, 1664525, 1013904223;
	and.b32  	%r73, %r72, 16777215;
	cvt.rn.f32.u32 	%f220, %r73;
	fma.rn.f32 	%f221, %f220, 0f33800000, %f30;
	mul.f32 	%f222, %f20, %f221;
	mad.lo.s32 	%r359, %r72, 1664525, 1013904223;
	and.b32  	%r74, %r359, 16777215;
	cvt.rn.f32.u32 	%f223, %r74;
	cvt.rn.f32.s32 	%f224, %r358;
	fma.rn.f32 	%f225, %f223, 0f33800000, %f224;
	mul.f32 	%f226, %f20, %f225;
	sqrt.rn.f32 	%f32, %f222;
	mul.f32 	%f33, %f226, 0f40C90FDB;
	mul.f32 	%f227, %f33, 0f3F22F983;
	cvt.rni.s32.f32 	%r366, %f227;
	cvt.rn.f32.s32 	%f228, %r366;
	mov.f32 	%f229, 0fBFC90FDA;
	fma.rn.f32 	%f230, %f228, %f229, %f33;
	mov.f32 	%f231, 0fB3A22168;
	fma.rn.f32 	%f232, %f228, %f231, %f230;
	mov.f32 	%f233, 0fA7C234C5;
	fma.rn.f32 	%f1098, %f228, %f233, %f232;
	abs.f32 	%f35, %f33;
	setp.ltu.f32 	%p18, %f35, 0f47CE4780;
	mov.u32 	%r363, %r366;
	mov.f32 	%f1095, %f1098;
	@%p18 bra 	$L__BB0_16;

	setp.eq.f32 	%p19, %f35, 0f7F800000;
	@%p19 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f236, 0f00000000;
	mul.rn.f32 	%f1095, %f33, %f236;
	mov.u32 	%r363, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f33;
	bfe.u32 	%r76, %r13, 23, 8;
	add.s32 	%r14, %r76, -128;
	shl.b32 	%r77, %r13, 8;
	or.b32  	%r15, %r77, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd118, 0;
	mov.u32 	%r360, 0;
	mov.u64 	%rd116, %rd1;
	mov.u64 	%rd117, %rd41;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r78, [%rd117];
	mad.wide.u32 	%rd43, %r78, %r15, %rd118;
	shr.u64 	%rd118, %rd43, 32;
	st.local.u32 	[%rd116], %rd43;
	add.s64 	%rd117, %rd117, 4;
	add.s64 	%rd116, %rd116, 4;
	add.s32 	%r360, %r360, 1;
	setp.ne.s32 	%p20, %r360, 6;
	@%p20 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd118;
	mov.u32 	%r79, 4;
	sub.s32 	%r19, %r79, %r16;
	mov.u32 	%r80, 6;
	sub.s32 	%r81, %r80, %r16;
	mul.wide.s32 	%rd44, %r81, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r361, [%rd45];
	ld.local.u32 	%r362, [%rd45+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p21, %r22, 0;
	@%p21 bra 	$L__BB0_14;

	mov.u32 	%r82, 32;
	sub.s32 	%r83, %r82, %r22;
	shr.u32 	%r84, %r362, %r83;
	shl.b32 	%r85, %r361, %r22;
	add.s32 	%r361, %r84, %r85;
	mul.wide.s32 	%rd46, %r19, 4;
	add.s64 	%rd47, %rd1, %rd46;
	ld.local.u32 	%r86, [%rd47];
	shr.u32 	%r87, %r86, %r83;
	shl.b32 	%r88, %r362, %r22;
	add.s32 	%r362, %r87, %r88;

$L__BB0_14:
	and.b32  	%r89, %r13, -2147483648;
	shr.u32 	%r90, %r362, 30;
	shl.b32 	%r91, %r361, 2;
	or.b32  	%r92, %r90, %r91;
	shr.u32 	%r93, %r92, 31;
	shr.u32 	%r94, %r361, 30;
	add.s32 	%r95, %r93, %r94;
	neg.s32 	%r96, %r95;
	setp.eq.s32 	%p22, %r89, 0;
	selp.b32 	%r363, %r95, %r96, %p22;
	setp.ne.s32 	%p23, %r93, 0;
	xor.b32  	%r97, %r89, -2147483648;
	selp.b32 	%r98, %r97, %r89, %p23;
	selp.b32 	%r99, -1, 0, %p23;
	xor.b32  	%r100, %r92, %r99;
	shl.b32 	%r101, %r362, 2;
	xor.b32  	%r102, %r101, %r99;
	cvt.u64.u32 	%rd48, %r100;
	cvt.u64.u32 	%rd49, %r102;
	bfi.b64 	%rd50, %rd48, %rd49, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd50;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f234, %fd2;
	setp.eq.s32 	%p24, %r98, 0;
	neg.f32 	%f235, %f234;
	selp.f32 	%f1095, %f234, %f235, %p24;

$L__BB0_16:
	add.s32 	%r29, %r363, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p25, %r30, 0;
	selp.f32 	%f39, %f1095, 0f3F800000, %p25;
	mul.rn.f32 	%f40, %f1095, %f1095;
	mov.f32 	%f1096, 0fB94D4153;
	@%p25 bra 	$L__BB0_18;

	mov.f32 	%f238, 0fBAB607ED;
	mov.f32 	%f239, 0f37CBAC00;
	fma.rn.f32 	%f1096, %f239, %f40, %f238;

$L__BB0_18:
	selp.f32 	%f240, 0f3C0885E4, 0f3D2AAABB, %p25;
	fma.rn.f32 	%f241, %f1096, %f40, %f240;
	selp.f32 	%f242, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
	fma.rn.f32 	%f243, %f241, %f40, %f242;
	mov.f32 	%f244, 0f00000000;
	fma.rn.f32 	%f245, %f40, %f39, %f244;
	fma.rn.f32 	%f1097, %f243, %f245, %f39;
	and.b32  	%r104, %r29, 2;
	setp.eq.s32 	%p27, %r104, 0;
	@%p27 bra 	$L__BB0_20;

	mov.f32 	%f247, 0fBF800000;
	fma.rn.f32 	%f1097, %f1097, %f247, %f244;

$L__BB0_20:
	@%p18 bra 	$L__BB0_28;

	setp.eq.f32 	%p29, %f35, 0f7F800000;
	@%p29 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f250, 0f00000000;
	mul.rn.f32 	%f1098, %f33, %f250;
	mov.u32 	%r366, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f33;
	bfe.u32 	%r105, %r31, 23, 8;
	add.s32 	%r32, %r105, -128;
	shl.b32 	%r106, %r31, 8;
	or.b32  	%r33, %r106, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd119, 0;
	mov.u64 	%rd120, %rd119;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd53, %rd119, 2;
	mov.u64 	%rd54, __cudart_i2opi_f;
	add.s64 	%rd55, %rd54, %rd53;
	ld.global.nc.u32 	%r107, [%rd55];
	mad.wide.u32 	%rd56, %r107, %r33, %rd120;
	shr.u64 	%rd120, %rd56, 32;
	add.s64 	%rd57, %rd1, %rd53;
	st.local.u32 	[%rd57], %rd56;
	cvt.u32.u64 	%r108, %rd119;
	add.s32 	%r109, %r108, 1;
	cvt.s64.s32 	%rd119, %r109;
	setp.ne.s32 	%p30, %r109, 6;
	@%p30 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd120;
	mov.u32 	%r110, 4;
	sub.s32 	%r35, %r110, %r34;
	mov.u32 	%r111, 6;
	sub.s32 	%r112, %r111, %r34;
	mul.wide.s32 	%rd58, %r112, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r364, [%rd59];
	ld.local.u32 	%r365, [%rd59+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p31, %r38, 0;
	@%p31 bra 	$L__BB0_26;

	mov.u32 	%r113, 32;
	sub.s32 	%r114, %r113, %r38;
	shr.u32 	%r115, %r365, %r114;
	shl.b32 	%r116, %r364, %r38;
	add.s32 	%r364, %r115, %r116;
	mul.wide.s32 	%rd60, %r35, 4;
	add.s64 	%rd61, %rd1, %rd60;
	ld.local.u32 	%r117, [%rd61];
	shr.u32 	%r118, %r117, %r114;
	shl.b32 	%r119, %r365, %r38;
	add.s32 	%r365, %r118, %r119;

$L__BB0_26:
	and.b32  	%r120, %r31, -2147483648;
	shr.u32 	%r121, %r365, 30;
	shl.b32 	%r122, %r364, 2;
	or.b32  	%r123, %r121, %r122;
	shr.u32 	%r124, %r123, 31;
	shr.u32 	%r125, %r364, 30;
	add.s32 	%r126, %r124, %r125;
	neg.s32 	%r127, %r126;
	setp.eq.s32 	%p32, %r120, 0;
	selp.b32 	%r366, %r126, %r127, %p32;
	setp.ne.s32 	%p33, %r124, 0;
	xor.b32  	%r128, %r120, -2147483648;
	selp.b32 	%r129, %r128, %r120, %p33;
	selp.b32 	%r130, -1, 0, %p33;
	xor.b32  	%r131, %r123, %r130;
	shl.b32 	%r132, %r365, 2;
	xor.b32  	%r133, %r132, %r130;
	cvt.u64.u32 	%rd62, %r131;
	cvt.u64.u32 	%rd63, %r133;
	bfi.b64 	%rd64, %rd62, %rd63, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd64;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f248, %fd4;
	setp.eq.s32 	%p34, %r129, 0;
	neg.f32 	%f249, %f248;
	selp.f32 	%f1098, %f248, %f249, %p34;

$L__BB0_28:
	mul.f32 	%f49, %f32, %f1097;
	and.b32  	%r45, %r366, 1;
	setp.eq.s32 	%p35, %r45, 0;
	selp.f32 	%f50, %f1098, 0f3F800000, %p35;
	mul.rn.f32 	%f51, %f1098, %f1098;
	mov.f32 	%f1099, 0fB94D4153;
	@%p35 bra 	$L__BB0_30;

	mov.f32 	%f252, 0fBAB607ED;
	mov.f32 	%f253, 0f37CBAC00;
	fma.rn.f32 	%f1099, %f253, %f51, %f252;

$L__BB0_30:
	selp.f32 	%f254, 0f3C0885E4, 0f3D2AAABB, %p35;
	fma.rn.f32 	%f255, %f1099, %f51, %f254;
	selp.f32 	%f256, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
	fma.rn.f32 	%f257, %f255, %f51, %f256;
	mov.f32 	%f258, 0f00000000;
	fma.rn.f32 	%f259, %f51, %f50, %f258;
	fma.rn.f32 	%f1100, %f257, %f259, %f50;
	and.b32  	%r135, %r366, 2;
	setp.eq.s32 	%p37, %r135, 0;
	@%p37 bra 	$L__BB0_32;

	mov.f32 	%f261, 0fBF800000;
	fma.rn.f32 	%f1100, %f1100, %f261, %f258;

$L__BB0_32:
	mul.f32 	%f271, %f49, %f49;
	mov.f32 	%f272, 0f3F800000;
	sub.f32 	%f273, %f272, %f271;
	mul.f32 	%f274, %f32, %f1100;
	mul.f32 	%f275, %f274, %f274;
	sub.f32 	%f276, %f273, %f275;
	max.f32 	%f277, %f258, %f276;
	sqrt.rn.f32 	%f278, %f277;
	mul.f32 	%f279, %f17, %f274;
	mul.f32 	%f280, %f18, %f274;
	mul.f32 	%f281, %f19, %f274;
	fma.rn.f32 	%f282, %f28, %f49, %f279;
	fma.rn.f32 	%f283, %f27, %f49, %f280;
	fma.rn.f32 	%f284, %f26, %f49, %f281;
	fma.rn.f32 	%f285, %f173, %f278, %f282;
	fma.rn.f32 	%f286, %f174, %f278, %f283;
	fma.rn.f32 	%f287, %f175, %f278, %f284;
	add.f32 	%f288, %f173, %f285;
	add.f32 	%f289, %f174, %f286;
	add.f32 	%f290, %f175, %f287;
	mul.f32 	%f291, %f21, %f288;
	mul.f32 	%f292, %f21, %f289;
	mul.f32 	%f293, %f21, %f290;
	sub.f32 	%f294, %f291, %f173;
	sub.f32 	%f295, %f292, %f174;
	sub.f32 	%f296, %f293, %f175;
	mul.f32 	%f297, %f295, %f295;
	fma.rn.f32 	%f298, %f294, %f294, %f297;
	fma.rn.f32 	%f299, %f296, %f296, %f298;
	sqrt.rn.f32 	%f300, %f299;
	rcp.rn.f32 	%f301, %f300;
	mul.f32 	%f265, %f301, %f294;
	mul.f32 	%f266, %f301, %f295;
	mul.f32 	%f267, %f301, %f296;
	mov.f32 	%f307, 0f38D1B717;
	max.f32 	%f308, %f306, %f307;
	mul.f32 	%f268, %f22, %f308;
	mov.f32 	%f269, 0f6C4ECB8F;
	mov.u32 	%r172, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f14,%f15,%f16,%f265,%f266,%f267,%f268,%f269,%f258,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f309, %r136;
	add.f32 	%f1094, %f1094, %f309;
	add.s32 	%r358, %r358, 1;
	setp.lt.s32 	%p38, %r358, %r5;
	@%p38 bra 	$L__BB0_8;

	add.s32 	%r356, %r356, 1;
	setp.lt.s32 	%p39, %r356, %r5;
	@%p39 bra 	$L__BB0_7;

$L__BB0_34:
	setp.eq.s32 	%p40, %r5, 0;
	mov.f32 	%f1102, 0f3F800000;
	@%p40 bra 	$L__BB0_36;

	mul.lo.s32 	%r207, %r5, %r5;
	cvt.rn.f32.s32 	%f311, %r207;
	div.rn.f32 	%f1102, %f1094, %f311;

$L__BB0_36:
	ld.const.f32 	%f312, [params+524];
	mul.f32 	%f313, %f1102, %f312;
	ld.const.v2.f32 	{%f314, %f315}, [params+528];
	mul.f32 	%f318, %f1102, %f314;
	mul.f32 	%f319, %f1102, %f315;
	cvt.sat.f32.f32 	%f320, %f13;
	mul.f32 	%f61, %f313, %f320;
	mul.f32 	%f62, %f318, %f320;
	mul.f32 	%f63, %f319, %f320;
	mul.f32 	%f64, %f313, 0f3E800000;
	mul.f32 	%f65, %f318, 0f3E800000;
	mul.f32 	%f66, %f319, 0f3E800000;
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r208, %r48, 8;
	setp.eq.s32 	%p41, %r208, 0;
	@%p41 bra 	$L__BB0_50;

	mov.f32 	%f325, 0f3EE8BA2E;
	abs.f32 	%f68, %f1102;
	setp.lt.f32 	%p42, %f68, 0f00800000;
	mul.f32 	%f327, %f68, 0f4B800000;
	selp.f32 	%f328, %f327, %f68, %p42;
	selp.f32 	%f329, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r211, %f328;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f330, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f331, %r214;
	add.f32 	%f332, %f329, %f331;
	setp.gt.f32 	%p43, %f330, 0f3FB504F3;
	mul.f32 	%f333, %f330, 0f3F000000;
	add.f32 	%f334, %f332, 0f3F800000;
	selp.f32 	%f335, %f334, %f332, %p43;
	selp.f32 	%f336, %f333, %f330, %p43;
	add.f32 	%f337, %f336, 0fBF800000;
	add.f32 	%f338, %f336, 0f3F800000;
	rcp.approx.ftz.f32 	%f339, %f338;
	add.f32 	%f340, %f337, %f337;
	mul.f32 	%f341, %f340, %f339;
	mul.f32 	%f342, %f341, %f341;
	mov.f32 	%f343, 0f3C4CAF63;
	mov.f32 	%f344, 0f3B18F0FE;
	fma.rn.f32 	%f345, %f344, %f342, %f343;
	mov.f32 	%f346, 0f3DAAAABD;
	fma.rn.f32 	%f347, %f345, %f342, %f346;
	mul.rn.f32 	%f348, %f347, %f342;
	mul.rn.f32 	%f349, %f348, %f341;
	sub.f32 	%f350, %f337, %f341;
	add.f32 	%f351, %f350, %f350;
	neg.f32 	%f352, %f341;
	fma.rn.f32 	%f353, %f352, %f337, %f351;
	mul.rn.f32 	%f354, %f339, %f353;
	add.f32 	%f355, %f349, %f341;
	sub.f32 	%f356, %f341, %f355;
	add.f32 	%f357, %f349, %f356;
	add.f32 	%f358, %f354, %f357;
	add.f32 	%f359, %f355, %f358;
	sub.f32 	%f360, %f355, %f359;
	add.f32 	%f361, %f358, %f360;
	mov.f32 	%f362, 0f3F317200;
	mul.rn.f32 	%f363, %f335, %f362;
	mov.f32 	%f364, 0f35BFBE8E;
	mul.rn.f32 	%f365, %f335, %f364;
	add.f32 	%f366, %f363, %f359;
	sub.f32 	%f367, %f363, %f366;
	add.f32 	%f368, %f359, %f367;
	add.f32 	%f369, %f361, %f368;
	add.f32 	%f370, %f365, %f369;
	add.f32 	%f371, %f366, %f370;
	sub.f32 	%f372, %f366, %f371;
	add.f32 	%f373, %f370, %f372;
	mul.rn.f32 	%f374, %f325, %f371;
	neg.f32 	%f375, %f374;
	fma.rn.f32 	%f376, %f325, %f371, %f375;
	fma.rn.f32 	%f377, %f325, %f373, %f376;
	mov.f32 	%f378, 0f00000000;
	fma.rn.f32 	%f379, %f378, %f371, %f377;
	add.rn.f32 	%f380, %f374, %f379;
	neg.f32 	%f381, %f380;
	add.rn.f32 	%f382, %f374, %f381;
	add.rn.f32 	%f383, %f382, %f379;
	mov.b32 	%r215, %f380;
	setp.eq.s32 	%p44, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f384, %r216;
	add.f32 	%f385, %f383, 0f37000000;
	selp.f32 	%f69, %f385, %f383, %p44;
	selp.f32 	%f386, %f384, %f380, %p44;
	mov.f32 	%f387, 0f3FB8AA3B;
	mul.rn.f32 	%f388, %f386, %f387;
	cvt.rzi.f32.f32 	%f389, %f388;
	abs.f32 	%f390, %f389;
	setp.gt.f32 	%p45, %f390, 0f42FC0000;
	mov.b32 	%r217, %f389;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f391, %r219;
	selp.f32 	%f392, %f391, %f389, %p45;
	mov.f32 	%f393, 0fBF317218;
	fma.rn.f32 	%f394, %f392, %f393, %f386;
	mov.f32 	%f395, 0f3102E308;
	fma.rn.f32 	%f396, %f392, %f395, %f394;
	mul.f32 	%f397, %f396, 0f3FB8AA3B;
	add.f32 	%f398, %f392, 0f4B40007F;
	mov.b32 	%r220, %f398;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f399, %r221;
	ex2.approx.ftz.f32 	%f400, %f397;
	mul.f32 	%f70, %f400, %f399;
	setp.eq.f32 	%p46, %f70, 0f7F800000;
	mov.f32 	%f1103, 0f7F800000;
	@%p46 bra 	$L__BB0_39;

	fma.rn.f32 	%f1103, %f70, %f69, %f70;

$L__BB0_39:
	mov.f32 	%f1053, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1052, %f1053;
	add.f32 	%f1051, %f1052, %f1052;
	mov.f32 	%f1050, 0f3EE8BA2E;
	sub.f32 	%f1049, %f1050, %f1051;
	abs.f32 	%f1048, %f1049;
	setp.lt.f32 	%p47, %f1102, 0f00000000;
	setp.eq.f32 	%p48, %f1048, 0f3F800000;
	and.pred  	%p1, %p47, %p48;
	setp.eq.f32 	%p49, %f1102, 0f00000000;
	@%p49 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f405, %f1102, %f1102;
	selp.f32 	%f1105, %f405, 0f00000000, %p48;
	bra.uni 	$L__BB0_44;

$L__BB0_147:
	mov.f32 	%f1005, 0f00000000;
	mov.u32 	%r368, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1005;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1005;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1005;}

	// end inline asm
	mov.u16 	%rs115, 0;
	st.global.v4.u16 	[%rd25], {%rs112, %rs113, %rs114, %rs115};

$L__BB0_148:
	ld.const.u64 	%rd98, [params+256];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r342, [params+248];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	mul.wide.u32 	%rd100, %r343, 8;
	add.s64 	%rd26, %rd99, %rd100;
	setp.eq.s32 	%p167, %r368, 0;
	@%p167 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs122, %rs123, %rs124, %rs125}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1006, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1007, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1008, %rs124;}

	// end inline asm
	add.f32 	%f1009, %f1006, 0f00000000;
	add.f32 	%f1010, %f1007, 0f00000000;
	add.f32 	%f1011, %f1008, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1011;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1010;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1009;}

	// end inline asm
	mov.u16 	%rs126, 0;
	st.global.v4.u16 	[%rd26], {%rs119, %rs120, %rs121, %rs126};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1014, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1014;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1014;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1014;}

	// end inline asm
	mov.u16 	%rs130, 0;
	st.global.v4.u16 	[%rd26], {%rs127, %rs128, %rs129, %rs130};

$L__BB0_151:
	ld.const.u64 	%rd101, [params+272];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r344, [params+264];
	mad.lo.s32 	%r345, %r344, %r4, %r3;
	mul.wide.u32 	%rd103, %r345, 8;
	add.s64 	%rd27, %rd102, %rd103;
	@%p167 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs137, %rs138, %rs139, %rs140}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1015, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1016, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1017, %rs139;}

	// end inline asm
	add.f32 	%f1018, %f1015, 0f00000000;
	add.f32 	%f1019, %f1016, 0f00000000;
	add.f32 	%f1020, %f1017, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1020;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1018;}

	// end inline asm
	mov.u16 	%rs141, 0;
	st.global.v4.u16 	[%rd27], {%rs134, %rs135, %rs136, %rs141};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1023, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1023;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1023;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1023;}

	// end inline asm
	mov.u16 	%rs145, 0;
	st.global.v4.u16 	[%rd27], {%rs142, %rs143, %rs144, %rs145};

$L__BB0_154:
	ld.const.u64 	%rd104, [params+288];
	cvta.to.global.u64 	%rd105, %rd104;
	ld.const.u32 	%r346, [params+280];
	mad.lo.s32 	%r347, %r346, %r4, %r3;
	mul.wide.u32 	%rd106, %r347, 8;
	add.s64 	%rd28, %rd105, %rd106;
	@%p167 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs152, %rs153, %rs154, %rs155}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1024, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1025, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1026, %rs154;}

	// end inline asm
	add.f32 	%f1027, %f1024, 0f00000000;
	add.f32 	%f1028, %f1025, 0f00000000;
	add.f32 	%f1029, %f1026, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1029;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1028;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1027;}

	// end inline asm
	mov.u16 	%rs156, 0;
	st.global.v4.u16 	[%rd28], {%rs149, %rs150, %rs151, %rs156};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1032, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1032;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1032;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1032;}

	// end inline asm
	mov.u16 	%rs160, 0;
	st.global.v4.u16 	[%rd28], {%rs157, %rs158, %rs159, %rs160};

$L__BB0_157:
	ld.const.u64 	%rd107, [params+304];
	cvta.to.global.u64 	%rd108, %rd107;
	ld.const.u32 	%r348, [params+296];
	mad.lo.s32 	%r349, %r348, %r4, %r3;
	mul.wide.u32 	%rd109, %r349, 8;
	add.s64 	%rd29, %rd108, %rd109;
	@%p167 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs167, %rs168, %rs169, %rs170}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1033, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1034, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1035, %rs169;}

	// end inline asm
	add.f32 	%f1036, %f1033, 0f00000000;
	add.f32 	%f1037, %f1034, 0f00000000;
	add.f32 	%f1038, %f1035, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1038;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1037;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1036;}

	// end inline asm
	mov.u16 	%rs171, 0;
	st.global.v4.u16 	[%rd29], {%rs164, %rs165, %rs166, %rs171};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1041, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1041;}

	// end inline asm
	mov.u16 	%rs175, 0;
	st.global.v4.u16 	[%rd29], {%rs172, %rs173, %rs174, %rs175};
	bra.uni 	$L__BB0_160;

$L__BB0_40:
	mov.b32 	%r222, %f1103;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f401, %r223;
	selp.f32 	%f1105, %f401, %f1103, %p1;
	setp.geu.f32 	%p50, %f1102, 0f00000000;
	@%p50 bra 	$L__BB0_44;

	mov.f32 	%f402, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f403, %f402;
	setp.eq.f32 	%p51, %f403, 0f3EE8BA2E;
	@%p51 bra 	$L__BB0_44;

	mov.f32 	%f1105, 0f7FFFFFFF;

$L__BB0_44:
	abs.f32 	%f1054, %f1102;
	add.f32 	%f406, %f1054, 0f3EE8BA2E;
	mov.b32 	%r224, %f406;
	setp.lt.s32 	%p53, %r224, 2139095040;
	@%p53 bra 	$L__BB0_49;

	abs.f32 	%f1055, %f1102;
	setp.gtu.f32 	%p54, %f1055, 0f7F800000;
	@%p54 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1105, %f1102, 0f3EE8BA2E;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	abs.f32 	%f1056, %f1102;
	setp.neu.f32 	%p55, %f1056, 0f7F800000;
	@%p55 bra 	$L__BB0_49;

	selp.f32 	%f1105, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	ld.const.u64 	%rd115, [params+192];
	cvta.to.global.u64 	%rd114, %rd115;
	ld.const.u32 	%r354, [params+184];
	mad.lo.s32 	%r353, %r354, %r4, %r3;
	cvt.u64.u32 	%rd113, %r353;
	mul.f32 	%f407, %f1105, 0f437F0000;
	setp.eq.f32 	%p56, %f1102, 0f3F800000;
	selp.f32 	%f408, 0f437F0000, %f407, %p56;
	cvt.rzi.u32.f32 	%r225, %f408;
	shl.b64 	%rd67, %rd113, 1;
	add.s64 	%rd68, %rd114, %rd67;
	cvt.u16.u32 	%rs17, %r225;
	mov.u16 	%rs18, 255;
	st.global.v2.u8 	[%rd68], {%rs17, %rs18};

$L__BB0_50:
	ld.const.u32 	%r355, [params+104];
	and.b32  	%r226, %r355, 1;
	setp.eq.b32 	%p57, %r226, 1;
	mov.pred 	%p58, 0;
	xor.pred  	%p59, %p57, %p58;
	not.pred 	%p60, %p59;
	@%p60 bra 	$L__BB0_124;

	mov.f32 	%f413, 0f3EE66666;
	abs.f32 	%f80, %f61;
	setp.lt.f32 	%p61, %f80, 0f00800000;
	mul.f32 	%f415, %f80, 0f4B800000;
	selp.f32 	%f416, %f415, %f80, %p61;
	selp.f32 	%f417, 0fC3170000, 0fC2FE0000, %p61;
	mov.b32 	%r227, %f416;
	and.b32  	%r228, %r227, 8388607;
	or.b32  	%r229, %r228, 1065353216;
	mov.b32 	%f418, %r229;
	shr.u32 	%r230, %r227, 23;
	cvt.rn.f32.u32 	%f419, %r230;
	add.f32 	%f420, %f417, %f419;
	setp.gt.f32 	%p62, %f418, 0f3FB504F3;
	mul.f32 	%f421, %f418, 0f3F000000;
	add.f32 	%f422, %f420, 0f3F800000;
	selp.f32 	%f423, %f422, %f420, %p62;
	selp.f32 	%f424, %f421, %f418, %p62;
	add.f32 	%f425, %f424, 0fBF800000;
	add.f32 	%f426, %f424, 0f3F800000;
	rcp.approx.ftz.f32 	%f427, %f426;
	add.f32 	%f428, %f425, %f425;
	mul.f32 	%f429, %f428, %f427;
	mul.f32 	%f430, %f429, %f429;
	mov.f32 	%f431, 0f3C4CAF63;
	mov.f32 	%f432, 0f3B18F0FE;
	fma.rn.f32 	%f433, %f432, %f430, %f431;
	mov.f32 	%f434, 0f3DAAAABD;
	fma.rn.f32 	%f435, %f433, %f430, %f434;
	mul.rn.f32 	%f436, %f435, %f430;
	mul.rn.f32 	%f437, %f436, %f429;
	sub.f32 	%f438, %f425, %f429;
	add.f32 	%f439, %f438, %f438;
	neg.f32 	%f440, %f429;
	fma.rn.f32 	%f441, %f440, %f425, %f439;
	mul.rn.f32 	%f442, %f427, %f441;
	add.f32 	%f443, %f437, %f429;
	sub.f32 	%f444, %f429, %f443;
	add.f32 	%f445, %f437, %f444;
	add.f32 	%f446, %f442, %f445;
	add.f32 	%f447, %f443, %f446;
	sub.f32 	%f448, %f443, %f447;
	add.f32 	%f449, %f446, %f448;
	mov.f32 	%f450, 0f3F317200;
	mul.rn.f32 	%f451, %f423, %f450;
	mov.f32 	%f452, 0f35BFBE8E;
	mul.rn.f32 	%f453, %f423, %f452;
	add.f32 	%f454, %f451, %f447;
	sub.f32 	%f455, %f451, %f454;
	add.f32 	%f456, %f447, %f455;
	add.f32 	%f457, %f449, %f456;
	add.f32 	%f458, %f453, %f457;
	add.f32 	%f459, %f454, %f458;
	sub.f32 	%f460, %f454, %f459;
	add.f32 	%f461, %f458, %f460;
	mul.rn.f32 	%f462, %f413, %f459;
	neg.f32 	%f463, %f462;
	fma.rn.f32 	%f464, %f413, %f459, %f463;
	fma.rn.f32 	%f465, %f413, %f461, %f464;
	mov.f32 	%f466, 0f00000000;
	fma.rn.f32 	%f467, %f466, %f459, %f465;
	add.rn.f32 	%f468, %f462, %f467;
	neg.f32 	%f469, %f468;
	add.rn.f32 	%f470, %f462, %f469;
	add.rn.f32 	%f471, %f470, %f467;
	mov.b32 	%r231, %f468;
	setp.eq.s32 	%p63, %r231, 1118925336;
	add.s32 	%r232, %r231, -1;
	mov.b32 	%f472, %r232;
	add.f32 	%f473, %f471, 0f37000000;
	selp.f32 	%f81, %f473, %f471, %p63;
	selp.f32 	%f474, %f472, %f468, %p63;
	mov.f32 	%f475, 0f3FB8AA3B;
	mul.rn.f32 	%f476, %f474, %f475;
	cvt.rzi.f32.f32 	%f477, %f476;
	abs.f32 	%f478, %f477;
	setp.gt.f32 	%p64, %f478, 0f42FC0000;
	mov.b32 	%r233, %f477;
	and.b32  	%r234, %r233, -2147483648;
	or.b32  	%r235, %r234, 1123811328;
	mov.b32 	%f479, %r235;
	selp.f32 	%f480, %f479, %f477, %p64;
	mov.f32 	%f481, 0fBF317218;
	fma.rn.f32 	%f482, %f480, %f481, %f474;
	mov.f32 	%f483, 0f3102E308;
	fma.rn.f32 	%f484, %f480, %f483, %f482;
	mul.f32 	%f485, %f484, 0f3FB8AA3B;
	add.f32 	%f486, %f480, 0f4B40007F;
	mov.b32 	%r236, %f486;
	shl.b32 	%r237, %r236, 23;
	mov.b32 	%f487, %r237;
	ex2.approx.ftz.f32 	%f488, %f485;
	mul.f32 	%f82, %f488, %f487;
	setp.eq.f32 	%p65, %f82, 0f7F800000;
	mov.f32 	%f1106, 0f7F800000;
	@%p65 bra 	$L__BB0_53;

	fma.rn.f32 	%f1106, %f82, %f81, %f82;

$L__BB0_53:
	mov.f32 	%f1062, 0f3E666666;
	cvt.rzi.f32.f32 	%f1061, %f1062;
	add.f32 	%f1060, %f1061, %f1061;
	mov.f32 	%f1059, 0f3EE66666;
	sub.f32 	%f1058, %f1059, %f1060;
	abs.f32 	%f1057, %f1058;
	setp.lt.f32 	%p66, %f61, 0f00000000;
	setp.eq.f32 	%p67, %f1057, 0f3F800000;
	and.pred  	%p2, %p66, %p67;
	setp.eq.f32 	%p68, %f61, 0f00000000;
	@%p68 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f493, %f61, %f61;
	selp.f32 	%f1108, %f493, 0f00000000, %p67;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r238, %f1106;
	xor.b32  	%r239, %r238, -2147483648;
	mov.b32 	%f489, %r239;
	selp.f32 	%f1108, %f489, %f1106, %p2;
	setp.geu.f32 	%p69, %f61, 0f00000000;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f490, 0f3EE66666;
	cvt.rzi.f32.f32 	%f491, %f490;
	setp.eq.f32 	%p70, %f491, 0f3EE66666;
	@%p70 bra 	$L__BB0_58;

	mov.f32 	%f1108, 0f7FFFFFFF;

$L__BB0_58:
	abs.f32 	%f1063, %f61;
	add.f32 	%f494, %f1063, 0f3EE66666;
	mov.b32 	%r240, %f494;
	setp.lt.s32 	%p72, %r240, 2139095040;
	@%p72 bra 	$L__BB0_63;

	abs.f32 	%f1064, %f61;
	setp.gtu.f32 	%p73, %f1064, 0f7F800000;
	@%p73 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1108, %f61, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	abs.f32 	%f1065, %f61;
	setp.neu.f32 	%p74, %f1065, 0f7F800000;
	@%p74 bra 	$L__BB0_63;

	selp.f32 	%f1108, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p75, %f61, 0f3F800000;
	selp.f32 	%f91, 0f3F800000, %f1108, %p75;
	abs.f32 	%f92, %f62;
	setp.lt.f32 	%p76, %f92, 0f00800000;
	mul.f32 	%f496, %f92, 0f4B800000;
	selp.f32 	%f497, %f496, %f92, %p76;
	selp.f32 	%f498, 0fC3170000, 0fC2FE0000, %p76;
	mov.b32 	%r241, %f497;
	and.b32  	%r242, %r241, 8388607;
	or.b32  	%r243, %r242, 1065353216;
	mov.b32 	%f499, %r243;
	shr.u32 	%r244, %r241, 23;
	cvt.rn.f32.u32 	%f500, %r244;
	add.f32 	%f501, %f498, %f500;
	setp.gt.f32 	%p77, %f499, 0f3FB504F3;
	mul.f32 	%f502, %f499, 0f3F000000;
	add.f32 	%f503, %f501, 0f3F800000;
	selp.f32 	%f504, %f503, %f501, %p77;
	selp.f32 	%f505, %f502, %f499, %p77;
	add.f32 	%f506, %f505, 0fBF800000;
	add.f32 	%f507, %f505, 0f3F800000;
	rcp.approx.ftz.f32 	%f508, %f507;
	add.f32 	%f509, %f506, %f506;
	mul.f32 	%f510, %f509, %f508;
	mul.f32 	%f511, %f510, %f510;
	mov.f32 	%f512, 0f3C4CAF63;
	mov.f32 	%f513, 0f3B18F0FE;
	fma.rn.f32 	%f514, %f513, %f511, %f512;
	mov.f32 	%f515, 0f3DAAAABD;
	fma.rn.f32 	%f516, %f514, %f511, %f515;
	mul.rn.f32 	%f517, %f516, %f511;
	mul.rn.f32 	%f518, %f517, %f510;
	sub.f32 	%f519, %f506, %f510;
	add.f32 	%f520, %f519, %f519;
	neg.f32 	%f521, %f510;
	fma.rn.f32 	%f522, %f521, %f506, %f520;
	mul.rn.f32 	%f523, %f508, %f522;
	add.f32 	%f524, %f518, %f510;
	sub.f32 	%f525, %f510, %f524;
	add.f32 	%f526, %f518, %f525;
	add.f32 	%f527, %f523, %f526;
	add.f32 	%f528, %f524, %f527;
	sub.f32 	%f529, %f524, %f528;
	add.f32 	%f530, %f527, %f529;
	mov.f32 	%f531, 0f3F317200;
	mul.rn.f32 	%f532, %f504, %f531;
	mov.f32 	%f533, 0f35BFBE8E;
	mul.rn.f32 	%f534, %f504, %f533;
	add.f32 	%f535, %f532, %f528;
	sub.f32 	%f536, %f532, %f535;
	add.f32 	%f537, %f528, %f536;
	add.f32 	%f538, %f530, %f537;
	add.f32 	%f539, %f534, %f538;
	add.f32 	%f540, %f535, %f539;
	sub.f32 	%f541, %f535, %f540;
	add.f32 	%f542, %f539, %f541;
	mov.f32 	%f543, 0f3EE66666;
	mul.rn.f32 	%f544, %f543, %f540;
	neg.f32 	%f545, %f544;
	fma.rn.f32 	%f546, %f543, %f540, %f545;
	fma.rn.f32 	%f547, %f543, %f542, %f546;
	mov.f32 	%f548, 0f00000000;
	fma.rn.f32 	%f549, %f548, %f540, %f547;
	add.rn.f32 	%f550, %f544, %f549;
	neg.f32 	%f551, %f550;
	add.rn.f32 	%f552, %f544, %f551;
	add.rn.f32 	%f553, %f552, %f549;
	mov.b32 	%r245, %f550;
	setp.eq.s32 	%p78, %r245, 1118925336;
	add.s32 	%r246, %r245, -1;
	mov.b32 	%f554, %r246;
	add.f32 	%f555, %f553, 0f37000000;
	selp.f32 	%f93, %f555, %f553, %p78;
	selp.f32 	%f556, %f554, %f550, %p78;
	mov.f32 	%f557, 0f3FB8AA3B;
	mul.rn.f32 	%f558, %f556, %f557;
	cvt.rzi.f32.f32 	%f559, %f558;
	abs.f32 	%f560, %f559;
	setp.gt.f32 	%p79, %f560, 0f42FC0000;
	mov.b32 	%r247, %f559;
	and.b32  	%r248, %r247, -2147483648;
	or.b32  	%r249, %r248, 1123811328;
	mov.b32 	%f561, %r249;
	selp.f32 	%f562, %f561, %f559, %p79;
	mov.f32 	%f563, 0fBF317218;
	fma.rn.f32 	%f564, %f562, %f563, %f556;
	mov.f32 	%f565, 0f3102E308;
	fma.rn.f32 	%f566, %f562, %f565, %f564;
	mul.f32 	%f567, %f566, 0f3FB8AA3B;
	add.f32 	%f568, %f562, 0f4B40007F;
	mov.b32 	%r250, %f568;
	shl.b32 	%r251, %r250, 23;
	mov.b32 	%f569, %r251;
	ex2.approx.ftz.f32 	%f570, %f567;
	mul.f32 	%f94, %f570, %f569;
	setp.eq.f32 	%p80, %f94, 0f7F800000;
	mov.f32 	%f1109, 0f7F800000;
	@%p80 bra 	$L__BB0_65;

	fma.rn.f32 	%f1109, %f94, %f93, %f94;

$L__BB0_65:
	setp.lt.f32 	%p81, %f62, 0f00000000;
	and.pred  	%p3, %p81, %p67;
	setp.eq.f32 	%p83, %f62, 0f00000000;
	@%p83 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f575, %f62, %f62;
	selp.f32 	%f1111, %f575, 0f00000000, %p67;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r252, %f1109;
	xor.b32  	%r253, %r252, -2147483648;
	mov.b32 	%f571, %r253;
	selp.f32 	%f1111, %f571, %f1109, %p3;
	setp.geu.f32 	%p84, %f62, 0f00000000;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f572, 0f3EE66666;
	cvt.rzi.f32.f32 	%f573, %f572;
	setp.eq.f32 	%p85, %f573, 0f3EE66666;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f1111, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1066, %f62;
	add.f32 	%f576, %f1066, 0f3EE66666;
	mov.b32 	%r254, %f576;
	setp.lt.s32 	%p87, %r254, 2139095040;
	@%p87 bra 	$L__BB0_75;

	abs.f32 	%f1067, %f62;
	setp.gtu.f32 	%p88, %f1067, 0f7F800000;
	@%p88 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1111, %f62, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1068, %f62;
	setp.neu.f32 	%p89, %f1068, 0f7F800000;
	@%p89 bra 	$L__BB0_75;

	selp.f32 	%f1111, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p90, %f62, 0f3F800000;
	selp.f32 	%f103, 0f3F800000, %f1111, %p90;
	abs.f32 	%f104, %f63;
	setp.lt.f32 	%p91, %f104, 0f00800000;
	mul.f32 	%f578, %f104, 0f4B800000;
	selp.f32 	%f579, %f578, %f104, %p91;
	selp.f32 	%f580, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r255, %f579;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f581, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f582, %r258;
	add.f32 	%f583, %f580, %f582;
	setp.gt.f32 	%p92, %f581, 0f3FB504F3;
	mul.f32 	%f584, %f581, 0f3F000000;
	add.f32 	%f585, %f583, 0f3F800000;
	selp.f32 	%f586, %f585, %f583, %p92;
	selp.f32 	%f587, %f584, %f581, %p92;
	add.f32 	%f588, %f587, 0fBF800000;
	add.f32 	%f589, %f587, 0f3F800000;
	rcp.approx.ftz.f32 	%f590, %f589;
	add.f32 	%f591, %f588, %f588;
	mul.f32 	%f592, %f591, %f590;
	mul.f32 	%f593, %f592, %f592;
	mov.f32 	%f594, 0f3C4CAF63;
	mov.f32 	%f595, 0f3B18F0FE;
	fma.rn.f32 	%f596, %f595, %f593, %f594;
	mov.f32 	%f597, 0f3DAAAABD;
	fma.rn.f32 	%f598, %f596, %f593, %f597;
	mul.rn.f32 	%f599, %f598, %f593;
	mul.rn.f32 	%f600, %f599, %f592;
	sub.f32 	%f601, %f588, %f592;
	add.f32 	%f602, %f601, %f601;
	neg.f32 	%f603, %f592;
	fma.rn.f32 	%f604, %f603, %f588, %f602;
	mul.rn.f32 	%f605, %f590, %f604;
	add.f32 	%f606, %f600, %f592;
	sub.f32 	%f607, %f592, %f606;
	add.f32 	%f608, %f600, %f607;
	add.f32 	%f609, %f605, %f608;
	add.f32 	%f610, %f606, %f609;
	sub.f32 	%f611, %f606, %f610;
	add.f32 	%f612, %f609, %f611;
	mov.f32 	%f613, 0f3F317200;
	mul.rn.f32 	%f614, %f586, %f613;
	mov.f32 	%f615, 0f35BFBE8E;
	mul.rn.f32 	%f616, %f586, %f615;
	add.f32 	%f617, %f614, %f610;
	sub.f32 	%f618, %f614, %f617;
	add.f32 	%f619, %f610, %f618;
	add.f32 	%f620, %f612, %f619;
	add.f32 	%f621, %f616, %f620;
	add.f32 	%f622, %f617, %f621;
	sub.f32 	%f623, %f617, %f622;
	add.f32 	%f624, %f621, %f623;
	mov.f32 	%f625, 0f3EE66666;
	mul.rn.f32 	%f626, %f625, %f622;
	neg.f32 	%f627, %f626;
	fma.rn.f32 	%f628, %f625, %f622, %f627;
	fma.rn.f32 	%f629, %f625, %f624, %f628;
	mov.f32 	%f630, 0f00000000;
	fma.rn.f32 	%f631, %f630, %f622, %f629;
	add.rn.f32 	%f632, %f626, %f631;
	neg.f32 	%f633, %f632;
	add.rn.f32 	%f634, %f626, %f633;
	add.rn.f32 	%f635, %f634, %f631;
	mov.b32 	%r259, %f632;
	setp.eq.s32 	%p93, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f636, %r260;
	add.f32 	%f637, %f635, 0f37000000;
	selp.f32 	%f105, %f637, %f635, %p93;
	selp.f32 	%f638, %f636, %f632, %p93;
	mov.f32 	%f639, 0f3FB8AA3B;
	mul.rn.f32 	%f640, %f638, %f639;
	cvt.rzi.f32.f32 	%f641, %f640;
	abs.f32 	%f642, %f641;
	setp.gt.f32 	%p94, %f642, 0f42FC0000;
	mov.b32 	%r261, %f641;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f643, %r263;
	selp.f32 	%f644, %f643, %f641, %p94;
	mov.f32 	%f645, 0fBF317218;
	fma.rn.f32 	%f646, %f644, %f645, %f638;
	mov.f32 	%f647, 0f3102E308;
	fma.rn.f32 	%f648, %f644, %f647, %f646;
	mul.f32 	%f649, %f648, 0f3FB8AA3B;
	add.f32 	%f650, %f644, 0f4B40007F;
	mov.b32 	%r264, %f650;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f651, %r265;
	ex2.approx.ftz.f32 	%f652, %f649;
	mul.f32 	%f106, %f652, %f651;
	setp.eq.f32 	%p95, %f106, 0f7F800000;
	mov.f32 	%f1112, 0f7F800000;
	@%p95 bra 	$L__BB0_77;

	fma.rn.f32 	%f1112, %f106, %f105, %f106;

$L__BB0_77:
	setp.lt.f32 	%p96, %f63, 0f00000000;
	and.pred  	%p4, %p96, %p67;
	setp.eq.f32 	%p98, %f63, 0f00000000;
	@%p98 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f657, %f63, %f63;
	selp.f32 	%f1114, %f657, 0f00000000, %p67;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r266, %f1112;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f653, %r267;
	selp.f32 	%f1114, %f653, %f1112, %p4;
	setp.geu.f32 	%p99, %f63, 0f00000000;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f654, 0f3EE66666;
	cvt.rzi.f32.f32 	%f655, %f654;
	setp.eq.f32 	%p100, %f655, 0f3EE66666;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f1114, 0f7FFFFFFF;

$L__BB0_82:
	abs.f32 	%f1069, %f63;
	add.f32 	%f658, %f1069, 0f3EE66666;
	mov.b32 	%r268, %f658;
	setp.lt.s32 	%p102, %r268, 2139095040;
	@%p102 bra 	$L__BB0_87;

	abs.f32 	%f1070, %f63;
	setp.gtu.f32 	%p103, %f1070, 0f7F800000;
	@%p103 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1114, %f63, 0f3EE66666;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	abs.f32 	%f1071, %f63;
	setp.neu.f32 	%p104, %f1071, 0f7F800000;
	@%p104 bra 	$L__BB0_87;

	selp.f32 	%f1114, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	setp.eq.f32 	%p105, %f63, 0f3F800000;
	mov.f32 	%f660, 0f3F800000;
	selp.f32 	%f661, 0f3F800000, %f1114, %p105;
	min.f32 	%f662, %f91, %f660;
	mov.f32 	%f663, 0f00000000;
	max.f32 	%f115, %f663, %f662;
	min.f32 	%f664, %f103, %f660;
	max.f32 	%f116, %f663, %f664;
	min.f32 	%f665, %f661, %f660;
	max.f32 	%f117, %f663, %f665;
	mov.f32 	%f669, 0f3ED55555;
	abs.f32 	%f119, %f115;
	setp.lt.f32 	%p106, %f119, 0f00800000;
	mul.f32 	%f671, %f119, 0f4B800000;
	selp.f32 	%f672, %f671, %f119, %p106;
	selp.f32 	%f673, 0fC3170000, 0fC2FE0000, %p106;
	mov.b32 	%r271, %f672;
	and.b32  	%r272, %r271, 8388607;
	or.b32  	%r273, %r272, 1065353216;
	mov.b32 	%f674, %r273;
	shr.u32 	%r274, %r271, 23;
	cvt.rn.f32.u32 	%f675, %r274;
	add.f32 	%f676, %f673, %f675;
	setp.gt.f32 	%p107, %f674, 0f3FB504F3;
	mul.f32 	%f677, %f674, 0f3F000000;
	add.f32 	%f678, %f676, 0f3F800000;
	selp.f32 	%f679, %f678, %f676, %p107;
	selp.f32 	%f680, %f677, %f674, %p107;
	add.f32 	%f681, %f680, 0fBF800000;
	add.f32 	%f682, %f680, 0f3F800000;
	rcp.approx.ftz.f32 	%f683, %f682;
	add.f32 	%f684, %f681, %f681;
	mul.f32 	%f685, %f684, %f683;
	mul.f32 	%f686, %f685, %f685;
	mov.f32 	%f687, 0f3C4CAF63;
	mov.f32 	%f688, 0f3B18F0FE;
	fma.rn.f32 	%f689, %f688, %f686, %f687;
	mov.f32 	%f690, 0f3DAAAABD;
	fma.rn.f32 	%f691, %f689, %f686, %f690;
	mul.rn.f32 	%f692, %f691, %f686;
	mul.rn.f32 	%f693, %f692, %f685;
	sub.f32 	%f694, %f681, %f685;
	add.f32 	%f695, %f694, %f694;
	neg.f32 	%f696, %f685;
	fma.rn.f32 	%f697, %f696, %f681, %f695;
	mul.rn.f32 	%f698, %f683, %f697;
	add.f32 	%f699, %f693, %f685;
	sub.f32 	%f700, %f685, %f699;
	add.f32 	%f701, %f693, %f700;
	add.f32 	%f702, %f698, %f701;
	add.f32 	%f703, %f699, %f702;
	sub.f32 	%f704, %f699, %f703;
	add.f32 	%f705, %f702, %f704;
	mov.f32 	%f706, 0f3F317200;
	mul.rn.f32 	%f707, %f679, %f706;
	mov.f32 	%f708, 0f35BFBE8E;
	mul.rn.f32 	%f709, %f679, %f708;
	add.f32 	%f710, %f707, %f703;
	sub.f32 	%f711, %f707, %f710;
	add.f32 	%f712, %f703, %f711;
	add.f32 	%f713, %f705, %f712;
	add.f32 	%f714, %f709, %f713;
	add.f32 	%f715, %f710, %f714;
	sub.f32 	%f716, %f710, %f715;
	add.f32 	%f717, %f714, %f716;
	mul.rn.f32 	%f718, %f669, %f715;
	neg.f32 	%f719, %f718;
	fma.rn.f32 	%f720, %f669, %f715, %f719;
	fma.rn.f32 	%f721, %f669, %f717, %f720;
	fma.rn.f32 	%f722, %f663, %f715, %f721;
	add.rn.f32 	%f723, %f718, %f722;
	neg.f32 	%f724, %f723;
	add.rn.f32 	%f725, %f718, %f724;
	add.rn.f32 	%f726, %f725, %f722;
	mov.b32 	%r275, %f723;
	setp.eq.s32 	%p108, %r275, 1118925336;
	add.s32 	%r276, %r275, -1;
	mov.b32 	%f727, %r276;
	add.f32 	%f728, %f726, 0f37000000;
	selp.f32 	%f120, %f728, %f726, %p108;
	selp.f32 	%f729, %f727, %f723, %p108;
	mov.f32 	%f730, 0f3FB8AA3B;
	mul.rn.f32 	%f731, %f729, %f730;
	cvt.rzi.f32.f32 	%f732, %f731;
	abs.f32 	%f733, %f732;
	setp.gt.f32 	%p109, %f733, 0f42FC0000;
	mov.b32 	%r277, %f732;
	and.b32  	%r278, %r277, -2147483648;
	or.b32  	%r279, %r278, 1123811328;
	mov.b32 	%f734, %r279;
	selp.f32 	%f735, %f734, %f732, %p109;
	mov.f32 	%f736, 0fBF317218;
	fma.rn.f32 	%f737, %f735, %f736, %f729;
	mov.f32 	%f738, 0f3102E308;
	fma.rn.f32 	%f739, %f735, %f738, %f737;
	mul.f32 	%f740, %f739, 0f3FB8AA3B;
	add.f32 	%f741, %f735, 0f4B40007F;
	mov.b32 	%r280, %f741;
	shl.b32 	%r281, %r280, 23;
	mov.b32 	%f742, %r281;
	ex2.approx.ftz.f32 	%f743, %f740;
	mul.f32 	%f121, %f743, %f742;
	setp.eq.f32 	%p110, %f121, 0f7F800000;
	mov.f32 	%f1115, 0f7F800000;
	@%p110 bra 	$L__BB0_89;

	fma.rn.f32 	%f1115, %f121, %f120, %f121;

$L__BB0_89:
	mov.f32 	%f1047, 0f3E555555;
	cvt.rzi.f32.f32 	%f1046, %f1047;
	add.f32 	%f1045, %f1046, %f1046;
	mov.f32 	%f1044, 0f3ED55555;
	sub.f32 	%f1043, %f1044, %f1045;
	abs.f32 	%f1042, %f1043;
	setp.lt.f32 	%p111, %f115, 0f00000000;
	setp.eq.f32 	%p112, %f1042, 0f3F800000;
	and.pred  	%p5, %p111, %p112;
	setp.eq.f32 	%p113, %f115, 0f00000000;
	@%p113 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	add.f32 	%f748, %f115, %f115;
	selp.f32 	%f1117, %f748, 0f00000000, %p112;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.b32 	%r282, %f1115;
	xor.b32  	%r283, %r282, -2147483648;
	mov.b32 	%f744, %r283;
	selp.f32 	%f1117, %f744, %f1115, %p5;
	setp.geu.f32 	%p114, %f115, 0f00000000;
	@%p114 bra 	$L__BB0_94;

	mov.f32 	%f745, 0f3ED55555;
	cvt.rzi.f32.f32 	%f746, %f745;
	setp.eq.f32 	%p115, %f746, 0f3ED55555;
	@%p115 bra 	$L__BB0_94;

	mov.f32 	%f1117, 0f7FFFFFFF;

$L__BB0_94:
	add.f32 	%f749, %f119, 0f3ED55555;
	mov.b32 	%r284, %f749;
	setp.lt.s32 	%p117, %r284, 2139095040;
	@%p117 bra 	$L__BB0_99;

	setp.gtu.f32 	%p118, %f119, 0f7F800000;
	@%p118 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	add.f32 	%f1117, %f115, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	setp.neu.f32 	%p119, %f119, 0f7F800000;
	@%p119 bra 	$L__BB0_99;

	selp.f32 	%f1117, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f130, %f116;
	setp.lt.f32 	%p120, %f130, 0f00800000;
	mul.f32 	%f751, %f130, 0f4B800000;
	selp.f32 	%f752, %f751, %f130, %p120;
	selp.f32 	%f753, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r285, %f752;
	and.b32  	%r286, %r285, 8388607;
	or.b32  	%r287, %r286, 1065353216;
	mov.b32 	%f754, %r287;
	shr.u32 	%r288, %r285, 23;
	cvt.rn.f32.u32 	%f755, %r288;
	add.f32 	%f756, %f753, %f755;
	setp.gt.f32 	%p121, %f754, 0f3FB504F3;
	mul.f32 	%f757, %f754, 0f3F000000;
	add.f32 	%f758, %f756, 0f3F800000;
	selp.f32 	%f759, %f758, %f756, %p121;
	selp.f32 	%f760, %f757, %f754, %p121;
	add.f32 	%f761, %f760, 0fBF800000;
	add.f32 	%f762, %f760, 0f3F800000;
	rcp.approx.ftz.f32 	%f763, %f762;
	add.f32 	%f764, %f761, %f761;
	mul.f32 	%f765, %f764, %f763;
	mul.f32 	%f766, %f765, %f765;
	mov.f32 	%f767, 0f3C4CAF63;
	mov.f32 	%f768, 0f3B18F0FE;
	fma.rn.f32 	%f769, %f768, %f766, %f767;
	mov.f32 	%f770, 0f3DAAAABD;
	fma.rn.f32 	%f771, %f769, %f766, %f770;
	mul.rn.f32 	%f772, %f771, %f766;
	mul.rn.f32 	%f773, %f772, %f765;
	sub.f32 	%f774, %f761, %f765;
	add.f32 	%f775, %f774, %f774;
	neg.f32 	%f776, %f765;
	fma.rn.f32 	%f777, %f776, %f761, %f775;
	mul.rn.f32 	%f778, %f763, %f777;
	add.f32 	%f779, %f773, %f765;
	sub.f32 	%f780, %f765, %f779;
	add.f32 	%f781, %f773, %f780;
	add.f32 	%f782, %f778, %f781;
	add.f32 	%f783, %f779, %f782;
	sub.f32 	%f784, %f779, %f783;
	add.f32 	%f785, %f782, %f784;
	mov.f32 	%f786, 0f3F317200;
	mul.rn.f32 	%f787, %f759, %f786;
	mov.f32 	%f788, 0f35BFBE8E;
	mul.rn.f32 	%f789, %f759, %f788;
	add.f32 	%f790, %f787, %f783;
	sub.f32 	%f791, %f787, %f790;
	add.f32 	%f792, %f783, %f791;
	add.f32 	%f793, %f785, %f792;
	add.f32 	%f794, %f789, %f793;
	add.f32 	%f795, %f790, %f794;
	sub.f32 	%f796, %f790, %f795;
	add.f32 	%f797, %f794, %f796;
	mov.f32 	%f798, 0f3ED55555;
	mul.rn.f32 	%f799, %f798, %f795;
	neg.f32 	%f800, %f799;
	fma.rn.f32 	%f801, %f798, %f795, %f800;
	fma.rn.f32 	%f802, %f798, %f797, %f801;
	mov.f32 	%f803, 0f00000000;
	fma.rn.f32 	%f804, %f803, %f795, %f802;
	add.rn.f32 	%f805, %f799, %f804;
	neg.f32 	%f806, %f805;
	add.rn.f32 	%f807, %f799, %f806;
	add.rn.f32 	%f808, %f807, %f804;
	mov.b32 	%r289, %f805;
	setp.eq.s32 	%p122, %r289, 1118925336;
	add.s32 	%r290, %r289, -1;
	mov.b32 	%f809, %r290;
	add.f32 	%f810, %f808, 0f37000000;
	selp.f32 	%f131, %f810, %f808, %p122;
	selp.f32 	%f811, %f809, %f805, %p122;
	mov.f32 	%f812, 0f3FB8AA3B;
	mul.rn.f32 	%f813, %f811, %f812;
	cvt.rzi.f32.f32 	%f814, %f813;
	abs.f32 	%f815, %f814;
	setp.gt.f32 	%p123, %f815, 0f42FC0000;
	mov.b32 	%r291, %f814;
	and.b32  	%r292, %r291, -2147483648;
	or.b32  	%r293, %r292, 1123811328;
	mov.b32 	%f816, %r293;
	selp.f32 	%f817, %f816, %f814, %p123;
	mov.f32 	%f818, 0fBF317218;
	fma.rn.f32 	%f819, %f817, %f818, %f811;
	mov.f32 	%f820, 0f3102E308;
	fma.rn.f32 	%f821, %f817, %f820, %f819;
	mul.f32 	%f822, %f821, 0f3FB8AA3B;
	add.f32 	%f823, %f817, 0f4B40007F;
	mov.b32 	%r294, %f823;
	shl.b32 	%r295, %r294, 23;
	mov.b32 	%f824, %r295;
	ex2.approx.ftz.f32 	%f825, %f822;
	mul.f32 	%f132, %f825, %f824;
	setp.eq.f32 	%p124, %f132, 0f7F800000;
	mov.f32 	%f1118, 0f7F800000;
	@%p124 bra 	$L__BB0_101;

	fma.rn.f32 	%f1118, %f132, %f131, %f132;

$L__BB0_101:
	setp.lt.f32 	%p125, %f116, 0f00000000;
	and.pred  	%p6, %p125, %p112;
	setp.eq.f32 	%p127, %f116, 0f00000000;
	@%p127 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f830, %f116, %f116;
	selp.f32 	%f1120, %f830, 0f00000000, %p112;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r296, %f1118;
	xor.b32  	%r297, %r296, -2147483648;
	mov.b32 	%f826, %r297;
	selp.f32 	%f1120, %f826, %f1118, %p6;
	setp.geu.f32 	%p128, %f116, 0f00000000;
	@%p128 bra 	$L__BB0_106;

	mov.f32 	%f827, 0f3ED55555;
	cvt.rzi.f32.f32 	%f828, %f827;
	setp.eq.f32 	%p129, %f828, 0f3ED55555;
	@%p129 bra 	$L__BB0_106;

	mov.f32 	%f1120, 0f7FFFFFFF;

$L__BB0_106:
	mov.f32 	%f1074, 0f00000000;
	max.f32 	%f1073, %f1074, %f664;
	abs.f32 	%f1072, %f1073;
	add.f32 	%f831, %f1072, 0f3ED55555;
	mov.b32 	%r298, %f831;
	setp.lt.s32 	%p131, %r298, 2139095040;
	@%p131 bra 	$L__BB0_111;

	mov.f32 	%f1077, 0f00000000;
	max.f32 	%f1076, %f1077, %f664;
	abs.f32 	%f1075, %f1076;
	setp.gtu.f32 	%p132, %f1075, 0f7F800000;
	@%p132 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1120, %f116, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	mov.f32 	%f1080, 0f00000000;
	max.f32 	%f1079, %f1080, %f664;
	abs.f32 	%f1078, %f1079;
	setp.neu.f32 	%p133, %f1078, 0f7F800000;
	@%p133 bra 	$L__BB0_111;

	selp.f32 	%f1120, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	abs.f32 	%f141, %f117;
	setp.lt.f32 	%p134, %f141, 0f00800000;
	mul.f32 	%f833, %f141, 0f4B800000;
	selp.f32 	%f834, %f833, %f141, %p134;
	selp.f32 	%f835, 0fC3170000, 0fC2FE0000, %p134;
	mov.b32 	%r299, %f834;
	and.b32  	%r300, %r299, 8388607;
	or.b32  	%r301, %r300, 1065353216;
	mov.b32 	%f836, %r301;
	shr.u32 	%r302, %r299, 23;
	cvt.rn.f32.u32 	%f837, %r302;
	add.f32 	%f838, %f835, %f837;
	setp.gt.f32 	%p135, %f836, 0f3FB504F3;
	mul.f32 	%f839, %f836, 0f3F000000;
	add.f32 	%f840, %f838, 0f3F800000;
	selp.f32 	%f841, %f840, %f838, %p135;
	selp.f32 	%f842, %f839, %f836, %p135;
	add.f32 	%f843, %f842, 0fBF800000;
	add.f32 	%f844, %f842, 0f3F800000;
	rcp.approx.ftz.f32 	%f845, %f844;
	add.f32 	%f846, %f843, %f843;
	mul.f32 	%f847, %f846, %f845;
	mul.f32 	%f848, %f847, %f847;
	mov.f32 	%f849, 0f3C4CAF63;
	mov.f32 	%f850, 0f3B18F0FE;
	fma.rn.f32 	%f851, %f850, %f848, %f849;
	mov.f32 	%f852, 0f3DAAAABD;
	fma.rn.f32 	%f853, %f851, %f848, %f852;
	mul.rn.f32 	%f854, %f853, %f848;
	mul.rn.f32 	%f855, %f854, %f847;
	sub.f32 	%f856, %f843, %f847;
	add.f32 	%f857, %f856, %f856;
	neg.f32 	%f858, %f847;
	fma.rn.f32 	%f859, %f858, %f843, %f857;
	mul.rn.f32 	%f860, %f845, %f859;
	add.f32 	%f861, %f855, %f847;
	sub.f32 	%f862, %f847, %f861;
	add.f32 	%f863, %f855, %f862;
	add.f32 	%f864, %f860, %f863;
	add.f32 	%f865, %f861, %f864;
	sub.f32 	%f866, %f861, %f865;
	add.f32 	%f867, %f864, %f866;
	mov.f32 	%f868, 0f3F317200;
	mul.rn.f32 	%f869, %f841, %f868;
	mov.f32 	%f870, 0f35BFBE8E;
	mul.rn.f32 	%f871, %f841, %f870;
	add.f32 	%f872, %f869, %f865;
	sub.f32 	%f873, %f869, %f872;
	add.f32 	%f874, %f865, %f873;
	add.f32 	%f875, %f867, %f874;
	add.f32 	%f876, %f871, %f875;
	add.f32 	%f877, %f872, %f876;
	sub.f32 	%f878, %f872, %f877;
	add.f32 	%f879, %f876, %f878;
	mov.f32 	%f880, 0f3ED55555;
	mul.rn.f32 	%f881, %f880, %f877;
	neg.f32 	%f882, %f881;
	fma.rn.f32 	%f883, %f880, %f877, %f882;
	fma.rn.f32 	%f884, %f880, %f879, %f883;
	mov.f32 	%f885, 0f00000000;
	fma.rn.f32 	%f886, %f885, %f877, %f884;
	add.rn.f32 	%f887, %f881, %f886;
	neg.f32 	%f888, %f887;
	add.rn.f32 	%f889, %f881, %f888;
	add.rn.f32 	%f890, %f889, %f886;
	mov.b32 	%r303, %f887;
	setp.eq.s32 	%p136, %r303, 1118925336;
	add.s32 	%r304, %r303, -1;
	mov.b32 	%f891, %r304;
	add.f32 	%f892, %f890, 0f37000000;
	selp.f32 	%f142, %f892, %f890, %p136;
	selp.f32 	%f893, %f891, %f887, %p136;
	mov.f32 	%f894, 0f3FB8AA3B;
	mul.rn.f32 	%f895, %f893, %f894;
	cvt.rzi.f32.f32 	%f896, %f895;
	abs.f32 	%f897, %f896;
	setp.gt.f32 	%p137, %f897, 0f42FC0000;
	mov.b32 	%r305, %f896;
	and.b32  	%r306, %r305, -2147483648;
	or.b32  	%r307, %r306, 1123811328;
	mov.b32 	%f898, %r307;
	selp.f32 	%f899, %f898, %f896, %p137;
	mov.f32 	%f900, 0fBF317218;
	fma.rn.f32 	%f901, %f899, %f900, %f893;
	mov.f32 	%f902, 0f3102E308;
	fma.rn.f32 	%f903, %f899, %f902, %f901;
	mul.f32 	%f904, %f903, 0f3FB8AA3B;
	add.f32 	%f905, %f899, 0f4B40007F;
	mov.b32 	%r308, %f905;
	shl.b32 	%r309, %r308, 23;
	mov.b32 	%f906, %r309;
	ex2.approx.ftz.f32 	%f907, %f904;
	mul.f32 	%f143, %f907, %f906;
	setp.eq.f32 	%p138, %f143, 0f7F800000;
	mov.f32 	%f1121, 0f7F800000;
	@%p138 bra 	$L__BB0_113;

	fma.rn.f32 	%f1121, %f143, %f142, %f143;

$L__BB0_113:
	setp.lt.f32 	%p139, %f117, 0f00000000;
	and.pred  	%p7, %p139, %p112;
	setp.eq.f32 	%p141, %f117, 0f00000000;
	@%p141 bra 	$L__BB0_117;
	bra.uni 	$L__BB0_114;

$L__BB0_117:
	add.f32 	%f912, %f117, %f117;
	selp.f32 	%f1123, %f912, 0f00000000, %p112;
	bra.uni 	$L__BB0_118;

$L__BB0_114:
	mov.b32 	%r310, %f1121;
	xor.b32  	%r311, %r310, -2147483648;
	mov.b32 	%f908, %r311;
	selp.f32 	%f1123, %f908, %f1121, %p7;
	setp.geu.f32 	%p142, %f117, 0f00000000;
	@%p142 bra 	$L__BB0_118;

	mov.f32 	%f909, 0f3ED55555;
	cvt.rzi.f32.f32 	%f910, %f909;
	setp.eq.f32 	%p143, %f910, 0f3ED55555;
	@%p143 bra 	$L__BB0_118;

	mov.f32 	%f1123, 0f7FFFFFFF;

$L__BB0_118:
	mov.f32 	%f1083, 0f00000000;
	max.f32 	%f1082, %f1083, %f665;
	abs.f32 	%f1081, %f1082;
	add.f32 	%f913, %f1081, 0f3ED55555;
	mov.b32 	%r312, %f913;
	setp.lt.s32 	%p145, %r312, 2139095040;
	@%p145 bra 	$L__BB0_123;

	mov.f32 	%f1086, 0f00000000;
	max.f32 	%f1085, %f1086, %f665;
	abs.f32 	%f1084, %f1085;
	setp.gtu.f32 	%p146, %f1084, 0f7F800000;
	@%p146 bra 	$L__BB0_122;
	bra.uni 	$L__BB0_120;

$L__BB0_122:
	add.f32 	%f1123, %f117, 0f3ED55555;
	bra.uni 	$L__BB0_123;

$L__BB0_120:
	mov.f32 	%f1089, 0f00000000;
	max.f32 	%f1088, %f1089, %f665;
	abs.f32 	%f1087, %f1088;
	setp.neu.f32 	%p147, %f1087, 0f7F800000;
	@%p147 bra 	$L__BB0_123;

	selp.f32 	%f1123, 0fFF800000, 0f7F800000, %p7;

$L__BB0_123:
	ld.const.u64 	%rd112, [params+144];
	cvta.to.global.u64 	%rd111, %rd112;
	ld.const.u32 	%r351, [params+136];
	mad.lo.s32 	%r350, %r351, %r4, %r3;
	cvt.u64.u32 	%rd110, %r350;
	fma.rn.f32 	%f914, %f1117, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p148, %f115, 0f3F800000;
	mov.f32 	%f915, 0f3F800000;
	selp.f32 	%f916, 0f3F7FFFFF, %f914, %p148;
	mul.f32 	%f917, %f115, 0f414EB852;
	setp.lt.f32 	%p149, %f115, 0f3B4D2E1C;
	selp.f32 	%f918, %f917, %f916, %p149;
	fma.rn.f32 	%f919, %f1120, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p150, %f116, 0f3F800000;
	selp.f32 	%f920, 0f3F7FFFFF, %f919, %p150;
	mul.f32 	%f921, %f116, 0f414EB852;
	setp.lt.f32 	%p151, %f116, 0f3B4D2E1C;
	selp.f32 	%f922, %f921, %f920, %p151;
	fma.rn.f32 	%f923, %f1123, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p152, %f117, 0f3F800000;
	selp.f32 	%f924, 0f3F7FFFFF, %f923, %p152;
	mul.f32 	%f925, %f117, 0f414EB852;
	setp.lt.f32 	%p153, %f117, 0f3B4D2E1C;
	selp.f32 	%f926, %f925, %f924, %p153;
	min.f32 	%f927, %f918, %f915;
	mov.f32 	%f928, 0f00000000;
	max.f32 	%f929, %f928, %f927;
	mul.f32 	%f930, %f929, 0f43800000;
	cvt.rzi.u32.f32 	%r313, %f930;
	min.u32 	%r314, %r313, 255;
	min.f32 	%f931, %f922, %f915;
	max.f32 	%f932, %f928, %f931;
	mul.f32 	%f933, %f932, 0f43800000;
	cvt.rzi.u32.f32 	%r315, %f933;
	min.u32 	%r316, %r315, 255;
	min.f32 	%f934, %f926, %f915;
	max.f32 	%f935, %f928, %f934;
	mul.f32 	%f936, %f935, 0f43800000;
	cvt.rzi.u32.f32 	%r317, %f936;
	min.u32 	%r318, %r317, 255;
	shl.b64 	%rd70, %rd110, 2;
	add.s64 	%rd71, %rd111, %rd70;
	cvt.u16.u32 	%rs19, %r318;
	cvt.u16.u32 	%rs20, %r316;
	cvt.u16.u32 	%rs21, %r314;
	mov.u16 	%rs22, 255;
	st.global.v4.u8 	[%rd71], {%rs21, %rs20, %rs19, %rs22};

$L__BB0_124:
	ld.const.u32 	%r352, [params+104];
	and.b32  	%r319, %r352, 4;
	setp.eq.s32 	%p154, %r319, 0;
	ld.const.u32 	%r367, [params+108];
	@%p154 bra 	$L__BB0_128;

	setp.eq.s32 	%p155, %r367, 0;
	ld.const.u64 	%rd72, [params+224];
	cvta.to.global.u64 	%rd73, %rd72;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r4, %r3;
	mul.wide.u32 	%rd74, %r321, 8;
	add.s64 	%rd20, %rd73, %rd74;
	@%p155 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs30, %rs31, %rs32, %rs33}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f937, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f938, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f939, %rs32;}

	// end inline asm
	add.f32 	%f940, %f61, %f937;
	add.f32 	%f941, %f62, %f938;
	add.f32 	%f942, %f63, %f939;
	mov.f32 	%f943, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f942;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f941;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f940;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f943;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs26, %rs27, %rs28, %rs29};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f947, 0f3F800000;
	mov.u32 	%r367, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f947;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f63;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f62;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f61;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs34, %rs35, %rs36, %rs37};

$L__BB0_128:
	ld.const.u64 	%rd75, [params+256];
	cvta.to.global.u64 	%rd76, %rd75;
	ld.const.u32 	%r323, [params+248];
	mad.lo.s32 	%r324, %r323, %r4, %r3;
	mul.wide.u32 	%rd77, %r324, 8;
	add.s64 	%rd21, %rd76, %rd77;
	setp.eq.s32 	%p156, %r367, 0;
	@%p156 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs45, %rs46, %rs47, %rs48}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f948, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f949, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f950, %rs47;}

	// end inline asm
	add.f32 	%f951, %f64, %f948;
	add.f32 	%f952, %f65, %f949;
	add.f32 	%f953, %f66, %f950;
	mov.f32 	%f954, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f953;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f952;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f951;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f954;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs41, %rs42, %rs43, %rs44};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f958, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f958;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f66;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f65;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f64;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs49, %rs50, %rs51, %rs52};

$L__BB0_131:
	mul.f32 	%f959, %f173, 0f3F000000;
	mov.f32 	%f960, 0f3F000000;
	sub.f32 	%f152, %f960, %f959;
	mul.f32 	%f961, %f174, 0f3F000000;
	sub.f32 	%f153, %f960, %f961;
	mul.f32 	%f962, %f175, 0f3F000000;
	sub.f32 	%f154, %f960, %f962;
	ld.const.u64 	%rd78, [params+272];
	cvta.to.global.u64 	%rd79, %rd78;
	ld.const.u32 	%r325, [params+264];
	mad.lo.s32 	%r326, %r325, %r4, %r3;
	mul.wide.u32 	%rd80, %r326, 8;
	add.s64 	%rd22, %rd79, %rd80;
	@%p156 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs60, %rs61, %rs62, %rs63}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f963, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f964, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f965, %rs62;}

	// end inline asm
	add.f32 	%f966, %f152, %f963;
	add.f32 	%f967, %f152, %f964;
	add.f32 	%f968, %f152, %f965;
	mov.f32 	%f969, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f968;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f967;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f966;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f969;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs56, %rs57, %rs58, %rs59};
	bra.uni 	$L__BB0_134;

$L__BB0_133:
	mov.f32 	%f973, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f973;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f152;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f152;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f152;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs64, %rs65, %rs66, %rs67};

$L__BB0_134:
	ld.const.u64 	%rd81, [params+288];
	cvta.to.global.u64 	%rd82, %rd81;
	ld.const.u32 	%r327, [params+280];
	mad.lo.s32 	%r328, %r327, %r4, %r3;
	mul.wide.u32 	%rd83, %r328, 8;
	add.s64 	%rd23, %rd82, %rd83;
	@%p156 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs75, %rs76, %rs77, %rs78}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f974, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f975, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f976, %rs77;}

	// end inline asm
	add.f32 	%f977, %f153, %f974;
	add.f32 	%f978, %f153, %f975;
	add.f32 	%f979, %f153, %f976;
	mov.f32 	%f980, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f979;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f978;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f977;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f980;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs71, %rs72, %rs73, %rs74};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f984, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f984;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f153;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f153;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f153;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs79, %rs80, %rs81, %rs82};

$L__BB0_137:
	ld.const.u64 	%rd84, [params+304];
	cvta.to.global.u64 	%rd85, %rd84;
	ld.const.u32 	%r329, [params+296];
	mad.lo.s32 	%r330, %r329, %r4, %r3;
	mul.wide.u32 	%rd86, %r330, 8;
	add.s64 	%rd24, %rd85, %rd86;
	@%p156 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs90, %rs91, %rs92, %rs93}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f985, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f986, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f987, %rs92;}

	// end inline asm
	add.f32 	%f988, %f154, %f985;
	add.f32 	%f989, %f154, %f986;
	add.f32 	%f990, %f154, %f987;
	mov.f32 	%f991, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f990;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f989;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f988;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f991;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs86, %rs87, %rs88, %rs89};
	bra.uni 	$L__BB0_160;

$L__BB0_139:
	mov.f32 	%f995, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f995;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f154;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f154;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f154;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs94, %rs95, %rs96, %rs97};

$L__BB0_160:
	ret;

}