//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<181>;
	.reg .b16 	%rs<328>;
	.reg .f32 	%f<1261>;
	.reg .b32 	%r<389>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<161>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r54), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r55), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd41, [params+400];
	cvta.to.global.u64 	%rd42, %rd41;
	ld.const.u32 	%r60, [params+392];
	mad.lo.s32 	%r61, %r60, %r55, %r54;
	mul.wide.u32 	%rd43, %r61, 4;
	add.s64 	%rd2, %rd42, %rd43;
	ld.global.v2.u8 	{%rs7, %rs327}, [%rd2];
	or.b16  	%rs9, %rs7, %rs327;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p8, %rs10, 0;
	@%p8 bra 	$L__BB0_2;

	ld.global.u8 	%rs326, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs326, [%rd2+2];
	setp.eq.s16 	%p9, %rs326, 0;
	mov.f32 	%f1227, 0f00000000;
	mov.u16 	%rs327, 0;
	mov.f32 	%f1228, %f1227;
	mov.f32 	%f1229, %f1227;
	@%p9 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f185, %rs7;
	div.rn.f32 	%f186, %f185, 0f437F0000;
	fma.rn.f32 	%f187, %f186, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs327, 255;
	cvt.rn.f32.u16 	%f188, %rs13;
	div.rn.f32 	%f189, %f188, 0f437F0000;
	fma.rn.f32 	%f190, %f189, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f191, %rs326;
	div.rn.f32 	%f192, %f191, 0f437F0000;
	fma.rn.f32 	%f193, %f192, 0f40000000, 0fBF800000;
	mul.f32 	%f194, %f190, %f190;
	fma.rn.f32 	%f195, %f187, %f187, %f194;
	fma.rn.f32 	%f196, %f193, %f193, %f195;
	sqrt.rn.f32 	%f197, %f196;
	rcp.rn.f32 	%f198, %f197;
	mul.f32 	%f1229, %f198, %f193;
	mul.f32 	%f1228, %f198, %f190;
	mul.f32 	%f1227, %f187, %f198;

$L__BB0_4:
	ld.const.v2.u32 	{%r62, %r63}, [params];
	add.s32 	%r3, %r62, %r54;
	add.s32 	%r4, %r63, %r55;
	setp.eq.f32 	%p10, %f1227, 0f00000000;
	setp.eq.f32 	%p11, %f1228, 0f00000000;
	and.pred  	%p12, %p10, %p11;
	setp.eq.f32 	%p13, %f1229, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	@%p14 bra 	$L__BB0_155;
	bra.uni 	$L__BB0_5;

$L__BB0_155:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r341, %r51, 1;
	setp.eq.b32 	%p165, %r341, 1;
	mov.pred 	%p166, 0;
	xor.pred  	%p167, %p165, %p166;
	not.pred 	%p168, %p167;
	@%p168 bra 	$L__BB0_157;

	ld.const.u64 	%rd112, [params+144];
	cvta.to.global.u64 	%rd113, %rd112;
	ld.const.u32 	%r342, [params+136];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	mul.wide.u32 	%rd114, %r343, 4;
	add.s64 	%rd115, %rd113, %rd114;
	mov.u16 	%rs173, 0;
	st.global.v4.u8 	[%rd115], {%rs173, %rs173, %rs173, %rs173};

$L__BB0_157:
	and.b32  	%r344, %r51, 8;
	setp.eq.s32 	%p169, %r344, 0;
	@%p169 bra 	$L__BB0_159;

	ld.const.u64 	%rd116, [params+192];
	cvta.to.global.u64 	%rd117, %rd116;
	ld.const.u32 	%r345, [params+184];
	mad.lo.s32 	%r346, %r345, %r4, %r3;
	mov.f32 	%f1086, 0f00000000;
	cvt.rzi.u32.f32 	%r347, %f1086;
	mul.wide.u32 	%rd118, %r346, 2;
	add.s64 	%rd119, %rd117, %rd118;
	mov.u16 	%rs174, 0;
	cvt.u16.u32 	%rs175, %r347;
	st.global.v2.u8 	[%rd119], {%rs175, %rs174};

$L__BB0_159:
	and.b32  	%r348, %r51, 4;
	setp.eq.s32 	%p170, %r348, 0;
	ld.const.u32 	%r388, [params+108];
	@%p170 bra 	$L__BB0_163;

	setp.eq.s32 	%p171, %r388, 0;
	ld.const.u64 	%rd120, [params+224];
	cvta.to.global.u64 	%rd121, %rd120;
	ld.const.u32 	%r349, [params+216];
	mad.lo.s32 	%r350, %r349, %r4, %r3;
	mul.wide.u32 	%rd122, %r350, 8;
	add.s64 	%rd30, %rd121, %rd122;
	@%p171 bra 	$L__BB0_162;

	ld.global.v4.u16 	{%rs182, %rs183, %rs184, %rs185}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1087, %rs182;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1088, %rs183;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1089, %rs184;}

	// end inline asm
	add.f32 	%f1090, %f1087, 0f00000000;
	add.f32 	%f1091, %f1088, 0f00000000;
	add.f32 	%f1092, %f1089, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs181, %f1092;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs180, %f1091;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs179, %f1090;}

	// end inline asm
	mov.u16 	%rs186, 0;
	st.global.v4.u16 	[%rd30], {%rs179, %rs180, %rs181, %rs186};
	bra.uni 	$L__BB0_163;

$L__BB0_5:
	ld.const.v4.f32 	{%f200, %f201, %f202, %f203}, [params+512];
	neg.f32 	%f204, %f201;
	neg.f32 	%f205, %f202;
	mul.f32 	%f206, %f1227, %f200;
	mul.f32 	%f207, %f1228, %f204;
	sub.f32 	%f208, %f207, %f206;
	mul.f32 	%f209, %f1229, %f202;
	sub.f32 	%f13, %f208, %f209;
	ld.const.u64 	%rd44, [params+432];
	cvta.to.global.u64 	%rd45, %rd44;
	ld.const.u32 	%r66, [params+424];
	mad.lo.s32 	%r67, %r66, %r55, %r54;
	mul.wide.u32 	%rd46, %r67, 12;
	add.s64 	%rd47, %rd45, %rd46;
	ld.global.f32 	%f210, [%rd47];
	mul.f32 	%f211, %f210, 0f3456BF95;
	ld.global.f32 	%f212, [%rd47+4];
	mul.f32 	%f213, %f212, 0f3456BF95;
	ld.global.f32 	%f214, [%rd47+8];
	mul.f32 	%f215, %f214, 0f3456BF95;
	abs.f32 	%f216, %f1227;
	div.rn.f32 	%f217, %f211, %f216;
	abs.f32 	%f218, %f1228;
	div.rn.f32 	%f219, %f213, %f218;
	abs.f32 	%f220, %f1229;
	div.rn.f32 	%f221, %f215, %f220;
	abs.f32 	%f222, %f217;
	abs.f32 	%f223, %f219;
	abs.f32 	%f224, %f221;
	mov.f32 	%f225, 0f38D1B717;
	max.f32 	%f226, %f222, %f225;
	max.f32 	%f227, %f223, %f225;
	max.f32 	%f228, %f224, %f225;
	fma.rn.f32 	%f14, %f1227, %f226, %f210;
	fma.rn.f32 	%f15, %f1228, %f227, %f212;
	fma.rn.f32 	%f16, %f1229, %f228, %f214;
	abs.f32 	%f229, %f200;
	abs.f32 	%f230, %f202;
	setp.gt.f32 	%p15, %f229, %f230;
	selp.f32 	%f231, %f204, 0f00000000, %p15;
	mov.f32 	%f1231, 0f00000000;
	selp.f32 	%f232, %f200, %f205, %p15;
	selp.f32 	%f233, 0f00000000, %f201, %p15;
	mul.f32 	%f234, %f232, %f232;
	fma.rn.f32 	%f235, %f231, %f231, %f234;
	fma.rn.f32 	%f236, %f233, %f233, %f235;
	sqrt.rn.f32 	%f237, %f236;
	rcp.rn.f32 	%f238, %f237;
	mul.f32 	%f17, %f231, %f238;
	mul.f32 	%f18, %f232, %f238;
	mul.f32 	%f19, %f233, %f238;
	ld.const.u64 	%rd48, [params+128];
	cvta.to.global.u64 	%rd49, %rd48;
	ld.const.u32 	%r68, [params+120];
	mad.lo.s32 	%r69, %r68, %r55, %r54;
	mul.wide.u32 	%rd50, %r69, 4;
	add.s64 	%rd3, %rd49, %rd50;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p16, %r5, 1;
	@%p16 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f240, %r5;
	rcp.rn.f32 	%f20, %f240;
	ld.global.u32 	%r379, [%rd3];
	ld.const.f32 	%f21, [params+536];
	ld.const.u8 	%rs15, [params+104];
	and.b16  	%rs16, %rs15, 32;
	setp.eq.s16 	%p17, %rs16, 0;
	mov.u32 	%r70, 0;
	selp.f32 	%f22, 0f3F800000, 0f41200000, %p17;
	mul.f32 	%f23, %f14, 0f3456BF95;
	mul.f32 	%f24, %f15, 0f3456BF95;
	mul.f32 	%f25, %f16, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f241, %f200, %f18;
	mul.f32 	%f242, %f201, %f17;
	sub.f32 	%f26, %f242, %f241;
	mul.f32 	%f243, %f202, %f17;
	mul.f32 	%f244, %f200, %f19;
	sub.f32 	%f27, %f244, %f243;
	mul.f32 	%f245, %f201, %f19;
	mul.f32 	%f246, %f202, %f18;
	sub.f32 	%f28, %f246, %f245;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f329, %f24;
	abs.f32 	%f330, %f23;
	max.f32 	%f331, %f330, %f329;
	abs.f32 	%f332, %f25;
	max.f32 	%f333, %f331, %f332;
	mov.u32 	%r376, %r70;

$L__BB0_7:
	cvt.rn.f32.s32 	%f30, %r376;
	mov.u32 	%r378, %r70;

$L__BB0_8:
	mad.lo.s32 	%r72, %r379, 1664525, 1013904223;
	and.b32  	%r73, %r72, 16777215;
	cvt.rn.f32.u32 	%f247, %r73;
	fma.rn.f32 	%f248, %f247, 0f33800000, %f30;
	mul.f32 	%f249, %f20, %f248;
	mad.lo.s32 	%r379, %r72, 1664525, 1013904223;
	and.b32  	%r74, %r379, 16777215;
	cvt.rn.f32.u32 	%f250, %r74;
	cvt.rn.f32.s32 	%f251, %r378;
	fma.rn.f32 	%f252, %f250, 0f33800000, %f251;
	mul.f32 	%f253, %f20, %f252;
	sqrt.rn.f32 	%f32, %f249;
	mul.f32 	%f33, %f253, 0f40C90FDB;
	mul.f32 	%f254, %f33, 0f3F22F983;
	cvt.rni.s32.f32 	%r386, %f254;
	cvt.rn.f32.s32 	%f255, %r386;
	mov.f32 	%f256, 0fBFC90FDA;
	fma.rn.f32 	%f257, %f255, %f256, %f33;
	mov.f32 	%f258, 0fB3A22168;
	fma.rn.f32 	%f259, %f255, %f258, %f257;
	mov.f32 	%f260, 0fA7C234C5;
	fma.rn.f32 	%f1235, %f255, %f260, %f259;
	abs.f32 	%f35, %f33;
	setp.ltu.f32 	%p18, %f35, 0f47CE4780;
	mov.u32 	%r383, %r386;
	mov.f32 	%f1232, %f1235;
	@%p18 bra 	$L__BB0_16;

	setp.eq.f32 	%p19, %f35, 0f7F800000;
	@%p19 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f263, 0f00000000;
	mul.rn.f32 	%f1232, %f33, %f263;
	mov.u32 	%r383, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f33;
	bfe.u32 	%r76, %r13, 23, 8;
	add.s32 	%r14, %r76, -128;
	shl.b32 	%r77, %r13, 8;
	or.b32  	%r15, %r77, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd158, 0;
	mov.u32 	%r380, 0;
	mov.u64 	%rd156, %rd1;
	mov.u64 	%rd157, %rd51;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r78, [%rd157];
	mad.wide.u32 	%rd53, %r78, %r15, %rd158;
	shr.u64 	%rd158, %rd53, 32;
	st.local.u32 	[%rd156], %rd53;
	add.s64 	%rd157, %rd157, 4;
	add.s64 	%rd156, %rd156, 4;
	add.s32 	%r380, %r380, 1;
	setp.ne.s32 	%p20, %r380, 6;
	@%p20 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd158;
	mov.u32 	%r79, 4;
	sub.s32 	%r19, %r79, %r16;
	mov.u32 	%r80, 6;
	sub.s32 	%r81, %r80, %r16;
	mul.wide.s32 	%rd54, %r81, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r381, [%rd55];
	ld.local.u32 	%r382, [%rd55+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p21, %r22, 0;
	@%p21 bra 	$L__BB0_14;

	mov.u32 	%r82, 32;
	sub.s32 	%r83, %r82, %r22;
	shr.u32 	%r84, %r382, %r83;
	shl.b32 	%r85, %r381, %r22;
	add.s32 	%r381, %r84, %r85;
	mul.wide.s32 	%rd56, %r19, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r86, [%rd57];
	shr.u32 	%r87, %r86, %r83;
	shl.b32 	%r88, %r382, %r22;
	add.s32 	%r382, %r87, %r88;

$L__BB0_14:
	and.b32  	%r89, %r13, -2147483648;
	shr.u32 	%r90, %r382, 30;
	shl.b32 	%r91, %r381, 2;
	or.b32  	%r92, %r90, %r91;
	shr.u32 	%r93, %r92, 31;
	shr.u32 	%r94, %r381, 30;
	add.s32 	%r95, %r93, %r94;
	neg.s32 	%r96, %r95;
	setp.eq.s32 	%p22, %r89, 0;
	selp.b32 	%r383, %r95, %r96, %p22;
	setp.ne.s32 	%p23, %r93, 0;
	xor.b32  	%r97, %r89, -2147483648;
	selp.b32 	%r98, %r97, %r89, %p23;
	selp.b32 	%r99, -1, 0, %p23;
	xor.b32  	%r100, %r92, %r99;
	shl.b32 	%r101, %r382, 2;
	xor.b32  	%r102, %r101, %r99;
	cvt.u64.u32 	%rd58, %r100;
	cvt.u64.u32 	%rd59, %r102;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f261, %fd2;
	setp.eq.s32 	%p24, %r98, 0;
	neg.f32 	%f262, %f261;
	selp.f32 	%f1232, %f261, %f262, %p24;

$L__BB0_16:
	add.s32 	%r29, %r383, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p25, %r30, 0;
	selp.f32 	%f39, %f1232, 0f3F800000, %p25;
	mul.rn.f32 	%f40, %f1232, %f1232;
	mov.f32 	%f1233, 0fB94D4153;
	@%p25 bra 	$L__BB0_18;

	mov.f32 	%f265, 0fBAB607ED;
	mov.f32 	%f266, 0f37CBAC00;
	fma.rn.f32 	%f1233, %f266, %f40, %f265;

$L__BB0_18:
	selp.f32 	%f267, 0f3C0885E4, 0f3D2AAABB, %p25;
	fma.rn.f32 	%f268, %f1233, %f40, %f267;
	selp.f32 	%f269, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
	fma.rn.f32 	%f270, %f268, %f40, %f269;
	mov.f32 	%f271, 0f00000000;
	fma.rn.f32 	%f272, %f40, %f39, %f271;
	fma.rn.f32 	%f1234, %f270, %f272, %f39;
	and.b32  	%r104, %r29, 2;
	setp.eq.s32 	%p27, %r104, 0;
	@%p27 bra 	$L__BB0_20;

	mov.f32 	%f274, 0fBF800000;
	fma.rn.f32 	%f1234, %f1234, %f274, %f271;

$L__BB0_20:
	@%p18 bra 	$L__BB0_28;

	setp.eq.f32 	%p29, %f35, 0f7F800000;
	@%p29 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f277, 0f00000000;
	mul.rn.f32 	%f1235, %f33, %f277;
	mov.u32 	%r386, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f33;
	bfe.u32 	%r105, %r31, 23, 8;
	add.s32 	%r32, %r105, -128;
	shl.b32 	%r106, %r31, 8;
	or.b32  	%r33, %r106, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd159, 0;
	mov.u64 	%rd160, %rd159;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd159, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r107, [%rd65];
	mad.wide.u32 	%rd66, %r107, %r33, %rd160;
	shr.u64 	%rd160, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r108, %rd159;
	add.s32 	%r109, %r108, 1;
	cvt.s64.s32 	%rd159, %r109;
	setp.ne.s32 	%p30, %r109, 6;
	@%p30 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd160;
	mov.u32 	%r110, 4;
	sub.s32 	%r35, %r110, %r34;
	mov.u32 	%r111, 6;
	sub.s32 	%r112, %r111, %r34;
	mul.wide.s32 	%rd68, %r112, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r384, [%rd69];
	ld.local.u32 	%r385, [%rd69+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p31, %r38, 0;
	@%p31 bra 	$L__BB0_26;

	mov.u32 	%r113, 32;
	sub.s32 	%r114, %r113, %r38;
	shr.u32 	%r115, %r385, %r114;
	shl.b32 	%r116, %r384, %r38;
	add.s32 	%r384, %r115, %r116;
	mul.wide.s32 	%rd70, %r35, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r117, [%rd71];
	shr.u32 	%r118, %r117, %r114;
	shl.b32 	%r119, %r385, %r38;
	add.s32 	%r385, %r118, %r119;

$L__BB0_26:
	and.b32  	%r120, %r31, -2147483648;
	shr.u32 	%r121, %r385, 30;
	shl.b32 	%r122, %r384, 2;
	or.b32  	%r123, %r121, %r122;
	shr.u32 	%r124, %r123, 31;
	shr.u32 	%r125, %r384, 30;
	add.s32 	%r126, %r124, %r125;
	neg.s32 	%r127, %r126;
	setp.eq.s32 	%p32, %r120, 0;
	selp.b32 	%r386, %r126, %r127, %p32;
	setp.ne.s32 	%p33, %r124, 0;
	xor.b32  	%r128, %r120, -2147483648;
	selp.b32 	%r129, %r128, %r120, %p33;
	selp.b32 	%r130, -1, 0, %p33;
	xor.b32  	%r131, %r123, %r130;
	shl.b32 	%r132, %r385, 2;
	xor.b32  	%r133, %r132, %r130;
	cvt.u64.u32 	%rd72, %r131;
	cvt.u64.u32 	%rd73, %r133;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f275, %fd4;
	setp.eq.s32 	%p34, %r129, 0;
	neg.f32 	%f276, %f275;
	selp.f32 	%f1235, %f275, %f276, %p34;

$L__BB0_28:
	mul.f32 	%f49, %f32, %f1234;
	and.b32  	%r45, %r386, 1;
	setp.eq.s32 	%p35, %r45, 0;
	selp.f32 	%f50, %f1235, 0f3F800000, %p35;
	mul.rn.f32 	%f51, %f1235, %f1235;
	mov.f32 	%f1236, 0fB94D4153;
	@%p35 bra 	$L__BB0_30;

	mov.f32 	%f279, 0fBAB607ED;
	mov.f32 	%f280, 0f37CBAC00;
	fma.rn.f32 	%f1236, %f280, %f51, %f279;

$L__BB0_30:
	selp.f32 	%f281, 0f3C0885E4, 0f3D2AAABB, %p35;
	fma.rn.f32 	%f282, %f1236, %f51, %f281;
	selp.f32 	%f283, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
	fma.rn.f32 	%f284, %f282, %f51, %f283;
	mov.f32 	%f285, 0f00000000;
	fma.rn.f32 	%f286, %f51, %f50, %f285;
	fma.rn.f32 	%f1237, %f284, %f286, %f50;
	and.b32  	%r135, %r386, 2;
	setp.eq.s32 	%p37, %r135, 0;
	@%p37 bra 	$L__BB0_32;

	mov.f32 	%f288, 0fBF800000;
	fma.rn.f32 	%f1237, %f1237, %f288, %f285;

$L__BB0_32:
	mul.f32 	%f298, %f49, %f49;
	mov.f32 	%f299, 0f3F800000;
	sub.f32 	%f300, %f299, %f298;
	mul.f32 	%f301, %f32, %f1237;
	mul.f32 	%f302, %f301, %f301;
	sub.f32 	%f303, %f300, %f302;
	max.f32 	%f304, %f285, %f303;
	sqrt.rn.f32 	%f305, %f304;
	mul.f32 	%f306, %f17, %f301;
	mul.f32 	%f307, %f18, %f301;
	mul.f32 	%f308, %f19, %f301;
	fma.rn.f32 	%f309, %f28, %f49, %f306;
	fma.rn.f32 	%f310, %f27, %f49, %f307;
	fma.rn.f32 	%f311, %f26, %f49, %f308;
	fma.rn.f32 	%f312, %f200, %f305, %f309;
	fma.rn.f32 	%f313, %f201, %f305, %f310;
	fma.rn.f32 	%f314, %f202, %f305, %f311;
	add.f32 	%f315, %f200, %f312;
	add.f32 	%f316, %f201, %f313;
	add.f32 	%f317, %f202, %f314;
	mul.f32 	%f318, %f21, %f315;
	mul.f32 	%f319, %f21, %f316;
	mul.f32 	%f320, %f21, %f317;
	sub.f32 	%f321, %f318, %f200;
	sub.f32 	%f322, %f319, %f201;
	sub.f32 	%f323, %f320, %f202;
	mul.f32 	%f324, %f322, %f322;
	fma.rn.f32 	%f325, %f321, %f321, %f324;
	fma.rn.f32 	%f326, %f323, %f323, %f325;
	sqrt.rn.f32 	%f327, %f326;
	rcp.rn.f32 	%f328, %f327;
	mul.f32 	%f292, %f328, %f321;
	mul.f32 	%f293, %f328, %f322;
	mul.f32 	%f294, %f328, %f323;
	mov.f32 	%f334, 0f38D1B717;
	max.f32 	%f335, %f333, %f334;
	mul.f32 	%f295, %f22, %f335;
	mov.f32 	%f296, 0f6C4ECB8F;
	mov.u32 	%r172, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f14,%f15,%f16,%f292,%f293,%f294,%f295,%f296,%f285,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f336, %r136;
	add.f32 	%f1231, %f1231, %f336;
	add.s32 	%r378, %r378, 1;
	setp.lt.s32 	%p38, %r378, %r5;
	@%p38 bra 	$L__BB0_8;

	add.s32 	%r376, %r376, 1;
	setp.lt.s32 	%p39, %r376, %r5;
	@%p39 bra 	$L__BB0_7;

$L__BB0_34:
	setp.eq.s32 	%p40, %r5, 0;
	mov.f32 	%f1239, 0f3F800000;
	@%p40 bra 	$L__BB0_36;

	mul.lo.s32 	%r207, %r5, %r5;
	cvt.rn.f32.s32 	%f338, %r207;
	div.rn.f32 	%f1239, %f1231, %f338;

$L__BB0_36:
	ld.const.f32 	%f339, [params+524];
	mul.f32 	%f61, %f1239, %f339;
	ld.const.v2.f32 	{%f340, %f341}, [params+528];
	mul.f32 	%f62, %f1239, %f340;
	mul.f32 	%f63, %f1239, %f341;
	cvt.sat.f32.f32 	%f344, %f13;
	mul.f32 	%f64, %f61, %f344;
	mul.f32 	%f65, %f62, %f344;
	mul.f32 	%f66, %f63, %f344;
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r208, %r48, 8;
	setp.eq.s32 	%p41, %r208, 0;
	@%p41 bra 	$L__BB0_50;

	mov.f32 	%f349, 0f3EE8BA2E;
	abs.f32 	%f68, %f1239;
	setp.lt.f32 	%p42, %f68, 0f00800000;
	mul.f32 	%f351, %f68, 0f4B800000;
	selp.f32 	%f352, %f351, %f68, %p42;
	selp.f32 	%f353, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r211, %f352;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f354, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f355, %r214;
	add.f32 	%f356, %f353, %f355;
	setp.gt.f32 	%p43, %f354, 0f3FB504F3;
	mul.f32 	%f357, %f354, 0f3F000000;
	add.f32 	%f358, %f356, 0f3F800000;
	selp.f32 	%f359, %f358, %f356, %p43;
	selp.f32 	%f360, %f357, %f354, %p43;
	add.f32 	%f361, %f360, 0fBF800000;
	add.f32 	%f362, %f360, 0f3F800000;
	rcp.approx.ftz.f32 	%f363, %f362;
	add.f32 	%f364, %f361, %f361;
	mul.f32 	%f365, %f364, %f363;
	mul.f32 	%f366, %f365, %f365;
	mov.f32 	%f367, 0f3C4CAF63;
	mov.f32 	%f368, 0f3B18F0FE;
	fma.rn.f32 	%f369, %f368, %f366, %f367;
	mov.f32 	%f370, 0f3DAAAABD;
	fma.rn.f32 	%f371, %f369, %f366, %f370;
	mul.rn.f32 	%f372, %f371, %f366;
	mul.rn.f32 	%f373, %f372, %f365;
	sub.f32 	%f374, %f361, %f365;
	add.f32 	%f375, %f374, %f374;
	neg.f32 	%f376, %f365;
	fma.rn.f32 	%f377, %f376, %f361, %f375;
	mul.rn.f32 	%f378, %f363, %f377;
	add.f32 	%f379, %f373, %f365;
	sub.f32 	%f380, %f365, %f379;
	add.f32 	%f381, %f373, %f380;
	add.f32 	%f382, %f378, %f381;
	add.f32 	%f383, %f379, %f382;
	sub.f32 	%f384, %f379, %f383;
	add.f32 	%f385, %f382, %f384;
	mov.f32 	%f386, 0f3F317200;
	mul.rn.f32 	%f387, %f359, %f386;
	mov.f32 	%f388, 0f35BFBE8E;
	mul.rn.f32 	%f389, %f359, %f388;
	add.f32 	%f390, %f387, %f383;
	sub.f32 	%f391, %f387, %f390;
	add.f32 	%f392, %f383, %f391;
	add.f32 	%f393, %f385, %f392;
	add.f32 	%f394, %f389, %f393;
	add.f32 	%f395, %f390, %f394;
	sub.f32 	%f396, %f390, %f395;
	add.f32 	%f397, %f394, %f396;
	mul.rn.f32 	%f398, %f349, %f395;
	neg.f32 	%f399, %f398;
	fma.rn.f32 	%f400, %f349, %f395, %f399;
	fma.rn.f32 	%f401, %f349, %f397, %f400;
	mov.f32 	%f402, 0f00000000;
	fma.rn.f32 	%f403, %f402, %f395, %f401;
	add.rn.f32 	%f404, %f398, %f403;
	neg.f32 	%f405, %f404;
	add.rn.f32 	%f406, %f398, %f405;
	add.rn.f32 	%f407, %f406, %f403;
	mov.b32 	%r215, %f404;
	setp.eq.s32 	%p44, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f408, %r216;
	add.f32 	%f409, %f407, 0f37000000;
	selp.f32 	%f69, %f409, %f407, %p44;
	selp.f32 	%f410, %f408, %f404, %p44;
	mov.f32 	%f411, 0f3FB8AA3B;
	mul.rn.f32 	%f412, %f410, %f411;
	cvt.rzi.f32.f32 	%f413, %f412;
	abs.f32 	%f414, %f413;
	setp.gt.f32 	%p45, %f414, 0f42FC0000;
	mov.b32 	%r217, %f413;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f415, %r219;
	selp.f32 	%f416, %f415, %f413, %p45;
	mov.f32 	%f417, 0fBF317218;
	fma.rn.f32 	%f418, %f416, %f417, %f410;
	mov.f32 	%f419, 0f3102E308;
	fma.rn.f32 	%f420, %f416, %f419, %f418;
	mul.f32 	%f421, %f420, 0f3FB8AA3B;
	add.f32 	%f422, %f416, 0f4B40007F;
	mov.b32 	%r220, %f422;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f423, %r221;
	ex2.approx.ftz.f32 	%f424, %f421;
	mul.f32 	%f70, %f424, %f423;
	setp.eq.f32 	%p46, %f70, 0f7F800000;
	mov.f32 	%f1240, 0f7F800000;
	@%p46 bra 	$L__BB0_39;

	fma.rn.f32 	%f1240, %f70, %f69, %f70;

$L__BB0_39:
	mov.f32 	%f1188, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1187, %f1188;
	add.f32 	%f1186, %f1187, %f1187;
	mov.f32 	%f1185, 0f3EE8BA2E;
	sub.f32 	%f1184, %f1185, %f1186;
	abs.f32 	%f1183, %f1184;
	setp.lt.f32 	%p47, %f1239, 0f00000000;
	setp.eq.f32 	%p48, %f1183, 0f3F800000;
	and.pred  	%p1, %p47, %p48;
	setp.eq.f32 	%p49, %f1239, 0f00000000;
	@%p49 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f429, %f1239, %f1239;
	selp.f32 	%f1242, %f429, 0f00000000, %p48;
	bra.uni 	$L__BB0_44;

$L__BB0_162:
	mov.f32 	%f1095, 0f00000000;
	mov.u32 	%r388, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs189, %f1095;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs188, %f1095;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs187, %f1095;}

	// end inline asm
	mov.u16 	%rs190, 0;
	st.global.v4.u16 	[%rd30], {%rs187, %rs188, %rs189, %rs190};

$L__BB0_163:
	ld.const.u64 	%rd123, [params+256];
	cvta.to.global.u64 	%rd124, %rd123;
	ld.const.u32 	%r352, [params+248];
	mad.lo.s32 	%r353, %r352, %r4, %r3;
	mul.wide.u32 	%rd125, %r353, 8;
	add.s64 	%rd31, %rd124, %rd125;
	setp.eq.s32 	%p172, %r388, 0;
	@%p172 bra 	$L__BB0_165;

	ld.global.v4.u16 	{%rs197, %rs198, %rs199, %rs200}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1096, %rs197;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1097, %rs198;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1098, %rs199;}

	// end inline asm
	add.f32 	%f1099, %f1096, 0f00000000;
	add.f32 	%f1100, %f1097, 0f00000000;
	add.f32 	%f1101, %f1098, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs196, %f1101;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs195, %f1100;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs194, %f1099;}

	// end inline asm
	mov.u16 	%rs201, 0;
	st.global.v4.u16 	[%rd31], {%rs194, %rs195, %rs196, %rs201};
	bra.uni 	$L__BB0_166;

$L__BB0_165:
	mov.f32 	%f1104, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs204, %f1104;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs203, %f1104;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs202, %f1104;}

	// end inline asm
	mov.u16 	%rs205, 0;
	st.global.v4.u16 	[%rd31], {%rs202, %rs203, %rs204, %rs205};

$L__BB0_166:
	ld.const.u64 	%rd126, [params+272];
	cvta.to.global.u64 	%rd127, %rd126;
	ld.const.u32 	%r354, [params+264];
	mad.lo.s32 	%r355, %r354, %r4, %r3;
	mul.wide.u32 	%rd128, %r355, 8;
	add.s64 	%rd32, %rd127, %rd128;
	@%p172 bra 	$L__BB0_168;

	ld.global.v4.u16 	{%rs212, %rs213, %rs214, %rs215}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1105, %rs212;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1106, %rs213;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1107, %rs214;}

	// end inline asm
	add.f32 	%f1108, %f1105, 0f00000000;
	add.f32 	%f1109, %f1106, 0f00000000;
	add.f32 	%f1110, %f1107, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs211, %f1110;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs210, %f1109;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs209, %f1108;}

	// end inline asm
	mov.u16 	%rs216, 0;
	st.global.v4.u16 	[%rd32], {%rs209, %rs210, %rs211, %rs216};
	bra.uni 	$L__BB0_169;

$L__BB0_168:
	mov.f32 	%f1113, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs219, %f1113;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs218, %f1113;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs217, %f1113;}

	// end inline asm
	mov.u16 	%rs220, 0;
	st.global.v4.u16 	[%rd32], {%rs217, %rs218, %rs219, %rs220};

$L__BB0_169:
	ld.const.u64 	%rd129, [params+288];
	cvta.to.global.u64 	%rd130, %rd129;
	ld.const.u32 	%r356, [params+280];
	mad.lo.s32 	%r357, %r356, %r4, %r3;
	mul.wide.u32 	%rd131, %r357, 8;
	add.s64 	%rd33, %rd130, %rd131;
	@%p172 bra 	$L__BB0_171;

	ld.global.v4.u16 	{%rs227, %rs228, %rs229, %rs230}, [%rd33];
	// begin inline asm
	{  cvt.f32.f16 %f1114, %rs227;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1115, %rs228;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1116, %rs229;}

	// end inline asm
	add.f32 	%f1117, %f1114, 0f00000000;
	add.f32 	%f1118, %f1115, 0f00000000;
	add.f32 	%f1119, %f1116, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs226, %f1119;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs225, %f1118;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs224, %f1117;}

	// end inline asm
	mov.u16 	%rs231, 0;
	st.global.v4.u16 	[%rd33], {%rs224, %rs225, %rs226, %rs231};
	bra.uni 	$L__BB0_172;

$L__BB0_171:
	mov.f32 	%f1122, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs234, %f1122;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs233, %f1122;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs232, %f1122;}

	// end inline asm
	mov.u16 	%rs235, 0;
	st.global.v4.u16 	[%rd33], {%rs232, %rs233, %rs234, %rs235};

$L__BB0_172:
	ld.const.u64 	%rd132, [params+304];
	cvta.to.global.u64 	%rd133, %rd132;
	ld.const.u32 	%r358, [params+296];
	mad.lo.s32 	%r359, %r358, %r4, %r3;
	mul.wide.u32 	%rd134, %r359, 8;
	add.s64 	%rd34, %rd133, %rd134;
	@%p172 bra 	$L__BB0_174;

	ld.global.v4.u16 	{%rs242, %rs243, %rs244, %rs245}, [%rd34];
	// begin inline asm
	{  cvt.f32.f16 %f1123, %rs242;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1124, %rs243;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1125, %rs244;}

	// end inline asm
	add.f32 	%f1126, %f1123, 0f00000000;
	add.f32 	%f1127, %f1124, 0f00000000;
	add.f32 	%f1128, %f1125, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs241, %f1128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs240, %f1127;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs239, %f1126;}

	// end inline asm
	mov.u16 	%rs246, 0;
	st.global.v4.u16 	[%rd34], {%rs239, %rs240, %rs241, %rs246};
	bra.uni 	$L__BB0_175;

$L__BB0_174:
	mov.f32 	%f1131, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs249, %f1131;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs248, %f1131;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs247, %f1131;}

	// end inline asm
	mov.u16 	%rs250, 0;
	st.global.v4.u16 	[%rd34], {%rs247, %rs248, %rs249, %rs250};

$L__BB0_175:
	ld.const.u64 	%rd135, [params+320];
	cvta.to.global.u64 	%rd136, %rd135;
	ld.const.u32 	%r360, [params+312];
	mad.lo.s32 	%r361, %r360, %r4, %r3;
	mul.wide.u32 	%rd137, %r361, 8;
	add.s64 	%rd35, %rd136, %rd137;
	@%p172 bra 	$L__BB0_177;

	ld.global.v4.u16 	{%rs257, %rs258, %rs259, %rs260}, [%rd35];
	// begin inline asm
	{  cvt.f32.f16 %f1132, %rs257;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1133, %rs258;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1134, %rs259;}

	// end inline asm
	add.f32 	%f1135, %f1132, 0f00000000;
	add.f32 	%f1136, %f1133, 0f00000000;
	add.f32 	%f1137, %f1134, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs256, %f1137;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs255, %f1136;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs254, %f1135;}

	// end inline asm
	mov.u16 	%rs261, 0;
	st.global.v4.u16 	[%rd35], {%rs254, %rs255, %rs256, %rs261};
	bra.uni 	$L__BB0_178;

$L__BB0_177:
	mov.f32 	%f1140, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs264, %f1140;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs263, %f1140;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs262, %f1140;}

	// end inline asm
	mov.u16 	%rs265, 0;
	st.global.v4.u16 	[%rd35], {%rs262, %rs263, %rs264, %rs265};

$L__BB0_178:
	ld.const.u64 	%rd138, [params+336];
	cvta.to.global.u64 	%rd139, %rd138;
	ld.const.u32 	%r362, [params+328];
	mad.lo.s32 	%r363, %r362, %r4, %r3;
	mul.wide.u32 	%rd140, %r363, 8;
	add.s64 	%rd36, %rd139, %rd140;
	@%p172 bra 	$L__BB0_180;

	ld.global.v4.u16 	{%rs272, %rs273, %rs274, %rs275}, [%rd36];
	// begin inline asm
	{  cvt.f32.f16 %f1141, %rs272;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1142, %rs273;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1143, %rs274;}

	// end inline asm
	add.f32 	%f1144, %f1141, 0f00000000;
	add.f32 	%f1145, %f1142, 0f00000000;
	add.f32 	%f1146, %f1143, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs271, %f1146;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs270, %f1145;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs269, %f1144;}

	// end inline asm
	mov.u16 	%rs276, 0;
	st.global.v4.u16 	[%rd36], {%rs269, %rs270, %rs271, %rs276};
	bra.uni 	$L__BB0_181;

$L__BB0_180:
	mov.f32 	%f1149, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs279, %f1149;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs278, %f1149;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs277, %f1149;}

	// end inline asm
	mov.u16 	%rs280, 0;
	st.global.v4.u16 	[%rd36], {%rs277, %rs278, %rs279, %rs280};

$L__BB0_181:
	ld.const.u64 	%rd141, [params+352];
	cvta.to.global.u64 	%rd142, %rd141;
	ld.const.u32 	%r364, [params+344];
	mad.lo.s32 	%r365, %r364, %r4, %r3;
	mul.wide.u32 	%rd143, %r365, 8;
	add.s64 	%rd37, %rd142, %rd143;
	@%p172 bra 	$L__BB0_183;

	ld.global.v4.u16 	{%rs287, %rs288, %rs289, %rs290}, [%rd37];
	// begin inline asm
	{  cvt.f32.f16 %f1150, %rs287;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1151, %rs288;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1152, %rs289;}

	// end inline asm
	add.f32 	%f1153, %f1150, 0f00000000;
	add.f32 	%f1154, %f1151, 0f00000000;
	add.f32 	%f1155, %f1152, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs286, %f1155;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs285, %f1154;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs284, %f1153;}

	// end inline asm
	mov.u16 	%rs291, 0;
	st.global.v4.u16 	[%rd37], {%rs284, %rs285, %rs286, %rs291};
	bra.uni 	$L__BB0_184;

$L__BB0_183:
	mov.f32 	%f1158, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs294, %f1158;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs293, %f1158;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs292, %f1158;}

	// end inline asm
	mov.u16 	%rs295, 0;
	st.global.v4.u16 	[%rd37], {%rs292, %rs293, %rs294, %rs295};

$L__BB0_184:
	ld.const.u64 	%rd144, [params+368];
	cvta.to.global.u64 	%rd145, %rd144;
	ld.const.u32 	%r366, [params+360];
	mad.lo.s32 	%r367, %r366, %r4, %r3;
	mul.wide.u32 	%rd146, %r367, 8;
	add.s64 	%rd38, %rd145, %rd146;
	@%p172 bra 	$L__BB0_186;

	ld.global.v4.u16 	{%rs302, %rs303, %rs304, %rs305}, [%rd38];
	// begin inline asm
	{  cvt.f32.f16 %f1159, %rs302;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1160, %rs303;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1161, %rs304;}

	// end inline asm
	add.f32 	%f1162, %f1159, 0f00000000;
	add.f32 	%f1163, %f1160, 0f00000000;
	add.f32 	%f1164, %f1161, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs301, %f1164;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs300, %f1163;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs299, %f1162;}

	// end inline asm
	mov.u16 	%rs306, 0;
	st.global.v4.u16 	[%rd38], {%rs299, %rs300, %rs301, %rs306};
	bra.uni 	$L__BB0_187;

$L__BB0_186:
	mov.f32 	%f1167, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs309, %f1167;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs308, %f1167;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs307, %f1167;}

	// end inline asm
	mov.u16 	%rs310, 0;
	st.global.v4.u16 	[%rd38], {%rs307, %rs308, %rs309, %rs310};

$L__BB0_187:
	ld.const.u64 	%rd147, [params+384];
	cvta.to.global.u64 	%rd148, %rd147;
	ld.const.u32 	%r368, [params+376];
	mad.lo.s32 	%r369, %r368, %r4, %r3;
	mul.wide.u32 	%rd149, %r369, 8;
	add.s64 	%rd39, %rd148, %rd149;
	@%p172 bra 	$L__BB0_189;

	ld.global.v4.u16 	{%rs317, %rs318, %rs319, %rs320}, [%rd39];
	// begin inline asm
	{  cvt.f32.f16 %f1168, %rs317;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1169, %rs318;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1170, %rs319;}

	// end inline asm
	add.f32 	%f1171, %f1168, 0f00000000;
	add.f32 	%f1172, %f1169, 0f00000000;
	add.f32 	%f1173, %f1170, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs316, %f1173;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs315, %f1172;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs314, %f1171;}

	// end inline asm
	mov.u16 	%rs321, 0;
	st.global.v4.u16 	[%rd39], {%rs314, %rs315, %rs316, %rs321};
	bra.uni 	$L__BB0_190;

$L__BB0_189:
	mov.f32 	%f1176, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs324, %f1176;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs323, %f1176;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs322, %f1176;}

	// end inline asm
	mov.u16 	%rs325, 0;
	st.global.v4.u16 	[%rd39], {%rs322, %rs323, %rs324, %rs325};
	bra.uni 	$L__BB0_190;

$L__BB0_40:
	mov.b32 	%r222, %f1240;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f425, %r223;
	selp.f32 	%f1242, %f425, %f1240, %p1;
	setp.geu.f32 	%p50, %f1239, 0f00000000;
	@%p50 bra 	$L__BB0_44;

	mov.f32 	%f426, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f427, %f426;
	setp.eq.f32 	%p51, %f427, 0f3EE8BA2E;
	@%p51 bra 	$L__BB0_44;

	mov.f32 	%f1242, 0f7FFFFFFF;

$L__BB0_44:
	abs.f32 	%f1189, %f1239;
	add.f32 	%f430, %f1189, 0f3EE8BA2E;
	mov.b32 	%r224, %f430;
	setp.lt.s32 	%p53, %r224, 2139095040;
	@%p53 bra 	$L__BB0_49;

	abs.f32 	%f1192, %f1239;
	setp.gtu.f32 	%p54, %f1192, 0f7F800000;
	@%p54 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1242, %f1239, 0f3EE8BA2E;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	abs.f32 	%f1193, %f1239;
	setp.neu.f32 	%p55, %f1193, 0f7F800000;
	@%p55 bra 	$L__BB0_49;

	selp.f32 	%f1242, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	ld.const.u32 	%r375, [params+184];
	mad.lo.s32 	%r374, %r375, %r4, %r3;
	cvt.u64.u32 	%rd155, %r374;
	ld.const.u64 	%rd154, [params+192];
	cvta.to.global.u64 	%rd153, %rd154;
	mul.f32 	%f431, %f1242, 0f437F0000;
	setp.eq.f32 	%p56, %f1239, 0f3F800000;
	selp.f32 	%f432, 0f437F0000, %f431, %p56;
	cvt.rzi.u32.f32 	%r225, %f432;
	shl.b64 	%rd77, %rd155, 1;
	add.s64 	%rd78, %rd153, %rd77;
	cvt.u16.u32 	%rs17, %r225;
	mov.u16 	%rs18, 255;
	st.global.v2.u8 	[%rd78], {%rs17, %rs18};

$L__BB0_50:
	ld.const.u32 	%r373, [params+104];
	and.b32  	%r226, %r373, 1;
	setp.eq.b32 	%p57, %r226, 1;
	mov.pred 	%p58, 0;
	xor.pred  	%p59, %p57, %p58;
	not.pred 	%p60, %p59;
	@%p60 bra 	$L__BB0_124;

	mov.f32 	%f437, 0f3EE66666;
	abs.f32 	%f80, %f64;
	setp.lt.f32 	%p61, %f80, 0f00800000;
	mul.f32 	%f439, %f80, 0f4B800000;
	selp.f32 	%f440, %f439, %f80, %p61;
	selp.f32 	%f441, 0fC3170000, 0fC2FE0000, %p61;
	mov.b32 	%r227, %f440;
	and.b32  	%r228, %r227, 8388607;
	or.b32  	%r229, %r228, 1065353216;
	mov.b32 	%f442, %r229;
	shr.u32 	%r230, %r227, 23;
	cvt.rn.f32.u32 	%f443, %r230;
	add.f32 	%f444, %f441, %f443;
	setp.gt.f32 	%p62, %f442, 0f3FB504F3;
	mul.f32 	%f445, %f442, 0f3F000000;
	add.f32 	%f446, %f444, 0f3F800000;
	selp.f32 	%f447, %f446, %f444, %p62;
	selp.f32 	%f448, %f445, %f442, %p62;
	add.f32 	%f449, %f448, 0fBF800000;
	add.f32 	%f450, %f448, 0f3F800000;
	rcp.approx.ftz.f32 	%f451, %f450;
	add.f32 	%f452, %f449, %f449;
	mul.f32 	%f453, %f452, %f451;
	mul.f32 	%f454, %f453, %f453;
	mov.f32 	%f455, 0f3C4CAF63;
	mov.f32 	%f456, 0f3B18F0FE;
	fma.rn.f32 	%f457, %f456, %f454, %f455;
	mov.f32 	%f458, 0f3DAAAABD;
	fma.rn.f32 	%f459, %f457, %f454, %f458;
	mul.rn.f32 	%f460, %f459, %f454;
	mul.rn.f32 	%f461, %f460, %f453;
	sub.f32 	%f462, %f449, %f453;
	add.f32 	%f463, %f462, %f462;
	neg.f32 	%f464, %f453;
	fma.rn.f32 	%f465, %f464, %f449, %f463;
	mul.rn.f32 	%f466, %f451, %f465;
	add.f32 	%f467, %f461, %f453;
	sub.f32 	%f468, %f453, %f467;
	add.f32 	%f469, %f461, %f468;
	add.f32 	%f470, %f466, %f469;
	add.f32 	%f471, %f467, %f470;
	sub.f32 	%f472, %f467, %f471;
	add.f32 	%f473, %f470, %f472;
	mov.f32 	%f474, 0f3F317200;
	mul.rn.f32 	%f475, %f447, %f474;
	mov.f32 	%f476, 0f35BFBE8E;
	mul.rn.f32 	%f477, %f447, %f476;
	add.f32 	%f478, %f475, %f471;
	sub.f32 	%f479, %f475, %f478;
	add.f32 	%f480, %f471, %f479;
	add.f32 	%f481, %f473, %f480;
	add.f32 	%f482, %f477, %f481;
	add.f32 	%f483, %f478, %f482;
	sub.f32 	%f484, %f478, %f483;
	add.f32 	%f485, %f482, %f484;
	mul.rn.f32 	%f486, %f437, %f483;
	neg.f32 	%f487, %f486;
	fma.rn.f32 	%f488, %f437, %f483, %f487;
	fma.rn.f32 	%f489, %f437, %f485, %f488;
	mov.f32 	%f490, 0f00000000;
	fma.rn.f32 	%f491, %f490, %f483, %f489;
	add.rn.f32 	%f492, %f486, %f491;
	neg.f32 	%f493, %f492;
	add.rn.f32 	%f494, %f486, %f493;
	add.rn.f32 	%f495, %f494, %f491;
	mov.b32 	%r231, %f492;
	setp.eq.s32 	%p63, %r231, 1118925336;
	add.s32 	%r232, %r231, -1;
	mov.b32 	%f496, %r232;
	add.f32 	%f497, %f495, 0f37000000;
	selp.f32 	%f81, %f497, %f495, %p63;
	selp.f32 	%f498, %f496, %f492, %p63;
	mov.f32 	%f499, 0f3FB8AA3B;
	mul.rn.f32 	%f500, %f498, %f499;
	cvt.rzi.f32.f32 	%f501, %f500;
	abs.f32 	%f502, %f501;
	setp.gt.f32 	%p64, %f502, 0f42FC0000;
	mov.b32 	%r233, %f501;
	and.b32  	%r234, %r233, -2147483648;
	or.b32  	%r235, %r234, 1123811328;
	mov.b32 	%f503, %r235;
	selp.f32 	%f504, %f503, %f501, %p64;
	mov.f32 	%f505, 0fBF317218;
	fma.rn.f32 	%f506, %f504, %f505, %f498;
	mov.f32 	%f507, 0f3102E308;
	fma.rn.f32 	%f508, %f504, %f507, %f506;
	mul.f32 	%f509, %f508, 0f3FB8AA3B;
	add.f32 	%f510, %f504, 0f4B40007F;
	mov.b32 	%r236, %f510;
	shl.b32 	%r237, %r236, 23;
	mov.b32 	%f511, %r237;
	ex2.approx.ftz.f32 	%f512, %f509;
	mul.f32 	%f82, %f512, %f511;
	setp.eq.f32 	%p65, %f82, 0f7F800000;
	mov.f32 	%f1243, 0f7F800000;
	@%p65 bra 	$L__BB0_53;

	fma.rn.f32 	%f1243, %f82, %f81, %f82;

$L__BB0_53:
	mov.f32 	%f1199, 0f3E666666;
	cvt.rzi.f32.f32 	%f1198, %f1199;
	add.f32 	%f1197, %f1198, %f1198;
	mov.f32 	%f1196, 0f3EE66666;
	sub.f32 	%f1195, %f1196, %f1197;
	abs.f32 	%f1194, %f1195;
	setp.lt.f32 	%p66, %f64, 0f00000000;
	setp.eq.f32 	%p67, %f1194, 0f3F800000;
	and.pred  	%p2, %p66, %p67;
	setp.eq.f32 	%p68, %f64, 0f00000000;
	@%p68 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f517, %f64, %f64;
	selp.f32 	%f1245, %f517, 0f00000000, %p67;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r238, %f1243;
	xor.b32  	%r239, %r238, -2147483648;
	mov.b32 	%f513, %r239;
	selp.f32 	%f1245, %f513, %f1243, %p2;
	setp.geu.f32 	%p69, %f64, 0f00000000;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f514, 0f3EE66666;
	cvt.rzi.f32.f32 	%f515, %f514;
	setp.eq.f32 	%p70, %f515, 0f3EE66666;
	@%p70 bra 	$L__BB0_58;

	mov.f32 	%f1245, 0f7FFFFFFF;

$L__BB0_58:
	abs.f32 	%f1200, %f64;
	add.f32 	%f518, %f1200, 0f3EE66666;
	mov.b32 	%r240, %f518;
	setp.lt.s32 	%p72, %r240, 2139095040;
	@%p72 bra 	$L__BB0_63;

	abs.f32 	%f1201, %f64;
	setp.gtu.f32 	%p73, %f1201, 0f7F800000;
	@%p73 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1245, %f64, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	abs.f32 	%f1202, %f64;
	setp.neu.f32 	%p74, %f1202, 0f7F800000;
	@%p74 bra 	$L__BB0_63;

	selp.f32 	%f1245, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p75, %f64, 0f3F800000;
	selp.f32 	%f91, 0f3F800000, %f1245, %p75;
	abs.f32 	%f92, %f65;
	setp.lt.f32 	%p76, %f92, 0f00800000;
	mul.f32 	%f520, %f92, 0f4B800000;
	selp.f32 	%f521, %f520, %f92, %p76;
	selp.f32 	%f522, 0fC3170000, 0fC2FE0000, %p76;
	mov.b32 	%r241, %f521;
	and.b32  	%r242, %r241, 8388607;
	or.b32  	%r243, %r242, 1065353216;
	mov.b32 	%f523, %r243;
	shr.u32 	%r244, %r241, 23;
	cvt.rn.f32.u32 	%f524, %r244;
	add.f32 	%f525, %f522, %f524;
	setp.gt.f32 	%p77, %f523, 0f3FB504F3;
	mul.f32 	%f526, %f523, 0f3F000000;
	add.f32 	%f527, %f525, 0f3F800000;
	selp.f32 	%f528, %f527, %f525, %p77;
	selp.f32 	%f529, %f526, %f523, %p77;
	add.f32 	%f530, %f529, 0fBF800000;
	add.f32 	%f531, %f529, 0f3F800000;
	rcp.approx.ftz.f32 	%f532, %f531;
	add.f32 	%f533, %f530, %f530;
	mul.f32 	%f534, %f533, %f532;
	mul.f32 	%f535, %f534, %f534;
	mov.f32 	%f536, 0f3C4CAF63;
	mov.f32 	%f537, 0f3B18F0FE;
	fma.rn.f32 	%f538, %f537, %f535, %f536;
	mov.f32 	%f539, 0f3DAAAABD;
	fma.rn.f32 	%f540, %f538, %f535, %f539;
	mul.rn.f32 	%f541, %f540, %f535;
	mul.rn.f32 	%f542, %f541, %f534;
	sub.f32 	%f543, %f530, %f534;
	add.f32 	%f544, %f543, %f543;
	neg.f32 	%f545, %f534;
	fma.rn.f32 	%f546, %f545, %f530, %f544;
	mul.rn.f32 	%f547, %f532, %f546;
	add.f32 	%f548, %f542, %f534;
	sub.f32 	%f549, %f534, %f548;
	add.f32 	%f550, %f542, %f549;
	add.f32 	%f551, %f547, %f550;
	add.f32 	%f552, %f548, %f551;
	sub.f32 	%f553, %f548, %f552;
	add.f32 	%f554, %f551, %f553;
	mov.f32 	%f555, 0f3F317200;
	mul.rn.f32 	%f556, %f528, %f555;
	mov.f32 	%f557, 0f35BFBE8E;
	mul.rn.f32 	%f558, %f528, %f557;
	add.f32 	%f559, %f556, %f552;
	sub.f32 	%f560, %f556, %f559;
	add.f32 	%f561, %f552, %f560;
	add.f32 	%f562, %f554, %f561;
	add.f32 	%f563, %f558, %f562;
	add.f32 	%f564, %f559, %f563;
	sub.f32 	%f565, %f559, %f564;
	add.f32 	%f566, %f563, %f565;
	mov.f32 	%f567, 0f3EE66666;
	mul.rn.f32 	%f568, %f567, %f564;
	neg.f32 	%f569, %f568;
	fma.rn.f32 	%f570, %f567, %f564, %f569;
	fma.rn.f32 	%f571, %f567, %f566, %f570;
	mov.f32 	%f572, 0f00000000;
	fma.rn.f32 	%f573, %f572, %f564, %f571;
	add.rn.f32 	%f574, %f568, %f573;
	neg.f32 	%f575, %f574;
	add.rn.f32 	%f576, %f568, %f575;
	add.rn.f32 	%f577, %f576, %f573;
	mov.b32 	%r245, %f574;
	setp.eq.s32 	%p78, %r245, 1118925336;
	add.s32 	%r246, %r245, -1;
	mov.b32 	%f578, %r246;
	add.f32 	%f579, %f577, 0f37000000;
	selp.f32 	%f93, %f579, %f577, %p78;
	selp.f32 	%f580, %f578, %f574, %p78;
	mov.f32 	%f581, 0f3FB8AA3B;
	mul.rn.f32 	%f582, %f580, %f581;
	cvt.rzi.f32.f32 	%f583, %f582;
	abs.f32 	%f584, %f583;
	setp.gt.f32 	%p79, %f584, 0f42FC0000;
	mov.b32 	%r247, %f583;
	and.b32  	%r248, %r247, -2147483648;
	or.b32  	%r249, %r248, 1123811328;
	mov.b32 	%f585, %r249;
	selp.f32 	%f586, %f585, %f583, %p79;
	mov.f32 	%f587, 0fBF317218;
	fma.rn.f32 	%f588, %f586, %f587, %f580;
	mov.f32 	%f589, 0f3102E308;
	fma.rn.f32 	%f590, %f586, %f589, %f588;
	mul.f32 	%f591, %f590, 0f3FB8AA3B;
	add.f32 	%f592, %f586, 0f4B40007F;
	mov.b32 	%r250, %f592;
	shl.b32 	%r251, %r250, 23;
	mov.b32 	%f593, %r251;
	ex2.approx.ftz.f32 	%f594, %f591;
	mul.f32 	%f94, %f594, %f593;
	setp.eq.f32 	%p80, %f94, 0f7F800000;
	mov.f32 	%f1246, 0f7F800000;
	@%p80 bra 	$L__BB0_65;

	fma.rn.f32 	%f1246, %f94, %f93, %f94;

$L__BB0_65:
	setp.lt.f32 	%p81, %f65, 0f00000000;
	and.pred  	%p3, %p81, %p67;
	setp.eq.f32 	%p83, %f65, 0f00000000;
	@%p83 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f599, %f65, %f65;
	selp.f32 	%f1248, %f599, 0f00000000, %p67;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r252, %f1246;
	xor.b32  	%r253, %r252, -2147483648;
	mov.b32 	%f595, %r253;
	selp.f32 	%f1248, %f595, %f1246, %p3;
	setp.geu.f32 	%p84, %f65, 0f00000000;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f596, 0f3EE66666;
	cvt.rzi.f32.f32 	%f597, %f596;
	setp.eq.f32 	%p85, %f597, 0f3EE66666;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f1248, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1203, %f65;
	add.f32 	%f600, %f1203, 0f3EE66666;
	mov.b32 	%r254, %f600;
	setp.lt.s32 	%p87, %r254, 2139095040;
	@%p87 bra 	$L__BB0_75;

	abs.f32 	%f1204, %f65;
	setp.gtu.f32 	%p88, %f1204, 0f7F800000;
	@%p88 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1248, %f65, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1205, %f65;
	setp.neu.f32 	%p89, %f1205, 0f7F800000;
	@%p89 bra 	$L__BB0_75;

	selp.f32 	%f1248, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p90, %f65, 0f3F800000;
	selp.f32 	%f103, 0f3F800000, %f1248, %p90;
	abs.f32 	%f104, %f66;
	setp.lt.f32 	%p91, %f104, 0f00800000;
	mul.f32 	%f602, %f104, 0f4B800000;
	selp.f32 	%f603, %f602, %f104, %p91;
	selp.f32 	%f604, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r255, %f603;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f605, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f606, %r258;
	add.f32 	%f607, %f604, %f606;
	setp.gt.f32 	%p92, %f605, 0f3FB504F3;
	mul.f32 	%f608, %f605, 0f3F000000;
	add.f32 	%f609, %f607, 0f3F800000;
	selp.f32 	%f610, %f609, %f607, %p92;
	selp.f32 	%f611, %f608, %f605, %p92;
	add.f32 	%f612, %f611, 0fBF800000;
	add.f32 	%f613, %f611, 0f3F800000;
	rcp.approx.ftz.f32 	%f614, %f613;
	add.f32 	%f615, %f612, %f612;
	mul.f32 	%f616, %f615, %f614;
	mul.f32 	%f617, %f616, %f616;
	mov.f32 	%f618, 0f3C4CAF63;
	mov.f32 	%f619, 0f3B18F0FE;
	fma.rn.f32 	%f620, %f619, %f617, %f618;
	mov.f32 	%f621, 0f3DAAAABD;
	fma.rn.f32 	%f622, %f620, %f617, %f621;
	mul.rn.f32 	%f623, %f622, %f617;
	mul.rn.f32 	%f624, %f623, %f616;
	sub.f32 	%f625, %f612, %f616;
	add.f32 	%f626, %f625, %f625;
	neg.f32 	%f627, %f616;
	fma.rn.f32 	%f628, %f627, %f612, %f626;
	mul.rn.f32 	%f629, %f614, %f628;
	add.f32 	%f630, %f624, %f616;
	sub.f32 	%f631, %f616, %f630;
	add.f32 	%f632, %f624, %f631;
	add.f32 	%f633, %f629, %f632;
	add.f32 	%f634, %f630, %f633;
	sub.f32 	%f635, %f630, %f634;
	add.f32 	%f636, %f633, %f635;
	mov.f32 	%f637, 0f3F317200;
	mul.rn.f32 	%f638, %f610, %f637;
	mov.f32 	%f639, 0f35BFBE8E;
	mul.rn.f32 	%f640, %f610, %f639;
	add.f32 	%f641, %f638, %f634;
	sub.f32 	%f642, %f638, %f641;
	add.f32 	%f643, %f634, %f642;
	add.f32 	%f644, %f636, %f643;
	add.f32 	%f645, %f640, %f644;
	add.f32 	%f646, %f641, %f645;
	sub.f32 	%f647, %f641, %f646;
	add.f32 	%f648, %f645, %f647;
	mov.f32 	%f649, 0f3EE66666;
	mul.rn.f32 	%f650, %f649, %f646;
	neg.f32 	%f651, %f650;
	fma.rn.f32 	%f652, %f649, %f646, %f651;
	fma.rn.f32 	%f653, %f649, %f648, %f652;
	mov.f32 	%f654, 0f00000000;
	fma.rn.f32 	%f655, %f654, %f646, %f653;
	add.rn.f32 	%f656, %f650, %f655;
	neg.f32 	%f657, %f656;
	add.rn.f32 	%f658, %f650, %f657;
	add.rn.f32 	%f659, %f658, %f655;
	mov.b32 	%r259, %f656;
	setp.eq.s32 	%p93, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f660, %r260;
	add.f32 	%f661, %f659, 0f37000000;
	selp.f32 	%f105, %f661, %f659, %p93;
	selp.f32 	%f662, %f660, %f656, %p93;
	mov.f32 	%f663, 0f3FB8AA3B;
	mul.rn.f32 	%f664, %f662, %f663;
	cvt.rzi.f32.f32 	%f665, %f664;
	abs.f32 	%f666, %f665;
	setp.gt.f32 	%p94, %f666, 0f42FC0000;
	mov.b32 	%r261, %f665;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f667, %r263;
	selp.f32 	%f668, %f667, %f665, %p94;
	mov.f32 	%f669, 0fBF317218;
	fma.rn.f32 	%f670, %f668, %f669, %f662;
	mov.f32 	%f671, 0f3102E308;
	fma.rn.f32 	%f672, %f668, %f671, %f670;
	mul.f32 	%f673, %f672, 0f3FB8AA3B;
	add.f32 	%f674, %f668, 0f4B40007F;
	mov.b32 	%r264, %f674;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f675, %r265;
	ex2.approx.ftz.f32 	%f676, %f673;
	mul.f32 	%f106, %f676, %f675;
	setp.eq.f32 	%p95, %f106, 0f7F800000;
	mov.f32 	%f1249, 0f7F800000;
	@%p95 bra 	$L__BB0_77;

	fma.rn.f32 	%f1249, %f106, %f105, %f106;

$L__BB0_77:
	setp.lt.f32 	%p96, %f66, 0f00000000;
	and.pred  	%p4, %p96, %p67;
	setp.eq.f32 	%p98, %f66, 0f00000000;
	@%p98 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f681, %f66, %f66;
	selp.f32 	%f1251, %f681, 0f00000000, %p67;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r266, %f1249;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f677, %r267;
	selp.f32 	%f1251, %f677, %f1249, %p4;
	setp.geu.f32 	%p99, %f66, 0f00000000;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f678, 0f3EE66666;
	cvt.rzi.f32.f32 	%f679, %f678;
	setp.eq.f32 	%p100, %f679, 0f3EE66666;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f1251, 0f7FFFFFFF;

$L__BB0_82:
	abs.f32 	%f1206, %f66;
	add.f32 	%f682, %f1206, 0f3EE66666;
	mov.b32 	%r268, %f682;
	setp.lt.s32 	%p102, %r268, 2139095040;
	@%p102 bra 	$L__BB0_87;

	abs.f32 	%f1207, %f66;
	setp.gtu.f32 	%p103, %f1207, 0f7F800000;
	@%p103 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1251, %f66, 0f3EE66666;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	abs.f32 	%f1208, %f66;
	setp.neu.f32 	%p104, %f1208, 0f7F800000;
	@%p104 bra 	$L__BB0_87;

	selp.f32 	%f1251, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	setp.eq.f32 	%p105, %f66, 0f3F800000;
	mov.f32 	%f684, 0f3F800000;
	selp.f32 	%f685, 0f3F800000, %f1251, %p105;
	min.f32 	%f686, %f91, %f684;
	mov.f32 	%f687, 0f00000000;
	max.f32 	%f115, %f687, %f686;
	min.f32 	%f688, %f103, %f684;
	max.f32 	%f116, %f687, %f688;
	min.f32 	%f689, %f685, %f684;
	max.f32 	%f117, %f687, %f689;
	mov.f32 	%f693, 0f3ED55555;
	abs.f32 	%f119, %f115;
	setp.lt.f32 	%p106, %f119, 0f00800000;
	mul.f32 	%f695, %f119, 0f4B800000;
	selp.f32 	%f696, %f695, %f119, %p106;
	selp.f32 	%f697, 0fC3170000, 0fC2FE0000, %p106;
	mov.b32 	%r271, %f696;
	and.b32  	%r272, %r271, 8388607;
	or.b32  	%r273, %r272, 1065353216;
	mov.b32 	%f698, %r273;
	shr.u32 	%r274, %r271, 23;
	cvt.rn.f32.u32 	%f699, %r274;
	add.f32 	%f700, %f697, %f699;
	setp.gt.f32 	%p107, %f698, 0f3FB504F3;
	mul.f32 	%f701, %f698, 0f3F000000;
	add.f32 	%f702, %f700, 0f3F800000;
	selp.f32 	%f703, %f702, %f700, %p107;
	selp.f32 	%f704, %f701, %f698, %p107;
	add.f32 	%f705, %f704, 0fBF800000;
	add.f32 	%f706, %f704, 0f3F800000;
	rcp.approx.ftz.f32 	%f707, %f706;
	add.f32 	%f708, %f705, %f705;
	mul.f32 	%f709, %f708, %f707;
	mul.f32 	%f710, %f709, %f709;
	mov.f32 	%f711, 0f3C4CAF63;
	mov.f32 	%f712, 0f3B18F0FE;
	fma.rn.f32 	%f713, %f712, %f710, %f711;
	mov.f32 	%f714, 0f3DAAAABD;
	fma.rn.f32 	%f715, %f713, %f710, %f714;
	mul.rn.f32 	%f716, %f715, %f710;
	mul.rn.f32 	%f717, %f716, %f709;
	sub.f32 	%f718, %f705, %f709;
	add.f32 	%f719, %f718, %f718;
	neg.f32 	%f720, %f709;
	fma.rn.f32 	%f721, %f720, %f705, %f719;
	mul.rn.f32 	%f722, %f707, %f721;
	add.f32 	%f723, %f717, %f709;
	sub.f32 	%f724, %f709, %f723;
	add.f32 	%f725, %f717, %f724;
	add.f32 	%f726, %f722, %f725;
	add.f32 	%f727, %f723, %f726;
	sub.f32 	%f728, %f723, %f727;
	add.f32 	%f729, %f726, %f728;
	mov.f32 	%f730, 0f3F317200;
	mul.rn.f32 	%f731, %f703, %f730;
	mov.f32 	%f732, 0f35BFBE8E;
	mul.rn.f32 	%f733, %f703, %f732;
	add.f32 	%f734, %f731, %f727;
	sub.f32 	%f735, %f731, %f734;
	add.f32 	%f736, %f727, %f735;
	add.f32 	%f737, %f729, %f736;
	add.f32 	%f738, %f733, %f737;
	add.f32 	%f739, %f734, %f738;
	sub.f32 	%f740, %f734, %f739;
	add.f32 	%f741, %f738, %f740;
	mul.rn.f32 	%f742, %f693, %f739;
	neg.f32 	%f743, %f742;
	fma.rn.f32 	%f744, %f693, %f739, %f743;
	fma.rn.f32 	%f745, %f693, %f741, %f744;
	fma.rn.f32 	%f746, %f687, %f739, %f745;
	add.rn.f32 	%f747, %f742, %f746;
	neg.f32 	%f748, %f747;
	add.rn.f32 	%f749, %f742, %f748;
	add.rn.f32 	%f750, %f749, %f746;
	mov.b32 	%r275, %f747;
	setp.eq.s32 	%p108, %r275, 1118925336;
	add.s32 	%r276, %r275, -1;
	mov.b32 	%f751, %r276;
	add.f32 	%f752, %f750, 0f37000000;
	selp.f32 	%f120, %f752, %f750, %p108;
	selp.f32 	%f753, %f751, %f747, %p108;
	mov.f32 	%f754, 0f3FB8AA3B;
	mul.rn.f32 	%f755, %f753, %f754;
	cvt.rzi.f32.f32 	%f756, %f755;
	abs.f32 	%f757, %f756;
	setp.gt.f32 	%p109, %f757, 0f42FC0000;
	mov.b32 	%r277, %f756;
	and.b32  	%r278, %r277, -2147483648;
	or.b32  	%r279, %r278, 1123811328;
	mov.b32 	%f758, %r279;
	selp.f32 	%f759, %f758, %f756, %p109;
	mov.f32 	%f760, 0fBF317218;
	fma.rn.f32 	%f761, %f759, %f760, %f753;
	mov.f32 	%f762, 0f3102E308;
	fma.rn.f32 	%f763, %f759, %f762, %f761;
	mul.f32 	%f764, %f763, 0f3FB8AA3B;
	add.f32 	%f765, %f759, 0f4B40007F;
	mov.b32 	%r280, %f765;
	shl.b32 	%r281, %r280, 23;
	mov.b32 	%f766, %r281;
	ex2.approx.ftz.f32 	%f767, %f764;
	mul.f32 	%f121, %f767, %f766;
	setp.eq.f32 	%p110, %f121, 0f7F800000;
	mov.f32 	%f1252, 0f7F800000;
	@%p110 bra 	$L__BB0_89;

	fma.rn.f32 	%f1252, %f121, %f120, %f121;

$L__BB0_89:
	mov.f32 	%f1182, 0f3E555555;
	cvt.rzi.f32.f32 	%f1181, %f1182;
	add.f32 	%f1180, %f1181, %f1181;
	mov.f32 	%f1179, 0f3ED55555;
	sub.f32 	%f1178, %f1179, %f1180;
	abs.f32 	%f1177, %f1178;
	setp.lt.f32 	%p111, %f115, 0f00000000;
	setp.eq.f32 	%p112, %f1177, 0f3F800000;
	and.pred  	%p5, %p111, %p112;
	setp.eq.f32 	%p113, %f115, 0f00000000;
	@%p113 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	add.f32 	%f772, %f115, %f115;
	selp.f32 	%f1254, %f772, 0f00000000, %p112;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.b32 	%r282, %f1252;
	xor.b32  	%r283, %r282, -2147483648;
	mov.b32 	%f768, %r283;
	selp.f32 	%f1254, %f768, %f1252, %p5;
	setp.geu.f32 	%p114, %f115, 0f00000000;
	@%p114 bra 	$L__BB0_94;

	mov.f32 	%f769, 0f3ED55555;
	cvt.rzi.f32.f32 	%f770, %f769;
	setp.eq.f32 	%p115, %f770, 0f3ED55555;
	@%p115 bra 	$L__BB0_94;

	mov.f32 	%f1254, 0f7FFFFFFF;

$L__BB0_94:
	add.f32 	%f773, %f119, 0f3ED55555;
	mov.b32 	%r284, %f773;
	setp.lt.s32 	%p117, %r284, 2139095040;
	@%p117 bra 	$L__BB0_99;

	setp.gtu.f32 	%p118, %f119, 0f7F800000;
	@%p118 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	add.f32 	%f1254, %f115, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	setp.neu.f32 	%p119, %f119, 0f7F800000;
	@%p119 bra 	$L__BB0_99;

	selp.f32 	%f1254, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f130, %f116;
	setp.lt.f32 	%p120, %f130, 0f00800000;
	mul.f32 	%f775, %f130, 0f4B800000;
	selp.f32 	%f776, %f775, %f130, %p120;
	selp.f32 	%f777, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r285, %f776;
	and.b32  	%r286, %r285, 8388607;
	or.b32  	%r287, %r286, 1065353216;
	mov.b32 	%f778, %r287;
	shr.u32 	%r288, %r285, 23;
	cvt.rn.f32.u32 	%f779, %r288;
	add.f32 	%f780, %f777, %f779;
	setp.gt.f32 	%p121, %f778, 0f3FB504F3;
	mul.f32 	%f781, %f778, 0f3F000000;
	add.f32 	%f782, %f780, 0f3F800000;
	selp.f32 	%f783, %f782, %f780, %p121;
	selp.f32 	%f784, %f781, %f778, %p121;
	add.f32 	%f785, %f784, 0fBF800000;
	add.f32 	%f786, %f784, 0f3F800000;
	rcp.approx.ftz.f32 	%f787, %f786;
	add.f32 	%f788, %f785, %f785;
	mul.f32 	%f789, %f788, %f787;
	mul.f32 	%f790, %f789, %f789;
	mov.f32 	%f791, 0f3C4CAF63;
	mov.f32 	%f792, 0f3B18F0FE;
	fma.rn.f32 	%f793, %f792, %f790, %f791;
	mov.f32 	%f794, 0f3DAAAABD;
	fma.rn.f32 	%f795, %f793, %f790, %f794;
	mul.rn.f32 	%f796, %f795, %f790;
	mul.rn.f32 	%f797, %f796, %f789;
	sub.f32 	%f798, %f785, %f789;
	add.f32 	%f799, %f798, %f798;
	neg.f32 	%f800, %f789;
	fma.rn.f32 	%f801, %f800, %f785, %f799;
	mul.rn.f32 	%f802, %f787, %f801;
	add.f32 	%f803, %f797, %f789;
	sub.f32 	%f804, %f789, %f803;
	add.f32 	%f805, %f797, %f804;
	add.f32 	%f806, %f802, %f805;
	add.f32 	%f807, %f803, %f806;
	sub.f32 	%f808, %f803, %f807;
	add.f32 	%f809, %f806, %f808;
	mov.f32 	%f810, 0f3F317200;
	mul.rn.f32 	%f811, %f783, %f810;
	mov.f32 	%f812, 0f35BFBE8E;
	mul.rn.f32 	%f813, %f783, %f812;
	add.f32 	%f814, %f811, %f807;
	sub.f32 	%f815, %f811, %f814;
	add.f32 	%f816, %f807, %f815;
	add.f32 	%f817, %f809, %f816;
	add.f32 	%f818, %f813, %f817;
	add.f32 	%f819, %f814, %f818;
	sub.f32 	%f820, %f814, %f819;
	add.f32 	%f821, %f818, %f820;
	mov.f32 	%f822, 0f3ED55555;
	mul.rn.f32 	%f823, %f822, %f819;
	neg.f32 	%f824, %f823;
	fma.rn.f32 	%f825, %f822, %f819, %f824;
	fma.rn.f32 	%f826, %f822, %f821, %f825;
	mov.f32 	%f827, 0f00000000;
	fma.rn.f32 	%f828, %f827, %f819, %f826;
	add.rn.f32 	%f829, %f823, %f828;
	neg.f32 	%f830, %f829;
	add.rn.f32 	%f831, %f823, %f830;
	add.rn.f32 	%f832, %f831, %f828;
	mov.b32 	%r289, %f829;
	setp.eq.s32 	%p122, %r289, 1118925336;
	add.s32 	%r290, %r289, -1;
	mov.b32 	%f833, %r290;
	add.f32 	%f834, %f832, 0f37000000;
	selp.f32 	%f131, %f834, %f832, %p122;
	selp.f32 	%f835, %f833, %f829, %p122;
	mov.f32 	%f836, 0f3FB8AA3B;
	mul.rn.f32 	%f837, %f835, %f836;
	cvt.rzi.f32.f32 	%f838, %f837;
	abs.f32 	%f839, %f838;
	setp.gt.f32 	%p123, %f839, 0f42FC0000;
	mov.b32 	%r291, %f838;
	and.b32  	%r292, %r291, -2147483648;
	or.b32  	%r293, %r292, 1123811328;
	mov.b32 	%f840, %r293;
	selp.f32 	%f841, %f840, %f838, %p123;
	mov.f32 	%f842, 0fBF317218;
	fma.rn.f32 	%f843, %f841, %f842, %f835;
	mov.f32 	%f844, 0f3102E308;
	fma.rn.f32 	%f845, %f841, %f844, %f843;
	mul.f32 	%f846, %f845, 0f3FB8AA3B;
	add.f32 	%f847, %f841, 0f4B40007F;
	mov.b32 	%r294, %f847;
	shl.b32 	%r295, %r294, 23;
	mov.b32 	%f848, %r295;
	ex2.approx.ftz.f32 	%f849, %f846;
	mul.f32 	%f132, %f849, %f848;
	setp.eq.f32 	%p124, %f132, 0f7F800000;
	mov.f32 	%f1255, 0f7F800000;
	@%p124 bra 	$L__BB0_101;

	fma.rn.f32 	%f1255, %f132, %f131, %f132;

$L__BB0_101:
	setp.lt.f32 	%p125, %f116, 0f00000000;
	and.pred  	%p6, %p125, %p112;
	setp.eq.f32 	%p127, %f116, 0f00000000;
	@%p127 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f854, %f116, %f116;
	selp.f32 	%f1257, %f854, 0f00000000, %p112;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r296, %f1255;
	xor.b32  	%r297, %r296, -2147483648;
	mov.b32 	%f850, %r297;
	selp.f32 	%f1257, %f850, %f1255, %p6;
	setp.geu.f32 	%p128, %f116, 0f00000000;
	@%p128 bra 	$L__BB0_106;

	mov.f32 	%f851, 0f3ED55555;
	cvt.rzi.f32.f32 	%f852, %f851;
	setp.eq.f32 	%p129, %f852, 0f3ED55555;
	@%p129 bra 	$L__BB0_106;

	mov.f32 	%f1257, 0f7FFFFFFF;

$L__BB0_106:
	mov.f32 	%f1211, 0f00000000;
	max.f32 	%f1210, %f1211, %f688;
	abs.f32 	%f1209, %f1210;
	add.f32 	%f855, %f1209, 0f3ED55555;
	mov.b32 	%r298, %f855;
	setp.lt.s32 	%p131, %r298, 2139095040;
	@%p131 bra 	$L__BB0_111;

	mov.f32 	%f1214, 0f00000000;
	max.f32 	%f1213, %f1214, %f688;
	abs.f32 	%f1212, %f1213;
	setp.gtu.f32 	%p132, %f1212, 0f7F800000;
	@%p132 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1257, %f116, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	mov.f32 	%f1217, 0f00000000;
	max.f32 	%f1216, %f1217, %f688;
	abs.f32 	%f1215, %f1216;
	setp.neu.f32 	%p133, %f1215, 0f7F800000;
	@%p133 bra 	$L__BB0_111;

	selp.f32 	%f1257, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	abs.f32 	%f141, %f117;
	setp.lt.f32 	%p134, %f141, 0f00800000;
	mul.f32 	%f857, %f141, 0f4B800000;
	selp.f32 	%f858, %f857, %f141, %p134;
	selp.f32 	%f859, 0fC3170000, 0fC2FE0000, %p134;
	mov.b32 	%r299, %f858;
	and.b32  	%r300, %r299, 8388607;
	or.b32  	%r301, %r300, 1065353216;
	mov.b32 	%f860, %r301;
	shr.u32 	%r302, %r299, 23;
	cvt.rn.f32.u32 	%f861, %r302;
	add.f32 	%f862, %f859, %f861;
	setp.gt.f32 	%p135, %f860, 0f3FB504F3;
	mul.f32 	%f863, %f860, 0f3F000000;
	add.f32 	%f864, %f862, 0f3F800000;
	selp.f32 	%f865, %f864, %f862, %p135;
	selp.f32 	%f866, %f863, %f860, %p135;
	add.f32 	%f867, %f866, 0fBF800000;
	add.f32 	%f868, %f866, 0f3F800000;
	rcp.approx.ftz.f32 	%f869, %f868;
	add.f32 	%f870, %f867, %f867;
	mul.f32 	%f871, %f870, %f869;
	mul.f32 	%f872, %f871, %f871;
	mov.f32 	%f873, 0f3C4CAF63;
	mov.f32 	%f874, 0f3B18F0FE;
	fma.rn.f32 	%f875, %f874, %f872, %f873;
	mov.f32 	%f876, 0f3DAAAABD;
	fma.rn.f32 	%f877, %f875, %f872, %f876;
	mul.rn.f32 	%f878, %f877, %f872;
	mul.rn.f32 	%f879, %f878, %f871;
	sub.f32 	%f880, %f867, %f871;
	add.f32 	%f881, %f880, %f880;
	neg.f32 	%f882, %f871;
	fma.rn.f32 	%f883, %f882, %f867, %f881;
	mul.rn.f32 	%f884, %f869, %f883;
	add.f32 	%f885, %f879, %f871;
	sub.f32 	%f886, %f871, %f885;
	add.f32 	%f887, %f879, %f886;
	add.f32 	%f888, %f884, %f887;
	add.f32 	%f889, %f885, %f888;
	sub.f32 	%f890, %f885, %f889;
	add.f32 	%f891, %f888, %f890;
	mov.f32 	%f892, 0f3F317200;
	mul.rn.f32 	%f893, %f865, %f892;
	mov.f32 	%f894, 0f35BFBE8E;
	mul.rn.f32 	%f895, %f865, %f894;
	add.f32 	%f896, %f893, %f889;
	sub.f32 	%f897, %f893, %f896;
	add.f32 	%f898, %f889, %f897;
	add.f32 	%f899, %f891, %f898;
	add.f32 	%f900, %f895, %f899;
	add.f32 	%f901, %f896, %f900;
	sub.f32 	%f902, %f896, %f901;
	add.f32 	%f903, %f900, %f902;
	mov.f32 	%f904, 0f3ED55555;
	mul.rn.f32 	%f905, %f904, %f901;
	neg.f32 	%f906, %f905;
	fma.rn.f32 	%f907, %f904, %f901, %f906;
	fma.rn.f32 	%f908, %f904, %f903, %f907;
	mov.f32 	%f909, 0f00000000;
	fma.rn.f32 	%f910, %f909, %f901, %f908;
	add.rn.f32 	%f911, %f905, %f910;
	neg.f32 	%f912, %f911;
	add.rn.f32 	%f913, %f905, %f912;
	add.rn.f32 	%f914, %f913, %f910;
	mov.b32 	%r303, %f911;
	setp.eq.s32 	%p136, %r303, 1118925336;
	add.s32 	%r304, %r303, -1;
	mov.b32 	%f915, %r304;
	add.f32 	%f916, %f914, 0f37000000;
	selp.f32 	%f142, %f916, %f914, %p136;
	selp.f32 	%f917, %f915, %f911, %p136;
	mov.f32 	%f918, 0f3FB8AA3B;
	mul.rn.f32 	%f919, %f917, %f918;
	cvt.rzi.f32.f32 	%f920, %f919;
	abs.f32 	%f921, %f920;
	setp.gt.f32 	%p137, %f921, 0f42FC0000;
	mov.b32 	%r305, %f920;
	and.b32  	%r306, %r305, -2147483648;
	or.b32  	%r307, %r306, 1123811328;
	mov.b32 	%f922, %r307;
	selp.f32 	%f923, %f922, %f920, %p137;
	mov.f32 	%f924, 0fBF317218;
	fma.rn.f32 	%f925, %f923, %f924, %f917;
	mov.f32 	%f926, 0f3102E308;
	fma.rn.f32 	%f927, %f923, %f926, %f925;
	mul.f32 	%f928, %f927, 0f3FB8AA3B;
	add.f32 	%f929, %f923, 0f4B40007F;
	mov.b32 	%r308, %f929;
	shl.b32 	%r309, %r308, 23;
	mov.b32 	%f930, %r309;
	ex2.approx.ftz.f32 	%f931, %f928;
	mul.f32 	%f143, %f931, %f930;
	setp.eq.f32 	%p138, %f143, 0f7F800000;
	mov.f32 	%f1258, 0f7F800000;
	@%p138 bra 	$L__BB0_113;

	fma.rn.f32 	%f1258, %f143, %f142, %f143;

$L__BB0_113:
	setp.lt.f32 	%p139, %f117, 0f00000000;
	and.pred  	%p7, %p139, %p112;
	setp.eq.f32 	%p141, %f117, 0f00000000;
	@%p141 bra 	$L__BB0_117;
	bra.uni 	$L__BB0_114;

$L__BB0_117:
	add.f32 	%f936, %f117, %f117;
	selp.f32 	%f1260, %f936, 0f00000000, %p112;
	bra.uni 	$L__BB0_118;

$L__BB0_114:
	mov.b32 	%r310, %f1258;
	xor.b32  	%r311, %r310, -2147483648;
	mov.b32 	%f932, %r311;
	selp.f32 	%f1260, %f932, %f1258, %p7;
	setp.geu.f32 	%p142, %f117, 0f00000000;
	@%p142 bra 	$L__BB0_118;

	mov.f32 	%f933, 0f3ED55555;
	cvt.rzi.f32.f32 	%f934, %f933;
	setp.eq.f32 	%p143, %f934, 0f3ED55555;
	@%p143 bra 	$L__BB0_118;

	mov.f32 	%f1260, 0f7FFFFFFF;

$L__BB0_118:
	mov.f32 	%f1220, 0f00000000;
	max.f32 	%f1219, %f1220, %f689;
	abs.f32 	%f1218, %f1219;
	add.f32 	%f937, %f1218, 0f3ED55555;
	mov.b32 	%r312, %f937;
	setp.lt.s32 	%p145, %r312, 2139095040;
	@%p145 bra 	$L__BB0_123;

	mov.f32 	%f1223, 0f00000000;
	max.f32 	%f1222, %f1223, %f689;
	abs.f32 	%f1221, %f1222;
	setp.gtu.f32 	%p146, %f1221, 0f7F800000;
	@%p146 bra 	$L__BB0_122;
	bra.uni 	$L__BB0_120;

$L__BB0_122:
	add.f32 	%f1260, %f117, 0f3ED55555;
	bra.uni 	$L__BB0_123;

$L__BB0_120:
	mov.f32 	%f1226, 0f00000000;
	max.f32 	%f1225, %f1226, %f689;
	abs.f32 	%f1224, %f1225;
	setp.neu.f32 	%p147, %f1224, 0f7F800000;
	@%p147 bra 	$L__BB0_123;

	selp.f32 	%f1260, 0fFF800000, 0f7F800000, %p7;

$L__BB0_123:
	ld.const.u64 	%rd152, [params+144];
	cvta.to.global.u64 	%rd151, %rd152;
	ld.const.u32 	%r371, [params+136];
	mad.lo.s32 	%r370, %r371, %r4, %r3;
	cvt.u64.u32 	%rd150, %r370;
	fma.rn.f32 	%f938, %f1254, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p148, %f115, 0f3F800000;
	mov.f32 	%f939, 0f3F800000;
	selp.f32 	%f940, 0f3F7FFFFF, %f938, %p148;
	mul.f32 	%f941, %f115, 0f414EB852;
	setp.lt.f32 	%p149, %f115, 0f3B4D2E1C;
	selp.f32 	%f942, %f941, %f940, %p149;
	fma.rn.f32 	%f943, %f1257, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p150, %f116, 0f3F800000;
	selp.f32 	%f944, 0f3F7FFFFF, %f943, %p150;
	mul.f32 	%f945, %f116, 0f414EB852;
	setp.lt.f32 	%p151, %f116, 0f3B4D2E1C;
	selp.f32 	%f946, %f945, %f944, %p151;
	fma.rn.f32 	%f947, %f1260, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p152, %f117, 0f3F800000;
	selp.f32 	%f948, 0f3F7FFFFF, %f947, %p152;
	mul.f32 	%f949, %f117, 0f414EB852;
	setp.lt.f32 	%p153, %f117, 0f3B4D2E1C;
	selp.f32 	%f950, %f949, %f948, %p153;
	min.f32 	%f951, %f942, %f939;
	mov.f32 	%f952, 0f00000000;
	max.f32 	%f953, %f952, %f951;
	mul.f32 	%f954, %f953, 0f43800000;
	cvt.rzi.u32.f32 	%r313, %f954;
	min.u32 	%r314, %r313, 255;
	min.f32 	%f955, %f946, %f939;
	max.f32 	%f956, %f952, %f955;
	mul.f32 	%f957, %f956, 0f43800000;
	cvt.rzi.u32.f32 	%r315, %f957;
	min.u32 	%r316, %r315, 255;
	min.f32 	%f958, %f950, %f939;
	max.f32 	%f959, %f952, %f958;
	mul.f32 	%f960, %f959, 0f43800000;
	cvt.rzi.u32.f32 	%r317, %f960;
	min.u32 	%r318, %r317, 255;
	shl.b64 	%rd80, %rd150, 2;
	add.s64 	%rd81, %rd151, %rd80;
	cvt.u16.u32 	%rs19, %r318;
	cvt.u16.u32 	%rs20, %r316;
	cvt.u16.u32 	%rs21, %r314;
	mov.u16 	%rs22, 255;
	st.global.v4.u8 	[%rd81], {%rs21, %rs20, %rs19, %rs22};

$L__BB0_124:
	ld.const.u32 	%r372, [params+104];
	and.b32  	%r319, %r372, 4;
	setp.eq.s32 	%p154, %r319, 0;
	ld.const.u32 	%r387, [params+108];
	@%p154 bra 	$L__BB0_128;

	setp.eq.s32 	%p155, %r387, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r4, %r3;
	mul.wide.u32 	%rd84, %r321, 8;
	add.s64 	%rd20, %rd83, %rd84;
	@%p155 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs30, %rs31, %rs32, %rs33}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f961, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f962, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f963, %rs32;}

	// end inline asm
	add.f32 	%f964, %f64, %f961;
	add.f32 	%f965, %f65, %f962;
	add.f32 	%f966, %f66, %f963;
	mov.f32 	%f967, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f966;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f965;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f964;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f967;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs26, %rs27, %rs28, %rs29};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f971, 0f3F800000;
	mov.u32 	%r387, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f971;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f66;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f65;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f64;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs34, %rs35, %rs36, %rs37};

$L__BB0_128:
	ld.const.f32 	%f1191, [params+524];
	mul.f32 	%f1190, %f1239, %f1191;
	mul.f32 	%f152, %f1190, 0f403D3C19;
	mul.f32 	%f153, %f152, 0f3E906EBB;
	mul.f32 	%f154, %f62, 0f403D3C19;
	mul.f32 	%f155, %f154, 0f3E906EBB;
	mul.f32 	%f156, %f63, 0f403D3C19;
	mul.f32 	%f157, %f156, 0f3E906EBB;
	ld.const.u64 	%rd85, [params+256];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r323, [params+248];
	mad.lo.s32 	%r324, %r323, %r4, %r3;
	mul.wide.u32 	%rd87, %r324, 8;
	add.s64 	%rd21, %rd86, %rd87;
	setp.eq.s32 	%p156, %r387, 0;
	@%p156 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs45, %rs46, %rs47, %rs48}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f972, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f973, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f974, %rs47;}

	// end inline asm
	add.f32 	%f975, %f153, %f972;
	add.f32 	%f976, %f155, %f973;
	add.f32 	%f977, %f157, %f974;
	mov.f32 	%f978, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f977;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f976;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f975;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f978;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs41, %rs42, %rs43, %rs44};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f982, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f982;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f155;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f153;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs49, %rs50, %rs51, %rs52};

$L__BB0_131:
	mul.f32 	%f983, %f201, 0fBEFA2A1C;
	mul.f32 	%f158, %f152, %f983;
	mul.f32 	%f159, %f154, %f983;
	mul.f32 	%f160, %f156, %f983;
	ld.const.u64 	%rd88, [params+272];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r325, [params+264];
	mad.lo.s32 	%r326, %r325, %r4, %r3;
	mul.wide.u32 	%rd90, %r326, 8;
	add.s64 	%rd22, %rd89, %rd90;
	@%p156 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs60, %rs61, %rs62, %rs63}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f984, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f985, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f986, %rs62;}

	// end inline asm
	add.f32 	%f987, %f158, %f984;
	add.f32 	%f988, %f159, %f985;
	add.f32 	%f989, %f160, %f986;
	mov.f32 	%f990, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f989;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f988;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f987;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f990;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs56, %rs57, %rs58, %rs59};
	bra.uni 	$L__BB0_134;

$L__BB0_133:
	mov.f32 	%f994, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f994;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f160;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f159;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f158;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs64, %rs65, %rs66, %rs67};

$L__BB0_134:
	mul.f32 	%f995, %f202, 0fBEFA2A1C;
	mul.f32 	%f161, %f152, %f995;
	mul.f32 	%f162, %f154, %f995;
	mul.f32 	%f163, %f156, %f995;
	ld.const.u64 	%rd91, [params+288];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r327, [params+280];
	mad.lo.s32 	%r328, %r327, %r4, %r3;
	mul.wide.u32 	%rd93, %r328, 8;
	add.s64 	%rd23, %rd92, %rd93;
	@%p156 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs75, %rs76, %rs77, %rs78}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f997, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f998, %rs77;}

	// end inline asm
	add.f32 	%f999, %f161, %f996;
	add.f32 	%f1000, %f162, %f997;
	add.f32 	%f1001, %f163, %f998;
	mov.f32 	%f1002, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1001;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1000;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1002;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs71, %rs72, %rs73, %rs74};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1006, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1006;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f163;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f162;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f161;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs79, %rs80, %rs81, %rs82};

$L__BB0_137:
	mul.f32 	%f1007, %f200, 0fBEFA2A1C;
	mul.f32 	%f164, %f152, %f1007;
	mul.f32 	%f165, %f154, %f1007;
	mul.f32 	%f166, %f156, %f1007;
	ld.const.u64 	%rd94, [params+304];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r329, [params+296];
	mad.lo.s32 	%r330, %r329, %r4, %r3;
	mul.wide.u32 	%rd96, %r330, 8;
	add.s64 	%rd24, %rd95, %rd96;
	@%p156 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs90, %rs91, %rs92, %rs93}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1008, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1009, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1010, %rs92;}

	// end inline asm
	add.f32 	%f1011, %f164, %f1008;
	add.f32 	%f1012, %f165, %f1009;
	add.f32 	%f1013, %f166, %f1010;
	mov.f32 	%f1014, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1013;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1012;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1011;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1014;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs86, %rs87, %rs88, %rs89};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1018, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1018;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f166;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f165;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f164;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs94, %rs95, %rs96, %rs97};

$L__BB0_140:
	mul.f32 	%f1019, %f200, %f201;
	mul.f32 	%f1020, %f1019, 0f3F8BD8A1;
	mul.f32 	%f167, %f152, %f1020;
	mul.f32 	%f168, %f154, %f1020;
	mul.f32 	%f169, %f156, %f1020;
	ld.const.u64 	%rd97, [params+320];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r331, [params+312];
	mad.lo.s32 	%r332, %r331, %r4, %r3;
	mul.wide.u32 	%rd99, %r332, 8;
	add.s64 	%rd25, %rd98, %rd99;
	@%p156 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs105, %rs106, %rs107, %rs108}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1021, %rs105;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1022, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1023, %rs107;}

	// end inline asm
	add.f32 	%f1024, %f167, %f1021;
	add.f32 	%f1025, %f168, %f1022;
	add.f32 	%f1026, %f169, %f1023;
	mov.f32 	%f1027, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs102, %f1025;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs101, %f1024;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1027;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs101, %rs102, %rs103, %rs104};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1031, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f169;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs110, %f168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs109, %f167;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs109, %rs110, %rs111, %rs112};

$L__BB0_143:
	mul.f32 	%f1032, %f201, %f202;
	mul.f32 	%f1033, %f1032, 0f3F8BD8A1;
	mul.f32 	%f170, %f152, %f1033;
	mul.f32 	%f171, %f154, %f1033;
	mul.f32 	%f172, %f156, %f1033;
	ld.const.u64 	%rd100, [params+336];
	cvta.to.global.u64 	%rd101, %rd100;
	ld.const.u32 	%r333, [params+328];
	mad.lo.s32 	%r334, %r333, %r4, %r3;
	mul.wide.u32 	%rd102, %r334, 8;
	add.s64 	%rd26, %rd101, %rd102;
	@%p156 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs120, %rs121, %rs122, %rs123}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1034, %rs120;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1035, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1036, %rs122;}

	// end inline asm
	add.f32 	%f1037, %f170, %f1034;
	add.f32 	%f1038, %f171, %f1035;
	add.f32 	%f1039, %f172, %f1036;
	mov.f32 	%f1040, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1039;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs117, %f1038;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs116, %f1037;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1040;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs116, %rs117, %rs118, %rs119};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1044, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1044;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f172;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs125, %f171;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs124, %f170;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs124, %rs125, %rs126, %rs127};

$L__BB0_146:
	fma.rn.f32 	%f1045, %f202, %f202, 0fBEAAAAAB;
	mul.f32 	%f1046, %f1045, 0f3F723881;
	mul.f32 	%f173, %f152, %f1046;
	mul.f32 	%f174, %f154, %f1046;
	mul.f32 	%f175, %f156, %f1046;
	ld.const.u64 	%rd103, [params+352];
	cvta.to.global.u64 	%rd104, %rd103;
	ld.const.u32 	%r335, [params+344];
	mad.lo.s32 	%r336, %r335, %r4, %r3;
	mul.wide.u32 	%rd105, %r336, 8;
	add.s64 	%rd27, %rd104, %rd105;
	@%p156 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs135, %rs136, %rs137, %rs138}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1047, %rs135;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1048, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1049, %rs137;}

	// end inline asm
	add.f32 	%f1050, %f173, %f1047;
	add.f32 	%f1051, %f174, %f1048;
	add.f32 	%f1052, %f175, %f1049;
	mov.f32 	%f1053, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1052;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs132, %f1051;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs131, %f1050;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1053;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs131, %rs132, %rs133, %rs134};
	bra.uni 	$L__BB0_149;

$L__BB0_148:
	mov.f32 	%f1057, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1057;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f175;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs140, %f174;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs139, %f173;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs139, %rs140, %rs141, %rs142};

$L__BB0_149:
	mul.f32 	%f1058, %f200, %f202;
	mul.f32 	%f1059, %f1058, 0f3F8BD8A1;
	mul.f32 	%f176, %f152, %f1059;
	mul.f32 	%f177, %f154, %f1059;
	mul.f32 	%f178, %f156, %f1059;
	ld.const.u64 	%rd106, [params+368];
	cvta.to.global.u64 	%rd107, %rd106;
	ld.const.u32 	%r337, [params+360];
	mad.lo.s32 	%r338, %r337, %r4, %r3;
	mul.wide.u32 	%rd108, %r338, 8;
	add.s64 	%rd28, %rd107, %rd108;
	@%p156 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs150, %rs151, %rs152, %rs153}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1060, %rs150;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1061, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1062, %rs152;}

	// end inline asm
	add.f32 	%f1063, %f176, %f1060;
	add.f32 	%f1064, %f177, %f1061;
	add.f32 	%f1065, %f178, %f1062;
	mov.f32 	%f1066, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1065;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs147, %f1064;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs146, %f1063;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1066;}

	// end inline asm
	st.global.v4.u16 	[%rd28], {%rs146, %rs147, %rs148, %rs149};
	bra.uni 	$L__BB0_152;

$L__BB0_151:
	mov.f32 	%f1070, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1070;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f178;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs155, %f177;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs154, %f176;}

	// end inline asm
	st.global.v4.u16 	[%rd28], {%rs154, %rs155, %rs156, %rs157};

$L__BB0_152:
	mul.f32 	%f1071, %f201, %f201;
	mul.f32 	%f1072, %f200, %f200;
	sub.f32 	%f1073, %f1072, %f1071;
	mul.f32 	%f1074, %f1073, 0f3F0BD8A1;
	mul.f32 	%f179, %f152, %f1074;
	mul.f32 	%f180, %f154, %f1074;
	mul.f32 	%f181, %f156, %f1074;
	ld.const.u64 	%rd109, [params+384];
	cvta.to.global.u64 	%rd110, %rd109;
	ld.const.u32 	%r339, [params+376];
	mad.lo.s32 	%r340, %r339, %r4, %r3;
	mul.wide.u32 	%rd111, %r340, 8;
	add.s64 	%rd29, %rd110, %rd111;
	@%p156 bra 	$L__BB0_154;

	ld.global.v4.u16 	{%rs165, %rs166, %rs167, %rs168}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1075, %rs165;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1076, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1077, %rs167;}

	// end inline asm
	add.f32 	%f1078, %f179, %f1075;
	add.f32 	%f1079, %f180, %f1076;
	add.f32 	%f1080, %f181, %f1077;
	mov.f32 	%f1081, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1080;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs162, %f1079;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs161, %f1078;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1081;}

	// end inline asm
	st.global.v4.u16 	[%rd29], {%rs161, %rs162, %rs163, %rs164};
	bra.uni 	$L__BB0_190;

$L__BB0_154:
	mov.f32 	%f1085, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1085;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f181;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs170, %f180;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs169, %f179;}

	// end inline asm
	st.global.v4.u16 	[%rd29], {%rs169, %rs170, %rs171, %rs172};

$L__BB0_190:
	ret;

}