//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<201>;
	.reg .b16 	%rs<177>;
	.reg .f32 	%f<1359>;
	.reg .b32 	%r<470>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<127>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r62), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r63), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+616];
	abs.s32 	%r4, %r3;
	ld.const.u32 	%r5, [params+540];
	ld.const.u64 	%rd34, [params+400];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r68, [params+392];
	mad.lo.s32 	%r69, %r68, %r63, %r62;
	mul.wide.u32 	%rd36, %r69, 4;
	add.s64 	%rd2, %rd35, %rd36;
	ld.global.v2.u8 	{%rs7, %rs176}, [%rd2];
	or.b16  	%rs9, %rs7, %rs176;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p10, %rs10, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs175, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs175, [%rd2+2];
	setp.eq.s16 	%p11, %rs175, 0;
	mov.f32 	%f1278, 0f00000000;
	mov.u16 	%rs176, 0;
	mov.f32 	%f1279, %f1278;
	mov.f32 	%f1280, %f1278;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f257, %rs7;
	div.rn.f32 	%f258, %f257, 0f437F0000;
	fma.rn.f32 	%f259, %f258, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs176, 255;
	cvt.rn.f32.u16 	%f260, %rs13;
	div.rn.f32 	%f261, %f260, 0f437F0000;
	fma.rn.f32 	%f262, %f261, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f263, %rs175;
	div.rn.f32 	%f264, %f263, 0f437F0000;
	fma.rn.f32 	%f265, %f264, 0f40000000, 0fBF800000;
	mul.f32 	%f266, %f262, %f262;
	fma.rn.f32 	%f267, %f259, %f259, %f266;
	fma.rn.f32 	%f268, %f265, %f265, %f267;
	sqrt.rn.f32 	%f269, %f268;
	rcp.rn.f32 	%f270, %f269;
	mul.f32 	%f1280, %f270, %f265;
	mul.f32 	%f1279, %f270, %f262;
	mul.f32 	%f1278, %f259, %f270;

$L__BB0_4:
	ld.const.v2.u32 	{%r70, %r71}, [params];
	add.s32 	%r6, %r70, %r62;
	add.s32 	%r7, %r71, %r63;
	setp.eq.f32 	%p12, %f1278, 0f00000000;
	setp.eq.f32 	%p13, %f1279, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1280, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_160;
	bra.uni 	$L__BB0_5;

$L__BB0_160:
	ld.const.u32 	%r59, [params+104];
	and.b32  	%r432, %r59, 1;
	setp.eq.b32 	%p189, %r432, 1;
	mov.pred 	%p190, 0;
	xor.pred  	%p191, %p189, %p190;
	not.pred 	%p192, %p191;
	@%p192 bra 	$L__BB0_162;

	ld.const.u64 	%rd97, [params+144];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r433, [params+136];
	mad.lo.s32 	%r434, %r433, %r7, %r6;
	mul.wide.u32 	%rd99, %r434, 4;
	add.s64 	%rd100, %rd98, %rd99;
	mov.u16 	%rs97, 0;
	st.global.v4.u8 	[%rd100], {%rs97, %rs97, %rs97, %rs97};

$L__BB0_162:
	and.b32  	%r435, %r59, 8;
	setp.eq.s32 	%p193, %r435, 0;
	@%p193 bra 	$L__BB0_164;

	ld.const.u64 	%rd101, [params+192];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r436, [params+184];
	mad.lo.s32 	%r437, %r436, %r7, %r6;
	mov.f32 	%f1224, 0f00000000;
	cvt.rzi.u32.f32 	%r438, %f1224;
	mul.wide.u32 	%rd103, %r437, 2;
	add.s64 	%rd104, %rd102, %rd103;
	mov.u16 	%rs98, 0;
	cvt.u16.u32 	%rs99, %r438;
	st.global.v2.u8 	[%rd104], {%rs99, %rs98};

$L__BB0_164:
	and.b32  	%r439, %r59, 4;
	setp.eq.s32 	%p194, %r439, 0;
	ld.const.u32 	%r469, [params+108];
	@%p194 bra 	$L__BB0_168;

	setp.eq.s32 	%p195, %r469, 0;
	ld.const.u64 	%rd105, [params+224];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r440, [params+216];
	mad.lo.s32 	%r441, %r440, %r7, %r6;
	mul.wide.u32 	%rd107, %r441, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p195 bra 	$L__BB0_167;

	ld.global.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1225, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1226, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1227, %rs108;}

	// end inline asm
	add.f32 	%f1228, %f1225, 0f00000000;
	add.f32 	%f1229, %f1226, 0f00000000;
	add.f32 	%f1230, %f1227, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1230;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1229;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1228;}

	// end inline asm
	mov.u16 	%rs110, 0;
	st.global.v4.u16 	[%rd28], {%rs103, %rs104, %rs105, %rs110};
	bra.uni 	$L__BB0_168;

$L__BB0_5:
	ld.const.u64 	%rd37, [params+432];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r75, [params+424];
	mad.lo.s32 	%r76, %r75, %r63, %r62;
	mul.wide.u32 	%rd39, %r76, 12;
	add.s64 	%rd40, %rd38, %rd39;
	ld.global.f32 	%f10, [%rd40];
	mul.f32 	%f277, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd40+4];
	mul.f32 	%f278, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd40+8];
	mul.f32 	%f279, %f12, 0f3456BF95;
	abs.f32 	%f13, %f1278;
	div.rn.f32 	%f280, %f277, %f13;
	abs.f32 	%f281, %f1279;
	div.rn.f32 	%f282, %f278, %f281;
	abs.f32 	%f14, %f1280;
	div.rn.f32 	%f283, %f279, %f14;
	abs.f32 	%f284, %f280;
	abs.f32 	%f285, %f282;
	abs.f32 	%f286, %f283;
	mov.f32 	%f287, 0f38D1B717;
	max.f32 	%f288, %f284, %f287;
	max.f32 	%f289, %f285, %f287;
	max.f32 	%f290, %f286, %f287;
	fma.rn.f32 	%f15, %f1278, %f288, %f10;
	fma.rn.f32 	%f16, %f1279, %f289, %f11;
	fma.rn.f32 	%f17, %f1280, %f290, %f12;
	ld.const.u64 	%rd41, [params+128];
	cvta.to.global.u64 	%rd42, %rd41;
	ld.const.u32 	%r77, [params+120];
	mad.lo.s32 	%r78, %r77, %r63, %r62;
	mul.wide.u32 	%rd43, %r78, 4;
	add.s64 	%rd44, %rd42, %rd43;
	ld.global.u32 	%r460, [%rd44];
	setp.lt.s32 	%p18, %r4, 1;
	mov.pred 	%p17, 0;
	mov.u32 	%r456, 0;
	mov.f32 	%f1290, 0f00000000;
	mov.f32 	%f1291, %f1290;
	mov.f32 	%f1292, %f1290;
	mov.f32 	%f1293, %f1290;
	mov.f32 	%f1294, %f1290;
	mov.f32 	%f1295, %f1290;
	mov.pred 	%p200, %p17;
	@%p18 bra 	$L__BB0_25;

	ld.const.f32 	%f18, [params+620];
	ld.const.u64 	%rd45, [params+624];
	cvta.to.global.u64 	%rd3, %rd45;
	ld.const.u64 	%rd46, [params+640];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r81, [params+632];
	and.b32  	%r82, %r63, 255;
	and.b32  	%r83, %r62, 255;
	mad.lo.s32 	%r84, %r81, %r82, %r83;
	mul.wide.u32 	%rd48, %r84, 3;
	add.s64 	%rd4, %rd47, %rd48;
	ld.const.f32 	%f19, [params+660];
	mul.f32 	%f20, %f15, 0f3456BF95;
	mul.f32 	%f21, %f16, 0f3456BF95;
	mul.f32 	%f22, %f17, 0f3456BF95;
	ld.const.u64 	%rd5, [params+96];
	abs.f32 	%f424, %f21;
	abs.f32 	%f425, %f20;
	max.f32 	%f426, %f425, %f424;
	abs.f32 	%f427, %f22;
	max.f32 	%f428, %f426, %f427;
	mov.u32 	%r453, %r456;

$L__BB0_7:
	shl.b32 	%r85, %r453, 1;
	mul.wide.s32 	%rd49, %r85, 12;
	add.s64 	%rd6, %rd3, %rd49;
	ld.global.f32 	%f297, [%rd6];
	sub.f32 	%f298, %f297, %f10;
	ld.global.f32 	%f299, [%rd6+4];
	sub.f32 	%f300, %f299, %f11;
	ld.global.f32 	%f301, [%rd6+8];
	sub.f32 	%f302, %f301, %f12;
	mul.f32 	%f303, %f300, %f300;
	fma.rn.f32 	%f304, %f298, %f298, %f303;
	fma.rn.f32 	%f305, %f302, %f302, %f304;
	sqrt.rn.f32 	%f29, %f305;
	rcp.rn.f32 	%f306, %f29;
	mul.f32 	%f30, %f298, %f306;
	mul.f32 	%f31, %f300, %f306;
	mul.f32 	%f32, %f302, %f306;
	mul.f32 	%f307, %f1279, %f31;
	fma.rn.f32 	%f308, %f1278, %f30, %f307;
	fma.rn.f32 	%f33, %f1280, %f32, %f308;
	setp.leu.f32 	%p19, %f33, 0f00000000;
	@%p19 bra 	$L__BB0_24;

	setp.ne.s32 	%p21, %r5, 0;
	mul.f32 	%f309, %f29, %f29;
	div.rn.f32 	%f34, %f18, %f309;
	ld.global.u8 	%rs15, [%rd4];
	cvt.rn.f32.u16 	%f310, %rs15;
	div.rn.f32 	%f311, %f310, 0fC37F0000;
	fma.rn.f32 	%f312, %f311, 0f3F333333, 0f3F800000;
	setp.gt.f32 	%p22, %f34, %f312;
	and.pred  	%p23, %p21, %p22;
	mov.pred 	%p200, -1;
	@%p23 bra 	$L__BB0_25;

	mul.f32 	%f35, %f29, %f19;
	mov.f32 	%f317, 0f40800000;
	abs.f32 	%f37, %f35;
	setp.lt.f32 	%p24, %f37, 0f00800000;
	mul.f32 	%f319, %f37, 0f4B800000;
	selp.f32 	%f320, %f319, %f37, %p24;
	selp.f32 	%f321, 0fC3170000, 0fC2FE0000, %p24;
	mov.b32 	%r86, %f320;
	and.b32  	%r87, %r86, 8388607;
	or.b32  	%r88, %r87, 1065353216;
	mov.b32 	%f322, %r88;
	shr.u32 	%r89, %r86, 23;
	cvt.rn.f32.u32 	%f323, %r89;
	add.f32 	%f324, %f321, %f323;
	setp.gt.f32 	%p25, %f322, 0f3FB504F3;
	mul.f32 	%f325, %f322, 0f3F000000;
	add.f32 	%f326, %f324, 0f3F800000;
	selp.f32 	%f327, %f326, %f324, %p25;
	selp.f32 	%f328, %f325, %f322, %p25;
	add.f32 	%f329, %f328, 0fBF800000;
	add.f32 	%f330, %f328, 0f3F800000;
	rcp.approx.ftz.f32 	%f331, %f330;
	add.f32 	%f332, %f329, %f329;
	mul.f32 	%f333, %f332, %f331;
	mul.f32 	%f334, %f333, %f333;
	mov.f32 	%f335, 0f3C4CAF63;
	mov.f32 	%f336, 0f3B18F0FE;
	fma.rn.f32 	%f337, %f336, %f334, %f335;
	mov.f32 	%f338, 0f3DAAAABD;
	fma.rn.f32 	%f339, %f337, %f334, %f338;
	mul.rn.f32 	%f340, %f339, %f334;
	mul.rn.f32 	%f341, %f340, %f333;
	sub.f32 	%f342, %f329, %f333;
	add.f32 	%f343, %f342, %f342;
	neg.f32 	%f344, %f333;
	fma.rn.f32 	%f345, %f344, %f329, %f343;
	mul.rn.f32 	%f346, %f331, %f345;
	add.f32 	%f347, %f341, %f333;
	sub.f32 	%f348, %f333, %f347;
	add.f32 	%f349, %f341, %f348;
	add.f32 	%f350, %f346, %f349;
	add.f32 	%f351, %f347, %f350;
	sub.f32 	%f352, %f347, %f351;
	add.f32 	%f353, %f350, %f352;
	mov.f32 	%f354, 0f3F317200;
	mul.rn.f32 	%f355, %f327, %f354;
	mov.f32 	%f356, 0f35BFBE8E;
	mul.rn.f32 	%f357, %f327, %f356;
	add.f32 	%f358, %f355, %f351;
	sub.f32 	%f359, %f355, %f358;
	add.f32 	%f360, %f351, %f359;
	add.f32 	%f361, %f353, %f360;
	add.f32 	%f362, %f357, %f361;
	add.f32 	%f363, %f358, %f362;
	sub.f32 	%f364, %f358, %f363;
	add.f32 	%f365, %f362, %f364;
	mul.rn.f32 	%f366, %f317, %f363;
	neg.f32 	%f367, %f366;
	fma.rn.f32 	%f368, %f317, %f363, %f367;
	fma.rn.f32 	%f369, %f317, %f365, %f368;
	mov.f32 	%f370, 0f00000000;
	fma.rn.f32 	%f371, %f370, %f363, %f369;
	add.rn.f32 	%f372, %f366, %f371;
	neg.f32 	%f373, %f372;
	add.rn.f32 	%f374, %f366, %f373;
	add.rn.f32 	%f375, %f374, %f371;
	mov.b32 	%r90, %f372;
	setp.eq.s32 	%p26, %r90, 1118925336;
	add.s32 	%r91, %r90, -1;
	mov.b32 	%f376, %r91;
	add.f32 	%f377, %f375, 0f37000000;
	selp.f32 	%f38, %f377, %f375, %p26;
	selp.f32 	%f378, %f376, %f372, %p26;
	mov.f32 	%f379, 0f3FB8AA3B;
	mul.rn.f32 	%f380, %f378, %f379;
	cvt.rzi.f32.f32 	%f381, %f380;
	abs.f32 	%f382, %f381;
	setp.gt.f32 	%p27, %f382, 0f42FC0000;
	mov.b32 	%r92, %f381;
	and.b32  	%r93, %r92, -2147483648;
	or.b32  	%r94, %r93, 1123811328;
	mov.b32 	%f383, %r94;
	selp.f32 	%f384, %f383, %f381, %p27;
	mov.f32 	%f385, 0fBF317218;
	fma.rn.f32 	%f386, %f384, %f385, %f378;
	mov.f32 	%f387, 0f3102E308;
	fma.rn.f32 	%f388, %f384, %f387, %f386;
	mul.f32 	%f389, %f388, 0f3FB8AA3B;
	add.f32 	%f390, %f384, 0f4B40007F;
	mov.b32 	%r95, %f390;
	shl.b32 	%r96, %r95, 23;
	mov.b32 	%f391, %r96;
	ex2.approx.ftz.f32 	%f392, %f389;
	mul.f32 	%f39, %f392, %f391;
	setp.eq.f32 	%p28, %f39, 0f7F800000;
	mov.f32 	%f1287, 0f7F800000;
	@%p28 bra 	$L__BB0_11;

	fma.rn.f32 	%f1287, %f39, %f38, %f39;

$L__BB0_11:
	mov.f32 	%f1275, 0f40000000;
	cvt.rzi.f32.f32 	%f1274, %f1275;
	add.f32 	%f1273, %f1274, %f1274;
	mov.f32 	%f1272, 0f40800000;
	sub.f32 	%f1271, %f1272, %f1273;
	abs.f32 	%f1270, %f1271;
	setp.lt.f32 	%p29, %f35, 0f00000000;
	setp.eq.f32 	%p30, %f1270, 0f3F800000;
	and.pred  	%p1, %p29, %p30;
	setp.eq.f32 	%p31, %f35, 0f00000000;
	@%p31 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_12;

$L__BB0_15:
	add.f32 	%f397, %f35, %f35;
	selp.f32 	%f1289, %f397, 0f00000000, %p30;
	bra.uni 	$L__BB0_16;

$L__BB0_12:
	mov.b32 	%r97, %f1287;
	xor.b32  	%r98, %r97, -2147483648;
	mov.b32 	%f393, %r98;
	selp.f32 	%f1289, %f393, %f1287, %p1;
	setp.geu.f32 	%p32, %f35, 0f00000000;
	@%p32 bra 	$L__BB0_16;

	mov.f32 	%f394, 0f40800000;
	cvt.rzi.f32.f32 	%f395, %f394;
	setp.eq.f32 	%p33, %f395, 0f40800000;
	@%p33 bra 	$L__BB0_16;

	mov.f32 	%f1289, 0f7FFFFFFF;

$L__BB0_16:
	add.f32 	%f398, %f37, 0f40800000;
	mov.b32 	%r99, %f398;
	setp.lt.s32 	%p35, %r99, 2139095040;
	@%p35 bra 	$L__BB0_21;

	setp.gtu.f32 	%p36, %f37, 0f7F800000;
	@%p36 bra 	$L__BB0_20;
	bra.uni 	$L__BB0_18;

$L__BB0_20:
	add.f32 	%f1289, %f35, 0f40800000;
	bra.uni 	$L__BB0_21;

$L__BB0_18:
	setp.neu.f32 	%p37, %f37, 0f7F800000;
	@%p37 bra 	$L__BB0_21;

	selp.f32 	%f1289, 0fFF800000, 0f7F800000, %p1;

$L__BB0_21:
	shl.b32 	%r451, %r453, 1;
	mul.wide.s32 	%rd121, %r451, 12;
	add.s64 	%rd120, %rd3, %rd121;
	mov.f32 	%f399, 0f3F800000;
	sub.f32 	%f400, %f399, %f1289;
	setp.eq.f32 	%p38, %f35, 0f3F800000;
	selp.f32 	%f401, 0f00000000, %f400, %p38;
	cvt.sat.f32.f32 	%f402, %f401;
	mul.f32 	%f403, %f34, %f402;
	ld.global.f32 	%f404, [%rd120+12];
	mul.f32 	%f405, %f30, %f404;
	ld.global.f32 	%f406, [%rd120+16];
	mul.f32 	%f407, %f31, %f406;
	neg.f32 	%f408, %f407;
	sub.f32 	%f409, %f408, %f405;
	ld.global.f32 	%f410, [%rd120+20];
	mul.f32 	%f411, %f32, %f410;
	sub.f32 	%f412, %f409, %f411;
	cvt.sat.f32.f32 	%f413, %f412;
	mul.f32 	%f48, %f403, %f413;
	setp.leu.f32 	%p39, %f48, 0f3727C5AC;
	@%p39 bra 	$L__BB0_23;

	cvt.sat.f32.f32 	%f423, %f33;
	mov.f32 	%f429, 0f38D1B717;
	max.f32 	%f420, %f428, %f429;
	sub.f32 	%f421, %f29, %f420;
	mov.f32 	%f422, 0f00000000;
	mov.u32 	%r136, 2;
	mov.u32 	%r138, 1;
	mov.u32 	%r139, 1065353216;
	mov.u32 	%r170, 0;
	// begin inline asm
	call(%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128,%r129,%r130,%r131),_optix_trace_typed_32,(%r170,%rd5,%f15,%f16,%f17,%f30,%f31,%f32,%f420,%f421,%f422,%r138,%r170,%r138,%r136,%r138,%r138,%r139,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170);
	// end inline asm
	mov.b32 	%f430, %r100;
	mul.f32 	%f431, %f48, 0f3EA2F983;
	mul.f32 	%f432, %f431, %f430;
	fma.rn.f32 	%f1295, %f423, %f432, %f1295;
	mul.f32 	%f433, %f33, 0f40800000;
	cvt.sat.f32.f32 	%f434, %f433;
	mul.f32 	%f435, %f434, %f432;
	fma.rn.f32 	%f1293, %f30, %f435, %f1293;
	fma.rn.f32 	%f1292, %f31, %f435, %f1292;
	fma.rn.f32 	%f1291, %f32, %f435, %f1291;
	add.f32 	%f1294, %f1294, %f435;
	add.f32 	%f1290, %f1290, %f430;

$L__BB0_23:
	add.s32 	%r456, %r456, 1;

$L__BB0_24:
	add.s32 	%r453, %r453, 1;
	setp.lt.s32 	%p41, %r453, %r4;
	mov.pred 	%p200, %p17;
	@%p41 bra 	$L__BB0_7;

$L__BB0_25:
	cvt.rn.f32.s32 	%f436, %r456;
	mov.f32 	%f437, 0f3F800000;
	max.f32 	%f438, %f436, %f437;
	div.rn.f32 	%f1337, %f1295, %f438;
	div.rn.f32 	%f1332, %f1290, %f438;
	div.rn.f32 	%f1336, %f1294, %f438;
	div.rn.f32 	%f1335, %f1293, %f438;
	div.rn.f32 	%f1334, %f1292, %f438;
	div.rn.f32 	%f1333, %f1291, %f438;
	not.pred 	%p42, %p200;
	@%p42 bra 	$L__BB0_56;

	abs.f32 	%f1277, %f1280;
	abs.f32 	%f1276, %f1278;
	setp.gt.f32 	%p43, %f1276, %f1277;
	selp.f32 	%f445, 0f00000000, %f1279, %p43;
	mov.f32 	%f1319, 0f00000000;
	neg.f32 	%f446, %f1280;
	selp.f32 	%f447, %f1278, %f446, %p43;
	neg.f32 	%f448, %f1279;
	selp.f32 	%f449, %f448, 0f00000000, %p43;
	mul.f32 	%f450, %f447, %f447;
	fma.rn.f32 	%f451, %f449, %f449, %f450;
	fma.rn.f32 	%f452, %f445, %f445, %f451;
	sqrt.rn.f32 	%f453, %f452;
	rcp.rn.f32 	%f454, %f453;
	mul.f32 	%f79, %f449, %f454;
	mul.f32 	%f80, %f447, %f454;
	mul.f32 	%f81, %f445, %f454;
	setp.lt.s32 	%p44, %r5, 1;
	mov.f32 	%f1318, %f1319;
	mov.f32 	%f1317, %f1319;
	mov.f32 	%f1316, %f1319;
	mov.f32 	%f1315, %f1319;
	mov.f32 	%f1314, %f1319;
	@%p44 bra 	$L__BB0_55;

	cvt.rn.f32.s32 	%f461, %r5;
	rcp.rn.f32 	%f82, %f461;
	mul.f32 	%f83, %f15, 0f3456BF95;
	mul.f32 	%f84, %f16, 0f3456BF95;
	mul.f32 	%f85, %f17, 0f3456BF95;
	ld.const.u64 	%rd7, [params+96];
	mul.f32 	%f462, %f1278, %f80;
	mul.f32 	%f463, %f1279, %f79;
	sub.f32 	%f86, %f463, %f462;
	mul.f32 	%f464, %f1280, %f79;
	mul.f32 	%f465, %f1278, %f81;
	sub.f32 	%f87, %f465, %f464;
	mul.f32 	%f466, %f1279, %f81;
	mul.f32 	%f467, %f1280, %f80;
	sub.f32 	%f88, %f467, %f466;
	mov.u32 	%r171, 0;
	add.s64 	%rd8, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f530, %f84;
	abs.f32 	%f531, %f83;
	max.f32 	%f532, %f531, %f530;
	abs.f32 	%f533, %f85;
	max.f32 	%f534, %f532, %f533;
	mov.u32 	%r457, %r171;

$L__BB0_28:
	cvt.rn.f32.s32 	%f95, %r457;
	mov.u32 	%r459, %r171;

$L__BB0_29:
	mad.lo.s32 	%r173, %r460, 1664525, 1013904223;
	and.b32  	%r174, %r173, 16777215;
	cvt.rn.f32.u32 	%f468, %r174;
	fma.rn.f32 	%f469, %f468, 0f33800000, %f95;
	mul.f32 	%f102, %f82, %f469;
	mad.lo.s32 	%r460, %r173, 1664525, 1013904223;
	and.b32  	%r175, %r460, 16777215;
	cvt.rn.f32.u32 	%f470, %r175;
	cvt.rn.f32.s32 	%f471, %r459;
	fma.rn.f32 	%f472, %f470, 0f33800000, %f471;
	mul.f32 	%f473, %f82, %f472;
	mul.f32 	%f474, %f102, %f102;
	mov.f32 	%f475, 0f3F800000;
	sub.f32 	%f476, %f475, %f474;
	mov.f32 	%f477, 0f00000000;
	max.f32 	%f478, %f477, %f476;
	sqrt.rn.f32 	%f103, %f478;
	mul.f32 	%f104, %f473, 0f40C90FDB;
	mul.f32 	%f479, %f104, 0f3F22F983;
	cvt.rni.s32.f32 	%r467, %f479;
	cvt.rn.f32.s32 	%f480, %r467;
	mov.f32 	%f481, 0fBFC90FDA;
	fma.rn.f32 	%f482, %f480, %f481, %f104;
	mov.f32 	%f483, 0fB3A22168;
	fma.rn.f32 	%f484, %f480, %f483, %f482;
	mov.f32 	%f485, 0fA7C234C5;
	fma.rn.f32 	%f1323, %f480, %f485, %f484;
	abs.f32 	%f106, %f104;
	setp.ltu.f32 	%p45, %f106, 0f47CE4780;
	mov.u32 	%r464, %r467;
	mov.f32 	%f1320, %f1323;
	@%p45 bra 	$L__BB0_37;

	setp.eq.f32 	%p46, %f106, 0f7F800000;
	@%p46 bra 	$L__BB0_36;
	bra.uni 	$L__BB0_31;

$L__BB0_36:
	mov.f32 	%f488, 0f00000000;
	mul.rn.f32 	%f1320, %f104, %f488;
	mov.u32 	%r464, 0;
	bra.uni 	$L__BB0_37;

$L__BB0_31:
	mov.b32 	%r21, %f104;
	bfe.u32 	%r177, %r21, 23, 8;
	add.s32 	%r22, %r177, -128;
	shl.b32 	%r178, %r21, 8;
	or.b32  	%r23, %r178, -2147483648;
	shr.u32 	%r24, %r22, 5;
	mov.u64 	%rd124, 0;
	mov.u32 	%r461, 0;
	mov.u64 	%rd122, %rd1;
	mov.u64 	%rd123, %rd51;

$L__BB0_32:
	.pragma "nounroll";
	ld.global.nc.u32 	%r179, [%rd123];
	mad.wide.u32 	%rd53, %r179, %r23, %rd124;
	shr.u64 	%rd124, %rd53, 32;
	st.local.u32 	[%rd122], %rd53;
	add.s64 	%rd123, %rd123, 4;
	add.s64 	%rd122, %rd122, 4;
	add.s32 	%r461, %r461, 1;
	setp.ne.s32 	%p47, %r461, 6;
	@%p47 bra 	$L__BB0_32;

	st.local.u32 	[%rd8], %rd124;
	mov.u32 	%r180, 4;
	sub.s32 	%r27, %r180, %r24;
	mov.u32 	%r181, 6;
	sub.s32 	%r182, %r181, %r24;
	mul.wide.s32 	%rd54, %r182, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r462, [%rd55];
	ld.local.u32 	%r463, [%rd55+-4];
	and.b32  	%r30, %r22, 31;
	setp.eq.s32 	%p48, %r30, 0;
	@%p48 bra 	$L__BB0_35;

	mov.u32 	%r183, 32;
	sub.s32 	%r184, %r183, %r30;
	shr.u32 	%r185, %r463, %r184;
	shl.b32 	%r186, %r462, %r30;
	add.s32 	%r462, %r185, %r186;
	mul.wide.s32 	%rd56, %r27, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r187, [%rd57];
	shr.u32 	%r188, %r187, %r184;
	shl.b32 	%r189, %r463, %r30;
	add.s32 	%r463, %r188, %r189;

$L__BB0_35:
	and.b32  	%r190, %r21, -2147483648;
	shr.u32 	%r191, %r463, 30;
	shl.b32 	%r192, %r462, 2;
	or.b32  	%r193, %r191, %r192;
	shr.u32 	%r194, %r193, 31;
	shr.u32 	%r195, %r462, 30;
	add.s32 	%r196, %r194, %r195;
	neg.s32 	%r197, %r196;
	setp.eq.s32 	%p49, %r190, 0;
	selp.b32 	%r464, %r196, %r197, %p49;
	setp.ne.s32 	%p50, %r194, 0;
	xor.b32  	%r198, %r190, -2147483648;
	selp.b32 	%r199, %r198, %r190, %p50;
	selp.b32 	%r200, -1, 0, %p50;
	xor.b32  	%r201, %r193, %r200;
	shl.b32 	%r202, %r463, 2;
	xor.b32  	%r203, %r202, %r200;
	cvt.u64.u32 	%rd58, %r201;
	cvt.u64.u32 	%rd59, %r203;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f486, %fd2;
	setp.eq.s32 	%p51, %r199, 0;
	neg.f32 	%f487, %f486;
	selp.f32 	%f1320, %f486, %f487, %p51;

$L__BB0_37:
	add.s32 	%r37, %r464, 1;
	and.b32  	%r38, %r37, 1;
	setp.eq.s32 	%p52, %r38, 0;
	selp.f32 	%f110, %f1320, 0f3F800000, %p52;
	mul.rn.f32 	%f111, %f1320, %f1320;
	mov.f32 	%f1321, 0fB94D4153;
	@%p52 bra 	$L__BB0_39;

	mov.f32 	%f490, 0fBAB607ED;
	mov.f32 	%f491, 0f37CBAC00;
	fma.rn.f32 	%f1321, %f491, %f111, %f490;

$L__BB0_39:
	selp.f32 	%f492, 0f3C0885E4, 0f3D2AAABB, %p52;
	fma.rn.f32 	%f493, %f1321, %f111, %f492;
	selp.f32 	%f494, 0fBE2AAAA8, 0fBEFFFFFF, %p52;
	fma.rn.f32 	%f495, %f493, %f111, %f494;
	mov.f32 	%f496, 0f00000000;
	fma.rn.f32 	%f497, %f111, %f110, %f496;
	fma.rn.f32 	%f1322, %f495, %f497, %f110;
	and.b32  	%r205, %r37, 2;
	setp.eq.s32 	%p54, %r205, 0;
	@%p54 bra 	$L__BB0_41;

	mov.f32 	%f499, 0fBF800000;
	fma.rn.f32 	%f1322, %f1322, %f499, %f496;

$L__BB0_41:
	@%p45 bra 	$L__BB0_49;

	setp.eq.f32 	%p56, %f106, 0f7F800000;
	@%p56 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_43;

$L__BB0_48:
	mov.f32 	%f502, 0f00000000;
	mul.rn.f32 	%f1323, %f104, %f502;
	mov.u32 	%r467, 0;
	bra.uni 	$L__BB0_49;

$L__BB0_43:
	mov.b32 	%r39, %f104;
	bfe.u32 	%r206, %r39, 23, 8;
	add.s32 	%r40, %r206, -128;
	shl.b32 	%r207, %r39, 8;
	or.b32  	%r41, %r207, -2147483648;
	shr.u32 	%r42, %r40, 5;
	mov.u64 	%rd125, 0;
	mov.u64 	%rd126, %rd125;

$L__BB0_44:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd125, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r208, [%rd65];
	mad.wide.u32 	%rd66, %r208, %r41, %rd126;
	shr.u64 	%rd126, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r209, %rd125;
	add.s32 	%r210, %r209, 1;
	cvt.s64.s32 	%rd125, %r210;
	setp.ne.s32 	%p57, %r210, 6;
	@%p57 bra 	$L__BB0_44;

	st.local.u32 	[%rd8], %rd126;
	mov.u32 	%r211, 4;
	sub.s32 	%r43, %r211, %r42;
	mov.u32 	%r212, 6;
	sub.s32 	%r213, %r212, %r42;
	mul.wide.s32 	%rd68, %r213, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r465, [%rd69];
	ld.local.u32 	%r466, [%rd69+-4];
	and.b32  	%r46, %r40, 31;
	setp.eq.s32 	%p58, %r46, 0;
	@%p58 bra 	$L__BB0_47;

	mov.u32 	%r214, 32;
	sub.s32 	%r215, %r214, %r46;
	shr.u32 	%r216, %r466, %r215;
	shl.b32 	%r217, %r465, %r46;
	add.s32 	%r465, %r216, %r217;
	mul.wide.s32 	%rd70, %r43, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r218, [%rd71];
	shr.u32 	%r219, %r218, %r215;
	shl.b32 	%r220, %r466, %r46;
	add.s32 	%r466, %r219, %r220;

$L__BB0_47:
	and.b32  	%r221, %r39, -2147483648;
	shr.u32 	%r222, %r466, 30;
	shl.b32 	%r223, %r465, 2;
	or.b32  	%r224, %r222, %r223;
	shr.u32 	%r225, %r224, 31;
	shr.u32 	%r226, %r465, 30;
	add.s32 	%r227, %r225, %r226;
	neg.s32 	%r228, %r227;
	setp.eq.s32 	%p59, %r221, 0;
	selp.b32 	%r467, %r227, %r228, %p59;
	setp.ne.s32 	%p60, %r225, 0;
	xor.b32  	%r229, %r221, -2147483648;
	selp.b32 	%r230, %r229, %r221, %p60;
	selp.b32 	%r231, -1, 0, %p60;
	xor.b32  	%r232, %r224, %r231;
	shl.b32 	%r233, %r466, 2;
	xor.b32  	%r234, %r233, %r231;
	cvt.u64.u32 	%rd72, %r232;
	cvt.u64.u32 	%rd73, %r234;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f500, %fd4;
	setp.eq.s32 	%p61, %r230, 0;
	neg.f32 	%f501, %f500;
	selp.f32 	%f1323, %f500, %f501, %p61;

$L__BB0_49:
	mul.f32 	%f120, %f103, %f1322;
	and.b32  	%r53, %r467, 1;
	setp.eq.s32 	%p62, %r53, 0;
	selp.f32 	%f121, %f1323, 0f3F800000, %p62;
	mul.rn.f32 	%f122, %f1323, %f1323;
	mov.f32 	%f1324, 0fB94D4153;
	@%p62 bra 	$L__BB0_51;

	mov.f32 	%f504, 0fBAB607ED;
	mov.f32 	%f505, 0f37CBAC00;
	fma.rn.f32 	%f1324, %f505, %f122, %f504;

$L__BB0_51:
	selp.f32 	%f506, 0f3C0885E4, 0f3D2AAABB, %p62;
	fma.rn.f32 	%f507, %f1324, %f122, %f506;
	selp.f32 	%f508, 0fBE2AAAA8, 0fBEFFFFFF, %p62;
	fma.rn.f32 	%f509, %f507, %f122, %f508;
	mov.f32 	%f510, 0f00000000;
	fma.rn.f32 	%f511, %f122, %f121, %f510;
	fma.rn.f32 	%f1325, %f509, %f511, %f121;
	and.b32  	%r236, %r467, 2;
	setp.eq.s32 	%p64, %r236, 0;
	@%p64 bra 	$L__BB0_53;

	mov.f32 	%f513, 0fBF800000;
	fma.rn.f32 	%f1325, %f1325, %f513, %f510;

$L__BB0_53:
	mul.f32 	%f523, %f103, %f1325;
	mul.f32 	%f524, %f79, %f523;
	mul.f32 	%f525, %f80, %f523;
	mul.f32 	%f526, %f81, %f523;
	fma.rn.f32 	%f527, %f88, %f120, %f524;
	fma.rn.f32 	%f528, %f87, %f120, %f525;
	fma.rn.f32 	%f529, %f86, %f120, %f526;
	fma.rn.f32 	%f517, %f1278, %f102, %f527;
	fma.rn.f32 	%f518, %f1279, %f102, %f528;
	fma.rn.f32 	%f519, %f1280, %f102, %f529;
	mov.f32 	%f535, 0f38D1B717;
	max.f32 	%f520, %f534, %f535;
	mov.f32 	%f521, 0f6C4ECB8F;
	mov.u32 	%r273, 2;
	mov.u32 	%r275, 1;
	mov.u32 	%r307, 0;
	// begin inline asm
	call(%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268),_optix_trace_typed_32,(%r307,%rd7,%f15,%f16,%f17,%f517,%f518,%f519,%f520,%f521,%f510,%r275,%r307,%r307,%r273,%r307,%r275,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307);
	// end inline asm
	mov.b32 	%f536, %r237;
	setp.lt.f32 	%p65, %f536, 0f00000000;
	selp.f32 	%f537, 0f00000000, %f536, %p65;
	setp.geu.f32 	%p66, %f536, 0f00000000;
	selp.f32 	%f538, 0f3F800000, 0f00000000, %p66;
	add.f32 	%f1319, %f1319, %f538;
	fma.rn.f32 	%f1316, %f517, %f537, %f1316;
	fma.rn.f32 	%f1317, %f518, %f537, %f1317;
	fma.rn.f32 	%f1318, %f519, %f537, %f1318;
	add.f32 	%f1315, %f1315, %f537;
	mul.f32 	%f539, %f1279, %f518;
	fma.rn.f32 	%f540, %f1278, %f517, %f539;
	fma.rn.f32 	%f541, %f1280, %f519, %f540;
	cvt.sat.f32.f32 	%f542, %f541;
	fma.rn.f32 	%f1314, %f542, %f537, %f1314;
	add.s32 	%r459, %r459, 1;
	setp.lt.s32 	%p67, %r459, %r5;
	@%p67 bra 	$L__BB0_29;

	add.s32 	%r457, %r457, 1;
	setp.lt.s32 	%p68, %r457, %r5;
	@%p68 bra 	$L__BB0_28;

$L__BB0_55:
	mul.lo.s32 	%r308, %r5, %r5;
	cvt.rn.f32.s32 	%f543, %r308;
	div.rn.f32 	%f544, %f1314, %f543;
	div.rn.f32 	%f1332, %f1319, %f543;
	div.rn.f32 	%f1336, %f1315, %f543;
	div.rn.f32 	%f1335, %f1316, %f543;
	div.rn.f32 	%f1334, %f1317, %f543;
	div.rn.f32 	%f1333, %f1318, %f543;
	add.f32 	%f1337, %f544, %f544;

$L__BB0_56:
	ld.const.u32 	%r452, [params+616];
	setp.lt.s32 	%p69, %r452, 0;
	selp.f32 	%f152, %f1337, %f1332, %p69;
	ld.const.u32 	%r56, [params+104];
	and.b32  	%r309, %r56, 8;
	setp.eq.s32 	%p70, %r309, 0;
	@%p70 bra 	$L__BB0_70;

	ld.const.u64 	%rd76, [params+192];
	cvta.to.global.u64 	%rd19, %rd76;
	ld.const.u32 	%r310, [params+184];
	mad.lo.s32 	%r311, %r310, %r7, %r6;
	cvt.u64.u32 	%rd20, %r311;
	mov.f32 	%f546, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f547, %f546;
	add.f32 	%f548, %f547, %f547;
	mov.f32 	%f549, 0f3EE8BA2E;
	sub.f32 	%f550, %f549, %f548;
	abs.f32 	%f153, %f550;
	abs.f32 	%f154, %f152;
	setp.lt.f32 	%p71, %f154, 0f00800000;
	mul.f32 	%f551, %f154, 0f4B800000;
	selp.f32 	%f552, %f551, %f154, %p71;
	selp.f32 	%f553, 0fC3170000, 0fC2FE0000, %p71;
	mov.b32 	%r312, %f552;
	and.b32  	%r313, %r312, 8388607;
	or.b32  	%r314, %r313, 1065353216;
	mov.b32 	%f554, %r314;
	shr.u32 	%r315, %r312, 23;
	cvt.rn.f32.u32 	%f555, %r315;
	add.f32 	%f556, %f553, %f555;
	setp.gt.f32 	%p72, %f554, 0f3FB504F3;
	mul.f32 	%f557, %f554, 0f3F000000;
	add.f32 	%f558, %f556, 0f3F800000;
	selp.f32 	%f559, %f558, %f556, %p72;
	selp.f32 	%f560, %f557, %f554, %p72;
	add.f32 	%f561, %f560, 0fBF800000;
	add.f32 	%f562, %f560, 0f3F800000;
	rcp.approx.ftz.f32 	%f563, %f562;
	add.f32 	%f564, %f561, %f561;
	mul.f32 	%f565, %f564, %f563;
	mul.f32 	%f566, %f565, %f565;
	mov.f32 	%f567, 0f3C4CAF63;
	mov.f32 	%f568, 0f3B18F0FE;
	fma.rn.f32 	%f569, %f568, %f566, %f567;
	mov.f32 	%f570, 0f3DAAAABD;
	fma.rn.f32 	%f571, %f569, %f566, %f570;
	mul.rn.f32 	%f572, %f571, %f566;
	mul.rn.f32 	%f573, %f572, %f565;
	sub.f32 	%f574, %f561, %f565;
	add.f32 	%f575, %f574, %f574;
	neg.f32 	%f576, %f565;
	fma.rn.f32 	%f577, %f576, %f561, %f575;
	mul.rn.f32 	%f578, %f563, %f577;
	add.f32 	%f579, %f573, %f565;
	sub.f32 	%f580, %f565, %f579;
	add.f32 	%f581, %f573, %f580;
	add.f32 	%f582, %f578, %f581;
	add.f32 	%f583, %f579, %f582;
	sub.f32 	%f584, %f579, %f583;
	add.f32 	%f585, %f582, %f584;
	mov.f32 	%f586, 0f3F317200;
	mul.rn.f32 	%f587, %f559, %f586;
	mov.f32 	%f588, 0f35BFBE8E;
	mul.rn.f32 	%f589, %f559, %f588;
	add.f32 	%f590, %f587, %f583;
	sub.f32 	%f591, %f587, %f590;
	add.f32 	%f592, %f583, %f591;
	add.f32 	%f593, %f585, %f592;
	add.f32 	%f594, %f589, %f593;
	add.f32 	%f595, %f590, %f594;
	sub.f32 	%f596, %f590, %f595;
	add.f32 	%f597, %f594, %f596;
	mul.rn.f32 	%f598, %f549, %f595;
	neg.f32 	%f599, %f598;
	fma.rn.f32 	%f600, %f549, %f595, %f599;
	fma.rn.f32 	%f601, %f549, %f597, %f600;
	mov.f32 	%f602, 0f00000000;
	fma.rn.f32 	%f603, %f602, %f595, %f601;
	add.rn.f32 	%f604, %f598, %f603;
	neg.f32 	%f605, %f604;
	add.rn.f32 	%f606, %f598, %f605;
	add.rn.f32 	%f607, %f606, %f603;
	mov.b32 	%r316, %f604;
	setp.eq.s32 	%p73, %r316, 1118925336;
	add.s32 	%r317, %r316, -1;
	mov.b32 	%f608, %r317;
	add.f32 	%f609, %f607, 0f37000000;
	selp.f32 	%f155, %f609, %f607, %p73;
	selp.f32 	%f610, %f608, %f604, %p73;
	mov.f32 	%f611, 0f3FB8AA3B;
	mul.rn.f32 	%f612, %f610, %f611;
	cvt.rzi.f32.f32 	%f613, %f612;
	abs.f32 	%f614, %f613;
	setp.gt.f32 	%p74, %f614, 0f42FC0000;
	mov.b32 	%r318, %f613;
	and.b32  	%r319, %r318, -2147483648;
	or.b32  	%r320, %r319, 1123811328;
	mov.b32 	%f615, %r320;
	selp.f32 	%f616, %f615, %f613, %p74;
	mov.f32 	%f617, 0fBF317218;
	fma.rn.f32 	%f618, %f616, %f617, %f610;
	mov.f32 	%f619, 0f3102E308;
	fma.rn.f32 	%f620, %f616, %f619, %f618;
	mul.f32 	%f621, %f620, 0f3FB8AA3B;
	add.f32 	%f622, %f616, 0f4B40007F;
	mov.b32 	%r321, %f622;
	shl.b32 	%r322, %r321, 23;
	mov.b32 	%f623, %r322;
	ex2.approx.ftz.f32 	%f624, %f621;
	mul.f32 	%f156, %f624, %f623;
	setp.eq.f32 	%p75, %f156, 0f7F800000;
	mov.f32 	%f1338, 0f7F800000;
	@%p75 bra 	$L__BB0_59;

	fma.rn.f32 	%f1338, %f156, %f155, %f156;

$L__BB0_59:
	setp.lt.f32 	%p76, %f152, 0f00000000;
	setp.eq.f32 	%p77, %f153, 0f3F800000;
	and.pred  	%p3, %p76, %p77;
	setp.eq.f32 	%p78, %f152, 0f00000000;
	@%p78 bra 	$L__BB0_63;
	bra.uni 	$L__BB0_60;

$L__BB0_63:
	add.f32 	%f629, %f152, %f152;
	selp.f32 	%f1340, %f629, 0f00000000, %p77;
	bra.uni 	$L__BB0_64;

$L__BB0_167:
	mov.f32 	%f1233, 0f00000000;
	mov.u32 	%r469, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1233;}

	// end inline asm
	mov.u16 	%rs114, 0;
	st.global.v4.u16 	[%rd28], {%rs111, %rs112, %rs113, %rs114};

$L__BB0_168:
	ld.const.u64 	%rd108, [params+256];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r443, [params+248];
	mad.lo.s32 	%r444, %r443, %r7, %r6;
	mul.wide.u32 	%rd110, %r444, 8;
	add.s64 	%rd29, %rd109, %rd110;
	setp.eq.s32 	%p196, %r469, 0;
	@%p196 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1234, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1235, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1236, %rs123;}

	// end inline asm
	add.f32 	%f1237, %f1234, 0f00000000;
	add.f32 	%f1238, %f1235, 0f00000000;
	add.f32 	%f1239, %f1236, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1239;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1238;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1237;}

	// end inline asm
	mov.u16 	%rs125, 0;
	st.global.v4.u16 	[%rd29], {%rs118, %rs119, %rs120, %rs125};
	bra.uni 	$L__BB0_171;

$L__BB0_170:
	mov.f32 	%f1242, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1242;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1242;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1242;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd29], {%rs126, %rs127, %rs128, %rs129};

$L__BB0_171:
	ld.const.u64 	%rd111, [params+272];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r445, [params+264];
	mad.lo.s32 	%r446, %r445, %r7, %r6;
	mul.wide.u32 	%rd113, %r446, 8;
	add.s64 	%rd30, %rd112, %rd113;
	@%p196 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1243, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1244, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1245, %rs138;}

	// end inline asm
	add.f32 	%f1246, %f1243, 0f00000000;
	add.f32 	%f1247, %f1244, 0f00000000;
	add.f32 	%f1248, %f1245, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1248;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1247;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1246;}

	// end inline asm
	mov.u16 	%rs140, 0;
	st.global.v4.u16 	[%rd30], {%rs133, %rs134, %rs135, %rs140};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1251, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1251;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1251;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1251;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd30], {%rs141, %rs142, %rs143, %rs144};

$L__BB0_174:
	ld.const.u64 	%rd114, [params+288];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r447, [params+280];
	mad.lo.s32 	%r448, %r447, %r7, %r6;
	mul.wide.u32 	%rd116, %r448, 8;
	add.s64 	%rd31, %rd115, %rd116;
	@%p196 bra 	$L__BB0_176;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1252, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1253, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1254, %rs153;}

	// end inline asm
	add.f32 	%f1255, %f1252, 0f00000000;
	add.f32 	%f1256, %f1253, 0f00000000;
	add.f32 	%f1257, %f1254, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1257;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1256;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1255;}

	// end inline asm
	mov.u16 	%rs155, 0;
	st.global.v4.u16 	[%rd31], {%rs148, %rs149, %rs150, %rs155};
	bra.uni 	$L__BB0_177;

$L__BB0_176:
	mov.f32 	%f1260, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1260;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1260;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1260;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd31], {%rs156, %rs157, %rs158, %rs159};

$L__BB0_177:
	ld.const.u64 	%rd117, [params+304];
	cvta.to.global.u64 	%rd118, %rd117;
	ld.const.u32 	%r449, [params+296];
	mad.lo.s32 	%r450, %r449, %r7, %r6;
	mul.wide.u32 	%rd119, %r450, 8;
	add.s64 	%rd32, %rd118, %rd119;
	@%p196 bra 	$L__BB0_179;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1261, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1262, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1263, %rs168;}

	// end inline asm
	add.f32 	%f1264, %f1261, 0f00000000;
	add.f32 	%f1265, %f1262, 0f00000000;
	add.f32 	%f1266, %f1263, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1266;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1265;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1264;}

	// end inline asm
	mov.u16 	%rs170, 0;
	st.global.v4.u16 	[%rd32], {%rs163, %rs164, %rs165, %rs170};
	bra.uni 	$L__BB0_180;

$L__BB0_179:
	mov.f32 	%f1269, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1269;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1269;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1269;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd32], {%rs171, %rs172, %rs173, %rs174};
	bra.uni 	$L__BB0_180;

$L__BB0_60:
	mov.b32 	%r323, %f1338;
	xor.b32  	%r324, %r323, -2147483648;
	mov.b32 	%f625, %r324;
	selp.f32 	%f1340, %f625, %f1338, %p3;
	setp.geu.f32 	%p79, %f152, 0f00000000;
	@%p79 bra 	$L__BB0_64;

	mov.f32 	%f626, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f627, %f626;
	setp.eq.f32 	%p80, %f627, 0f3EE8BA2E;
	@%p80 bra 	$L__BB0_64;

	mov.f32 	%f1340, 0f7FFFFFFF;

$L__BB0_64:
	add.f32 	%f630, %f154, 0f3EE8BA2E;
	mov.b32 	%r325, %f630;
	setp.lt.s32 	%p82, %r325, 2139095040;
	@%p82 bra 	$L__BB0_69;

	setp.gtu.f32 	%p83, %f154, 0f7F800000;
	@%p83 bra 	$L__BB0_68;
	bra.uni 	$L__BB0_66;

$L__BB0_68:
	add.f32 	%f1340, %f152, 0f3EE8BA2E;
	bra.uni 	$L__BB0_69;

$L__BB0_66:
	setp.neu.f32 	%p84, %f154, 0f7F800000;
	@%p84 bra 	$L__BB0_69;

	selp.f32 	%f1340, 0fFF800000, 0f7F800000, %p3;

$L__BB0_69:
	mul.f32 	%f631, %f1340, 0f437F0000;
	setp.eq.f32 	%p85, %f152, 0f3F800000;
	selp.f32 	%f632, 0f437F0000, %f631, %p85;
	cvt.rzi.u32.f32 	%r326, %f632;
	shl.b64 	%rd77, %rd20, 1;
	add.s64 	%rd78, %rd19, %rd77;
	cvt.u16.u32 	%rs16, %r326;
	mov.u16 	%rs17, 255;
	st.global.v2.u8 	[%rd78], {%rs16, %rs17};

$L__BB0_70:
	ld.const.v2.f32 	{%f633, %f634}, [params+648];
	mul.f32 	%f167, %f1337, %f633;
	mul.f32 	%f168, %f1337, %f634;
	ld.const.f32 	%f169, [params+656];
	mul.f32 	%f170, %f1337, %f169;
	and.b32  	%r327, %r56, 1;
	setp.eq.b32 	%p86, %r327, 1;
	mov.pred 	%p87, 0;
	xor.pred  	%p88, %p86, %p87;
	not.pred 	%p89, %p88;
	@%p89 bra 	$L__BB0_144;

	mov.f32 	%f636, 0f3E666666;
	cvt.rzi.f32.f32 	%f637, %f636;
	add.f32 	%f638, %f637, %f637;
	mov.f32 	%f639, 0f3EE66666;
	sub.f32 	%f640, %f639, %f638;
	abs.f32 	%f171, %f640;
	abs.f32 	%f172, %f167;
	setp.lt.f32 	%p90, %f172, 0f00800000;
	mul.f32 	%f641, %f172, 0f4B800000;
	selp.f32 	%f642, %f641, %f172, %p90;
	selp.f32 	%f643, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r328, %f642;
	and.b32  	%r329, %r328, 8388607;
	or.b32  	%r330, %r329, 1065353216;
	mov.b32 	%f644, %r330;
	shr.u32 	%r331, %r328, 23;
	cvt.rn.f32.u32 	%f645, %r331;
	add.f32 	%f646, %f643, %f645;
	setp.gt.f32 	%p91, %f644, 0f3FB504F3;
	mul.f32 	%f647, %f644, 0f3F000000;
	add.f32 	%f648, %f646, 0f3F800000;
	selp.f32 	%f649, %f648, %f646, %p91;
	selp.f32 	%f650, %f647, %f644, %p91;
	add.f32 	%f651, %f650, 0fBF800000;
	add.f32 	%f652, %f650, 0f3F800000;
	rcp.approx.ftz.f32 	%f653, %f652;
	add.f32 	%f654, %f651, %f651;
	mul.f32 	%f655, %f654, %f653;
	mul.f32 	%f656, %f655, %f655;
	mov.f32 	%f657, 0f3C4CAF63;
	mov.f32 	%f658, 0f3B18F0FE;
	fma.rn.f32 	%f659, %f658, %f656, %f657;
	mov.f32 	%f660, 0f3DAAAABD;
	fma.rn.f32 	%f661, %f659, %f656, %f660;
	mul.rn.f32 	%f662, %f661, %f656;
	mul.rn.f32 	%f663, %f662, %f655;
	sub.f32 	%f664, %f651, %f655;
	add.f32 	%f665, %f664, %f664;
	neg.f32 	%f666, %f655;
	fma.rn.f32 	%f667, %f666, %f651, %f665;
	mul.rn.f32 	%f668, %f653, %f667;
	add.f32 	%f669, %f663, %f655;
	sub.f32 	%f670, %f655, %f669;
	add.f32 	%f671, %f663, %f670;
	add.f32 	%f672, %f668, %f671;
	add.f32 	%f673, %f669, %f672;
	sub.f32 	%f674, %f669, %f673;
	add.f32 	%f675, %f672, %f674;
	mov.f32 	%f676, 0f3F317200;
	mul.rn.f32 	%f677, %f649, %f676;
	mov.f32 	%f678, 0f35BFBE8E;
	mul.rn.f32 	%f679, %f649, %f678;
	add.f32 	%f680, %f677, %f673;
	sub.f32 	%f681, %f677, %f680;
	add.f32 	%f682, %f673, %f681;
	add.f32 	%f683, %f675, %f682;
	add.f32 	%f684, %f679, %f683;
	add.f32 	%f685, %f680, %f684;
	sub.f32 	%f686, %f680, %f685;
	add.f32 	%f687, %f684, %f686;
	mul.rn.f32 	%f688, %f639, %f685;
	neg.f32 	%f689, %f688;
	fma.rn.f32 	%f690, %f639, %f685, %f689;
	fma.rn.f32 	%f691, %f639, %f687, %f690;
	mov.f32 	%f692, 0f00000000;
	fma.rn.f32 	%f693, %f692, %f685, %f691;
	add.rn.f32 	%f694, %f688, %f693;
	neg.f32 	%f695, %f694;
	add.rn.f32 	%f696, %f688, %f695;
	add.rn.f32 	%f697, %f696, %f693;
	mov.b32 	%r332, %f694;
	setp.eq.s32 	%p92, %r332, 1118925336;
	add.s32 	%r333, %r332, -1;
	mov.b32 	%f698, %r333;
	add.f32 	%f699, %f697, 0f37000000;
	selp.f32 	%f173, %f699, %f697, %p92;
	selp.f32 	%f700, %f698, %f694, %p92;
	mov.f32 	%f701, 0f3FB8AA3B;
	mul.rn.f32 	%f702, %f700, %f701;
	cvt.rzi.f32.f32 	%f703, %f702;
	abs.f32 	%f704, %f703;
	setp.gt.f32 	%p93, %f704, 0f42FC0000;
	mov.b32 	%r334, %f703;
	and.b32  	%r335, %r334, -2147483648;
	or.b32  	%r336, %r335, 1123811328;
	mov.b32 	%f705, %r336;
	selp.f32 	%f706, %f705, %f703, %p93;
	mov.f32 	%f707, 0fBF317218;
	fma.rn.f32 	%f708, %f706, %f707, %f700;
	mov.f32 	%f709, 0f3102E308;
	fma.rn.f32 	%f710, %f706, %f709, %f708;
	mul.f32 	%f711, %f710, 0f3FB8AA3B;
	add.f32 	%f712, %f706, 0f4B40007F;
	mov.b32 	%r337, %f712;
	shl.b32 	%r338, %r337, 23;
	mov.b32 	%f713, %r338;
	ex2.approx.ftz.f32 	%f714, %f711;
	mul.f32 	%f174, %f714, %f713;
	setp.eq.f32 	%p94, %f174, 0f7F800000;
	mov.f32 	%f1341, 0f7F800000;
	@%p94 bra 	$L__BB0_73;

	fma.rn.f32 	%f1341, %f174, %f173, %f174;

$L__BB0_73:
	setp.lt.f32 	%p95, %f167, 0f00000000;
	setp.eq.f32 	%p96, %f171, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f167, 0f00000000;
	@%p97 bra 	$L__BB0_77;
	bra.uni 	$L__BB0_74;

$L__BB0_77:
	add.f32 	%f719, %f167, %f167;
	selp.f32 	%f1343, %f719, 0f00000000, %p96;
	bra.uni 	$L__BB0_78;

$L__BB0_74:
	mov.b32 	%r339, %f1341;
	xor.b32  	%r340, %r339, -2147483648;
	mov.b32 	%f715, %r340;
	selp.f32 	%f1343, %f715, %f1341, %p4;
	setp.geu.f32 	%p98, %f167, 0f00000000;
	@%p98 bra 	$L__BB0_78;

	mov.f32 	%f716, 0f3EE66666;
	cvt.rzi.f32.f32 	%f717, %f716;
	setp.eq.f32 	%p99, %f717, 0f3EE66666;
	@%p99 bra 	$L__BB0_78;

	mov.f32 	%f1343, 0f7FFFFFFF;

$L__BB0_78:
	add.f32 	%f720, %f172, 0f3EE66666;
	mov.b32 	%r341, %f720;
	setp.lt.s32 	%p101, %r341, 2139095040;
	@%p101 bra 	$L__BB0_83;

	setp.gtu.f32 	%p102, %f172, 0f7F800000;
	@%p102 bra 	$L__BB0_82;
	bra.uni 	$L__BB0_80;

$L__BB0_82:
	add.f32 	%f1343, %f167, 0f3EE66666;
	bra.uni 	$L__BB0_83;

$L__BB0_80:
	setp.neu.f32 	%p103, %f172, 0f7F800000;
	@%p103 bra 	$L__BB0_83;

	selp.f32 	%f1343, 0fFF800000, 0f7F800000, %p4;

$L__BB0_83:
	setp.eq.f32 	%p104, %f167, 0f3F800000;
	selp.f32 	%f183, 0f3F800000, %f1343, %p104;
	abs.f32 	%f184, %f168;
	setp.lt.f32 	%p105, %f184, 0f00800000;
	mul.f32 	%f722, %f184, 0f4B800000;
	selp.f32 	%f723, %f722, %f184, %p105;
	selp.f32 	%f724, 0fC3170000, 0fC2FE0000, %p105;
	mov.b32 	%r342, %f723;
	and.b32  	%r343, %r342, 8388607;
	or.b32  	%r344, %r343, 1065353216;
	mov.b32 	%f725, %r344;
	shr.u32 	%r345, %r342, 23;
	cvt.rn.f32.u32 	%f726, %r345;
	add.f32 	%f727, %f724, %f726;
	setp.gt.f32 	%p106, %f725, 0f3FB504F3;
	mul.f32 	%f728, %f725, 0f3F000000;
	add.f32 	%f729, %f727, 0f3F800000;
	selp.f32 	%f730, %f729, %f727, %p106;
	selp.f32 	%f731, %f728, %f725, %p106;
	add.f32 	%f732, %f731, 0fBF800000;
	add.f32 	%f733, %f731, 0f3F800000;
	rcp.approx.ftz.f32 	%f734, %f733;
	add.f32 	%f735, %f732, %f732;
	mul.f32 	%f736, %f735, %f734;
	mul.f32 	%f737, %f736, %f736;
	mov.f32 	%f738, 0f3C4CAF63;
	mov.f32 	%f739, 0f3B18F0FE;
	fma.rn.f32 	%f740, %f739, %f737, %f738;
	mov.f32 	%f741, 0f3DAAAABD;
	fma.rn.f32 	%f742, %f740, %f737, %f741;
	mul.rn.f32 	%f743, %f742, %f737;
	mul.rn.f32 	%f744, %f743, %f736;
	sub.f32 	%f745, %f732, %f736;
	add.f32 	%f746, %f745, %f745;
	neg.f32 	%f747, %f736;
	fma.rn.f32 	%f748, %f747, %f732, %f746;
	mul.rn.f32 	%f749, %f734, %f748;
	add.f32 	%f750, %f744, %f736;
	sub.f32 	%f751, %f736, %f750;
	add.f32 	%f752, %f744, %f751;
	add.f32 	%f753, %f749, %f752;
	add.f32 	%f754, %f750, %f753;
	sub.f32 	%f755, %f750, %f754;
	add.f32 	%f756, %f753, %f755;
	mov.f32 	%f757, 0f3F317200;
	mul.rn.f32 	%f758, %f730, %f757;
	mov.f32 	%f759, 0f35BFBE8E;
	mul.rn.f32 	%f760, %f730, %f759;
	add.f32 	%f761, %f758, %f754;
	sub.f32 	%f762, %f758, %f761;
	add.f32 	%f763, %f754, %f762;
	add.f32 	%f764, %f756, %f763;
	add.f32 	%f765, %f760, %f764;
	add.f32 	%f766, %f761, %f765;
	sub.f32 	%f767, %f761, %f766;
	add.f32 	%f768, %f765, %f767;
	mov.f32 	%f769, 0f3EE66666;
	mul.rn.f32 	%f770, %f769, %f766;
	neg.f32 	%f771, %f770;
	fma.rn.f32 	%f772, %f769, %f766, %f771;
	fma.rn.f32 	%f773, %f769, %f768, %f772;
	mov.f32 	%f774, 0f00000000;
	fma.rn.f32 	%f775, %f774, %f766, %f773;
	add.rn.f32 	%f776, %f770, %f775;
	neg.f32 	%f777, %f776;
	add.rn.f32 	%f778, %f770, %f777;
	add.rn.f32 	%f779, %f778, %f775;
	mov.b32 	%r346, %f776;
	setp.eq.s32 	%p107, %r346, 1118925336;
	add.s32 	%r347, %r346, -1;
	mov.b32 	%f780, %r347;
	add.f32 	%f781, %f779, 0f37000000;
	selp.f32 	%f185, %f781, %f779, %p107;
	selp.f32 	%f782, %f780, %f776, %p107;
	mov.f32 	%f783, 0f3FB8AA3B;
	mul.rn.f32 	%f784, %f782, %f783;
	cvt.rzi.f32.f32 	%f785, %f784;
	abs.f32 	%f786, %f785;
	setp.gt.f32 	%p108, %f786, 0f42FC0000;
	mov.b32 	%r348, %f785;
	and.b32  	%r349, %r348, -2147483648;
	or.b32  	%r350, %r349, 1123811328;
	mov.b32 	%f787, %r350;
	selp.f32 	%f788, %f787, %f785, %p108;
	mov.f32 	%f789, 0fBF317218;
	fma.rn.f32 	%f790, %f788, %f789, %f782;
	mov.f32 	%f791, 0f3102E308;
	fma.rn.f32 	%f792, %f788, %f791, %f790;
	mul.f32 	%f793, %f792, 0f3FB8AA3B;
	add.f32 	%f794, %f788, 0f4B40007F;
	mov.b32 	%r351, %f794;
	shl.b32 	%r352, %r351, 23;
	mov.b32 	%f795, %r352;
	ex2.approx.ftz.f32 	%f796, %f793;
	mul.f32 	%f186, %f796, %f795;
	setp.eq.f32 	%p109, %f186, 0f7F800000;
	mov.f32 	%f1344, 0f7F800000;
	@%p109 bra 	$L__BB0_85;

	fma.rn.f32 	%f1344, %f186, %f185, %f186;

$L__BB0_85:
	setp.lt.f32 	%p110, %f168, 0f00000000;
	and.pred  	%p5, %p110, %p96;
	setp.eq.f32 	%p112, %f168, 0f00000000;
	@%p112 bra 	$L__BB0_89;
	bra.uni 	$L__BB0_86;

$L__BB0_89:
	add.f32 	%f801, %f168, %f168;
	selp.f32 	%f1346, %f801, 0f00000000, %p96;
	bra.uni 	$L__BB0_90;

$L__BB0_86:
	mov.b32 	%r353, %f1344;
	xor.b32  	%r354, %r353, -2147483648;
	mov.b32 	%f797, %r354;
	selp.f32 	%f1346, %f797, %f1344, %p5;
	setp.geu.f32 	%p113, %f168, 0f00000000;
	@%p113 bra 	$L__BB0_90;

	mov.f32 	%f798, 0f3EE66666;
	cvt.rzi.f32.f32 	%f799, %f798;
	setp.eq.f32 	%p114, %f799, 0f3EE66666;
	@%p114 bra 	$L__BB0_90;

	mov.f32 	%f1346, 0f7FFFFFFF;

$L__BB0_90:
	add.f32 	%f802, %f184, 0f3EE66666;
	mov.b32 	%r355, %f802;
	setp.lt.s32 	%p116, %r355, 2139095040;
	@%p116 bra 	$L__BB0_95;

	setp.gtu.f32 	%p117, %f184, 0f7F800000;
	@%p117 bra 	$L__BB0_94;
	bra.uni 	$L__BB0_92;

$L__BB0_94:
	add.f32 	%f1346, %f168, 0f3EE66666;
	bra.uni 	$L__BB0_95;

$L__BB0_92:
	setp.neu.f32 	%p118, %f184, 0f7F800000;
	@%p118 bra 	$L__BB0_95;

	selp.f32 	%f1346, 0fFF800000, 0f7F800000, %p5;

$L__BB0_95:
	setp.eq.f32 	%p119, %f168, 0f3F800000;
	selp.f32 	%f195, 0f3F800000, %f1346, %p119;
	abs.f32 	%f196, %f170;
	setp.lt.f32 	%p120, %f196, 0f00800000;
	mul.f32 	%f804, %f196, 0f4B800000;
	selp.f32 	%f805, %f804, %f196, %p120;
	selp.f32 	%f806, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r356, %f805;
	and.b32  	%r357, %r356, 8388607;
	or.b32  	%r358, %r357, 1065353216;
	mov.b32 	%f807, %r358;
	shr.u32 	%r359, %r356, 23;
	cvt.rn.f32.u32 	%f808, %r359;
	add.f32 	%f809, %f806, %f808;
	setp.gt.f32 	%p121, %f807, 0f3FB504F3;
	mul.f32 	%f810, %f807, 0f3F000000;
	add.f32 	%f811, %f809, 0f3F800000;
	selp.f32 	%f812, %f811, %f809, %p121;
	selp.f32 	%f813, %f810, %f807, %p121;
	add.f32 	%f814, %f813, 0fBF800000;
	add.f32 	%f815, %f813, 0f3F800000;
	rcp.approx.ftz.f32 	%f816, %f815;
	add.f32 	%f817, %f814, %f814;
	mul.f32 	%f818, %f817, %f816;
	mul.f32 	%f819, %f818, %f818;
	mov.f32 	%f820, 0f3C4CAF63;
	mov.f32 	%f821, 0f3B18F0FE;
	fma.rn.f32 	%f822, %f821, %f819, %f820;
	mov.f32 	%f823, 0f3DAAAABD;
	fma.rn.f32 	%f824, %f822, %f819, %f823;
	mul.rn.f32 	%f825, %f824, %f819;
	mul.rn.f32 	%f826, %f825, %f818;
	sub.f32 	%f827, %f814, %f818;
	add.f32 	%f828, %f827, %f827;
	neg.f32 	%f829, %f818;
	fma.rn.f32 	%f830, %f829, %f814, %f828;
	mul.rn.f32 	%f831, %f816, %f830;
	add.f32 	%f832, %f826, %f818;
	sub.f32 	%f833, %f818, %f832;
	add.f32 	%f834, %f826, %f833;
	add.f32 	%f835, %f831, %f834;
	add.f32 	%f836, %f832, %f835;
	sub.f32 	%f837, %f832, %f836;
	add.f32 	%f838, %f835, %f837;
	mov.f32 	%f839, 0f3F317200;
	mul.rn.f32 	%f840, %f812, %f839;
	mov.f32 	%f841, 0f35BFBE8E;
	mul.rn.f32 	%f842, %f812, %f841;
	add.f32 	%f843, %f840, %f836;
	sub.f32 	%f844, %f840, %f843;
	add.f32 	%f845, %f836, %f844;
	add.f32 	%f846, %f838, %f845;
	add.f32 	%f847, %f842, %f846;
	add.f32 	%f848, %f843, %f847;
	sub.f32 	%f849, %f843, %f848;
	add.f32 	%f850, %f847, %f849;
	mov.f32 	%f851, 0f3EE66666;
	mul.rn.f32 	%f852, %f851, %f848;
	neg.f32 	%f853, %f852;
	fma.rn.f32 	%f854, %f851, %f848, %f853;
	fma.rn.f32 	%f855, %f851, %f850, %f854;
	mov.f32 	%f856, 0f00000000;
	fma.rn.f32 	%f857, %f856, %f848, %f855;
	add.rn.f32 	%f858, %f852, %f857;
	neg.f32 	%f859, %f858;
	add.rn.f32 	%f860, %f852, %f859;
	add.rn.f32 	%f861, %f860, %f857;
	mov.b32 	%r360, %f858;
	setp.eq.s32 	%p122, %r360, 1118925336;
	add.s32 	%r361, %r360, -1;
	mov.b32 	%f862, %r361;
	add.f32 	%f863, %f861, 0f37000000;
	selp.f32 	%f197, %f863, %f861, %p122;
	selp.f32 	%f864, %f862, %f858, %p122;
	mov.f32 	%f865, 0f3FB8AA3B;
	mul.rn.f32 	%f866, %f864, %f865;
	cvt.rzi.f32.f32 	%f867, %f866;
	abs.f32 	%f868, %f867;
	setp.gt.f32 	%p123, %f868, 0f42FC0000;
	mov.b32 	%r362, %f867;
	and.b32  	%r363, %r362, -2147483648;
	or.b32  	%r364, %r363, 1123811328;
	mov.b32 	%f869, %r364;
	selp.f32 	%f870, %f869, %f867, %p123;
	mov.f32 	%f871, 0fBF317218;
	fma.rn.f32 	%f872, %f870, %f871, %f864;
	mov.f32 	%f873, 0f3102E308;
	fma.rn.f32 	%f874, %f870, %f873, %f872;
	mul.f32 	%f875, %f874, 0f3FB8AA3B;
	add.f32 	%f876, %f870, 0f4B40007F;
	mov.b32 	%r365, %f876;
	shl.b32 	%r366, %r365, 23;
	mov.b32 	%f877, %r366;
	ex2.approx.ftz.f32 	%f878, %f875;
	mul.f32 	%f198, %f878, %f877;
	setp.eq.f32 	%p124, %f198, 0f7F800000;
	mov.f32 	%f1347, 0f7F800000;
	@%p124 bra 	$L__BB0_97;

	fma.rn.f32 	%f1347, %f198, %f197, %f198;

$L__BB0_97:
	setp.lt.f32 	%p125, %f170, 0f00000000;
	and.pred  	%p6, %p125, %p96;
	setp.eq.f32 	%p127, %f170, 0f00000000;
	@%p127 bra 	$L__BB0_101;
	bra.uni 	$L__BB0_98;

$L__BB0_101:
	add.f32 	%f883, %f170, %f170;
	selp.f32 	%f1349, %f883, 0f00000000, %p96;
	bra.uni 	$L__BB0_102;

$L__BB0_98:
	mov.b32 	%r367, %f1347;
	xor.b32  	%r368, %r367, -2147483648;
	mov.b32 	%f879, %r368;
	selp.f32 	%f1349, %f879, %f1347, %p6;
	setp.geu.f32 	%p128, %f170, 0f00000000;
	@%p128 bra 	$L__BB0_102;

	mov.f32 	%f880, 0f3EE66666;
	cvt.rzi.f32.f32 	%f881, %f880;
	setp.eq.f32 	%p129, %f881, 0f3EE66666;
	@%p129 bra 	$L__BB0_102;

	mov.f32 	%f1349, 0f7FFFFFFF;

$L__BB0_102:
	add.f32 	%f884, %f196, 0f3EE66666;
	mov.b32 	%r369, %f884;
	setp.lt.s32 	%p131, %r369, 2139095040;
	@%p131 bra 	$L__BB0_107;

	setp.gtu.f32 	%p132, %f196, 0f7F800000;
	@%p132 bra 	$L__BB0_106;
	bra.uni 	$L__BB0_104;

$L__BB0_106:
	add.f32 	%f1349, %f170, 0f3EE66666;
	bra.uni 	$L__BB0_107;

$L__BB0_104:
	setp.neu.f32 	%p133, %f196, 0f7F800000;
	@%p133 bra 	$L__BB0_107;

	selp.f32 	%f1349, 0fFF800000, 0f7F800000, %p6;

$L__BB0_107:
	setp.eq.f32 	%p134, %f170, 0f3F800000;
	mov.f32 	%f886, 0f3F800000;
	selp.f32 	%f887, 0f3F800000, %f1349, %p134;
	ld.const.u64 	%rd79, [params+144];
	cvta.to.global.u64 	%rd21, %rd79;
	ld.const.u32 	%r370, [params+136];
	mad.lo.s32 	%r371, %r370, %r7, %r6;
	cvt.u64.u32 	%rd22, %r371;
	min.f32 	%f888, %f183, %f886;
	mov.f32 	%f889, 0f00000000;
	max.f32 	%f207, %f889, %f888;
	min.f32 	%f890, %f195, %f886;
	max.f32 	%f208, %f889, %f890;
	min.f32 	%f891, %f887, %f886;
	max.f32 	%f209, %f889, %f891;
	mov.f32 	%f892, 0f3E555555;
	cvt.rzi.f32.f32 	%f893, %f892;
	add.f32 	%f894, %f893, %f893;
	mov.f32 	%f895, 0f3ED55555;
	sub.f32 	%f896, %f895, %f894;
	abs.f32 	%f210, %f896;
	abs.f32 	%f211, %f207;
	setp.lt.f32 	%p135, %f211, 0f00800000;
	mul.f32 	%f897, %f211, 0f4B800000;
	selp.f32 	%f898, %f897, %f211, %p135;
	selp.f32 	%f899, 0fC3170000, 0fC2FE0000, %p135;
	mov.b32 	%r372, %f898;
	and.b32  	%r373, %r372, 8388607;
	or.b32  	%r374, %r373, 1065353216;
	mov.b32 	%f900, %r374;
	shr.u32 	%r375, %r372, 23;
	cvt.rn.f32.u32 	%f901, %r375;
	add.f32 	%f902, %f899, %f901;
	setp.gt.f32 	%p136, %f900, 0f3FB504F3;
	mul.f32 	%f903, %f900, 0f3F000000;
	add.f32 	%f904, %f902, 0f3F800000;
	selp.f32 	%f905, %f904, %f902, %p136;
	selp.f32 	%f906, %f903, %f900, %p136;
	add.f32 	%f907, %f906, 0fBF800000;
	add.f32 	%f908, %f906, 0f3F800000;
	rcp.approx.ftz.f32 	%f909, %f908;
	add.f32 	%f910, %f907, %f907;
	mul.f32 	%f911, %f910, %f909;
	mul.f32 	%f912, %f911, %f911;
	mov.f32 	%f913, 0f3C4CAF63;
	mov.f32 	%f914, 0f3B18F0FE;
	fma.rn.f32 	%f915, %f914, %f912, %f913;
	mov.f32 	%f916, 0f3DAAAABD;
	fma.rn.f32 	%f917, %f915, %f912, %f916;
	mul.rn.f32 	%f918, %f917, %f912;
	mul.rn.f32 	%f919, %f918, %f911;
	sub.f32 	%f920, %f907, %f911;
	add.f32 	%f921, %f920, %f920;
	neg.f32 	%f922, %f911;
	fma.rn.f32 	%f923, %f922, %f907, %f921;
	mul.rn.f32 	%f924, %f909, %f923;
	add.f32 	%f925, %f919, %f911;
	sub.f32 	%f926, %f911, %f925;
	add.f32 	%f927, %f919, %f926;
	add.f32 	%f928, %f924, %f927;
	add.f32 	%f929, %f925, %f928;
	sub.f32 	%f930, %f925, %f929;
	add.f32 	%f931, %f928, %f930;
	mov.f32 	%f932, 0f3F317200;
	mul.rn.f32 	%f933, %f905, %f932;
	mov.f32 	%f934, 0f35BFBE8E;
	mul.rn.f32 	%f935, %f905, %f934;
	add.f32 	%f936, %f933, %f929;
	sub.f32 	%f937, %f933, %f936;
	add.f32 	%f938, %f929, %f937;
	add.f32 	%f939, %f931, %f938;
	add.f32 	%f940, %f935, %f939;
	add.f32 	%f941, %f936, %f940;
	sub.f32 	%f942, %f936, %f941;
	add.f32 	%f943, %f940, %f942;
	mul.rn.f32 	%f944, %f895, %f941;
	neg.f32 	%f945, %f944;
	fma.rn.f32 	%f946, %f895, %f941, %f945;
	fma.rn.f32 	%f947, %f895, %f943, %f946;
	fma.rn.f32 	%f948, %f889, %f941, %f947;
	add.rn.f32 	%f949, %f944, %f948;
	neg.f32 	%f950, %f949;
	add.rn.f32 	%f951, %f944, %f950;
	add.rn.f32 	%f952, %f951, %f948;
	mov.b32 	%r376, %f949;
	setp.eq.s32 	%p137, %r376, 1118925336;
	add.s32 	%r377, %r376, -1;
	mov.b32 	%f953, %r377;
	add.f32 	%f954, %f952, 0f37000000;
	selp.f32 	%f212, %f954, %f952, %p137;
	selp.f32 	%f955, %f953, %f949, %p137;
	mov.f32 	%f956, 0f3FB8AA3B;
	mul.rn.f32 	%f957, %f955, %f956;
	cvt.rzi.f32.f32 	%f958, %f957;
	abs.f32 	%f959, %f958;
	setp.gt.f32 	%p138, %f959, 0f42FC0000;
	mov.b32 	%r378, %f958;
	and.b32  	%r379, %r378, -2147483648;
	or.b32  	%r380, %r379, 1123811328;
	mov.b32 	%f960, %r380;
	selp.f32 	%f961, %f960, %f958, %p138;
	mov.f32 	%f962, 0fBF317218;
	fma.rn.f32 	%f963, %f961, %f962, %f955;
	mov.f32 	%f964, 0f3102E308;
	fma.rn.f32 	%f965, %f961, %f964, %f963;
	mul.f32 	%f966, %f965, 0f3FB8AA3B;
	add.f32 	%f967, %f961, 0f4B40007F;
	mov.b32 	%r381, %f967;
	shl.b32 	%r382, %r381, 23;
	mov.b32 	%f968, %r382;
	ex2.approx.ftz.f32 	%f969, %f966;
	mul.f32 	%f213, %f969, %f968;
	setp.eq.f32 	%p139, %f213, 0f7F800000;
	mov.f32 	%f1350, 0f7F800000;
	@%p139 bra 	$L__BB0_109;

	fma.rn.f32 	%f1350, %f213, %f212, %f213;

$L__BB0_109:
	setp.lt.f32 	%p140, %f207, 0f00000000;
	setp.eq.f32 	%p141, %f210, 0f3F800000;
	and.pred  	%p7, %p140, %p141;
	setp.eq.f32 	%p142, %f207, 0f00000000;
	@%p142 bra 	$L__BB0_113;
	bra.uni 	$L__BB0_110;

$L__BB0_113:
	add.f32 	%f974, %f207, %f207;
	selp.f32 	%f1352, %f974, 0f00000000, %p141;
	bra.uni 	$L__BB0_114;

$L__BB0_110:
	mov.b32 	%r383, %f1350;
	xor.b32  	%r384, %r383, -2147483648;
	mov.b32 	%f970, %r384;
	selp.f32 	%f1352, %f970, %f1350, %p7;
	setp.geu.f32 	%p143, %f207, 0f00000000;
	@%p143 bra 	$L__BB0_114;

	mov.f32 	%f971, 0f3ED55555;
	cvt.rzi.f32.f32 	%f972, %f971;
	setp.eq.f32 	%p144, %f972, 0f3ED55555;
	@%p144 bra 	$L__BB0_114;

	mov.f32 	%f1352, 0f7FFFFFFF;

$L__BB0_114:
	add.f32 	%f975, %f211, 0f3ED55555;
	mov.b32 	%r385, %f975;
	setp.lt.s32 	%p146, %r385, 2139095040;
	@%p146 bra 	$L__BB0_119;

	setp.gtu.f32 	%p147, %f211, 0f7F800000;
	@%p147 bra 	$L__BB0_118;
	bra.uni 	$L__BB0_116;

$L__BB0_118:
	add.f32 	%f1352, %f207, 0f3ED55555;
	bra.uni 	$L__BB0_119;

$L__BB0_116:
	setp.neu.f32 	%p148, %f211, 0f7F800000;
	@%p148 bra 	$L__BB0_119;

	selp.f32 	%f1352, 0fFF800000, 0f7F800000, %p7;

$L__BB0_119:
	abs.f32 	%f222, %f208;
	setp.lt.f32 	%p149, %f222, 0f00800000;
	mul.f32 	%f977, %f222, 0f4B800000;
	selp.f32 	%f978, %f977, %f222, %p149;
	selp.f32 	%f979, 0fC3170000, 0fC2FE0000, %p149;
	mov.b32 	%r386, %f978;
	and.b32  	%r387, %r386, 8388607;
	or.b32  	%r388, %r387, 1065353216;
	mov.b32 	%f980, %r388;
	shr.u32 	%r389, %r386, 23;
	cvt.rn.f32.u32 	%f981, %r389;
	add.f32 	%f982, %f979, %f981;
	setp.gt.f32 	%p150, %f980, 0f3FB504F3;
	mul.f32 	%f983, %f980, 0f3F000000;
	add.f32 	%f984, %f982, 0f3F800000;
	selp.f32 	%f985, %f984, %f982, %p150;
	selp.f32 	%f986, %f983, %f980, %p150;
	add.f32 	%f987, %f986, 0fBF800000;
	add.f32 	%f988, %f986, 0f3F800000;
	rcp.approx.ftz.f32 	%f989, %f988;
	add.f32 	%f990, %f987, %f987;
	mul.f32 	%f991, %f990, %f989;
	mul.f32 	%f992, %f991, %f991;
	mov.f32 	%f993, 0f3C4CAF63;
	mov.f32 	%f994, 0f3B18F0FE;
	fma.rn.f32 	%f995, %f994, %f992, %f993;
	mov.f32 	%f996, 0f3DAAAABD;
	fma.rn.f32 	%f997, %f995, %f992, %f996;
	mul.rn.f32 	%f998, %f997, %f992;
	mul.rn.f32 	%f999, %f998, %f991;
	sub.f32 	%f1000, %f987, %f991;
	add.f32 	%f1001, %f1000, %f1000;
	neg.f32 	%f1002, %f991;
	fma.rn.f32 	%f1003, %f1002, %f987, %f1001;
	mul.rn.f32 	%f1004, %f989, %f1003;
	add.f32 	%f1005, %f999, %f991;
	sub.f32 	%f1006, %f991, %f1005;
	add.f32 	%f1007, %f999, %f1006;
	add.f32 	%f1008, %f1004, %f1007;
	add.f32 	%f1009, %f1005, %f1008;
	sub.f32 	%f1010, %f1005, %f1009;
	add.f32 	%f1011, %f1008, %f1010;
	mov.f32 	%f1012, 0f3F317200;
	mul.rn.f32 	%f1013, %f985, %f1012;
	mov.f32 	%f1014, 0f35BFBE8E;
	mul.rn.f32 	%f1015, %f985, %f1014;
	add.f32 	%f1016, %f1013, %f1009;
	sub.f32 	%f1017, %f1013, %f1016;
	add.f32 	%f1018, %f1009, %f1017;
	add.f32 	%f1019, %f1011, %f1018;
	add.f32 	%f1020, %f1015, %f1019;
	add.f32 	%f1021, %f1016, %f1020;
	sub.f32 	%f1022, %f1016, %f1021;
	add.f32 	%f1023, %f1020, %f1022;
	mov.f32 	%f1024, 0f3ED55555;
	mul.rn.f32 	%f1025, %f1024, %f1021;
	neg.f32 	%f1026, %f1025;
	fma.rn.f32 	%f1027, %f1024, %f1021, %f1026;
	fma.rn.f32 	%f1028, %f1024, %f1023, %f1027;
	mov.f32 	%f1029, 0f00000000;
	fma.rn.f32 	%f1030, %f1029, %f1021, %f1028;
	add.rn.f32 	%f1031, %f1025, %f1030;
	neg.f32 	%f1032, %f1031;
	add.rn.f32 	%f1033, %f1025, %f1032;
	add.rn.f32 	%f1034, %f1033, %f1030;
	mov.b32 	%r390, %f1031;
	setp.eq.s32 	%p151, %r390, 1118925336;
	add.s32 	%r391, %r390, -1;
	mov.b32 	%f1035, %r391;
	add.f32 	%f1036, %f1034, 0f37000000;
	selp.f32 	%f223, %f1036, %f1034, %p151;
	selp.f32 	%f1037, %f1035, %f1031, %p151;
	mov.f32 	%f1038, 0f3FB8AA3B;
	mul.rn.f32 	%f1039, %f1037, %f1038;
	cvt.rzi.f32.f32 	%f1040, %f1039;
	abs.f32 	%f1041, %f1040;
	setp.gt.f32 	%p152, %f1041, 0f42FC0000;
	mov.b32 	%r392, %f1040;
	and.b32  	%r393, %r392, -2147483648;
	or.b32  	%r394, %r393, 1123811328;
	mov.b32 	%f1042, %r394;
	selp.f32 	%f1043, %f1042, %f1040, %p152;
	mov.f32 	%f1044, 0fBF317218;
	fma.rn.f32 	%f1045, %f1043, %f1044, %f1037;
	mov.f32 	%f1046, 0f3102E308;
	fma.rn.f32 	%f1047, %f1043, %f1046, %f1045;
	mul.f32 	%f1048, %f1047, 0f3FB8AA3B;
	add.f32 	%f1049, %f1043, 0f4B40007F;
	mov.b32 	%r395, %f1049;
	shl.b32 	%r396, %r395, 23;
	mov.b32 	%f1050, %r396;
	ex2.approx.ftz.f32 	%f1051, %f1048;
	mul.f32 	%f224, %f1051, %f1050;
	setp.eq.f32 	%p153, %f224, 0f7F800000;
	mov.f32 	%f1353, 0f7F800000;
	@%p153 bra 	$L__BB0_121;

	fma.rn.f32 	%f1353, %f224, %f223, %f224;

$L__BB0_121:
	setp.lt.f32 	%p154, %f208, 0f00000000;
	and.pred  	%p8, %p154, %p141;
	setp.eq.f32 	%p156, %f208, 0f00000000;
	@%p156 bra 	$L__BB0_125;
	bra.uni 	$L__BB0_122;

$L__BB0_125:
	add.f32 	%f1056, %f208, %f208;
	selp.f32 	%f1355, %f1056, 0f00000000, %p141;
	bra.uni 	$L__BB0_126;

$L__BB0_122:
	mov.b32 	%r397, %f1353;
	xor.b32  	%r398, %r397, -2147483648;
	mov.b32 	%f1052, %r398;
	selp.f32 	%f1355, %f1052, %f1353, %p8;
	setp.geu.f32 	%p157, %f208, 0f00000000;
	@%p157 bra 	$L__BB0_126;

	mov.f32 	%f1053, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1054, %f1053;
	setp.eq.f32 	%p158, %f1054, 0f3ED55555;
	@%p158 bra 	$L__BB0_126;

	mov.f32 	%f1355, 0f7FFFFFFF;

$L__BB0_126:
	add.f32 	%f1057, %f222, 0f3ED55555;
	mov.b32 	%r399, %f1057;
	setp.lt.s32 	%p160, %r399, 2139095040;
	@%p160 bra 	$L__BB0_131;

	setp.gtu.f32 	%p161, %f222, 0f7F800000;
	@%p161 bra 	$L__BB0_130;
	bra.uni 	$L__BB0_128;

$L__BB0_130:
	add.f32 	%f1355, %f208, 0f3ED55555;
	bra.uni 	$L__BB0_131;

$L__BB0_128:
	setp.neu.f32 	%p162, %f222, 0f7F800000;
	@%p162 bra 	$L__BB0_131;

	selp.f32 	%f1355, 0fFF800000, 0f7F800000, %p8;

$L__BB0_131:
	abs.f32 	%f233, %f209;
	setp.lt.f32 	%p163, %f233, 0f00800000;
	mul.f32 	%f1059, %f233, 0f4B800000;
	selp.f32 	%f1060, %f1059, %f233, %p163;
	selp.f32 	%f1061, 0fC3170000, 0fC2FE0000, %p163;
	mov.b32 	%r400, %f1060;
	and.b32  	%r401, %r400, 8388607;
	or.b32  	%r402, %r401, 1065353216;
	mov.b32 	%f1062, %r402;
	shr.u32 	%r403, %r400, 23;
	cvt.rn.f32.u32 	%f1063, %r403;
	add.f32 	%f1064, %f1061, %f1063;
	setp.gt.f32 	%p164, %f1062, 0f3FB504F3;
	mul.f32 	%f1065, %f1062, 0f3F000000;
	add.f32 	%f1066, %f1064, 0f3F800000;
	selp.f32 	%f1067, %f1066, %f1064, %p164;
	selp.f32 	%f1068, %f1065, %f1062, %p164;
	add.f32 	%f1069, %f1068, 0fBF800000;
	add.f32 	%f1070, %f1068, 0f3F800000;
	rcp.approx.ftz.f32 	%f1071, %f1070;
	add.f32 	%f1072, %f1069, %f1069;
	mul.f32 	%f1073, %f1072, %f1071;
	mul.f32 	%f1074, %f1073, %f1073;
	mov.f32 	%f1075, 0f3C4CAF63;
	mov.f32 	%f1076, 0f3B18F0FE;
	fma.rn.f32 	%f1077, %f1076, %f1074, %f1075;
	mov.f32 	%f1078, 0f3DAAAABD;
	fma.rn.f32 	%f1079, %f1077, %f1074, %f1078;
	mul.rn.f32 	%f1080, %f1079, %f1074;
	mul.rn.f32 	%f1081, %f1080, %f1073;
	sub.f32 	%f1082, %f1069, %f1073;
	add.f32 	%f1083, %f1082, %f1082;
	neg.f32 	%f1084, %f1073;
	fma.rn.f32 	%f1085, %f1084, %f1069, %f1083;
	mul.rn.f32 	%f1086, %f1071, %f1085;
	add.f32 	%f1087, %f1081, %f1073;
	sub.f32 	%f1088, %f1073, %f1087;
	add.f32 	%f1089, %f1081, %f1088;
	add.f32 	%f1090, %f1086, %f1089;
	add.f32 	%f1091, %f1087, %f1090;
	sub.f32 	%f1092, %f1087, %f1091;
	add.f32 	%f1093, %f1090, %f1092;
	mov.f32 	%f1094, 0f3F317200;
	mul.rn.f32 	%f1095, %f1067, %f1094;
	mov.f32 	%f1096, 0f35BFBE8E;
	mul.rn.f32 	%f1097, %f1067, %f1096;
	add.f32 	%f1098, %f1095, %f1091;
	sub.f32 	%f1099, %f1095, %f1098;
	add.f32 	%f1100, %f1091, %f1099;
	add.f32 	%f1101, %f1093, %f1100;
	add.f32 	%f1102, %f1097, %f1101;
	add.f32 	%f1103, %f1098, %f1102;
	sub.f32 	%f1104, %f1098, %f1103;
	add.f32 	%f1105, %f1102, %f1104;
	mov.f32 	%f1106, 0f3ED55555;
	mul.rn.f32 	%f1107, %f1106, %f1103;
	neg.f32 	%f1108, %f1107;
	fma.rn.f32 	%f1109, %f1106, %f1103, %f1108;
	fma.rn.f32 	%f1110, %f1106, %f1105, %f1109;
	mov.f32 	%f1111, 0f00000000;
	fma.rn.f32 	%f1112, %f1111, %f1103, %f1110;
	add.rn.f32 	%f1113, %f1107, %f1112;
	neg.f32 	%f1114, %f1113;
	add.rn.f32 	%f1115, %f1107, %f1114;
	add.rn.f32 	%f1116, %f1115, %f1112;
	mov.b32 	%r404, %f1113;
	setp.eq.s32 	%p165, %r404, 1118925336;
	add.s32 	%r405, %r404, -1;
	mov.b32 	%f1117, %r405;
	add.f32 	%f1118, %f1116, 0f37000000;
	selp.f32 	%f234, %f1118, %f1116, %p165;
	selp.f32 	%f1119, %f1117, %f1113, %p165;
	mov.f32 	%f1120, 0f3FB8AA3B;
	mul.rn.f32 	%f1121, %f1119, %f1120;
	cvt.rzi.f32.f32 	%f1122, %f1121;
	abs.f32 	%f1123, %f1122;
	setp.gt.f32 	%p166, %f1123, 0f42FC0000;
	mov.b32 	%r406, %f1122;
	and.b32  	%r407, %r406, -2147483648;
	or.b32  	%r408, %r407, 1123811328;
	mov.b32 	%f1124, %r408;
	selp.f32 	%f1125, %f1124, %f1122, %p166;
	mov.f32 	%f1126, 0fBF317218;
	fma.rn.f32 	%f1127, %f1125, %f1126, %f1119;
	mov.f32 	%f1128, 0f3102E308;
	fma.rn.f32 	%f1129, %f1125, %f1128, %f1127;
	mul.f32 	%f1130, %f1129, 0f3FB8AA3B;
	add.f32 	%f1131, %f1125, 0f4B40007F;
	mov.b32 	%r409, %f1131;
	shl.b32 	%r410, %r409, 23;
	mov.b32 	%f1132, %r410;
	ex2.approx.ftz.f32 	%f1133, %f1130;
	mul.f32 	%f235, %f1133, %f1132;
	setp.eq.f32 	%p167, %f235, 0f7F800000;
	mov.f32 	%f1356, 0f7F800000;
	@%p167 bra 	$L__BB0_133;

	fma.rn.f32 	%f1356, %f235, %f234, %f235;

$L__BB0_133:
	setp.lt.f32 	%p168, %f209, 0f00000000;
	and.pred  	%p9, %p168, %p141;
	setp.eq.f32 	%p170, %f209, 0f00000000;
	@%p170 bra 	$L__BB0_137;
	bra.uni 	$L__BB0_134;

$L__BB0_137:
	add.f32 	%f1138, %f209, %f209;
	selp.f32 	%f1358, %f1138, 0f00000000, %p141;
	bra.uni 	$L__BB0_138;

$L__BB0_134:
	mov.b32 	%r411, %f1356;
	xor.b32  	%r412, %r411, -2147483648;
	mov.b32 	%f1134, %r412;
	selp.f32 	%f1358, %f1134, %f1356, %p9;
	setp.geu.f32 	%p171, %f209, 0f00000000;
	@%p171 bra 	$L__BB0_138;

	mov.f32 	%f1135, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1136, %f1135;
	setp.eq.f32 	%p172, %f1136, 0f3ED55555;
	@%p172 bra 	$L__BB0_138;

	mov.f32 	%f1358, 0f7FFFFFFF;

$L__BB0_138:
	add.f32 	%f1139, %f233, 0f3ED55555;
	mov.b32 	%r413, %f1139;
	setp.lt.s32 	%p174, %r413, 2139095040;
	@%p174 bra 	$L__BB0_143;

	setp.gtu.f32 	%p175, %f233, 0f7F800000;
	@%p175 bra 	$L__BB0_142;
	bra.uni 	$L__BB0_140;

$L__BB0_142:
	add.f32 	%f1358, %f209, 0f3ED55555;
	bra.uni 	$L__BB0_143;

$L__BB0_140:
	setp.neu.f32 	%p176, %f233, 0f7F800000;
	@%p176 bra 	$L__BB0_143;

	selp.f32 	%f1358, 0fFF800000, 0f7F800000, %p9;

$L__BB0_143:
	fma.rn.f32 	%f1140, %f1352, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p177, %f207, 0f3F800000;
	mov.f32 	%f1141, 0f3F800000;
	selp.f32 	%f1142, 0f3F7FFFFF, %f1140, %p177;
	mul.f32 	%f1143, %f207, 0f414EB852;
	setp.lt.f32 	%p178, %f207, 0f3B4D2E1C;
	selp.f32 	%f1144, %f1143, %f1142, %p178;
	fma.rn.f32 	%f1145, %f1355, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p179, %f208, 0f3F800000;
	selp.f32 	%f1146, 0f3F7FFFFF, %f1145, %p179;
	mul.f32 	%f1147, %f208, 0f414EB852;
	setp.lt.f32 	%p180, %f208, 0f3B4D2E1C;
	selp.f32 	%f1148, %f1147, %f1146, %p180;
	fma.rn.f32 	%f1149, %f1358, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p181, %f209, 0f3F800000;
	selp.f32 	%f1150, 0f3F7FFFFF, %f1149, %p181;
	mul.f32 	%f1151, %f209, 0f414EB852;
	setp.lt.f32 	%p182, %f209, 0f3B4D2E1C;
	selp.f32 	%f1152, %f1151, %f1150, %p182;
	min.f32 	%f1153, %f1144, %f1141;
	mov.f32 	%f1154, 0f00000000;
	max.f32 	%f1155, %f1154, %f1153;
	mul.f32 	%f1156, %f1155, 0f43800000;
	cvt.rzi.u32.f32 	%r414, %f1156;
	min.u32 	%r415, %r414, 255;
	min.f32 	%f1157, %f1148, %f1141;
	max.f32 	%f1158, %f1154, %f1157;
	mul.f32 	%f1159, %f1158, 0f43800000;
	cvt.rzi.u32.f32 	%r416, %f1159;
	min.u32 	%r417, %r416, 255;
	min.f32 	%f1160, %f1152, %f1141;
	max.f32 	%f1161, %f1154, %f1160;
	mul.f32 	%f1162, %f1161, 0f43800000;
	cvt.rzi.u32.f32 	%r418, %f1162;
	min.u32 	%r419, %r418, 255;
	shl.b64 	%rd80, %rd22, 2;
	add.s64 	%rd81, %rd21, %rd80;
	cvt.u16.u32 	%rs18, %r419;
	cvt.u16.u32 	%rs19, %r417;
	cvt.u16.u32 	%rs20, %r415;
	mov.u16 	%rs21, 255;
	st.global.v4.u8 	[%rd81], {%rs20, %rs19, %rs18, %rs21};

$L__BB0_144:
	and.b32  	%r420, %r56, 4;
	setp.eq.s32 	%p183, %r420, 0;
	ld.const.u32 	%r468, [params+108];
	@%p183 bra 	$L__BB0_148;

	setp.eq.s32 	%p184, %r468, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r421, [params+216];
	mad.lo.s32 	%r422, %r421, %r7, %r6;
	mul.wide.u32 	%rd84, %r422, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p184 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs29, %rs30, %rs31, %rs32}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1163, %rs29;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1164, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1165, %rs31;}

	// end inline asm
	add.f32 	%f1166, %f167, %f1163;
	add.f32 	%f1167, %f168, %f1164;
	add.f32 	%f1168, %f170, %f1165;
	mov.f32 	%f1169, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f1167;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f1166;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1169;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs25, %rs26, %rs27, %rs28};
	bra.uni 	$L__BB0_148;

$L__BB0_147:
	mov.f32 	%f1173, 0f3F800000;
	mov.u32 	%r468, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1173;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f170;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f168;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f167;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs33, %rs34, %rs35, %rs36};

$L__BB0_148:
	selp.f32 	%f1174, 0f3F000000, 0f3E800000, %p200;
	mul.f32 	%f244, %f1174, %f1336;
	mul.f32 	%f245, %f1174, %f1335;
	mul.f32 	%f246, %f1174, %f1334;
	mul.f32 	%f247, %f1174, %f1333;
	mul.f32 	%f248, %f244, %f633;
	mul.f32 	%f249, %f244, %f634;
	mul.f32 	%f250, %f244, %f169;
	ld.const.u64 	%rd85, [params+256];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r424, [params+248];
	mad.lo.s32 	%r425, %r424, %r7, %r6;
	mul.wide.u32 	%rd87, %r425, 8;
	add.s64 	%rd24, %rd86, %rd87;
	setp.eq.s32 	%p185, %r468, 0;
	@%p185 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs44, %rs45, %rs46, %rs47}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1175, %rs44;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1176, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1177, %rs46;}

	// end inline asm
	add.f32 	%f1178, %f248, %f1175;
	add.f32 	%f1179, %f249, %f1176;
	add.f32 	%f1180, %f250, %f1177;
	mov.f32 	%f1181, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1180;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1179;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1178;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1181;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs40, %rs41, %rs42, %rs43};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1185, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1185;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f250;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f249;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f248;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs48, %rs49, %rs50, %rs51};

$L__BB0_151:
	mov.f32 	%f1186, 0f34000000;
	max.f32 	%f1187, %f244, %f1186;
	div.rn.f32 	%f1188, %f245, %f1187;
	fma.rn.f32 	%f251, %f1188, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1189, %f246, %f1187;
	fma.rn.f32 	%f252, %f1189, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1190, %f247, %f1187;
	fma.rn.f32 	%f253, %f1190, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd88, [params+272];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r426, [params+264];
	mad.lo.s32 	%r427, %r426, %r7, %r6;
	mul.wide.u32 	%rd90, %r427, 8;
	add.s64 	%rd25, %rd89, %rd90;
	@%p185 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs59, %rs60, %rs61, %rs62}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1191, %rs59;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1192, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1193, %rs61;}

	// end inline asm
	add.f32 	%f1194, %f251, %f1191;
	add.f32 	%f1195, %f251, %f1192;
	add.f32 	%f1196, %f251, %f1193;
	mov.f32 	%f1197, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1196;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1195;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1194;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1197;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs55, %rs56, %rs57, %rs58};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1201, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f251;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f251;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f251;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs63, %rs64, %rs65, %rs66};

$L__BB0_154:
	ld.const.u64 	%rd91, [params+288];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r428, [params+280];
	mad.lo.s32 	%r429, %r428, %r7, %r6;
	mul.wide.u32 	%rd93, %r429, 8;
	add.s64 	%rd26, %rd92, %rd93;
	@%p185 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1202, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1203, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1204, %rs76;}

	// end inline asm
	add.f32 	%f1205, %f252, %f1202;
	add.f32 	%f1206, %f252, %f1203;
	add.f32 	%f1207, %f252, %f1204;
	mov.f32 	%f1208, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1207;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1206;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1205;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1208;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1212, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1212;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f252;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f252;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f252;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_157:
	ld.const.u64 	%rd94, [params+304];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r430, [params+296];
	mad.lo.s32 	%r431, %r430, %r7, %r6;
	mul.wide.u32 	%rd96, %r431, 8;
	add.s64 	%rd27, %rd95, %rd96;
	@%p185 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1213, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1214, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1215, %rs91;}

	// end inline asm
	add.f32 	%f1216, %f253, %f1213;
	add.f32 	%f1217, %f253, %f1214;
	add.f32 	%f1218, %f253, %f1215;
	mov.f32 	%f1219, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1218;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1217;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1216;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1219;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_180;

$L__BB0_159:
	mov.f32 	%f1223, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1223;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f253;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f253;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f253;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_180:
	ret;

}