//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<155>;
	.reg .b16 	%rs<172>;
	.reg .f32 	%f<1205>;
	.reg .b32 	%r<362>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<110>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r56), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r57), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	shl.b32 	%r4, %r3, 1;
	ld.const.u64 	%rd30, [params+400];
	cvta.to.global.u64 	%rd31, %rd30;
	ld.const.u32 	%r62, [params+392];
	mad.lo.s32 	%r63, %r62, %r57, %r56;
	mul.wide.u32 	%rd32, %r63, 4;
	add.s64 	%rd2, %rd31, %rd32;
	ld.global.v2.u8 	{%rs7, %rs171}, [%rd2];
	or.b16  	%rs9, %rs7, %rs171;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p7, %rs10, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs170, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs170, [%rd2+2];
	setp.eq.s16 	%p8, %rs170, 0;
	mov.f32 	%f1118, 0f00000000;
	mov.u16 	%rs171, 0;
	mov.f32 	%f1119, %f1118;
	mov.f32 	%f1120, %f1118;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f243, %rs7;
	div.rn.f32 	%f244, %f243, 0f437F0000;
	fma.rn.f32 	%f245, %f244, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs171, 255;
	cvt.rn.f32.u16 	%f246, %rs13;
	div.rn.f32 	%f247, %f246, 0f437F0000;
	fma.rn.f32 	%f248, %f247, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f249, %rs170;
	div.rn.f32 	%f250, %f249, 0f437F0000;
	fma.rn.f32 	%f251, %f250, 0f40000000, 0fBF800000;
	mul.f32 	%f252, %f248, %f248;
	fma.rn.f32 	%f253, %f245, %f245, %f252;
	fma.rn.f32 	%f254, %f251, %f251, %f253;
	sqrt.rn.f32 	%f255, %f254;
	rcp.rn.f32 	%f256, %f255;
	mul.f32 	%f1120, %f256, %f251;
	mul.f32 	%f1119, %f256, %f248;
	mul.f32 	%f1118, %f245, %f256;

$L__BB0_4:
	ld.const.v2.u32 	{%r64, %r65}, [params];
	add.s32 	%r5, %r64, %r56;
	add.s32 	%r6, %r65, %r57;
	setp.eq.f32 	%p9, %f1118, 0f00000000;
	setp.eq.f32 	%p10, %f1119, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1120, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_126;
	bra.uni 	$L__BB0_5;

$L__BB0_126:
	ld.const.u32 	%r53, [params+104];
	and.b32  	%r315, %r53, 1;
	setp.eq.b32 	%p144, %r315, 1;
	mov.pred 	%p145, 0;
	xor.pred  	%p146, %p144, %p145;
	not.pred 	%p147, %p146;
	@%p147 bra 	$L__BB0_128;

	ld.const.u64 	%rd83, [params+144];
	cvta.to.global.u64 	%rd84, %rd83;
	ld.const.u32 	%r316, [params+136];
	mad.lo.s32 	%r317, %r316, %r6, %r5;
	mul.wide.u32 	%rd85, %r317, 4;
	add.s64 	%rd86, %rd84, %rd85;
	mov.u16 	%rs94, 0;
	st.global.v4.u8 	[%rd86], {%rs94, %rs94, %rs94, %rs94};

$L__BB0_128:
	and.b32  	%r318, %r53, 4;
	setp.eq.s32 	%p148, %r318, 0;
	ld.const.u32 	%r361, [params+108];
	@%p148 bra 	$L__BB0_132;

	setp.eq.s32 	%p149, %r361, 0;
	ld.const.u64 	%rd87, [params+224];
	cvta.to.global.u64 	%rd88, %rd87;
	ld.const.u32 	%r319, [params+216];
	mad.lo.s32 	%r320, %r319, %r6, %r5;
	mul.wide.u32 	%rd89, %r320, 8;
	add.s64 	%rd24, %rd88, %rd89;
	@%p149 bra 	$L__BB0_131;

	ld.global.v4.u16 	{%rs101, %rs102, %rs103, %rs104}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1027, %rs101;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1028, %rs102;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1029, %rs103;}

	// end inline asm
	add.f32 	%f1030, %f1027, 0f00000000;
	add.f32 	%f1031, %f1028, 0f00000000;
	add.f32 	%f1032, %f1029, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1032;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1030;}

	// end inline asm
	mov.u16 	%rs105, 0;
	st.global.v4.u16 	[%rd24], {%rs98, %rs99, %rs100, %rs105};
	bra.uni 	$L__BB0_132;

$L__BB0_5:
	ld.const.u64 	%rd33, [params+432];
	cvta.to.global.u64 	%rd34, %rd33;
	ld.const.u32 	%r68, [params+424];
	mad.lo.s32 	%r69, %r68, %r57, %r56;
	mul.wide.u32 	%rd35, %r69, 12;
	add.s64 	%rd36, %rd34, %rd35;
	ld.global.f32 	%f272, [%rd36];
	mul.f32 	%f273, %f272, 0f3456BF95;
	ld.global.f32 	%f274, [%rd36+4];
	mul.f32 	%f275, %f274, 0f3456BF95;
	ld.global.f32 	%f276, [%rd36+8];
	mul.f32 	%f277, %f276, 0f3456BF95;
	abs.f32 	%f278, %f1118;
	div.rn.f32 	%f279, %f273, %f278;
	abs.f32 	%f280, %f1119;
	div.rn.f32 	%f281, %f275, %f280;
	abs.f32 	%f282, %f1120;
	div.rn.f32 	%f283, %f277, %f282;
	abs.f32 	%f284, %f279;
	abs.f32 	%f285, %f281;
	abs.f32 	%f286, %f283;
	mov.f32 	%f287, 0f38D1B717;
	max.f32 	%f288, %f284, %f287;
	max.f32 	%f289, %f285, %f287;
	max.f32 	%f290, %f286, %f287;
	fma.rn.f32 	%f10, %f1118, %f288, %f272;
	fma.rn.f32 	%f11, %f1119, %f289, %f274;
	fma.rn.f32 	%f12, %f1120, %f290, %f276;
	setp.gt.f32 	%p14, %f278, %f282;
	neg.f32 	%f291, %f1119;
	selp.f32 	%f292, %f291, 0f00000000, %p14;
	mov.f32 	%f1157, 0f00000000;
	neg.f32 	%f293, %f1120;
	selp.f32 	%f294, %f1118, %f293, %p14;
	selp.f32 	%f295, 0f00000000, %f1119, %p14;
	mul.f32 	%f296, %f294, %f294;
	fma.rn.f32 	%f297, %f292, %f292, %f296;
	fma.rn.f32 	%f298, %f295, %f295, %f297;
	sqrt.rn.f32 	%f299, %f298;
	rcp.rn.f32 	%f300, %f299;
	mul.f32 	%f13, %f292, %f300;
	mul.f32 	%f14, %f294, %f300;
	mul.f32 	%f15, %f295, %f300;
	ld.const.u64 	%rd37, [params+128];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r70, [params+120];
	mad.lo.s32 	%r71, %r70, %r57, %r56;
	mul.wide.u32 	%rd39, %r71, 4;
	add.s64 	%rd3, %rd38, %rd39;
	setp.lt.s32 	%p15, %r3, 1;
	mov.f32 	%f1158, %f1157;
	mov.f32 	%f1159, %f1157;
	mov.f32 	%f1160, %f1157;
	mov.f32 	%f1161, %f1157;
	mov.f32 	%f1162, %f1157;
	mov.f32 	%f1163, %f1157;
	mov.f32 	%f1164, %f1157;
	mov.f32 	%f1165, %f1157;
	mov.f32 	%f1166, %f1157;
	mov.f32 	%f1167, %f1157;
	mov.f32 	%f1168, %f1157;
	mov.f32 	%f1169, %f1157;
	mov.f32 	%f1170, %f1157;
	mov.f32 	%f1171, %f1157;
	@%p15 bra 	$L__BB0_36;

	ld.const.u32 	%r7, [params+588];
	cvt.rn.f32.s32 	%f316, %r4;
	rcp.rn.f32 	%f16, %f316;
	ld.global.u32 	%r352, [%rd3];
	mul.f32 	%f17, %f10, 0f3456BF95;
	mul.f32 	%f18, %f11, 0f3456BF95;
	mul.f32 	%f19, %f12, 0f3456BF95;
	ld.const.u64 	%rd4, [params+592];
	ld.const.u64 	%rd5, [params+96];
	mul.f32 	%f317, %f1118, %f14;
	mul.f32 	%f318, %f1119, %f13;
	sub.f32 	%f20, %f318, %f317;
	mul.f32 	%f319, %f1120, %f13;
	mul.f32 	%f320, %f1118, %f15;
	sub.f32 	%f21, %f320, %f319;
	mul.f32 	%f321, %f1119, %f15;
	mul.f32 	%f322, %f1120, %f14;
	sub.f32 	%f22, %f322, %f321;
	mov.u32 	%r72, 0;
	add.s64 	%rd6, %rd1, 24;
	abs.f32 	%f387, %f17;
	abs.f32 	%f388, %f18;
	max.f32 	%f389, %f387, %f388;
	abs.f32 	%f390, %f19;
	max.f32 	%f391, %f389, %f390;
	mov.u32 	%r349, %r72;

$L__BB0_7:
	mov.u32 	%r351, %r72;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1073, %r349;
	mad.lo.s32 	%r74, %r352, 1664525, 1013904223;
	and.b32  	%r75, %r74, 16777215;
	cvt.rn.f32.u32 	%f323, %r75;
	fma.rn.f32 	%f324, %f323, 0f33800000, %f1073;
	mul.f32 	%f325, %f16, %f324;
	mad.lo.s32 	%r352, %r74, 1664525, 1013904223;
	and.b32  	%r76, %r352, 16777215;
	cvt.rn.f32.u32 	%f326, %r76;
	cvt.rn.f32.s32 	%f327, %r351;
	fma.rn.f32 	%f328, %f326, 0f33800000, %f327;
	mul.f32 	%f329, %f16, %f328;
	fma.rn.f32 	%f330, %f16, %f324, %f325;
	mov.f32 	%f331, 0f3F800000;
	sub.f32 	%f54, %f331, %f330;
	mul.f32 	%f332, %f54, %f54;
	sub.f32 	%f333, %f331, %f332;
	mov.f32 	%f334, 0f00000000;
	max.f32 	%f335, %f334, %f333;
	sqrt.rn.f32 	%f55, %f335;
	mul.f32 	%f56, %f329, 0f40C90FDB;
	mul.f32 	%f336, %f56, 0f3F22F983;
	cvt.rni.s32.f32 	%r356, %f336;
	cvt.rn.f32.s32 	%f337, %r356;
	mov.f32 	%f338, 0fBFC90FDA;
	fma.rn.f32 	%f339, %f337, %f338, %f56;
	mov.f32 	%f340, 0fB3A22168;
	fma.rn.f32 	%f341, %f337, %f340, %f339;
	mov.f32 	%f342, 0fA7C234C5;
	fma.rn.f32 	%f1154, %f337, %f342, %f341;
	abs.f32 	%f58, %f56;
	setp.ltu.f32 	%p16, %f58, 0f47CE4780;
	mov.f32 	%f1151, %f1154;
	@%p16 bra 	$L__BB0_16;

	setp.eq.f32 	%p17, %f58, 0f7F800000;
	@%p17 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f345, 0f00000000;
	mul.rn.f32 	%f1151, %f56, %f345;
	mov.u32 	%r356, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r15, %f56;
	bfe.u32 	%r78, %r15, 23, 8;
	mov.u64 	%rd107, 0;
	mov.u32 	%r353, 0;
	mov.u64 	%rd106, __cudart_i2opi_f;
	mov.u64 	%rd105, %rd1;

$L__BB0_11:
	.pragma "nounroll";
	mov.b32 	%r332, %f56;
	shl.b32 	%r331, %r332, 8;
	or.b32  	%r330, %r331, -2147483648;
	ld.global.nc.u32 	%r80, [%rd106];
	mad.wide.u32 	%rd42, %r80, %r330, %rd107;
	shr.u64 	%rd107, %rd42, 32;
	st.local.u32 	[%rd105], %rd42;
	add.s64 	%rd106, %rd106, 4;
	add.s64 	%rd105, %rd105, 4;
	add.s32 	%r353, %r353, 1;
	setp.ne.s32 	%p18, %r353, 6;
	@%p18 bra 	$L__BB0_11;

	add.s32 	%r337, %r78, -128;
	mov.b32 	%r336, %f56;
	bfe.u32 	%r335, %r336, 23, 8;
	add.s32 	%r334, %r335, -128;
	shr.u32 	%r333, %r334, 5;
	st.local.u32 	[%rd6], %rd107;
	mov.u32 	%r82, 6;
	sub.s32 	%r83, %r82, %r333;
	mul.wide.s32 	%rd43, %r83, 4;
	add.s64 	%rd44, %rd1, %rd43;
	ld.local.u32 	%r354, [%rd44];
	ld.local.u32 	%r355, [%rd44+-4];
	and.b32  	%r24, %r334, 31;
	setp.eq.s32 	%p19, %r24, 0;
	@%p19 bra 	$L__BB0_14;

	mov.b32 	%r345, %f56;
	bfe.u32 	%r344, %r345, 23, 8;
	add.s32 	%r343, %r344, -128;
	shr.u32 	%r342, %r343, 5;
	mov.u32 	%r341, 4;
	sub.s32 	%r340, %r341, %r342;
	mov.u32 	%r84, 32;
	sub.s32 	%r85, %r84, %r24;
	shr.u32 	%r86, %r355, %r85;
	shl.b32 	%r87, %r354, %r24;
	add.s32 	%r354, %r86, %r87;
	mul.wide.s32 	%rd45, %r340, 4;
	add.s64 	%rd46, %rd1, %rd45;
	ld.local.u32 	%r88, [%rd46];
	shr.u32 	%r89, %r88, %r85;
	shl.b32 	%r90, %r355, %r24;
	add.s32 	%r355, %r89, %r90;

$L__BB0_14:
	mov.b32 	%r338, %f56;
	and.b32  	%r91, %r338, -2147483648;
	shr.u32 	%r92, %r355, 30;
	shl.b32 	%r93, %r354, 2;
	or.b32  	%r94, %r92, %r93;
	shr.u32 	%r95, %r94, 31;
	shr.u32 	%r96, %r354, 30;
	add.s32 	%r97, %r95, %r96;
	neg.s32 	%r98, %r97;
	setp.eq.s32 	%p20, %r91, 0;
	selp.b32 	%r356, %r97, %r98, %p20;
	setp.ne.s32 	%p21, %r95, 0;
	xor.b32  	%r99, %r91, -2147483648;
	selp.b32 	%r100, %r99, %r91, %p21;
	selp.b32 	%r101, -1, 0, %p21;
	xor.b32  	%r102, %r94, %r101;
	shl.b32 	%r103, %r355, 2;
	xor.b32  	%r104, %r103, %r101;
	cvt.u64.u32 	%rd47, %r102;
	cvt.u64.u32 	%rd48, %r104;
	bfi.b64 	%rd49, %rd47, %rd48, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd49;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f343, %fd2;
	setp.eq.s32 	%p22, %r100, 0;
	neg.f32 	%f344, %f343;
	selp.f32 	%f1151, %f343, %f344, %p22;

$L__BB0_16:
	add.s32 	%r31, %r356, 1;
	and.b32  	%r32, %r31, 1;
	setp.eq.s32 	%p23, %r32, 0;
	selp.f32 	%f62, %f1151, 0f3F800000, %p23;
	mul.rn.f32 	%f63, %f1151, %f1151;
	mov.f32 	%f1152, 0fB94D4153;
	@%p23 bra 	$L__BB0_18;

	mov.f32 	%f347, 0fBAB607ED;
	mov.f32 	%f348, 0f37CBAC00;
	fma.rn.f32 	%f1152, %f348, %f63, %f347;

$L__BB0_18:
	selp.f32 	%f349, 0f3C0885E4, 0f3D2AAABB, %p23;
	fma.rn.f32 	%f350, %f1152, %f63, %f349;
	selp.f32 	%f351, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
	fma.rn.f32 	%f352, %f350, %f63, %f351;
	mov.f32 	%f353, 0f00000000;
	fma.rn.f32 	%f354, %f63, %f62, %f353;
	fma.rn.f32 	%f1153, %f352, %f354, %f62;
	and.b32  	%r106, %r31, 2;
	setp.eq.s32 	%p25, %r106, 0;
	@%p25 bra 	$L__BB0_20;

	mov.f32 	%f356, 0fBF800000;
	fma.rn.f32 	%f1153, %f1153, %f356, %f353;

$L__BB0_20:
	mul.f32 	%f1072, %f56, 0f3F22F983;
	cvt.rni.s32.f32 	%r359, %f1072;
	setp.ltu.f32 	%p154, %f58, 0f47CE4780;
	@%p154 bra 	$L__BB0_28;

	setp.eq.f32 	%p27, %f58, 0f7F800000;
	@%p27 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f359, 0f00000000;
	mul.rn.f32 	%f1154, %f56, %f359;
	mov.u32 	%r359, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r33, %f56;
	bfe.u32 	%r107, %r33, 23, 8;
	add.s32 	%r34, %r107, -128;
	shl.b32 	%r108, %r33, 8;
	or.b32  	%r35, %r108, -2147483648;
	shr.u32 	%r36, %r34, 5;
	mov.u64 	%rd108, 0;
	mov.u64 	%rd109, %rd108;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd52, %rd108, 2;
	mov.u64 	%rd53, __cudart_i2opi_f;
	add.s64 	%rd54, %rd53, %rd52;
	ld.global.nc.u32 	%r109, [%rd54];
	mad.wide.u32 	%rd55, %r109, %r35, %rd109;
	shr.u64 	%rd109, %rd55, 32;
	add.s64 	%rd56, %rd1, %rd52;
	st.local.u32 	[%rd56], %rd55;
	cvt.u32.u64 	%r110, %rd108;
	add.s32 	%r111, %r110, 1;
	cvt.s64.s32 	%rd108, %r111;
	setp.ne.s32 	%p28, %r111, 6;
	@%p28 bra 	$L__BB0_23;

	st.local.u32 	[%rd6], %rd109;
	mov.u32 	%r112, 4;
	sub.s32 	%r37, %r112, %r36;
	mov.u32 	%r113, 6;
	sub.s32 	%r114, %r113, %r36;
	mul.wide.s32 	%rd57, %r114, 4;
	add.s64 	%rd58, %rd1, %rd57;
	ld.local.u32 	%r357, [%rd58];
	ld.local.u32 	%r358, [%rd58+-4];
	and.b32  	%r40, %r34, 31;
	setp.eq.s32 	%p29, %r40, 0;
	@%p29 bra 	$L__BB0_26;

	mov.u32 	%r115, 32;
	sub.s32 	%r116, %r115, %r40;
	shr.u32 	%r117, %r358, %r116;
	shl.b32 	%r118, %r357, %r40;
	add.s32 	%r357, %r117, %r118;
	mul.wide.s32 	%rd59, %r37, 4;
	add.s64 	%rd60, %rd1, %rd59;
	ld.local.u32 	%r119, [%rd60];
	shr.u32 	%r120, %r119, %r116;
	shl.b32 	%r121, %r358, %r40;
	add.s32 	%r358, %r120, %r121;

$L__BB0_26:
	and.b32  	%r122, %r33, -2147483648;
	shr.u32 	%r123, %r358, 30;
	shl.b32 	%r124, %r357, 2;
	or.b32  	%r125, %r123, %r124;
	shr.u32 	%r126, %r125, 31;
	shr.u32 	%r127, %r357, 30;
	add.s32 	%r128, %r126, %r127;
	neg.s32 	%r129, %r128;
	setp.eq.s32 	%p30, %r122, 0;
	selp.b32 	%r359, %r128, %r129, %p30;
	setp.ne.s32 	%p31, %r126, 0;
	xor.b32  	%r130, %r122, -2147483648;
	selp.b32 	%r131, %r130, %r122, %p31;
	selp.b32 	%r132, -1, 0, %p31;
	xor.b32  	%r133, %r125, %r132;
	shl.b32 	%r134, %r358, 2;
	xor.b32  	%r135, %r134, %r132;
	cvt.u64.u32 	%rd61, %r133;
	cvt.u64.u32 	%rd62, %r135;
	bfi.b64 	%rd63, %rd61, %rd62, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd63;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f357, %fd4;
	setp.eq.s32 	%p32, %r131, 0;
	neg.f32 	%f358, %f357;
	selp.f32 	%f1154, %f357, %f358, %p32;

$L__BB0_28:
	mul.f32 	%f72, %f55, %f1153;
	and.b32  	%r47, %r359, 1;
	setp.eq.s32 	%p33, %r47, 0;
	mul.rn.f32 	%f74, %f1154, %f1154;
	mov.f32 	%f1155, 0fB94D4153;
	@%p33 bra 	$L__BB0_30;

	mov.f32 	%f361, 0fBAB607ED;
	mov.f32 	%f362, 0f37CBAC00;
	fma.rn.f32 	%f1155, %f362, %f74, %f361;

$L__BB0_30:
	selp.f32 	%f1074, %f1154, 0f3F800000, %p33;
	selp.f32 	%f363, 0f3C0885E4, 0f3D2AAABB, %p33;
	fma.rn.f32 	%f364, %f1155, %f74, %f363;
	selp.f32 	%f365, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
	fma.rn.f32 	%f366, %f364, %f74, %f365;
	mov.f32 	%f367, 0f00000000;
	fma.rn.f32 	%f368, %f74, %f1074, %f367;
	fma.rn.f32 	%f1156, %f366, %f368, %f1074;
	and.b32  	%r137, %r359, 2;
	setp.eq.s32 	%p35, %r137, 0;
	@%p35 bra 	$L__BB0_32;

	mov.f32 	%f370, 0fBF800000;
	fma.rn.f32 	%f1156, %f1156, %f370, %f367;

$L__BB0_32:
	mul.f32 	%f371, %f55, %f1156;
	mul.f32 	%f372, %f13, %f371;
	mul.f32 	%f373, %f14, %f371;
	mul.f32 	%f374, %f15, %f371;
	fma.rn.f32 	%f375, %f22, %f72, %f372;
	fma.rn.f32 	%f376, %f21, %f72, %f373;
	fma.rn.f32 	%f377, %f20, %f72, %f374;
	fma.rn.f32 	%f80, %f1118, %f54, %f375;
	fma.rn.f32 	%f81, %f1119, %f54, %f376;
	fma.rn.f32 	%f82, %f1120, %f54, %f377;
	setp.leu.f32 	%p36, %f81, 0f00000000;
	setp.ne.s32 	%p37, %r7, 0;
	and.pred  	%p38, %p37, %p36;
	@%p38 bra 	$L__BB0_34;

	mov.f32 	%f392, 0f38D1B717;
	max.f32 	%f384, %f391, %f392;
	neg.f32 	%f393, %f80;
	neg.f32 	%f394, %f81;
	neg.f32 	%f395, %f82;
	tex.cube.v4.f32.f32 	{%f396, %f397, %f398, %f399}, [%rd4, {%f395, %f394, %f393, %f393}];
	mov.b32 	%r177, %f396;
	mov.b32 	%r178, %f397;
	mov.b32 	%r179, %f398;
	mov.f32 	%f385, 0f6C4ECB8F;
	mov.f32 	%f386, 0f00000000;
	mov.u32 	%r174, 2;
	mov.u32 	%r175, 1;
	mov.u32 	%r176, 3;
	mov.u32 	%r208, 0;
	// begin inline asm
	call(%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169),_optix_trace_typed_32,(%r208,%rd5,%f10,%f11,%f12,%f80,%f81,%f82,%f384,%f385,%f386,%r175,%r208,%r175,%r174,%r175,%r176,%r177,%r178,%r179,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208);
	// end inline asm
	mov.b32 	%f400, %r138;
	mov.b32 	%f401, %r139;
	mov.b32 	%f402, %r140;
	mul.f32 	%f403, %f1119, %f81;
	fma.rn.f32 	%f404, %f1118, %f80, %f403;
	fma.rn.f32 	%f405, %f1120, %f82, %f404;
	fma.rn.f32 	%f1163, %f80, %f400, %f1163;
	fma.rn.f32 	%f1164, %f80, %f401, %f1164;
	fma.rn.f32 	%f1165, %f80, %f402, %f1165;
	fma.rn.f32 	%f1160, %f81, %f400, %f1160;
	fma.rn.f32 	%f1161, %f81, %f401, %f1161;
	fma.rn.f32 	%f1162, %f81, %f402, %f1162;
	fma.rn.f32 	%f1157, %f82, %f400, %f1157;
	fma.rn.f32 	%f1158, %f82, %f401, %f1158;
	fma.rn.f32 	%f1159, %f82, %f402, %f1159;
	add.f32 	%f1166, %f1166, %f400;
	add.f32 	%f1167, %f1167, %f401;
	add.f32 	%f1168, %f1168, %f402;
	cvt.sat.f32.f32 	%f406, %f405;
	fma.rn.f32 	%f1169, %f406, %f400, %f1169;
	fma.rn.f32 	%f1170, %f406, %f401, %f1170;
	fma.rn.f32 	%f1171, %f406, %f402, %f1171;

$L__BB0_34:
	add.s32 	%r351, %r351, 1;
	setp.lt.s32 	%p39, %r351, %r4;
	@%p39 bra 	$L__BB0_8;

	add.s32 	%r349, %r349, 1;
	setp.lt.s32 	%p40, %r349, %r4;
	@%p40 bra 	$L__BB0_7;

$L__BB0_36:
	mul.lo.s32 	%r209, %r4, %r4;
	cvt.rn.f32.s32 	%f407, %r209;
	rcp.rn.f32 	%f408, %f407;
	mul.f32 	%f409, %f408, %f1169;
	mul.f32 	%f410, %f408, %f1170;
	mul.f32 	%f411, %f408, %f1171;
	mul.f32 	%f128, %f408, %f1166;
	mul.f32 	%f129, %f408, %f1167;
	mul.f32 	%f130, %f408, %f1168;
	mul.f32 	%f131, %f408, %f1163;
	mul.f32 	%f132, %f408, %f1164;
	mul.f32 	%f133, %f408, %f1165;
	mul.f32 	%f134, %f408, %f1160;
	mul.f32 	%f135, %f408, %f1161;
	mul.f32 	%f136, %f408, %f1162;
	mul.f32 	%f137, %f408, %f1157;
	mul.f32 	%f138, %f408, %f1158;
	mul.f32 	%f139, %f408, %f1159;
	fma.rn.f32 	%f412, %f408, %f1169, %f409;
	fma.rn.f32 	%f413, %f408, %f1170, %f410;
	fma.rn.f32 	%f414, %f408, %f1171, %f411;
	ld.const.v4.f32 	{%f415, %f416, %f417, %f418}, [params+576];
	mul.f32 	%f143, %f412, %f415;
	mul.f32 	%f144, %f413, %f416;
	mul.f32 	%f145, %f414, %f417;
	ld.const.u32 	%r50, [params+104];
	and.b32  	%r210, %r50, 1;
	setp.eq.b32 	%p41, %r210, 1;
	mov.pred 	%p42, 0;
	xor.pred  	%p43, %p41, %p42;
	not.pred 	%p44, %p43;
	@%p44 bra 	$L__BB0_110;

	mov.f32 	%f420, 0f3E666666;
	cvt.rzi.f32.f32 	%f421, %f420;
	add.f32 	%f422, %f421, %f421;
	mov.f32 	%f423, 0f3EE66666;
	sub.f32 	%f424, %f423, %f422;
	abs.f32 	%f146, %f424;
	abs.f32 	%f147, %f143;
	setp.lt.f32 	%p45, %f147, 0f00800000;
	mul.f32 	%f425, %f147, 0f4B800000;
	selp.f32 	%f426, %f425, %f147, %p45;
	selp.f32 	%f427, 0fC3170000, 0fC2FE0000, %p45;
	mov.b32 	%r211, %f426;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f428, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f429, %r214;
	add.f32 	%f430, %f427, %f429;
	setp.gt.f32 	%p46, %f428, 0f3FB504F3;
	mul.f32 	%f431, %f428, 0f3F000000;
	add.f32 	%f432, %f430, 0f3F800000;
	selp.f32 	%f433, %f432, %f430, %p46;
	selp.f32 	%f434, %f431, %f428, %p46;
	add.f32 	%f435, %f434, 0fBF800000;
	add.f32 	%f436, %f434, 0f3F800000;
	rcp.approx.ftz.f32 	%f437, %f436;
	add.f32 	%f438, %f435, %f435;
	mul.f32 	%f439, %f438, %f437;
	mul.f32 	%f440, %f439, %f439;
	mov.f32 	%f441, 0f3C4CAF63;
	mov.f32 	%f442, 0f3B18F0FE;
	fma.rn.f32 	%f443, %f442, %f440, %f441;
	mov.f32 	%f444, 0f3DAAAABD;
	fma.rn.f32 	%f445, %f443, %f440, %f444;
	mul.rn.f32 	%f446, %f445, %f440;
	mul.rn.f32 	%f447, %f446, %f439;
	sub.f32 	%f448, %f435, %f439;
	add.f32 	%f449, %f448, %f448;
	neg.f32 	%f450, %f439;
	fma.rn.f32 	%f451, %f450, %f435, %f449;
	mul.rn.f32 	%f452, %f437, %f451;
	add.f32 	%f453, %f447, %f439;
	sub.f32 	%f454, %f439, %f453;
	add.f32 	%f455, %f447, %f454;
	add.f32 	%f456, %f452, %f455;
	add.f32 	%f457, %f453, %f456;
	sub.f32 	%f458, %f453, %f457;
	add.f32 	%f459, %f456, %f458;
	mov.f32 	%f460, 0f3F317200;
	mul.rn.f32 	%f461, %f433, %f460;
	mov.f32 	%f462, 0f35BFBE8E;
	mul.rn.f32 	%f463, %f433, %f462;
	add.f32 	%f464, %f461, %f457;
	sub.f32 	%f465, %f461, %f464;
	add.f32 	%f466, %f457, %f465;
	add.f32 	%f467, %f459, %f466;
	add.f32 	%f468, %f463, %f467;
	add.f32 	%f469, %f464, %f468;
	sub.f32 	%f470, %f464, %f469;
	add.f32 	%f471, %f468, %f470;
	mul.rn.f32 	%f472, %f423, %f469;
	neg.f32 	%f473, %f472;
	fma.rn.f32 	%f474, %f423, %f469, %f473;
	fma.rn.f32 	%f475, %f423, %f471, %f474;
	mov.f32 	%f476, 0f00000000;
	fma.rn.f32 	%f477, %f476, %f469, %f475;
	add.rn.f32 	%f478, %f472, %f477;
	neg.f32 	%f479, %f478;
	add.rn.f32 	%f480, %f472, %f479;
	add.rn.f32 	%f481, %f480, %f477;
	mov.b32 	%r215, %f478;
	setp.eq.s32 	%p47, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f482, %r216;
	add.f32 	%f483, %f481, 0f37000000;
	selp.f32 	%f148, %f483, %f481, %p47;
	selp.f32 	%f484, %f482, %f478, %p47;
	mov.f32 	%f485, 0f3FB8AA3B;
	mul.rn.f32 	%f486, %f484, %f485;
	cvt.rzi.f32.f32 	%f487, %f486;
	abs.f32 	%f488, %f487;
	setp.gt.f32 	%p48, %f488, 0f42FC0000;
	mov.b32 	%r217, %f487;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f489, %r219;
	selp.f32 	%f490, %f489, %f487, %p48;
	mov.f32 	%f491, 0fBF317218;
	fma.rn.f32 	%f492, %f490, %f491, %f484;
	mov.f32 	%f493, 0f3102E308;
	fma.rn.f32 	%f494, %f490, %f493, %f492;
	mul.f32 	%f495, %f494, 0f3FB8AA3B;
	add.f32 	%f496, %f490, 0f4B40007F;
	mov.b32 	%r220, %f496;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f497, %r221;
	ex2.approx.ftz.f32 	%f498, %f495;
	mul.f32 	%f149, %f498, %f497;
	setp.eq.f32 	%p49, %f149, 0f7F800000;
	mov.f32 	%f1187, 0f7F800000;
	@%p49 bra 	$L__BB0_39;

	fma.rn.f32 	%f1187, %f149, %f148, %f149;

$L__BB0_39:
	setp.lt.f32 	%p50, %f143, 0f00000000;
	setp.eq.f32 	%p51, %f146, 0f3F800000;
	and.pred  	%p1, %p50, %p51;
	setp.eq.f32 	%p52, %f143, 0f00000000;
	@%p52 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f503, %f143, %f143;
	selp.f32 	%f1189, %f503, 0f00000000, %p51;
	bra.uni 	$L__BB0_44;

$L__BB0_131:
	mov.f32 	%f1035, 0f00000000;
	mov.u32 	%r361, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1035;}

	// end inline asm
	mov.u16 	%rs109, 0;
	st.global.v4.u16 	[%rd24], {%rs106, %rs107, %rs108, %rs109};

$L__BB0_132:
	ld.const.u64 	%rd90, [params+256];
	cvta.to.global.u64 	%rd91, %rd90;
	ld.const.u32 	%r322, [params+248];
	mad.lo.s32 	%r323, %r322, %r6, %r5;
	mul.wide.u32 	%rd92, %r323, 8;
	add.s64 	%rd25, %rd91, %rd92;
	setp.eq.s32 	%p150, %r361, 0;
	@%p150 bra 	$L__BB0_134;

	ld.global.v4.u16 	{%rs116, %rs117, %rs118, %rs119}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1036, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1037, %rs117;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1038, %rs118;}

	// end inline asm
	add.f32 	%f1039, %f1036, 0f00000000;
	add.f32 	%f1040, %f1037, 0f00000000;
	add.f32 	%f1041, %f1038, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1039;}

	// end inline asm
	mov.u16 	%rs120, 0;
	st.global.v4.u16 	[%rd25], {%rs113, %rs114, %rs115, %rs120};
	bra.uni 	$L__BB0_135;

$L__BB0_134:
	mov.f32 	%f1044, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f1044;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1044;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1044;}

	// end inline asm
	mov.u16 	%rs124, 0;
	st.global.v4.u16 	[%rd25], {%rs121, %rs122, %rs123, %rs124};

$L__BB0_135:
	ld.const.u64 	%rd93, [params+272];
	cvta.to.global.u64 	%rd94, %rd93;
	ld.const.u32 	%r324, [params+264];
	mad.lo.s32 	%r325, %r324, %r6, %r5;
	mul.wide.u32 	%rd95, %r325, 8;
	add.s64 	%rd26, %rd94, %rd95;
	@%p150 bra 	$L__BB0_137;

	ld.global.v4.u16 	{%rs131, %rs132, %rs133, %rs134}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1045, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1046, %rs132;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1047, %rs133;}

	// end inline asm
	add.f32 	%f1048, %f1045, 0f00000000;
	add.f32 	%f1049, %f1046, 0f00000000;
	add.f32 	%f1050, %f1047, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1050;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1049;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1048;}

	// end inline asm
	mov.u16 	%rs135, 0;
	st.global.v4.u16 	[%rd26], {%rs128, %rs129, %rs130, %rs135};
	bra.uni 	$L__BB0_138;

$L__BB0_137:
	mov.f32 	%f1053, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f1053;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1053;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1053;}

	// end inline asm
	mov.u16 	%rs139, 0;
	st.global.v4.u16 	[%rd26], {%rs136, %rs137, %rs138, %rs139};

$L__BB0_138:
	ld.const.u64 	%rd96, [params+288];
	cvta.to.global.u64 	%rd97, %rd96;
	ld.const.u32 	%r326, [params+280];
	mad.lo.s32 	%r327, %r326, %r6, %r5;
	mul.wide.u32 	%rd98, %r327, 8;
	add.s64 	%rd27, %rd97, %rd98;
	@%p150 bra 	$L__BB0_140;

	ld.global.v4.u16 	{%rs146, %rs147, %rs148, %rs149}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1054, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1055, %rs147;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1056, %rs148;}

	// end inline asm
	add.f32 	%f1057, %f1054, 0f00000000;
	add.f32 	%f1058, %f1055, 0f00000000;
	add.f32 	%f1059, %f1056, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1059;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1058;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1057;}

	// end inline asm
	mov.u16 	%rs150, 0;
	st.global.v4.u16 	[%rd27], {%rs143, %rs144, %rs145, %rs150};
	bra.uni 	$L__BB0_141;

$L__BB0_140:
	mov.f32 	%f1062, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f1062;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1062;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1062;}

	// end inline asm
	mov.u16 	%rs154, 0;
	st.global.v4.u16 	[%rd27], {%rs151, %rs152, %rs153, %rs154};

$L__BB0_141:
	ld.const.u64 	%rd99, [params+304];
	cvta.to.global.u64 	%rd100, %rd99;
	ld.const.u32 	%r328, [params+296];
	mad.lo.s32 	%r329, %r328, %r6, %r5;
	mul.wide.u32 	%rd101, %r329, 8;
	add.s64 	%rd28, %rd100, %rd101;
	@%p150 bra 	$L__BB0_143;

	ld.global.v4.u16 	{%rs161, %rs162, %rs163, %rs164}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1063, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1064, %rs162;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1065, %rs163;}

	// end inline asm
	add.f32 	%f1066, %f1063, 0f00000000;
	add.f32 	%f1067, %f1064, 0f00000000;
	add.f32 	%f1068, %f1065, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1068;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1067;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1066;}

	// end inline asm
	mov.u16 	%rs165, 0;
	st.global.v4.u16 	[%rd28], {%rs158, %rs159, %rs160, %rs165};
	bra.uni 	$L__BB0_144;

$L__BB0_143:
	mov.f32 	%f1071, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f1071;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1071;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1071;}

	// end inline asm
	mov.u16 	%rs169, 0;
	st.global.v4.u16 	[%rd28], {%rs166, %rs167, %rs168, %rs169};
	bra.uni 	$L__BB0_144;

$L__BB0_40:
	mov.b32 	%r222, %f1187;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f499, %r223;
	selp.f32 	%f1189, %f499, %f1187, %p1;
	setp.geu.f32 	%p53, %f143, 0f00000000;
	@%p53 bra 	$L__BB0_44;

	mov.f32 	%f500, 0f3EE66666;
	cvt.rzi.f32.f32 	%f501, %f500;
	setp.eq.f32 	%p54, %f501, 0f3EE66666;
	@%p54 bra 	$L__BB0_44;

	mov.f32 	%f1189, 0f7FFFFFFF;

$L__BB0_44:
	add.f32 	%f504, %f147, 0f3EE66666;
	mov.b32 	%r224, %f504;
	setp.lt.s32 	%p56, %r224, 2139095040;
	@%p56 bra 	$L__BB0_49;

	setp.gtu.f32 	%p57, %f147, 0f7F800000;
	@%p57 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1189, %f143, 0f3EE66666;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	setp.neu.f32 	%p58, %f147, 0f7F800000;
	@%p58 bra 	$L__BB0_49;

	selp.f32 	%f1189, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	setp.eq.f32 	%p59, %f143, 0f3F800000;
	selp.f32 	%f158, 0f3F800000, %f1189, %p59;
	abs.f32 	%f159, %f144;
	setp.lt.f32 	%p60, %f159, 0f00800000;
	mul.f32 	%f506, %f159, 0f4B800000;
	selp.f32 	%f507, %f506, %f159, %p60;
	selp.f32 	%f508, 0fC3170000, 0fC2FE0000, %p60;
	mov.b32 	%r225, %f507;
	and.b32  	%r226, %r225, 8388607;
	or.b32  	%r227, %r226, 1065353216;
	mov.b32 	%f509, %r227;
	shr.u32 	%r228, %r225, 23;
	cvt.rn.f32.u32 	%f510, %r228;
	add.f32 	%f511, %f508, %f510;
	setp.gt.f32 	%p61, %f509, 0f3FB504F3;
	mul.f32 	%f512, %f509, 0f3F000000;
	add.f32 	%f513, %f511, 0f3F800000;
	selp.f32 	%f514, %f513, %f511, %p61;
	selp.f32 	%f515, %f512, %f509, %p61;
	add.f32 	%f516, %f515, 0fBF800000;
	add.f32 	%f517, %f515, 0f3F800000;
	rcp.approx.ftz.f32 	%f518, %f517;
	add.f32 	%f519, %f516, %f516;
	mul.f32 	%f520, %f519, %f518;
	mul.f32 	%f521, %f520, %f520;
	mov.f32 	%f522, 0f3C4CAF63;
	mov.f32 	%f523, 0f3B18F0FE;
	fma.rn.f32 	%f524, %f523, %f521, %f522;
	mov.f32 	%f525, 0f3DAAAABD;
	fma.rn.f32 	%f526, %f524, %f521, %f525;
	mul.rn.f32 	%f527, %f526, %f521;
	mul.rn.f32 	%f528, %f527, %f520;
	sub.f32 	%f529, %f516, %f520;
	add.f32 	%f530, %f529, %f529;
	neg.f32 	%f531, %f520;
	fma.rn.f32 	%f532, %f531, %f516, %f530;
	mul.rn.f32 	%f533, %f518, %f532;
	add.f32 	%f534, %f528, %f520;
	sub.f32 	%f535, %f520, %f534;
	add.f32 	%f536, %f528, %f535;
	add.f32 	%f537, %f533, %f536;
	add.f32 	%f538, %f534, %f537;
	sub.f32 	%f539, %f534, %f538;
	add.f32 	%f540, %f537, %f539;
	mov.f32 	%f541, 0f3F317200;
	mul.rn.f32 	%f542, %f514, %f541;
	mov.f32 	%f543, 0f35BFBE8E;
	mul.rn.f32 	%f544, %f514, %f543;
	add.f32 	%f545, %f542, %f538;
	sub.f32 	%f546, %f542, %f545;
	add.f32 	%f547, %f538, %f546;
	add.f32 	%f548, %f540, %f547;
	add.f32 	%f549, %f544, %f548;
	add.f32 	%f550, %f545, %f549;
	sub.f32 	%f551, %f545, %f550;
	add.f32 	%f552, %f549, %f551;
	mov.f32 	%f553, 0f3EE66666;
	mul.rn.f32 	%f554, %f553, %f550;
	neg.f32 	%f555, %f554;
	fma.rn.f32 	%f556, %f553, %f550, %f555;
	fma.rn.f32 	%f557, %f553, %f552, %f556;
	mov.f32 	%f558, 0f00000000;
	fma.rn.f32 	%f559, %f558, %f550, %f557;
	add.rn.f32 	%f560, %f554, %f559;
	neg.f32 	%f561, %f560;
	add.rn.f32 	%f562, %f554, %f561;
	add.rn.f32 	%f563, %f562, %f559;
	mov.b32 	%r229, %f560;
	setp.eq.s32 	%p62, %r229, 1118925336;
	add.s32 	%r230, %r229, -1;
	mov.b32 	%f564, %r230;
	add.f32 	%f565, %f563, 0f37000000;
	selp.f32 	%f160, %f565, %f563, %p62;
	selp.f32 	%f566, %f564, %f560, %p62;
	mov.f32 	%f567, 0f3FB8AA3B;
	mul.rn.f32 	%f568, %f566, %f567;
	cvt.rzi.f32.f32 	%f569, %f568;
	abs.f32 	%f570, %f569;
	setp.gt.f32 	%p63, %f570, 0f42FC0000;
	mov.b32 	%r231, %f569;
	and.b32  	%r232, %r231, -2147483648;
	or.b32  	%r233, %r232, 1123811328;
	mov.b32 	%f571, %r233;
	selp.f32 	%f572, %f571, %f569, %p63;
	mov.f32 	%f573, 0fBF317218;
	fma.rn.f32 	%f574, %f572, %f573, %f566;
	mov.f32 	%f575, 0f3102E308;
	fma.rn.f32 	%f576, %f572, %f575, %f574;
	mul.f32 	%f577, %f576, 0f3FB8AA3B;
	add.f32 	%f578, %f572, 0f4B40007F;
	mov.b32 	%r234, %f578;
	shl.b32 	%r235, %r234, 23;
	mov.b32 	%f579, %r235;
	ex2.approx.ftz.f32 	%f580, %f577;
	mul.f32 	%f161, %f580, %f579;
	setp.eq.f32 	%p64, %f161, 0f7F800000;
	mov.f32 	%f1190, 0f7F800000;
	@%p64 bra 	$L__BB0_51;

	fma.rn.f32 	%f1190, %f161, %f160, %f161;

$L__BB0_51:
	setp.lt.f32 	%p65, %f144, 0f00000000;
	and.pred  	%p2, %p65, %p51;
	setp.eq.f32 	%p67, %f144, 0f00000000;
	@%p67 bra 	$L__BB0_55;
	bra.uni 	$L__BB0_52;

$L__BB0_55:
	add.f32 	%f585, %f144, %f144;
	selp.f32 	%f1192, %f585, 0f00000000, %p51;
	bra.uni 	$L__BB0_56;

$L__BB0_52:
	mov.b32 	%r236, %f1190;
	xor.b32  	%r237, %r236, -2147483648;
	mov.b32 	%f581, %r237;
	selp.f32 	%f1192, %f581, %f1190, %p2;
	setp.geu.f32 	%p68, %f144, 0f00000000;
	@%p68 bra 	$L__BB0_56;

	mov.f32 	%f582, 0f3EE66666;
	cvt.rzi.f32.f32 	%f583, %f582;
	setp.eq.f32 	%p69, %f583, 0f3EE66666;
	@%p69 bra 	$L__BB0_56;

	mov.f32 	%f1192, 0f7FFFFFFF;

$L__BB0_56:
	add.f32 	%f586, %f159, 0f3EE66666;
	mov.b32 	%r238, %f586;
	setp.lt.s32 	%p71, %r238, 2139095040;
	@%p71 bra 	$L__BB0_61;

	setp.gtu.f32 	%p72, %f159, 0f7F800000;
	@%p72 bra 	$L__BB0_60;
	bra.uni 	$L__BB0_58;

$L__BB0_60:
	add.f32 	%f1192, %f144, 0f3EE66666;
	bra.uni 	$L__BB0_61;

$L__BB0_58:
	setp.neu.f32 	%p73, %f159, 0f7F800000;
	@%p73 bra 	$L__BB0_61;

	selp.f32 	%f1192, 0fFF800000, 0f7F800000, %p2;

$L__BB0_61:
	setp.eq.f32 	%p74, %f144, 0f3F800000;
	selp.f32 	%f170, 0f3F800000, %f1192, %p74;
	abs.f32 	%f171, %f145;
	setp.lt.f32 	%p75, %f171, 0f00800000;
	mul.f32 	%f588, %f171, 0f4B800000;
	selp.f32 	%f589, %f588, %f171, %p75;
	selp.f32 	%f590, 0fC3170000, 0fC2FE0000, %p75;
	mov.b32 	%r239, %f589;
	and.b32  	%r240, %r239, 8388607;
	or.b32  	%r241, %r240, 1065353216;
	mov.b32 	%f591, %r241;
	shr.u32 	%r242, %r239, 23;
	cvt.rn.f32.u32 	%f592, %r242;
	add.f32 	%f593, %f590, %f592;
	setp.gt.f32 	%p76, %f591, 0f3FB504F3;
	mul.f32 	%f594, %f591, 0f3F000000;
	add.f32 	%f595, %f593, 0f3F800000;
	selp.f32 	%f596, %f595, %f593, %p76;
	selp.f32 	%f597, %f594, %f591, %p76;
	add.f32 	%f598, %f597, 0fBF800000;
	add.f32 	%f599, %f597, 0f3F800000;
	rcp.approx.ftz.f32 	%f600, %f599;
	add.f32 	%f601, %f598, %f598;
	mul.f32 	%f602, %f601, %f600;
	mul.f32 	%f603, %f602, %f602;
	mov.f32 	%f604, 0f3C4CAF63;
	mov.f32 	%f605, 0f3B18F0FE;
	fma.rn.f32 	%f606, %f605, %f603, %f604;
	mov.f32 	%f607, 0f3DAAAABD;
	fma.rn.f32 	%f608, %f606, %f603, %f607;
	mul.rn.f32 	%f609, %f608, %f603;
	mul.rn.f32 	%f610, %f609, %f602;
	sub.f32 	%f611, %f598, %f602;
	add.f32 	%f612, %f611, %f611;
	neg.f32 	%f613, %f602;
	fma.rn.f32 	%f614, %f613, %f598, %f612;
	mul.rn.f32 	%f615, %f600, %f614;
	add.f32 	%f616, %f610, %f602;
	sub.f32 	%f617, %f602, %f616;
	add.f32 	%f618, %f610, %f617;
	add.f32 	%f619, %f615, %f618;
	add.f32 	%f620, %f616, %f619;
	sub.f32 	%f621, %f616, %f620;
	add.f32 	%f622, %f619, %f621;
	mov.f32 	%f623, 0f3F317200;
	mul.rn.f32 	%f624, %f596, %f623;
	mov.f32 	%f625, 0f35BFBE8E;
	mul.rn.f32 	%f626, %f596, %f625;
	add.f32 	%f627, %f624, %f620;
	sub.f32 	%f628, %f624, %f627;
	add.f32 	%f629, %f620, %f628;
	add.f32 	%f630, %f622, %f629;
	add.f32 	%f631, %f626, %f630;
	add.f32 	%f632, %f627, %f631;
	sub.f32 	%f633, %f627, %f632;
	add.f32 	%f634, %f631, %f633;
	mov.f32 	%f635, 0f3EE66666;
	mul.rn.f32 	%f636, %f635, %f632;
	neg.f32 	%f637, %f636;
	fma.rn.f32 	%f638, %f635, %f632, %f637;
	fma.rn.f32 	%f639, %f635, %f634, %f638;
	mov.f32 	%f640, 0f00000000;
	fma.rn.f32 	%f641, %f640, %f632, %f639;
	add.rn.f32 	%f642, %f636, %f641;
	neg.f32 	%f643, %f642;
	add.rn.f32 	%f644, %f636, %f643;
	add.rn.f32 	%f645, %f644, %f641;
	mov.b32 	%r243, %f642;
	setp.eq.s32 	%p77, %r243, 1118925336;
	add.s32 	%r244, %r243, -1;
	mov.b32 	%f646, %r244;
	add.f32 	%f647, %f645, 0f37000000;
	selp.f32 	%f172, %f647, %f645, %p77;
	selp.f32 	%f648, %f646, %f642, %p77;
	mov.f32 	%f649, 0f3FB8AA3B;
	mul.rn.f32 	%f650, %f648, %f649;
	cvt.rzi.f32.f32 	%f651, %f650;
	abs.f32 	%f652, %f651;
	setp.gt.f32 	%p78, %f652, 0f42FC0000;
	mov.b32 	%r245, %f651;
	and.b32  	%r246, %r245, -2147483648;
	or.b32  	%r247, %r246, 1123811328;
	mov.b32 	%f653, %r247;
	selp.f32 	%f654, %f653, %f651, %p78;
	mov.f32 	%f655, 0fBF317218;
	fma.rn.f32 	%f656, %f654, %f655, %f648;
	mov.f32 	%f657, 0f3102E308;
	fma.rn.f32 	%f658, %f654, %f657, %f656;
	mul.f32 	%f659, %f658, 0f3FB8AA3B;
	add.f32 	%f660, %f654, 0f4B40007F;
	mov.b32 	%r248, %f660;
	shl.b32 	%r249, %r248, 23;
	mov.b32 	%f661, %r249;
	ex2.approx.ftz.f32 	%f662, %f659;
	mul.f32 	%f173, %f662, %f661;
	setp.eq.f32 	%p79, %f173, 0f7F800000;
	mov.f32 	%f1193, 0f7F800000;
	@%p79 bra 	$L__BB0_63;

	fma.rn.f32 	%f1193, %f173, %f172, %f173;

$L__BB0_63:
	setp.lt.f32 	%p80, %f145, 0f00000000;
	and.pred  	%p3, %p80, %p51;
	setp.eq.f32 	%p82, %f145, 0f00000000;
	@%p82 bra 	$L__BB0_67;
	bra.uni 	$L__BB0_64;

$L__BB0_67:
	add.f32 	%f667, %f145, %f145;
	selp.f32 	%f1195, %f667, 0f00000000, %p51;
	bra.uni 	$L__BB0_68;

$L__BB0_64:
	mov.b32 	%r250, %f1193;
	xor.b32  	%r251, %r250, -2147483648;
	mov.b32 	%f663, %r251;
	selp.f32 	%f1195, %f663, %f1193, %p3;
	setp.geu.f32 	%p83, %f145, 0f00000000;
	@%p83 bra 	$L__BB0_68;

	mov.f32 	%f664, 0f3EE66666;
	cvt.rzi.f32.f32 	%f665, %f664;
	setp.eq.f32 	%p84, %f665, 0f3EE66666;
	@%p84 bra 	$L__BB0_68;

	mov.f32 	%f1195, 0f7FFFFFFF;

$L__BB0_68:
	add.f32 	%f668, %f171, 0f3EE66666;
	mov.b32 	%r252, %f668;
	setp.lt.s32 	%p86, %r252, 2139095040;
	@%p86 bra 	$L__BB0_73;

	setp.gtu.f32 	%p87, %f171, 0f7F800000;
	@%p87 bra 	$L__BB0_72;
	bra.uni 	$L__BB0_70;

$L__BB0_72:
	add.f32 	%f1195, %f145, 0f3EE66666;
	bra.uni 	$L__BB0_73;

$L__BB0_70:
	setp.neu.f32 	%p88, %f171, 0f7F800000;
	@%p88 bra 	$L__BB0_73;

	selp.f32 	%f1195, 0fFF800000, 0f7F800000, %p3;

$L__BB0_73:
	setp.eq.f32 	%p89, %f145, 0f3F800000;
	mov.f32 	%f670, 0f3F800000;
	selp.f32 	%f671, 0f3F800000, %f1195, %p89;
	min.f32 	%f672, %f158, %f670;
	mov.f32 	%f673, 0f00000000;
	max.f32 	%f182, %f673, %f672;
	min.f32 	%f674, %f170, %f670;
	max.f32 	%f183, %f673, %f674;
	min.f32 	%f675, %f671, %f670;
	max.f32 	%f184, %f673, %f675;
	mov.f32 	%f679, 0f3ED55555;
	abs.f32 	%f186, %f182;
	setp.lt.f32 	%p90, %f186, 0f00800000;
	mul.f32 	%f681, %f186, 0f4B800000;
	selp.f32 	%f682, %f681, %f186, %p90;
	selp.f32 	%f683, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r255, %f682;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f684, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f685, %r258;
	add.f32 	%f686, %f683, %f685;
	setp.gt.f32 	%p91, %f684, 0f3FB504F3;
	mul.f32 	%f687, %f684, 0f3F000000;
	add.f32 	%f688, %f686, 0f3F800000;
	selp.f32 	%f689, %f688, %f686, %p91;
	selp.f32 	%f690, %f687, %f684, %p91;
	add.f32 	%f691, %f690, 0fBF800000;
	add.f32 	%f692, %f690, 0f3F800000;
	rcp.approx.ftz.f32 	%f693, %f692;
	add.f32 	%f694, %f691, %f691;
	mul.f32 	%f695, %f694, %f693;
	mul.f32 	%f696, %f695, %f695;
	mov.f32 	%f697, 0f3C4CAF63;
	mov.f32 	%f698, 0f3B18F0FE;
	fma.rn.f32 	%f699, %f698, %f696, %f697;
	mov.f32 	%f700, 0f3DAAAABD;
	fma.rn.f32 	%f701, %f699, %f696, %f700;
	mul.rn.f32 	%f702, %f701, %f696;
	mul.rn.f32 	%f703, %f702, %f695;
	sub.f32 	%f704, %f691, %f695;
	add.f32 	%f705, %f704, %f704;
	neg.f32 	%f706, %f695;
	fma.rn.f32 	%f707, %f706, %f691, %f705;
	mul.rn.f32 	%f708, %f693, %f707;
	add.f32 	%f709, %f703, %f695;
	sub.f32 	%f710, %f695, %f709;
	add.f32 	%f711, %f703, %f710;
	add.f32 	%f712, %f708, %f711;
	add.f32 	%f713, %f709, %f712;
	sub.f32 	%f714, %f709, %f713;
	add.f32 	%f715, %f712, %f714;
	mov.f32 	%f716, 0f3F317200;
	mul.rn.f32 	%f717, %f689, %f716;
	mov.f32 	%f718, 0f35BFBE8E;
	mul.rn.f32 	%f719, %f689, %f718;
	add.f32 	%f720, %f717, %f713;
	sub.f32 	%f721, %f717, %f720;
	add.f32 	%f722, %f713, %f721;
	add.f32 	%f723, %f715, %f722;
	add.f32 	%f724, %f719, %f723;
	add.f32 	%f725, %f720, %f724;
	sub.f32 	%f726, %f720, %f725;
	add.f32 	%f727, %f724, %f726;
	mul.rn.f32 	%f728, %f679, %f725;
	neg.f32 	%f729, %f728;
	fma.rn.f32 	%f730, %f679, %f725, %f729;
	fma.rn.f32 	%f731, %f679, %f727, %f730;
	fma.rn.f32 	%f732, %f673, %f725, %f731;
	add.rn.f32 	%f733, %f728, %f732;
	neg.f32 	%f734, %f733;
	add.rn.f32 	%f735, %f728, %f734;
	add.rn.f32 	%f736, %f735, %f732;
	mov.b32 	%r259, %f733;
	setp.eq.s32 	%p92, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f737, %r260;
	add.f32 	%f738, %f736, 0f37000000;
	selp.f32 	%f187, %f738, %f736, %p92;
	selp.f32 	%f739, %f737, %f733, %p92;
	mov.f32 	%f740, 0f3FB8AA3B;
	mul.rn.f32 	%f741, %f739, %f740;
	cvt.rzi.f32.f32 	%f742, %f741;
	abs.f32 	%f743, %f742;
	setp.gt.f32 	%p93, %f743, 0f42FC0000;
	mov.b32 	%r261, %f742;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f744, %r263;
	selp.f32 	%f745, %f744, %f742, %p93;
	mov.f32 	%f746, 0fBF317218;
	fma.rn.f32 	%f747, %f745, %f746, %f739;
	mov.f32 	%f748, 0f3102E308;
	fma.rn.f32 	%f749, %f745, %f748, %f747;
	mul.f32 	%f750, %f749, 0f3FB8AA3B;
	add.f32 	%f751, %f745, 0f4B40007F;
	mov.b32 	%r264, %f751;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f752, %r265;
	ex2.approx.ftz.f32 	%f753, %f750;
	mul.f32 	%f188, %f753, %f752;
	setp.eq.f32 	%p94, %f188, 0f7F800000;
	mov.f32 	%f1196, 0f7F800000;
	@%p94 bra 	$L__BB0_75;

	fma.rn.f32 	%f1196, %f188, %f187, %f188;

$L__BB0_75:
	mov.f32 	%f1100, 0f00000000;
	max.f32 	%f1099, %f1100, %f672;
	mov.f32 	%f1080, 0f3E555555;
	cvt.rzi.f32.f32 	%f1079, %f1080;
	add.f32 	%f1078, %f1079, %f1079;
	mov.f32 	%f1077, 0f3ED55555;
	sub.f32 	%f1076, %f1077, %f1078;
	abs.f32 	%f1075, %f1076;
	setp.lt.f32 	%p95, %f1099, 0f00000000;
	setp.eq.f32 	%p96, %f1075, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f1099, 0f00000000;
	@%p97 bra 	$L__BB0_79;
	bra.uni 	$L__BB0_76;

$L__BB0_79:
	mov.f32 	%f1117, 0f00000000;
	max.f32 	%f1116, %f1117, %f672;
	add.f32 	%f758, %f1116, %f1116;
	selp.f32 	%f1198, %f758, 0f00000000, %p96;
	bra.uni 	$L__BB0_80;

$L__BB0_76:
	mov.f32 	%f1102, 0f00000000;
	max.f32 	%f1101, %f1102, %f672;
	mov.b32 	%r266, %f1196;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f754, %r267;
	selp.f32 	%f1198, %f754, %f1196, %p4;
	setp.geu.f32 	%p98, %f1101, 0f00000000;
	@%p98 bra 	$L__BB0_80;

	mov.f32 	%f755, 0f3ED55555;
	cvt.rzi.f32.f32 	%f756, %f755;
	setp.eq.f32 	%p99, %f756, 0f3ED55555;
	@%p99 bra 	$L__BB0_80;

	mov.f32 	%f1198, 0f7FFFFFFF;

$L__BB0_80:
	mov.f32 	%f1105, 0f00000000;
	max.f32 	%f1104, %f1105, %f672;
	abs.f32 	%f1103, %f1104;
	add.f32 	%f759, %f1103, 0f3ED55555;
	mov.b32 	%r268, %f759;
	setp.lt.s32 	%p101, %r268, 2139095040;
	@%p101 bra 	$L__BB0_85;

	mov.f32 	%f1110, 0f00000000;
	max.f32 	%f1109, %f1110, %f672;
	abs.f32 	%f1108, %f1109;
	setp.gtu.f32 	%p102, %f1108, 0f7F800000;
	@%p102 bra 	$L__BB0_84;
	bra.uni 	$L__BB0_82;

$L__BB0_84:
	mov.f32 	%f1115, 0f00000000;
	max.f32 	%f1114, %f1115, %f672;
	add.f32 	%f1198, %f1114, 0f3ED55555;
	bra.uni 	$L__BB0_85;

$L__BB0_82:
	mov.f32 	%f1113, 0f00000000;
	max.f32 	%f1112, %f1113, %f672;
	abs.f32 	%f1111, %f1112;
	setp.neu.f32 	%p103, %f1111, 0f7F800000;
	@%p103 bra 	$L__BB0_85;

	selp.f32 	%f1198, 0fFF800000, 0f7F800000, %p4;

$L__BB0_85:
	abs.f32 	%f197, %f183;
	setp.lt.f32 	%p104, %f197, 0f00800000;
	mul.f32 	%f761, %f197, 0f4B800000;
	selp.f32 	%f762, %f761, %f197, %p104;
	selp.f32 	%f763, 0fC3170000, 0fC2FE0000, %p104;
	mov.b32 	%r269, %f762;
	and.b32  	%r270, %r269, 8388607;
	or.b32  	%r271, %r270, 1065353216;
	mov.b32 	%f764, %r271;
	shr.u32 	%r272, %r269, 23;
	cvt.rn.f32.u32 	%f765, %r272;
	add.f32 	%f766, %f763, %f765;
	setp.gt.f32 	%p105, %f764, 0f3FB504F3;
	mul.f32 	%f767, %f764, 0f3F000000;
	add.f32 	%f768, %f766, 0f3F800000;
	selp.f32 	%f769, %f768, %f766, %p105;
	selp.f32 	%f770, %f767, %f764, %p105;
	add.f32 	%f771, %f770, 0fBF800000;
	add.f32 	%f772, %f770, 0f3F800000;
	rcp.approx.ftz.f32 	%f773, %f772;
	add.f32 	%f774, %f771, %f771;
	mul.f32 	%f775, %f774, %f773;
	mul.f32 	%f776, %f775, %f775;
	mov.f32 	%f777, 0f3C4CAF63;
	mov.f32 	%f778, 0f3B18F0FE;
	fma.rn.f32 	%f779, %f778, %f776, %f777;
	mov.f32 	%f780, 0f3DAAAABD;
	fma.rn.f32 	%f781, %f779, %f776, %f780;
	mul.rn.f32 	%f782, %f781, %f776;
	mul.rn.f32 	%f783, %f782, %f775;
	sub.f32 	%f784, %f771, %f775;
	add.f32 	%f785, %f784, %f784;
	neg.f32 	%f786, %f775;
	fma.rn.f32 	%f787, %f786, %f771, %f785;
	mul.rn.f32 	%f788, %f773, %f787;
	add.f32 	%f789, %f783, %f775;
	sub.f32 	%f790, %f775, %f789;
	add.f32 	%f791, %f783, %f790;
	add.f32 	%f792, %f788, %f791;
	add.f32 	%f793, %f789, %f792;
	sub.f32 	%f794, %f789, %f793;
	add.f32 	%f795, %f792, %f794;
	mov.f32 	%f796, 0f3F317200;
	mul.rn.f32 	%f797, %f769, %f796;
	mov.f32 	%f798, 0f35BFBE8E;
	mul.rn.f32 	%f799, %f769, %f798;
	add.f32 	%f800, %f797, %f793;
	sub.f32 	%f801, %f797, %f800;
	add.f32 	%f802, %f793, %f801;
	add.f32 	%f803, %f795, %f802;
	add.f32 	%f804, %f799, %f803;
	add.f32 	%f805, %f800, %f804;
	sub.f32 	%f806, %f800, %f805;
	add.f32 	%f807, %f804, %f806;
	mov.f32 	%f808, 0f3ED55555;
	mul.rn.f32 	%f809, %f808, %f805;
	neg.f32 	%f810, %f809;
	fma.rn.f32 	%f811, %f808, %f805, %f810;
	fma.rn.f32 	%f812, %f808, %f807, %f811;
	mov.f32 	%f813, 0f00000000;
	fma.rn.f32 	%f814, %f813, %f805, %f812;
	add.rn.f32 	%f815, %f809, %f814;
	neg.f32 	%f816, %f815;
	add.rn.f32 	%f817, %f809, %f816;
	add.rn.f32 	%f818, %f817, %f814;
	mov.b32 	%r273, %f815;
	setp.eq.s32 	%p106, %r273, 1118925336;
	add.s32 	%r274, %r273, -1;
	mov.b32 	%f819, %r274;
	add.f32 	%f820, %f818, 0f37000000;
	selp.f32 	%f198, %f820, %f818, %p106;
	selp.f32 	%f821, %f819, %f815, %p106;
	mov.f32 	%f822, 0f3FB8AA3B;
	mul.rn.f32 	%f823, %f821, %f822;
	cvt.rzi.f32.f32 	%f824, %f823;
	abs.f32 	%f825, %f824;
	setp.gt.f32 	%p107, %f825, 0f42FC0000;
	mov.b32 	%r275, %f824;
	and.b32  	%r276, %r275, -2147483648;
	or.b32  	%r277, %r276, 1123811328;
	mov.b32 	%f826, %r277;
	selp.f32 	%f827, %f826, %f824, %p107;
	mov.f32 	%f828, 0fBF317218;
	fma.rn.f32 	%f829, %f827, %f828, %f821;
	mov.f32 	%f830, 0f3102E308;
	fma.rn.f32 	%f831, %f827, %f830, %f829;
	mul.f32 	%f832, %f831, 0f3FB8AA3B;
	add.f32 	%f833, %f827, 0f4B40007F;
	mov.b32 	%r278, %f833;
	shl.b32 	%r279, %r278, 23;
	mov.b32 	%f834, %r279;
	ex2.approx.ftz.f32 	%f835, %f832;
	mul.f32 	%f199, %f835, %f834;
	setp.eq.f32 	%p108, %f199, 0f7F800000;
	mov.f32 	%f1199, 0f7F800000;
	@%p108 bra 	$L__BB0_87;

	fma.rn.f32 	%f1199, %f199, %f198, %f199;

$L__BB0_87:
	setp.lt.f32 	%p109, %f183, 0f00000000;
	and.pred  	%p5, %p109, %p96;
	setp.eq.f32 	%p111, %f183, 0f00000000;
	@%p111 bra 	$L__BB0_91;
	bra.uni 	$L__BB0_88;

$L__BB0_91:
	add.f32 	%f840, %f183, %f183;
	selp.f32 	%f1201, %f840, 0f00000000, %p96;
	bra.uni 	$L__BB0_92;

$L__BB0_88:
	mov.b32 	%r280, %f1199;
	xor.b32  	%r281, %r280, -2147483648;
	mov.b32 	%f836, %r281;
	selp.f32 	%f1201, %f836, %f1199, %p5;
	setp.geu.f32 	%p112, %f183, 0f00000000;
	@%p112 bra 	$L__BB0_92;

	mov.f32 	%f837, 0f3ED55555;
	cvt.rzi.f32.f32 	%f838, %f837;
	setp.eq.f32 	%p113, %f838, 0f3ED55555;
	@%p113 bra 	$L__BB0_92;

	mov.f32 	%f1201, 0f7FFFFFFF;

$L__BB0_92:
	mov.f32 	%f1083, 0f00000000;
	max.f32 	%f1082, %f1083, %f674;
	abs.f32 	%f1081, %f1082;
	add.f32 	%f841, %f1081, 0f3ED55555;
	mov.b32 	%r282, %f841;
	setp.lt.s32 	%p115, %r282, 2139095040;
	@%p115 bra 	$L__BB0_97;

	mov.f32 	%f1086, 0f00000000;
	max.f32 	%f1085, %f1086, %f674;
	abs.f32 	%f1084, %f1085;
	setp.gtu.f32 	%p116, %f1084, 0f7F800000;
	@%p116 bra 	$L__BB0_96;
	bra.uni 	$L__BB0_94;

$L__BB0_96:
	add.f32 	%f1201, %f183, 0f3ED55555;
	bra.uni 	$L__BB0_97;

$L__BB0_94:
	mov.f32 	%f1089, 0f00000000;
	max.f32 	%f1088, %f1089, %f674;
	abs.f32 	%f1087, %f1088;
	setp.neu.f32 	%p117, %f1087, 0f7F800000;
	@%p117 bra 	$L__BB0_97;

	selp.f32 	%f1201, 0fFF800000, 0f7F800000, %p5;

$L__BB0_97:
	abs.f32 	%f208, %f184;
	setp.lt.f32 	%p118, %f208, 0f00800000;
	mul.f32 	%f843, %f208, 0f4B800000;
	selp.f32 	%f844, %f843, %f208, %p118;
	selp.f32 	%f845, 0fC3170000, 0fC2FE0000, %p118;
	mov.b32 	%r283, %f844;
	and.b32  	%r284, %r283, 8388607;
	or.b32  	%r285, %r284, 1065353216;
	mov.b32 	%f846, %r285;
	shr.u32 	%r286, %r283, 23;
	cvt.rn.f32.u32 	%f847, %r286;
	add.f32 	%f848, %f845, %f847;
	setp.gt.f32 	%p119, %f846, 0f3FB504F3;
	mul.f32 	%f849, %f846, 0f3F000000;
	add.f32 	%f850, %f848, 0f3F800000;
	selp.f32 	%f851, %f850, %f848, %p119;
	selp.f32 	%f852, %f849, %f846, %p119;
	add.f32 	%f853, %f852, 0fBF800000;
	add.f32 	%f854, %f852, 0f3F800000;
	rcp.approx.ftz.f32 	%f855, %f854;
	add.f32 	%f856, %f853, %f853;
	mul.f32 	%f857, %f856, %f855;
	mul.f32 	%f858, %f857, %f857;
	mov.f32 	%f859, 0f3C4CAF63;
	mov.f32 	%f860, 0f3B18F0FE;
	fma.rn.f32 	%f861, %f860, %f858, %f859;
	mov.f32 	%f862, 0f3DAAAABD;
	fma.rn.f32 	%f863, %f861, %f858, %f862;
	mul.rn.f32 	%f864, %f863, %f858;
	mul.rn.f32 	%f865, %f864, %f857;
	sub.f32 	%f866, %f853, %f857;
	add.f32 	%f867, %f866, %f866;
	neg.f32 	%f868, %f857;
	fma.rn.f32 	%f869, %f868, %f853, %f867;
	mul.rn.f32 	%f870, %f855, %f869;
	add.f32 	%f871, %f865, %f857;
	sub.f32 	%f872, %f857, %f871;
	add.f32 	%f873, %f865, %f872;
	add.f32 	%f874, %f870, %f873;
	add.f32 	%f875, %f871, %f874;
	sub.f32 	%f876, %f871, %f875;
	add.f32 	%f877, %f874, %f876;
	mov.f32 	%f878, 0f3F317200;
	mul.rn.f32 	%f879, %f851, %f878;
	mov.f32 	%f880, 0f35BFBE8E;
	mul.rn.f32 	%f881, %f851, %f880;
	add.f32 	%f882, %f879, %f875;
	sub.f32 	%f883, %f879, %f882;
	add.f32 	%f884, %f875, %f883;
	add.f32 	%f885, %f877, %f884;
	add.f32 	%f886, %f881, %f885;
	add.f32 	%f887, %f882, %f886;
	sub.f32 	%f888, %f882, %f887;
	add.f32 	%f889, %f886, %f888;
	mov.f32 	%f890, 0f3ED55555;
	mul.rn.f32 	%f891, %f890, %f887;
	neg.f32 	%f892, %f891;
	fma.rn.f32 	%f893, %f890, %f887, %f892;
	fma.rn.f32 	%f894, %f890, %f889, %f893;
	mov.f32 	%f895, 0f00000000;
	fma.rn.f32 	%f896, %f895, %f887, %f894;
	add.rn.f32 	%f897, %f891, %f896;
	neg.f32 	%f898, %f897;
	add.rn.f32 	%f899, %f891, %f898;
	add.rn.f32 	%f900, %f899, %f896;
	mov.b32 	%r287, %f897;
	setp.eq.s32 	%p120, %r287, 1118925336;
	add.s32 	%r288, %r287, -1;
	mov.b32 	%f901, %r288;
	add.f32 	%f902, %f900, 0f37000000;
	selp.f32 	%f209, %f902, %f900, %p120;
	selp.f32 	%f903, %f901, %f897, %p120;
	mov.f32 	%f904, 0f3FB8AA3B;
	mul.rn.f32 	%f905, %f903, %f904;
	cvt.rzi.f32.f32 	%f906, %f905;
	abs.f32 	%f907, %f906;
	setp.gt.f32 	%p121, %f907, 0f42FC0000;
	mov.b32 	%r289, %f906;
	and.b32  	%r290, %r289, -2147483648;
	or.b32  	%r291, %r290, 1123811328;
	mov.b32 	%f908, %r291;
	selp.f32 	%f909, %f908, %f906, %p121;
	mov.f32 	%f910, 0fBF317218;
	fma.rn.f32 	%f911, %f909, %f910, %f903;
	mov.f32 	%f912, 0f3102E308;
	fma.rn.f32 	%f913, %f909, %f912, %f911;
	mul.f32 	%f914, %f913, 0f3FB8AA3B;
	add.f32 	%f915, %f909, 0f4B40007F;
	mov.b32 	%r292, %f915;
	shl.b32 	%r293, %r292, 23;
	mov.b32 	%f916, %r293;
	ex2.approx.ftz.f32 	%f917, %f914;
	mul.f32 	%f210, %f917, %f916;
	setp.eq.f32 	%p122, %f210, 0f7F800000;
	mov.f32 	%f1202, 0f7F800000;
	@%p122 bra 	$L__BB0_99;

	fma.rn.f32 	%f1202, %f210, %f209, %f210;

$L__BB0_99:
	setp.lt.f32 	%p123, %f184, 0f00000000;
	and.pred  	%p6, %p123, %p96;
	setp.eq.f32 	%p125, %f184, 0f00000000;
	@%p125 bra 	$L__BB0_103;
	bra.uni 	$L__BB0_100;

$L__BB0_103:
	add.f32 	%f922, %f184, %f184;
	selp.f32 	%f1204, %f922, 0f00000000, %p96;
	bra.uni 	$L__BB0_104;

$L__BB0_100:
	mov.b32 	%r294, %f1202;
	xor.b32  	%r295, %r294, -2147483648;
	mov.b32 	%f918, %r295;
	selp.f32 	%f1204, %f918, %f1202, %p6;
	setp.geu.f32 	%p126, %f184, 0f00000000;
	@%p126 bra 	$L__BB0_104;

	mov.f32 	%f919, 0f3ED55555;
	cvt.rzi.f32.f32 	%f920, %f919;
	setp.eq.f32 	%p127, %f920, 0f3ED55555;
	@%p127 bra 	$L__BB0_104;

	mov.f32 	%f1204, 0f7FFFFFFF;

$L__BB0_104:
	mov.f32 	%f1092, 0f00000000;
	max.f32 	%f1091, %f1092, %f675;
	abs.f32 	%f1090, %f1091;
	add.f32 	%f923, %f1090, 0f3ED55555;
	mov.b32 	%r296, %f923;
	setp.lt.s32 	%p129, %r296, 2139095040;
	@%p129 bra 	$L__BB0_109;

	mov.f32 	%f1095, 0f00000000;
	max.f32 	%f1094, %f1095, %f675;
	abs.f32 	%f1093, %f1094;
	setp.gtu.f32 	%p130, %f1093, 0f7F800000;
	@%p130 bra 	$L__BB0_108;
	bra.uni 	$L__BB0_106;

$L__BB0_108:
	add.f32 	%f1204, %f184, 0f3ED55555;
	bra.uni 	$L__BB0_109;

$L__BB0_106:
	mov.f32 	%f1098, 0f00000000;
	max.f32 	%f1097, %f1098, %f675;
	abs.f32 	%f1096, %f1097;
	setp.neu.f32 	%p131, %f1096, 0f7F800000;
	@%p131 bra 	$L__BB0_109;

	selp.f32 	%f1204, 0fFF800000, 0f7F800000, %p6;

$L__BB0_109:
	mov.f32 	%f1107, 0f00000000;
	max.f32 	%f1106, %f1107, %f672;
	ld.const.u64 	%rd104, [params+144];
	cvta.to.global.u64 	%rd103, %rd104;
	ld.const.u32 	%r347, [params+136];
	mad.lo.s32 	%r346, %r347, %r6, %r5;
	cvt.u64.u32 	%rd102, %r346;
	fma.rn.f32 	%f924, %f1198, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p132, %f1106, 0f3F800000;
	mov.f32 	%f925, 0f3F800000;
	selp.f32 	%f926, 0f3F7FFFFF, %f924, %p132;
	mul.f32 	%f927, %f1106, 0f414EB852;
	setp.lt.f32 	%p133, %f1106, 0f3B4D2E1C;
	selp.f32 	%f928, %f927, %f926, %p133;
	fma.rn.f32 	%f929, %f1201, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p134, %f183, 0f3F800000;
	selp.f32 	%f930, 0f3F7FFFFF, %f929, %p134;
	mul.f32 	%f931, %f183, 0f414EB852;
	setp.lt.f32 	%p135, %f183, 0f3B4D2E1C;
	selp.f32 	%f932, %f931, %f930, %p135;
	fma.rn.f32 	%f933, %f1204, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p136, %f184, 0f3F800000;
	selp.f32 	%f934, 0f3F7FFFFF, %f933, %p136;
	mul.f32 	%f935, %f184, 0f414EB852;
	setp.lt.f32 	%p137, %f184, 0f3B4D2E1C;
	selp.f32 	%f936, %f935, %f934, %p137;
	min.f32 	%f937, %f928, %f925;
	mov.f32 	%f938, 0f00000000;
	max.f32 	%f939, %f938, %f937;
	mul.f32 	%f940, %f939, 0f43800000;
	cvt.rzi.u32.f32 	%r297, %f940;
	min.u32 	%r298, %r297, 255;
	min.f32 	%f941, %f932, %f925;
	max.f32 	%f942, %f938, %f941;
	mul.f32 	%f943, %f942, 0f43800000;
	cvt.rzi.u32.f32 	%r299, %f943;
	min.u32 	%r300, %r299, 255;
	min.f32 	%f944, %f936, %f925;
	max.f32 	%f945, %f938, %f944;
	mul.f32 	%f946, %f945, 0f43800000;
	cvt.rzi.u32.f32 	%r301, %f946;
	min.u32 	%r302, %r301, 255;
	shl.b64 	%rd66, %rd102, 2;
	add.s64 	%rd67, %rd103, %rd66;
	cvt.u16.u32 	%rs15, %r302;
	cvt.u16.u32 	%rs16, %r300;
	cvt.u16.u32 	%rs17, %r298;
	mov.u16 	%rs18, 255;
	st.global.v4.u8 	[%rd67], {%rs17, %rs16, %rs15, %rs18};

$L__BB0_110:
	ld.const.u32 	%r348, [params+104];
	and.b32  	%r303, %r348, 4;
	setp.eq.s32 	%p138, %r303, 0;
	ld.const.u32 	%r360, [params+108];
	@%p138 bra 	$L__BB0_114;

	setp.eq.s32 	%p139, %r360, 0;
	ld.const.u64 	%rd68, [params+224];
	cvta.to.global.u64 	%rd69, %rd68;
	ld.const.u32 	%r304, [params+216];
	mad.lo.s32 	%r305, %r304, %r6, %r5;
	mul.wide.u32 	%rd70, %r305, 8;
	add.s64 	%rd19, %rd69, %rd70;
	@%p139 bra 	$L__BB0_113;

	ld.global.v4.u16 	{%rs26, %rs27, %rs28, %rs29}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f947, %rs26;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f948, %rs27;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f949, %rs28;}

	// end inline asm
	add.f32 	%f950, %f143, %f947;
	add.f32 	%f951, %f144, %f948;
	add.f32 	%f952, %f145, %f949;
	mov.f32 	%f953, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs24, %f952;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs23, %f951;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs22, %f950;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f953;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs22, %rs23, %rs24, %rs25};
	bra.uni 	$L__BB0_114;

$L__BB0_113:
	mov.f32 	%f957, 0f3F800000;
	mov.u32 	%r360, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f957;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f145;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs31, %f144;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f143;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs30, %rs31, %rs32, %rs33};

$L__BB0_114:
	mul.f32 	%f958, %f128, %f415;
	mul.f32 	%f219, %f958, 0f3F000000;
	mul.f32 	%f959, %f129, %f416;
	mul.f32 	%f220, %f959, 0f3F000000;
	mul.f32 	%f960, %f130, %f417;
	mul.f32 	%f221, %f960, 0f3F000000;
	mul.f32 	%f222, %f131, %f415;
	mul.f32 	%f223, %f132, %f416;
	mul.f32 	%f224, %f133, %f417;
	mul.f32 	%f225, %f134, %f415;
	mul.f32 	%f226, %f135, %f416;
	mul.f32 	%f227, %f136, %f417;
	mul.f32 	%f228, %f137, %f415;
	mul.f32 	%f229, %f138, %f416;
	mul.f32 	%f230, %f139, %f417;
	ld.const.u64 	%rd71, [params+256];
	cvta.to.global.u64 	%rd72, %rd71;
	ld.const.u32 	%r307, [params+248];
	mad.lo.s32 	%r308, %r307, %r6, %r5;
	mul.wide.u32 	%rd73, %r308, 8;
	add.s64 	%rd20, %rd72, %rd73;
	setp.eq.s32 	%p140, %r360, 0;
	@%p140 bra 	$L__BB0_116;

	ld.global.v4.u16 	{%rs41, %rs42, %rs43, %rs44}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f961, %rs41;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f962, %rs42;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f963, %rs43;}

	// end inline asm
	add.f32 	%f964, %f219, %f961;
	add.f32 	%f965, %f220, %f962;
	add.f32 	%f966, %f221, %f963;
	mov.f32 	%f967, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs39, %f966;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f965;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f964;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f967;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs37, %rs38, %rs39, %rs40};
	bra.uni 	$L__BB0_117;

$L__BB0_116:
	mov.f32 	%f971, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f971;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs47, %f221;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f220;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f219;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs45, %rs46, %rs47, %rs48};

$L__BB0_117:
	mov.f32 	%f972, 0f34000000;
	max.f32 	%f973, %f219, %f972;
	mul.f32 	%f974, %f222, 0f3F000000;
	div.rn.f32 	%f975, %f974, %f973;
	max.f32 	%f976, %f220, %f972;
	mul.f32 	%f977, %f223, 0f3F000000;
	div.rn.f32 	%f978, %f977, %f976;
	max.f32 	%f979, %f221, %f972;
	mul.f32 	%f980, %f224, 0f3F000000;
	div.rn.f32 	%f981, %f980, %f979;
	fma.rn.f32 	%f231, %f975, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f232, %f978, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f233, %f981, 0f3F000000, 0f3F000000;
	mul.f32 	%f982, %f225, 0f3F000000;
	div.rn.f32 	%f983, %f982, %f973;
	mul.f32 	%f984, %f226, 0f3F000000;
	div.rn.f32 	%f985, %f984, %f976;
	mul.f32 	%f986, %f227, 0f3F000000;
	div.rn.f32 	%f987, %f986, %f979;
	fma.rn.f32 	%f234, %f983, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f235, %f985, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f236, %f987, 0f3F000000, 0f3F000000;
	mul.f32 	%f988, %f228, 0f3F000000;
	div.rn.f32 	%f989, %f988, %f973;
	mul.f32 	%f990, %f229, 0f3F000000;
	div.rn.f32 	%f991, %f990, %f976;
	mul.f32 	%f992, %f230, 0f3F000000;
	div.rn.f32 	%f993, %f992, %f979;
	fma.rn.f32 	%f237, %f989, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f238, %f991, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f239, %f993, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd74, [params+272];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r309, [params+264];
	mad.lo.s32 	%r310, %r309, %r6, %r5;
	mul.wide.u32 	%rd76, %r310, 8;
	add.s64 	%rd21, %rd75, %rd76;
	@%p140 bra 	$L__BB0_119;

	ld.global.v4.u16 	{%rs56, %rs57, %rs58, %rs59}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f994, %rs56;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f995, %rs57;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs58;}

	// end inline asm
	add.f32 	%f997, %f231, %f994;
	add.f32 	%f998, %f232, %f995;
	add.f32 	%f999, %f233, %f996;
	mov.f32 	%f1000, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f997;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1000;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs52, %rs53, %rs54, %rs55};
	bra.uni 	$L__BB0_120;

$L__BB0_119:
	mov.f32 	%f1004, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f1004;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f232;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f231;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs60, %rs61, %rs62, %rs63};

$L__BB0_120:
	ld.const.u64 	%rd77, [params+288];
	cvta.to.global.u64 	%rd78, %rd77;
	ld.const.u32 	%r311, [params+280];
	mad.lo.s32 	%r312, %r311, %r6, %r5;
	mul.wide.u32 	%rd79, %r312, 8;
	add.s64 	%rd22, %rd78, %rd79;
	@%p140 bra 	$L__BB0_122;

	ld.global.v4.u16 	{%rs71, %rs72, %rs73, %rs74}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1005, %rs71;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1006, %rs72;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1007, %rs73;}

	// end inline asm
	add.f32 	%f1008, %f234, %f1005;
	add.f32 	%f1009, %f235, %f1006;
	add.f32 	%f1010, %f236, %f1007;
	mov.f32 	%f1011, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1010;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1009;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f1008;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1011;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs67, %rs68, %rs69, %rs70};
	bra.uni 	$L__BB0_123;

$L__BB0_122:
	mov.f32 	%f1015, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f1015;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f236;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f235;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f234;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs75, %rs76, %rs77, %rs78};

$L__BB0_123:
	ld.const.u64 	%rd80, [params+304];
	cvta.to.global.u64 	%rd81, %rd80;
	ld.const.u32 	%r313, [params+296];
	mad.lo.s32 	%r314, %r313, %r6, %r5;
	mul.wide.u32 	%rd82, %r314, 8;
	add.s64 	%rd23, %rd81, %rd82;
	@%p140 bra 	$L__BB0_125;

	ld.global.v4.u16 	{%rs86, %rs87, %rs88, %rs89}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1016, %rs86;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1017, %rs87;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1018, %rs88;}

	// end inline asm
	add.f32 	%f1019, %f237, %f1016;
	add.f32 	%f1020, %f238, %f1017;
	add.f32 	%f1021, %f239, %f1018;
	mov.f32 	%f1022, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1021;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1020;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1022;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs82, %rs83, %rs84, %rs85};
	bra.uni 	$L__BB0_144;

$L__BB0_125:
	mov.f32 	%f1026, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f239;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f238;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f237;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs90, %rs91, %rs92, %rs93};

$L__BB0_144:
	ret;

}