//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<171>;
	.reg .b16 	%rs<178>;
	.reg .f32 	%f<1165>;
	.reg .b32 	%r<369>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<122>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r54), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r55), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd31, [params+400];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r60, [params+392];
	mad.lo.s32 	%r61, %r60, %r55, %r54;
	mul.wide.u32 	%rd33, %r61, 4;
	add.s64 	%rd2, %rd32, %rd33;
	ld.global.v2.u8 	{%rs7, %rs177}, [%rd2];
	or.b16  	%rs9, %rs7, %rs177;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p8, %rs10, 0;
	@%p8 bra 	$L__BB0_2;

	ld.global.u8 	%rs176, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs176, [%rd2+2];
	setp.eq.s16 	%p9, %rs176, 0;
	mov.f32 	%f1131, 0f00000000;
	mov.u16 	%rs177, 0;
	mov.f32 	%f1132, %f1131;
	mov.f32 	%f1133, %f1131;
	@%p9 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f162, %rs7;
	div.rn.f32 	%f163, %f162, 0f437F0000;
	fma.rn.f32 	%f164, %f163, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs177, 255;
	cvt.rn.f32.u16 	%f165, %rs13;
	div.rn.f32 	%f166, %f165, 0f437F0000;
	fma.rn.f32 	%f167, %f166, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f168, %rs176;
	div.rn.f32 	%f169, %f168, 0f437F0000;
	fma.rn.f32 	%f170, %f169, 0f40000000, 0fBF800000;
	mul.f32 	%f171, %f167, %f167;
	fma.rn.f32 	%f172, %f164, %f164, %f171;
	fma.rn.f32 	%f173, %f170, %f170, %f172;
	sqrt.rn.f32 	%f174, %f173;
	rcp.rn.f32 	%f175, %f174;
	mul.f32 	%f1133, %f175, %f170;
	mul.f32 	%f1132, %f175, %f167;
	mul.f32 	%f1131, %f164, %f175;

$L__BB0_4:
	ld.const.v2.u32 	{%r62, %r63}, [params];
	add.s32 	%r3, %r62, %r54;
	add.s32 	%r4, %r63, %r55;
	setp.eq.f32 	%p10, %f1131, 0f00000000;
	setp.eq.f32 	%p11, %f1132, 0f00000000;
	and.pred  	%p12, %p10, %p11;
	setp.eq.f32 	%p13, %f1133, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	@%p14 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_5;

$L__BB0_140:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r331, %r51, 1;
	setp.eq.b32 	%p160, %r331, 1;
	mov.pred 	%p161, 0;
	xor.pred  	%p162, %p160, %p161;
	not.pred 	%p163, %p162;
	@%p163 bra 	$L__BB0_142;

	ld.const.u64 	%rd88, [params+144];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r332, [params+136];
	mad.lo.s32 	%r333, %r332, %r4, %r3;
	mul.wide.u32 	%rd90, %r333, 4;
	add.s64 	%rd91, %rd89, %rd90;
	mov.u16 	%rs98, 0;
	st.global.v4.u8 	[%rd91], {%rs98, %rs98, %rs98, %rs98};

$L__BB0_142:
	and.b32  	%r334, %r51, 8;
	setp.eq.s32 	%p164, %r334, 0;
	@%p164 bra 	$L__BB0_144;

	ld.const.u64 	%rd92, [params+192];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r335, [params+184];
	mad.lo.s32 	%r336, %r335, %r4, %r3;
	mov.f32 	%f1027, 0f00000000;
	cvt.rzi.u32.f32 	%r337, %f1027;
	mul.wide.u32 	%rd94, %r336, 2;
	add.s64 	%rd95, %rd93, %rd94;
	mov.u16 	%rs99, 0;
	cvt.u16.u32 	%rs100, %r337;
	st.global.v2.u8 	[%rd95], {%rs100, %rs99};

$L__BB0_144:
	and.b32  	%r338, %r51, 4;
	setp.eq.s32 	%p165, %r338, 0;
	ld.const.u32 	%r368, [params+108];
	@%p165 bra 	$L__BB0_148;

	setp.eq.s32 	%p166, %r368, 0;
	ld.const.u64 	%rd96, [params+224];
	cvta.to.global.u64 	%rd97, %rd96;
	ld.const.u32 	%r339, [params+216];
	mad.lo.s32 	%r340, %r339, %r4, %r3;
	mul.wide.u32 	%rd98, %r340, 8;
	add.s64 	%rd25, %rd97, %rd98;
	@%p166 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs107, %rs108, %rs109, %rs110}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1028, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1029, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1030, %rs109;}

	// end inline asm
	add.f32 	%f1031, %f1028, 0f00000000;
	add.f32 	%f1032, %f1029, 0f00000000;
	add.f32 	%f1033, %f1030, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1033;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1032;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1031;}

	// end inline asm
	mov.u16 	%rs111, 0;
	st.global.v4.u16 	[%rd25], {%rs104, %rs105, %rs106, %rs111};
	bra.uni 	$L__BB0_148;

$L__BB0_5:
	ld.const.v4.f32 	{%f177, %f178, %f179, %f180}, [params+512];
	neg.f32 	%f181, %f178;
	neg.f32 	%f182, %f179;
	mul.f32 	%f183, %f1131, %f177;
	mul.f32 	%f184, %f1132, %f181;
	sub.f32 	%f185, %f184, %f183;
	mul.f32 	%f186, %f1133, %f179;
	sub.f32 	%f13, %f185, %f186;
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r66, [params+424];
	mad.lo.s32 	%r67, %r66, %r55, %r54;
	mul.wide.u32 	%rd36, %r67, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f14, [%rd37];
	mul.f32 	%f187, %f14, 0f3456BF95;
	ld.global.f32 	%f15, [%rd37+4];
	mul.f32 	%f188, %f15, 0f3456BF95;
	ld.global.f32 	%f16, [%rd37+8];
	mul.f32 	%f189, %f16, 0f3456BF95;
	abs.f32 	%f190, %f1131;
	div.rn.f32 	%f191, %f187, %f190;
	abs.f32 	%f192, %f1132;
	div.rn.f32 	%f193, %f188, %f192;
	abs.f32 	%f194, %f1133;
	div.rn.f32 	%f195, %f189, %f194;
	abs.f32 	%f196, %f191;
	abs.f32 	%f197, %f193;
	abs.f32 	%f198, %f195;
	mov.f32 	%f199, 0f38D1B717;
	max.f32 	%f200, %f196, %f199;
	max.f32 	%f201, %f197, %f199;
	max.f32 	%f202, %f198, %f199;
	fma.rn.f32 	%f17, %f1131, %f200, %f14;
	fma.rn.f32 	%f18, %f1132, %f201, %f15;
	fma.rn.f32 	%f19, %f1133, %f202, %f16;
	abs.f32 	%f203, %f177;
	abs.f32 	%f204, %f179;
	setp.gt.f32 	%p15, %f203, %f204;
	selp.f32 	%f205, %f181, 0f00000000, %p15;
	mov.f32 	%f1135, 0f00000000;
	selp.f32 	%f206, %f177, %f182, %p15;
	selp.f32 	%f207, 0f00000000, %f178, %p15;
	mul.f32 	%f208, %f206, %f206;
	fma.rn.f32 	%f209, %f205, %f205, %f208;
	fma.rn.f32 	%f210, %f207, %f207, %f209;
	sqrt.rn.f32 	%f211, %f210;
	rcp.rn.f32 	%f212, %f211;
	mul.f32 	%f20, %f205, %f212;
	mul.f32 	%f21, %f206, %f212;
	mul.f32 	%f22, %f207, %f212;
	mul.f32 	%f213, %f179, %f21;
	mul.f32 	%f214, %f178, %f22;
	sub.f32 	%f23, %f213, %f214;
	mul.f32 	%f215, %f177, %f22;
	mul.f32 	%f216, %f179, %f20;
	sub.f32 	%f24, %f215, %f216;
	mul.f32 	%f217, %f178, %f20;
	mul.f32 	%f218, %f177, %f21;
	sub.f32 	%f25, %f217, %f218;
	ld.const.u64 	%rd38, [params+128];
	cvta.to.global.u64 	%rd39, %rd38;
	ld.const.u32 	%r68, [params+120];
	mad.lo.s32 	%r69, %r68, %r55, %r54;
	mul.wide.u32 	%rd40, %r69, 4;
	add.s64 	%rd3, %rd39, %rd40;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p16, %r5, 1;
	@%p16 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f220, %r5;
	rcp.rn.f32 	%f26, %f220;
	ld.global.u32 	%r359, [%rd3];
	ld.const.f32 	%f27, [params+536];
	ld.const.u8 	%rs15, [params+104];
	and.b16  	%rs16, %rs15, 32;
	setp.eq.s16 	%p17, %rs16, 0;
	mov.u32 	%r70, 0;
	selp.f32 	%f28, 0f3F800000, 0f41200000, %p17;
	mul.f32 	%f29, %f17, 0f3456BF95;
	mul.f32 	%f30, %f18, 0f3456BF95;
	mul.f32 	%f31, %f19, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd41, __cudart_i2opi_f;
	abs.f32 	%f303, %f30;
	abs.f32 	%f304, %f29;
	max.f32 	%f305, %f304, %f303;
	abs.f32 	%f306, %f31;
	max.f32 	%f307, %f305, %f306;
	mov.u32 	%r356, %r70;

$L__BB0_7:
	cvt.rn.f32.s32 	%f33, %r356;
	mov.u32 	%r358, %r70;

$L__BB0_8:
	mad.lo.s32 	%r72, %r359, 1664525, 1013904223;
	and.b32  	%r73, %r72, 16777215;
	cvt.rn.f32.u32 	%f221, %r73;
	fma.rn.f32 	%f222, %f221, 0f33800000, %f33;
	mul.f32 	%f223, %f26, %f222;
	mad.lo.s32 	%r359, %r72, 1664525, 1013904223;
	and.b32  	%r74, %r359, 16777215;
	cvt.rn.f32.u32 	%f224, %r74;
	cvt.rn.f32.s32 	%f225, %r358;
	fma.rn.f32 	%f226, %f224, 0f33800000, %f225;
	mul.f32 	%f227, %f26, %f226;
	sqrt.rn.f32 	%f35, %f223;
	mul.f32 	%f36, %f227, 0f40C90FDB;
	mul.f32 	%f228, %f36, 0f3F22F983;
	cvt.rni.s32.f32 	%r366, %f228;
	cvt.rn.f32.s32 	%f229, %r366;
	mov.f32 	%f230, 0fBFC90FDA;
	fma.rn.f32 	%f231, %f229, %f230, %f36;
	mov.f32 	%f232, 0fB3A22168;
	fma.rn.f32 	%f233, %f229, %f232, %f231;
	mov.f32 	%f234, 0fA7C234C5;
	fma.rn.f32 	%f1139, %f229, %f234, %f233;
	abs.f32 	%f38, %f36;
	setp.ltu.f32 	%p18, %f38, 0f47CE4780;
	mov.u32 	%r363, %r366;
	mov.f32 	%f1136, %f1139;
	@%p18 bra 	$L__BB0_16;

	setp.eq.f32 	%p19, %f38, 0f7F800000;
	@%p19 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f237, 0f00000000;
	mul.rn.f32 	%f1136, %f36, %f237;
	mov.u32 	%r363, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f36;
	bfe.u32 	%r76, %r13, 23, 8;
	add.s32 	%r14, %r76, -128;
	shl.b32 	%r77, %r13, 8;
	or.b32  	%r15, %r77, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd119, 0;
	mov.u32 	%r360, 0;
	mov.u64 	%rd117, %rd1;
	mov.u64 	%rd118, %rd41;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r78, [%rd118];
	mad.wide.u32 	%rd43, %r78, %r15, %rd119;
	shr.u64 	%rd119, %rd43, 32;
	st.local.u32 	[%rd117], %rd43;
	add.s64 	%rd118, %rd118, 4;
	add.s64 	%rd117, %rd117, 4;
	add.s32 	%r360, %r360, 1;
	setp.ne.s32 	%p20, %r360, 6;
	@%p20 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd119;
	mov.u32 	%r79, 4;
	sub.s32 	%r19, %r79, %r16;
	mov.u32 	%r80, 6;
	sub.s32 	%r81, %r80, %r16;
	mul.wide.s32 	%rd44, %r81, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r361, [%rd45];
	ld.local.u32 	%r362, [%rd45+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p21, %r22, 0;
	@%p21 bra 	$L__BB0_14;

	mov.u32 	%r82, 32;
	sub.s32 	%r83, %r82, %r22;
	shr.u32 	%r84, %r362, %r83;
	shl.b32 	%r85, %r361, %r22;
	add.s32 	%r361, %r84, %r85;
	mul.wide.s32 	%rd46, %r19, 4;
	add.s64 	%rd47, %rd1, %rd46;
	ld.local.u32 	%r86, [%rd47];
	shr.u32 	%r87, %r86, %r83;
	shl.b32 	%r88, %r362, %r22;
	add.s32 	%r362, %r87, %r88;

$L__BB0_14:
	and.b32  	%r89, %r13, -2147483648;
	shr.u32 	%r90, %r362, 30;
	shl.b32 	%r91, %r361, 2;
	or.b32  	%r92, %r90, %r91;
	shr.u32 	%r93, %r92, 31;
	shr.u32 	%r94, %r361, 30;
	add.s32 	%r95, %r93, %r94;
	neg.s32 	%r96, %r95;
	setp.eq.s32 	%p22, %r89, 0;
	selp.b32 	%r363, %r95, %r96, %p22;
	setp.ne.s32 	%p23, %r93, 0;
	xor.b32  	%r97, %r89, -2147483648;
	selp.b32 	%r98, %r97, %r89, %p23;
	selp.b32 	%r99, -1, 0, %p23;
	xor.b32  	%r100, %r92, %r99;
	shl.b32 	%r101, %r362, 2;
	xor.b32  	%r102, %r101, %r99;
	cvt.u64.u32 	%rd48, %r100;
	cvt.u64.u32 	%rd49, %r102;
	bfi.b64 	%rd50, %rd48, %rd49, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd50;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f235, %fd2;
	setp.eq.s32 	%p24, %r98, 0;
	neg.f32 	%f236, %f235;
	selp.f32 	%f1136, %f235, %f236, %p24;

$L__BB0_16:
	add.s32 	%r29, %r363, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p25, %r30, 0;
	selp.f32 	%f42, %f1136, 0f3F800000, %p25;
	mul.rn.f32 	%f43, %f1136, %f1136;
	mov.f32 	%f1137, 0fB94D4153;
	@%p25 bra 	$L__BB0_18;

	mov.f32 	%f239, 0fBAB607ED;
	mov.f32 	%f240, 0f37CBAC00;
	fma.rn.f32 	%f1137, %f240, %f43, %f239;

$L__BB0_18:
	selp.f32 	%f241, 0f3C0885E4, 0f3D2AAABB, %p25;
	fma.rn.f32 	%f242, %f1137, %f43, %f241;
	selp.f32 	%f243, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
	fma.rn.f32 	%f244, %f242, %f43, %f243;
	mov.f32 	%f245, 0f00000000;
	fma.rn.f32 	%f246, %f43, %f42, %f245;
	fma.rn.f32 	%f1138, %f244, %f246, %f42;
	and.b32  	%r104, %r29, 2;
	setp.eq.s32 	%p27, %r104, 0;
	@%p27 bra 	$L__BB0_20;

	mov.f32 	%f248, 0fBF800000;
	fma.rn.f32 	%f1138, %f1138, %f248, %f245;

$L__BB0_20:
	@%p18 bra 	$L__BB0_28;

	setp.eq.f32 	%p29, %f38, 0f7F800000;
	@%p29 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f251, 0f00000000;
	mul.rn.f32 	%f1139, %f36, %f251;
	mov.u32 	%r366, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f36;
	bfe.u32 	%r105, %r31, 23, 8;
	add.s32 	%r32, %r105, -128;
	shl.b32 	%r106, %r31, 8;
	or.b32  	%r33, %r106, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd120, 0;
	mov.u64 	%rd121, %rd120;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd53, %rd120, 2;
	mov.u64 	%rd54, __cudart_i2opi_f;
	add.s64 	%rd55, %rd54, %rd53;
	ld.global.nc.u32 	%r107, [%rd55];
	mad.wide.u32 	%rd56, %r107, %r33, %rd121;
	shr.u64 	%rd121, %rd56, 32;
	add.s64 	%rd57, %rd1, %rd53;
	st.local.u32 	[%rd57], %rd56;
	cvt.u32.u64 	%r108, %rd120;
	add.s32 	%r109, %r108, 1;
	cvt.s64.s32 	%rd120, %r109;
	setp.ne.s32 	%p30, %r109, 6;
	@%p30 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd121;
	mov.u32 	%r110, 4;
	sub.s32 	%r35, %r110, %r34;
	mov.u32 	%r111, 6;
	sub.s32 	%r112, %r111, %r34;
	mul.wide.s32 	%rd58, %r112, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r364, [%rd59];
	ld.local.u32 	%r365, [%rd59+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p31, %r38, 0;
	@%p31 bra 	$L__BB0_26;

	mov.u32 	%r113, 32;
	sub.s32 	%r114, %r113, %r38;
	shr.u32 	%r115, %r365, %r114;
	shl.b32 	%r116, %r364, %r38;
	add.s32 	%r364, %r115, %r116;
	mul.wide.s32 	%rd60, %r35, 4;
	add.s64 	%rd61, %rd1, %rd60;
	ld.local.u32 	%r117, [%rd61];
	shr.u32 	%r118, %r117, %r114;
	shl.b32 	%r119, %r365, %r38;
	add.s32 	%r365, %r118, %r119;

$L__BB0_26:
	and.b32  	%r120, %r31, -2147483648;
	shr.u32 	%r121, %r365, 30;
	shl.b32 	%r122, %r364, 2;
	or.b32  	%r123, %r121, %r122;
	shr.u32 	%r124, %r123, 31;
	shr.u32 	%r125, %r364, 30;
	add.s32 	%r126, %r124, %r125;
	neg.s32 	%r127, %r126;
	setp.eq.s32 	%p32, %r120, 0;
	selp.b32 	%r366, %r126, %r127, %p32;
	setp.ne.s32 	%p33, %r124, 0;
	xor.b32  	%r128, %r120, -2147483648;
	selp.b32 	%r129, %r128, %r120, %p33;
	selp.b32 	%r130, -1, 0, %p33;
	xor.b32  	%r131, %r123, %r130;
	shl.b32 	%r132, %r365, 2;
	xor.b32  	%r133, %r132, %r130;
	cvt.u64.u32 	%rd62, %r131;
	cvt.u64.u32 	%rd63, %r133;
	bfi.b64 	%rd64, %rd62, %rd63, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd64;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f249, %fd4;
	setp.eq.s32 	%p34, %r129, 0;
	neg.f32 	%f250, %f249;
	selp.f32 	%f1139, %f249, %f250, %p34;

$L__BB0_28:
	mul.f32 	%f52, %f35, %f1138;
	and.b32  	%r45, %r366, 1;
	setp.eq.s32 	%p35, %r45, 0;
	selp.f32 	%f53, %f1139, 0f3F800000, %p35;
	mul.rn.f32 	%f54, %f1139, %f1139;
	mov.f32 	%f1140, 0fB94D4153;
	@%p35 bra 	$L__BB0_30;

	mov.f32 	%f253, 0fBAB607ED;
	mov.f32 	%f254, 0f37CBAC00;
	fma.rn.f32 	%f1140, %f254, %f54, %f253;

$L__BB0_30:
	selp.f32 	%f255, 0f3C0885E4, 0f3D2AAABB, %p35;
	fma.rn.f32 	%f256, %f1140, %f54, %f255;
	selp.f32 	%f257, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
	fma.rn.f32 	%f258, %f256, %f54, %f257;
	mov.f32 	%f259, 0f00000000;
	fma.rn.f32 	%f260, %f54, %f53, %f259;
	fma.rn.f32 	%f1141, %f258, %f260, %f53;
	and.b32  	%r135, %r366, 2;
	setp.eq.s32 	%p37, %r135, 0;
	@%p37 bra 	$L__BB0_32;

	mov.f32 	%f262, 0fBF800000;
	fma.rn.f32 	%f1141, %f1141, %f262, %f259;

$L__BB0_32:
	mul.f32 	%f272, %f52, %f52;
	mov.f32 	%f273, 0f3F800000;
	sub.f32 	%f274, %f273, %f272;
	mul.f32 	%f275, %f35, %f1141;
	mul.f32 	%f276, %f275, %f275;
	sub.f32 	%f277, %f274, %f276;
	max.f32 	%f278, %f259, %f277;
	sqrt.rn.f32 	%f279, %f278;
	mul.f32 	%f280, %f20, %f275;
	mul.f32 	%f281, %f21, %f275;
	mul.f32 	%f282, %f22, %f275;
	fma.rn.f32 	%f283, %f23, %f52, %f280;
	fma.rn.f32 	%f284, %f24, %f52, %f281;
	fma.rn.f32 	%f285, %f25, %f52, %f282;
	fma.rn.f32 	%f286, %f177, %f279, %f283;
	fma.rn.f32 	%f287, %f178, %f279, %f284;
	fma.rn.f32 	%f288, %f179, %f279, %f285;
	add.f32 	%f289, %f177, %f286;
	add.f32 	%f290, %f178, %f287;
	add.f32 	%f291, %f179, %f288;
	mul.f32 	%f292, %f27, %f289;
	mul.f32 	%f293, %f27, %f290;
	mul.f32 	%f294, %f27, %f291;
	sub.f32 	%f295, %f292, %f177;
	sub.f32 	%f296, %f293, %f178;
	sub.f32 	%f297, %f294, %f179;
	mul.f32 	%f298, %f296, %f296;
	fma.rn.f32 	%f299, %f295, %f295, %f298;
	fma.rn.f32 	%f300, %f297, %f297, %f299;
	sqrt.rn.f32 	%f301, %f300;
	rcp.rn.f32 	%f302, %f301;
	mul.f32 	%f266, %f302, %f295;
	mul.f32 	%f267, %f302, %f296;
	mul.f32 	%f268, %f302, %f297;
	mov.f32 	%f308, 0f38D1B717;
	max.f32 	%f309, %f307, %f308;
	mul.f32 	%f269, %f28, %f309;
	mov.f32 	%f270, 0f6C4ECB8F;
	mov.u32 	%r172, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f17,%f18,%f19,%f266,%f267,%f268,%f269,%f270,%f259,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f310, %r136;
	add.f32 	%f1135, %f1135, %f310;
	add.s32 	%r358, %r358, 1;
	setp.lt.s32 	%p38, %r358, %r5;
	@%p38 bra 	$L__BB0_8;

	add.s32 	%r356, %r356, 1;
	setp.lt.s32 	%p39, %r356, %r5;
	@%p39 bra 	$L__BB0_7;

$L__BB0_34:
	setp.eq.s32 	%p40, %r5, 0;
	mov.f32 	%f1143, 0f3F800000;
	@%p40 bra 	$L__BB0_36;

	mul.lo.s32 	%r207, %r5, %r5;
	cvt.rn.f32.s32 	%f312, %r207;
	div.rn.f32 	%f1143, %f1135, %f312;

$L__BB0_36:
	mul.f32 	%f313, %f15, %f24;
	fma.rn.f32 	%f314, %f14, %f23, %f313;
	fma.rn.f32 	%f315, %f16, %f25, %f314;
	ld.const.v4.f32 	{%f316, %f317, %f318, %f319}, [params+560];
	fma.rn.f32 	%f324, %f315, %f316, %f318;
	mul.f32 	%f325, %f15, %f21;
	fma.rn.f32 	%f326, %f14, %f20, %f325;
	fma.rn.f32 	%f327, %f16, %f22, %f326;
	fma.rn.f32 	%f328, %f327, %f317, %f319;
	ld.const.u64 	%rd66, [params+552];
	tex.2d.v4.f32.f32 	{%f329, %f330, %f331, %f332}, [%rd66, {%f324, %f328}];
	min.f32 	%f333, %f329, %f330;
	min.f32 	%f334, %f333, %f331;
	mul.f32 	%f64, %f1143, %f334;
	ld.const.f32 	%f335, [params+524];
	mul.f32 	%f336, %f1143, %f335;
	ld.const.v2.f32 	{%f337, %f338}, [params+528];
	mul.f32 	%f341, %f1143, %f337;
	mul.f32 	%f342, %f1143, %f338;
	mul.f32 	%f343, %f329, %f336;
	mul.f32 	%f344, %f330, %f341;
	mul.f32 	%f345, %f331, %f342;
	cvt.sat.f32.f32 	%f346, %f13;
	mul.f32 	%f65, %f343, %f346;
	mul.f32 	%f66, %f344, %f346;
	mul.f32 	%f67, %f346, %f345;
	mul.f32 	%f347, %f13, 0f40800000;
	cvt.sat.f32.f32 	%f348, %f347;
	mul.f32 	%f349, %f343, %f348;
	mul.f32 	%f350, %f344, %f348;
	mul.f32 	%f351, %f345, %f348;
	mul.f32 	%f68, %f349, 0f3E800000;
	mul.f32 	%f69, %f350, 0f3E800000;
	mul.f32 	%f70, %f351, 0f3E800000;
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r208, %r48, 8;
	setp.eq.s32 	%p41, %r208, 0;
	@%p41 bra 	$L__BB0_50;

	mov.f32 	%f356, 0f3EE8BA2E;
	abs.f32 	%f72, %f64;
	setp.lt.f32 	%p42, %f72, 0f00800000;
	mul.f32 	%f358, %f72, 0f4B800000;
	selp.f32 	%f359, %f358, %f72, %p42;
	selp.f32 	%f360, 0fC3170000, 0fC2FE0000, %p42;
	mov.b32 	%r211, %f359;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f361, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f362, %r214;
	add.f32 	%f363, %f360, %f362;
	setp.gt.f32 	%p43, %f361, 0f3FB504F3;
	mul.f32 	%f364, %f361, 0f3F000000;
	add.f32 	%f365, %f363, 0f3F800000;
	selp.f32 	%f366, %f365, %f363, %p43;
	selp.f32 	%f367, %f364, %f361, %p43;
	add.f32 	%f368, %f367, 0fBF800000;
	add.f32 	%f369, %f367, 0f3F800000;
	rcp.approx.ftz.f32 	%f370, %f369;
	add.f32 	%f371, %f368, %f368;
	mul.f32 	%f372, %f371, %f370;
	mul.f32 	%f373, %f372, %f372;
	mov.f32 	%f374, 0f3C4CAF63;
	mov.f32 	%f375, 0f3B18F0FE;
	fma.rn.f32 	%f376, %f375, %f373, %f374;
	mov.f32 	%f377, 0f3DAAAABD;
	fma.rn.f32 	%f378, %f376, %f373, %f377;
	mul.rn.f32 	%f379, %f378, %f373;
	mul.rn.f32 	%f380, %f379, %f372;
	sub.f32 	%f381, %f368, %f372;
	add.f32 	%f382, %f381, %f381;
	neg.f32 	%f383, %f372;
	fma.rn.f32 	%f384, %f383, %f368, %f382;
	mul.rn.f32 	%f385, %f370, %f384;
	add.f32 	%f386, %f380, %f372;
	sub.f32 	%f387, %f372, %f386;
	add.f32 	%f388, %f380, %f387;
	add.f32 	%f389, %f385, %f388;
	add.f32 	%f390, %f386, %f389;
	sub.f32 	%f391, %f386, %f390;
	add.f32 	%f392, %f389, %f391;
	mov.f32 	%f393, 0f3F317200;
	mul.rn.f32 	%f394, %f366, %f393;
	mov.f32 	%f395, 0f35BFBE8E;
	mul.rn.f32 	%f396, %f366, %f395;
	add.f32 	%f397, %f394, %f390;
	sub.f32 	%f398, %f394, %f397;
	add.f32 	%f399, %f390, %f398;
	add.f32 	%f400, %f392, %f399;
	add.f32 	%f401, %f396, %f400;
	add.f32 	%f402, %f397, %f401;
	sub.f32 	%f403, %f397, %f402;
	add.f32 	%f404, %f401, %f403;
	mul.rn.f32 	%f405, %f356, %f402;
	neg.f32 	%f406, %f405;
	fma.rn.f32 	%f407, %f356, %f402, %f406;
	fma.rn.f32 	%f408, %f356, %f404, %f407;
	mov.f32 	%f409, 0f00000000;
	fma.rn.f32 	%f410, %f409, %f402, %f408;
	add.rn.f32 	%f411, %f405, %f410;
	neg.f32 	%f412, %f411;
	add.rn.f32 	%f413, %f405, %f412;
	add.rn.f32 	%f414, %f413, %f410;
	mov.b32 	%r215, %f411;
	setp.eq.s32 	%p44, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f415, %r216;
	add.f32 	%f416, %f414, 0f37000000;
	selp.f32 	%f73, %f416, %f414, %p44;
	selp.f32 	%f417, %f415, %f411, %p44;
	mov.f32 	%f418, 0f3FB8AA3B;
	mul.rn.f32 	%f419, %f417, %f418;
	cvt.rzi.f32.f32 	%f420, %f419;
	abs.f32 	%f421, %f420;
	setp.gt.f32 	%p45, %f421, 0f42FC0000;
	mov.b32 	%r217, %f420;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f422, %r219;
	selp.f32 	%f423, %f422, %f420, %p45;
	mov.f32 	%f424, 0fBF317218;
	fma.rn.f32 	%f425, %f423, %f424, %f417;
	mov.f32 	%f426, 0f3102E308;
	fma.rn.f32 	%f427, %f423, %f426, %f425;
	mul.f32 	%f428, %f427, 0f3FB8AA3B;
	add.f32 	%f429, %f423, 0f4B40007F;
	mov.b32 	%r220, %f429;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f430, %r221;
	ex2.approx.ftz.f32 	%f431, %f428;
	mul.f32 	%f74, %f431, %f430;
	setp.eq.f32 	%p46, %f74, 0f7F800000;
	mov.f32 	%f1144, 0f7F800000;
	@%p46 bra 	$L__BB0_39;

	fma.rn.f32 	%f1144, %f74, %f73, %f74;

$L__BB0_39:
	mov.f32 	%f1084, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f1083, %f1084;
	add.f32 	%f1082, %f1083, %f1083;
	mov.f32 	%f1081, 0f3EE8BA2E;
	sub.f32 	%f1080, %f1081, %f1082;
	abs.f32 	%f1079, %f1080;
	setp.lt.f32 	%p47, %f64, 0f00000000;
	setp.eq.f32 	%p48, %f1079, 0f3F800000;
	and.pred  	%p1, %p47, %p48;
	setp.eq.f32 	%p49, %f64, 0f00000000;
	@%p49 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f436, %f64, %f64;
	selp.f32 	%f1146, %f436, 0f00000000, %p48;
	bra.uni 	$L__BB0_44;

$L__BB0_147:
	mov.f32 	%f1036, 0f00000000;
	mov.u32 	%r368, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1036;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1036;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1036;}

	// end inline asm
	mov.u16 	%rs115, 0;
	st.global.v4.u16 	[%rd25], {%rs112, %rs113, %rs114, %rs115};

$L__BB0_148:
	ld.const.u64 	%rd99, [params+256];
	cvta.to.global.u64 	%rd100, %rd99;
	ld.const.u32 	%r342, [params+248];
	mad.lo.s32 	%r343, %r342, %r4, %r3;
	mul.wide.u32 	%rd101, %r343, 8;
	add.s64 	%rd26, %rd100, %rd101;
	setp.eq.s32 	%p167, %r368, 0;
	@%p167 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs122, %rs123, %rs124, %rs125}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1037, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1038, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1039, %rs124;}

	// end inline asm
	add.f32 	%f1040, %f1037, 0f00000000;
	add.f32 	%f1041, %f1038, 0f00000000;
	add.f32 	%f1042, %f1039, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1042;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1040;}

	// end inline asm
	mov.u16 	%rs126, 0;
	st.global.v4.u16 	[%rd26], {%rs119, %rs120, %rs121, %rs126};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1045, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1045;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1045;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1045;}

	// end inline asm
	mov.u16 	%rs130, 0;
	st.global.v4.u16 	[%rd26], {%rs127, %rs128, %rs129, %rs130};

$L__BB0_151:
	ld.const.u64 	%rd102, [params+272];
	cvta.to.global.u64 	%rd103, %rd102;
	ld.const.u32 	%r344, [params+264];
	mad.lo.s32 	%r345, %r344, %r4, %r3;
	mul.wide.u32 	%rd104, %r345, 8;
	add.s64 	%rd27, %rd103, %rd104;
	@%p167 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs137, %rs138, %rs139, %rs140}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1046, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1047, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1048, %rs139;}

	// end inline asm
	add.f32 	%f1049, %f1046, 0f00000000;
	add.f32 	%f1050, %f1047, 0f00000000;
	add.f32 	%f1051, %f1048, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1051;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1050;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1049;}

	// end inline asm
	mov.u16 	%rs141, 0;
	st.global.v4.u16 	[%rd27], {%rs134, %rs135, %rs136, %rs141};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1054, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1054;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1054;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1054;}

	// end inline asm
	mov.u16 	%rs145, 0;
	st.global.v4.u16 	[%rd27], {%rs142, %rs143, %rs144, %rs145};

$L__BB0_154:
	ld.const.u64 	%rd105, [params+288];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r346, [params+280];
	mad.lo.s32 	%r347, %r346, %r4, %r3;
	mul.wide.u32 	%rd107, %r347, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p167 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs152, %rs153, %rs154, %rs155}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1055, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1056, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1057, %rs154;}

	// end inline asm
	add.f32 	%f1058, %f1055, 0f00000000;
	add.f32 	%f1059, %f1056, 0f00000000;
	add.f32 	%f1060, %f1057, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1060;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1059;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1058;}

	// end inline asm
	mov.u16 	%rs156, 0;
	st.global.v4.u16 	[%rd28], {%rs149, %rs150, %rs151, %rs156};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1063, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1063;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1063;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1063;}

	// end inline asm
	mov.u16 	%rs160, 0;
	st.global.v4.u16 	[%rd28], {%rs157, %rs158, %rs159, %rs160};

$L__BB0_157:
	ld.const.u64 	%rd108, [params+304];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r348, [params+296];
	mad.lo.s32 	%r349, %r348, %r4, %r3;
	mul.wide.u32 	%rd110, %r349, 8;
	add.s64 	%rd29, %rd109, %rd110;
	@%p167 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs167, %rs168, %rs169, %rs170}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1064, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1065, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1066, %rs169;}

	// end inline asm
	add.f32 	%f1067, %f1064, 0f00000000;
	add.f32 	%f1068, %f1065, 0f00000000;
	add.f32 	%f1069, %f1066, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1069;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1068;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1067;}

	// end inline asm
	mov.u16 	%rs171, 0;
	st.global.v4.u16 	[%rd29], {%rs164, %rs165, %rs166, %rs171};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1072, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1072;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1072;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1072;}

	// end inline asm
	mov.u16 	%rs175, 0;
	st.global.v4.u16 	[%rd29], {%rs172, %rs173, %rs174, %rs175};
	bra.uni 	$L__BB0_160;

$L__BB0_40:
	mov.b32 	%r222, %f1144;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f432, %r223;
	selp.f32 	%f1146, %f432, %f1144, %p1;
	setp.geu.f32 	%p50, %f64, 0f00000000;
	@%p50 bra 	$L__BB0_44;

	mov.f32 	%f433, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f434, %f433;
	setp.eq.f32 	%p51, %f434, 0f3EE8BA2E;
	@%p51 bra 	$L__BB0_44;

	mov.f32 	%f1146, 0f7FFFFFFF;

$L__BB0_44:
	abs.f32 	%f1085, %f64;
	add.f32 	%f437, %f1085, 0f3EE8BA2E;
	mov.b32 	%r224, %f437;
	setp.lt.s32 	%p53, %r224, 2139095040;
	@%p53 bra 	$L__BB0_49;

	abs.f32 	%f1086, %f64;
	setp.gtu.f32 	%p54, %f1086, 0f7F800000;
	@%p54 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1146, %f64, 0f3EE8BA2E;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	abs.f32 	%f1087, %f64;
	setp.neu.f32 	%p55, %f1087, 0f7F800000;
	@%p55 bra 	$L__BB0_49;

	selp.f32 	%f1146, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	ld.const.u32 	%r355, [params+184];
	mad.lo.s32 	%r354, %r355, %r4, %r3;
	cvt.u64.u32 	%rd116, %r354;
	ld.const.u64 	%rd115, [params+192];
	cvta.to.global.u64 	%rd114, %rd115;
	mul.f32 	%f438, %f1146, 0f437F0000;
	setp.eq.f32 	%p56, %f64, 0f3F800000;
	selp.f32 	%f439, 0f437F0000, %f438, %p56;
	cvt.rzi.u32.f32 	%r225, %f439;
	shl.b64 	%rd68, %rd116, 1;
	add.s64 	%rd69, %rd114, %rd68;
	cvt.u16.u32 	%rs17, %r225;
	mov.u16 	%rs18, 255;
	st.global.v2.u8 	[%rd69], {%rs17, %rs18};

$L__BB0_50:
	ld.const.u32 	%r353, [params+104];
	and.b32  	%r226, %r353, 1;
	setp.eq.b32 	%p57, %r226, 1;
	mov.pred 	%p58, 0;
	xor.pred  	%p59, %p57, %p58;
	not.pred 	%p60, %p59;
	@%p60 bra 	$L__BB0_124;

	mov.f32 	%f444, 0f3EE66666;
	abs.f32 	%f84, %f65;
	setp.lt.f32 	%p61, %f84, 0f00800000;
	mul.f32 	%f446, %f84, 0f4B800000;
	selp.f32 	%f447, %f446, %f84, %p61;
	selp.f32 	%f448, 0fC3170000, 0fC2FE0000, %p61;
	mov.b32 	%r227, %f447;
	and.b32  	%r228, %r227, 8388607;
	or.b32  	%r229, %r228, 1065353216;
	mov.b32 	%f449, %r229;
	shr.u32 	%r230, %r227, 23;
	cvt.rn.f32.u32 	%f450, %r230;
	add.f32 	%f451, %f448, %f450;
	setp.gt.f32 	%p62, %f449, 0f3FB504F3;
	mul.f32 	%f452, %f449, 0f3F000000;
	add.f32 	%f453, %f451, 0f3F800000;
	selp.f32 	%f454, %f453, %f451, %p62;
	selp.f32 	%f455, %f452, %f449, %p62;
	add.f32 	%f456, %f455, 0fBF800000;
	add.f32 	%f457, %f455, 0f3F800000;
	rcp.approx.ftz.f32 	%f458, %f457;
	add.f32 	%f459, %f456, %f456;
	mul.f32 	%f460, %f459, %f458;
	mul.f32 	%f461, %f460, %f460;
	mov.f32 	%f462, 0f3C4CAF63;
	mov.f32 	%f463, 0f3B18F0FE;
	fma.rn.f32 	%f464, %f463, %f461, %f462;
	mov.f32 	%f465, 0f3DAAAABD;
	fma.rn.f32 	%f466, %f464, %f461, %f465;
	mul.rn.f32 	%f467, %f466, %f461;
	mul.rn.f32 	%f468, %f467, %f460;
	sub.f32 	%f469, %f456, %f460;
	add.f32 	%f470, %f469, %f469;
	neg.f32 	%f471, %f460;
	fma.rn.f32 	%f472, %f471, %f456, %f470;
	mul.rn.f32 	%f473, %f458, %f472;
	add.f32 	%f474, %f468, %f460;
	sub.f32 	%f475, %f460, %f474;
	add.f32 	%f476, %f468, %f475;
	add.f32 	%f477, %f473, %f476;
	add.f32 	%f478, %f474, %f477;
	sub.f32 	%f479, %f474, %f478;
	add.f32 	%f480, %f477, %f479;
	mov.f32 	%f481, 0f3F317200;
	mul.rn.f32 	%f482, %f454, %f481;
	mov.f32 	%f483, 0f35BFBE8E;
	mul.rn.f32 	%f484, %f454, %f483;
	add.f32 	%f485, %f482, %f478;
	sub.f32 	%f486, %f482, %f485;
	add.f32 	%f487, %f478, %f486;
	add.f32 	%f488, %f480, %f487;
	add.f32 	%f489, %f484, %f488;
	add.f32 	%f490, %f485, %f489;
	sub.f32 	%f491, %f485, %f490;
	add.f32 	%f492, %f489, %f491;
	mul.rn.f32 	%f493, %f444, %f490;
	neg.f32 	%f494, %f493;
	fma.rn.f32 	%f495, %f444, %f490, %f494;
	fma.rn.f32 	%f496, %f444, %f492, %f495;
	mov.f32 	%f497, 0f00000000;
	fma.rn.f32 	%f498, %f497, %f490, %f496;
	add.rn.f32 	%f499, %f493, %f498;
	neg.f32 	%f500, %f499;
	add.rn.f32 	%f501, %f493, %f500;
	add.rn.f32 	%f502, %f501, %f498;
	mov.b32 	%r231, %f499;
	setp.eq.s32 	%p63, %r231, 1118925336;
	add.s32 	%r232, %r231, -1;
	mov.b32 	%f503, %r232;
	add.f32 	%f504, %f502, 0f37000000;
	selp.f32 	%f85, %f504, %f502, %p63;
	selp.f32 	%f505, %f503, %f499, %p63;
	mov.f32 	%f506, 0f3FB8AA3B;
	mul.rn.f32 	%f507, %f505, %f506;
	cvt.rzi.f32.f32 	%f508, %f507;
	abs.f32 	%f509, %f508;
	setp.gt.f32 	%p64, %f509, 0f42FC0000;
	mov.b32 	%r233, %f508;
	and.b32  	%r234, %r233, -2147483648;
	or.b32  	%r235, %r234, 1123811328;
	mov.b32 	%f510, %r235;
	selp.f32 	%f511, %f510, %f508, %p64;
	mov.f32 	%f512, 0fBF317218;
	fma.rn.f32 	%f513, %f511, %f512, %f505;
	mov.f32 	%f514, 0f3102E308;
	fma.rn.f32 	%f515, %f511, %f514, %f513;
	mul.f32 	%f516, %f515, 0f3FB8AA3B;
	add.f32 	%f517, %f511, 0f4B40007F;
	mov.b32 	%r236, %f517;
	shl.b32 	%r237, %r236, 23;
	mov.b32 	%f518, %r237;
	ex2.approx.ftz.f32 	%f519, %f516;
	mul.f32 	%f86, %f519, %f518;
	setp.eq.f32 	%p65, %f86, 0f7F800000;
	mov.f32 	%f1147, 0f7F800000;
	@%p65 bra 	$L__BB0_53;

	fma.rn.f32 	%f1147, %f86, %f85, %f86;

$L__BB0_53:
	mov.f32 	%f1093, 0f3E666666;
	cvt.rzi.f32.f32 	%f1092, %f1093;
	add.f32 	%f1091, %f1092, %f1092;
	mov.f32 	%f1090, 0f3EE66666;
	sub.f32 	%f1089, %f1090, %f1091;
	abs.f32 	%f1088, %f1089;
	setp.lt.f32 	%p66, %f65, 0f00000000;
	setp.eq.f32 	%p67, %f1088, 0f3F800000;
	and.pred  	%p2, %p66, %p67;
	setp.eq.f32 	%p68, %f65, 0f00000000;
	@%p68 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f524, %f65, %f65;
	selp.f32 	%f1149, %f524, 0f00000000, %p67;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r238, %f1147;
	xor.b32  	%r239, %r238, -2147483648;
	mov.b32 	%f520, %r239;
	selp.f32 	%f1149, %f520, %f1147, %p2;
	setp.geu.f32 	%p69, %f65, 0f00000000;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f521, 0f3EE66666;
	cvt.rzi.f32.f32 	%f522, %f521;
	setp.eq.f32 	%p70, %f522, 0f3EE66666;
	@%p70 bra 	$L__BB0_58;

	mov.f32 	%f1149, 0f7FFFFFFF;

$L__BB0_58:
	abs.f32 	%f1094, %f65;
	add.f32 	%f525, %f1094, 0f3EE66666;
	mov.b32 	%r240, %f525;
	setp.lt.s32 	%p72, %r240, 2139095040;
	@%p72 bra 	$L__BB0_63;

	abs.f32 	%f1095, %f65;
	setp.gtu.f32 	%p73, %f1095, 0f7F800000;
	@%p73 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1149, %f65, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	abs.f32 	%f1096, %f65;
	setp.neu.f32 	%p74, %f1096, 0f7F800000;
	@%p74 bra 	$L__BB0_63;

	selp.f32 	%f1149, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p75, %f65, 0f3F800000;
	selp.f32 	%f95, 0f3F800000, %f1149, %p75;
	abs.f32 	%f96, %f66;
	setp.lt.f32 	%p76, %f96, 0f00800000;
	mul.f32 	%f527, %f96, 0f4B800000;
	selp.f32 	%f528, %f527, %f96, %p76;
	selp.f32 	%f529, 0fC3170000, 0fC2FE0000, %p76;
	mov.b32 	%r241, %f528;
	and.b32  	%r242, %r241, 8388607;
	or.b32  	%r243, %r242, 1065353216;
	mov.b32 	%f530, %r243;
	shr.u32 	%r244, %r241, 23;
	cvt.rn.f32.u32 	%f531, %r244;
	add.f32 	%f532, %f529, %f531;
	setp.gt.f32 	%p77, %f530, 0f3FB504F3;
	mul.f32 	%f533, %f530, 0f3F000000;
	add.f32 	%f534, %f532, 0f3F800000;
	selp.f32 	%f535, %f534, %f532, %p77;
	selp.f32 	%f536, %f533, %f530, %p77;
	add.f32 	%f537, %f536, 0fBF800000;
	add.f32 	%f538, %f536, 0f3F800000;
	rcp.approx.ftz.f32 	%f539, %f538;
	add.f32 	%f540, %f537, %f537;
	mul.f32 	%f541, %f540, %f539;
	mul.f32 	%f542, %f541, %f541;
	mov.f32 	%f543, 0f3C4CAF63;
	mov.f32 	%f544, 0f3B18F0FE;
	fma.rn.f32 	%f545, %f544, %f542, %f543;
	mov.f32 	%f546, 0f3DAAAABD;
	fma.rn.f32 	%f547, %f545, %f542, %f546;
	mul.rn.f32 	%f548, %f547, %f542;
	mul.rn.f32 	%f549, %f548, %f541;
	sub.f32 	%f550, %f537, %f541;
	add.f32 	%f551, %f550, %f550;
	neg.f32 	%f552, %f541;
	fma.rn.f32 	%f553, %f552, %f537, %f551;
	mul.rn.f32 	%f554, %f539, %f553;
	add.f32 	%f555, %f549, %f541;
	sub.f32 	%f556, %f541, %f555;
	add.f32 	%f557, %f549, %f556;
	add.f32 	%f558, %f554, %f557;
	add.f32 	%f559, %f555, %f558;
	sub.f32 	%f560, %f555, %f559;
	add.f32 	%f561, %f558, %f560;
	mov.f32 	%f562, 0f3F317200;
	mul.rn.f32 	%f563, %f535, %f562;
	mov.f32 	%f564, 0f35BFBE8E;
	mul.rn.f32 	%f565, %f535, %f564;
	add.f32 	%f566, %f563, %f559;
	sub.f32 	%f567, %f563, %f566;
	add.f32 	%f568, %f559, %f567;
	add.f32 	%f569, %f561, %f568;
	add.f32 	%f570, %f565, %f569;
	add.f32 	%f571, %f566, %f570;
	sub.f32 	%f572, %f566, %f571;
	add.f32 	%f573, %f570, %f572;
	mov.f32 	%f574, 0f3EE66666;
	mul.rn.f32 	%f575, %f574, %f571;
	neg.f32 	%f576, %f575;
	fma.rn.f32 	%f577, %f574, %f571, %f576;
	fma.rn.f32 	%f578, %f574, %f573, %f577;
	mov.f32 	%f579, 0f00000000;
	fma.rn.f32 	%f580, %f579, %f571, %f578;
	add.rn.f32 	%f581, %f575, %f580;
	neg.f32 	%f582, %f581;
	add.rn.f32 	%f583, %f575, %f582;
	add.rn.f32 	%f584, %f583, %f580;
	mov.b32 	%r245, %f581;
	setp.eq.s32 	%p78, %r245, 1118925336;
	add.s32 	%r246, %r245, -1;
	mov.b32 	%f585, %r246;
	add.f32 	%f586, %f584, 0f37000000;
	selp.f32 	%f97, %f586, %f584, %p78;
	selp.f32 	%f587, %f585, %f581, %p78;
	mov.f32 	%f588, 0f3FB8AA3B;
	mul.rn.f32 	%f589, %f587, %f588;
	cvt.rzi.f32.f32 	%f590, %f589;
	abs.f32 	%f591, %f590;
	setp.gt.f32 	%p79, %f591, 0f42FC0000;
	mov.b32 	%r247, %f590;
	and.b32  	%r248, %r247, -2147483648;
	or.b32  	%r249, %r248, 1123811328;
	mov.b32 	%f592, %r249;
	selp.f32 	%f593, %f592, %f590, %p79;
	mov.f32 	%f594, 0fBF317218;
	fma.rn.f32 	%f595, %f593, %f594, %f587;
	mov.f32 	%f596, 0f3102E308;
	fma.rn.f32 	%f597, %f593, %f596, %f595;
	mul.f32 	%f598, %f597, 0f3FB8AA3B;
	add.f32 	%f599, %f593, 0f4B40007F;
	mov.b32 	%r250, %f599;
	shl.b32 	%r251, %r250, 23;
	mov.b32 	%f600, %r251;
	ex2.approx.ftz.f32 	%f601, %f598;
	mul.f32 	%f98, %f601, %f600;
	setp.eq.f32 	%p80, %f98, 0f7F800000;
	mov.f32 	%f1150, 0f7F800000;
	@%p80 bra 	$L__BB0_65;

	fma.rn.f32 	%f1150, %f98, %f97, %f98;

$L__BB0_65:
	setp.lt.f32 	%p81, %f66, 0f00000000;
	and.pred  	%p3, %p81, %p67;
	setp.eq.f32 	%p83, %f66, 0f00000000;
	@%p83 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f606, %f66, %f66;
	selp.f32 	%f1152, %f606, 0f00000000, %p67;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r252, %f1150;
	xor.b32  	%r253, %r252, -2147483648;
	mov.b32 	%f602, %r253;
	selp.f32 	%f1152, %f602, %f1150, %p3;
	setp.geu.f32 	%p84, %f66, 0f00000000;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f603, 0f3EE66666;
	cvt.rzi.f32.f32 	%f604, %f603;
	setp.eq.f32 	%p85, %f604, 0f3EE66666;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f1152, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1097, %f66;
	add.f32 	%f607, %f1097, 0f3EE66666;
	mov.b32 	%r254, %f607;
	setp.lt.s32 	%p87, %r254, 2139095040;
	@%p87 bra 	$L__BB0_75;

	abs.f32 	%f1098, %f66;
	setp.gtu.f32 	%p88, %f1098, 0f7F800000;
	@%p88 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1152, %f66, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1099, %f66;
	setp.neu.f32 	%p89, %f1099, 0f7F800000;
	@%p89 bra 	$L__BB0_75;

	selp.f32 	%f1152, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p90, %f66, 0f3F800000;
	selp.f32 	%f107, 0f3F800000, %f1152, %p90;
	abs.f32 	%f108, %f67;
	setp.lt.f32 	%p91, %f108, 0f00800000;
	mul.f32 	%f609, %f108, 0f4B800000;
	selp.f32 	%f610, %f609, %f108, %p91;
	selp.f32 	%f611, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r255, %f610;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f612, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f613, %r258;
	add.f32 	%f614, %f611, %f613;
	setp.gt.f32 	%p92, %f612, 0f3FB504F3;
	mul.f32 	%f615, %f612, 0f3F000000;
	add.f32 	%f616, %f614, 0f3F800000;
	selp.f32 	%f617, %f616, %f614, %p92;
	selp.f32 	%f618, %f615, %f612, %p92;
	add.f32 	%f619, %f618, 0fBF800000;
	add.f32 	%f620, %f618, 0f3F800000;
	rcp.approx.ftz.f32 	%f621, %f620;
	add.f32 	%f622, %f619, %f619;
	mul.f32 	%f623, %f622, %f621;
	mul.f32 	%f624, %f623, %f623;
	mov.f32 	%f625, 0f3C4CAF63;
	mov.f32 	%f626, 0f3B18F0FE;
	fma.rn.f32 	%f627, %f626, %f624, %f625;
	mov.f32 	%f628, 0f3DAAAABD;
	fma.rn.f32 	%f629, %f627, %f624, %f628;
	mul.rn.f32 	%f630, %f629, %f624;
	mul.rn.f32 	%f631, %f630, %f623;
	sub.f32 	%f632, %f619, %f623;
	add.f32 	%f633, %f632, %f632;
	neg.f32 	%f634, %f623;
	fma.rn.f32 	%f635, %f634, %f619, %f633;
	mul.rn.f32 	%f636, %f621, %f635;
	add.f32 	%f637, %f631, %f623;
	sub.f32 	%f638, %f623, %f637;
	add.f32 	%f639, %f631, %f638;
	add.f32 	%f640, %f636, %f639;
	add.f32 	%f641, %f637, %f640;
	sub.f32 	%f642, %f637, %f641;
	add.f32 	%f643, %f640, %f642;
	mov.f32 	%f644, 0f3F317200;
	mul.rn.f32 	%f645, %f617, %f644;
	mov.f32 	%f646, 0f35BFBE8E;
	mul.rn.f32 	%f647, %f617, %f646;
	add.f32 	%f648, %f645, %f641;
	sub.f32 	%f649, %f645, %f648;
	add.f32 	%f650, %f641, %f649;
	add.f32 	%f651, %f643, %f650;
	add.f32 	%f652, %f647, %f651;
	add.f32 	%f653, %f648, %f652;
	sub.f32 	%f654, %f648, %f653;
	add.f32 	%f655, %f652, %f654;
	mov.f32 	%f656, 0f3EE66666;
	mul.rn.f32 	%f657, %f656, %f653;
	neg.f32 	%f658, %f657;
	fma.rn.f32 	%f659, %f656, %f653, %f658;
	fma.rn.f32 	%f660, %f656, %f655, %f659;
	mov.f32 	%f661, 0f00000000;
	fma.rn.f32 	%f662, %f661, %f653, %f660;
	add.rn.f32 	%f663, %f657, %f662;
	neg.f32 	%f664, %f663;
	add.rn.f32 	%f665, %f657, %f664;
	add.rn.f32 	%f666, %f665, %f662;
	mov.b32 	%r259, %f663;
	setp.eq.s32 	%p93, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f667, %r260;
	add.f32 	%f668, %f666, 0f37000000;
	selp.f32 	%f109, %f668, %f666, %p93;
	selp.f32 	%f669, %f667, %f663, %p93;
	mov.f32 	%f670, 0f3FB8AA3B;
	mul.rn.f32 	%f671, %f669, %f670;
	cvt.rzi.f32.f32 	%f672, %f671;
	abs.f32 	%f673, %f672;
	setp.gt.f32 	%p94, %f673, 0f42FC0000;
	mov.b32 	%r261, %f672;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f674, %r263;
	selp.f32 	%f675, %f674, %f672, %p94;
	mov.f32 	%f676, 0fBF317218;
	fma.rn.f32 	%f677, %f675, %f676, %f669;
	mov.f32 	%f678, 0f3102E308;
	fma.rn.f32 	%f679, %f675, %f678, %f677;
	mul.f32 	%f680, %f679, 0f3FB8AA3B;
	add.f32 	%f681, %f675, 0f4B40007F;
	mov.b32 	%r264, %f681;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f682, %r265;
	ex2.approx.ftz.f32 	%f683, %f680;
	mul.f32 	%f110, %f683, %f682;
	setp.eq.f32 	%p95, %f110, 0f7F800000;
	mov.f32 	%f1153, 0f7F800000;
	@%p95 bra 	$L__BB0_77;

	fma.rn.f32 	%f1153, %f110, %f109, %f110;

$L__BB0_77:
	setp.lt.f32 	%p96, %f67, 0f00000000;
	and.pred  	%p4, %p96, %p67;
	setp.eq.f32 	%p98, %f67, 0f00000000;
	@%p98 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f688, %f67, %f67;
	selp.f32 	%f1155, %f688, 0f00000000, %p67;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r266, %f1153;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f684, %r267;
	selp.f32 	%f1155, %f684, %f1153, %p4;
	setp.geu.f32 	%p99, %f67, 0f00000000;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f685, 0f3EE66666;
	cvt.rzi.f32.f32 	%f686, %f685;
	setp.eq.f32 	%p100, %f686, 0f3EE66666;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f1155, 0f7FFFFFFF;

$L__BB0_82:
	abs.f32 	%f1100, %f67;
	add.f32 	%f689, %f1100, 0f3EE66666;
	mov.b32 	%r268, %f689;
	setp.lt.s32 	%p102, %r268, 2139095040;
	@%p102 bra 	$L__BB0_87;

	abs.f32 	%f1101, %f67;
	setp.gtu.f32 	%p103, %f1101, 0f7F800000;
	@%p103 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1155, %f67, 0f3EE66666;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	abs.f32 	%f1102, %f67;
	setp.neu.f32 	%p104, %f1102, 0f7F800000;
	@%p104 bra 	$L__BB0_87;

	selp.f32 	%f1155, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	setp.eq.f32 	%p105, %f67, 0f3F800000;
	mov.f32 	%f691, 0f3F800000;
	selp.f32 	%f692, 0f3F800000, %f1155, %p105;
	min.f32 	%f693, %f95, %f691;
	mov.f32 	%f694, 0f00000000;
	max.f32 	%f119, %f694, %f693;
	min.f32 	%f695, %f107, %f691;
	max.f32 	%f120, %f694, %f695;
	min.f32 	%f696, %f692, %f691;
	max.f32 	%f121, %f694, %f696;
	mov.f32 	%f700, 0f3ED55555;
	abs.f32 	%f123, %f119;
	setp.lt.f32 	%p106, %f123, 0f00800000;
	mul.f32 	%f702, %f123, 0f4B800000;
	selp.f32 	%f703, %f702, %f123, %p106;
	selp.f32 	%f704, 0fC3170000, 0fC2FE0000, %p106;
	mov.b32 	%r271, %f703;
	and.b32  	%r272, %r271, 8388607;
	or.b32  	%r273, %r272, 1065353216;
	mov.b32 	%f705, %r273;
	shr.u32 	%r274, %r271, 23;
	cvt.rn.f32.u32 	%f706, %r274;
	add.f32 	%f707, %f704, %f706;
	setp.gt.f32 	%p107, %f705, 0f3FB504F3;
	mul.f32 	%f708, %f705, 0f3F000000;
	add.f32 	%f709, %f707, 0f3F800000;
	selp.f32 	%f710, %f709, %f707, %p107;
	selp.f32 	%f711, %f708, %f705, %p107;
	add.f32 	%f712, %f711, 0fBF800000;
	add.f32 	%f713, %f711, 0f3F800000;
	rcp.approx.ftz.f32 	%f714, %f713;
	add.f32 	%f715, %f712, %f712;
	mul.f32 	%f716, %f715, %f714;
	mul.f32 	%f717, %f716, %f716;
	mov.f32 	%f718, 0f3C4CAF63;
	mov.f32 	%f719, 0f3B18F0FE;
	fma.rn.f32 	%f720, %f719, %f717, %f718;
	mov.f32 	%f721, 0f3DAAAABD;
	fma.rn.f32 	%f722, %f720, %f717, %f721;
	mul.rn.f32 	%f723, %f722, %f717;
	mul.rn.f32 	%f724, %f723, %f716;
	sub.f32 	%f725, %f712, %f716;
	add.f32 	%f726, %f725, %f725;
	neg.f32 	%f727, %f716;
	fma.rn.f32 	%f728, %f727, %f712, %f726;
	mul.rn.f32 	%f729, %f714, %f728;
	add.f32 	%f730, %f724, %f716;
	sub.f32 	%f731, %f716, %f730;
	add.f32 	%f732, %f724, %f731;
	add.f32 	%f733, %f729, %f732;
	add.f32 	%f734, %f730, %f733;
	sub.f32 	%f735, %f730, %f734;
	add.f32 	%f736, %f733, %f735;
	mov.f32 	%f737, 0f3F317200;
	mul.rn.f32 	%f738, %f710, %f737;
	mov.f32 	%f739, 0f35BFBE8E;
	mul.rn.f32 	%f740, %f710, %f739;
	add.f32 	%f741, %f738, %f734;
	sub.f32 	%f742, %f738, %f741;
	add.f32 	%f743, %f734, %f742;
	add.f32 	%f744, %f736, %f743;
	add.f32 	%f745, %f740, %f744;
	add.f32 	%f746, %f741, %f745;
	sub.f32 	%f747, %f741, %f746;
	add.f32 	%f748, %f745, %f747;
	mul.rn.f32 	%f749, %f700, %f746;
	neg.f32 	%f750, %f749;
	fma.rn.f32 	%f751, %f700, %f746, %f750;
	fma.rn.f32 	%f752, %f700, %f748, %f751;
	fma.rn.f32 	%f753, %f694, %f746, %f752;
	add.rn.f32 	%f754, %f749, %f753;
	neg.f32 	%f755, %f754;
	add.rn.f32 	%f756, %f749, %f755;
	add.rn.f32 	%f757, %f756, %f753;
	mov.b32 	%r275, %f754;
	setp.eq.s32 	%p108, %r275, 1118925336;
	add.s32 	%r276, %r275, -1;
	mov.b32 	%f758, %r276;
	add.f32 	%f759, %f757, 0f37000000;
	selp.f32 	%f124, %f759, %f757, %p108;
	selp.f32 	%f760, %f758, %f754, %p108;
	mov.f32 	%f761, 0f3FB8AA3B;
	mul.rn.f32 	%f762, %f760, %f761;
	cvt.rzi.f32.f32 	%f763, %f762;
	abs.f32 	%f764, %f763;
	setp.gt.f32 	%p109, %f764, 0f42FC0000;
	mov.b32 	%r277, %f763;
	and.b32  	%r278, %r277, -2147483648;
	or.b32  	%r279, %r278, 1123811328;
	mov.b32 	%f765, %r279;
	selp.f32 	%f766, %f765, %f763, %p109;
	mov.f32 	%f767, 0fBF317218;
	fma.rn.f32 	%f768, %f766, %f767, %f760;
	mov.f32 	%f769, 0f3102E308;
	fma.rn.f32 	%f770, %f766, %f769, %f768;
	mul.f32 	%f771, %f770, 0f3FB8AA3B;
	add.f32 	%f772, %f766, 0f4B40007F;
	mov.b32 	%r280, %f772;
	shl.b32 	%r281, %r280, 23;
	mov.b32 	%f773, %r281;
	ex2.approx.ftz.f32 	%f774, %f771;
	mul.f32 	%f125, %f774, %f773;
	setp.eq.f32 	%p110, %f125, 0f7F800000;
	mov.f32 	%f1156, 0f7F800000;
	@%p110 bra 	$L__BB0_89;

	fma.rn.f32 	%f1156, %f125, %f124, %f125;

$L__BB0_89:
	mov.f32 	%f1113, 0f00000000;
	max.f32 	%f1112, %f1113, %f693;
	mov.f32 	%f1078, 0f3E555555;
	cvt.rzi.f32.f32 	%f1077, %f1078;
	add.f32 	%f1076, %f1077, %f1077;
	mov.f32 	%f1075, 0f3ED55555;
	sub.f32 	%f1074, %f1075, %f1076;
	abs.f32 	%f1073, %f1074;
	setp.lt.f32 	%p111, %f1112, 0f00000000;
	setp.eq.f32 	%p112, %f1073, 0f3F800000;
	and.pred  	%p5, %p111, %p112;
	setp.eq.f32 	%p113, %f1112, 0f00000000;
	@%p113 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	mov.f32 	%f1130, 0f00000000;
	max.f32 	%f1129, %f1130, %f693;
	add.f32 	%f779, %f1129, %f1129;
	selp.f32 	%f1158, %f779, 0f00000000, %p112;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.f32 	%f1115, 0f00000000;
	max.f32 	%f1114, %f1115, %f693;
	mov.b32 	%r282, %f1156;
	xor.b32  	%r283, %r282, -2147483648;
	mov.b32 	%f775, %r283;
	selp.f32 	%f1158, %f775, %f1156, %p5;
	setp.geu.f32 	%p114, %f1114, 0f00000000;
	@%p114 bra 	$L__BB0_94;

	mov.f32 	%f776, 0f3ED55555;
	cvt.rzi.f32.f32 	%f777, %f776;
	setp.eq.f32 	%p115, %f777, 0f3ED55555;
	@%p115 bra 	$L__BB0_94;

	mov.f32 	%f1158, 0f7FFFFFFF;

$L__BB0_94:
	mov.f32 	%f1118, 0f00000000;
	max.f32 	%f1117, %f1118, %f693;
	abs.f32 	%f1116, %f1117;
	add.f32 	%f780, %f1116, 0f3ED55555;
	mov.b32 	%r284, %f780;
	setp.lt.s32 	%p117, %r284, 2139095040;
	@%p117 bra 	$L__BB0_99;

	mov.f32 	%f1123, 0f00000000;
	max.f32 	%f1122, %f1123, %f693;
	abs.f32 	%f1121, %f1122;
	setp.gtu.f32 	%p118, %f1121, 0f7F800000;
	@%p118 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	mov.f32 	%f1128, 0f00000000;
	max.f32 	%f1127, %f1128, %f693;
	add.f32 	%f1158, %f1127, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	mov.f32 	%f1126, 0f00000000;
	max.f32 	%f1125, %f1126, %f693;
	abs.f32 	%f1124, %f1125;
	setp.neu.f32 	%p119, %f1124, 0f7F800000;
	@%p119 bra 	$L__BB0_99;

	selp.f32 	%f1158, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f134, %f120;
	setp.lt.f32 	%p120, %f134, 0f00800000;
	mul.f32 	%f782, %f134, 0f4B800000;
	selp.f32 	%f783, %f782, %f134, %p120;
	selp.f32 	%f784, 0fC3170000, 0fC2FE0000, %p120;
	mov.b32 	%r285, %f783;
	and.b32  	%r286, %r285, 8388607;
	or.b32  	%r287, %r286, 1065353216;
	mov.b32 	%f785, %r287;
	shr.u32 	%r288, %r285, 23;
	cvt.rn.f32.u32 	%f786, %r288;
	add.f32 	%f787, %f784, %f786;
	setp.gt.f32 	%p121, %f785, 0f3FB504F3;
	mul.f32 	%f788, %f785, 0f3F000000;
	add.f32 	%f789, %f787, 0f3F800000;
	selp.f32 	%f790, %f789, %f787, %p121;
	selp.f32 	%f791, %f788, %f785, %p121;
	add.f32 	%f792, %f791, 0fBF800000;
	add.f32 	%f793, %f791, 0f3F800000;
	rcp.approx.ftz.f32 	%f794, %f793;
	add.f32 	%f795, %f792, %f792;
	mul.f32 	%f796, %f795, %f794;
	mul.f32 	%f797, %f796, %f796;
	mov.f32 	%f798, 0f3C4CAF63;
	mov.f32 	%f799, 0f3B18F0FE;
	fma.rn.f32 	%f800, %f799, %f797, %f798;
	mov.f32 	%f801, 0f3DAAAABD;
	fma.rn.f32 	%f802, %f800, %f797, %f801;
	mul.rn.f32 	%f803, %f802, %f797;
	mul.rn.f32 	%f804, %f803, %f796;
	sub.f32 	%f805, %f792, %f796;
	add.f32 	%f806, %f805, %f805;
	neg.f32 	%f807, %f796;
	fma.rn.f32 	%f808, %f807, %f792, %f806;
	mul.rn.f32 	%f809, %f794, %f808;
	add.f32 	%f810, %f804, %f796;
	sub.f32 	%f811, %f796, %f810;
	add.f32 	%f812, %f804, %f811;
	add.f32 	%f813, %f809, %f812;
	add.f32 	%f814, %f810, %f813;
	sub.f32 	%f815, %f810, %f814;
	add.f32 	%f816, %f813, %f815;
	mov.f32 	%f817, 0f3F317200;
	mul.rn.f32 	%f818, %f790, %f817;
	mov.f32 	%f819, 0f35BFBE8E;
	mul.rn.f32 	%f820, %f790, %f819;
	add.f32 	%f821, %f818, %f814;
	sub.f32 	%f822, %f818, %f821;
	add.f32 	%f823, %f814, %f822;
	add.f32 	%f824, %f816, %f823;
	add.f32 	%f825, %f820, %f824;
	add.f32 	%f826, %f821, %f825;
	sub.f32 	%f827, %f821, %f826;
	add.f32 	%f828, %f825, %f827;
	mov.f32 	%f829, 0f3ED55555;
	mul.rn.f32 	%f830, %f829, %f826;
	neg.f32 	%f831, %f830;
	fma.rn.f32 	%f832, %f829, %f826, %f831;
	fma.rn.f32 	%f833, %f829, %f828, %f832;
	mov.f32 	%f834, 0f00000000;
	fma.rn.f32 	%f835, %f834, %f826, %f833;
	add.rn.f32 	%f836, %f830, %f835;
	neg.f32 	%f837, %f836;
	add.rn.f32 	%f838, %f830, %f837;
	add.rn.f32 	%f839, %f838, %f835;
	mov.b32 	%r289, %f836;
	setp.eq.s32 	%p122, %r289, 1118925336;
	add.s32 	%r290, %r289, -1;
	mov.b32 	%f840, %r290;
	add.f32 	%f841, %f839, 0f37000000;
	selp.f32 	%f135, %f841, %f839, %p122;
	selp.f32 	%f842, %f840, %f836, %p122;
	mov.f32 	%f843, 0f3FB8AA3B;
	mul.rn.f32 	%f844, %f842, %f843;
	cvt.rzi.f32.f32 	%f845, %f844;
	abs.f32 	%f846, %f845;
	setp.gt.f32 	%p123, %f846, 0f42FC0000;
	mov.b32 	%r291, %f845;
	and.b32  	%r292, %r291, -2147483648;
	or.b32  	%r293, %r292, 1123811328;
	mov.b32 	%f847, %r293;
	selp.f32 	%f848, %f847, %f845, %p123;
	mov.f32 	%f849, 0fBF317218;
	fma.rn.f32 	%f850, %f848, %f849, %f842;
	mov.f32 	%f851, 0f3102E308;
	fma.rn.f32 	%f852, %f848, %f851, %f850;
	mul.f32 	%f853, %f852, 0f3FB8AA3B;
	add.f32 	%f854, %f848, 0f4B40007F;
	mov.b32 	%r294, %f854;
	shl.b32 	%r295, %r294, 23;
	mov.b32 	%f855, %r295;
	ex2.approx.ftz.f32 	%f856, %f853;
	mul.f32 	%f136, %f856, %f855;
	setp.eq.f32 	%p124, %f136, 0f7F800000;
	mov.f32 	%f1159, 0f7F800000;
	@%p124 bra 	$L__BB0_101;

	fma.rn.f32 	%f1159, %f136, %f135, %f136;

$L__BB0_101:
	setp.lt.f32 	%p125, %f120, 0f00000000;
	and.pred  	%p6, %p125, %p112;
	setp.eq.f32 	%p127, %f120, 0f00000000;
	@%p127 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f861, %f120, %f120;
	selp.f32 	%f1161, %f861, 0f00000000, %p112;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r296, %f1159;
	xor.b32  	%r297, %r296, -2147483648;
	mov.b32 	%f857, %r297;
	selp.f32 	%f1161, %f857, %f1159, %p6;
	setp.geu.f32 	%p128, %f120, 0f00000000;
	@%p128 bra 	$L__BB0_106;

	mov.f32 	%f858, 0f3ED55555;
	cvt.rzi.f32.f32 	%f859, %f858;
	setp.eq.f32 	%p129, %f859, 0f3ED55555;
	@%p129 bra 	$L__BB0_106;

	mov.f32 	%f1161, 0f7FFFFFFF;

$L__BB0_106:
	mov.f32 	%f1105, 0f00000000;
	max.f32 	%f1104, %f1105, %f695;
	abs.f32 	%f1103, %f1104;
	add.f32 	%f862, %f1103, 0f3ED55555;
	mov.b32 	%r298, %f862;
	setp.lt.s32 	%p131, %r298, 2139095040;
	@%p131 bra 	$L__BB0_111;

	mov.f32 	%f1108, 0f00000000;
	max.f32 	%f1107, %f1108, %f695;
	abs.f32 	%f1106, %f1107;
	setp.gtu.f32 	%p132, %f1106, 0f7F800000;
	@%p132 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1161, %f120, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	mov.f32 	%f1111, 0f00000000;
	max.f32 	%f1110, %f1111, %f695;
	abs.f32 	%f1109, %f1110;
	setp.neu.f32 	%p133, %f1109, 0f7F800000;
	@%p133 bra 	$L__BB0_111;

	selp.f32 	%f1161, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	abs.f32 	%f145, %f121;
	setp.lt.f32 	%p134, %f145, 0f00800000;
	mul.f32 	%f864, %f145, 0f4B800000;
	selp.f32 	%f865, %f864, %f145, %p134;
	selp.f32 	%f866, 0fC3170000, 0fC2FE0000, %p134;
	mov.b32 	%r299, %f865;
	and.b32  	%r300, %r299, 8388607;
	or.b32  	%r301, %r300, 1065353216;
	mov.b32 	%f867, %r301;
	shr.u32 	%r302, %r299, 23;
	cvt.rn.f32.u32 	%f868, %r302;
	add.f32 	%f869, %f866, %f868;
	setp.gt.f32 	%p135, %f867, 0f3FB504F3;
	mul.f32 	%f870, %f867, 0f3F000000;
	add.f32 	%f871, %f869, 0f3F800000;
	selp.f32 	%f872, %f871, %f869, %p135;
	selp.f32 	%f873, %f870, %f867, %p135;
	add.f32 	%f874, %f873, 0fBF800000;
	add.f32 	%f875, %f873, 0f3F800000;
	rcp.approx.ftz.f32 	%f876, %f875;
	add.f32 	%f877, %f874, %f874;
	mul.f32 	%f878, %f877, %f876;
	mul.f32 	%f879, %f878, %f878;
	mov.f32 	%f880, 0f3C4CAF63;
	mov.f32 	%f881, 0f3B18F0FE;
	fma.rn.f32 	%f882, %f881, %f879, %f880;
	mov.f32 	%f883, 0f3DAAAABD;
	fma.rn.f32 	%f884, %f882, %f879, %f883;
	mul.rn.f32 	%f885, %f884, %f879;
	mul.rn.f32 	%f886, %f885, %f878;
	sub.f32 	%f887, %f874, %f878;
	add.f32 	%f888, %f887, %f887;
	neg.f32 	%f889, %f878;
	fma.rn.f32 	%f890, %f889, %f874, %f888;
	mul.rn.f32 	%f891, %f876, %f890;
	add.f32 	%f892, %f886, %f878;
	sub.f32 	%f893, %f878, %f892;
	add.f32 	%f894, %f886, %f893;
	add.f32 	%f895, %f891, %f894;
	add.f32 	%f896, %f892, %f895;
	sub.f32 	%f897, %f892, %f896;
	add.f32 	%f898, %f895, %f897;
	mov.f32 	%f899, 0f3F317200;
	mul.rn.f32 	%f900, %f872, %f899;
	mov.f32 	%f901, 0f35BFBE8E;
	mul.rn.f32 	%f902, %f872, %f901;
	add.f32 	%f903, %f900, %f896;
	sub.f32 	%f904, %f900, %f903;
	add.f32 	%f905, %f896, %f904;
	add.f32 	%f906, %f898, %f905;
	add.f32 	%f907, %f902, %f906;
	add.f32 	%f908, %f903, %f907;
	sub.f32 	%f909, %f903, %f908;
	add.f32 	%f910, %f907, %f909;
	mov.f32 	%f911, 0f3ED55555;
	mul.rn.f32 	%f912, %f911, %f908;
	neg.f32 	%f913, %f912;
	fma.rn.f32 	%f914, %f911, %f908, %f913;
	fma.rn.f32 	%f915, %f911, %f910, %f914;
	mov.f32 	%f916, 0f00000000;
	fma.rn.f32 	%f917, %f916, %f908, %f915;
	add.rn.f32 	%f918, %f912, %f917;
	neg.f32 	%f919, %f918;
	add.rn.f32 	%f920, %f912, %f919;
	add.rn.f32 	%f921, %f920, %f917;
	mov.b32 	%r303, %f918;
	setp.eq.s32 	%p136, %r303, 1118925336;
	add.s32 	%r304, %r303, -1;
	mov.b32 	%f922, %r304;
	add.f32 	%f923, %f921, 0f37000000;
	selp.f32 	%f146, %f923, %f921, %p136;
	selp.f32 	%f924, %f922, %f918, %p136;
	mov.f32 	%f925, 0f3FB8AA3B;
	mul.rn.f32 	%f926, %f924, %f925;
	cvt.rzi.f32.f32 	%f927, %f926;
	abs.f32 	%f928, %f927;
	setp.gt.f32 	%p137, %f928, 0f42FC0000;
	mov.b32 	%r305, %f927;
	and.b32  	%r306, %r305, -2147483648;
	or.b32  	%r307, %r306, 1123811328;
	mov.b32 	%f929, %r307;
	selp.f32 	%f930, %f929, %f927, %p137;
	mov.f32 	%f931, 0fBF317218;
	fma.rn.f32 	%f932, %f930, %f931, %f924;
	mov.f32 	%f933, 0f3102E308;
	fma.rn.f32 	%f934, %f930, %f933, %f932;
	mul.f32 	%f935, %f934, 0f3FB8AA3B;
	add.f32 	%f936, %f930, 0f4B40007F;
	mov.b32 	%r308, %f936;
	shl.b32 	%r309, %r308, 23;
	mov.b32 	%f937, %r309;
	ex2.approx.ftz.f32 	%f938, %f935;
	mul.f32 	%f147, %f938, %f937;
	setp.eq.f32 	%p138, %f147, 0f7F800000;
	mov.f32 	%f1162, 0f7F800000;
	@%p138 bra 	$L__BB0_113;

	fma.rn.f32 	%f1162, %f147, %f146, %f147;

$L__BB0_113:
	setp.lt.f32 	%p139, %f121, 0f00000000;
	and.pred  	%p7, %p139, %p112;
	setp.eq.f32 	%p141, %f121, 0f00000000;
	@%p141 bra 	$L__BB0_117;
	bra.uni 	$L__BB0_114;

$L__BB0_117:
	add.f32 	%f943, %f121, %f121;
	selp.f32 	%f1164, %f943, 0f00000000, %p112;
	bra.uni 	$L__BB0_118;

$L__BB0_114:
	mov.b32 	%r310, %f1162;
	xor.b32  	%r311, %r310, -2147483648;
	mov.b32 	%f939, %r311;
	selp.f32 	%f1164, %f939, %f1162, %p7;
	setp.geu.f32 	%p142, %f121, 0f00000000;
	@%p142 bra 	$L__BB0_118;

	mov.f32 	%f940, 0f3ED55555;
	cvt.rzi.f32.f32 	%f941, %f940;
	setp.eq.f32 	%p143, %f941, 0f3ED55555;
	@%p143 bra 	$L__BB0_118;

	mov.f32 	%f1164, 0f7FFFFFFF;

$L__BB0_118:
	add.f32 	%f944, %f145, 0f3ED55555;
	mov.b32 	%r312, %f944;
	setp.lt.s32 	%p145, %r312, 2139095040;
	@%p145 bra 	$L__BB0_123;

	setp.gtu.f32 	%p146, %f145, 0f7F800000;
	@%p146 bra 	$L__BB0_122;
	bra.uni 	$L__BB0_120;

$L__BB0_122:
	add.f32 	%f1164, %f121, 0f3ED55555;
	bra.uni 	$L__BB0_123;

$L__BB0_120:
	setp.neu.f32 	%p147, %f145, 0f7F800000;
	@%p147 bra 	$L__BB0_123;

	selp.f32 	%f1164, 0fFF800000, 0f7F800000, %p7;

$L__BB0_123:
	mov.f32 	%f1120, 0f00000000;
	max.f32 	%f1119, %f1120, %f693;
	ld.const.u64 	%rd113, [params+144];
	cvta.to.global.u64 	%rd112, %rd113;
	ld.const.u32 	%r351, [params+136];
	mad.lo.s32 	%r350, %r351, %r4, %r3;
	cvt.u64.u32 	%rd111, %r350;
	fma.rn.f32 	%f945, %f1158, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p148, %f1119, 0f3F800000;
	mov.f32 	%f946, 0f3F800000;
	selp.f32 	%f947, 0f3F7FFFFF, %f945, %p148;
	mul.f32 	%f948, %f1119, 0f414EB852;
	setp.lt.f32 	%p149, %f1119, 0f3B4D2E1C;
	selp.f32 	%f949, %f948, %f947, %p149;
	fma.rn.f32 	%f950, %f1161, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p150, %f120, 0f3F800000;
	selp.f32 	%f951, 0f3F7FFFFF, %f950, %p150;
	mul.f32 	%f952, %f120, 0f414EB852;
	setp.lt.f32 	%p151, %f120, 0f3B4D2E1C;
	selp.f32 	%f953, %f952, %f951, %p151;
	fma.rn.f32 	%f954, %f1164, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p152, %f121, 0f3F800000;
	selp.f32 	%f955, 0f3F7FFFFF, %f954, %p152;
	mul.f32 	%f956, %f121, 0f414EB852;
	setp.lt.f32 	%p153, %f121, 0f3B4D2E1C;
	selp.f32 	%f957, %f956, %f955, %p153;
	min.f32 	%f958, %f949, %f946;
	mov.f32 	%f959, 0f00000000;
	max.f32 	%f960, %f959, %f958;
	mul.f32 	%f961, %f960, 0f43800000;
	cvt.rzi.u32.f32 	%r313, %f961;
	min.u32 	%r314, %r313, 255;
	min.f32 	%f962, %f953, %f946;
	max.f32 	%f963, %f959, %f962;
	mul.f32 	%f964, %f963, 0f43800000;
	cvt.rzi.u32.f32 	%r315, %f964;
	min.u32 	%r316, %r315, 255;
	min.f32 	%f965, %f957, %f946;
	max.f32 	%f966, %f959, %f965;
	mul.f32 	%f967, %f966, 0f43800000;
	cvt.rzi.u32.f32 	%r317, %f967;
	min.u32 	%r318, %r317, 255;
	shl.b64 	%rd71, %rd111, 2;
	add.s64 	%rd72, %rd112, %rd71;
	cvt.u16.u32 	%rs19, %r318;
	cvt.u16.u32 	%rs20, %r316;
	cvt.u16.u32 	%rs21, %r314;
	mov.u16 	%rs22, 255;
	st.global.v4.u8 	[%rd72], {%rs21, %rs20, %rs19, %rs22};

$L__BB0_124:
	ld.const.u32 	%r352, [params+104];
	and.b32  	%r319, %r352, 4;
	setp.eq.s32 	%p154, %r319, 0;
	ld.const.u32 	%r367, [params+108];
	@%p154 bra 	$L__BB0_128;

	setp.eq.s32 	%p155, %r367, 0;
	ld.const.u64 	%rd73, [params+224];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r4, %r3;
	mul.wide.u32 	%rd75, %r321, 8;
	add.s64 	%rd20, %rd74, %rd75;
	@%p155 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs30, %rs31, %rs32, %rs33}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f968, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f969, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f970, %rs32;}

	// end inline asm
	add.f32 	%f971, %f65, %f968;
	add.f32 	%f972, %f66, %f969;
	add.f32 	%f973, %f67, %f970;
	mov.f32 	%f974, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f973;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f972;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f971;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f974;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs26, %rs27, %rs28, %rs29};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f978, 0f3F800000;
	mov.u32 	%r367, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f978;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f67;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f66;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f65;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs34, %rs35, %rs36, %rs37};

$L__BB0_128:
	ld.const.u64 	%rd76, [params+256];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r323, [params+248];
	mad.lo.s32 	%r324, %r323, %r4, %r3;
	mul.wide.u32 	%rd78, %r324, 8;
	add.s64 	%rd21, %rd77, %rd78;
	setp.eq.s32 	%p156, %r367, 0;
	@%p156 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs45, %rs46, %rs47, %rs48}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f979, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f980, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f981, %rs47;}

	// end inline asm
	add.f32 	%f982, %f68, %f979;
	add.f32 	%f983, %f69, %f980;
	add.f32 	%f984, %f70, %f981;
	mov.f32 	%f985, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f984;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f983;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f982;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f985;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs41, %rs42, %rs43, %rs44};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f989, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f989;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f70;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f69;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f68;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs49, %rs50, %rs51, %rs52};

$L__BB0_131:
	mul.f32 	%f990, %f177, 0f3F000000;
	mov.f32 	%f991, 0f3F000000;
	sub.f32 	%f156, %f991, %f990;
	mul.f32 	%f992, %f178, 0f3F000000;
	sub.f32 	%f157, %f991, %f992;
	mul.f32 	%f993, %f179, 0f3F000000;
	sub.f32 	%f158, %f991, %f993;
	ld.const.u64 	%rd79, [params+272];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r325, [params+264];
	mad.lo.s32 	%r326, %r325, %r4, %r3;
	mul.wide.u32 	%rd81, %r326, 8;
	add.s64 	%rd22, %rd80, %rd81;
	@%p156 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs60, %rs61, %rs62, %rs63}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f994, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f995, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs62;}

	// end inline asm
	add.f32 	%f997, %f156, %f994;
	add.f32 	%f998, %f156, %f995;
	add.f32 	%f999, %f156, %f996;
	mov.f32 	%f1000, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f997;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1000;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs56, %rs57, %rs58, %rs59};
	bra.uni 	$L__BB0_134;

$L__BB0_133:
	mov.f32 	%f1004, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f1004;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f156;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f156;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f156;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs64, %rs65, %rs66, %rs67};

$L__BB0_134:
	ld.const.u64 	%rd82, [params+288];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r327, [params+280];
	mad.lo.s32 	%r328, %r327, %r4, %r3;
	mul.wide.u32 	%rd84, %r328, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p156 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs75, %rs76, %rs77, %rs78}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1005, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1006, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1007, %rs77;}

	// end inline asm
	add.f32 	%f1008, %f157, %f1005;
	add.f32 	%f1009, %f157, %f1006;
	add.f32 	%f1010, %f157, %f1007;
	mov.f32 	%f1011, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1010;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1009;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1008;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1011;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs71, %rs72, %rs73, %rs74};
	bra.uni 	$L__BB0_137;

$L__BB0_136:
	mov.f32 	%f1015, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1015;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f157;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs79, %rs80, %rs81, %rs82};

$L__BB0_137:
	ld.const.u64 	%rd85, [params+304];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r329, [params+296];
	mad.lo.s32 	%r330, %r329, %r4, %r3;
	mul.wide.u32 	%rd87, %r330, 8;
	add.s64 	%rd24, %rd86, %rd87;
	@%p156 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs90, %rs91, %rs92, %rs93}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1016, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1017, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1018, %rs92;}

	// end inline asm
	add.f32 	%f1019, %f158, %f1016;
	add.f32 	%f1020, %f158, %f1017;
	add.f32 	%f1021, %f158, %f1018;
	mov.f32 	%f1022, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1021;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1020;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1022;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs86, %rs87, %rs88, %rs89};
	bra.uni 	$L__BB0_160;

$L__BB0_139:
	mov.f32 	%f1026, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f158;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f158;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f158;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs94, %rs95, %rs96, %rs97};

$L__BB0_160:
	ret;

}