//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[1184];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<7>;
	.reg .b16 	%rs<57>;
	.reg .f32 	%f<140>;
	.reg .b32 	%r<41>;
	.reg .b64 	%rd<51>;


	ld.param.u32 	%r6, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f41, [__direct_callable__oxMain_param_1+4];
	ld.param.f32 	%f40, [__direct_callable__oxMain_param_1];
	// begin inline asm
	call (%r7), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r8), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd6, [params+72];
	cvta.to.global.u64 	%rd7, %rd6;
	mul.wide.s32 	%rd8, %r6, 4;
	add.s64 	%rd9, %rd7, %rd8;
	ld.global.u32 	%r3, [%rd9];
	setp.eq.s32 	%p1, %r3, 0;
	@%p1 bra 	$L__BB0_2;

	ld.const.u64 	%rd10, [params+480];
	cvta.to.global.u64 	%rd11, %rd10;
	ld.const.u32 	%r10, [params+472];
	mad.lo.s32 	%r11, %r10, %r8, %r7;
	cvt.u64.u32 	%rd12, %r11;
	add.s64 	%rd13, %rd11, %rd12;
	ld.global.u8 	%r12, [%rd13];
	mov.u32 	%r13, 1;
	shl.b32 	%r14, %r13, %r12;
	and.b32  	%r15, %r14, %r3;
	setp.eq.s32 	%p2, %r15, 0;
	mov.f32 	%f134, 0f00000000;
	mov.f32 	%f135, %f134;
	mov.f32 	%f136, %f134;
	mov.f32 	%f137, %f134;
	mov.f32 	%f138, %f134;
	mov.f32 	%f139, %f134;
	@%p2 bra 	$L__BB0_11;

$L__BB0_2:
	ld.const.u64 	%rd14, [params+24];
	cvta.to.global.u64 	%rd15, %rd14;
	mul.wide.u32 	%rd16, %r6, 12;
	add.s64 	%rd17, %rd15, %rd16;
	ld.global.s32 	%rd1, [%rd17];
	ld.global.s32 	%rd2, [%rd17+4];
	ld.global.s32 	%rd3, [%rd17+8];
	ld.const.u32 	%r4, [params+32];
	setp.gt.u32 	%p3, %r4, %r6;
	@%p3 bra 	$L__BB0_6;
	bra.uni 	$L__BB0_3;

$L__BB0_6:
	mov.f32 	%f139, 0f3F800000;
	sub.f32 	%f92, %f139, %f40;
	sub.f32 	%f130, %f92, %f41;
	bra.uni 	$L__BB0_7;

$L__BB0_3:
	sub.s32 	%r16, %r6, %r4;
	ld.const.u64 	%rd18, [params+48];
	cvta.to.global.u64 	%rd19, %rd18;
	mul.wide.u32 	%rd20, %r16, 4;
	add.s64 	%rd21, %rd19, %rd20;
	ld.const.u64 	%rd22, [params+40];
	cvta.to.global.u64 	%rd23, %rd22;
	shl.b64 	%rd24, %rd1, 3;
	add.s64 	%rd25, %rd23, %rd24;
	ld.global.v2.f32 	{%f48, %f49}, [%rd25];
	shl.b64 	%rd26, %rd2, 3;
	add.s64 	%rd27, %rd23, %rd26;
	ld.global.v2.f32 	{%f52, %f53}, [%rd27];
	shl.b64 	%rd28, %rd3, 3;
	add.s64 	%rd29, %rd23, %rd28;
	ld.global.v2.f32 	{%f56, %f57}, [%rd29];
	mov.f32 	%f60, 0f3F800000;
	sub.f32 	%f61, %f60, %f40;
	sub.f32 	%f130, %f61, %f41;
	mul.f32 	%f62, %f40, %f52;
	mul.f32 	%f63, %f40, %f53;
	fma.rn.f32 	%f64, %f130, %f48, %f62;
	fma.rn.f32 	%f65, %f130, %f49, %f63;
	fma.rn.f32 	%f4, %f41, %f56, %f64;
	fma.rn.f32 	%f5, %f41, %f57, %f65;
	ld.global.u32 	%r5, [%rd21];
	and.b32  	%r17, %r5, -16384;
	setp.eq.s32 	%p4, %r17, 16384;
	@%p4 bra 	$L__BB0_5;
	bra.uni 	$L__BB0_4;

$L__BB0_5:
	add.s32 	%r29, %r5, -16384;
	ld.const.u64 	%rd38, [params+64];
	cvta.to.global.u64 	%rd39, %rd38;
	mul.wide.u32 	%rd40, %r29, 8;
	add.s64 	%rd41, %rd39, %rd40;
	ld.global.u64 	%rd42, [%rd41];
	tex.2d.v4.f32.f32 	{%f76, %f77, %f78, %f79}, [%rd42, {%f4, %f5}];
	cvt.sat.f32.f32 	%f80, %f76;
	mul.f32 	%f81, %f80, 0f437F0000;
	cvt.rzi.s32.f32 	%r30, %f81;
	cvt.sat.f32.f32 	%f82, %f77;
	mul.f32 	%f83, %f82, 0f437F0000;
	cvt.rzi.s32.f32 	%r31, %f83;
	cvt.sat.f32.f32 	%f84, %f78;
	mul.f32 	%f85, %f84, 0f437F0000;
	cvt.rzi.s32.f32 	%r32, %f85;
	shl.b32 	%r33, %r31, 8;
	or.b32  	%r34, %r33, %r30;
	shl.b32 	%r35, %r32, 16;
	or.b32  	%r36, %r34, %r35;
	not.b32 	%r37, %r36;
	cvt.rn.f32.s32 	%f139, %r37;
	bra.uni 	$L__BB0_11;

$L__BB0_4:
	abs.f32 	%f66, %f4;
	cvt.rmi.f32.f32 	%f67, %f66;
	sub.f32 	%f68, %f66, %f67;
	abs.f32 	%f69, %f5;
	cvt.rmi.f32.f32 	%f70, %f69;
	sub.f32 	%f71, %f69, %f70;
	ld.const.u64 	%rd30, [params+56];
	cvta.to.global.u64 	%rd31, %rd30;
	shl.b32 	%r18, %r5, 4;
	cvt.u64.u32 	%rd32, %r18;
	and.b64  	%rd33, %rd32, 1048560;
	add.s64 	%rd34, %rd31, %rd33;
	ld.global.v2.u32 	{%r19, %r20}, [%rd34];
	cvt.rn.f32.u32 	%f72, %r19;
	mul.f32 	%f73, %f68, %f72;
	cvt.rzi.u32.f32 	%r23, %f73;
	cvt.rn.f32.u32 	%f74, %r20;
	mul.f32 	%f75, %f71, %f74;
	cvt.rzi.u32.f32 	%r24, %f75;
	mad.lo.s32 	%r25, %r19, %r24, %r23;
	cvt.u64.u32 	%rd35, %r25;
	ld.global.u64 	%rd36, [%rd34+8];
	add.s64 	%rd37, %rd36, %rd35;
	ld.u8 	%r26, [%rd37];
	shr.u32 	%r27, %r5, 16;
	and.b32  	%r28, %r27, %r26;
	setp.eq.s32 	%p5, %r28, 0;
	selp.f32 	%f139, 0f00000000, 0f3F800000, %p5;

$L__BB0_7:
	cvt.u32.u64 	%r38, %rd1;
	cvt.u32.u64 	%r39, %rd2;
	cvt.u32.u64 	%r40, %rd3;
	ld.const.u64 	%rd43, [params+16];
	cvta.to.global.u64 	%rd44, %rd43;
	mul.wide.s32 	%rd45, %r38, 32;
	add.s64 	%rd46, %rd44, %rd45;
	mul.wide.s32 	%rd47, %r39, 32;
	add.s64 	%rd48, %rd44, %rd47;
	add.s64 	%rd4, %rd48, 12;
	mul.wide.s32 	%rd49, %r40, 32;
	add.s64 	%rd50, %rd44, %rd49;
	add.s64 	%rd5, %rd50, 12;
	ld.global.f32 	%f93, [%rd46+12];
	ld.global.f32 	%f94, [%rd46+16];
	ld.global.f32 	%f95, [%rd46+20];
	ld.global.f32 	%f96, [%rd48+12];
	mul.f32 	%f97, %f40, %f96;
	ld.global.f32 	%f98, [%rd48+16];
	mul.f32 	%f99, %f40, %f98;
	ld.global.f32 	%f100, [%rd48+20];
	mul.f32 	%f101, %f40, %f100;
	fma.rn.f32 	%f102, %f130, %f93, %f97;
	fma.rn.f32 	%f103, %f130, %f94, %f99;
	fma.rn.f32 	%f104, %f130, %f95, %f101;
	ld.global.f32 	%f105, [%rd50+12];
	ld.global.f32 	%f106, [%rd50+16];
	ld.global.f32 	%f107, [%rd50+20];
	fma.rn.f32 	%f108, %f41, %f105, %f102;
	fma.rn.f32 	%f109, %f41, %f106, %f103;
	fma.rn.f32 	%f110, %f41, %f107, %f104;
	mul.f32 	%f111, %f109, %f109;
	fma.rn.f32 	%f112, %f108, %f108, %f111;
	fma.rn.f32 	%f113, %f110, %f110, %f112;
	sqrt.rn.f32 	%f114, %f113;
	rcp.rn.f32 	%f115, %f114;
	mul.f32 	%f134, %f108, %f115;
	mul.f32 	%f135, %f109, %f115;
	mul.f32 	%f136, %f110, %f115;
	ld.global.v2.f32 	{%f137, %f117}, [%rd46+24];
	setp.lt.f32 	%p6, %f117, 0f00000000;
	@%p6 bra 	$L__BB0_9;
	bra.uni 	$L__BB0_8;

$L__BB0_9:
	add.f32 	%f138, %f117, 0f3F800000;
	bra.uni 	$L__BB0_11;

$L__BB0_8:
	ld.global.v2.f32 	{%f118, %f119}, [%rd4+12];
	ld.global.v2.f32 	{%f120, %f121}, [%rd5+12];
	mul.f32 	%f123, %f40, %f118;
	mul.f32 	%f125, %f40, %f119;
	fma.rn.f32 	%f126, %f130, %f137, %f123;
	fma.rn.f32 	%f127, %f130, %f117, %f125;
	fma.rn.f32 	%f137, %f41, %f120, %f126;
	fma.rn.f32 	%f138, %f41, %f121, %f127;

$L__BB0_11:
	st.param.f32 	[func_retval0+0], %f134;
	st.param.f32 	[func_retval0+4], %f135;
	st.param.f32 	[func_retval0+8], %f136;
	st.param.v4.b8 	[func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
	st.param.f32 	[func_retval0+16], %f137;
	st.param.f32 	[func_retval0+20], %f138;
	st.param.f32 	[func_retval0+24], %f139;
	st.param.v4.b8 	[func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}