//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<160>;
	.reg .b16 	%rs<205>;
	.reg .f32 	%f<1207>;
	.reg .b32 	%r<357>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<113>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r55), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r56), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	ld.const.u64 	%rd29, [params+400];
	cvta.to.global.u64 	%rd30, %rd29;
	ld.const.u32 	%r61, [params+392];
	mad.lo.s32 	%r62, %r61, %r56, %r55;
	mul.wide.u32 	%rd31, %r62, 4;
	add.s64 	%rd2, %rd30, %rd31;
	ld.global.v2.u8 	{%rs16, %rs200}, [%rd2];
	or.b16  	%rs18, %rs16, %rs200;
	and.b16  	%rs19, %rs18, 255;
	setp.eq.s16 	%p7, %rs19, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs199, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs199, [%rd2+2];
	setp.eq.s16 	%p8, %rs199, 0;
	mov.f32 	%f1151, 0f00000000;
	mov.u16 	%rs200, 0;
	mov.f32 	%f1152, %f1151;
	mov.f32 	%f1153, %f1151;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f205, %rs16;
	div.rn.f32 	%f206, %f205, 0f437F0000;
	fma.rn.f32 	%f207, %f206, 0f40000000, 0fBF800000;
	and.b16  	%rs22, %rs200, 255;
	cvt.rn.f32.u16 	%f208, %rs22;
	div.rn.f32 	%f209, %f208, 0f437F0000;
	fma.rn.f32 	%f210, %f209, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f211, %rs199;
	div.rn.f32 	%f212, %f211, 0f437F0000;
	fma.rn.f32 	%f213, %f212, 0f40000000, 0fBF800000;
	mul.f32 	%f214, %f210, %f210;
	fma.rn.f32 	%f215, %f207, %f207, %f214;
	fma.rn.f32 	%f216, %f213, %f213, %f215;
	sqrt.rn.f32 	%f217, %f216;
	rcp.rn.f32 	%f218, %f217;
	mul.f32 	%f1153, %f218, %f213;
	mul.f32 	%f1152, %f218, %f210;
	mul.f32 	%f1151, %f207, %f218;

$L__BB0_4:
	ld.const.v2.u32 	{%r63, %r64}, [params];
	add.s32 	%r4, %r63, %r55;
	add.s32 	%r5, %r64, %r56;
	setp.eq.f32 	%p9, %f1151, 0f00000000;
	setp.eq.f32 	%p10, %f1152, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1153, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_134;
	bra.uni 	$L__BB0_5;

$L__BB0_134:
	ld.const.u32 	%r52, [params+104];
	and.b32  	%r316, %r52, 1;
	setp.eq.b32 	%p149, %r316, 1;
	mov.pred 	%p150, 0;
	xor.pred  	%p151, %p149, %p150;
	not.pred 	%p152, %p151;
	@%p152 bra 	$L__BB0_136;

	ld.const.u64 	%rd86, [params+144];
	cvta.to.global.u64 	%rd87, %rd86;
	ld.const.u32 	%r317, [params+136];
	mad.lo.s32 	%r318, %r317, %r5, %r4;
	mul.wide.u32 	%rd88, %r318, 4;
	add.s64 	%rd89, %rd87, %rd88;
	mov.u16 	%rs123, 0;
	st.global.v4.u8 	[%rd89], {%rs123, %rs123, %rs123, %rs123};

$L__BB0_136:
	and.b32  	%r319, %r52, 4;
	setp.eq.s32 	%p153, %r319, 0;
	ld.const.u32 	%r356, [params+108];
	@%p153 bra 	$L__BB0_140;

	setp.eq.s32 	%p154, %r356, 0;
	ld.const.u64 	%rd90, [params+224];
	cvta.to.global.u64 	%rd91, %rd90;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r5, %r4;
	mul.wide.u32 	%rd92, %r321, 8;
	add.s64 	%rd23, %rd91, %rd92;
	@%p154 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs130, %rs131, %rs132, %rs133}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1047, %rs130;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1048, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1049, %rs132;}

	// end inline asm
	add.f32 	%f1050, %f1047, 0f00000000;
	add.f32 	%f1051, %f1048, 0f00000000;
	add.f32 	%f1052, %f1049, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1052;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1051;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1050;}

	// end inline asm
	mov.u16 	%rs134, 0;
	st.global.v4.u16 	[%rd23], {%rs127, %rs128, %rs129, %rs134};
	bra.uni 	$L__BB0_140;

$L__BB0_5:
	ld.const.u64 	%rd32, [params+432];
	cvta.to.global.u64 	%rd33, %rd32;
	ld.const.u32 	%r67, [params+424];
	mad.lo.s32 	%r68, %r67, %r56, %r55;
	mul.wide.u32 	%rd34, %r68, 12;
	add.s64 	%rd35, %rd33, %rd34;
	ld.global.f32 	%f219, [%rd35];
	mul.f32 	%f220, %f219, 0f3456BF95;
	ld.global.f32 	%f221, [%rd35+4];
	mul.f32 	%f222, %f221, 0f3456BF95;
	ld.global.f32 	%f223, [%rd35+8];
	mul.f32 	%f224, %f223, 0f3456BF95;
	abs.f32 	%f225, %f1151;
	div.rn.f32 	%f226, %f220, %f225;
	abs.f32 	%f227, %f1152;
	div.rn.f32 	%f228, %f222, %f227;
	abs.f32 	%f229, %f1153;
	div.rn.f32 	%f230, %f224, %f229;
	abs.f32 	%f231, %f226;
	abs.f32 	%f232, %f228;
	abs.f32 	%f233, %f230;
	mov.f32 	%f234, 0f38D1B717;
	max.f32 	%f235, %f231, %f234;
	max.f32 	%f236, %f232, %f234;
	max.f32 	%f237, %f233, %f234;
	fma.rn.f32 	%f10, %f1151, %f235, %f219;
	fma.rn.f32 	%f11, %f1152, %f236, %f221;
	fma.rn.f32 	%f12, %f1153, %f237, %f223;
	ld.const.u32 	%r6, [params+588];
	setp.gt.f32 	%p14, %f225, %f229;
	neg.f32 	%f238, %f1152;
	selp.f32 	%f239, %f238, 0f00000000, %p14;
	neg.f32 	%f240, %f1153;
	selp.f32 	%f241, %f1151, %f240, %p14;
	selp.f32 	%f242, 0f00000000, %f1152, %p14;
	mul.f32 	%f243, %f241, %f241;
	fma.rn.f32 	%f244, %f239, %f239, %f243;
	fma.rn.f32 	%f245, %f242, %f242, %f244;
	sqrt.rn.f32 	%f246, %f245;
	rcp.rn.f32 	%f247, %f246;
	mul.f32 	%f13, %f239, %f247;
	mul.f32 	%f14, %f241, %f247;
	mul.f32 	%f15, %f242, %f247;
	ld.const.u64 	%rd36, [params+128];
	cvta.to.global.u64 	%rd37, %rd36;
	ld.const.u32 	%r69, [params+120];
	mad.lo.s32 	%r70, %r69, %r56, %r55;
	mul.wide.u32 	%rd38, %r70, 4;
	add.s64 	%rd39, %rd37, %rd38;
	ld.global.u32 	%r347, [%rd39];
	ld.const.u64 	%rd40, [params+464];
	cvta.to.global.u64 	%rd41, %rd40;
	ld.const.u32 	%r71, [params+456];
	mad.lo.s32 	%r72, %r71, %r56, %r55;
	mul.wide.u32 	%rd42, %r72, 4;
	add.s64 	%rd3, %rd41, %rd42;
	ld.global.v2.u8 	{%rs24, %rs203}, [%rd3];
	or.b16  	%rs26, %rs24, %rs203;
	and.b16  	%rs27, %rs26, 255;
	setp.eq.s16 	%p15, %rs27, 0;
	@%p15 bra 	$L__BB0_7;

	ld.global.u8 	%rs201, [%rd3+2];
	bra.uni 	$L__BB0_8;

$L__BB0_7:
	ld.global.u8 	%rs201, [%rd3+2];
	setp.eq.s16 	%p16, %rs201, 0;
	mov.f32 	%f1154, 0f00000000;
	mov.u16 	%rs203, 0;
	mov.u16 	%rs204, %rs203;
	mov.f32 	%f1155, %f1154;
	mov.f32 	%f1156, %f1154;
	@%p16 bra 	$L__BB0_9;

$L__BB0_8:
	mov.u16 	%rs204, %rs203;
	cvt.rn.f32.u16 	%f251, %rs24;
	div.rn.f32 	%f252, %f251, 0f437F0000;
	fma.rn.f32 	%f253, %f252, 0f40000000, 0fBF800000;
	and.b16  	%rs32, %rs204, 255;
	cvt.rn.f32.u16 	%f254, %rs32;
	div.rn.f32 	%f255, %f254, 0f437F0000;
	fma.rn.f32 	%f256, %f255, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f257, %rs201;
	div.rn.f32 	%f258, %f257, 0f437F0000;
	fma.rn.f32 	%f259, %f258, 0f40000000, 0fBF800000;
	mul.f32 	%f260, %f256, %f256;
	fma.rn.f32 	%f261, %f253, %f253, %f260;
	fma.rn.f32 	%f262, %f259, %f259, %f261;
	sqrt.rn.f32 	%f263, %f262;
	rcp.rn.f32 	%f264, %f263;
	mul.f32 	%f1156, %f264, %f259;
	mul.f32 	%f1155, %f264, %f256;
	mul.f32 	%f1154, %f253, %f264;
	mov.u16 	%rs203, %rs201;

$L__BB0_9:
	mul.f32 	%f268, %f1152, %f1156;
	mul.f32 	%f269, %f1153, %f1155;
	sub.f32 	%f270, %f268, %f269;
	mul.f32 	%f271, %f1153, %f1154;
	mul.f32 	%f272, %f1151, %f1156;
	sub.f32 	%f273, %f271, %f272;
	mul.f32 	%f274, %f1151, %f1155;
	mul.f32 	%f275, %f1152, %f1154;
	sub.f32 	%f276, %f274, %f275;
	ld.global.u8 	%rs34, [%rd3+3];
	setp.eq.s16 	%p17, %rs34, 0;
	selp.f32 	%f22, 0fBF800000, 0f3F800000, %p17;
	mul.f32 	%f277, %f270, %f22;
	mul.f32 	%f278, %f273, %f22;
	mul.f32 	%f279, %f276, %f22;
	fma.rn.f32 	%f280, %f277, 0f00000000, %f1154;
	fma.rn.f32 	%f281, %f278, 0f00000000, %f1155;
	fma.rn.f32 	%f282, %f279, 0f00000000, %f1156;
	mul.f32 	%f23, %f1151, 0f00000000;
	add.f32 	%f24, %f23, %f280;
	mul.f32 	%f25, %f1152, 0f00000000;
	add.f32 	%f26, %f25, %f281;
	mul.f32 	%f27, %f1153, 0f00000000;
	add.f32 	%f28, %f27, %f282;
	or.b16  	%rs35, %rs24, %rs204;
	or.b16  	%rs15, %rs35, %rs203;
	and.b16  	%rs36, %rs15, 255;
	setp.eq.s16 	%p18, %rs36, 0;
	mov.f32 	%f1160, 0f00000000;
	mov.f32 	%f1157, %f1160;
	mov.f32 	%f1158, %f1160;
	mov.f32 	%f1159, %f1160;
	@%p18 bra 	$L__BB0_11;

	cvt.rn.f32.u16 	%f283, %rs24;
	div.rn.f32 	%f284, %f283, 0f437F0000;
	fma.rn.f32 	%f285, %f284, 0f40000000, 0fBF800000;
	and.b16  	%rs38, %rs204, 255;
	cvt.rn.f32.u16 	%f286, %rs38;
	div.rn.f32 	%f287, %f286, 0f437F0000;
	fma.rn.f32 	%f288, %f287, 0f40000000, 0fBF800000;
	and.b16  	%rs39, %rs203, 255;
	cvt.rn.f32.u16 	%f289, %rs39;
	div.rn.f32 	%f290, %f289, 0f437F0000;
	fma.rn.f32 	%f291, %f290, 0f40000000, 0fBF800000;
	mul.f32 	%f292, %f288, %f288;
	fma.rn.f32 	%f293, %f285, %f285, %f292;
	fma.rn.f32 	%f294, %f291, %f291, %f293;
	sqrt.rn.f32 	%f295, %f294;
	rcp.rn.f32 	%f296, %f295;
	mul.f32 	%f1159, %f296, %f291;
	mul.f32 	%f1158, %f296, %f288;
	mul.f32 	%f1157, %f285, %f296;

$L__BB0_11:
	mul.f32 	%f300, %f1152, %f1159;
	mul.f32 	%f301, %f1153, %f1158;
	sub.f32 	%f302, %f300, %f301;
	mul.f32 	%f303, %f1153, %f1157;
	mul.f32 	%f304, %f1151, %f1159;
	sub.f32 	%f305, %f303, %f304;
	mul.f32 	%f306, %f1151, %f1158;
	mul.f32 	%f307, %f1152, %f1157;
	sub.f32 	%f308, %f306, %f307;
	mul.f32 	%f309, %f302, %f22;
	mul.f32 	%f310, %f305, %f22;
	mul.f32 	%f311, %f308, %f22;
	fma.rn.f32 	%f312, %f1157, 0f00000000, %f309;
	fma.rn.f32 	%f313, %f1158, 0f00000000, %f310;
	fma.rn.f32 	%f314, %f1159, 0f00000000, %f311;
	add.f32 	%f35, %f23, %f312;
	add.f32 	%f36, %f25, %f313;
	add.f32 	%f37, %f27, %f314;
	mov.f32 	%f1161, %f1160;
	mov.f32 	%f1162, %f1160;
	@%p18 bra 	$L__BB0_13;

	cvt.rn.f32.u16 	%f315, %rs24;
	div.rn.f32 	%f316, %f315, 0f437F0000;
	fma.rn.f32 	%f317, %f316, 0f40000000, 0fBF800000;
	and.b16  	%rs42, %rs204, 255;
	cvt.rn.f32.u16 	%f318, %rs42;
	div.rn.f32 	%f319, %f318, 0f437F0000;
	fma.rn.f32 	%f320, %f319, 0f40000000, 0fBF800000;
	and.b16  	%rs43, %rs203, 255;
	cvt.rn.f32.u16 	%f321, %rs43;
	div.rn.f32 	%f322, %f321, 0f437F0000;
	fma.rn.f32 	%f323, %f322, 0f40000000, 0fBF800000;
	mul.f32 	%f324, %f320, %f320;
	fma.rn.f32 	%f325, %f317, %f317, %f324;
	fma.rn.f32 	%f326, %f323, %f323, %f325;
	sqrt.rn.f32 	%f327, %f326;
	rcp.rn.f32 	%f328, %f327;
	mul.f32 	%f1162, %f328, %f323;
	mul.f32 	%f1161, %f328, %f320;
	mul.f32 	%f1160, %f317, %f328;

$L__BB0_13:
	mul.f32 	%f334, %f1152, %f1162;
	mul.f32 	%f335, %f1153, %f1161;
	sub.f32 	%f336, %f334, %f335;
	mul.f32 	%f337, %f1153, %f1160;
	mul.f32 	%f338, %f1151, %f1162;
	sub.f32 	%f339, %f337, %f338;
	mul.f32 	%f340, %f1151, %f1161;
	mul.f32 	%f341, %f1152, %f1160;
	sub.f32 	%f342, %f340, %f341;
	mul.f32 	%f343, %f336, %f22;
	mul.f32 	%f344, %f339, %f22;
	mul.f32 	%f345, %f342, %f22;
	mov.f32 	%f1179, 0f00000000;
	mul.f32 	%f346, %f343, 0f00000000;
	mul.f32 	%f347, %f344, 0f00000000;
	mul.f32 	%f348, %f345, 0f00000000;
	fma.rn.f32 	%f44, %f1160, 0f00000000, %f346;
	fma.rn.f32 	%f45, %f1161, 0f00000000, %f347;
	fma.rn.f32 	%f46, %f1162, 0f00000000, %f348;
	setp.lt.s32 	%p20, %r3, 1;
	mov.f32 	%f1180, %f1179;
	mov.f32 	%f1181, %f1179;
	mov.f32 	%f1182, %f1179;
	mov.f32 	%f1183, %f1179;
	@%p20 bra 	$L__BB0_44;

	cvt.rn.f32.s32 	%f354, %r3;
	rcp.rn.f32 	%f47, %f354;
	mul.f32 	%f48, %f10, 0f3456BF95;
	mul.f32 	%f49, %f11, 0f3456BF95;
	mul.f32 	%f50, %f12, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f355, %f1153, %f14;
	mul.f32 	%f356, %f1152, %f15;
	sub.f32 	%f51, %f355, %f356;
	mul.f32 	%f357, %f1151, %f15;
	mul.f32 	%f358, %f1153, %f13;
	sub.f32 	%f52, %f357, %f358;
	mul.f32 	%f359, %f1152, %f13;
	mul.f32 	%f360, %f1151, %f14;
	sub.f32 	%f53, %f359, %f360;
	add.f32 	%f54, %f1153, %f46;
	add.f32 	%f55, %f1152, %f45;
	add.f32 	%f56, %f1151, %f44;
	mov.u32 	%r73, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd43, __cudart_i2opi_f;
	abs.f32 	%f423, %f48;
	abs.f32 	%f424, %f49;
	max.f32 	%f425, %f423, %f424;
	abs.f32 	%f426, %f50;
	max.f32 	%f427, %f425, %f426;
	mov.u32 	%r344, %r73;

$L__BB0_15:
	mov.u32 	%r346, %r73;

$L__BB0_16:
	cvt.rn.f32.s32 	%f1121, %r344;
	mad.lo.s32 	%r75, %r347, 1664525, 1013904223;
	and.b32  	%r76, %r75, 16777215;
	cvt.rn.f32.u32 	%f361, %r76;
	fma.rn.f32 	%f362, %f361, 0f33800000, %f1121;
	mul.f32 	%f68, %f47, %f362;
	mad.lo.s32 	%r347, %r75, 1664525, 1013904223;
	and.b32  	%r77, %r347, 16777215;
	cvt.rn.f32.u32 	%f363, %r77;
	cvt.rn.f32.s32 	%f364, %r346;
	fma.rn.f32 	%f365, %f363, 0f33800000, %f364;
	mul.f32 	%f366, %f47, %f365;
	mul.f32 	%f367, %f68, %f68;
	mov.f32 	%f368, 0f3F800000;
	sub.f32 	%f369, %f368, %f367;
	mov.f32 	%f370, 0f00000000;
	max.f32 	%f371, %f370, %f369;
	sqrt.rn.f32 	%f69, %f371;
	mul.f32 	%f70, %f366, 0f40C90FDB;
	mul.f32 	%f372, %f70, 0f3F22F983;
	cvt.rni.s32.f32 	%r351, %f372;
	cvt.rn.f32.s32 	%f373, %r351;
	mov.f32 	%f374, 0fBFC90FDA;
	fma.rn.f32 	%f375, %f373, %f374, %f70;
	mov.f32 	%f376, 0fB3A22168;
	fma.rn.f32 	%f377, %f373, %f376, %f375;
	mov.f32 	%f378, 0fA7C234C5;
	fma.rn.f32 	%f1176, %f373, %f378, %f377;
	abs.f32 	%f72, %f70;
	setp.ltu.f32 	%p21, %f72, 0f47CE4780;
	mov.f32 	%f1173, %f1176;
	@%p21 bra 	$L__BB0_24;

	setp.eq.f32 	%p22, %f72, 0f7F800000;
	@%p22 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_18;

$L__BB0_23:
	mov.f32 	%f381, 0f00000000;
	mul.rn.f32 	%f1173, %f70, %f381;
	mov.u32 	%r351, 0;
	bra.uni 	$L__BB0_24;

$L__BB0_18:
	mov.b32 	%r14, %f70;
	bfe.u32 	%r79, %r14, 23, 8;
	mov.u64 	%rd110, 0;
	mov.u32 	%r348, 0;
	mov.u64 	%rd108, %rd1;
	mov.u64 	%rd109, %rd43;

$L__BB0_19:
	.pragma "nounroll";
	mov.b32 	%r336, %f70;
	shl.b32 	%r335, %r336, 8;
	or.b32  	%r334, %r335, -2147483648;
	ld.global.nc.u32 	%r81, [%rd109];
	mad.wide.u32 	%rd45, %r81, %r334, %rd110;
	shr.u64 	%rd110, %rd45, 32;
	st.local.u32 	[%rd108], %rd45;
	add.s64 	%rd109, %rd109, 4;
	add.s64 	%rd108, %rd108, 4;
	add.s32 	%r348, %r348, 1;
	setp.ne.s32 	%p23, %r348, 6;
	@%p23 bra 	$L__BB0_19;

	add.s32 	%r341, %r79, -128;
	mov.b32 	%r340, %f70;
	bfe.u32 	%r339, %r340, 23, 8;
	add.s32 	%r338, %r339, -128;
	shr.u32 	%r337, %r338, 5;
	st.local.u32 	[%rd5], %rd110;
	mov.u32 	%r82, 4;
	sub.s32 	%r20, %r82, %r337;
	mov.u32 	%r83, 6;
	sub.s32 	%r84, %r83, %r337;
	mul.wide.s32 	%rd46, %r84, 4;
	add.s64 	%rd47, %rd1, %rd46;
	ld.local.u32 	%r349, [%rd47];
	ld.local.u32 	%r350, [%rd47+-4];
	and.b32  	%r23, %r338, 31;
	setp.eq.s32 	%p24, %r23, 0;
	@%p24 bra 	$L__BB0_22;

	mov.u32 	%r85, 32;
	sub.s32 	%r86, %r85, %r23;
	shr.u32 	%r87, %r350, %r86;
	shl.b32 	%r88, %r349, %r23;
	add.s32 	%r349, %r87, %r88;
	mul.wide.s32 	%rd48, %r20, 4;
	add.s64 	%rd49, %rd1, %rd48;
	ld.local.u32 	%r89, [%rd49];
	shr.u32 	%r90, %r89, %r86;
	shl.b32 	%r91, %r350, %r23;
	add.s32 	%r350, %r90, %r91;

$L__BB0_22:
	mov.b32 	%r342, %f70;
	and.b32  	%r92, %r342, -2147483648;
	shr.u32 	%r93, %r350, 30;
	shl.b32 	%r94, %r349, 2;
	or.b32  	%r95, %r93, %r94;
	shr.u32 	%r96, %r95, 31;
	shr.u32 	%r97, %r349, 30;
	add.s32 	%r98, %r96, %r97;
	neg.s32 	%r99, %r98;
	setp.eq.s32 	%p25, %r92, 0;
	selp.b32 	%r351, %r98, %r99, %p25;
	setp.ne.s32 	%p26, %r96, 0;
	xor.b32  	%r100, %r92, -2147483648;
	selp.b32 	%r101, %r100, %r92, %p26;
	selp.b32 	%r102, -1, 0, %p26;
	xor.b32  	%r103, %r95, %r102;
	shl.b32 	%r104, %r350, 2;
	xor.b32  	%r105, %r104, %r102;
	cvt.u64.u32 	%rd50, %r103;
	cvt.u64.u32 	%rd51, %r105;
	bfi.b64 	%rd52, %rd50, %rd51, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd52;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f379, %fd2;
	setp.eq.s32 	%p27, %r101, 0;
	neg.f32 	%f380, %f379;
	selp.f32 	%f1173, %f379, %f380, %p27;

$L__BB0_24:
	add.s32 	%r30, %r351, 1;
	and.b32  	%r31, %r30, 1;
	setp.eq.s32 	%p28, %r31, 0;
	selp.f32 	%f76, %f1173, 0f3F800000, %p28;
	mul.rn.f32 	%f77, %f1173, %f1173;
	mov.f32 	%f1174, 0fB94D4153;
	@%p28 bra 	$L__BB0_26;

	mov.f32 	%f383, 0fBAB607ED;
	mov.f32 	%f384, 0f37CBAC00;
	fma.rn.f32 	%f1174, %f384, %f77, %f383;

$L__BB0_26:
	selp.f32 	%f385, 0f3C0885E4, 0f3D2AAABB, %p28;
	fma.rn.f32 	%f386, %f1174, %f77, %f385;
	selp.f32 	%f387, 0fBE2AAAA8, 0fBEFFFFFF, %p28;
	fma.rn.f32 	%f388, %f386, %f77, %f387;
	mov.f32 	%f389, 0f00000000;
	fma.rn.f32 	%f390, %f77, %f76, %f389;
	fma.rn.f32 	%f1175, %f388, %f390, %f76;
	and.b32  	%r107, %r30, 2;
	setp.eq.s32 	%p30, %r107, 0;
	@%p30 bra 	$L__BB0_28;

	mov.f32 	%f392, 0fBF800000;
	fma.rn.f32 	%f1175, %f1175, %f392, %f389;

$L__BB0_28:
	mul.f32 	%f1122, %f70, 0f3F22F983;
	cvt.rni.s32.f32 	%r354, %f1122;
	setp.ltu.f32 	%p159, %f72, 0f47CE4780;
	@%p159 bra 	$L__BB0_36;

	setp.eq.f32 	%p32, %f72, 0f7F800000;
	@%p32 bra 	$L__BB0_35;
	bra.uni 	$L__BB0_30;

$L__BB0_35:
	mov.f32 	%f395, 0f00000000;
	mul.rn.f32 	%f1176, %f70, %f395;
	mov.u32 	%r354, 0;
	bra.uni 	$L__BB0_36;

$L__BB0_30:
	mov.b32 	%r32, %f70;
	bfe.u32 	%r108, %r32, 23, 8;
	add.s32 	%r33, %r108, -128;
	shl.b32 	%r109, %r32, 8;
	or.b32  	%r34, %r109, -2147483648;
	shr.u32 	%r35, %r33, 5;
	mov.u64 	%rd111, 0;
	mov.u64 	%rd112, %rd111;

$L__BB0_31:
	.pragma "nounroll";
	shl.b64 	%rd55, %rd111, 2;
	mov.u64 	%rd56, __cudart_i2opi_f;
	add.s64 	%rd57, %rd56, %rd55;
	ld.global.nc.u32 	%r110, [%rd57];
	mad.wide.u32 	%rd58, %r110, %r34, %rd112;
	shr.u64 	%rd112, %rd58, 32;
	add.s64 	%rd59, %rd1, %rd55;
	st.local.u32 	[%rd59], %rd58;
	cvt.u32.u64 	%r111, %rd111;
	add.s32 	%r112, %r111, 1;
	cvt.s64.s32 	%rd111, %r112;
	setp.ne.s32 	%p33, %r112, 6;
	@%p33 bra 	$L__BB0_31;

	st.local.u32 	[%rd5], %rd112;
	mov.u32 	%r113, 4;
	sub.s32 	%r36, %r113, %r35;
	mov.u32 	%r114, 6;
	sub.s32 	%r115, %r114, %r35;
	mul.wide.s32 	%rd60, %r115, 4;
	add.s64 	%rd61, %rd1, %rd60;
	ld.local.u32 	%r352, [%rd61];
	ld.local.u32 	%r353, [%rd61+-4];
	and.b32  	%r39, %r33, 31;
	setp.eq.s32 	%p34, %r39, 0;
	@%p34 bra 	$L__BB0_34;

	mov.u32 	%r116, 32;
	sub.s32 	%r117, %r116, %r39;
	shr.u32 	%r118, %r353, %r117;
	shl.b32 	%r119, %r352, %r39;
	add.s32 	%r352, %r118, %r119;
	mul.wide.s32 	%rd62, %r36, 4;
	add.s64 	%rd63, %rd1, %rd62;
	ld.local.u32 	%r120, [%rd63];
	shr.u32 	%r121, %r120, %r117;
	shl.b32 	%r122, %r353, %r39;
	add.s32 	%r353, %r121, %r122;

$L__BB0_34:
	and.b32  	%r123, %r32, -2147483648;
	shr.u32 	%r124, %r353, 30;
	shl.b32 	%r125, %r352, 2;
	or.b32  	%r126, %r124, %r125;
	shr.u32 	%r127, %r126, 31;
	shr.u32 	%r128, %r352, 30;
	add.s32 	%r129, %r127, %r128;
	neg.s32 	%r130, %r129;
	setp.eq.s32 	%p35, %r123, 0;
	selp.b32 	%r354, %r129, %r130, %p35;
	setp.ne.s32 	%p36, %r127, 0;
	xor.b32  	%r131, %r123, -2147483648;
	selp.b32 	%r132, %r131, %r123, %p36;
	selp.b32 	%r133, -1, 0, %p36;
	xor.b32  	%r134, %r126, %r133;
	shl.b32 	%r135, %r353, 2;
	xor.b32  	%r136, %r135, %r133;
	cvt.u64.u32 	%rd64, %r134;
	cvt.u64.u32 	%rd65, %r136;
	bfi.b64 	%rd66, %rd64, %rd65, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd66;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f393, %fd4;
	setp.eq.s32 	%p37, %r132, 0;
	neg.f32 	%f394, %f393;
	selp.f32 	%f1176, %f393, %f394, %p37;

$L__BB0_36:
	mul.f32 	%f86, %f69, %f1175;
	and.b32  	%r46, %r354, 1;
	setp.eq.s32 	%p38, %r46, 0;
	selp.f32 	%f87, %f1176, 0f3F800000, %p38;
	mul.rn.f32 	%f88, %f1176, %f1176;
	mov.f32 	%f1177, 0fB94D4153;
	@%p38 bra 	$L__BB0_38;

	mov.f32 	%f397, 0fBAB607ED;
	mov.f32 	%f398, 0f37CBAC00;
	fma.rn.f32 	%f1177, %f398, %f88, %f397;

$L__BB0_38:
	selp.f32 	%f399, 0f3C0885E4, 0f3D2AAABB, %p38;
	fma.rn.f32 	%f400, %f1177, %f88, %f399;
	selp.f32 	%f401, 0fBE2AAAA8, 0fBEFFFFFF, %p38;
	fma.rn.f32 	%f402, %f400, %f88, %f401;
	mov.f32 	%f403, 0f00000000;
	fma.rn.f32 	%f404, %f88, %f87, %f403;
	fma.rn.f32 	%f1178, %f402, %f404, %f87;
	and.b32  	%r138, %r354, 2;
	setp.eq.s32 	%p40, %r138, 0;
	@%p40 bra 	$L__BB0_40;

	mov.f32 	%f406, 0fBF800000;
	fma.rn.f32 	%f1178, %f1178, %f406, %f403;

$L__BB0_40:
	mul.f32 	%f407, %f69, %f1178;
	mul.f32 	%f408, %f13, %f407;
	mul.f32 	%f409, %f14, %f407;
	mul.f32 	%f410, %f15, %f407;
	fma.rn.f32 	%f411, %f51, %f86, %f408;
	fma.rn.f32 	%f412, %f52, %f86, %f409;
	fma.rn.f32 	%f413, %f53, %f86, %f410;
	fma.rn.f32 	%f94, %f1151, %f68, %f411;
	fma.rn.f32 	%f95, %f1152, %f68, %f412;
	fma.rn.f32 	%f96, %f1153, %f68, %f413;
	setp.leu.f32 	%p41, %f95, 0f00000000;
	setp.ne.s32 	%p42, %r6, 0;
	and.pred  	%p43, %p42, %p41;
	@%p43 bra 	$L__BB0_42;

	mov.f32 	%f428, 0f38D1B717;
	max.f32 	%f420, %f427, %f428;
	mov.f32 	%f421, 0f6C4ECB8F;
	mov.f32 	%f422, 0f00000000;
	mov.u32 	%r175, 2;
	mov.u32 	%r177, 1;
	mov.u32 	%r178, 1065353216;
	mov.u32 	%r209, 0;
	// begin inline asm
	call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd4,%f10,%f11,%f12,%f94,%f95,%f96,%f420,%f421,%f422,%r177,%r209,%r177,%r175,%r177,%r177,%r178,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
	// end inline asm
	mov.b32 	%f429, %r139;
	mul.f32 	%f430, %f1152, %f95;
	fma.rn.f32 	%f431, %f1151, %f94, %f430;
	fma.rn.f32 	%f432, %f1153, %f96, %f431;
	mul.f32 	%f433, %f432, 0f40800000;
	cvt.sat.f32.f32 	%f434, %f433;
	mul.f32 	%f435, %f434, %f429;
	mul.f32 	%f436, %f26, %f95;
	fma.rn.f32 	%f437, %f24, %f94, %f436;
	fma.rn.f32 	%f438, %f28, %f96, %f437;
	cvt.sat.f32.f32 	%f439, %f438;
	fma.rn.f32 	%f1181, %f439, %f435, %f1181;
	mul.f32 	%f440, %f36, %f95;
	fma.rn.f32 	%f441, %f35, %f94, %f440;
	fma.rn.f32 	%f442, %f37, %f96, %f441;
	cvt.sat.f32.f32 	%f443, %f442;
	fma.rn.f32 	%f1182, %f443, %f435, %f1182;
	mul.f32 	%f444, %f55, %f95;
	fma.rn.f32 	%f445, %f56, %f94, %f444;
	fma.rn.f32 	%f446, %f54, %f96, %f445;
	cvt.sat.f32.f32 	%f447, %f446;
	fma.rn.f32 	%f1183, %f435, %f447, %f1183;
	add.f32 	%f1179, %f1179, %f435;
	cvt.sat.f32.f32 	%f448, %f432;
	fma.rn.f32 	%f1180, %f448, %f429, %f1180;

$L__BB0_42:
	add.s32 	%r346, %r346, 1;
	setp.lt.s32 	%p44, %r346, %r3;
	@%p44 bra 	$L__BB0_16;

	add.s32 	%r344, %r344, 1;
	setp.lt.s32 	%p45, %r344, %r3;
	@%p45 bra 	$L__BB0_15;

$L__BB0_44:
	mul.lo.s32 	%r210, %r3, %r3;
	cvt.rn.f32.s32 	%f449, %r210;
	div.rn.f32 	%f450, %f1180, %f449;
	div.rn.f32 	%f112, %f1179, %f449;
	div.rn.f32 	%f113, %f1181, %f449;
	div.rn.f32 	%f114, %f1182, %f449;
	div.rn.f32 	%f115, %f1183, %f449;
	add.f32 	%f451, %f450, %f450;
	ld.const.v4.f32 	{%f452, %f453, %f454, %f455}, [params+576];
	mul.f32 	%f119, %f451, %f452;
	mul.f32 	%f120, %f451, %f453;
	mul.f32 	%f121, %f451, %f454;
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r211, %r49, 1;
	setp.eq.b32 	%p46, %r211, 1;
	mov.pred 	%p47, 0;
	xor.pred  	%p48, %p46, %p47;
	not.pred 	%p49, %p48;
	@%p49 bra 	$L__BB0_118;

	mov.f32 	%f460, 0f3EE66666;
	abs.f32 	%f123, %f119;
	setp.lt.f32 	%p50, %f123, 0f00800000;
	mul.f32 	%f462, %f123, 0f4B800000;
	selp.f32 	%f463, %f462, %f123, %p50;
	selp.f32 	%f464, 0fC3170000, 0fC2FE0000, %p50;
	mov.b32 	%r212, %f463;
	and.b32  	%r213, %r212, 8388607;
	or.b32  	%r214, %r213, 1065353216;
	mov.b32 	%f465, %r214;
	shr.u32 	%r215, %r212, 23;
	cvt.rn.f32.u32 	%f466, %r215;
	add.f32 	%f467, %f464, %f466;
	setp.gt.f32 	%p51, %f465, 0f3FB504F3;
	mul.f32 	%f468, %f465, 0f3F000000;
	add.f32 	%f469, %f467, 0f3F800000;
	selp.f32 	%f470, %f469, %f467, %p51;
	selp.f32 	%f471, %f468, %f465, %p51;
	add.f32 	%f472, %f471, 0fBF800000;
	add.f32 	%f473, %f471, 0f3F800000;
	rcp.approx.ftz.f32 	%f474, %f473;
	add.f32 	%f475, %f472, %f472;
	mul.f32 	%f476, %f475, %f474;
	mul.f32 	%f477, %f476, %f476;
	mov.f32 	%f478, 0f3C4CAF63;
	mov.f32 	%f479, 0f3B18F0FE;
	fma.rn.f32 	%f480, %f479, %f477, %f478;
	mov.f32 	%f481, 0f3DAAAABD;
	fma.rn.f32 	%f482, %f480, %f477, %f481;
	mul.rn.f32 	%f483, %f482, %f477;
	mul.rn.f32 	%f484, %f483, %f476;
	sub.f32 	%f485, %f472, %f476;
	add.f32 	%f486, %f485, %f485;
	neg.f32 	%f487, %f476;
	fma.rn.f32 	%f488, %f487, %f472, %f486;
	mul.rn.f32 	%f489, %f474, %f488;
	add.f32 	%f490, %f484, %f476;
	sub.f32 	%f491, %f476, %f490;
	add.f32 	%f492, %f484, %f491;
	add.f32 	%f493, %f489, %f492;
	add.f32 	%f494, %f490, %f493;
	sub.f32 	%f495, %f490, %f494;
	add.f32 	%f496, %f493, %f495;
	mov.f32 	%f497, 0f3F317200;
	mul.rn.f32 	%f498, %f470, %f497;
	mov.f32 	%f499, 0f35BFBE8E;
	mul.rn.f32 	%f500, %f470, %f499;
	add.f32 	%f501, %f498, %f494;
	sub.f32 	%f502, %f498, %f501;
	add.f32 	%f503, %f494, %f502;
	add.f32 	%f504, %f496, %f503;
	add.f32 	%f505, %f500, %f504;
	add.f32 	%f506, %f501, %f505;
	sub.f32 	%f507, %f501, %f506;
	add.f32 	%f508, %f505, %f507;
	mul.rn.f32 	%f509, %f460, %f506;
	neg.f32 	%f510, %f509;
	fma.rn.f32 	%f511, %f460, %f506, %f510;
	fma.rn.f32 	%f512, %f460, %f508, %f511;
	mov.f32 	%f513, 0f00000000;
	fma.rn.f32 	%f514, %f513, %f506, %f512;
	add.rn.f32 	%f515, %f509, %f514;
	neg.f32 	%f516, %f515;
	add.rn.f32 	%f517, %f509, %f516;
	add.rn.f32 	%f518, %f517, %f514;
	mov.b32 	%r216, %f515;
	setp.eq.s32 	%p52, %r216, 1118925336;
	add.s32 	%r217, %r216, -1;
	mov.b32 	%f519, %r217;
	add.f32 	%f520, %f518, 0f37000000;
	selp.f32 	%f124, %f520, %f518, %p52;
	selp.f32 	%f521, %f519, %f515, %p52;
	mov.f32 	%f522, 0f3FB8AA3B;
	mul.rn.f32 	%f523, %f521, %f522;
	cvt.rzi.f32.f32 	%f524, %f523;
	abs.f32 	%f525, %f524;
	setp.gt.f32 	%p53, %f525, 0f42FC0000;
	mov.b32 	%r218, %f524;
	and.b32  	%r219, %r218, -2147483648;
	or.b32  	%r220, %r219, 1123811328;
	mov.b32 	%f526, %r220;
	selp.f32 	%f527, %f526, %f524, %p53;
	mov.f32 	%f528, 0fBF317218;
	fma.rn.f32 	%f529, %f527, %f528, %f521;
	mov.f32 	%f530, 0f3102E308;
	fma.rn.f32 	%f531, %f527, %f530, %f529;
	mul.f32 	%f532, %f531, 0f3FB8AA3B;
	add.f32 	%f533, %f527, 0f4B40007F;
	mov.b32 	%r221, %f533;
	shl.b32 	%r222, %r221, 23;
	mov.b32 	%f534, %r222;
	ex2.approx.ftz.f32 	%f535, %f532;
	mul.f32 	%f125, %f535, %f534;
	setp.eq.f32 	%p54, %f125, 0f7F800000;
	mov.f32 	%f1189, 0f7F800000;
	@%p54 bra 	$L__BB0_47;

	fma.rn.f32 	%f1189, %f125, %f124, %f125;

$L__BB0_47:
	mov.f32 	%f1128, 0f3E666666;
	cvt.rzi.f32.f32 	%f1127, %f1128;
	add.f32 	%f1126, %f1127, %f1127;
	mov.f32 	%f1125, 0f3EE66666;
	sub.f32 	%f1124, %f1125, %f1126;
	abs.f32 	%f1123, %f1124;
	setp.lt.f32 	%p55, %f119, 0f00000000;
	setp.eq.f32 	%p56, %f1123, 0f3F800000;
	and.pred  	%p1, %p55, %p56;
	setp.eq.f32 	%p57, %f119, 0f00000000;
	@%p57 bra 	$L__BB0_51;
	bra.uni 	$L__BB0_48;

$L__BB0_51:
	add.f32 	%f540, %f119, %f119;
	selp.f32 	%f1191, %f540, 0f00000000, %p56;
	bra.uni 	$L__BB0_52;

$L__BB0_139:
	mov.f32 	%f1055, 0f00000000;
	mov.u32 	%r356, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1055;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1055;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1055;}

	// end inline asm
	mov.u16 	%rs138, 0;
	st.global.v4.u16 	[%rd23], {%rs135, %rs136, %rs137, %rs138};

$L__BB0_140:
	ld.const.u64 	%rd93, [params+256];
	cvta.to.global.u64 	%rd94, %rd93;
	ld.const.u32 	%r323, [params+248];
	mad.lo.s32 	%r324, %r323, %r5, %r4;
	mul.wide.u32 	%rd95, %r324, 8;
	add.s64 	%rd24, %rd94, %rd95;
	setp.eq.s32 	%p155, %r356, 0;
	@%p155 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs145, %rs146, %rs147, %rs148}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1056, %rs145;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1057, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1058, %rs147;}

	// end inline asm
	add.f32 	%f1059, %f1056, 0f00000000;
	add.f32 	%f1060, %f1057, 0f00000000;
	add.f32 	%f1061, %f1058, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1061;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1060;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1059;}

	// end inline asm
	mov.u16 	%rs149, 0;
	st.global.v4.u16 	[%rd24], {%rs142, %rs143, %rs144, %rs149};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1064, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1064;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1064;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1064;}

	// end inline asm
	mov.u16 	%rs153, 0;
	st.global.v4.u16 	[%rd24], {%rs150, %rs151, %rs152, %rs153};

$L__BB0_143:
	ld.const.u64 	%rd96, [params+272];
	cvta.to.global.u64 	%rd97, %rd96;
	ld.const.u32 	%r325, [params+264];
	mad.lo.s32 	%r326, %r325, %r5, %r4;
	mul.wide.u32 	%rd98, %r326, 8;
	add.s64 	%rd25, %rd97, %rd98;
	@%p155 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs160, %rs161, %rs162, %rs163}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1065, %rs160;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1066, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1067, %rs162;}

	// end inline asm
	add.f32 	%f1068, %f1065, 0f00000000;
	add.f32 	%f1069, %f1066, 0f00000000;
	add.f32 	%f1070, %f1067, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1070;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1069;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1068;}

	// end inline asm
	mov.u16 	%rs164, 0;
	st.global.v4.u16 	[%rd25], {%rs157, %rs158, %rs159, %rs164};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1073, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1073;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1073;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1073;}

	// end inline asm
	mov.u16 	%rs168, 0;
	st.global.v4.u16 	[%rd25], {%rs165, %rs166, %rs167, %rs168};

$L__BB0_146:
	ld.const.u64 	%rd99, [params+288];
	cvta.to.global.u64 	%rd100, %rd99;
	ld.const.u32 	%r327, [params+280];
	mad.lo.s32 	%r328, %r327, %r5, %r4;
	mul.wide.u32 	%rd101, %r328, 8;
	add.s64 	%rd26, %rd100, %rd101;
	@%p155 bra 	$L__BB0_148;

	ld.global.v4.u16 	{%rs175, %rs176, %rs177, %rs178}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1074, %rs175;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1075, %rs176;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1076, %rs177;}

	// end inline asm
	add.f32 	%f1077, %f1074, 0f00000000;
	add.f32 	%f1078, %f1075, 0f00000000;
	add.f32 	%f1079, %f1076, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1079;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1078;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1077;}

	// end inline asm
	mov.u16 	%rs179, 0;
	st.global.v4.u16 	[%rd26], {%rs172, %rs173, %rs174, %rs179};
	bra.uni 	$L__BB0_149;

$L__BB0_148:
	mov.f32 	%f1082, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs182, %f1082;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs181, %f1082;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs180, %f1082;}

	// end inline asm
	mov.u16 	%rs183, 0;
	st.global.v4.u16 	[%rd26], {%rs180, %rs181, %rs182, %rs183};

$L__BB0_149:
	ld.const.u64 	%rd102, [params+304];
	cvta.to.global.u64 	%rd103, %rd102;
	ld.const.u32 	%r329, [params+296];
	mad.lo.s32 	%r330, %r329, %r5, %r4;
	mul.wide.u32 	%rd104, %r330, 8;
	add.s64 	%rd27, %rd103, %rd104;
	@%p155 bra 	$L__BB0_151;

	ld.global.v4.u16 	{%rs190, %rs191, %rs192, %rs193}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1083, %rs190;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1084, %rs191;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1085, %rs192;}

	// end inline asm
	add.f32 	%f1086, %f1083, 0f00000000;
	add.f32 	%f1087, %f1084, 0f00000000;
	add.f32 	%f1088, %f1085, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs189, %f1088;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs188, %f1087;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs187, %f1086;}

	// end inline asm
	mov.u16 	%rs194, 0;
	st.global.v4.u16 	[%rd27], {%rs187, %rs188, %rs189, %rs194};
	bra.uni 	$L__BB0_152;

$L__BB0_151:
	mov.f32 	%f1091, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs197, %f1091;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs196, %f1091;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs195, %f1091;}

	// end inline asm
	mov.u16 	%rs198, 0;
	st.global.v4.u16 	[%rd27], {%rs195, %rs196, %rs197, %rs198};
	bra.uni 	$L__BB0_152;

$L__BB0_48:
	mov.b32 	%r223, %f1189;
	xor.b32  	%r224, %r223, -2147483648;
	mov.b32 	%f536, %r224;
	selp.f32 	%f1191, %f536, %f1189, %p1;
	setp.geu.f32 	%p58, %f119, 0f00000000;
	@%p58 bra 	$L__BB0_52;

	mov.f32 	%f537, 0f3EE66666;
	cvt.rzi.f32.f32 	%f538, %f537;
	setp.eq.f32 	%p59, %f538, 0f3EE66666;
	@%p59 bra 	$L__BB0_52;

	mov.f32 	%f1191, 0f7FFFFFFF;

$L__BB0_52:
	add.f32 	%f541, %f123, 0f3EE66666;
	mov.b32 	%r225, %f541;
	setp.lt.s32 	%p61, %r225, 2139095040;
	@%p61 bra 	$L__BB0_57;

	setp.gtu.f32 	%p62, %f123, 0f7F800000;
	@%p62 bra 	$L__BB0_56;
	bra.uni 	$L__BB0_54;

$L__BB0_56:
	add.f32 	%f1191, %f119, 0f3EE66666;
	bra.uni 	$L__BB0_57;

$L__BB0_54:
	setp.neu.f32 	%p63, %f123, 0f7F800000;
	@%p63 bra 	$L__BB0_57;

	selp.f32 	%f1191, 0fFF800000, 0f7F800000, %p1;

$L__BB0_57:
	setp.eq.f32 	%p64, %f119, 0f3F800000;
	selp.f32 	%f134, 0f3F800000, %f1191, %p64;
	abs.f32 	%f135, %f120;
	setp.lt.f32 	%p65, %f135, 0f00800000;
	mul.f32 	%f543, %f135, 0f4B800000;
	selp.f32 	%f544, %f543, %f135, %p65;
	selp.f32 	%f545, 0fC3170000, 0fC2FE0000, %p65;
	mov.b32 	%r226, %f544;
	and.b32  	%r227, %r226, 8388607;
	or.b32  	%r228, %r227, 1065353216;
	mov.b32 	%f546, %r228;
	shr.u32 	%r229, %r226, 23;
	cvt.rn.f32.u32 	%f547, %r229;
	add.f32 	%f548, %f545, %f547;
	setp.gt.f32 	%p66, %f546, 0f3FB504F3;
	mul.f32 	%f549, %f546, 0f3F000000;
	add.f32 	%f550, %f548, 0f3F800000;
	selp.f32 	%f551, %f550, %f548, %p66;
	selp.f32 	%f552, %f549, %f546, %p66;
	add.f32 	%f553, %f552, 0fBF800000;
	add.f32 	%f554, %f552, 0f3F800000;
	rcp.approx.ftz.f32 	%f555, %f554;
	add.f32 	%f556, %f553, %f553;
	mul.f32 	%f557, %f556, %f555;
	mul.f32 	%f558, %f557, %f557;
	mov.f32 	%f559, 0f3C4CAF63;
	mov.f32 	%f560, 0f3B18F0FE;
	fma.rn.f32 	%f561, %f560, %f558, %f559;
	mov.f32 	%f562, 0f3DAAAABD;
	fma.rn.f32 	%f563, %f561, %f558, %f562;
	mul.rn.f32 	%f564, %f563, %f558;
	mul.rn.f32 	%f565, %f564, %f557;
	sub.f32 	%f566, %f553, %f557;
	add.f32 	%f567, %f566, %f566;
	neg.f32 	%f568, %f557;
	fma.rn.f32 	%f569, %f568, %f553, %f567;
	mul.rn.f32 	%f570, %f555, %f569;
	add.f32 	%f571, %f565, %f557;
	sub.f32 	%f572, %f557, %f571;
	add.f32 	%f573, %f565, %f572;
	add.f32 	%f574, %f570, %f573;
	add.f32 	%f575, %f571, %f574;
	sub.f32 	%f576, %f571, %f575;
	add.f32 	%f577, %f574, %f576;
	mov.f32 	%f578, 0f3F317200;
	mul.rn.f32 	%f579, %f551, %f578;
	mov.f32 	%f580, 0f35BFBE8E;
	mul.rn.f32 	%f581, %f551, %f580;
	add.f32 	%f582, %f579, %f575;
	sub.f32 	%f583, %f579, %f582;
	add.f32 	%f584, %f575, %f583;
	add.f32 	%f585, %f577, %f584;
	add.f32 	%f586, %f581, %f585;
	add.f32 	%f587, %f582, %f586;
	sub.f32 	%f588, %f582, %f587;
	add.f32 	%f589, %f586, %f588;
	mov.f32 	%f590, 0f3EE66666;
	mul.rn.f32 	%f591, %f590, %f587;
	neg.f32 	%f592, %f591;
	fma.rn.f32 	%f593, %f590, %f587, %f592;
	fma.rn.f32 	%f594, %f590, %f589, %f593;
	mov.f32 	%f595, 0f00000000;
	fma.rn.f32 	%f596, %f595, %f587, %f594;
	add.rn.f32 	%f597, %f591, %f596;
	neg.f32 	%f598, %f597;
	add.rn.f32 	%f599, %f591, %f598;
	add.rn.f32 	%f600, %f599, %f596;
	mov.b32 	%r230, %f597;
	setp.eq.s32 	%p67, %r230, 1118925336;
	add.s32 	%r231, %r230, -1;
	mov.b32 	%f601, %r231;
	add.f32 	%f602, %f600, 0f37000000;
	selp.f32 	%f136, %f602, %f600, %p67;
	selp.f32 	%f603, %f601, %f597, %p67;
	mov.f32 	%f604, 0f3FB8AA3B;
	mul.rn.f32 	%f605, %f603, %f604;
	cvt.rzi.f32.f32 	%f606, %f605;
	abs.f32 	%f607, %f606;
	setp.gt.f32 	%p68, %f607, 0f42FC0000;
	mov.b32 	%r232, %f606;
	and.b32  	%r233, %r232, -2147483648;
	or.b32  	%r234, %r233, 1123811328;
	mov.b32 	%f608, %r234;
	selp.f32 	%f609, %f608, %f606, %p68;
	mov.f32 	%f610, 0fBF317218;
	fma.rn.f32 	%f611, %f609, %f610, %f603;
	mov.f32 	%f612, 0f3102E308;
	fma.rn.f32 	%f613, %f609, %f612, %f611;
	mul.f32 	%f614, %f613, 0f3FB8AA3B;
	add.f32 	%f615, %f609, 0f4B40007F;
	mov.b32 	%r235, %f615;
	shl.b32 	%r236, %r235, 23;
	mov.b32 	%f616, %r236;
	ex2.approx.ftz.f32 	%f617, %f614;
	mul.f32 	%f137, %f617, %f616;
	setp.eq.f32 	%p69, %f137, 0f7F800000;
	mov.f32 	%f1192, 0f7F800000;
	@%p69 bra 	$L__BB0_59;

	fma.rn.f32 	%f1192, %f137, %f136, %f137;

$L__BB0_59:
	setp.lt.f32 	%p70, %f120, 0f00000000;
	and.pred  	%p2, %p70, %p56;
	setp.eq.f32 	%p72, %f120, 0f00000000;
	@%p72 bra 	$L__BB0_63;
	bra.uni 	$L__BB0_60;

$L__BB0_63:
	add.f32 	%f622, %f120, %f120;
	selp.f32 	%f1194, %f622, 0f00000000, %p56;
	bra.uni 	$L__BB0_64;

$L__BB0_60:
	mov.b32 	%r237, %f1192;
	xor.b32  	%r238, %r237, -2147483648;
	mov.b32 	%f618, %r238;
	selp.f32 	%f1194, %f618, %f1192, %p2;
	setp.geu.f32 	%p73, %f120, 0f00000000;
	@%p73 bra 	$L__BB0_64;

	mov.f32 	%f619, 0f3EE66666;
	cvt.rzi.f32.f32 	%f620, %f619;
	setp.eq.f32 	%p74, %f620, 0f3EE66666;
	@%p74 bra 	$L__BB0_64;

	mov.f32 	%f1194, 0f7FFFFFFF;

$L__BB0_64:
	add.f32 	%f623, %f135, 0f3EE66666;
	mov.b32 	%r239, %f623;
	setp.lt.s32 	%p76, %r239, 2139095040;
	@%p76 bra 	$L__BB0_69;

	setp.gtu.f32 	%p77, %f135, 0f7F800000;
	@%p77 bra 	$L__BB0_68;
	bra.uni 	$L__BB0_66;

$L__BB0_68:
	add.f32 	%f1194, %f120, 0f3EE66666;
	bra.uni 	$L__BB0_69;

$L__BB0_66:
	setp.neu.f32 	%p78, %f135, 0f7F800000;
	@%p78 bra 	$L__BB0_69;

	selp.f32 	%f1194, 0fFF800000, 0f7F800000, %p2;

$L__BB0_69:
	setp.eq.f32 	%p79, %f120, 0f3F800000;
	selp.f32 	%f146, 0f3F800000, %f1194, %p79;
	abs.f32 	%f147, %f121;
	setp.lt.f32 	%p80, %f147, 0f00800000;
	mul.f32 	%f625, %f147, 0f4B800000;
	selp.f32 	%f626, %f625, %f147, %p80;
	selp.f32 	%f627, 0fC3170000, 0fC2FE0000, %p80;
	mov.b32 	%r240, %f626;
	and.b32  	%r241, %r240, 8388607;
	or.b32  	%r242, %r241, 1065353216;
	mov.b32 	%f628, %r242;
	shr.u32 	%r243, %r240, 23;
	cvt.rn.f32.u32 	%f629, %r243;
	add.f32 	%f630, %f627, %f629;
	setp.gt.f32 	%p81, %f628, 0f3FB504F3;
	mul.f32 	%f631, %f628, 0f3F000000;
	add.f32 	%f632, %f630, 0f3F800000;
	selp.f32 	%f633, %f632, %f630, %p81;
	selp.f32 	%f634, %f631, %f628, %p81;
	add.f32 	%f635, %f634, 0fBF800000;
	add.f32 	%f636, %f634, 0f3F800000;
	rcp.approx.ftz.f32 	%f637, %f636;
	add.f32 	%f638, %f635, %f635;
	mul.f32 	%f639, %f638, %f637;
	mul.f32 	%f640, %f639, %f639;
	mov.f32 	%f641, 0f3C4CAF63;
	mov.f32 	%f642, 0f3B18F0FE;
	fma.rn.f32 	%f643, %f642, %f640, %f641;
	mov.f32 	%f644, 0f3DAAAABD;
	fma.rn.f32 	%f645, %f643, %f640, %f644;
	mul.rn.f32 	%f646, %f645, %f640;
	mul.rn.f32 	%f647, %f646, %f639;
	sub.f32 	%f648, %f635, %f639;
	add.f32 	%f649, %f648, %f648;
	neg.f32 	%f650, %f639;
	fma.rn.f32 	%f651, %f650, %f635, %f649;
	mul.rn.f32 	%f652, %f637, %f651;
	add.f32 	%f653, %f647, %f639;
	sub.f32 	%f654, %f639, %f653;
	add.f32 	%f655, %f647, %f654;
	add.f32 	%f656, %f652, %f655;
	add.f32 	%f657, %f653, %f656;
	sub.f32 	%f658, %f653, %f657;
	add.f32 	%f659, %f656, %f658;
	mov.f32 	%f660, 0f3F317200;
	mul.rn.f32 	%f661, %f633, %f660;
	mov.f32 	%f662, 0f35BFBE8E;
	mul.rn.f32 	%f663, %f633, %f662;
	add.f32 	%f664, %f661, %f657;
	sub.f32 	%f665, %f661, %f664;
	add.f32 	%f666, %f657, %f665;
	add.f32 	%f667, %f659, %f666;
	add.f32 	%f668, %f663, %f667;
	add.f32 	%f669, %f664, %f668;
	sub.f32 	%f670, %f664, %f669;
	add.f32 	%f671, %f668, %f670;
	mov.f32 	%f672, 0f3EE66666;
	mul.rn.f32 	%f673, %f672, %f669;
	neg.f32 	%f674, %f673;
	fma.rn.f32 	%f675, %f672, %f669, %f674;
	fma.rn.f32 	%f676, %f672, %f671, %f675;
	mov.f32 	%f677, 0f00000000;
	fma.rn.f32 	%f678, %f677, %f669, %f676;
	add.rn.f32 	%f679, %f673, %f678;
	neg.f32 	%f680, %f679;
	add.rn.f32 	%f681, %f673, %f680;
	add.rn.f32 	%f682, %f681, %f678;
	mov.b32 	%r244, %f679;
	setp.eq.s32 	%p82, %r244, 1118925336;
	add.s32 	%r245, %r244, -1;
	mov.b32 	%f683, %r245;
	add.f32 	%f684, %f682, 0f37000000;
	selp.f32 	%f148, %f684, %f682, %p82;
	selp.f32 	%f685, %f683, %f679, %p82;
	mov.f32 	%f686, 0f3FB8AA3B;
	mul.rn.f32 	%f687, %f685, %f686;
	cvt.rzi.f32.f32 	%f688, %f687;
	abs.f32 	%f689, %f688;
	setp.gt.f32 	%p83, %f689, 0f42FC0000;
	mov.b32 	%r246, %f688;
	and.b32  	%r247, %r246, -2147483648;
	or.b32  	%r248, %r247, 1123811328;
	mov.b32 	%f690, %r248;
	selp.f32 	%f691, %f690, %f688, %p83;
	mov.f32 	%f692, 0fBF317218;
	fma.rn.f32 	%f693, %f691, %f692, %f685;
	mov.f32 	%f694, 0f3102E308;
	fma.rn.f32 	%f695, %f691, %f694, %f693;
	mul.f32 	%f696, %f695, 0f3FB8AA3B;
	add.f32 	%f697, %f691, 0f4B40007F;
	mov.b32 	%r249, %f697;
	shl.b32 	%r250, %r249, 23;
	mov.b32 	%f698, %r250;
	ex2.approx.ftz.f32 	%f699, %f696;
	mul.f32 	%f149, %f699, %f698;
	setp.eq.f32 	%p84, %f149, 0f7F800000;
	mov.f32 	%f1195, 0f7F800000;
	@%p84 bra 	$L__BB0_71;

	fma.rn.f32 	%f1195, %f149, %f148, %f149;

$L__BB0_71:
	setp.lt.f32 	%p85, %f121, 0f00000000;
	and.pred  	%p3, %p85, %p56;
	setp.eq.f32 	%p87, %f121, 0f00000000;
	@%p87 bra 	$L__BB0_75;
	bra.uni 	$L__BB0_72;

$L__BB0_75:
	add.f32 	%f704, %f121, %f121;
	selp.f32 	%f1197, %f704, 0f00000000, %p56;
	bra.uni 	$L__BB0_76;

$L__BB0_72:
	mov.b32 	%r251, %f1195;
	xor.b32  	%r252, %r251, -2147483648;
	mov.b32 	%f700, %r252;
	selp.f32 	%f1197, %f700, %f1195, %p3;
	setp.geu.f32 	%p88, %f121, 0f00000000;
	@%p88 bra 	$L__BB0_76;

	mov.f32 	%f701, 0f3EE66666;
	cvt.rzi.f32.f32 	%f702, %f701;
	setp.eq.f32 	%p89, %f702, 0f3EE66666;
	@%p89 bra 	$L__BB0_76;

	mov.f32 	%f1197, 0f7FFFFFFF;

$L__BB0_76:
	add.f32 	%f705, %f147, 0f3EE66666;
	mov.b32 	%r253, %f705;
	setp.lt.s32 	%p91, %r253, 2139095040;
	@%p91 bra 	$L__BB0_81;

	setp.gtu.f32 	%p92, %f147, 0f7F800000;
	@%p92 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_78;

$L__BB0_80:
	add.f32 	%f1197, %f121, 0f3EE66666;
	bra.uni 	$L__BB0_81;

$L__BB0_78:
	setp.neu.f32 	%p93, %f147, 0f7F800000;
	@%p93 bra 	$L__BB0_81;

	selp.f32 	%f1197, 0fFF800000, 0f7F800000, %p3;

$L__BB0_81:
	setp.eq.f32 	%p94, %f121, 0f3F800000;
	mov.f32 	%f707, 0f3F800000;
	selp.f32 	%f708, 0f3F800000, %f1197, %p94;
	min.f32 	%f709, %f134, %f707;
	mov.f32 	%f710, 0f00000000;
	max.f32 	%f158, %f710, %f709;
	min.f32 	%f711, %f146, %f707;
	max.f32 	%f159, %f710, %f711;
	min.f32 	%f712, %f708, %f707;
	max.f32 	%f160, %f710, %f712;
	mov.f32 	%f716, 0f3ED55555;
	abs.f32 	%f162, %f158;
	setp.lt.f32 	%p95, %f162, 0f00800000;
	mul.f32 	%f718, %f162, 0f4B800000;
	selp.f32 	%f719, %f718, %f162, %p95;
	selp.f32 	%f720, 0fC3170000, 0fC2FE0000, %p95;
	mov.b32 	%r256, %f719;
	and.b32  	%r257, %r256, 8388607;
	or.b32  	%r258, %r257, 1065353216;
	mov.b32 	%f721, %r258;
	shr.u32 	%r259, %r256, 23;
	cvt.rn.f32.u32 	%f722, %r259;
	add.f32 	%f723, %f720, %f722;
	setp.gt.f32 	%p96, %f721, 0f3FB504F3;
	mul.f32 	%f724, %f721, 0f3F000000;
	add.f32 	%f725, %f723, 0f3F800000;
	selp.f32 	%f726, %f725, %f723, %p96;
	selp.f32 	%f727, %f724, %f721, %p96;
	add.f32 	%f728, %f727, 0fBF800000;
	add.f32 	%f729, %f727, 0f3F800000;
	rcp.approx.ftz.f32 	%f730, %f729;
	add.f32 	%f731, %f728, %f728;
	mul.f32 	%f732, %f731, %f730;
	mul.f32 	%f733, %f732, %f732;
	mov.f32 	%f734, 0f3C4CAF63;
	mov.f32 	%f735, 0f3B18F0FE;
	fma.rn.f32 	%f736, %f735, %f733, %f734;
	mov.f32 	%f737, 0f3DAAAABD;
	fma.rn.f32 	%f738, %f736, %f733, %f737;
	mul.rn.f32 	%f739, %f738, %f733;
	mul.rn.f32 	%f740, %f739, %f732;
	sub.f32 	%f741, %f728, %f732;
	add.f32 	%f742, %f741, %f741;
	neg.f32 	%f743, %f732;
	fma.rn.f32 	%f744, %f743, %f728, %f742;
	mul.rn.f32 	%f745, %f730, %f744;
	add.f32 	%f746, %f740, %f732;
	sub.f32 	%f747, %f732, %f746;
	add.f32 	%f748, %f740, %f747;
	add.f32 	%f749, %f745, %f748;
	add.f32 	%f750, %f746, %f749;
	sub.f32 	%f751, %f746, %f750;
	add.f32 	%f752, %f749, %f751;
	mov.f32 	%f753, 0f3F317200;
	mul.rn.f32 	%f754, %f726, %f753;
	mov.f32 	%f755, 0f35BFBE8E;
	mul.rn.f32 	%f756, %f726, %f755;
	add.f32 	%f757, %f754, %f750;
	sub.f32 	%f758, %f754, %f757;
	add.f32 	%f759, %f750, %f758;
	add.f32 	%f760, %f752, %f759;
	add.f32 	%f761, %f756, %f760;
	add.f32 	%f762, %f757, %f761;
	sub.f32 	%f763, %f757, %f762;
	add.f32 	%f764, %f761, %f763;
	mul.rn.f32 	%f765, %f716, %f762;
	neg.f32 	%f766, %f765;
	fma.rn.f32 	%f767, %f716, %f762, %f766;
	fma.rn.f32 	%f768, %f716, %f764, %f767;
	fma.rn.f32 	%f769, %f710, %f762, %f768;
	add.rn.f32 	%f770, %f765, %f769;
	neg.f32 	%f771, %f770;
	add.rn.f32 	%f772, %f765, %f771;
	add.rn.f32 	%f773, %f772, %f769;
	mov.b32 	%r260, %f770;
	setp.eq.s32 	%p97, %r260, 1118925336;
	add.s32 	%r261, %r260, -1;
	mov.b32 	%f774, %r261;
	add.f32 	%f775, %f773, 0f37000000;
	selp.f32 	%f163, %f775, %f773, %p97;
	selp.f32 	%f776, %f774, %f770, %p97;
	mov.f32 	%f777, 0f3FB8AA3B;
	mul.rn.f32 	%f778, %f776, %f777;
	cvt.rzi.f32.f32 	%f779, %f778;
	abs.f32 	%f780, %f779;
	setp.gt.f32 	%p98, %f780, 0f42FC0000;
	mov.b32 	%r262, %f779;
	and.b32  	%r263, %r262, -2147483648;
	or.b32  	%r264, %r263, 1123811328;
	mov.b32 	%f781, %r264;
	selp.f32 	%f782, %f781, %f779, %p98;
	mov.f32 	%f783, 0fBF317218;
	fma.rn.f32 	%f784, %f782, %f783, %f776;
	mov.f32 	%f785, 0f3102E308;
	fma.rn.f32 	%f786, %f782, %f785, %f784;
	mul.f32 	%f787, %f786, 0f3FB8AA3B;
	add.f32 	%f788, %f782, 0f4B40007F;
	mov.b32 	%r265, %f788;
	shl.b32 	%r266, %r265, 23;
	mov.b32 	%f789, %r266;
	ex2.approx.ftz.f32 	%f790, %f787;
	mul.f32 	%f164, %f790, %f789;
	setp.eq.f32 	%p99, %f164, 0f7F800000;
	mov.f32 	%f1198, 0f7F800000;
	@%p99 bra 	$L__BB0_83;

	fma.rn.f32 	%f1198, %f164, %f163, %f164;

$L__BB0_83:
	mov.f32 	%f1099, 0f00000000;
	max.f32 	%f1098, %f1099, %f709;
	mov.f32 	%f1097, 0f3E555555;
	cvt.rzi.f32.f32 	%f1096, %f1097;
	add.f32 	%f1095, %f1096, %f1096;
	mov.f32 	%f1094, 0f3ED55555;
	sub.f32 	%f1093, %f1094, %f1095;
	abs.f32 	%f1092, %f1093;
	setp.lt.f32 	%p100, %f1098, 0f00000000;
	setp.eq.f32 	%p101, %f1092, 0f3F800000;
	and.pred  	%p4, %p100, %p101;
	setp.eq.f32 	%p102, %f1098, 0f00000000;
	@%p102 bra 	$L__BB0_87;
	bra.uni 	$L__BB0_84;

$L__BB0_87:
	mov.f32 	%f1120, 0f00000000;
	max.f32 	%f1119, %f1120, %f709;
	add.f32 	%f795, %f1119, %f1119;
	selp.f32 	%f1200, %f795, 0f00000000, %p101;
	bra.uni 	$L__BB0_88;

$L__BB0_84:
	mov.f32 	%f1101, 0f00000000;
	max.f32 	%f1100, %f1101, %f709;
	mov.b32 	%r267, %f1198;
	xor.b32  	%r268, %r267, -2147483648;
	mov.b32 	%f791, %r268;
	selp.f32 	%f1200, %f791, %f1198, %p4;
	setp.geu.f32 	%p103, %f1100, 0f00000000;
	@%p103 bra 	$L__BB0_88;

	mov.f32 	%f792, 0f3ED55555;
	cvt.rzi.f32.f32 	%f793, %f792;
	setp.eq.f32 	%p104, %f793, 0f3ED55555;
	@%p104 bra 	$L__BB0_88;

	mov.f32 	%f1200, 0f7FFFFFFF;

$L__BB0_88:
	mov.f32 	%f1104, 0f00000000;
	max.f32 	%f1103, %f1104, %f709;
	abs.f32 	%f1102, %f1103;
	add.f32 	%f796, %f1102, 0f3ED55555;
	mov.b32 	%r269, %f796;
	setp.lt.s32 	%p106, %r269, 2139095040;
	@%p106 bra 	$L__BB0_93;

	mov.f32 	%f1113, 0f00000000;
	max.f32 	%f1112, %f1113, %f709;
	abs.f32 	%f1111, %f1112;
	setp.gtu.f32 	%p107, %f1111, 0f7F800000;
	@%p107 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_90;

$L__BB0_92:
	mov.f32 	%f1118, 0f00000000;
	max.f32 	%f1117, %f1118, %f709;
	add.f32 	%f1200, %f1117, 0f3ED55555;
	bra.uni 	$L__BB0_93;

$L__BB0_90:
	mov.f32 	%f1116, 0f00000000;
	max.f32 	%f1115, %f1116, %f709;
	abs.f32 	%f1114, %f1115;
	setp.neu.f32 	%p108, %f1114, 0f7F800000;
	@%p108 bra 	$L__BB0_93;

	selp.f32 	%f1200, 0fFF800000, 0f7F800000, %p4;

$L__BB0_93:
	abs.f32 	%f173, %f159;
	setp.lt.f32 	%p109, %f173, 0f00800000;
	mul.f32 	%f798, %f173, 0f4B800000;
	selp.f32 	%f799, %f798, %f173, %p109;
	selp.f32 	%f800, 0fC3170000, 0fC2FE0000, %p109;
	mov.b32 	%r270, %f799;
	and.b32  	%r271, %r270, 8388607;
	or.b32  	%r272, %r271, 1065353216;
	mov.b32 	%f801, %r272;
	shr.u32 	%r273, %r270, 23;
	cvt.rn.f32.u32 	%f802, %r273;
	add.f32 	%f803, %f800, %f802;
	setp.gt.f32 	%p110, %f801, 0f3FB504F3;
	mul.f32 	%f804, %f801, 0f3F000000;
	add.f32 	%f805, %f803, 0f3F800000;
	selp.f32 	%f806, %f805, %f803, %p110;
	selp.f32 	%f807, %f804, %f801, %p110;
	add.f32 	%f808, %f807, 0fBF800000;
	add.f32 	%f809, %f807, 0f3F800000;
	rcp.approx.ftz.f32 	%f810, %f809;
	add.f32 	%f811, %f808, %f808;
	mul.f32 	%f812, %f811, %f810;
	mul.f32 	%f813, %f812, %f812;
	mov.f32 	%f814, 0f3C4CAF63;
	mov.f32 	%f815, 0f3B18F0FE;
	fma.rn.f32 	%f816, %f815, %f813, %f814;
	mov.f32 	%f817, 0f3DAAAABD;
	fma.rn.f32 	%f818, %f816, %f813, %f817;
	mul.rn.f32 	%f819, %f818, %f813;
	mul.rn.f32 	%f820, %f819, %f812;
	sub.f32 	%f821, %f808, %f812;
	add.f32 	%f822, %f821, %f821;
	neg.f32 	%f823, %f812;
	fma.rn.f32 	%f824, %f823, %f808, %f822;
	mul.rn.f32 	%f825, %f810, %f824;
	add.f32 	%f826, %f820, %f812;
	sub.f32 	%f827, %f812, %f826;
	add.f32 	%f828, %f820, %f827;
	add.f32 	%f829, %f825, %f828;
	add.f32 	%f830, %f826, %f829;
	sub.f32 	%f831, %f826, %f830;
	add.f32 	%f832, %f829, %f831;
	mov.f32 	%f833, 0f3F317200;
	mul.rn.f32 	%f834, %f806, %f833;
	mov.f32 	%f835, 0f35BFBE8E;
	mul.rn.f32 	%f836, %f806, %f835;
	add.f32 	%f837, %f834, %f830;
	sub.f32 	%f838, %f834, %f837;
	add.f32 	%f839, %f830, %f838;
	add.f32 	%f840, %f832, %f839;
	add.f32 	%f841, %f836, %f840;
	add.f32 	%f842, %f837, %f841;
	sub.f32 	%f843, %f837, %f842;
	add.f32 	%f844, %f841, %f843;
	mov.f32 	%f845, 0f3ED55555;
	mul.rn.f32 	%f846, %f845, %f842;
	neg.f32 	%f847, %f846;
	fma.rn.f32 	%f848, %f845, %f842, %f847;
	fma.rn.f32 	%f849, %f845, %f844, %f848;
	mov.f32 	%f850, 0f00000000;
	fma.rn.f32 	%f851, %f850, %f842, %f849;
	add.rn.f32 	%f852, %f846, %f851;
	neg.f32 	%f853, %f852;
	add.rn.f32 	%f854, %f846, %f853;
	add.rn.f32 	%f855, %f854, %f851;
	mov.b32 	%r274, %f852;
	setp.eq.s32 	%p111, %r274, 1118925336;
	add.s32 	%r275, %r274, -1;
	mov.b32 	%f856, %r275;
	add.f32 	%f857, %f855, 0f37000000;
	selp.f32 	%f174, %f857, %f855, %p111;
	selp.f32 	%f858, %f856, %f852, %p111;
	mov.f32 	%f859, 0f3FB8AA3B;
	mul.rn.f32 	%f860, %f858, %f859;
	cvt.rzi.f32.f32 	%f861, %f860;
	abs.f32 	%f862, %f861;
	setp.gt.f32 	%p112, %f862, 0f42FC0000;
	mov.b32 	%r276, %f861;
	and.b32  	%r277, %r276, -2147483648;
	or.b32  	%r278, %r277, 1123811328;
	mov.b32 	%f863, %r278;
	selp.f32 	%f864, %f863, %f861, %p112;
	mov.f32 	%f865, 0fBF317218;
	fma.rn.f32 	%f866, %f864, %f865, %f858;
	mov.f32 	%f867, 0f3102E308;
	fma.rn.f32 	%f868, %f864, %f867, %f866;
	mul.f32 	%f869, %f868, 0f3FB8AA3B;
	add.f32 	%f870, %f864, 0f4B40007F;
	mov.b32 	%r279, %f870;
	shl.b32 	%r280, %r279, 23;
	mov.b32 	%f871, %r280;
	ex2.approx.ftz.f32 	%f872, %f869;
	mul.f32 	%f175, %f872, %f871;
	setp.eq.f32 	%p113, %f175, 0f7F800000;
	mov.f32 	%f1201, 0f7F800000;
	@%p113 bra 	$L__BB0_95;

	fma.rn.f32 	%f1201, %f175, %f174, %f175;

$L__BB0_95:
	setp.lt.f32 	%p114, %f159, 0f00000000;
	and.pred  	%p5, %p114, %p101;
	setp.eq.f32 	%p116, %f159, 0f00000000;
	@%p116 bra 	$L__BB0_99;
	bra.uni 	$L__BB0_96;

$L__BB0_99:
	add.f32 	%f877, %f159, %f159;
	selp.f32 	%f1203, %f877, 0f00000000, %p101;
	bra.uni 	$L__BB0_100;

$L__BB0_96:
	mov.b32 	%r281, %f1201;
	xor.b32  	%r282, %r281, -2147483648;
	mov.b32 	%f873, %r282;
	selp.f32 	%f1203, %f873, %f1201, %p5;
	setp.geu.f32 	%p117, %f159, 0f00000000;
	@%p117 bra 	$L__BB0_100;

	mov.f32 	%f874, 0f3ED55555;
	cvt.rzi.f32.f32 	%f875, %f874;
	setp.eq.f32 	%p118, %f875, 0f3ED55555;
	@%p118 bra 	$L__BB0_100;

	mov.f32 	%f1203, 0f7FFFFFFF;

$L__BB0_100:
	mov.f32 	%f1135, 0f00000000;
	max.f32 	%f1134, %f1135, %f711;
	abs.f32 	%f1133, %f1134;
	add.f32 	%f878, %f1133, 0f3ED55555;
	mov.b32 	%r283, %f878;
	setp.lt.s32 	%p120, %r283, 2139095040;
	@%p120 bra 	$L__BB0_105;

	mov.f32 	%f1138, 0f00000000;
	max.f32 	%f1137, %f1138, %f711;
	abs.f32 	%f1136, %f1137;
	setp.gtu.f32 	%p121, %f1136, 0f7F800000;
	@%p121 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_102;

$L__BB0_104:
	add.f32 	%f1203, %f159, 0f3ED55555;
	bra.uni 	$L__BB0_105;

$L__BB0_102:
	mov.f32 	%f1141, 0f00000000;
	max.f32 	%f1140, %f1141, %f711;
	abs.f32 	%f1139, %f1140;
	setp.neu.f32 	%p122, %f1139, 0f7F800000;
	@%p122 bra 	$L__BB0_105;

	selp.f32 	%f1203, 0fFF800000, 0f7F800000, %p5;

$L__BB0_105:
	abs.f32 	%f184, %f160;
	setp.lt.f32 	%p123, %f184, 0f00800000;
	mul.f32 	%f880, %f184, 0f4B800000;
	selp.f32 	%f881, %f880, %f184, %p123;
	selp.f32 	%f882, 0fC3170000, 0fC2FE0000, %p123;
	mov.b32 	%r284, %f881;
	and.b32  	%r285, %r284, 8388607;
	or.b32  	%r286, %r285, 1065353216;
	mov.b32 	%f883, %r286;
	shr.u32 	%r287, %r284, 23;
	cvt.rn.f32.u32 	%f884, %r287;
	add.f32 	%f885, %f882, %f884;
	setp.gt.f32 	%p124, %f883, 0f3FB504F3;
	mul.f32 	%f886, %f883, 0f3F000000;
	add.f32 	%f887, %f885, 0f3F800000;
	selp.f32 	%f888, %f887, %f885, %p124;
	selp.f32 	%f889, %f886, %f883, %p124;
	add.f32 	%f890, %f889, 0fBF800000;
	add.f32 	%f891, %f889, 0f3F800000;
	rcp.approx.ftz.f32 	%f892, %f891;
	add.f32 	%f893, %f890, %f890;
	mul.f32 	%f894, %f893, %f892;
	mul.f32 	%f895, %f894, %f894;
	mov.f32 	%f896, 0f3C4CAF63;
	mov.f32 	%f897, 0f3B18F0FE;
	fma.rn.f32 	%f898, %f897, %f895, %f896;
	mov.f32 	%f899, 0f3DAAAABD;
	fma.rn.f32 	%f900, %f898, %f895, %f899;
	mul.rn.f32 	%f901, %f900, %f895;
	mul.rn.f32 	%f902, %f901, %f894;
	sub.f32 	%f903, %f890, %f894;
	add.f32 	%f904, %f903, %f903;
	neg.f32 	%f905, %f894;
	fma.rn.f32 	%f906, %f905, %f890, %f904;
	mul.rn.f32 	%f907, %f892, %f906;
	add.f32 	%f908, %f902, %f894;
	sub.f32 	%f909, %f894, %f908;
	add.f32 	%f910, %f902, %f909;
	add.f32 	%f911, %f907, %f910;
	add.f32 	%f912, %f908, %f911;
	sub.f32 	%f913, %f908, %f912;
	add.f32 	%f914, %f911, %f913;
	mov.f32 	%f915, 0f3F317200;
	mul.rn.f32 	%f916, %f888, %f915;
	mov.f32 	%f917, 0f35BFBE8E;
	mul.rn.f32 	%f918, %f888, %f917;
	add.f32 	%f919, %f916, %f912;
	sub.f32 	%f920, %f916, %f919;
	add.f32 	%f921, %f912, %f920;
	add.f32 	%f922, %f914, %f921;
	add.f32 	%f923, %f918, %f922;
	add.f32 	%f924, %f919, %f923;
	sub.f32 	%f925, %f919, %f924;
	add.f32 	%f926, %f923, %f925;
	mov.f32 	%f927, 0f3ED55555;
	mul.rn.f32 	%f928, %f927, %f924;
	neg.f32 	%f929, %f928;
	fma.rn.f32 	%f930, %f927, %f924, %f929;
	fma.rn.f32 	%f931, %f927, %f926, %f930;
	mov.f32 	%f932, 0f00000000;
	fma.rn.f32 	%f933, %f932, %f924, %f931;
	add.rn.f32 	%f934, %f928, %f933;
	neg.f32 	%f935, %f934;
	add.rn.f32 	%f936, %f928, %f935;
	add.rn.f32 	%f937, %f936, %f933;
	mov.b32 	%r288, %f934;
	setp.eq.s32 	%p125, %r288, 1118925336;
	add.s32 	%r289, %r288, -1;
	mov.b32 	%f938, %r289;
	add.f32 	%f939, %f937, 0f37000000;
	selp.f32 	%f185, %f939, %f937, %p125;
	selp.f32 	%f940, %f938, %f934, %p125;
	mov.f32 	%f941, 0f3FB8AA3B;
	mul.rn.f32 	%f942, %f940, %f941;
	cvt.rzi.f32.f32 	%f943, %f942;
	abs.f32 	%f944, %f943;
	setp.gt.f32 	%p126, %f944, 0f42FC0000;
	mov.b32 	%r290, %f943;
	and.b32  	%r291, %r290, -2147483648;
	or.b32  	%r292, %r291, 1123811328;
	mov.b32 	%f945, %r292;
	selp.f32 	%f946, %f945, %f943, %p126;
	mov.f32 	%f947, 0fBF317218;
	fma.rn.f32 	%f948, %f946, %f947, %f940;
	mov.f32 	%f949, 0f3102E308;
	fma.rn.f32 	%f950, %f946, %f949, %f948;
	mul.f32 	%f951, %f950, 0f3FB8AA3B;
	add.f32 	%f952, %f946, 0f4B40007F;
	mov.b32 	%r293, %f952;
	shl.b32 	%r294, %r293, 23;
	mov.b32 	%f953, %r294;
	ex2.approx.ftz.f32 	%f954, %f951;
	mul.f32 	%f186, %f954, %f953;
	setp.eq.f32 	%p127, %f186, 0f7F800000;
	mov.f32 	%f1204, 0f7F800000;
	@%p127 bra 	$L__BB0_107;

	fma.rn.f32 	%f1204, %f186, %f185, %f186;

$L__BB0_107:
	setp.lt.f32 	%p128, %f160, 0f00000000;
	and.pred  	%p6, %p128, %p101;
	setp.eq.f32 	%p130, %f160, 0f00000000;
	@%p130 bra 	$L__BB0_111;
	bra.uni 	$L__BB0_108;

$L__BB0_111:
	add.f32 	%f959, %f160, %f160;
	selp.f32 	%f1206, %f959, 0f00000000, %p101;
	bra.uni 	$L__BB0_112;

$L__BB0_108:
	mov.b32 	%r295, %f1204;
	xor.b32  	%r296, %r295, -2147483648;
	mov.b32 	%f955, %r296;
	selp.f32 	%f1206, %f955, %f1204, %p6;
	setp.geu.f32 	%p131, %f160, 0f00000000;
	@%p131 bra 	$L__BB0_112;

	mov.f32 	%f956, 0f3ED55555;
	cvt.rzi.f32.f32 	%f957, %f956;
	setp.eq.f32 	%p132, %f957, 0f3ED55555;
	@%p132 bra 	$L__BB0_112;

	mov.f32 	%f1206, 0f7FFFFFFF;

$L__BB0_112:
	mov.f32 	%f1144, 0f00000000;
	max.f32 	%f1143, %f1144, %f712;
	abs.f32 	%f1142, %f1143;
	add.f32 	%f960, %f1142, 0f3ED55555;
	mov.b32 	%r297, %f960;
	setp.lt.s32 	%p134, %r297, 2139095040;
	@%p134 bra 	$L__BB0_117;

	mov.f32 	%f1147, 0f00000000;
	max.f32 	%f1146, %f1147, %f712;
	abs.f32 	%f1145, %f1146;
	setp.gtu.f32 	%p135, %f1145, 0f7F800000;
	@%p135 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_114;

$L__BB0_116:
	add.f32 	%f1206, %f160, 0f3ED55555;
	bra.uni 	$L__BB0_117;

$L__BB0_114:
	mov.f32 	%f1150, 0f00000000;
	max.f32 	%f1149, %f1150, %f712;
	abs.f32 	%f1148, %f1149;
	setp.neu.f32 	%p136, %f1148, 0f7F800000;
	@%p136 bra 	$L__BB0_117;

	selp.f32 	%f1206, 0fFF800000, 0f7F800000, %p6;

$L__BB0_117:
	mov.f32 	%f1106, 0f00000000;
	max.f32 	%f1105, %f1106, %f709;
	ld.const.u64 	%rd107, [params+144];
	cvta.to.global.u64 	%rd106, %rd107;
	ld.const.u32 	%r332, [params+136];
	mad.lo.s32 	%r331, %r332, %r5, %r4;
	cvt.u64.u32 	%rd105, %r331;
	fma.rn.f32 	%f961, %f1200, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p137, %f1105, 0f3F800000;
	mov.f32 	%f962, 0f3F800000;
	selp.f32 	%f963, 0f3F7FFFFF, %f961, %p137;
	mul.f32 	%f964, %f1105, 0f414EB852;
	setp.lt.f32 	%p138, %f1105, 0f3B4D2E1C;
	selp.f32 	%f965, %f964, %f963, %p138;
	fma.rn.f32 	%f966, %f1203, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p139, %f159, 0f3F800000;
	selp.f32 	%f967, 0f3F7FFFFF, %f966, %p139;
	mul.f32 	%f968, %f159, 0f414EB852;
	setp.lt.f32 	%p140, %f159, 0f3B4D2E1C;
	selp.f32 	%f969, %f968, %f967, %p140;
	fma.rn.f32 	%f970, %f1206, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p141, %f160, 0f3F800000;
	selp.f32 	%f971, 0f3F7FFFFF, %f970, %p141;
	mul.f32 	%f972, %f160, 0f414EB852;
	setp.lt.f32 	%p142, %f160, 0f3B4D2E1C;
	selp.f32 	%f973, %f972, %f971, %p142;
	min.f32 	%f974, %f965, %f962;
	mov.f32 	%f975, 0f00000000;
	max.f32 	%f976, %f975, %f974;
	mul.f32 	%f977, %f976, 0f43800000;
	cvt.rzi.u32.f32 	%r298, %f977;
	min.u32 	%r299, %r298, 255;
	min.f32 	%f978, %f969, %f962;
	max.f32 	%f979, %f975, %f978;
	mul.f32 	%f980, %f979, 0f43800000;
	cvt.rzi.u32.f32 	%r300, %f980;
	min.u32 	%r301, %r300, 255;
	min.f32 	%f981, %f973, %f962;
	max.f32 	%f982, %f975, %f981;
	mul.f32 	%f983, %f982, 0f43800000;
	cvt.rzi.u32.f32 	%r302, %f983;
	min.u32 	%r303, %r302, 255;
	shl.b64 	%rd69, %rd105, 2;
	add.s64 	%rd70, %rd106, %rd69;
	cvt.u16.u32 	%rs44, %r303;
	cvt.u16.u32 	%rs45, %r301;
	cvt.u16.u32 	%rs46, %r299;
	mov.u16 	%rs47, 255;
	st.global.v4.u8 	[%rd70], {%rs46, %rs45, %rs44, %rs47};

$L__BB0_118:
	ld.const.u32 	%r333, [params+104];
	and.b32  	%r304, %r333, 4;
	setp.eq.s32 	%p143, %r304, 0;
	ld.const.u32 	%r355, [params+108];
	@%p143 bra 	$L__BB0_122;

	setp.eq.s32 	%p144, %r355, 0;
	ld.const.u64 	%rd71, [params+224];
	cvta.to.global.u64 	%rd72, %rd71;
	ld.const.u32 	%r305, [params+216];
	mad.lo.s32 	%r306, %r305, %r5, %r4;
	mul.wide.u32 	%rd73, %r306, 8;
	add.s64 	%rd18, %rd72, %rd73;
	@%p144 bra 	$L__BB0_121;

	add.f32 	%f1130, %f450, %f450;
	mul.f32 	%f1129, %f1130, %f452;
	add.f32 	%f1108, %f450, %f450;
	mul.f32 	%f1107, %f1108, %f453;
	ld.global.v4.u16 	{%rs55, %rs56, %rs57, %rs58}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f984, %rs55;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f985, %rs56;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f986, %rs57;}

	// end inline asm
	add.f32 	%f987, %f1129, %f984;
	add.f32 	%f988, %f1107, %f985;
	add.f32 	%f989, %f121, %f986;
	mov.f32 	%f990, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f989;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f988;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f987;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f990;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs51, %rs52, %rs53, %rs54};
	bra.uni 	$L__BB0_122;

$L__BB0_121:
	add.f32 	%f1132, %f450, %f450;
	mul.f32 	%f1131, %f1132, %f452;
	add.f32 	%f1110, %f450, %f450;
	mul.f32 	%f1109, %f1110, %f453;
	mov.f32 	%f994, 0f3F800000;
	mov.u32 	%r355, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f994;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f121;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1109;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1131;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs59, %rs60, %rs61, %rs62};

$L__BB0_122:
	mul.f32 	%f195, %f112, 0f3F000000;
	mul.f32 	%f196, %f195, %f452;
	mul.f32 	%f197, %f195, %f453;
	mul.f32 	%f198, %f195, %f454;
	ld.const.u64 	%rd74, [params+256];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r308, [params+248];
	mad.lo.s32 	%r309, %r308, %r5, %r4;
	mul.wide.u32 	%rd76, %r309, 8;
	add.s64 	%rd19, %rd75, %rd76;
	setp.eq.s32 	%p145, %r355, 0;
	@%p145 bra 	$L__BB0_124;

	ld.global.v4.u16 	{%rs70, %rs71, %rs72, %rs73}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f995, %rs70;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs71;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f997, %rs72;}

	// end inline asm
	add.f32 	%f998, %f196, %f995;
	add.f32 	%f999, %f197, %f996;
	add.f32 	%f1000, %f198, %f997;
	mov.f32 	%f1001, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1000;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1001;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs66, %rs67, %rs68, %rs69};
	bra.uni 	$L__BB0_125;

$L__BB0_124:
	mov.f32 	%f1005, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f1005;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f198;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f197;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f196;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs74, %rs75, %rs76, %rs77};

$L__BB0_125:
	mov.f32 	%f1006, 0f34000000;
	max.f32 	%f1007, %f195, %f1006;
	mul.f32 	%f1008, %f113, 0f3F000000;
	div.rn.f32 	%f1009, %f1008, %f1007;
	fma.rn.f32 	%f199, %f1009, 0f3F000000, 0f3F000000;
	mul.f32 	%f1010, %f114, 0f3F000000;
	div.rn.f32 	%f1011, %f1010, %f1007;
	fma.rn.f32 	%f200, %f1011, 0f3F000000, 0f3F000000;
	mul.f32 	%f1012, %f115, 0f3F000000;
	div.rn.f32 	%f1013, %f1012, %f1007;
	fma.rn.f32 	%f201, %f1013, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd77, [params+272];
	cvta.to.global.u64 	%rd78, %rd77;
	ld.const.u32 	%r310, [params+264];
	mad.lo.s32 	%r311, %r310, %r5, %r4;
	mul.wide.u32 	%rd79, %r311, 8;
	add.s64 	%rd20, %rd78, %rd79;
	@%p145 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs85, %rs86, %rs87, %rs88}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1014, %rs85;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1015, %rs86;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1016, %rs87;}

	// end inline asm
	add.f32 	%f1017, %f199, %f1014;
	add.f32 	%f1018, %f199, %f1015;
	add.f32 	%f1019, %f199, %f1016;
	mov.f32 	%f1020, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1018;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1017;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1020;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs81, %rs82, %rs83, %rs84};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f1024, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f1024;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f199;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f199;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f199;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs89, %rs90, %rs91, %rs92};

$L__BB0_128:
	ld.const.u64 	%rd80, [params+288];
	cvta.to.global.u64 	%rd81, %rd80;
	ld.const.u32 	%r312, [params+280];
	mad.lo.s32 	%r313, %r312, %r5, %r4;
	mul.wide.u32 	%rd82, %r313, 8;
	add.s64 	%rd21, %rd81, %rd82;
	@%p145 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs100, %rs101, %rs102, %rs103}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1025, %rs100;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1026, %rs101;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1027, %rs102;}

	// end inline asm
	add.f32 	%f1028, %f200, %f1025;
	add.f32 	%f1029, %f200, %f1026;
	add.f32 	%f1030, %f200, %f1027;
	mov.f32 	%f1031, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1030;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1029;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1028;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1031;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs96, %rs97, %rs98, %rs99};
	bra.uni 	$L__BB0_131;

$L__BB0_130:
	mov.f32 	%f1035, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f200;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f200;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f200;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs104, %rs105, %rs106, %rs107};

$L__BB0_131:
	ld.const.u64 	%rd83, [params+304];
	cvta.to.global.u64 	%rd84, %rd83;
	ld.const.u32 	%r314, [params+296];
	mad.lo.s32 	%r315, %r314, %r5, %r4;
	mul.wide.u32 	%rd85, %r315, 8;
	add.s64 	%rd22, %rd84, %rd85;
	@%p145 bra 	$L__BB0_133;

	ld.global.v4.u16 	{%rs115, %rs116, %rs117, %rs118}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1036, %rs115;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1037, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1038, %rs117;}

	// end inline asm
	add.f32 	%f1039, %f201, %f1036;
	add.f32 	%f1040, %f201, %f1037;
	add.f32 	%f1041, %f201, %f1038;
	mov.f32 	%f1042, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1039;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1042;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs111, %rs112, %rs113, %rs114};
	bra.uni 	$L__BB0_152;

$L__BB0_133:
	mov.f32 	%f1046, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1046;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f201;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs119, %rs120, %rs121, %rs122};

$L__BB0_152:
	ret;

}