//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<200>;
	.reg .b16 	%rs<177>;
	.reg .f32 	%f<1645>;
	.reg .b32 	%r<469>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<125>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r62), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r63), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+616];
	abs.s32 	%r4, %r3;
	ld.const.u32 	%r5, [params+540];
	ld.const.u64 	%rd34, [params+400];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r68, [params+392];
	mad.lo.s32 	%r69, %r68, %r63, %r62;
	mul.wide.u32 	%rd36, %r69, 4;
	add.s64 	%rd2, %rd35, %rd36;
	ld.global.v2.u8 	{%rs7, %rs176}, [%rd2];
	or.b16  	%rs9, %rs7, %rs176;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p10, %rs10, 0;
	@%p10 bra 	$L__BB0_2;

	ld.global.u8 	%rs175, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs175, [%rd2+2];
	setp.eq.s16 	%p11, %rs175, 0;
	mov.f32 	%f1487, 0f00000000;
	mov.u16 	%rs176, 0;
	mov.f32 	%f1488, %f1487;
	mov.f32 	%f1489, %f1487;
	@%p11 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f384, %rs7;
	div.rn.f32 	%f385, %f384, 0f437F0000;
	fma.rn.f32 	%f386, %f385, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs176, 255;
	cvt.rn.f32.u16 	%f387, %rs13;
	div.rn.f32 	%f388, %f387, 0f437F0000;
	fma.rn.f32 	%f389, %f388, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f390, %rs175;
	div.rn.f32 	%f391, %f390, 0f437F0000;
	fma.rn.f32 	%f392, %f391, 0f40000000, 0fBF800000;
	mul.f32 	%f393, %f389, %f389;
	fma.rn.f32 	%f394, %f386, %f386, %f393;
	fma.rn.f32 	%f395, %f392, %f392, %f394;
	sqrt.rn.f32 	%f396, %f395;
	rcp.rn.f32 	%f397, %f396;
	mul.f32 	%f1489, %f397, %f392;
	mul.f32 	%f1488, %f397, %f389;
	mul.f32 	%f1487, %f386, %f397;

$L__BB0_4:
	ld.const.v2.u32 	{%r70, %r71}, [params];
	add.s32 	%r6, %r70, %r62;
	add.s32 	%r7, %r71, %r63;
	setp.eq.f32 	%p12, %f1487, 0f00000000;
	setp.eq.f32 	%p13, %f1488, 0f00000000;
	and.pred  	%p14, %p12, %p13;
	setp.eq.f32 	%p15, %f1489, 0f00000000;
	and.pred  	%p16, %p15, %p14;
	@%p16 bra 	$L__BB0_160;
	bra.uni 	$L__BB0_5;

$L__BB0_160:
	ld.const.u32 	%r59, [params+104];
	and.b32  	%r432, %r59, 1;
	setp.eq.b32 	%p188, %r432, 1;
	mov.pred 	%p189, 0;
	xor.pred  	%p190, %p188, %p189;
	not.pred 	%p191, %p190;
	@%p191 bra 	$L__BB0_162;

	ld.const.u64 	%rd97, [params+144];
	cvta.to.global.u64 	%rd98, %rd97;
	ld.const.u32 	%r433, [params+136];
	mad.lo.s32 	%r434, %r433, %r7, %r6;
	mul.wide.u32 	%rd99, %r434, 4;
	add.s64 	%rd100, %rd98, %rd99;
	mov.u16 	%rs97, 0;
	st.global.v4.u8 	[%rd100], {%rs97, %rs97, %rs97, %rs97};

$L__BB0_162:
	and.b32  	%r435, %r59, 8;
	setp.eq.s32 	%p192, %r435, 0;
	@%p192 bra 	$L__BB0_164;

	ld.const.u64 	%rd101, [params+192];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r436, [params+184];
	mad.lo.s32 	%r437, %r436, %r7, %r6;
	mov.f32 	%f1433, 0f00000000;
	cvt.rzi.u32.f32 	%r438, %f1433;
	mul.wide.u32 	%rd103, %r437, 2;
	add.s64 	%rd104, %rd102, %rd103;
	mov.u16 	%rs98, 0;
	cvt.u16.u32 	%rs99, %r438;
	st.global.v2.u8 	[%rd104], {%rs99, %rs98};

$L__BB0_164:
	and.b32  	%r439, %r59, 4;
	setp.eq.s32 	%p193, %r439, 0;
	ld.const.u32 	%r468, [params+108];
	@%p193 bra 	$L__BB0_168;

	setp.eq.s32 	%p194, %r468, 0;
	ld.const.u64 	%rd105, [params+224];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r440, [params+216];
	mad.lo.s32 	%r441, %r440, %r7, %r6;
	mul.wide.u32 	%rd107, %r441, 8;
	add.s64 	%rd28, %rd106, %rd107;
	@%p194 bra 	$L__BB0_167;

	ld.global.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1434, %rs106;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1435, %rs107;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1436, %rs108;}

	// end inline asm
	add.f32 	%f1437, %f1434, 0f00000000;
	add.f32 	%f1438, %f1435, 0f00000000;
	add.f32 	%f1439, %f1436, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1439;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f1438;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f1437;}

	// end inline asm
	mov.u16 	%rs110, 0;
	st.global.v4.u16 	[%rd28], {%rs103, %rs104, %rs105, %rs110};
	bra.uni 	$L__BB0_168;

$L__BB0_5:
	ld.const.u64 	%rd37, [params+432];
	cvta.to.global.u64 	%rd38, %rd37;
	ld.const.u32 	%r75, [params+424];
	mad.lo.s32 	%r76, %r75, %r63, %r62;
	mul.wide.u32 	%rd39, %r76, 12;
	add.s64 	%rd40, %rd38, %rd39;
	ld.global.f32 	%f10, [%rd40];
	mul.f32 	%f414, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd40+4];
	mul.f32 	%f415, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd40+8];
	mul.f32 	%f416, %f12, 0f3456BF95;
	abs.f32 	%f13, %f1487;
	div.rn.f32 	%f417, %f414, %f13;
	abs.f32 	%f418, %f1488;
	div.rn.f32 	%f419, %f415, %f418;
	abs.f32 	%f14, %f1489;
	div.rn.f32 	%f420, %f416, %f14;
	abs.f32 	%f421, %f417;
	abs.f32 	%f422, %f419;
	abs.f32 	%f423, %f420;
	mov.f32 	%f424, 0f38D1B717;
	max.f32 	%f425, %f421, %f424;
	max.f32 	%f426, %f422, %f424;
	max.f32 	%f427, %f423, %f424;
	fma.rn.f32 	%f15, %f1487, %f425, %f10;
	fma.rn.f32 	%f16, %f1488, %f426, %f11;
	fma.rn.f32 	%f17, %f1489, %f427, %f12;
	ld.const.u64 	%rd41, [params+128];
	cvta.to.global.u64 	%rd42, %rd41;
	ld.const.u32 	%r77, [params+120];
	mad.lo.s32 	%r78, %r77, %r63, %r62;
	mul.wide.u32 	%rd43, %r78, 4;
	add.s64 	%rd44, %rd42, %rd43;
	ld.global.u32 	%r459, [%rd44];
	setp.lt.s32 	%p18, %r4, 1;
	mov.pred 	%p17, 0;
	mov.u32 	%r455, 0;
	mov.f32 	%f1509, 0f00000000;
	mov.f32 	%f1510, %f1509;
	mov.f32 	%f1511, %f1509;
	mov.f32 	%f1512, %f1509;
	mov.f32 	%f1513, %f1509;
	mov.f32 	%f1514, %f1509;
	mov.f32 	%f1515, %f1509;
	mov.f32 	%f1516, %f1509;
	mov.f32 	%f1517, %f1509;
	mov.f32 	%f1518, %f1509;
	mov.f32 	%f1519, %f1509;
	mov.f32 	%f1520, %f1509;
	mov.f32 	%f1521, %f1509;
	mov.f32 	%f1522, %f1509;
	mov.f32 	%f1523, %f1509;
	mov.f32 	%f1524, %f1509;
	mov.pred 	%p199, %p17;
	@%p18 bra 	$L__BB0_25;

	ld.const.f32 	%f18, [params+620];
	ld.const.u64 	%rd45, [params+624];
	cvta.to.global.u64 	%rd3, %rd45;
	ld.const.u64 	%rd46, [params+640];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r81, [params+632];
	and.b32  	%r82, %r63, 255;
	and.b32  	%r83, %r62, 255;
	mad.lo.s32 	%r84, %r81, %r82, %r83;
	mul.wide.u32 	%rd48, %r84, 3;
	add.s64 	%rd4, %rd47, %rd48;
	ld.const.f32 	%f19, [params+660];
	mul.f32 	%f20, %f15, 0f3456BF95;
	mul.f32 	%f21, %f16, 0f3456BF95;
	mul.f32 	%f22, %f17, 0f3456BF95;
	ld.const.u64 	%rd5, [params+96];
	abs.f32 	%f571, %f21;
	abs.f32 	%f572, %f20;
	max.f32 	%f573, %f572, %f571;
	abs.f32 	%f574, %f22;
	max.f32 	%f575, %f573, %f574;
	mov.u32 	%r452, %r455;

$L__BB0_7:
	mul.lo.s32 	%r85, %r452, 3;
	mul.wide.s32 	%rd49, %r85, 12;
	add.s64 	%rd6, %rd3, %rd49;
	ld.global.f32 	%f444, [%rd6];
	sub.f32 	%f445, %f444, %f10;
	ld.global.f32 	%f446, [%rd6+4];
	sub.f32 	%f447, %f446, %f11;
	ld.global.f32 	%f448, [%rd6+8];
	sub.f32 	%f449, %f448, %f12;
	mul.f32 	%f450, %f447, %f447;
	fma.rn.f32 	%f451, %f445, %f445, %f450;
	fma.rn.f32 	%f452, %f449, %f449, %f451;
	sqrt.rn.f32 	%f39, %f452;
	rcp.rn.f32 	%f453, %f39;
	mul.f32 	%f40, %f445, %f453;
	mul.f32 	%f41, %f447, %f453;
	mul.f32 	%f42, %f449, %f453;
	mul.f32 	%f454, %f1488, %f41;
	fma.rn.f32 	%f455, %f1487, %f40, %f454;
	fma.rn.f32 	%f43, %f1489, %f42, %f455;
	setp.leu.f32 	%p19, %f43, 0f00000000;
	@%p19 bra 	$L__BB0_24;

	setp.ne.s32 	%p21, %r5, 0;
	mul.f32 	%f456, %f39, %f39;
	div.rn.f32 	%f44, %f18, %f456;
	ld.global.u8 	%rs15, [%rd4];
	cvt.rn.f32.u16 	%f457, %rs15;
	div.rn.f32 	%f458, %f457, 0fC37F0000;
	fma.rn.f32 	%f459, %f458, 0f3F333333, 0f3F800000;
	setp.gt.f32 	%p22, %f44, %f459;
	and.pred  	%p23, %p21, %p22;
	mov.pred 	%p199, -1;
	@%p23 bra 	$L__BB0_25;

	mul.f32 	%f45, %f39, %f19;
	mov.f32 	%f464, 0f40800000;
	abs.f32 	%f47, %f45;
	setp.lt.f32 	%p24, %f47, 0f00800000;
	mul.f32 	%f466, %f47, 0f4B800000;
	selp.f32 	%f467, %f466, %f47, %p24;
	selp.f32 	%f468, 0fC3170000, 0fC2FE0000, %p24;
	mov.b32 	%r86, %f467;
	and.b32  	%r87, %r86, 8388607;
	or.b32  	%r88, %r87, 1065353216;
	mov.b32 	%f469, %r88;
	shr.u32 	%r89, %r86, 23;
	cvt.rn.f32.u32 	%f470, %r89;
	add.f32 	%f471, %f468, %f470;
	setp.gt.f32 	%p25, %f469, 0f3FB504F3;
	mul.f32 	%f472, %f469, 0f3F000000;
	add.f32 	%f473, %f471, 0f3F800000;
	selp.f32 	%f474, %f473, %f471, %p25;
	selp.f32 	%f475, %f472, %f469, %p25;
	add.f32 	%f476, %f475, 0fBF800000;
	add.f32 	%f477, %f475, 0f3F800000;
	rcp.approx.ftz.f32 	%f478, %f477;
	add.f32 	%f479, %f476, %f476;
	mul.f32 	%f480, %f479, %f478;
	mul.f32 	%f481, %f480, %f480;
	mov.f32 	%f482, 0f3C4CAF63;
	mov.f32 	%f483, 0f3B18F0FE;
	fma.rn.f32 	%f484, %f483, %f481, %f482;
	mov.f32 	%f485, 0f3DAAAABD;
	fma.rn.f32 	%f486, %f484, %f481, %f485;
	mul.rn.f32 	%f487, %f486, %f481;
	mul.rn.f32 	%f488, %f487, %f480;
	sub.f32 	%f489, %f476, %f480;
	add.f32 	%f490, %f489, %f489;
	neg.f32 	%f491, %f480;
	fma.rn.f32 	%f492, %f491, %f476, %f490;
	mul.rn.f32 	%f493, %f478, %f492;
	add.f32 	%f494, %f488, %f480;
	sub.f32 	%f495, %f480, %f494;
	add.f32 	%f496, %f488, %f495;
	add.f32 	%f497, %f493, %f496;
	add.f32 	%f498, %f494, %f497;
	sub.f32 	%f499, %f494, %f498;
	add.f32 	%f500, %f497, %f499;
	mov.f32 	%f501, 0f3F317200;
	mul.rn.f32 	%f502, %f474, %f501;
	mov.f32 	%f503, 0f35BFBE8E;
	mul.rn.f32 	%f504, %f474, %f503;
	add.f32 	%f505, %f502, %f498;
	sub.f32 	%f506, %f502, %f505;
	add.f32 	%f507, %f498, %f506;
	add.f32 	%f508, %f500, %f507;
	add.f32 	%f509, %f504, %f508;
	add.f32 	%f510, %f505, %f509;
	sub.f32 	%f511, %f505, %f510;
	add.f32 	%f512, %f509, %f511;
	mul.rn.f32 	%f513, %f464, %f510;
	neg.f32 	%f514, %f513;
	fma.rn.f32 	%f515, %f464, %f510, %f514;
	fma.rn.f32 	%f516, %f464, %f512, %f515;
	mov.f32 	%f517, 0f00000000;
	fma.rn.f32 	%f518, %f517, %f510, %f516;
	add.rn.f32 	%f519, %f513, %f518;
	neg.f32 	%f520, %f519;
	add.rn.f32 	%f521, %f513, %f520;
	add.rn.f32 	%f522, %f521, %f518;
	mov.b32 	%r90, %f519;
	setp.eq.s32 	%p26, %r90, 1118925336;
	add.s32 	%r91, %r90, -1;
	mov.b32 	%f523, %r91;
	add.f32 	%f524, %f522, 0f37000000;
	selp.f32 	%f48, %f524, %f522, %p26;
	selp.f32 	%f525, %f523, %f519, %p26;
	mov.f32 	%f526, 0f3FB8AA3B;
	mul.rn.f32 	%f527, %f525, %f526;
	cvt.rzi.f32.f32 	%f528, %f527;
	abs.f32 	%f529, %f528;
	setp.gt.f32 	%p27, %f529, 0f42FC0000;
	mov.b32 	%r92, %f528;
	and.b32  	%r93, %r92, -2147483648;
	or.b32  	%r94, %r93, 1123811328;
	mov.b32 	%f530, %r94;
	selp.f32 	%f531, %f530, %f528, %p27;
	mov.f32 	%f532, 0fBF317218;
	fma.rn.f32 	%f533, %f531, %f532, %f525;
	mov.f32 	%f534, 0f3102E308;
	fma.rn.f32 	%f535, %f531, %f534, %f533;
	mul.f32 	%f536, %f535, 0f3FB8AA3B;
	add.f32 	%f537, %f531, 0f4B40007F;
	mov.b32 	%r95, %f537;
	shl.b32 	%r96, %r95, 23;
	mov.b32 	%f538, %r96;
	ex2.approx.ftz.f32 	%f539, %f536;
	mul.f32 	%f49, %f539, %f538;
	setp.eq.f32 	%p28, %f49, 0f7F800000;
	mov.f32 	%f1506, 0f7F800000;
	@%p28 bra 	$L__BB0_11;

	fma.rn.f32 	%f1506, %f49, %f48, %f49;

$L__BB0_11:
	mov.f32 	%f1484, 0f40000000;
	cvt.rzi.f32.f32 	%f1483, %f1484;
	add.f32 	%f1482, %f1483, %f1483;
	mov.f32 	%f1481, 0f40800000;
	sub.f32 	%f1480, %f1481, %f1482;
	abs.f32 	%f1479, %f1480;
	setp.lt.f32 	%p29, %f45, 0f00000000;
	setp.eq.f32 	%p30, %f1479, 0f3F800000;
	and.pred  	%p1, %p29, %p30;
	setp.eq.f32 	%p31, %f45, 0f00000000;
	@%p31 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_12;

$L__BB0_15:
	add.f32 	%f544, %f45, %f45;
	selp.f32 	%f1508, %f544, 0f00000000, %p30;
	bra.uni 	$L__BB0_16;

$L__BB0_12:
	mov.b32 	%r97, %f1506;
	xor.b32  	%r98, %r97, -2147483648;
	mov.b32 	%f540, %r98;
	selp.f32 	%f1508, %f540, %f1506, %p1;
	setp.geu.f32 	%p32, %f45, 0f00000000;
	@%p32 bra 	$L__BB0_16;

	mov.f32 	%f541, 0f40800000;
	cvt.rzi.f32.f32 	%f542, %f541;
	setp.eq.f32 	%p33, %f542, 0f40800000;
	@%p33 bra 	$L__BB0_16;

	mov.f32 	%f1508, 0f7FFFFFFF;

$L__BB0_16:
	add.f32 	%f545, %f47, 0f40800000;
	mov.b32 	%r99, %f545;
	setp.lt.s32 	%p35, %r99, 2139095040;
	@%p35 bra 	$L__BB0_21;

	setp.gtu.f32 	%p36, %f47, 0f7F800000;
	@%p36 bra 	$L__BB0_20;
	bra.uni 	$L__BB0_18;

$L__BB0_20:
	add.f32 	%f1508, %f45, 0f40800000;
	bra.uni 	$L__BB0_21;

$L__BB0_18:
	setp.neu.f32 	%p37, %f47, 0f7F800000;
	@%p37 bra 	$L__BB0_21;

	selp.f32 	%f1508, 0fFF800000, 0f7F800000, %p1;

$L__BB0_21:
	mov.f32 	%f546, 0f3F800000;
	sub.f32 	%f547, %f546, %f1508;
	setp.eq.f32 	%p38, %f45, 0f3F800000;
	selp.f32 	%f548, 0f00000000, %f547, %p38;
	cvt.sat.f32.f32 	%f549, %f548;
	mul.f32 	%f550, %f44, %f549;
	ld.global.f32 	%f551, [%rd6+12];
	mul.f32 	%f552, %f40, %f551;
	ld.global.f32 	%f553, [%rd6+16];
	mul.f32 	%f554, %f41, %f553;
	neg.f32 	%f555, %f554;
	sub.f32 	%f556, %f555, %f552;
	ld.global.f32 	%f557, [%rd6+20];
	mul.f32 	%f558, %f42, %f557;
	sub.f32 	%f559, %f556, %f558;
	cvt.sat.f32.f32 	%f560, %f559;
	mul.f32 	%f58, %f550, %f560;
	setp.leu.f32 	%p39, %f58, 0f3727C5AC;
	@%p39 bra 	$L__BB0_23;

	cvt.sat.f32.f32 	%f570, %f43;
	mov.f32 	%f576, 0f38D1B717;
	max.f32 	%f567, %f575, %f576;
	sub.f32 	%f568, %f39, %f567;
	mov.f32 	%f569, 0f00000000;
	mov.u32 	%r136, 2;
	mov.u32 	%r137, 1;
	mov.u32 	%r138, 3;
	mov.u32 	%r141, 1065353216;
	mov.u32 	%r170, 0;
	// begin inline asm
	call(%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128,%r129,%r130,%r131),_optix_trace_typed_32,(%r170,%rd5,%f15,%f16,%f17,%f40,%f41,%f42,%f567,%f568,%f569,%r137,%r170,%r137,%r136,%r137,%r138,%r141,%r141,%r141,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170,%r170);
	// end inline asm
	mov.b32 	%f577, %r100;
	mov.b32 	%f578, %r101;
	mov.b32 	%f579, %r102;
	ld.global.f32 	%f580, [%rd6+24];
	mul.f32 	%f581, %f580, %f577;
	ld.global.f32 	%f582, [%rd6+28];
	mul.f32 	%f583, %f582, %f578;
	ld.global.f32 	%f584, [%rd6+32];
	mul.f32 	%f585, %f584, %f579;
	mul.f32 	%f586, %f58, 0f3EA2F983;
	mul.f32 	%f587, %f586, %f581;
	mul.f32 	%f588, %f586, %f583;
	mul.f32 	%f589, %f586, %f585;
	fma.rn.f32 	%f1521, %f570, %f587, %f1521;
	fma.rn.f32 	%f1522, %f570, %f588, %f1522;
	fma.rn.f32 	%f1523, %f570, %f589, %f1523;
	mul.f32 	%f590, %f43, 0f40800000;
	cvt.sat.f32.f32 	%f591, %f590;
	mul.f32 	%f592, %f587, %f591;
	mul.f32 	%f593, %f588, %f591;
	mul.f32 	%f594, %f591, %f589;
	fma.rn.f32 	%f1515, %f40, %f592, %f1515;
	fma.rn.f32 	%f1516, %f40, %f593, %f1516;
	fma.rn.f32 	%f1517, %f40, %f594, %f1517;
	fma.rn.f32 	%f1512, %f41, %f592, %f1512;
	fma.rn.f32 	%f1513, %f41, %f593, %f1513;
	fma.rn.f32 	%f1514, %f41, %f594, %f1514;
	fma.rn.f32 	%f1509, %f42, %f592, %f1509;
	fma.rn.f32 	%f1510, %f42, %f593, %f1510;
	fma.rn.f32 	%f1511, %f42, %f594, %f1511;
	add.f32 	%f1518, %f1518, %f592;
	add.f32 	%f1519, %f1519, %f593;
	add.f32 	%f1520, %f1520, %f594;
	add.f32 	%f1524, %f1524, %f577;

$L__BB0_23:
	add.s32 	%r455, %r455, 1;

$L__BB0_24:
	add.s32 	%r452, %r452, 1;
	setp.lt.s32 	%p41, %r452, %r4;
	mov.pred 	%p199, %p17;
	@%p41 bra 	$L__BB0_7;

$L__BB0_25:
	cvt.rn.f32.s32 	%f595, %r455;
	mov.f32 	%f596, 0f3F800000;
	max.f32 	%f597, %f595, %f596;
	rcp.rn.f32 	%f598, %f597;
	mul.f32 	%f1620, %f1521, %f598;
	mul.f32 	%f1621, %f1522, %f598;
	mul.f32 	%f1622, %f1523, %f598;
	div.rn.f32 	%f1623, %f1524, %f597;
	mul.f32 	%f1617, %f1518, %f598;
	mul.f32 	%f1618, %f1519, %f598;
	mul.f32 	%f1619, %f1520, %f598;
	mul.f32 	%f1614, %f1515, %f598;
	mul.f32 	%f1615, %f1516, %f598;
	mul.f32 	%f1616, %f1517, %f598;
	mul.f32 	%f1611, %f1512, %f598;
	mul.f32 	%f1612, %f1513, %f598;
	mul.f32 	%f1613, %f1514, %f598;
	mul.f32 	%f1608, %f1509, %f598;
	mul.f32 	%f1609, %f1510, %f598;
	mul.f32 	%f1610, %f1511, %f598;
	not.pred 	%p42, %p199;
	@%p42 bra 	$L__BB0_56;

	abs.f32 	%f1486, %f1489;
	abs.f32 	%f1485, %f1487;
	setp.gt.f32 	%p43, %f1485, %f1486;
	selp.f32 	%f614, 0f00000000, %f1488, %p43;
	mov.f32 	%f613, 0f00000000;
	neg.f32 	%f615, %f1489;
	selp.f32 	%f616, %f1487, %f615, %p43;
	neg.f32 	%f617, %f1488;
	selp.f32 	%f618, %f617, 0f00000000, %p43;
	mul.f32 	%f619, %f616, %f616;
	fma.rn.f32 	%f620, %f618, %f618, %f619;
	fma.rn.f32 	%f621, %f614, %f614, %f620;
	sqrt.rn.f32 	%f622, %f621;
	rcp.rn.f32 	%f623, %f622;
	mul.f32 	%f139, %f618, %f623;
	mul.f32 	%f140, %f616, %f623;
	mul.f32 	%f141, %f614, %f623;
	setp.lt.s32 	%p44, %r5, 1;
	mov.f32 	%f1586, %f613;
	mov.f32 	%f1585, %f613;
	mov.f32 	%f1584, %f613;
	mov.f32 	%f1583, %f613;
	mov.f32 	%f1582, %f613;
	mov.f32 	%f1581, %f613;
	mov.f32 	%f1580, %f613;
	mov.f32 	%f1579, %f613;
	mov.f32 	%f1578, %f613;
	mov.f32 	%f1577, %f613;
	mov.f32 	%f1576, %f613;
	mov.f32 	%f1575, %f613;
	mov.f32 	%f1574, %f613;
	mov.f32 	%f1573, %f613;
	mov.f32 	%f1572, %f613;
	@%p44 bra 	$L__BB0_55;

	cvt.rn.f32.s32 	%f639, %r5;
	rcp.rn.f32 	%f142, %f639;
	mul.f32 	%f143, %f15, 0f3456BF95;
	mul.f32 	%f144, %f16, 0f3456BF95;
	mul.f32 	%f145, %f17, 0f3456BF95;
	ld.const.u64 	%rd7, [params+96];
	mul.f32 	%f640, %f1487, %f140;
	mul.f32 	%f641, %f1488, %f139;
	sub.f32 	%f146, %f641, %f640;
	mul.f32 	%f642, %f1489, %f139;
	mul.f32 	%f643, %f1487, %f141;
	sub.f32 	%f147, %f643, %f642;
	mul.f32 	%f644, %f1488, %f141;
	mul.f32 	%f645, %f1489, %f140;
	sub.f32 	%f148, %f645, %f644;
	mov.u32 	%r171, 0;
	add.s64 	%rd8, %rd1, 24;
	mov.u64 	%rd51, __cudart_i2opi_f;
	abs.f32 	%f708, %f144;
	abs.f32 	%f709, %f143;
	max.f32 	%f710, %f709, %f708;
	abs.f32 	%f711, %f145;
	max.f32 	%f712, %f710, %f711;
	mov.u32 	%r456, %r171;

$L__BB0_28:
	cvt.rn.f32.s32 	%f164, %r456;
	mov.u32 	%r458, %r171;

$L__BB0_29:
	mad.lo.s32 	%r173, %r459, 1664525, 1013904223;
	and.b32  	%r174, %r173, 16777215;
	cvt.rn.f32.u32 	%f646, %r174;
	fma.rn.f32 	%f647, %f646, 0f33800000, %f164;
	mul.f32 	%f180, %f142, %f647;
	mad.lo.s32 	%r459, %r173, 1664525, 1013904223;
	and.b32  	%r175, %r459, 16777215;
	cvt.rn.f32.u32 	%f648, %r175;
	cvt.rn.f32.s32 	%f649, %r458;
	fma.rn.f32 	%f650, %f648, 0f33800000, %f649;
	mul.f32 	%f651, %f142, %f650;
	mul.f32 	%f652, %f180, %f180;
	mov.f32 	%f653, 0f3F800000;
	sub.f32 	%f654, %f653, %f652;
	mov.f32 	%f655, 0f00000000;
	max.f32 	%f656, %f655, %f654;
	sqrt.rn.f32 	%f181, %f656;
	mul.f32 	%f182, %f651, 0f40C90FDB;
	mul.f32 	%f657, %f182, 0f3F22F983;
	cvt.rni.s32.f32 	%r466, %f657;
	cvt.rn.f32.s32 	%f658, %r466;
	mov.f32 	%f659, 0fBFC90FDA;
	fma.rn.f32 	%f660, %f658, %f659, %f182;
	mov.f32 	%f661, 0fB3A22168;
	fma.rn.f32 	%f662, %f658, %f661, %f660;
	mov.f32 	%f663, 0fA7C234C5;
	fma.rn.f32 	%f1590, %f658, %f663, %f662;
	abs.f32 	%f184, %f182;
	setp.ltu.f32 	%p45, %f184, 0f47CE4780;
	mov.u32 	%r463, %r466;
	mov.f32 	%f1587, %f1590;
	@%p45 bra 	$L__BB0_37;

	setp.eq.f32 	%p46, %f184, 0f7F800000;
	@%p46 bra 	$L__BB0_36;
	bra.uni 	$L__BB0_31;

$L__BB0_36:
	mov.f32 	%f666, 0f00000000;
	mul.rn.f32 	%f1587, %f182, %f666;
	mov.u32 	%r463, 0;
	bra.uni 	$L__BB0_37;

$L__BB0_31:
	mov.b32 	%r21, %f182;
	bfe.u32 	%r177, %r21, 23, 8;
	add.s32 	%r22, %r177, -128;
	shl.b32 	%r178, %r21, 8;
	or.b32  	%r23, %r178, -2147483648;
	shr.u32 	%r24, %r22, 5;
	mov.u64 	%rd122, 0;
	mov.u32 	%r460, 0;
	mov.u64 	%rd120, %rd1;
	mov.u64 	%rd121, %rd51;

$L__BB0_32:
	.pragma "nounroll";
	ld.global.nc.u32 	%r179, [%rd121];
	mad.wide.u32 	%rd53, %r179, %r23, %rd122;
	shr.u64 	%rd122, %rd53, 32;
	st.local.u32 	[%rd120], %rd53;
	add.s64 	%rd121, %rd121, 4;
	add.s64 	%rd120, %rd120, 4;
	add.s32 	%r460, %r460, 1;
	setp.ne.s32 	%p47, %r460, 6;
	@%p47 bra 	$L__BB0_32;

	st.local.u32 	[%rd8], %rd122;
	mov.u32 	%r180, 4;
	sub.s32 	%r27, %r180, %r24;
	mov.u32 	%r181, 6;
	sub.s32 	%r182, %r181, %r24;
	mul.wide.s32 	%rd54, %r182, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r461, [%rd55];
	ld.local.u32 	%r462, [%rd55+-4];
	and.b32  	%r30, %r22, 31;
	setp.eq.s32 	%p48, %r30, 0;
	@%p48 bra 	$L__BB0_35;

	mov.u32 	%r183, 32;
	sub.s32 	%r184, %r183, %r30;
	shr.u32 	%r185, %r462, %r184;
	shl.b32 	%r186, %r461, %r30;
	add.s32 	%r461, %r185, %r186;
	mul.wide.s32 	%rd56, %r27, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r187, [%rd57];
	shr.u32 	%r188, %r187, %r184;
	shl.b32 	%r189, %r462, %r30;
	add.s32 	%r462, %r188, %r189;

$L__BB0_35:
	and.b32  	%r190, %r21, -2147483648;
	shr.u32 	%r191, %r462, 30;
	shl.b32 	%r192, %r461, 2;
	or.b32  	%r193, %r191, %r192;
	shr.u32 	%r194, %r193, 31;
	shr.u32 	%r195, %r461, 30;
	add.s32 	%r196, %r194, %r195;
	neg.s32 	%r197, %r196;
	setp.eq.s32 	%p49, %r190, 0;
	selp.b32 	%r463, %r196, %r197, %p49;
	setp.ne.s32 	%p50, %r194, 0;
	xor.b32  	%r198, %r190, -2147483648;
	selp.b32 	%r199, %r198, %r190, %p50;
	selp.b32 	%r200, -1, 0, %p50;
	xor.b32  	%r201, %r193, %r200;
	shl.b32 	%r202, %r462, 2;
	xor.b32  	%r203, %r202, %r200;
	cvt.u64.u32 	%rd58, %r201;
	cvt.u64.u32 	%rd59, %r203;
	bfi.b64 	%rd60, %rd58, %rd59, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd60;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f664, %fd2;
	setp.eq.s32 	%p51, %r199, 0;
	neg.f32 	%f665, %f664;
	selp.f32 	%f1587, %f664, %f665, %p51;

$L__BB0_37:
	add.s32 	%r37, %r463, 1;
	and.b32  	%r38, %r37, 1;
	setp.eq.s32 	%p52, %r38, 0;
	selp.f32 	%f188, %f1587, 0f3F800000, %p52;
	mul.rn.f32 	%f189, %f1587, %f1587;
	mov.f32 	%f1588, 0fB94D4153;
	@%p52 bra 	$L__BB0_39;

	mov.f32 	%f668, 0fBAB607ED;
	mov.f32 	%f669, 0f37CBAC00;
	fma.rn.f32 	%f1588, %f669, %f189, %f668;

$L__BB0_39:
	selp.f32 	%f670, 0f3C0885E4, 0f3D2AAABB, %p52;
	fma.rn.f32 	%f671, %f1588, %f189, %f670;
	selp.f32 	%f672, 0fBE2AAAA8, 0fBEFFFFFF, %p52;
	fma.rn.f32 	%f673, %f671, %f189, %f672;
	mov.f32 	%f674, 0f00000000;
	fma.rn.f32 	%f675, %f189, %f188, %f674;
	fma.rn.f32 	%f1589, %f673, %f675, %f188;
	and.b32  	%r205, %r37, 2;
	setp.eq.s32 	%p54, %r205, 0;
	@%p54 bra 	$L__BB0_41;

	mov.f32 	%f677, 0fBF800000;
	fma.rn.f32 	%f1589, %f1589, %f677, %f674;

$L__BB0_41:
	@%p45 bra 	$L__BB0_49;

	setp.eq.f32 	%p56, %f184, 0f7F800000;
	@%p56 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_43;

$L__BB0_48:
	mov.f32 	%f680, 0f00000000;
	mul.rn.f32 	%f1590, %f182, %f680;
	mov.u32 	%r466, 0;
	bra.uni 	$L__BB0_49;

$L__BB0_43:
	mov.b32 	%r39, %f182;
	bfe.u32 	%r206, %r39, 23, 8;
	add.s32 	%r40, %r206, -128;
	shl.b32 	%r207, %r39, 8;
	or.b32  	%r41, %r207, -2147483648;
	shr.u32 	%r42, %r40, 5;
	mov.u64 	%rd123, 0;
	mov.u64 	%rd124, %rd123;

$L__BB0_44:
	.pragma "nounroll";
	shl.b64 	%rd63, %rd123, 2;
	mov.u64 	%rd64, __cudart_i2opi_f;
	add.s64 	%rd65, %rd64, %rd63;
	ld.global.nc.u32 	%r208, [%rd65];
	mad.wide.u32 	%rd66, %r208, %r41, %rd124;
	shr.u64 	%rd124, %rd66, 32;
	add.s64 	%rd67, %rd1, %rd63;
	st.local.u32 	[%rd67], %rd66;
	cvt.u32.u64 	%r209, %rd123;
	add.s32 	%r210, %r209, 1;
	cvt.s64.s32 	%rd123, %r210;
	setp.ne.s32 	%p57, %r210, 6;
	@%p57 bra 	$L__BB0_44;

	st.local.u32 	[%rd8], %rd124;
	mov.u32 	%r211, 4;
	sub.s32 	%r43, %r211, %r42;
	mov.u32 	%r212, 6;
	sub.s32 	%r213, %r212, %r42;
	mul.wide.s32 	%rd68, %r213, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r464, [%rd69];
	ld.local.u32 	%r465, [%rd69+-4];
	and.b32  	%r46, %r40, 31;
	setp.eq.s32 	%p58, %r46, 0;
	@%p58 bra 	$L__BB0_47;

	mov.u32 	%r214, 32;
	sub.s32 	%r215, %r214, %r46;
	shr.u32 	%r216, %r465, %r215;
	shl.b32 	%r217, %r464, %r46;
	add.s32 	%r464, %r216, %r217;
	mul.wide.s32 	%rd70, %r43, 4;
	add.s64 	%rd71, %rd1, %rd70;
	ld.local.u32 	%r218, [%rd71];
	shr.u32 	%r219, %r218, %r215;
	shl.b32 	%r220, %r465, %r46;
	add.s32 	%r465, %r219, %r220;

$L__BB0_47:
	and.b32  	%r221, %r39, -2147483648;
	shr.u32 	%r222, %r465, 30;
	shl.b32 	%r223, %r464, 2;
	or.b32  	%r224, %r222, %r223;
	shr.u32 	%r225, %r224, 31;
	shr.u32 	%r226, %r464, 30;
	add.s32 	%r227, %r225, %r226;
	neg.s32 	%r228, %r227;
	setp.eq.s32 	%p59, %r221, 0;
	selp.b32 	%r466, %r227, %r228, %p59;
	setp.ne.s32 	%p60, %r225, 0;
	xor.b32  	%r229, %r221, -2147483648;
	selp.b32 	%r230, %r229, %r221, %p60;
	selp.b32 	%r231, -1, 0, %p60;
	xor.b32  	%r232, %r224, %r231;
	shl.b32 	%r233, %r465, 2;
	xor.b32  	%r234, %r233, %r231;
	cvt.u64.u32 	%rd72, %r232;
	cvt.u64.u32 	%rd73, %r234;
	bfi.b64 	%rd74, %rd72, %rd73, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd74;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f678, %fd4;
	setp.eq.s32 	%p61, %r230, 0;
	neg.f32 	%f679, %f678;
	selp.f32 	%f1590, %f678, %f679, %p61;

$L__BB0_49:
	mul.f32 	%f198, %f181, %f1589;
	and.b32  	%r53, %r466, 1;
	setp.eq.s32 	%p62, %r53, 0;
	selp.f32 	%f199, %f1590, 0f3F800000, %p62;
	mul.rn.f32 	%f200, %f1590, %f1590;
	mov.f32 	%f1591, 0fB94D4153;
	@%p62 bra 	$L__BB0_51;

	mov.f32 	%f682, 0fBAB607ED;
	mov.f32 	%f683, 0f37CBAC00;
	fma.rn.f32 	%f1591, %f683, %f200, %f682;

$L__BB0_51:
	selp.f32 	%f684, 0f3C0885E4, 0f3D2AAABB, %p62;
	fma.rn.f32 	%f685, %f1591, %f200, %f684;
	selp.f32 	%f686, 0fBE2AAAA8, 0fBEFFFFFF, %p62;
	fma.rn.f32 	%f687, %f685, %f200, %f686;
	mov.f32 	%f688, 0f00000000;
	fma.rn.f32 	%f689, %f200, %f199, %f688;
	fma.rn.f32 	%f1592, %f687, %f689, %f199;
	and.b32  	%r236, %r466, 2;
	setp.eq.s32 	%p64, %r236, 0;
	@%p64 bra 	$L__BB0_53;

	mov.f32 	%f691, 0fBF800000;
	fma.rn.f32 	%f1592, %f1592, %f691, %f688;

$L__BB0_53:
	mul.f32 	%f701, %f181, %f1592;
	mul.f32 	%f702, %f139, %f701;
	mul.f32 	%f703, %f140, %f701;
	mul.f32 	%f704, %f141, %f701;
	fma.rn.f32 	%f705, %f148, %f198, %f702;
	fma.rn.f32 	%f706, %f147, %f198, %f703;
	fma.rn.f32 	%f707, %f146, %f198, %f704;
	fma.rn.f32 	%f695, %f1487, %f180, %f705;
	fma.rn.f32 	%f696, %f1488, %f180, %f706;
	fma.rn.f32 	%f697, %f1489, %f180, %f707;
	mov.f32 	%f713, 0f38D1B717;
	max.f32 	%f698, %f712, %f713;
	mov.f32 	%f699, 0f6C4ECB8F;
	mov.u32 	%r270, 1;
	mov.u32 	%r273, 2;
	mov.u32 	%r275, 4;
	mov.u32 	%r278, 1065353216;
	mov.u32 	%r279, 2139095039;
	mov.u32 	%r307, 0;
	// begin inline asm
	call(%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268),_optix_trace_typed_32,(%r307,%rd7,%f15,%f16,%f17,%f695,%f696,%f697,%f698,%f699,%f688,%r270,%r307,%r307,%r273,%r307,%r275,%r278,%r278,%r278,%r279,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307);
	// end inline asm
	mov.b32 	%f714, %r237;
	mov.b32 	%f715, %r238;
	mov.b32 	%f716, %r239;
	mov.b32 	%f717, %r240;
	max.f32 	%f718, %f714, %f688;
	max.f32 	%f719, %f715, %f688;
	max.f32 	%f720, %f716, %f688;
	setp.ltu.f32 	%p65, %f717, 0f00000000;
	selp.f32 	%f721, %f720, 0f00000000, %p65;
	selp.f32 	%f722, %f719, 0f00000000, %p65;
	selp.f32 	%f723, %f718, 0f00000000, %p65;
	fma.rn.f32 	%f1580, %f695, %f723, %f1580;
	fma.rn.f32 	%f1579, %f695, %f722, %f1579;
	fma.rn.f32 	%f1578, %f695, %f721, %f1578;
	fma.rn.f32 	%f1583, %f696, %f723, %f1583;
	fma.rn.f32 	%f1582, %f696, %f722, %f1582;
	fma.rn.f32 	%f1581, %f696, %f721, %f1581;
	fma.rn.f32 	%f1586, %f697, %f723, %f1586;
	fma.rn.f32 	%f1585, %f697, %f722, %f1585;
	fma.rn.f32 	%f1584, %f697, %f721, %f1584;
	add.f32 	%f1577, %f1577, %f723;
	add.f32 	%f1576, %f1576, %f722;
	add.f32 	%f1575, %f1575, %f721;
	mul.f32 	%f724, %f1488, %f696;
	fma.rn.f32 	%f725, %f1487, %f695, %f724;
	fma.rn.f32 	%f726, %f1489, %f697, %f725;
	cvt.sat.f32.f32 	%f727, %f726;
	fma.rn.f32 	%f1574, %f723, %f727, %f1574;
	fma.rn.f32 	%f1573, %f722, %f727, %f1573;
	fma.rn.f32 	%f1572, %f721, %f727, %f1572;
	add.s32 	%r458, %r458, 1;
	setp.lt.s32 	%p66, %r458, %r5;
	@%p66 bra 	$L__BB0_29;

	add.s32 	%r456, %r456, 1;
	setp.lt.s32 	%p67, %r456, %r5;
	@%p67 bra 	$L__BB0_28;

$L__BB0_55:
	mul.lo.s32 	%r308, %r5, %r5;
	cvt.rn.f32.s32 	%f728, %r308;
	rcp.rn.f32 	%f729, %f728;
	mul.f32 	%f730, %f729, %f1574;
	mul.f32 	%f731, %f729, %f1573;
	mul.f32 	%f732, %f729, %f1572;
	div.rn.f32 	%f1623, %f613, %f728;
	mul.f32 	%f1617, %f729, %f1577;
	mul.f32 	%f1618, %f729, %f1576;
	mul.f32 	%f1619, %f729, %f1575;
	mul.f32 	%f1614, %f729, %f1580;
	mul.f32 	%f1615, %f729, %f1579;
	mul.f32 	%f1616, %f729, %f1578;
	mul.f32 	%f1611, %f729, %f1583;
	mul.f32 	%f1612, %f729, %f1582;
	mul.f32 	%f1613, %f729, %f1581;
	mul.f32 	%f1608, %f729, %f1586;
	mul.f32 	%f1609, %f729, %f1585;
	mul.f32 	%f1610, %f729, %f1584;
	fma.rn.f32 	%f1620, %f729, %f1574, %f730;
	fma.rn.f32 	%f1621, %f729, %f1573, %f731;
	fma.rn.f32 	%f1622, %f729, %f1572, %f732;

$L__BB0_56:
	ld.const.u32 	%r451, [params+616];
	setp.lt.s32 	%p68, %r451, 0;
	selp.f32 	%f268, %f1620, %f1623, %p68;
	ld.const.u32 	%r56, [params+104];
	and.b32  	%r309, %r56, 8;
	setp.eq.s32 	%p69, %r309, 0;
	@%p69 bra 	$L__BB0_70;

	ld.const.u64 	%rd76, [params+192];
	cvta.to.global.u64 	%rd19, %rd76;
	ld.const.u32 	%r310, [params+184];
	mad.lo.s32 	%r311, %r310, %r7, %r6;
	cvt.u64.u32 	%rd20, %r311;
	mov.f32 	%f735, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f736, %f735;
	add.f32 	%f737, %f736, %f736;
	mov.f32 	%f738, 0f3EE8BA2E;
	sub.f32 	%f739, %f738, %f737;
	abs.f32 	%f269, %f739;
	abs.f32 	%f270, %f268;
	setp.lt.f32 	%p70, %f270, 0f00800000;
	mul.f32 	%f740, %f270, 0f4B800000;
	selp.f32 	%f741, %f740, %f270, %p70;
	selp.f32 	%f742, 0fC3170000, 0fC2FE0000, %p70;
	mov.b32 	%r312, %f741;
	and.b32  	%r313, %r312, 8388607;
	or.b32  	%r314, %r313, 1065353216;
	mov.b32 	%f743, %r314;
	shr.u32 	%r315, %r312, 23;
	cvt.rn.f32.u32 	%f744, %r315;
	add.f32 	%f745, %f742, %f744;
	setp.gt.f32 	%p71, %f743, 0f3FB504F3;
	mul.f32 	%f746, %f743, 0f3F000000;
	add.f32 	%f747, %f745, 0f3F800000;
	selp.f32 	%f748, %f747, %f745, %p71;
	selp.f32 	%f749, %f746, %f743, %p71;
	add.f32 	%f750, %f749, 0fBF800000;
	add.f32 	%f751, %f749, 0f3F800000;
	rcp.approx.ftz.f32 	%f752, %f751;
	add.f32 	%f753, %f750, %f750;
	mul.f32 	%f754, %f753, %f752;
	mul.f32 	%f755, %f754, %f754;
	mov.f32 	%f756, 0f3C4CAF63;
	mov.f32 	%f757, 0f3B18F0FE;
	fma.rn.f32 	%f758, %f757, %f755, %f756;
	mov.f32 	%f759, 0f3DAAAABD;
	fma.rn.f32 	%f760, %f758, %f755, %f759;
	mul.rn.f32 	%f761, %f760, %f755;
	mul.rn.f32 	%f762, %f761, %f754;
	sub.f32 	%f763, %f750, %f754;
	add.f32 	%f764, %f763, %f763;
	neg.f32 	%f765, %f754;
	fma.rn.f32 	%f766, %f765, %f750, %f764;
	mul.rn.f32 	%f767, %f752, %f766;
	add.f32 	%f768, %f762, %f754;
	sub.f32 	%f769, %f754, %f768;
	add.f32 	%f770, %f762, %f769;
	add.f32 	%f771, %f767, %f770;
	add.f32 	%f772, %f768, %f771;
	sub.f32 	%f773, %f768, %f772;
	add.f32 	%f774, %f771, %f773;
	mov.f32 	%f775, 0f3F317200;
	mul.rn.f32 	%f776, %f748, %f775;
	mov.f32 	%f777, 0f35BFBE8E;
	mul.rn.f32 	%f778, %f748, %f777;
	add.f32 	%f779, %f776, %f772;
	sub.f32 	%f780, %f776, %f779;
	add.f32 	%f781, %f772, %f780;
	add.f32 	%f782, %f774, %f781;
	add.f32 	%f783, %f778, %f782;
	add.f32 	%f784, %f779, %f783;
	sub.f32 	%f785, %f779, %f784;
	add.f32 	%f786, %f783, %f785;
	mul.rn.f32 	%f787, %f738, %f784;
	neg.f32 	%f788, %f787;
	fma.rn.f32 	%f789, %f738, %f784, %f788;
	fma.rn.f32 	%f790, %f738, %f786, %f789;
	mov.f32 	%f791, 0f00000000;
	fma.rn.f32 	%f792, %f791, %f784, %f790;
	add.rn.f32 	%f793, %f787, %f792;
	neg.f32 	%f794, %f793;
	add.rn.f32 	%f795, %f787, %f794;
	add.rn.f32 	%f796, %f795, %f792;
	mov.b32 	%r316, %f793;
	setp.eq.s32 	%p72, %r316, 1118925336;
	add.s32 	%r317, %r316, -1;
	mov.b32 	%f797, %r317;
	add.f32 	%f798, %f796, 0f37000000;
	selp.f32 	%f271, %f798, %f796, %p72;
	selp.f32 	%f799, %f797, %f793, %p72;
	mov.f32 	%f800, 0f3FB8AA3B;
	mul.rn.f32 	%f801, %f799, %f800;
	cvt.rzi.f32.f32 	%f802, %f801;
	abs.f32 	%f803, %f802;
	setp.gt.f32 	%p73, %f803, 0f42FC0000;
	mov.b32 	%r318, %f802;
	and.b32  	%r319, %r318, -2147483648;
	or.b32  	%r320, %r319, 1123811328;
	mov.b32 	%f804, %r320;
	selp.f32 	%f805, %f804, %f802, %p73;
	mov.f32 	%f806, 0fBF317218;
	fma.rn.f32 	%f807, %f805, %f806, %f799;
	mov.f32 	%f808, 0f3102E308;
	fma.rn.f32 	%f809, %f805, %f808, %f807;
	mul.f32 	%f810, %f809, 0f3FB8AA3B;
	add.f32 	%f811, %f805, 0f4B40007F;
	mov.b32 	%r321, %f811;
	shl.b32 	%r322, %r321, 23;
	mov.b32 	%f812, %r322;
	ex2.approx.ftz.f32 	%f813, %f810;
	mul.f32 	%f272, %f813, %f812;
	setp.eq.f32 	%p74, %f272, 0f7F800000;
	mov.f32 	%f1624, 0f7F800000;
	@%p74 bra 	$L__BB0_59;

	fma.rn.f32 	%f1624, %f272, %f271, %f272;

$L__BB0_59:
	setp.lt.f32 	%p75, %f268, 0f00000000;
	setp.eq.f32 	%p76, %f269, 0f3F800000;
	and.pred  	%p3, %p75, %p76;
	setp.eq.f32 	%p77, %f268, 0f00000000;
	@%p77 bra 	$L__BB0_63;
	bra.uni 	$L__BB0_60;

$L__BB0_63:
	add.f32 	%f818, %f268, %f268;
	selp.f32 	%f1626, %f818, 0f00000000, %p76;
	bra.uni 	$L__BB0_64;

$L__BB0_167:
	mov.f32 	%f1442, 0f00000000;
	mov.u32 	%r468, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1442;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1442;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs111, %f1442;}

	// end inline asm
	mov.u16 	%rs114, 0;
	st.global.v4.u16 	[%rd28], {%rs111, %rs112, %rs113, %rs114};

$L__BB0_168:
	ld.const.u64 	%rd108, [params+256];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r443, [params+248];
	mad.lo.s32 	%r444, %r443, %r7, %r6;
	mul.wide.u32 	%rd110, %r444, 8;
	add.s64 	%rd29, %rd109, %rd110;
	setp.eq.s32 	%p195, %r468, 0;
	@%p195 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs121, %rs122, %rs123, %rs124}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1443, %rs121;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1444, %rs122;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1445, %rs123;}

	// end inline asm
	add.f32 	%f1446, %f1443, 0f00000000;
	add.f32 	%f1447, %f1444, 0f00000000;
	add.f32 	%f1448, %f1445, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1448;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs119, %f1447;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs118, %f1446;}

	// end inline asm
	mov.u16 	%rs125, 0;
	st.global.v4.u16 	[%rd29], {%rs118, %rs119, %rs120, %rs125};
	bra.uni 	$L__BB0_171;

$L__BB0_170:
	mov.f32 	%f1451, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1451;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1451;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs126, %f1451;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd29], {%rs126, %rs127, %rs128, %rs129};

$L__BB0_171:
	ld.const.u64 	%rd111, [params+272];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r445, [params+264];
	mad.lo.s32 	%r446, %r445, %r7, %r6;
	mul.wide.u32 	%rd113, %r446, 8;
	add.s64 	%rd30, %rd112, %rd113;
	@%p195 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs136, %rs137, %rs138, %rs139}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1452, %rs136;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1453, %rs137;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1454, %rs138;}

	// end inline asm
	add.f32 	%f1455, %f1452, 0f00000000;
	add.f32 	%f1456, %f1453, 0f00000000;
	add.f32 	%f1457, %f1454, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1457;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs134, %f1456;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs133, %f1455;}

	// end inline asm
	mov.u16 	%rs140, 0;
	st.global.v4.u16 	[%rd30], {%rs133, %rs134, %rs135, %rs140};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1460, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1460;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1460;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs141, %f1460;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd30], {%rs141, %rs142, %rs143, %rs144};

$L__BB0_174:
	ld.const.u64 	%rd114, [params+288];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r447, [params+280];
	mad.lo.s32 	%r448, %r447, %r7, %r6;
	mul.wide.u32 	%rd116, %r448, 8;
	add.s64 	%rd31, %rd115, %rd116;
	@%p195 bra 	$L__BB0_176;

	ld.global.v4.u16 	{%rs151, %rs152, %rs153, %rs154}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1461, %rs151;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1462, %rs152;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1463, %rs153;}

	// end inline asm
	add.f32 	%f1464, %f1461, 0f00000000;
	add.f32 	%f1465, %f1462, 0f00000000;
	add.f32 	%f1466, %f1463, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1466;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs149, %f1465;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs148, %f1464;}

	// end inline asm
	mov.u16 	%rs155, 0;
	st.global.v4.u16 	[%rd31], {%rs148, %rs149, %rs150, %rs155};
	bra.uni 	$L__BB0_177;

$L__BB0_176:
	mov.f32 	%f1469, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1469;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1469;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs156, %f1469;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd31], {%rs156, %rs157, %rs158, %rs159};

$L__BB0_177:
	ld.const.u64 	%rd117, [params+304];
	cvta.to.global.u64 	%rd118, %rd117;
	ld.const.u32 	%r449, [params+296];
	mad.lo.s32 	%r450, %r449, %r7, %r6;
	mul.wide.u32 	%rd119, %r450, 8;
	add.s64 	%rd32, %rd118, %rd119;
	@%p195 bra 	$L__BB0_179;

	ld.global.v4.u16 	{%rs166, %rs167, %rs168, %rs169}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1470, %rs166;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1471, %rs167;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1472, %rs168;}

	// end inline asm
	add.f32 	%f1473, %f1470, 0f00000000;
	add.f32 	%f1474, %f1471, 0f00000000;
	add.f32 	%f1475, %f1472, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1475;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs164, %f1474;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs163, %f1473;}

	// end inline asm
	mov.u16 	%rs170, 0;
	st.global.v4.u16 	[%rd32], {%rs163, %rs164, %rs165, %rs170};
	bra.uni 	$L__BB0_180;

$L__BB0_179:
	mov.f32 	%f1478, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1478;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs172, %f1478;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs171, %f1478;}

	// end inline asm
	mov.u16 	%rs174, 0;
	st.global.v4.u16 	[%rd32], {%rs171, %rs172, %rs173, %rs174};
	bra.uni 	$L__BB0_180;

$L__BB0_60:
	mov.b32 	%r323, %f1624;
	xor.b32  	%r324, %r323, -2147483648;
	mov.b32 	%f814, %r324;
	selp.f32 	%f1626, %f814, %f1624, %p3;
	setp.geu.f32 	%p78, %f268, 0f00000000;
	@%p78 bra 	$L__BB0_64;

	mov.f32 	%f815, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f816, %f815;
	setp.eq.f32 	%p79, %f816, 0f3EE8BA2E;
	@%p79 bra 	$L__BB0_64;

	mov.f32 	%f1626, 0f7FFFFFFF;

$L__BB0_64:
	add.f32 	%f819, %f270, 0f3EE8BA2E;
	mov.b32 	%r325, %f819;
	setp.lt.s32 	%p81, %r325, 2139095040;
	@%p81 bra 	$L__BB0_69;

	setp.gtu.f32 	%p82, %f270, 0f7F800000;
	@%p82 bra 	$L__BB0_68;
	bra.uni 	$L__BB0_66;

$L__BB0_68:
	add.f32 	%f1626, %f268, 0f3EE8BA2E;
	bra.uni 	$L__BB0_69;

$L__BB0_66:
	setp.neu.f32 	%p83, %f270, 0f7F800000;
	@%p83 bra 	$L__BB0_69;

	selp.f32 	%f1626, 0fFF800000, 0f7F800000, %p3;

$L__BB0_69:
	mul.f32 	%f820, %f1626, 0f437F0000;
	setp.eq.f32 	%p84, %f268, 0f3F800000;
	selp.f32 	%f821, 0f437F0000, %f820, %p84;
	cvt.rzi.u32.f32 	%r326, %f821;
	shl.b64 	%rd77, %rd20, 1;
	add.s64 	%rd78, %rd19, %rd77;
	cvt.u16.u32 	%rs16, %r326;
	mov.u16 	%rs17, 255;
	st.global.v2.u8 	[%rd78], {%rs16, %rs17};

$L__BB0_70:
	ld.const.v2.f32 	{%f822, %f823}, [params+648];
	mul.f32 	%f283, %f1620, %f822;
	mul.f32 	%f284, %f1621, %f823;
	ld.const.f32 	%f285, [params+656];
	mul.f32 	%f286, %f1622, %f285;
	and.b32  	%r327, %r56, 1;
	setp.eq.b32 	%p85, %r327, 1;
	mov.pred 	%p86, 0;
	xor.pred  	%p87, %p85, %p86;
	not.pred 	%p88, %p87;
	@%p88 bra 	$L__BB0_144;

	mov.f32 	%f825, 0f3E666666;
	cvt.rzi.f32.f32 	%f826, %f825;
	add.f32 	%f827, %f826, %f826;
	mov.f32 	%f828, 0f3EE66666;
	sub.f32 	%f829, %f828, %f827;
	abs.f32 	%f287, %f829;
	abs.f32 	%f288, %f283;
	setp.lt.f32 	%p89, %f288, 0f00800000;
	mul.f32 	%f830, %f288, 0f4B800000;
	selp.f32 	%f831, %f830, %f288, %p89;
	selp.f32 	%f832, 0fC3170000, 0fC2FE0000, %p89;
	mov.b32 	%r328, %f831;
	and.b32  	%r329, %r328, 8388607;
	or.b32  	%r330, %r329, 1065353216;
	mov.b32 	%f833, %r330;
	shr.u32 	%r331, %r328, 23;
	cvt.rn.f32.u32 	%f834, %r331;
	add.f32 	%f835, %f832, %f834;
	setp.gt.f32 	%p90, %f833, 0f3FB504F3;
	mul.f32 	%f836, %f833, 0f3F000000;
	add.f32 	%f837, %f835, 0f3F800000;
	selp.f32 	%f838, %f837, %f835, %p90;
	selp.f32 	%f839, %f836, %f833, %p90;
	add.f32 	%f840, %f839, 0fBF800000;
	add.f32 	%f841, %f839, 0f3F800000;
	rcp.approx.ftz.f32 	%f842, %f841;
	add.f32 	%f843, %f840, %f840;
	mul.f32 	%f844, %f843, %f842;
	mul.f32 	%f845, %f844, %f844;
	mov.f32 	%f846, 0f3C4CAF63;
	mov.f32 	%f847, 0f3B18F0FE;
	fma.rn.f32 	%f848, %f847, %f845, %f846;
	mov.f32 	%f849, 0f3DAAAABD;
	fma.rn.f32 	%f850, %f848, %f845, %f849;
	mul.rn.f32 	%f851, %f850, %f845;
	mul.rn.f32 	%f852, %f851, %f844;
	sub.f32 	%f853, %f840, %f844;
	add.f32 	%f854, %f853, %f853;
	neg.f32 	%f855, %f844;
	fma.rn.f32 	%f856, %f855, %f840, %f854;
	mul.rn.f32 	%f857, %f842, %f856;
	add.f32 	%f858, %f852, %f844;
	sub.f32 	%f859, %f844, %f858;
	add.f32 	%f860, %f852, %f859;
	add.f32 	%f861, %f857, %f860;
	add.f32 	%f862, %f858, %f861;
	sub.f32 	%f863, %f858, %f862;
	add.f32 	%f864, %f861, %f863;
	mov.f32 	%f865, 0f3F317200;
	mul.rn.f32 	%f866, %f838, %f865;
	mov.f32 	%f867, 0f35BFBE8E;
	mul.rn.f32 	%f868, %f838, %f867;
	add.f32 	%f869, %f866, %f862;
	sub.f32 	%f870, %f866, %f869;
	add.f32 	%f871, %f862, %f870;
	add.f32 	%f872, %f864, %f871;
	add.f32 	%f873, %f868, %f872;
	add.f32 	%f874, %f869, %f873;
	sub.f32 	%f875, %f869, %f874;
	add.f32 	%f876, %f873, %f875;
	mul.rn.f32 	%f877, %f828, %f874;
	neg.f32 	%f878, %f877;
	fma.rn.f32 	%f879, %f828, %f874, %f878;
	fma.rn.f32 	%f880, %f828, %f876, %f879;
	mov.f32 	%f881, 0f00000000;
	fma.rn.f32 	%f882, %f881, %f874, %f880;
	add.rn.f32 	%f883, %f877, %f882;
	neg.f32 	%f884, %f883;
	add.rn.f32 	%f885, %f877, %f884;
	add.rn.f32 	%f886, %f885, %f882;
	mov.b32 	%r332, %f883;
	setp.eq.s32 	%p91, %r332, 1118925336;
	add.s32 	%r333, %r332, -1;
	mov.b32 	%f887, %r333;
	add.f32 	%f888, %f886, 0f37000000;
	selp.f32 	%f289, %f888, %f886, %p91;
	selp.f32 	%f889, %f887, %f883, %p91;
	mov.f32 	%f890, 0f3FB8AA3B;
	mul.rn.f32 	%f891, %f889, %f890;
	cvt.rzi.f32.f32 	%f892, %f891;
	abs.f32 	%f893, %f892;
	setp.gt.f32 	%p92, %f893, 0f42FC0000;
	mov.b32 	%r334, %f892;
	and.b32  	%r335, %r334, -2147483648;
	or.b32  	%r336, %r335, 1123811328;
	mov.b32 	%f894, %r336;
	selp.f32 	%f895, %f894, %f892, %p92;
	mov.f32 	%f896, 0fBF317218;
	fma.rn.f32 	%f897, %f895, %f896, %f889;
	mov.f32 	%f898, 0f3102E308;
	fma.rn.f32 	%f899, %f895, %f898, %f897;
	mul.f32 	%f900, %f899, 0f3FB8AA3B;
	add.f32 	%f901, %f895, 0f4B40007F;
	mov.b32 	%r337, %f901;
	shl.b32 	%r338, %r337, 23;
	mov.b32 	%f902, %r338;
	ex2.approx.ftz.f32 	%f903, %f900;
	mul.f32 	%f290, %f903, %f902;
	setp.eq.f32 	%p93, %f290, 0f7F800000;
	mov.f32 	%f1627, 0f7F800000;
	@%p93 bra 	$L__BB0_73;

	fma.rn.f32 	%f1627, %f290, %f289, %f290;

$L__BB0_73:
	setp.lt.f32 	%p94, %f283, 0f00000000;
	setp.eq.f32 	%p95, %f287, 0f3F800000;
	and.pred  	%p4, %p94, %p95;
	setp.eq.f32 	%p96, %f283, 0f00000000;
	@%p96 bra 	$L__BB0_77;
	bra.uni 	$L__BB0_74;

$L__BB0_77:
	add.f32 	%f908, %f283, %f283;
	selp.f32 	%f1629, %f908, 0f00000000, %p95;
	bra.uni 	$L__BB0_78;

$L__BB0_74:
	mov.b32 	%r339, %f1627;
	xor.b32  	%r340, %r339, -2147483648;
	mov.b32 	%f904, %r340;
	selp.f32 	%f1629, %f904, %f1627, %p4;
	setp.geu.f32 	%p97, %f283, 0f00000000;
	@%p97 bra 	$L__BB0_78;

	mov.f32 	%f905, 0f3EE66666;
	cvt.rzi.f32.f32 	%f906, %f905;
	setp.eq.f32 	%p98, %f906, 0f3EE66666;
	@%p98 bra 	$L__BB0_78;

	mov.f32 	%f1629, 0f7FFFFFFF;

$L__BB0_78:
	add.f32 	%f909, %f288, 0f3EE66666;
	mov.b32 	%r341, %f909;
	setp.lt.s32 	%p100, %r341, 2139095040;
	@%p100 bra 	$L__BB0_83;

	setp.gtu.f32 	%p101, %f288, 0f7F800000;
	@%p101 bra 	$L__BB0_82;
	bra.uni 	$L__BB0_80;

$L__BB0_82:
	add.f32 	%f1629, %f283, 0f3EE66666;
	bra.uni 	$L__BB0_83;

$L__BB0_80:
	setp.neu.f32 	%p102, %f288, 0f7F800000;
	@%p102 bra 	$L__BB0_83;

	selp.f32 	%f1629, 0fFF800000, 0f7F800000, %p4;

$L__BB0_83:
	setp.eq.f32 	%p103, %f283, 0f3F800000;
	selp.f32 	%f299, 0f3F800000, %f1629, %p103;
	abs.f32 	%f300, %f284;
	setp.lt.f32 	%p104, %f300, 0f00800000;
	mul.f32 	%f911, %f300, 0f4B800000;
	selp.f32 	%f912, %f911, %f300, %p104;
	selp.f32 	%f913, 0fC3170000, 0fC2FE0000, %p104;
	mov.b32 	%r342, %f912;
	and.b32  	%r343, %r342, 8388607;
	or.b32  	%r344, %r343, 1065353216;
	mov.b32 	%f914, %r344;
	shr.u32 	%r345, %r342, 23;
	cvt.rn.f32.u32 	%f915, %r345;
	add.f32 	%f916, %f913, %f915;
	setp.gt.f32 	%p105, %f914, 0f3FB504F3;
	mul.f32 	%f917, %f914, 0f3F000000;
	add.f32 	%f918, %f916, 0f3F800000;
	selp.f32 	%f919, %f918, %f916, %p105;
	selp.f32 	%f920, %f917, %f914, %p105;
	add.f32 	%f921, %f920, 0fBF800000;
	add.f32 	%f922, %f920, 0f3F800000;
	rcp.approx.ftz.f32 	%f923, %f922;
	add.f32 	%f924, %f921, %f921;
	mul.f32 	%f925, %f924, %f923;
	mul.f32 	%f926, %f925, %f925;
	mov.f32 	%f927, 0f3C4CAF63;
	mov.f32 	%f928, 0f3B18F0FE;
	fma.rn.f32 	%f929, %f928, %f926, %f927;
	mov.f32 	%f930, 0f3DAAAABD;
	fma.rn.f32 	%f931, %f929, %f926, %f930;
	mul.rn.f32 	%f932, %f931, %f926;
	mul.rn.f32 	%f933, %f932, %f925;
	sub.f32 	%f934, %f921, %f925;
	add.f32 	%f935, %f934, %f934;
	neg.f32 	%f936, %f925;
	fma.rn.f32 	%f937, %f936, %f921, %f935;
	mul.rn.f32 	%f938, %f923, %f937;
	add.f32 	%f939, %f933, %f925;
	sub.f32 	%f940, %f925, %f939;
	add.f32 	%f941, %f933, %f940;
	add.f32 	%f942, %f938, %f941;
	add.f32 	%f943, %f939, %f942;
	sub.f32 	%f944, %f939, %f943;
	add.f32 	%f945, %f942, %f944;
	mov.f32 	%f946, 0f3F317200;
	mul.rn.f32 	%f947, %f919, %f946;
	mov.f32 	%f948, 0f35BFBE8E;
	mul.rn.f32 	%f949, %f919, %f948;
	add.f32 	%f950, %f947, %f943;
	sub.f32 	%f951, %f947, %f950;
	add.f32 	%f952, %f943, %f951;
	add.f32 	%f953, %f945, %f952;
	add.f32 	%f954, %f949, %f953;
	add.f32 	%f955, %f950, %f954;
	sub.f32 	%f956, %f950, %f955;
	add.f32 	%f957, %f954, %f956;
	mov.f32 	%f958, 0f3EE66666;
	mul.rn.f32 	%f959, %f958, %f955;
	neg.f32 	%f960, %f959;
	fma.rn.f32 	%f961, %f958, %f955, %f960;
	fma.rn.f32 	%f962, %f958, %f957, %f961;
	mov.f32 	%f963, 0f00000000;
	fma.rn.f32 	%f964, %f963, %f955, %f962;
	add.rn.f32 	%f965, %f959, %f964;
	neg.f32 	%f966, %f965;
	add.rn.f32 	%f967, %f959, %f966;
	add.rn.f32 	%f968, %f967, %f964;
	mov.b32 	%r346, %f965;
	setp.eq.s32 	%p106, %r346, 1118925336;
	add.s32 	%r347, %r346, -1;
	mov.b32 	%f969, %r347;
	add.f32 	%f970, %f968, 0f37000000;
	selp.f32 	%f301, %f970, %f968, %p106;
	selp.f32 	%f971, %f969, %f965, %p106;
	mov.f32 	%f972, 0f3FB8AA3B;
	mul.rn.f32 	%f973, %f971, %f972;
	cvt.rzi.f32.f32 	%f974, %f973;
	abs.f32 	%f975, %f974;
	setp.gt.f32 	%p107, %f975, 0f42FC0000;
	mov.b32 	%r348, %f974;
	and.b32  	%r349, %r348, -2147483648;
	or.b32  	%r350, %r349, 1123811328;
	mov.b32 	%f976, %r350;
	selp.f32 	%f977, %f976, %f974, %p107;
	mov.f32 	%f978, 0fBF317218;
	fma.rn.f32 	%f979, %f977, %f978, %f971;
	mov.f32 	%f980, 0f3102E308;
	fma.rn.f32 	%f981, %f977, %f980, %f979;
	mul.f32 	%f982, %f981, 0f3FB8AA3B;
	add.f32 	%f983, %f977, 0f4B40007F;
	mov.b32 	%r351, %f983;
	shl.b32 	%r352, %r351, 23;
	mov.b32 	%f984, %r352;
	ex2.approx.ftz.f32 	%f985, %f982;
	mul.f32 	%f302, %f985, %f984;
	setp.eq.f32 	%p108, %f302, 0f7F800000;
	mov.f32 	%f1630, 0f7F800000;
	@%p108 bra 	$L__BB0_85;

	fma.rn.f32 	%f1630, %f302, %f301, %f302;

$L__BB0_85:
	setp.lt.f32 	%p109, %f284, 0f00000000;
	and.pred  	%p5, %p109, %p95;
	setp.eq.f32 	%p111, %f284, 0f00000000;
	@%p111 bra 	$L__BB0_89;
	bra.uni 	$L__BB0_86;

$L__BB0_89:
	add.f32 	%f990, %f284, %f284;
	selp.f32 	%f1632, %f990, 0f00000000, %p95;
	bra.uni 	$L__BB0_90;

$L__BB0_86:
	mov.b32 	%r353, %f1630;
	xor.b32  	%r354, %r353, -2147483648;
	mov.b32 	%f986, %r354;
	selp.f32 	%f1632, %f986, %f1630, %p5;
	setp.geu.f32 	%p112, %f284, 0f00000000;
	@%p112 bra 	$L__BB0_90;

	mov.f32 	%f987, 0f3EE66666;
	cvt.rzi.f32.f32 	%f988, %f987;
	setp.eq.f32 	%p113, %f988, 0f3EE66666;
	@%p113 bra 	$L__BB0_90;

	mov.f32 	%f1632, 0f7FFFFFFF;

$L__BB0_90:
	add.f32 	%f991, %f300, 0f3EE66666;
	mov.b32 	%r355, %f991;
	setp.lt.s32 	%p115, %r355, 2139095040;
	@%p115 bra 	$L__BB0_95;

	setp.gtu.f32 	%p116, %f300, 0f7F800000;
	@%p116 bra 	$L__BB0_94;
	bra.uni 	$L__BB0_92;

$L__BB0_94:
	add.f32 	%f1632, %f284, 0f3EE66666;
	bra.uni 	$L__BB0_95;

$L__BB0_92:
	setp.neu.f32 	%p117, %f300, 0f7F800000;
	@%p117 bra 	$L__BB0_95;

	selp.f32 	%f1632, 0fFF800000, 0f7F800000, %p5;

$L__BB0_95:
	setp.eq.f32 	%p118, %f284, 0f3F800000;
	selp.f32 	%f311, 0f3F800000, %f1632, %p118;
	abs.f32 	%f312, %f286;
	setp.lt.f32 	%p119, %f312, 0f00800000;
	mul.f32 	%f993, %f312, 0f4B800000;
	selp.f32 	%f994, %f993, %f312, %p119;
	selp.f32 	%f995, 0fC3170000, 0fC2FE0000, %p119;
	mov.b32 	%r356, %f994;
	and.b32  	%r357, %r356, 8388607;
	or.b32  	%r358, %r357, 1065353216;
	mov.b32 	%f996, %r358;
	shr.u32 	%r359, %r356, 23;
	cvt.rn.f32.u32 	%f997, %r359;
	add.f32 	%f998, %f995, %f997;
	setp.gt.f32 	%p120, %f996, 0f3FB504F3;
	mul.f32 	%f999, %f996, 0f3F000000;
	add.f32 	%f1000, %f998, 0f3F800000;
	selp.f32 	%f1001, %f1000, %f998, %p120;
	selp.f32 	%f1002, %f999, %f996, %p120;
	add.f32 	%f1003, %f1002, 0fBF800000;
	add.f32 	%f1004, %f1002, 0f3F800000;
	rcp.approx.ftz.f32 	%f1005, %f1004;
	add.f32 	%f1006, %f1003, %f1003;
	mul.f32 	%f1007, %f1006, %f1005;
	mul.f32 	%f1008, %f1007, %f1007;
	mov.f32 	%f1009, 0f3C4CAF63;
	mov.f32 	%f1010, 0f3B18F0FE;
	fma.rn.f32 	%f1011, %f1010, %f1008, %f1009;
	mov.f32 	%f1012, 0f3DAAAABD;
	fma.rn.f32 	%f1013, %f1011, %f1008, %f1012;
	mul.rn.f32 	%f1014, %f1013, %f1008;
	mul.rn.f32 	%f1015, %f1014, %f1007;
	sub.f32 	%f1016, %f1003, %f1007;
	add.f32 	%f1017, %f1016, %f1016;
	neg.f32 	%f1018, %f1007;
	fma.rn.f32 	%f1019, %f1018, %f1003, %f1017;
	mul.rn.f32 	%f1020, %f1005, %f1019;
	add.f32 	%f1021, %f1015, %f1007;
	sub.f32 	%f1022, %f1007, %f1021;
	add.f32 	%f1023, %f1015, %f1022;
	add.f32 	%f1024, %f1020, %f1023;
	add.f32 	%f1025, %f1021, %f1024;
	sub.f32 	%f1026, %f1021, %f1025;
	add.f32 	%f1027, %f1024, %f1026;
	mov.f32 	%f1028, 0f3F317200;
	mul.rn.f32 	%f1029, %f1001, %f1028;
	mov.f32 	%f1030, 0f35BFBE8E;
	mul.rn.f32 	%f1031, %f1001, %f1030;
	add.f32 	%f1032, %f1029, %f1025;
	sub.f32 	%f1033, %f1029, %f1032;
	add.f32 	%f1034, %f1025, %f1033;
	add.f32 	%f1035, %f1027, %f1034;
	add.f32 	%f1036, %f1031, %f1035;
	add.f32 	%f1037, %f1032, %f1036;
	sub.f32 	%f1038, %f1032, %f1037;
	add.f32 	%f1039, %f1036, %f1038;
	mov.f32 	%f1040, 0f3EE66666;
	mul.rn.f32 	%f1041, %f1040, %f1037;
	neg.f32 	%f1042, %f1041;
	fma.rn.f32 	%f1043, %f1040, %f1037, %f1042;
	fma.rn.f32 	%f1044, %f1040, %f1039, %f1043;
	mov.f32 	%f1045, 0f00000000;
	fma.rn.f32 	%f1046, %f1045, %f1037, %f1044;
	add.rn.f32 	%f1047, %f1041, %f1046;
	neg.f32 	%f1048, %f1047;
	add.rn.f32 	%f1049, %f1041, %f1048;
	add.rn.f32 	%f1050, %f1049, %f1046;
	mov.b32 	%r360, %f1047;
	setp.eq.s32 	%p121, %r360, 1118925336;
	add.s32 	%r361, %r360, -1;
	mov.b32 	%f1051, %r361;
	add.f32 	%f1052, %f1050, 0f37000000;
	selp.f32 	%f313, %f1052, %f1050, %p121;
	selp.f32 	%f1053, %f1051, %f1047, %p121;
	mov.f32 	%f1054, 0f3FB8AA3B;
	mul.rn.f32 	%f1055, %f1053, %f1054;
	cvt.rzi.f32.f32 	%f1056, %f1055;
	abs.f32 	%f1057, %f1056;
	setp.gt.f32 	%p122, %f1057, 0f42FC0000;
	mov.b32 	%r362, %f1056;
	and.b32  	%r363, %r362, -2147483648;
	or.b32  	%r364, %r363, 1123811328;
	mov.b32 	%f1058, %r364;
	selp.f32 	%f1059, %f1058, %f1056, %p122;
	mov.f32 	%f1060, 0fBF317218;
	fma.rn.f32 	%f1061, %f1059, %f1060, %f1053;
	mov.f32 	%f1062, 0f3102E308;
	fma.rn.f32 	%f1063, %f1059, %f1062, %f1061;
	mul.f32 	%f1064, %f1063, 0f3FB8AA3B;
	add.f32 	%f1065, %f1059, 0f4B40007F;
	mov.b32 	%r365, %f1065;
	shl.b32 	%r366, %r365, 23;
	mov.b32 	%f1066, %r366;
	ex2.approx.ftz.f32 	%f1067, %f1064;
	mul.f32 	%f314, %f1067, %f1066;
	setp.eq.f32 	%p123, %f314, 0f7F800000;
	mov.f32 	%f1633, 0f7F800000;
	@%p123 bra 	$L__BB0_97;

	fma.rn.f32 	%f1633, %f314, %f313, %f314;

$L__BB0_97:
	setp.lt.f32 	%p124, %f286, 0f00000000;
	and.pred  	%p6, %p124, %p95;
	setp.eq.f32 	%p126, %f286, 0f00000000;
	@%p126 bra 	$L__BB0_101;
	bra.uni 	$L__BB0_98;

$L__BB0_101:
	add.f32 	%f1072, %f286, %f286;
	selp.f32 	%f1635, %f1072, 0f00000000, %p95;
	bra.uni 	$L__BB0_102;

$L__BB0_98:
	mov.b32 	%r367, %f1633;
	xor.b32  	%r368, %r367, -2147483648;
	mov.b32 	%f1068, %r368;
	selp.f32 	%f1635, %f1068, %f1633, %p6;
	setp.geu.f32 	%p127, %f286, 0f00000000;
	@%p127 bra 	$L__BB0_102;

	mov.f32 	%f1069, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1070, %f1069;
	setp.eq.f32 	%p128, %f1070, 0f3EE66666;
	@%p128 bra 	$L__BB0_102;

	mov.f32 	%f1635, 0f7FFFFFFF;

$L__BB0_102:
	add.f32 	%f1073, %f312, 0f3EE66666;
	mov.b32 	%r369, %f1073;
	setp.lt.s32 	%p130, %r369, 2139095040;
	@%p130 bra 	$L__BB0_107;

	setp.gtu.f32 	%p131, %f312, 0f7F800000;
	@%p131 bra 	$L__BB0_106;
	bra.uni 	$L__BB0_104;

$L__BB0_106:
	add.f32 	%f1635, %f286, 0f3EE66666;
	bra.uni 	$L__BB0_107;

$L__BB0_104:
	setp.neu.f32 	%p132, %f312, 0f7F800000;
	@%p132 bra 	$L__BB0_107;

	selp.f32 	%f1635, 0fFF800000, 0f7F800000, %p6;

$L__BB0_107:
	setp.eq.f32 	%p133, %f286, 0f3F800000;
	mov.f32 	%f1075, 0f3F800000;
	selp.f32 	%f1076, 0f3F800000, %f1635, %p133;
	ld.const.u64 	%rd79, [params+144];
	cvta.to.global.u64 	%rd21, %rd79;
	ld.const.u32 	%r370, [params+136];
	mad.lo.s32 	%r371, %r370, %r7, %r6;
	cvt.u64.u32 	%rd22, %r371;
	min.f32 	%f1077, %f299, %f1075;
	mov.f32 	%f1078, 0f00000000;
	max.f32 	%f323, %f1078, %f1077;
	min.f32 	%f1079, %f311, %f1075;
	max.f32 	%f324, %f1078, %f1079;
	min.f32 	%f1080, %f1076, %f1075;
	max.f32 	%f325, %f1078, %f1080;
	mov.f32 	%f1081, 0f3E555555;
	cvt.rzi.f32.f32 	%f1082, %f1081;
	add.f32 	%f1083, %f1082, %f1082;
	mov.f32 	%f1084, 0f3ED55555;
	sub.f32 	%f1085, %f1084, %f1083;
	abs.f32 	%f326, %f1085;
	abs.f32 	%f327, %f323;
	setp.lt.f32 	%p134, %f327, 0f00800000;
	mul.f32 	%f1086, %f327, 0f4B800000;
	selp.f32 	%f1087, %f1086, %f327, %p134;
	selp.f32 	%f1088, 0fC3170000, 0fC2FE0000, %p134;
	mov.b32 	%r372, %f1087;
	and.b32  	%r373, %r372, 8388607;
	or.b32  	%r374, %r373, 1065353216;
	mov.b32 	%f1089, %r374;
	shr.u32 	%r375, %r372, 23;
	cvt.rn.f32.u32 	%f1090, %r375;
	add.f32 	%f1091, %f1088, %f1090;
	setp.gt.f32 	%p135, %f1089, 0f3FB504F3;
	mul.f32 	%f1092, %f1089, 0f3F000000;
	add.f32 	%f1093, %f1091, 0f3F800000;
	selp.f32 	%f1094, %f1093, %f1091, %p135;
	selp.f32 	%f1095, %f1092, %f1089, %p135;
	add.f32 	%f1096, %f1095, 0fBF800000;
	add.f32 	%f1097, %f1095, 0f3F800000;
	rcp.approx.ftz.f32 	%f1098, %f1097;
	add.f32 	%f1099, %f1096, %f1096;
	mul.f32 	%f1100, %f1099, %f1098;
	mul.f32 	%f1101, %f1100, %f1100;
	mov.f32 	%f1102, 0f3C4CAF63;
	mov.f32 	%f1103, 0f3B18F0FE;
	fma.rn.f32 	%f1104, %f1103, %f1101, %f1102;
	mov.f32 	%f1105, 0f3DAAAABD;
	fma.rn.f32 	%f1106, %f1104, %f1101, %f1105;
	mul.rn.f32 	%f1107, %f1106, %f1101;
	mul.rn.f32 	%f1108, %f1107, %f1100;
	sub.f32 	%f1109, %f1096, %f1100;
	add.f32 	%f1110, %f1109, %f1109;
	neg.f32 	%f1111, %f1100;
	fma.rn.f32 	%f1112, %f1111, %f1096, %f1110;
	mul.rn.f32 	%f1113, %f1098, %f1112;
	add.f32 	%f1114, %f1108, %f1100;
	sub.f32 	%f1115, %f1100, %f1114;
	add.f32 	%f1116, %f1108, %f1115;
	add.f32 	%f1117, %f1113, %f1116;
	add.f32 	%f1118, %f1114, %f1117;
	sub.f32 	%f1119, %f1114, %f1118;
	add.f32 	%f1120, %f1117, %f1119;
	mov.f32 	%f1121, 0f3F317200;
	mul.rn.f32 	%f1122, %f1094, %f1121;
	mov.f32 	%f1123, 0f35BFBE8E;
	mul.rn.f32 	%f1124, %f1094, %f1123;
	add.f32 	%f1125, %f1122, %f1118;
	sub.f32 	%f1126, %f1122, %f1125;
	add.f32 	%f1127, %f1118, %f1126;
	add.f32 	%f1128, %f1120, %f1127;
	add.f32 	%f1129, %f1124, %f1128;
	add.f32 	%f1130, %f1125, %f1129;
	sub.f32 	%f1131, %f1125, %f1130;
	add.f32 	%f1132, %f1129, %f1131;
	mul.rn.f32 	%f1133, %f1084, %f1130;
	neg.f32 	%f1134, %f1133;
	fma.rn.f32 	%f1135, %f1084, %f1130, %f1134;
	fma.rn.f32 	%f1136, %f1084, %f1132, %f1135;
	fma.rn.f32 	%f1137, %f1078, %f1130, %f1136;
	add.rn.f32 	%f1138, %f1133, %f1137;
	neg.f32 	%f1139, %f1138;
	add.rn.f32 	%f1140, %f1133, %f1139;
	add.rn.f32 	%f1141, %f1140, %f1137;
	mov.b32 	%r376, %f1138;
	setp.eq.s32 	%p136, %r376, 1118925336;
	add.s32 	%r377, %r376, -1;
	mov.b32 	%f1142, %r377;
	add.f32 	%f1143, %f1141, 0f37000000;
	selp.f32 	%f328, %f1143, %f1141, %p136;
	selp.f32 	%f1144, %f1142, %f1138, %p136;
	mov.f32 	%f1145, 0f3FB8AA3B;
	mul.rn.f32 	%f1146, %f1144, %f1145;
	cvt.rzi.f32.f32 	%f1147, %f1146;
	abs.f32 	%f1148, %f1147;
	setp.gt.f32 	%p137, %f1148, 0f42FC0000;
	mov.b32 	%r378, %f1147;
	and.b32  	%r379, %r378, -2147483648;
	or.b32  	%r380, %r379, 1123811328;
	mov.b32 	%f1149, %r380;
	selp.f32 	%f1150, %f1149, %f1147, %p137;
	mov.f32 	%f1151, 0fBF317218;
	fma.rn.f32 	%f1152, %f1150, %f1151, %f1144;
	mov.f32 	%f1153, 0f3102E308;
	fma.rn.f32 	%f1154, %f1150, %f1153, %f1152;
	mul.f32 	%f1155, %f1154, 0f3FB8AA3B;
	add.f32 	%f1156, %f1150, 0f4B40007F;
	mov.b32 	%r381, %f1156;
	shl.b32 	%r382, %r381, 23;
	mov.b32 	%f1157, %r382;
	ex2.approx.ftz.f32 	%f1158, %f1155;
	mul.f32 	%f329, %f1158, %f1157;
	setp.eq.f32 	%p138, %f329, 0f7F800000;
	mov.f32 	%f1636, 0f7F800000;
	@%p138 bra 	$L__BB0_109;

	fma.rn.f32 	%f1636, %f329, %f328, %f329;

$L__BB0_109:
	setp.lt.f32 	%p139, %f323, 0f00000000;
	setp.eq.f32 	%p140, %f326, 0f3F800000;
	and.pred  	%p7, %p139, %p140;
	setp.eq.f32 	%p141, %f323, 0f00000000;
	@%p141 bra 	$L__BB0_113;
	bra.uni 	$L__BB0_110;

$L__BB0_113:
	add.f32 	%f1163, %f323, %f323;
	selp.f32 	%f1638, %f1163, 0f00000000, %p140;
	bra.uni 	$L__BB0_114;

$L__BB0_110:
	mov.b32 	%r383, %f1636;
	xor.b32  	%r384, %r383, -2147483648;
	mov.b32 	%f1159, %r384;
	selp.f32 	%f1638, %f1159, %f1636, %p7;
	setp.geu.f32 	%p142, %f323, 0f00000000;
	@%p142 bra 	$L__BB0_114;

	mov.f32 	%f1160, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1161, %f1160;
	setp.eq.f32 	%p143, %f1161, 0f3ED55555;
	@%p143 bra 	$L__BB0_114;

	mov.f32 	%f1638, 0f7FFFFFFF;

$L__BB0_114:
	add.f32 	%f1164, %f327, 0f3ED55555;
	mov.b32 	%r385, %f1164;
	setp.lt.s32 	%p145, %r385, 2139095040;
	@%p145 bra 	$L__BB0_119;

	setp.gtu.f32 	%p146, %f327, 0f7F800000;
	@%p146 bra 	$L__BB0_118;
	bra.uni 	$L__BB0_116;

$L__BB0_118:
	add.f32 	%f1638, %f323, 0f3ED55555;
	bra.uni 	$L__BB0_119;

$L__BB0_116:
	setp.neu.f32 	%p147, %f327, 0f7F800000;
	@%p147 bra 	$L__BB0_119;

	selp.f32 	%f1638, 0fFF800000, 0f7F800000, %p7;

$L__BB0_119:
	abs.f32 	%f338, %f324;
	setp.lt.f32 	%p148, %f338, 0f00800000;
	mul.f32 	%f1166, %f338, 0f4B800000;
	selp.f32 	%f1167, %f1166, %f338, %p148;
	selp.f32 	%f1168, 0fC3170000, 0fC2FE0000, %p148;
	mov.b32 	%r386, %f1167;
	and.b32  	%r387, %r386, 8388607;
	or.b32  	%r388, %r387, 1065353216;
	mov.b32 	%f1169, %r388;
	shr.u32 	%r389, %r386, 23;
	cvt.rn.f32.u32 	%f1170, %r389;
	add.f32 	%f1171, %f1168, %f1170;
	setp.gt.f32 	%p149, %f1169, 0f3FB504F3;
	mul.f32 	%f1172, %f1169, 0f3F000000;
	add.f32 	%f1173, %f1171, 0f3F800000;
	selp.f32 	%f1174, %f1173, %f1171, %p149;
	selp.f32 	%f1175, %f1172, %f1169, %p149;
	add.f32 	%f1176, %f1175, 0fBF800000;
	add.f32 	%f1177, %f1175, 0f3F800000;
	rcp.approx.ftz.f32 	%f1178, %f1177;
	add.f32 	%f1179, %f1176, %f1176;
	mul.f32 	%f1180, %f1179, %f1178;
	mul.f32 	%f1181, %f1180, %f1180;
	mov.f32 	%f1182, 0f3C4CAF63;
	mov.f32 	%f1183, 0f3B18F0FE;
	fma.rn.f32 	%f1184, %f1183, %f1181, %f1182;
	mov.f32 	%f1185, 0f3DAAAABD;
	fma.rn.f32 	%f1186, %f1184, %f1181, %f1185;
	mul.rn.f32 	%f1187, %f1186, %f1181;
	mul.rn.f32 	%f1188, %f1187, %f1180;
	sub.f32 	%f1189, %f1176, %f1180;
	add.f32 	%f1190, %f1189, %f1189;
	neg.f32 	%f1191, %f1180;
	fma.rn.f32 	%f1192, %f1191, %f1176, %f1190;
	mul.rn.f32 	%f1193, %f1178, %f1192;
	add.f32 	%f1194, %f1188, %f1180;
	sub.f32 	%f1195, %f1180, %f1194;
	add.f32 	%f1196, %f1188, %f1195;
	add.f32 	%f1197, %f1193, %f1196;
	add.f32 	%f1198, %f1194, %f1197;
	sub.f32 	%f1199, %f1194, %f1198;
	add.f32 	%f1200, %f1197, %f1199;
	mov.f32 	%f1201, 0f3F317200;
	mul.rn.f32 	%f1202, %f1174, %f1201;
	mov.f32 	%f1203, 0f35BFBE8E;
	mul.rn.f32 	%f1204, %f1174, %f1203;
	add.f32 	%f1205, %f1202, %f1198;
	sub.f32 	%f1206, %f1202, %f1205;
	add.f32 	%f1207, %f1198, %f1206;
	add.f32 	%f1208, %f1200, %f1207;
	add.f32 	%f1209, %f1204, %f1208;
	add.f32 	%f1210, %f1205, %f1209;
	sub.f32 	%f1211, %f1205, %f1210;
	add.f32 	%f1212, %f1209, %f1211;
	mov.f32 	%f1213, 0f3ED55555;
	mul.rn.f32 	%f1214, %f1213, %f1210;
	neg.f32 	%f1215, %f1214;
	fma.rn.f32 	%f1216, %f1213, %f1210, %f1215;
	fma.rn.f32 	%f1217, %f1213, %f1212, %f1216;
	mov.f32 	%f1218, 0f00000000;
	fma.rn.f32 	%f1219, %f1218, %f1210, %f1217;
	add.rn.f32 	%f1220, %f1214, %f1219;
	neg.f32 	%f1221, %f1220;
	add.rn.f32 	%f1222, %f1214, %f1221;
	add.rn.f32 	%f1223, %f1222, %f1219;
	mov.b32 	%r390, %f1220;
	setp.eq.s32 	%p150, %r390, 1118925336;
	add.s32 	%r391, %r390, -1;
	mov.b32 	%f1224, %r391;
	add.f32 	%f1225, %f1223, 0f37000000;
	selp.f32 	%f339, %f1225, %f1223, %p150;
	selp.f32 	%f1226, %f1224, %f1220, %p150;
	mov.f32 	%f1227, 0f3FB8AA3B;
	mul.rn.f32 	%f1228, %f1226, %f1227;
	cvt.rzi.f32.f32 	%f1229, %f1228;
	abs.f32 	%f1230, %f1229;
	setp.gt.f32 	%p151, %f1230, 0f42FC0000;
	mov.b32 	%r392, %f1229;
	and.b32  	%r393, %r392, -2147483648;
	or.b32  	%r394, %r393, 1123811328;
	mov.b32 	%f1231, %r394;
	selp.f32 	%f1232, %f1231, %f1229, %p151;
	mov.f32 	%f1233, 0fBF317218;
	fma.rn.f32 	%f1234, %f1232, %f1233, %f1226;
	mov.f32 	%f1235, 0f3102E308;
	fma.rn.f32 	%f1236, %f1232, %f1235, %f1234;
	mul.f32 	%f1237, %f1236, 0f3FB8AA3B;
	add.f32 	%f1238, %f1232, 0f4B40007F;
	mov.b32 	%r395, %f1238;
	shl.b32 	%r396, %r395, 23;
	mov.b32 	%f1239, %r396;
	ex2.approx.ftz.f32 	%f1240, %f1237;
	mul.f32 	%f340, %f1240, %f1239;
	setp.eq.f32 	%p152, %f340, 0f7F800000;
	mov.f32 	%f1639, 0f7F800000;
	@%p152 bra 	$L__BB0_121;

	fma.rn.f32 	%f1639, %f340, %f339, %f340;

$L__BB0_121:
	setp.lt.f32 	%p153, %f324, 0f00000000;
	and.pred  	%p8, %p153, %p140;
	setp.eq.f32 	%p155, %f324, 0f00000000;
	@%p155 bra 	$L__BB0_125;
	bra.uni 	$L__BB0_122;

$L__BB0_125:
	add.f32 	%f1245, %f324, %f324;
	selp.f32 	%f1641, %f1245, 0f00000000, %p140;
	bra.uni 	$L__BB0_126;

$L__BB0_122:
	mov.b32 	%r397, %f1639;
	xor.b32  	%r398, %r397, -2147483648;
	mov.b32 	%f1241, %r398;
	selp.f32 	%f1641, %f1241, %f1639, %p8;
	setp.geu.f32 	%p156, %f324, 0f00000000;
	@%p156 bra 	$L__BB0_126;

	mov.f32 	%f1242, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1243, %f1242;
	setp.eq.f32 	%p157, %f1243, 0f3ED55555;
	@%p157 bra 	$L__BB0_126;

	mov.f32 	%f1641, 0f7FFFFFFF;

$L__BB0_126:
	add.f32 	%f1246, %f338, 0f3ED55555;
	mov.b32 	%r399, %f1246;
	setp.lt.s32 	%p159, %r399, 2139095040;
	@%p159 bra 	$L__BB0_131;

	setp.gtu.f32 	%p160, %f338, 0f7F800000;
	@%p160 bra 	$L__BB0_130;
	bra.uni 	$L__BB0_128;

$L__BB0_130:
	add.f32 	%f1641, %f324, 0f3ED55555;
	bra.uni 	$L__BB0_131;

$L__BB0_128:
	setp.neu.f32 	%p161, %f338, 0f7F800000;
	@%p161 bra 	$L__BB0_131;

	selp.f32 	%f1641, 0fFF800000, 0f7F800000, %p8;

$L__BB0_131:
	abs.f32 	%f349, %f325;
	setp.lt.f32 	%p162, %f349, 0f00800000;
	mul.f32 	%f1248, %f349, 0f4B800000;
	selp.f32 	%f1249, %f1248, %f349, %p162;
	selp.f32 	%f1250, 0fC3170000, 0fC2FE0000, %p162;
	mov.b32 	%r400, %f1249;
	and.b32  	%r401, %r400, 8388607;
	or.b32  	%r402, %r401, 1065353216;
	mov.b32 	%f1251, %r402;
	shr.u32 	%r403, %r400, 23;
	cvt.rn.f32.u32 	%f1252, %r403;
	add.f32 	%f1253, %f1250, %f1252;
	setp.gt.f32 	%p163, %f1251, 0f3FB504F3;
	mul.f32 	%f1254, %f1251, 0f3F000000;
	add.f32 	%f1255, %f1253, 0f3F800000;
	selp.f32 	%f1256, %f1255, %f1253, %p163;
	selp.f32 	%f1257, %f1254, %f1251, %p163;
	add.f32 	%f1258, %f1257, 0fBF800000;
	add.f32 	%f1259, %f1257, 0f3F800000;
	rcp.approx.ftz.f32 	%f1260, %f1259;
	add.f32 	%f1261, %f1258, %f1258;
	mul.f32 	%f1262, %f1261, %f1260;
	mul.f32 	%f1263, %f1262, %f1262;
	mov.f32 	%f1264, 0f3C4CAF63;
	mov.f32 	%f1265, 0f3B18F0FE;
	fma.rn.f32 	%f1266, %f1265, %f1263, %f1264;
	mov.f32 	%f1267, 0f3DAAAABD;
	fma.rn.f32 	%f1268, %f1266, %f1263, %f1267;
	mul.rn.f32 	%f1269, %f1268, %f1263;
	mul.rn.f32 	%f1270, %f1269, %f1262;
	sub.f32 	%f1271, %f1258, %f1262;
	add.f32 	%f1272, %f1271, %f1271;
	neg.f32 	%f1273, %f1262;
	fma.rn.f32 	%f1274, %f1273, %f1258, %f1272;
	mul.rn.f32 	%f1275, %f1260, %f1274;
	add.f32 	%f1276, %f1270, %f1262;
	sub.f32 	%f1277, %f1262, %f1276;
	add.f32 	%f1278, %f1270, %f1277;
	add.f32 	%f1279, %f1275, %f1278;
	add.f32 	%f1280, %f1276, %f1279;
	sub.f32 	%f1281, %f1276, %f1280;
	add.f32 	%f1282, %f1279, %f1281;
	mov.f32 	%f1283, 0f3F317200;
	mul.rn.f32 	%f1284, %f1256, %f1283;
	mov.f32 	%f1285, 0f35BFBE8E;
	mul.rn.f32 	%f1286, %f1256, %f1285;
	add.f32 	%f1287, %f1284, %f1280;
	sub.f32 	%f1288, %f1284, %f1287;
	add.f32 	%f1289, %f1280, %f1288;
	add.f32 	%f1290, %f1282, %f1289;
	add.f32 	%f1291, %f1286, %f1290;
	add.f32 	%f1292, %f1287, %f1291;
	sub.f32 	%f1293, %f1287, %f1292;
	add.f32 	%f1294, %f1291, %f1293;
	mov.f32 	%f1295, 0f3ED55555;
	mul.rn.f32 	%f1296, %f1295, %f1292;
	neg.f32 	%f1297, %f1296;
	fma.rn.f32 	%f1298, %f1295, %f1292, %f1297;
	fma.rn.f32 	%f1299, %f1295, %f1294, %f1298;
	mov.f32 	%f1300, 0f00000000;
	fma.rn.f32 	%f1301, %f1300, %f1292, %f1299;
	add.rn.f32 	%f1302, %f1296, %f1301;
	neg.f32 	%f1303, %f1302;
	add.rn.f32 	%f1304, %f1296, %f1303;
	add.rn.f32 	%f1305, %f1304, %f1301;
	mov.b32 	%r404, %f1302;
	setp.eq.s32 	%p164, %r404, 1118925336;
	add.s32 	%r405, %r404, -1;
	mov.b32 	%f1306, %r405;
	add.f32 	%f1307, %f1305, 0f37000000;
	selp.f32 	%f350, %f1307, %f1305, %p164;
	selp.f32 	%f1308, %f1306, %f1302, %p164;
	mov.f32 	%f1309, 0f3FB8AA3B;
	mul.rn.f32 	%f1310, %f1308, %f1309;
	cvt.rzi.f32.f32 	%f1311, %f1310;
	abs.f32 	%f1312, %f1311;
	setp.gt.f32 	%p165, %f1312, 0f42FC0000;
	mov.b32 	%r406, %f1311;
	and.b32  	%r407, %r406, -2147483648;
	or.b32  	%r408, %r407, 1123811328;
	mov.b32 	%f1313, %r408;
	selp.f32 	%f1314, %f1313, %f1311, %p165;
	mov.f32 	%f1315, 0fBF317218;
	fma.rn.f32 	%f1316, %f1314, %f1315, %f1308;
	mov.f32 	%f1317, 0f3102E308;
	fma.rn.f32 	%f1318, %f1314, %f1317, %f1316;
	mul.f32 	%f1319, %f1318, 0f3FB8AA3B;
	add.f32 	%f1320, %f1314, 0f4B40007F;
	mov.b32 	%r409, %f1320;
	shl.b32 	%r410, %r409, 23;
	mov.b32 	%f1321, %r410;
	ex2.approx.ftz.f32 	%f1322, %f1319;
	mul.f32 	%f351, %f1322, %f1321;
	setp.eq.f32 	%p166, %f351, 0f7F800000;
	mov.f32 	%f1642, 0f7F800000;
	@%p166 bra 	$L__BB0_133;

	fma.rn.f32 	%f1642, %f351, %f350, %f351;

$L__BB0_133:
	setp.lt.f32 	%p167, %f325, 0f00000000;
	and.pred  	%p9, %p167, %p140;
	setp.eq.f32 	%p169, %f325, 0f00000000;
	@%p169 bra 	$L__BB0_137;
	bra.uni 	$L__BB0_134;

$L__BB0_137:
	add.f32 	%f1327, %f325, %f325;
	selp.f32 	%f1644, %f1327, 0f00000000, %p140;
	bra.uni 	$L__BB0_138;

$L__BB0_134:
	mov.b32 	%r411, %f1642;
	xor.b32  	%r412, %r411, -2147483648;
	mov.b32 	%f1323, %r412;
	selp.f32 	%f1644, %f1323, %f1642, %p9;
	setp.geu.f32 	%p170, %f325, 0f00000000;
	@%p170 bra 	$L__BB0_138;

	mov.f32 	%f1324, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1325, %f1324;
	setp.eq.f32 	%p171, %f1325, 0f3ED55555;
	@%p171 bra 	$L__BB0_138;

	mov.f32 	%f1644, 0f7FFFFFFF;

$L__BB0_138:
	add.f32 	%f1328, %f349, 0f3ED55555;
	mov.b32 	%r413, %f1328;
	setp.lt.s32 	%p173, %r413, 2139095040;
	@%p173 bra 	$L__BB0_143;

	setp.gtu.f32 	%p174, %f349, 0f7F800000;
	@%p174 bra 	$L__BB0_142;
	bra.uni 	$L__BB0_140;

$L__BB0_142:
	add.f32 	%f1644, %f325, 0f3ED55555;
	bra.uni 	$L__BB0_143;

$L__BB0_140:
	setp.neu.f32 	%p175, %f349, 0f7F800000;
	@%p175 bra 	$L__BB0_143;

	selp.f32 	%f1644, 0fFF800000, 0f7F800000, %p9;

$L__BB0_143:
	fma.rn.f32 	%f1329, %f1638, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p176, %f323, 0f3F800000;
	mov.f32 	%f1330, 0f3F800000;
	selp.f32 	%f1331, 0f3F7FFFFF, %f1329, %p176;
	mul.f32 	%f1332, %f323, 0f414EB852;
	setp.lt.f32 	%p177, %f323, 0f3B4D2E1C;
	selp.f32 	%f1333, %f1332, %f1331, %p177;
	fma.rn.f32 	%f1334, %f1641, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p178, %f324, 0f3F800000;
	selp.f32 	%f1335, 0f3F7FFFFF, %f1334, %p178;
	mul.f32 	%f1336, %f324, 0f414EB852;
	setp.lt.f32 	%p179, %f324, 0f3B4D2E1C;
	selp.f32 	%f1337, %f1336, %f1335, %p179;
	fma.rn.f32 	%f1338, %f1644, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p180, %f325, 0f3F800000;
	selp.f32 	%f1339, 0f3F7FFFFF, %f1338, %p180;
	mul.f32 	%f1340, %f325, 0f414EB852;
	setp.lt.f32 	%p181, %f325, 0f3B4D2E1C;
	selp.f32 	%f1341, %f1340, %f1339, %p181;
	min.f32 	%f1342, %f1333, %f1330;
	mov.f32 	%f1343, 0f00000000;
	max.f32 	%f1344, %f1343, %f1342;
	mul.f32 	%f1345, %f1344, 0f43800000;
	cvt.rzi.u32.f32 	%r414, %f1345;
	min.u32 	%r415, %r414, 255;
	min.f32 	%f1346, %f1337, %f1330;
	max.f32 	%f1347, %f1343, %f1346;
	mul.f32 	%f1348, %f1347, 0f43800000;
	cvt.rzi.u32.f32 	%r416, %f1348;
	min.u32 	%r417, %r416, 255;
	min.f32 	%f1349, %f1341, %f1330;
	max.f32 	%f1350, %f1343, %f1349;
	mul.f32 	%f1351, %f1350, 0f43800000;
	cvt.rzi.u32.f32 	%r418, %f1351;
	min.u32 	%r419, %r418, 255;
	shl.b64 	%rd80, %rd22, 2;
	add.s64 	%rd81, %rd21, %rd80;
	cvt.u16.u32 	%rs18, %r419;
	cvt.u16.u32 	%rs19, %r417;
	cvt.u16.u32 	%rs20, %r415;
	mov.u16 	%rs21, 255;
	st.global.v4.u8 	[%rd81], {%rs20, %rs19, %rs18, %rs21};

$L__BB0_144:
	and.b32  	%r420, %r56, 4;
	setp.eq.s32 	%p182, %r420, 0;
	ld.const.u32 	%r467, [params+108];
	@%p182 bra 	$L__BB0_148;

	setp.eq.s32 	%p183, %r467, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r421, [params+216];
	mad.lo.s32 	%r422, %r421, %r7, %r6;
	mul.wide.u32 	%rd84, %r422, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p183 bra 	$L__BB0_147;

	ld.global.v4.u16 	{%rs29, %rs30, %rs31, %rs32}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1352, %rs29;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1353, %rs30;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1354, %rs31;}

	// end inline asm
	add.f32 	%f1355, %f283, %f1352;
	add.f32 	%f1356, %f284, %f1353;
	add.f32 	%f1357, %f286, %f1354;
	mov.f32 	%f1358, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1357;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f1356;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f1355;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1358;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs25, %rs26, %rs27, %rs28};
	bra.uni 	$L__BB0_148;

$L__BB0_147:
	mov.f32 	%f1362, 0f3F800000;
	mov.u32 	%r467, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1362;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f286;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f284;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f283;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs33, %rs34, %rs35, %rs36};

$L__BB0_148:
	selp.f32 	%f1363, 0f3F000000, 0f3E800000, %p199;
	mul.f32 	%f1364, %f1363, %f1617;
	mul.f32 	%f1365, %f1363, %f1618;
	mul.f32 	%f1366, %f1363, %f1619;
	mul.f32 	%f1367, %f1363, %f1614;
	mul.f32 	%f1368, %f1363, %f1615;
	mul.f32 	%f1369, %f1363, %f1616;
	mul.f32 	%f1370, %f1363, %f1611;
	mul.f32 	%f1371, %f1363, %f1612;
	mul.f32 	%f1372, %f1363, %f1613;
	mul.f32 	%f1373, %f1363, %f1608;
	mul.f32 	%f1374, %f1363, %f1609;
	mul.f32 	%f1375, %f1363, %f1610;
	mul.f32 	%f360, %f1364, %f822;
	mul.f32 	%f361, %f1365, %f823;
	mul.f32 	%f362, %f1366, %f285;
	mul.f32 	%f363, %f1367, %f822;
	mul.f32 	%f364, %f1368, %f823;
	mul.f32 	%f365, %f1369, %f285;
	mul.f32 	%f366, %f1370, %f822;
	mul.f32 	%f367, %f1371, %f823;
	mul.f32 	%f368, %f1372, %f285;
	mul.f32 	%f369, %f1373, %f822;
	mul.f32 	%f370, %f1374, %f823;
	mul.f32 	%f371, %f1375, %f285;
	ld.const.u64 	%rd85, [params+256];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r424, [params+248];
	mad.lo.s32 	%r425, %r424, %r7, %r6;
	mul.wide.u32 	%rd87, %r425, 8;
	add.s64 	%rd24, %rd86, %rd87;
	setp.eq.s32 	%p184, %r467, 0;
	@%p184 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs44, %rs45, %rs46, %rs47}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1376, %rs44;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1377, %rs45;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1378, %rs46;}

	// end inline asm
	add.f32 	%f1379, %f360, %f1376;
	add.f32 	%f1380, %f361, %f1377;
	add.f32 	%f1381, %f362, %f1378;
	mov.f32 	%f1382, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1381;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f1380;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f1379;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1382;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs40, %rs41, %rs42, %rs43};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1386, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1386;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f362;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f361;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f360;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs48, %rs49, %rs50, %rs51};

$L__BB0_151:
	mov.f32 	%f1387, 0f34000000;
	max.f32 	%f1388, %f360, %f1387;
	div.rn.f32 	%f1389, %f363, %f1388;
	max.f32 	%f1390, %f361, %f1387;
	div.rn.f32 	%f1391, %f364, %f1390;
	max.f32 	%f1392, %f362, %f1387;
	div.rn.f32 	%f1393, %f365, %f1392;
	fma.rn.f32 	%f372, %f1389, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f373, %f1391, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f374, %f1393, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1394, %f366, %f1388;
	div.rn.f32 	%f1395, %f367, %f1390;
	div.rn.f32 	%f1396, %f368, %f1392;
	fma.rn.f32 	%f375, %f1394, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f376, %f1395, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f377, %f1396, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1397, %f369, %f1388;
	div.rn.f32 	%f1398, %f370, %f1390;
	div.rn.f32 	%f1399, %f371, %f1392;
	fma.rn.f32 	%f378, %f1397, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f379, %f1398, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f380, %f1399, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd88, [params+272];
	cvta.to.global.u64 	%rd89, %rd88;
	ld.const.u32 	%r426, [params+264];
	mad.lo.s32 	%r427, %r426, %r7, %r6;
	mul.wide.u32 	%rd90, %r427, 8;
	add.s64 	%rd25, %rd89, %rd90;
	@%p184 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs59, %rs60, %rs61, %rs62}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1400, %rs59;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1401, %rs60;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1402, %rs61;}

	// end inline asm
	add.f32 	%f1403, %f372, %f1400;
	add.f32 	%f1404, %f373, %f1401;
	add.f32 	%f1405, %f374, %f1402;
	mov.f32 	%f1406, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1405;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f1404;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f1403;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1406;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs55, %rs56, %rs57, %rs58};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1410, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1410;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f374;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f373;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f372;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs63, %rs64, %rs65, %rs66};

$L__BB0_154:
	ld.const.u64 	%rd91, [params+288];
	cvta.to.global.u64 	%rd92, %rd91;
	ld.const.u32 	%r428, [params+280];
	mad.lo.s32 	%r429, %r428, %r7, %r6;
	mul.wide.u32 	%rd93, %r429, 8;
	add.s64 	%rd26, %rd92, %rd93;
	@%p184 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs74, %rs75, %rs76, %rs77}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1411, %rs74;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1412, %rs75;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1413, %rs76;}

	// end inline asm
	add.f32 	%f1414, %f375, %f1411;
	add.f32 	%f1415, %f376, %f1412;
	add.f32 	%f1416, %f377, %f1413;
	mov.f32 	%f1417, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1416;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1415;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1414;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1417;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs70, %rs71, %rs72, %rs73};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1421, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1421;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f377;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f376;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f375;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs78, %rs79, %rs80, %rs81};

$L__BB0_157:
	ld.const.u64 	%rd94, [params+304];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r430, [params+296];
	mad.lo.s32 	%r431, %r430, %r7, %r6;
	mul.wide.u32 	%rd96, %r431, 8;
	add.s64 	%rd27, %rd95, %rd96;
	@%p184 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs89, %rs90, %rs91, %rs92}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1422, %rs89;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1423, %rs90;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1424, %rs91;}

	// end inline asm
	add.f32 	%f1425, %f378, %f1422;
	add.f32 	%f1426, %f379, %f1423;
	add.f32 	%f1427, %f380, %f1424;
	mov.f32 	%f1428, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1427;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1426;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1425;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1428;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs85, %rs86, %rs87, %rs88};
	bra.uni 	$L__BB0_180;

$L__BB0_159:
	mov.f32 	%f1432, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1432;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f380;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f379;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f378;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs93, %rs94, %rs95, %rs96};

$L__BB0_180:
	ret;

}