//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[1184];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<6>;
	.reg .b16 	%rs<41>;
	.reg .f32 	%f<119>;
	.reg .b32 	%r<27>;
	.reg .b64 	%rd<52>;


	ld.param.u32 	%r4, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f33, [__direct_callable__oxMain_param_1+4];
	ld.param.f32 	%f32, [__direct_callable__oxMain_param_1];
	// begin inline asm
	call (%r5), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r6), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd7, [params+72];
	cvta.to.global.u64 	%rd8, %rd7;
	mul.wide.s32 	%rd9, %r4, 8;
	add.s64 	%rd10, %rd8, %rd9;
	ld.global.u64 	%rd1, [%rd10];
	setp.eq.s64 	%p1, %rd1, 0;
	@%p1 bra 	$L__BB0_2;

	ld.const.u64 	%rd11, [params+480];
	cvta.to.global.u64 	%rd12, %rd11;
	ld.const.u32 	%r8, [params+472];
	mad.lo.s32 	%r9, %r8, %r6, %r5;
	cvt.u64.u32 	%rd13, %r9;
	add.s64 	%rd14, %rd12, %rd13;
	ld.global.u8 	%r10, [%rd14];
	mov.u64 	%rd15, 1;
	shl.b64 	%rd16, %rd15, %r10;
	and.b64  	%rd17, %rd16, %rd1;
	setp.eq.s64 	%p2, %rd17, 0;
	mov.f32 	%f113, 0f00000000;
	mov.f32 	%f114, %f113;
	mov.f32 	%f115, %f113;
	mov.f32 	%f116, %f113;
	mov.f32 	%f117, %f113;
	mov.f32 	%f118, %f113;
	@%p2 bra 	$L__BB0_9;

$L__BB0_2:
	ld.const.u64 	%rd18, [params+24];
	cvta.to.global.u64 	%rd19, %rd18;
	mul.wide.u32 	%rd20, %r4, 12;
	add.s64 	%rd21, %rd19, %rd20;
	ld.global.s32 	%rd2, [%rd21];
	ld.global.s32 	%rd3, [%rd21+4];
	ld.global.s32 	%rd4, [%rd21+8];
	ld.const.u32 	%r3, [params+32];
	setp.gt.u32 	%p3, %r3, %r4;
	@%p3 bra 	$L__BB0_4;
	bra.uni 	$L__BB0_3;

$L__BB0_4:
	mov.f32 	%f118, 0f3F800000;
	sub.f32 	%f71, %f118, %f32;
	sub.f32 	%f109, %f71, %f33;
	bra.uni 	$L__BB0_5;

$L__BB0_3:
	sub.s32 	%r11, %r4, %r3;
	ld.const.v2.u64 	{%rd22, %rd23}, [params+48];
	cvta.to.global.u64 	%rd26, %rd22;
	mul.wide.u32 	%rd27, %r11, 4;
	add.s64 	%rd28, %rd26, %rd27;
	ld.const.u64 	%rd29, [params+40];
	cvta.to.global.u64 	%rd30, %rd29;
	shl.b64 	%rd31, %rd2, 3;
	add.s64 	%rd32, %rd30, %rd31;
	ld.global.v2.f32 	{%f40, %f41}, [%rd32];
	shl.b64 	%rd33, %rd3, 3;
	add.s64 	%rd34, %rd30, %rd33;
	ld.global.v2.f32 	{%f44, %f45}, [%rd34];
	shl.b64 	%rd35, %rd4, 3;
	add.s64 	%rd36, %rd30, %rd35;
	ld.global.v2.f32 	{%f48, %f49}, [%rd36];
	mov.f32 	%f52, 0f3F800000;
	sub.f32 	%f53, %f52, %f32;
	sub.f32 	%f109, %f53, %f33;
	mul.f32 	%f54, %f32, %f44;
	mul.f32 	%f55, %f32, %f45;
	fma.rn.f32 	%f56, %f109, %f40, %f54;
	fma.rn.f32 	%f57, %f109, %f41, %f55;
	fma.rn.f32 	%f58, %f33, %f48, %f56;
	fma.rn.f32 	%f59, %f33, %f49, %f57;
	ld.global.u32 	%r12, [%rd28];
	shr.u32 	%r13, %r12, 16;
	abs.f32 	%f60, %f58;
	cvt.rmi.f32.f32 	%f61, %f60;
	sub.f32 	%f62, %f60, %f61;
	abs.f32 	%f63, %f59;
	cvt.rmi.f32.f32 	%f64, %f63;
	sub.f32 	%f65, %f63, %f64;
	cvta.to.global.u64 	%rd37, %rd23;
	shl.b32 	%r14, %r12, 4;
	cvt.u64.u32 	%rd38, %r14;
	and.b64  	%rd39, %rd38, 1048560;
	add.s64 	%rd40, %rd37, %rd39;
	ld.global.v2.u32 	{%r15, %r16}, [%rd40];
	cvt.rn.f32.u32 	%f66, %r15;
	mul.f32 	%f67, %f62, %f66;
	cvt.rzi.u32.f32 	%r19, %f67;
	cvt.rn.f32.u32 	%f68, %r16;
	mul.f32 	%f69, %f65, %f68;
	cvt.rzi.u32.f32 	%r20, %f69;
	mad.lo.s32 	%r21, %r15, %r20, %r19;
	cvt.u64.u32 	%rd41, %r21;
	ld.global.u64 	%rd42, [%rd40+8];
	add.s64 	%rd43, %rd42, %rd41;
	ld.u8 	%r22, [%rd43];
	and.b32  	%r23, %r13, %r22;
	setp.eq.s32 	%p4, %r23, 0;
	selp.f32 	%f118, 0f00000000, 0f3F800000, %p4;

$L__BB0_5:
	cvt.u32.u64 	%r24, %rd2;
	cvt.u32.u64 	%r25, %rd3;
	cvt.u32.u64 	%r26, %rd4;
	ld.const.u64 	%rd44, [params+16];
	cvta.to.global.u64 	%rd45, %rd44;
	mul.wide.s32 	%rd46, %r24, 32;
	add.s64 	%rd47, %rd45, %rd46;
	mul.wide.s32 	%rd48, %r25, 32;
	add.s64 	%rd49, %rd45, %rd48;
	add.s64 	%rd5, %rd49, 12;
	mul.wide.s32 	%rd50, %r26, 32;
	add.s64 	%rd51, %rd45, %rd50;
	add.s64 	%rd6, %rd51, 12;
	ld.global.f32 	%f72, [%rd47+12];
	ld.global.f32 	%f73, [%rd47+16];
	ld.global.f32 	%f74, [%rd47+20];
	ld.global.f32 	%f75, [%rd49+12];
	mul.f32 	%f76, %f32, %f75;
	ld.global.f32 	%f77, [%rd49+16];
	mul.f32 	%f78, %f32, %f77;
	ld.global.f32 	%f79, [%rd49+20];
	mul.f32 	%f80, %f32, %f79;
	fma.rn.f32 	%f81, %f109, %f72, %f76;
	fma.rn.f32 	%f82, %f109, %f73, %f78;
	fma.rn.f32 	%f83, %f109, %f74, %f80;
	ld.global.f32 	%f84, [%rd51+12];
	ld.global.f32 	%f85, [%rd51+16];
	ld.global.f32 	%f86, [%rd51+20];
	fma.rn.f32 	%f87, %f33, %f84, %f81;
	fma.rn.f32 	%f88, %f33, %f85, %f82;
	fma.rn.f32 	%f89, %f33, %f86, %f83;
	mul.f32 	%f90, %f88, %f88;
	fma.rn.f32 	%f91, %f87, %f87, %f90;
	fma.rn.f32 	%f92, %f89, %f89, %f91;
	sqrt.rn.f32 	%f93, %f92;
	rcp.rn.f32 	%f94, %f93;
	mul.f32 	%f113, %f87, %f94;
	mul.f32 	%f114, %f88, %f94;
	mul.f32 	%f115, %f89, %f94;
	ld.global.v2.f32 	{%f116, %f96}, [%rd47+24];
	setp.lt.f32 	%p5, %f96, 0f00000000;
	@%p5 bra 	$L__BB0_7;
	bra.uni 	$L__BB0_6;

$L__BB0_7:
	add.f32 	%f117, %f96, 0f3F800000;
	bra.uni 	$L__BB0_9;

$L__BB0_6:
	ld.global.v2.f32 	{%f97, %f98}, [%rd5+12];
	ld.global.v2.f32 	{%f99, %f100}, [%rd6+12];
	mul.f32 	%f102, %f32, %f97;
	mul.f32 	%f104, %f32, %f98;
	fma.rn.f32 	%f105, %f109, %f116, %f102;
	fma.rn.f32 	%f106, %f109, %f96, %f104;
	fma.rn.f32 	%f116, %f33, %f99, %f105;
	fma.rn.f32 	%f117, %f33, %f100, %f106;

$L__BB0_9:
	st.param.f32 	[func_retval0+0], %f113;
	st.param.f32 	[func_retval0+4], %f114;
	st.param.f32 	[func_retval0+8], %f115;
	st.param.v4.b8 	[func_retval0+12], {%rs9, %rs10, %rs11, %rs12};
	st.param.f32 	[func_retval0+16], %f116;
	st.param.f32 	[func_retval0+20], %f117;
	st.param.f32 	[func_retval0+24], %f118;
	st.param.v4.b8 	[func_retval0+28], {%rs13, %rs14, %rs15, %rs16};
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}