//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<161>;
	.reg .b16 	%rs<175>;
	.reg .f32 	%f<1260>;
	.reg .b32 	%r<359>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<106>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r55), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r56), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	ld.const.u64 	%rd28, [params+400];
	cvta.to.global.u64 	%rd29, %rd28;
	ld.const.u32 	%r61, [params+392];
	mad.lo.s32 	%r62, %r61, %r56, %r55;
	mul.wide.u32 	%rd30, %r62, 4;
	add.s64 	%rd2, %rd29, %rd30;
	ld.global.v2.u8 	{%rs16, %rs170}, [%rd2];
	or.b16  	%rs18, %rs16, %rs170;
	and.b16  	%rs19, %rs18, 255;
	setp.eq.s16 	%p7, %rs19, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs169, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs169, [%rd2+2];
	setp.eq.s16 	%p8, %rs169, 0;
	mov.f32 	%f1176, 0f00000000;
	mov.u16 	%rs170, 0;
	mov.f32 	%f1177, %f1176;
	mov.f32 	%f1178, %f1176;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f244, %rs16;
	div.rn.f32 	%f245, %f244, 0f437F0000;
	fma.rn.f32 	%f246, %f245, 0f40000000, 0fBF800000;
	and.b16  	%rs22, %rs170, 255;
	cvt.rn.f32.u16 	%f247, %rs22;
	div.rn.f32 	%f248, %f247, 0f437F0000;
	fma.rn.f32 	%f249, %f248, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f250, %rs169;
	div.rn.f32 	%f251, %f250, 0f437F0000;
	fma.rn.f32 	%f252, %f251, 0f40000000, 0fBF800000;
	mul.f32 	%f253, %f249, %f249;
	fma.rn.f32 	%f254, %f246, %f246, %f253;
	fma.rn.f32 	%f255, %f252, %f252, %f254;
	sqrt.rn.f32 	%f256, %f255;
	rcp.rn.f32 	%f257, %f256;
	mul.f32 	%f1178, %f257, %f252;
	mul.f32 	%f1177, %f257, %f249;
	mul.f32 	%f1176, %f246, %f257;

$L__BB0_4:
	ld.const.v2.u32 	{%r63, %r64}, [params];
	add.s32 	%r4, %r63, %r55;
	add.s32 	%r5, %r64, %r56;
	setp.eq.f32 	%p9, %f1176, 0f00000000;
	setp.eq.f32 	%p10, %f1177, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1178, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_131;
	bra.uni 	$L__BB0_5;

$L__BB0_131:
	ld.const.u32 	%r52, [params+104];
	and.b32  	%r314, %r52, 1;
	setp.eq.b32 	%p151, %r314, 1;
	mov.pred 	%p152, 0;
	xor.pred  	%p153, %p151, %p152;
	not.pred 	%p154, %p153;
	@%p154 bra 	$L__BB0_133;

	ld.const.u64 	%rd82, [params+144];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r315, [params+136];
	mad.lo.s32 	%r316, %r315, %r5, %r4;
	mul.wide.u32 	%rd84, %r316, 4;
	add.s64 	%rd85, %rd83, %rd84;
	mov.u16 	%rs108, 0;
	st.global.v4.u8 	[%rd85], {%rs108, %rs108, %rs108, %rs108};

$L__BB0_133:
	and.b32  	%r317, %r52, 4;
	setp.eq.s32 	%p155, %r317, 0;
	ld.const.u32 	%r358, [params+108];
	@%p155 bra 	$L__BB0_137;

	setp.eq.s32 	%p156, %r358, 0;
	ld.const.u64 	%rd86, [params+224];
	cvta.to.global.u64 	%rd87, %rd86;
	ld.const.u32 	%r318, [params+216];
	mad.lo.s32 	%r319, %r318, %r5, %r4;
	mul.wide.u32 	%rd88, %r319, 8;
	add.s64 	%rd23, %rd87, %rd88;
	@%p156 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs115, %rs116, %rs117, %rs118}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1131, %rs115;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1132, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1133, %rs117;}

	// end inline asm
	add.f32 	%f1134, %f1131, 0f00000000;
	add.f32 	%f1135, %f1132, 0f00000000;
	add.f32 	%f1136, %f1133, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1136;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1135;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f1134;}

	// end inline asm
	mov.u16 	%rs119, 0;
	st.global.v4.u16 	[%rd23], {%rs112, %rs113, %rs114, %rs119};
	bra.uni 	$L__BB0_137;

$L__BB0_5:
	ld.const.u64 	%rd31, [params+432];
	cvta.to.global.u64 	%rd32, %rd31;
	ld.const.u32 	%r67, [params+424];
	mad.lo.s32 	%r68, %r67, %r56, %r55;
	mul.wide.u32 	%rd33, %r68, 12;
	add.s64 	%rd34, %rd32, %rd33;
	ld.global.f32 	%f258, [%rd34];
	mul.f32 	%f259, %f258, 0f3456BF95;
	ld.global.f32 	%f260, [%rd34+4];
	mul.f32 	%f261, %f260, 0f3456BF95;
	ld.global.f32 	%f262, [%rd34+8];
	mul.f32 	%f263, %f262, 0f3456BF95;
	abs.f32 	%f264, %f1176;
	div.rn.f32 	%f265, %f259, %f264;
	abs.f32 	%f266, %f1177;
	div.rn.f32 	%f267, %f261, %f266;
	abs.f32 	%f268, %f1178;
	div.rn.f32 	%f269, %f263, %f268;
	abs.f32 	%f270, %f265;
	abs.f32 	%f271, %f267;
	abs.f32 	%f272, %f269;
	mov.f32 	%f273, 0f38D1B717;
	max.f32 	%f274, %f270, %f273;
	max.f32 	%f275, %f271, %f273;
	max.f32 	%f276, %f272, %f273;
	fma.rn.f32 	%f10, %f1176, %f274, %f258;
	fma.rn.f32 	%f11, %f1177, %f275, %f260;
	fma.rn.f32 	%f12, %f1178, %f276, %f262;
	ld.const.u32 	%r6, [params+588];
	setp.gt.f32 	%p14, %f264, %f268;
	neg.f32 	%f277, %f1177;
	selp.f32 	%f278, %f277, 0f00000000, %p14;
	neg.f32 	%f279, %f1178;
	selp.f32 	%f280, %f1176, %f279, %p14;
	selp.f32 	%f281, 0f00000000, %f1177, %p14;
	mul.f32 	%f282, %f280, %f280;
	fma.rn.f32 	%f283, %f278, %f278, %f282;
	fma.rn.f32 	%f284, %f281, %f281, %f283;
	sqrt.rn.f32 	%f285, %f284;
	rcp.rn.f32 	%f286, %f285;
	mul.f32 	%f13, %f278, %f286;
	mul.f32 	%f14, %f280, %f286;
	mul.f32 	%f15, %f281, %f286;
	ld.const.u64 	%rd35, [params+128];
	cvta.to.global.u64 	%rd36, %rd35;
	ld.const.u32 	%r69, [params+120];
	mad.lo.s32 	%r70, %r69, %r56, %r55;
	mul.wide.u32 	%rd37, %r70, 4;
	add.s64 	%rd38, %rd36, %rd37;
	ld.global.u32 	%r349, [%rd38];
	ld.const.u64 	%rd39, [params+464];
	cvta.to.global.u64 	%rd40, %rd39;
	ld.const.u32 	%r71, [params+456];
	mad.lo.s32 	%r72, %r71, %r56, %r55;
	mul.wide.u32 	%rd41, %r72, 4;
	add.s64 	%rd3, %rd40, %rd41;
	ld.global.v2.u8 	{%rs24, %rs173}, [%rd3];
	or.b16  	%rs26, %rs24, %rs173;
	and.b16  	%rs27, %rs26, 255;
	setp.eq.s16 	%p15, %rs27, 0;
	@%p15 bra 	$L__BB0_7;

	ld.global.u8 	%rs171, [%rd3+2];
	bra.uni 	$L__BB0_8;

$L__BB0_7:
	ld.global.u8 	%rs171, [%rd3+2];
	setp.eq.s16 	%p16, %rs171, 0;
	mov.f32 	%f1179, 0f00000000;
	mov.u16 	%rs173, 0;
	mov.u16 	%rs174, %rs173;
	mov.f32 	%f1180, %f1179;
	mov.f32 	%f1181, %f1179;
	@%p16 bra 	$L__BB0_9;

$L__BB0_8:
	mov.u16 	%rs174, %rs173;
	cvt.rn.f32.u16 	%f290, %rs24;
	div.rn.f32 	%f291, %f290, 0f437F0000;
	fma.rn.f32 	%f292, %f291, 0f40000000, 0fBF800000;
	and.b16  	%rs32, %rs174, 255;
	cvt.rn.f32.u16 	%f293, %rs32;
	div.rn.f32 	%f294, %f293, 0f437F0000;
	fma.rn.f32 	%f295, %f294, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f296, %rs171;
	div.rn.f32 	%f297, %f296, 0f437F0000;
	fma.rn.f32 	%f298, %f297, 0f40000000, 0fBF800000;
	mul.f32 	%f299, %f295, %f295;
	fma.rn.f32 	%f300, %f292, %f292, %f299;
	fma.rn.f32 	%f301, %f298, %f298, %f300;
	sqrt.rn.f32 	%f302, %f301;
	rcp.rn.f32 	%f303, %f302;
	mul.f32 	%f1181, %f303, %f298;
	mul.f32 	%f1180, %f303, %f295;
	mul.f32 	%f1179, %f292, %f303;
	mov.u16 	%rs173, %rs171;

$L__BB0_9:
	mul.f32 	%f307, %f1177, %f1181;
	mul.f32 	%f308, %f1178, %f1180;
	sub.f32 	%f309, %f307, %f308;
	mul.f32 	%f310, %f1178, %f1179;
	mul.f32 	%f311, %f1176, %f1181;
	sub.f32 	%f312, %f310, %f311;
	mul.f32 	%f313, %f1176, %f1180;
	mul.f32 	%f314, %f1177, %f1179;
	sub.f32 	%f315, %f313, %f314;
	ld.global.u8 	%rs34, [%rd3+3];
	setp.eq.s16 	%p17, %rs34, 0;
	selp.f32 	%f22, 0fBF800000, 0f3F800000, %p17;
	mul.f32 	%f316, %f309, %f22;
	mul.f32 	%f317, %f312, %f22;
	mul.f32 	%f318, %f315, %f22;
	mul.f32 	%f319, %f316, 0f00000000;
	mul.f32 	%f320, %f317, 0f00000000;
	mul.f32 	%f321, %f318, 0f00000000;
	fma.rn.f32 	%f322, %f1179, 0f3F5105EC, %f319;
	fma.rn.f32 	%f323, %f1180, 0f3F5105EC, %f320;
	fma.rn.f32 	%f324, %f1181, 0f3F5105EC, %f321;
	mul.f32 	%f23, %f1176, 0f3F13CD3A;
	add.f32 	%f24, %f23, %f322;
	mul.f32 	%f25, %f1177, 0f3F13CD3A;
	add.f32 	%f26, %f25, %f323;
	mul.f32 	%f27, %f1178, 0f3F13CD3A;
	add.f32 	%f28, %f27, %f324;
	or.b16  	%rs35, %rs24, %rs174;
	or.b16  	%rs15, %rs35, %rs173;
	and.b16  	%rs36, %rs15, 255;
	setp.eq.s16 	%p18, %rs36, 0;
	mov.f32 	%f1185, 0f00000000;
	mov.f32 	%f1182, %f1185;
	mov.f32 	%f1183, %f1185;
	mov.f32 	%f1184, %f1185;
	@%p18 bra 	$L__BB0_11;

	cvt.rn.f32.u16 	%f325, %rs24;
	div.rn.f32 	%f326, %f325, 0f437F0000;
	fma.rn.f32 	%f327, %f326, 0f40000000, 0fBF800000;
	and.b16  	%rs38, %rs174, 255;
	cvt.rn.f32.u16 	%f328, %rs38;
	div.rn.f32 	%f329, %f328, 0f437F0000;
	fma.rn.f32 	%f330, %f329, 0f40000000, 0fBF800000;
	and.b16  	%rs39, %rs173, 255;
	cvt.rn.f32.u16 	%f331, %rs39;
	div.rn.f32 	%f332, %f331, 0f437F0000;
	fma.rn.f32 	%f333, %f332, 0f40000000, 0fBF800000;
	mul.f32 	%f334, %f330, %f330;
	fma.rn.f32 	%f335, %f327, %f327, %f334;
	fma.rn.f32 	%f336, %f333, %f333, %f335;
	sqrt.rn.f32 	%f337, %f336;
	rcp.rn.f32 	%f338, %f337;
	mul.f32 	%f1184, %f338, %f333;
	mul.f32 	%f1183, %f338, %f330;
	mul.f32 	%f1182, %f327, %f338;

$L__BB0_11:
	mul.f32 	%f342, %f1177, %f1184;
	mul.f32 	%f343, %f1178, %f1183;
	sub.f32 	%f344, %f342, %f343;
	mul.f32 	%f345, %f1178, %f1182;
	mul.f32 	%f346, %f1176, %f1184;
	sub.f32 	%f347, %f345, %f346;
	mul.f32 	%f348, %f1176, %f1183;
	mul.f32 	%f349, %f1177, %f1182;
	sub.f32 	%f350, %f348, %f349;
	mul.f32 	%f351, %f344, %f22;
	mul.f32 	%f352, %f347, %f22;
	mul.f32 	%f353, %f350, %f22;
	mul.f32 	%f354, %f1182, 0f3ED105EC;
	mul.f32 	%f355, %f1183, 0f3ED105EC;
	mul.f32 	%f356, %f1184, 0f3ED105EC;
	mul.f32 	%f357, %f351, 0f3F3504F3;
	mul.f32 	%f358, %f352, 0f3F3504F3;
	mul.f32 	%f359, %f353, 0f3F3504F3;
	sub.f32 	%f360, %f357, %f354;
	sub.f32 	%f361, %f358, %f355;
	sub.f32 	%f362, %f359, %f356;
	add.f32 	%f35, %f23, %f360;
	add.f32 	%f36, %f25, %f361;
	add.f32 	%f37, %f27, %f362;
	mov.f32 	%f1186, %f1185;
	mov.f32 	%f1187, %f1185;
	@%p18 bra 	$L__BB0_13;

	cvt.rn.f32.u16 	%f363, %rs24;
	div.rn.f32 	%f364, %f363, 0f437F0000;
	fma.rn.f32 	%f365, %f364, 0f40000000, 0fBF800000;
	and.b16  	%rs42, %rs174, 255;
	cvt.rn.f32.u16 	%f366, %rs42;
	div.rn.f32 	%f367, %f366, 0f437F0000;
	fma.rn.f32 	%f368, %f367, 0f40000000, 0fBF800000;
	and.b16  	%rs43, %rs173, 255;
	cvt.rn.f32.u16 	%f369, %rs43;
	div.rn.f32 	%f370, %f369, 0f437F0000;
	fma.rn.f32 	%f371, %f370, 0f40000000, 0fBF800000;
	mul.f32 	%f372, %f368, %f368;
	fma.rn.f32 	%f373, %f365, %f365, %f372;
	fma.rn.f32 	%f374, %f371, %f371, %f373;
	sqrt.rn.f32 	%f375, %f374;
	rcp.rn.f32 	%f376, %f375;
	mul.f32 	%f1187, %f376, %f371;
	mul.f32 	%f1186, %f376, %f368;
	mul.f32 	%f1185, %f365, %f376;

$L__BB0_13:
	mul.f32 	%f389, %f1177, %f1187;
	mul.f32 	%f390, %f1178, %f1186;
	sub.f32 	%f391, %f389, %f390;
	mul.f32 	%f392, %f1178, %f1185;
	mul.f32 	%f393, %f1176, %f1187;
	sub.f32 	%f394, %f392, %f393;
	mul.f32 	%f395, %f1176, %f1186;
	mul.f32 	%f396, %f1177, %f1185;
	sub.f32 	%f397, %f395, %f396;
	mul.f32 	%f398, %f391, %f22;
	mul.f32 	%f399, %f394, %f22;
	mul.f32 	%f400, %f397, %f22;
	mul.f32 	%f401, %f1185, 0f3ED105EC;
	mul.f32 	%f402, %f1186, 0f3ED105EC;
	mul.f32 	%f403, %f1187, 0f3ED105EC;
	mul.f32 	%f404, %f398, 0fBF3504F3;
	mul.f32 	%f405, %f399, 0fBF3504F3;
	mul.f32 	%f406, %f400, 0fBF3504F3;
	sub.f32 	%f407, %f404, %f401;
	sub.f32 	%f408, %f405, %f402;
	sub.f32 	%f409, %f406, %f403;
	add.f32 	%f44, %f23, %f407;
	add.f32 	%f45, %f25, %f408;
	add.f32 	%f46, %f27, %f409;
	setp.lt.s32 	%p20, %r3, 1;
	mov.f32 	%f1218, 0f00000000;
	mov.f32 	%f1219, %f1218;
	mov.f32 	%f1220, %f1218;
	mov.f32 	%f1221, %f1218;
	mov.f32 	%f1222, %f1218;
	mov.f32 	%f1223, %f1218;
	mov.f32 	%f1224, %f1218;
	mov.f32 	%f1225, %f1218;
	mov.f32 	%f1226, %f1218;
	mov.f32 	%f1227, %f1218;
	mov.f32 	%f1228, %f1218;
	mov.f32 	%f1229, %f1218;
	@%p20 bra 	$L__BB0_44;

	cvt.rn.f32.s32 	%f422, %r3;
	rcp.rn.f32 	%f47, %f422;
	mul.f32 	%f48, %f10, 0f3456BF95;
	mul.f32 	%f49, %f11, 0f3456BF95;
	mul.f32 	%f50, %f12, 0f3456BF95;
	ld.const.u64 	%rd4, [params+592];
	ld.const.u64 	%rd5, [params+96];
	mul.f32 	%f423, %f1178, %f14;
	mul.f32 	%f424, %f1177, %f15;
	sub.f32 	%f51, %f423, %f424;
	mul.f32 	%f425, %f1176, %f15;
	mul.f32 	%f426, %f1178, %f13;
	sub.f32 	%f52, %f425, %f426;
	mul.f32 	%f427, %f1177, %f13;
	mul.f32 	%f428, %f1176, %f14;
	sub.f32 	%f53, %f427, %f428;
	mov.u32 	%r73, 0;
	add.s64 	%rd6, %rd1, 24;
	mov.u64 	%rd42, __cudart_i2opi_f;
	abs.f32 	%f491, %f48;
	abs.f32 	%f492, %f49;
	max.f32 	%f493, %f491, %f492;
	abs.f32 	%f494, %f50;
	max.f32 	%f495, %f493, %f494;
	mov.u32 	%r346, %r73;

$L__BB0_15:
	mov.u32 	%r348, %r73;

$L__BB0_16:
	cvt.rn.f32.s32 	%f1168, %r346;
	mad.lo.s32 	%r75, %r349, 1664525, 1013904223;
	and.b32  	%r76, %r75, 16777215;
	cvt.rn.f32.u32 	%f429, %r76;
	fma.rn.f32 	%f430, %f429, 0f33800000, %f1168;
	mul.f32 	%f79, %f47, %f430;
	mad.lo.s32 	%r349, %r75, 1664525, 1013904223;
	and.b32  	%r77, %r349, 16777215;
	cvt.rn.f32.u32 	%f431, %r77;
	cvt.rn.f32.s32 	%f432, %r348;
	fma.rn.f32 	%f433, %f431, 0f33800000, %f432;
	mul.f32 	%f434, %f47, %f433;
	mul.f32 	%f435, %f79, %f79;
	mov.f32 	%f436, 0f3F800000;
	sub.f32 	%f437, %f436, %f435;
	mov.f32 	%f438, 0f00000000;
	max.f32 	%f439, %f438, %f437;
	sqrt.rn.f32 	%f80, %f439;
	mul.f32 	%f81, %f434, 0f40C90FDB;
	mul.f32 	%f440, %f81, 0f3F22F983;
	cvt.rni.s32.f32 	%r353, %f440;
	cvt.rn.f32.s32 	%f441, %r353;
	mov.f32 	%f442, 0fBFC90FDA;
	fma.rn.f32 	%f443, %f441, %f442, %f81;
	mov.f32 	%f444, 0fB3A22168;
	fma.rn.f32 	%f445, %f441, %f444, %f443;
	mov.f32 	%f446, 0fA7C234C5;
	fma.rn.f32 	%f1215, %f441, %f446, %f445;
	abs.f32 	%f83, %f81;
	setp.ltu.f32 	%p21, %f83, 0f47CE4780;
	mov.f32 	%f1212, %f1215;
	@%p21 bra 	$L__BB0_24;

	setp.eq.f32 	%p22, %f83, 0f7F800000;
	@%p22 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_18;

$L__BB0_23:
	mov.f32 	%f449, 0f00000000;
	mul.rn.f32 	%f1212, %f81, %f449;
	mov.u32 	%r353, 0;
	bra.uni 	$L__BB0_24;

$L__BB0_18:
	mov.b32 	%r14, %f81;
	bfe.u32 	%r79, %r14, 23, 8;
	mov.u64 	%rd103, 0;
	mov.u32 	%r350, 0;
	mov.u64 	%rd101, %rd1;
	mov.u64 	%rd102, %rd42;

$L__BB0_19:
	.pragma "nounroll";
	mov.b32 	%r329, %f81;
	shl.b32 	%r328, %r329, 8;
	or.b32  	%r327, %r328, -2147483648;
	ld.global.nc.u32 	%r81, [%rd102];
	mad.wide.u32 	%rd44, %r81, %r327, %rd103;
	shr.u64 	%rd103, %rd44, 32;
	st.local.u32 	[%rd101], %rd44;
	add.s64 	%rd102, %rd102, 4;
	add.s64 	%rd101, %rd101, 4;
	add.s32 	%r350, %r350, 1;
	setp.ne.s32 	%p23, %r350, 6;
	@%p23 bra 	$L__BB0_19;

	add.s32 	%r334, %r79, -128;
	mov.b32 	%r333, %f81;
	bfe.u32 	%r332, %r333, 23, 8;
	add.s32 	%r331, %r332, -128;
	shr.u32 	%r330, %r331, 5;
	st.local.u32 	[%rd6], %rd103;
	mov.u32 	%r83, 6;
	sub.s32 	%r84, %r83, %r330;
	mul.wide.s32 	%rd45, %r84, 4;
	add.s64 	%rd46, %rd1, %rd45;
	ld.local.u32 	%r351, [%rd46];
	ld.local.u32 	%r352, [%rd46+-4];
	and.b32  	%r23, %r331, 31;
	setp.eq.s32 	%p24, %r23, 0;
	@%p24 bra 	$L__BB0_22;

	mov.b32 	%r342, %f81;
	bfe.u32 	%r341, %r342, 23, 8;
	add.s32 	%r340, %r341, -128;
	shr.u32 	%r339, %r340, 5;
	mov.u32 	%r338, 4;
	sub.s32 	%r337, %r338, %r339;
	mov.u32 	%r85, 32;
	sub.s32 	%r86, %r85, %r23;
	shr.u32 	%r87, %r352, %r86;
	shl.b32 	%r88, %r351, %r23;
	add.s32 	%r351, %r87, %r88;
	mul.wide.s32 	%rd47, %r337, 4;
	add.s64 	%rd48, %rd1, %rd47;
	ld.local.u32 	%r89, [%rd48];
	shr.u32 	%r90, %r89, %r86;
	shl.b32 	%r91, %r352, %r23;
	add.s32 	%r352, %r90, %r91;

$L__BB0_22:
	mov.b32 	%r335, %f81;
	and.b32  	%r92, %r335, -2147483648;
	shr.u32 	%r93, %r352, 30;
	shl.b32 	%r94, %r351, 2;
	or.b32  	%r95, %r93, %r94;
	shr.u32 	%r96, %r95, 31;
	shr.u32 	%r97, %r351, 30;
	add.s32 	%r98, %r96, %r97;
	neg.s32 	%r99, %r98;
	setp.eq.s32 	%p25, %r92, 0;
	selp.b32 	%r353, %r98, %r99, %p25;
	setp.ne.s32 	%p26, %r96, 0;
	xor.b32  	%r100, %r92, -2147483648;
	selp.b32 	%r101, %r100, %r92, %p26;
	selp.b32 	%r102, -1, 0, %p26;
	xor.b32  	%r103, %r95, %r102;
	shl.b32 	%r104, %r352, 2;
	xor.b32  	%r105, %r104, %r102;
	cvt.u64.u32 	%rd49, %r103;
	cvt.u64.u32 	%rd50, %r105;
	bfi.b64 	%rd51, %rd49, %rd50, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd51;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f447, %fd2;
	setp.eq.s32 	%p27, %r101, 0;
	neg.f32 	%f448, %f447;
	selp.f32 	%f1212, %f447, %f448, %p27;

$L__BB0_24:
	add.s32 	%r30, %r353, 1;
	and.b32  	%r31, %r30, 1;
	setp.eq.s32 	%p28, %r31, 0;
	selp.f32 	%f87, %f1212, 0f3F800000, %p28;
	mul.rn.f32 	%f88, %f1212, %f1212;
	mov.f32 	%f1213, 0fB94D4153;
	@%p28 bra 	$L__BB0_26;

	mov.f32 	%f451, 0fBAB607ED;
	mov.f32 	%f452, 0f37CBAC00;
	fma.rn.f32 	%f1213, %f452, %f88, %f451;

$L__BB0_26:
	selp.f32 	%f453, 0f3C0885E4, 0f3D2AAABB, %p28;
	fma.rn.f32 	%f454, %f1213, %f88, %f453;
	selp.f32 	%f455, 0fBE2AAAA8, 0fBEFFFFFF, %p28;
	fma.rn.f32 	%f456, %f454, %f88, %f455;
	mov.f32 	%f457, 0f00000000;
	fma.rn.f32 	%f458, %f88, %f87, %f457;
	fma.rn.f32 	%f1214, %f456, %f458, %f87;
	and.b32  	%r107, %r30, 2;
	setp.eq.s32 	%p30, %r107, 0;
	@%p30 bra 	$L__BB0_28;

	mov.f32 	%f460, 0fBF800000;
	fma.rn.f32 	%f1214, %f1214, %f460, %f457;

$L__BB0_28:
	mul.f32 	%f1167, %f81, 0f3F22F983;
	cvt.rni.s32.f32 	%r356, %f1167;
	setp.ltu.f32 	%p160, %f83, 0f47CE4780;
	@%p160 bra 	$L__BB0_36;

	setp.eq.f32 	%p32, %f83, 0f7F800000;
	@%p32 bra 	$L__BB0_35;
	bra.uni 	$L__BB0_30;

$L__BB0_35:
	mov.f32 	%f463, 0f00000000;
	mul.rn.f32 	%f1215, %f81, %f463;
	mov.u32 	%r356, 0;
	bra.uni 	$L__BB0_36;

$L__BB0_30:
	mov.b32 	%r32, %f81;
	bfe.u32 	%r108, %r32, 23, 8;
	add.s32 	%r33, %r108, -128;
	shl.b32 	%r109, %r32, 8;
	or.b32  	%r34, %r109, -2147483648;
	shr.u32 	%r35, %r33, 5;
	mov.u64 	%rd104, 0;
	mov.u64 	%rd105, %rd104;

$L__BB0_31:
	.pragma "nounroll";
	shl.b64 	%rd54, %rd104, 2;
	mov.u64 	%rd55, __cudart_i2opi_f;
	add.s64 	%rd56, %rd55, %rd54;
	ld.global.nc.u32 	%r110, [%rd56];
	mad.wide.u32 	%rd57, %r110, %r34, %rd105;
	shr.u64 	%rd105, %rd57, 32;
	add.s64 	%rd58, %rd1, %rd54;
	st.local.u32 	[%rd58], %rd57;
	cvt.u32.u64 	%r111, %rd104;
	add.s32 	%r112, %r111, 1;
	cvt.s64.s32 	%rd104, %r112;
	setp.ne.s32 	%p33, %r112, 6;
	@%p33 bra 	$L__BB0_31;

	st.local.u32 	[%rd6], %rd105;
	mov.u32 	%r113, 4;
	sub.s32 	%r36, %r113, %r35;
	mov.u32 	%r114, 6;
	sub.s32 	%r115, %r114, %r35;
	mul.wide.s32 	%rd59, %r115, 4;
	add.s64 	%rd60, %rd1, %rd59;
	ld.local.u32 	%r354, [%rd60];
	ld.local.u32 	%r355, [%rd60+-4];
	and.b32  	%r39, %r33, 31;
	setp.eq.s32 	%p34, %r39, 0;
	@%p34 bra 	$L__BB0_34;

	mov.u32 	%r116, 32;
	sub.s32 	%r117, %r116, %r39;
	shr.u32 	%r118, %r355, %r117;
	shl.b32 	%r119, %r354, %r39;
	add.s32 	%r354, %r118, %r119;
	mul.wide.s32 	%rd61, %r36, 4;
	add.s64 	%rd62, %rd1, %rd61;
	ld.local.u32 	%r120, [%rd62];
	shr.u32 	%r121, %r120, %r117;
	shl.b32 	%r122, %r355, %r39;
	add.s32 	%r355, %r121, %r122;

$L__BB0_34:
	and.b32  	%r123, %r32, -2147483648;
	shr.u32 	%r124, %r355, 30;
	shl.b32 	%r125, %r354, 2;
	or.b32  	%r126, %r124, %r125;
	shr.u32 	%r127, %r126, 31;
	shr.u32 	%r128, %r354, 30;
	add.s32 	%r129, %r127, %r128;
	neg.s32 	%r130, %r129;
	setp.eq.s32 	%p35, %r123, 0;
	selp.b32 	%r356, %r129, %r130, %p35;
	setp.ne.s32 	%p36, %r127, 0;
	xor.b32  	%r131, %r123, -2147483648;
	selp.b32 	%r132, %r131, %r123, %p36;
	selp.b32 	%r133, -1, 0, %p36;
	xor.b32  	%r134, %r126, %r133;
	shl.b32 	%r135, %r355, 2;
	xor.b32  	%r136, %r135, %r133;
	cvt.u64.u32 	%rd63, %r134;
	cvt.u64.u32 	%rd64, %r136;
	bfi.b64 	%rd65, %rd63, %rd64, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd65;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f461, %fd4;
	setp.eq.s32 	%p37, %r132, 0;
	neg.f32 	%f462, %f461;
	selp.f32 	%f1215, %f461, %f462, %p37;

$L__BB0_36:
	mul.f32 	%f97, %f80, %f1214;
	and.b32  	%r46, %r356, 1;
	setp.eq.s32 	%p38, %r46, 0;
	mul.rn.f32 	%f99, %f1215, %f1215;
	mov.f32 	%f1216, 0fB94D4153;
	@%p38 bra 	$L__BB0_38;

	mov.f32 	%f465, 0fBAB607ED;
	mov.f32 	%f466, 0f37CBAC00;
	fma.rn.f32 	%f1216, %f466, %f99, %f465;

$L__BB0_38:
	selp.f32 	%f1169, %f1215, 0f3F800000, %p38;
	selp.f32 	%f467, 0f3C0885E4, 0f3D2AAABB, %p38;
	fma.rn.f32 	%f468, %f1216, %f99, %f467;
	selp.f32 	%f469, 0fBE2AAAA8, 0fBEFFFFFF, %p38;
	fma.rn.f32 	%f470, %f468, %f99, %f469;
	mov.f32 	%f471, 0f00000000;
	fma.rn.f32 	%f472, %f99, %f1169, %f471;
	fma.rn.f32 	%f1217, %f470, %f472, %f1169;
	and.b32  	%r138, %r356, 2;
	setp.eq.s32 	%p40, %r138, 0;
	@%p40 bra 	$L__BB0_40;

	mov.f32 	%f474, 0fBF800000;
	fma.rn.f32 	%f1217, %f1217, %f474, %f471;

$L__BB0_40:
	mul.f32 	%f475, %f80, %f1217;
	mul.f32 	%f476, %f13, %f475;
	mul.f32 	%f477, %f14, %f475;
	mul.f32 	%f478, %f15, %f475;
	fma.rn.f32 	%f479, %f51, %f97, %f476;
	fma.rn.f32 	%f480, %f52, %f97, %f477;
	fma.rn.f32 	%f481, %f53, %f97, %f478;
	fma.rn.f32 	%f105, %f1176, %f79, %f479;
	fma.rn.f32 	%f106, %f1177, %f79, %f480;
	fma.rn.f32 	%f107, %f1178, %f79, %f481;
	setp.leu.f32 	%p41, %f106, 0f00000000;
	setp.ne.s32 	%p42, %r6, 0;
	and.pred  	%p43, %p42, %p41;
	@%p43 bra 	$L__BB0_42;

	mov.f32 	%f496, 0f38D1B717;
	max.f32 	%f488, %f495, %f496;
	neg.f32 	%f497, %f105;
	neg.f32 	%f498, %f106;
	neg.f32 	%f499, %f107;
	tex.cube.v4.f32.f32 	{%f500, %f501, %f502, %f503}, [%rd4, {%f499, %f498, %f497, %f497}];
	mov.b32 	%r178, %f500;
	mov.b32 	%r179, %f501;
	mov.b32 	%r180, %f502;
	mov.f32 	%f489, 0f6C4ECB8F;
	mov.f32 	%f490, 0f00000000;
	mov.u32 	%r175, 2;
	mov.u32 	%r176, 1;
	mov.u32 	%r177, 3;
	mov.u32 	%r209, 0;
	// begin inline asm
	call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd5,%f10,%f11,%f12,%f105,%f106,%f107,%f488,%f489,%f490,%r176,%r209,%r176,%r175,%r176,%r177,%r178,%r179,%r180,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
	// end inline asm
	mov.b32 	%f504, %r139;
	mov.b32 	%f505, %r140;
	mov.b32 	%f506, %r141;
	mul.f32 	%f507, %f26, %f106;
	fma.rn.f32 	%f508, %f24, %f105, %f507;
	fma.rn.f32 	%f509, %f28, %f107, %f508;
	cvt.sat.f32.f32 	%f510, %f509;
	fma.rn.f32 	%f1224, %f510, %f504, %f1224;
	fma.rn.f32 	%f1225, %f510, %f505, %f1225;
	fma.rn.f32 	%f1226, %f510, %f506, %f1226;
	mul.f32 	%f511, %f36, %f106;
	fma.rn.f32 	%f512, %f35, %f105, %f511;
	fma.rn.f32 	%f513, %f37, %f107, %f512;
	cvt.sat.f32.f32 	%f514, %f513;
	fma.rn.f32 	%f1221, %f514, %f504, %f1221;
	fma.rn.f32 	%f1222, %f514, %f505, %f1222;
	fma.rn.f32 	%f1223, %f514, %f506, %f1223;
	mul.f32 	%f515, %f45, %f106;
	fma.rn.f32 	%f516, %f44, %f105, %f515;
	fma.rn.f32 	%f517, %f46, %f107, %f516;
	cvt.sat.f32.f32 	%f518, %f517;
	fma.rn.f32 	%f1218, %f518, %f504, %f1218;
	fma.rn.f32 	%f1219, %f518, %f505, %f1219;
	fma.rn.f32 	%f1220, %f518, %f506, %f1220;
	mul.f32 	%f519, %f1177, %f106;
	fma.rn.f32 	%f520, %f1176, %f105, %f519;
	fma.rn.f32 	%f521, %f1178, %f107, %f520;
	cvt.sat.f32.f32 	%f522, %f521;
	fma.rn.f32 	%f1227, %f522, %f504, %f1227;
	fma.rn.f32 	%f1228, %f522, %f505, %f1228;
	fma.rn.f32 	%f1229, %f522, %f506, %f1229;

$L__BB0_42:
	add.s32 	%r348, %r348, 1;
	setp.lt.s32 	%p44, %r348, %r3;
	@%p44 bra 	$L__BB0_16;

	add.s32 	%r346, %r346, 1;
	setp.lt.s32 	%p45, %r346, %r3;
	@%p45 bra 	$L__BB0_15;

$L__BB0_44:
	mul.lo.s32 	%r210, %r3, %r3;
	cvt.rn.f32.s32 	%f523, %r210;
	rcp.rn.f32 	%f524, %f523;
	mul.f32 	%f525, %f524, %f1227;
	mul.f32 	%f526, %f524, %f1228;
	mul.f32 	%f527, %f524, %f1229;
	mul.f32 	%f144, %f524, %f1224;
	mul.f32 	%f145, %f524, %f1225;
	mul.f32 	%f146, %f524, %f1226;
	mul.f32 	%f147, %f524, %f1221;
	mul.f32 	%f148, %f524, %f1222;
	mul.f32 	%f149, %f524, %f1223;
	mul.f32 	%f150, %f524, %f1218;
	mul.f32 	%f151, %f524, %f1219;
	mul.f32 	%f152, %f524, %f1220;
	fma.rn.f32 	%f528, %f524, %f1227, %f525;
	fma.rn.f32 	%f529, %f524, %f1228, %f526;
	fma.rn.f32 	%f530, %f524, %f1229, %f527;
	ld.const.v4.f32 	{%f531, %f532, %f533, %f534}, [params+576];
	mul.f32 	%f156, %f528, %f531;
	mul.f32 	%f157, %f529, %f532;
	mul.f32 	%f158, %f530, %f533;
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r211, %r49, 1;
	setp.eq.b32 	%p46, %r211, 1;
	mov.pred 	%p47, 0;
	xor.pred  	%p48, %p46, %p47;
	not.pred 	%p49, %p48;
	@%p49 bra 	$L__BB0_118;

	mov.f32 	%f536, 0f3E666666;
	cvt.rzi.f32.f32 	%f537, %f536;
	add.f32 	%f538, %f537, %f537;
	mov.f32 	%f539, 0f3EE66666;
	sub.f32 	%f540, %f539, %f538;
	abs.f32 	%f159, %f540;
	abs.f32 	%f160, %f156;
	setp.lt.f32 	%p50, %f160, 0f00800000;
	mul.f32 	%f541, %f160, 0f4B800000;
	selp.f32 	%f542, %f541, %f160, %p50;
	selp.f32 	%f543, 0fC3170000, 0fC2FE0000, %p50;
	mov.b32 	%r212, %f542;
	and.b32  	%r213, %r212, 8388607;
	or.b32  	%r214, %r213, 1065353216;
	mov.b32 	%f544, %r214;
	shr.u32 	%r215, %r212, 23;
	cvt.rn.f32.u32 	%f545, %r215;
	add.f32 	%f546, %f543, %f545;
	setp.gt.f32 	%p51, %f544, 0f3FB504F3;
	mul.f32 	%f547, %f544, 0f3F000000;
	add.f32 	%f548, %f546, 0f3F800000;
	selp.f32 	%f549, %f548, %f546, %p51;
	selp.f32 	%f550, %f547, %f544, %p51;
	add.f32 	%f551, %f550, 0fBF800000;
	add.f32 	%f552, %f550, 0f3F800000;
	rcp.approx.ftz.f32 	%f553, %f552;
	add.f32 	%f554, %f551, %f551;
	mul.f32 	%f555, %f554, %f553;
	mul.f32 	%f556, %f555, %f555;
	mov.f32 	%f557, 0f3C4CAF63;
	mov.f32 	%f558, 0f3B18F0FE;
	fma.rn.f32 	%f559, %f558, %f556, %f557;
	mov.f32 	%f560, 0f3DAAAABD;
	fma.rn.f32 	%f561, %f559, %f556, %f560;
	mul.rn.f32 	%f562, %f561, %f556;
	mul.rn.f32 	%f563, %f562, %f555;
	sub.f32 	%f564, %f551, %f555;
	add.f32 	%f565, %f564, %f564;
	neg.f32 	%f566, %f555;
	fma.rn.f32 	%f567, %f566, %f551, %f565;
	mul.rn.f32 	%f568, %f553, %f567;
	add.f32 	%f569, %f563, %f555;
	sub.f32 	%f570, %f555, %f569;
	add.f32 	%f571, %f563, %f570;
	add.f32 	%f572, %f568, %f571;
	add.f32 	%f573, %f569, %f572;
	sub.f32 	%f574, %f569, %f573;
	add.f32 	%f575, %f572, %f574;
	mov.f32 	%f576, 0f3F317200;
	mul.rn.f32 	%f577, %f549, %f576;
	mov.f32 	%f578, 0f35BFBE8E;
	mul.rn.f32 	%f579, %f549, %f578;
	add.f32 	%f580, %f577, %f573;
	sub.f32 	%f581, %f577, %f580;
	add.f32 	%f582, %f573, %f581;
	add.f32 	%f583, %f575, %f582;
	add.f32 	%f584, %f579, %f583;
	add.f32 	%f585, %f580, %f584;
	sub.f32 	%f586, %f580, %f585;
	add.f32 	%f587, %f584, %f586;
	mul.rn.f32 	%f588, %f539, %f585;
	neg.f32 	%f589, %f588;
	fma.rn.f32 	%f590, %f539, %f585, %f589;
	fma.rn.f32 	%f591, %f539, %f587, %f590;
	mov.f32 	%f592, 0f00000000;
	fma.rn.f32 	%f593, %f592, %f585, %f591;
	add.rn.f32 	%f594, %f588, %f593;
	neg.f32 	%f595, %f594;
	add.rn.f32 	%f596, %f588, %f595;
	add.rn.f32 	%f597, %f596, %f593;
	mov.b32 	%r216, %f594;
	setp.eq.s32 	%p52, %r216, 1118925336;
	add.s32 	%r217, %r216, -1;
	mov.b32 	%f598, %r217;
	add.f32 	%f599, %f597, 0f37000000;
	selp.f32 	%f161, %f599, %f597, %p52;
	selp.f32 	%f600, %f598, %f594, %p52;
	mov.f32 	%f601, 0f3FB8AA3B;
	mul.rn.f32 	%f602, %f600, %f601;
	cvt.rzi.f32.f32 	%f603, %f602;
	abs.f32 	%f604, %f603;
	setp.gt.f32 	%p53, %f604, 0f42FC0000;
	mov.b32 	%r218, %f603;
	and.b32  	%r219, %r218, -2147483648;
	or.b32  	%r220, %r219, 1123811328;
	mov.b32 	%f605, %r220;
	selp.f32 	%f606, %f605, %f603, %p53;
	mov.f32 	%f607, 0fBF317218;
	fma.rn.f32 	%f608, %f606, %f607, %f600;
	mov.f32 	%f609, 0f3102E308;
	fma.rn.f32 	%f610, %f606, %f609, %f608;
	mul.f32 	%f611, %f610, 0f3FB8AA3B;
	add.f32 	%f612, %f606, 0f4B40007F;
	mov.b32 	%r221, %f612;
	shl.b32 	%r222, %r221, 23;
	mov.b32 	%f613, %r222;
	ex2.approx.ftz.f32 	%f614, %f611;
	mul.f32 	%f162, %f614, %f613;
	setp.eq.f32 	%p54, %f162, 0f7F800000;
	mov.f32 	%f1242, 0f7F800000;
	@%p54 bra 	$L__BB0_47;

	fma.rn.f32 	%f1242, %f162, %f161, %f162;

$L__BB0_47:
	setp.lt.f32 	%p55, %f156, 0f00000000;
	setp.eq.f32 	%p56, %f159, 0f3F800000;
	and.pred  	%p1, %p55, %p56;
	setp.eq.f32 	%p57, %f156, 0f00000000;
	@%p57 bra 	$L__BB0_51;
	bra.uni 	$L__BB0_48;

$L__BB0_51:
	add.f32 	%f619, %f156, %f156;
	selp.f32 	%f1244, %f619, 0f00000000, %p56;
	bra.uni 	$L__BB0_52;

$L__BB0_136:
	mov.f32 	%f1139, 0f00000000;
	mov.u32 	%r358, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1139;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1139;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1139;}

	// end inline asm
	mov.u16 	%rs123, 0;
	st.global.v4.u16 	[%rd23], {%rs120, %rs121, %rs122, %rs123};

$L__BB0_137:
	ld.const.u64 	%rd89, [params+256];
	cvta.to.global.u64 	%rd90, %rd89;
	ld.const.u32 	%r321, [params+248];
	mad.lo.s32 	%r322, %r321, %r5, %r4;
	mul.wide.u32 	%rd91, %r322, 8;
	add.s64 	%rd24, %rd90, %rd91;
	setp.eq.s32 	%p157, %r358, 0;
	@%p157 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs130, %rs131, %rs132, %rs133}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1140, %rs130;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1141, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1142, %rs132;}

	// end inline asm
	add.f32 	%f1143, %f1140, 0f00000000;
	add.f32 	%f1144, %f1141, 0f00000000;
	add.f32 	%f1145, %f1142, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1145;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1144;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1143;}

	// end inline asm
	mov.u16 	%rs134, 0;
	st.global.v4.u16 	[%rd24], {%rs127, %rs128, %rs129, %rs134};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1148, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1148;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1148;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1148;}

	// end inline asm
	mov.u16 	%rs138, 0;
	st.global.v4.u16 	[%rd24], {%rs135, %rs136, %rs137, %rs138};

$L__BB0_140:
	ld.const.u64 	%rd92, [params+272];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r323, [params+264];
	mad.lo.s32 	%r324, %r323, %r5, %r4;
	mul.wide.u32 	%rd94, %r324, 8;
	add.s64 	%rd25, %rd93, %rd94;
	@%p157 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs145, %rs146, %rs147, %rs148}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1149, %rs145;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1150, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1151, %rs147;}

	// end inline asm
	add.f32 	%f1152, %f1149, 0f00000000;
	add.f32 	%f1153, %f1150, 0f00000000;
	add.f32 	%f1154, %f1151, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1154;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1153;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1152;}

	// end inline asm
	mov.u16 	%rs149, 0;
	st.global.v4.u16 	[%rd25], {%rs142, %rs143, %rs144, %rs149};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1157, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1157;}

	// end inline asm
	mov.u16 	%rs153, 0;
	st.global.v4.u16 	[%rd25], {%rs150, %rs151, %rs152, %rs153};

$L__BB0_143:
	ld.const.u64 	%rd95, [params+288];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r325, [params+280];
	mad.lo.s32 	%r326, %r325, %r5, %r4;
	mul.wide.u32 	%rd97, %r326, 8;
	add.s64 	%rd26, %rd96, %rd97;
	@%p157 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs160, %rs161, %rs162, %rs163}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1158, %rs160;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1159, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1160, %rs162;}

	// end inline asm
	add.f32 	%f1161, %f1158, 0f00000000;
	add.f32 	%f1162, %f1159, 0f00000000;
	add.f32 	%f1163, %f1160, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1163;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1162;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1161;}

	// end inline asm
	mov.u16 	%rs164, 0;
	st.global.v4.u16 	[%rd26], {%rs157, %rs158, %rs159, %rs164};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1166, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1166;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1166;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1166;}

	// end inline asm
	mov.u16 	%rs168, 0;
	st.global.v4.u16 	[%rd26], {%rs165, %rs166, %rs167, %rs168};
	bra.uni 	$L__BB0_146;

$L__BB0_48:
	mov.b32 	%r223, %f1242;
	xor.b32  	%r224, %r223, -2147483648;
	mov.b32 	%f615, %r224;
	selp.f32 	%f1244, %f615, %f1242, %p1;
	setp.geu.f32 	%p58, %f156, 0f00000000;
	@%p58 bra 	$L__BB0_52;

	mov.f32 	%f616, 0f3EE66666;
	cvt.rzi.f32.f32 	%f617, %f616;
	setp.eq.f32 	%p59, %f617, 0f3EE66666;
	@%p59 bra 	$L__BB0_52;

	mov.f32 	%f1244, 0f7FFFFFFF;

$L__BB0_52:
	add.f32 	%f620, %f160, 0f3EE66666;
	mov.b32 	%r225, %f620;
	setp.lt.s32 	%p61, %r225, 2139095040;
	@%p61 bra 	$L__BB0_57;

	setp.gtu.f32 	%p62, %f160, 0f7F800000;
	@%p62 bra 	$L__BB0_56;
	bra.uni 	$L__BB0_54;

$L__BB0_56:
	add.f32 	%f1244, %f156, 0f3EE66666;
	bra.uni 	$L__BB0_57;

$L__BB0_54:
	setp.neu.f32 	%p63, %f160, 0f7F800000;
	@%p63 bra 	$L__BB0_57;

	selp.f32 	%f1244, 0fFF800000, 0f7F800000, %p1;

$L__BB0_57:
	setp.eq.f32 	%p64, %f156, 0f3F800000;
	selp.f32 	%f171, 0f3F800000, %f1244, %p64;
	abs.f32 	%f172, %f157;
	setp.lt.f32 	%p65, %f172, 0f00800000;
	mul.f32 	%f622, %f172, 0f4B800000;
	selp.f32 	%f623, %f622, %f172, %p65;
	selp.f32 	%f624, 0fC3170000, 0fC2FE0000, %p65;
	mov.b32 	%r226, %f623;
	and.b32  	%r227, %r226, 8388607;
	or.b32  	%r228, %r227, 1065353216;
	mov.b32 	%f625, %r228;
	shr.u32 	%r229, %r226, 23;
	cvt.rn.f32.u32 	%f626, %r229;
	add.f32 	%f627, %f624, %f626;
	setp.gt.f32 	%p66, %f625, 0f3FB504F3;
	mul.f32 	%f628, %f625, 0f3F000000;
	add.f32 	%f629, %f627, 0f3F800000;
	selp.f32 	%f630, %f629, %f627, %p66;
	selp.f32 	%f631, %f628, %f625, %p66;
	add.f32 	%f632, %f631, 0fBF800000;
	add.f32 	%f633, %f631, 0f3F800000;
	rcp.approx.ftz.f32 	%f634, %f633;
	add.f32 	%f635, %f632, %f632;
	mul.f32 	%f636, %f635, %f634;
	mul.f32 	%f637, %f636, %f636;
	mov.f32 	%f638, 0f3C4CAF63;
	mov.f32 	%f639, 0f3B18F0FE;
	fma.rn.f32 	%f640, %f639, %f637, %f638;
	mov.f32 	%f641, 0f3DAAAABD;
	fma.rn.f32 	%f642, %f640, %f637, %f641;
	mul.rn.f32 	%f643, %f642, %f637;
	mul.rn.f32 	%f644, %f643, %f636;
	sub.f32 	%f645, %f632, %f636;
	add.f32 	%f646, %f645, %f645;
	neg.f32 	%f647, %f636;
	fma.rn.f32 	%f648, %f647, %f632, %f646;
	mul.rn.f32 	%f649, %f634, %f648;
	add.f32 	%f650, %f644, %f636;
	sub.f32 	%f651, %f636, %f650;
	add.f32 	%f652, %f644, %f651;
	add.f32 	%f653, %f649, %f652;
	add.f32 	%f654, %f650, %f653;
	sub.f32 	%f655, %f650, %f654;
	add.f32 	%f656, %f653, %f655;
	mov.f32 	%f657, 0f3F317200;
	mul.rn.f32 	%f658, %f630, %f657;
	mov.f32 	%f659, 0f35BFBE8E;
	mul.rn.f32 	%f660, %f630, %f659;
	add.f32 	%f661, %f658, %f654;
	sub.f32 	%f662, %f658, %f661;
	add.f32 	%f663, %f654, %f662;
	add.f32 	%f664, %f656, %f663;
	add.f32 	%f665, %f660, %f664;
	add.f32 	%f666, %f661, %f665;
	sub.f32 	%f667, %f661, %f666;
	add.f32 	%f668, %f665, %f667;
	mov.f32 	%f669, 0f3EE66666;
	mul.rn.f32 	%f670, %f669, %f666;
	neg.f32 	%f671, %f670;
	fma.rn.f32 	%f672, %f669, %f666, %f671;
	fma.rn.f32 	%f673, %f669, %f668, %f672;
	mov.f32 	%f674, 0f00000000;
	fma.rn.f32 	%f675, %f674, %f666, %f673;
	add.rn.f32 	%f676, %f670, %f675;
	neg.f32 	%f677, %f676;
	add.rn.f32 	%f678, %f670, %f677;
	add.rn.f32 	%f679, %f678, %f675;
	mov.b32 	%r230, %f676;
	setp.eq.s32 	%p67, %r230, 1118925336;
	add.s32 	%r231, %r230, -1;
	mov.b32 	%f680, %r231;
	add.f32 	%f681, %f679, 0f37000000;
	selp.f32 	%f173, %f681, %f679, %p67;
	selp.f32 	%f682, %f680, %f676, %p67;
	mov.f32 	%f683, 0f3FB8AA3B;
	mul.rn.f32 	%f684, %f682, %f683;
	cvt.rzi.f32.f32 	%f685, %f684;
	abs.f32 	%f686, %f685;
	setp.gt.f32 	%p68, %f686, 0f42FC0000;
	mov.b32 	%r232, %f685;
	and.b32  	%r233, %r232, -2147483648;
	or.b32  	%r234, %r233, 1123811328;
	mov.b32 	%f687, %r234;
	selp.f32 	%f688, %f687, %f685, %p68;
	mov.f32 	%f689, 0fBF317218;
	fma.rn.f32 	%f690, %f688, %f689, %f682;
	mov.f32 	%f691, 0f3102E308;
	fma.rn.f32 	%f692, %f688, %f691, %f690;
	mul.f32 	%f693, %f692, 0f3FB8AA3B;
	add.f32 	%f694, %f688, 0f4B40007F;
	mov.b32 	%r235, %f694;
	shl.b32 	%r236, %r235, 23;
	mov.b32 	%f695, %r236;
	ex2.approx.ftz.f32 	%f696, %f693;
	mul.f32 	%f174, %f696, %f695;
	setp.eq.f32 	%p69, %f174, 0f7F800000;
	mov.f32 	%f1245, 0f7F800000;
	@%p69 bra 	$L__BB0_59;

	fma.rn.f32 	%f1245, %f174, %f173, %f174;

$L__BB0_59:
	setp.lt.f32 	%p70, %f157, 0f00000000;
	and.pred  	%p2, %p70, %p56;
	setp.eq.f32 	%p72, %f157, 0f00000000;
	@%p72 bra 	$L__BB0_63;
	bra.uni 	$L__BB0_60;

$L__BB0_63:
	add.f32 	%f701, %f157, %f157;
	selp.f32 	%f1247, %f701, 0f00000000, %p56;
	bra.uni 	$L__BB0_64;

$L__BB0_60:
	mov.b32 	%r237, %f1245;
	xor.b32  	%r238, %r237, -2147483648;
	mov.b32 	%f697, %r238;
	selp.f32 	%f1247, %f697, %f1245, %p2;
	setp.geu.f32 	%p73, %f157, 0f00000000;
	@%p73 bra 	$L__BB0_64;

	mov.f32 	%f698, 0f3EE66666;
	cvt.rzi.f32.f32 	%f699, %f698;
	setp.eq.f32 	%p74, %f699, 0f3EE66666;
	@%p74 bra 	$L__BB0_64;

	mov.f32 	%f1247, 0f7FFFFFFF;

$L__BB0_64:
	add.f32 	%f702, %f172, 0f3EE66666;
	mov.b32 	%r239, %f702;
	setp.lt.s32 	%p76, %r239, 2139095040;
	@%p76 bra 	$L__BB0_69;

	setp.gtu.f32 	%p77, %f172, 0f7F800000;
	@%p77 bra 	$L__BB0_68;
	bra.uni 	$L__BB0_66;

$L__BB0_68:
	add.f32 	%f1247, %f157, 0f3EE66666;
	bra.uni 	$L__BB0_69;

$L__BB0_66:
	setp.neu.f32 	%p78, %f172, 0f7F800000;
	@%p78 bra 	$L__BB0_69;

	selp.f32 	%f1247, 0fFF800000, 0f7F800000, %p2;

$L__BB0_69:
	setp.eq.f32 	%p79, %f157, 0f3F800000;
	selp.f32 	%f183, 0f3F800000, %f1247, %p79;
	abs.f32 	%f184, %f158;
	setp.lt.f32 	%p80, %f184, 0f00800000;
	mul.f32 	%f704, %f184, 0f4B800000;
	selp.f32 	%f705, %f704, %f184, %p80;
	selp.f32 	%f706, 0fC3170000, 0fC2FE0000, %p80;
	mov.b32 	%r240, %f705;
	and.b32  	%r241, %r240, 8388607;
	or.b32  	%r242, %r241, 1065353216;
	mov.b32 	%f707, %r242;
	shr.u32 	%r243, %r240, 23;
	cvt.rn.f32.u32 	%f708, %r243;
	add.f32 	%f709, %f706, %f708;
	setp.gt.f32 	%p81, %f707, 0f3FB504F3;
	mul.f32 	%f710, %f707, 0f3F000000;
	add.f32 	%f711, %f709, 0f3F800000;
	selp.f32 	%f712, %f711, %f709, %p81;
	selp.f32 	%f713, %f710, %f707, %p81;
	add.f32 	%f714, %f713, 0fBF800000;
	add.f32 	%f715, %f713, 0f3F800000;
	rcp.approx.ftz.f32 	%f716, %f715;
	add.f32 	%f717, %f714, %f714;
	mul.f32 	%f718, %f717, %f716;
	mul.f32 	%f719, %f718, %f718;
	mov.f32 	%f720, 0f3C4CAF63;
	mov.f32 	%f721, 0f3B18F0FE;
	fma.rn.f32 	%f722, %f721, %f719, %f720;
	mov.f32 	%f723, 0f3DAAAABD;
	fma.rn.f32 	%f724, %f722, %f719, %f723;
	mul.rn.f32 	%f725, %f724, %f719;
	mul.rn.f32 	%f726, %f725, %f718;
	sub.f32 	%f727, %f714, %f718;
	add.f32 	%f728, %f727, %f727;
	neg.f32 	%f729, %f718;
	fma.rn.f32 	%f730, %f729, %f714, %f728;
	mul.rn.f32 	%f731, %f716, %f730;
	add.f32 	%f732, %f726, %f718;
	sub.f32 	%f733, %f718, %f732;
	add.f32 	%f734, %f726, %f733;
	add.f32 	%f735, %f731, %f734;
	add.f32 	%f736, %f732, %f735;
	sub.f32 	%f737, %f732, %f736;
	add.f32 	%f738, %f735, %f737;
	mov.f32 	%f739, 0f3F317200;
	mul.rn.f32 	%f740, %f712, %f739;
	mov.f32 	%f741, 0f35BFBE8E;
	mul.rn.f32 	%f742, %f712, %f741;
	add.f32 	%f743, %f740, %f736;
	sub.f32 	%f744, %f740, %f743;
	add.f32 	%f745, %f736, %f744;
	add.f32 	%f746, %f738, %f745;
	add.f32 	%f747, %f742, %f746;
	add.f32 	%f748, %f743, %f747;
	sub.f32 	%f749, %f743, %f748;
	add.f32 	%f750, %f747, %f749;
	mov.f32 	%f751, 0f3EE66666;
	mul.rn.f32 	%f752, %f751, %f748;
	neg.f32 	%f753, %f752;
	fma.rn.f32 	%f754, %f751, %f748, %f753;
	fma.rn.f32 	%f755, %f751, %f750, %f754;
	mov.f32 	%f756, 0f00000000;
	fma.rn.f32 	%f757, %f756, %f748, %f755;
	add.rn.f32 	%f758, %f752, %f757;
	neg.f32 	%f759, %f758;
	add.rn.f32 	%f760, %f752, %f759;
	add.rn.f32 	%f761, %f760, %f757;
	mov.b32 	%r244, %f758;
	setp.eq.s32 	%p82, %r244, 1118925336;
	add.s32 	%r245, %r244, -1;
	mov.b32 	%f762, %r245;
	add.f32 	%f763, %f761, 0f37000000;
	selp.f32 	%f185, %f763, %f761, %p82;
	selp.f32 	%f764, %f762, %f758, %p82;
	mov.f32 	%f765, 0f3FB8AA3B;
	mul.rn.f32 	%f766, %f764, %f765;
	cvt.rzi.f32.f32 	%f767, %f766;
	abs.f32 	%f768, %f767;
	setp.gt.f32 	%p83, %f768, 0f42FC0000;
	mov.b32 	%r246, %f767;
	and.b32  	%r247, %r246, -2147483648;
	or.b32  	%r248, %r247, 1123811328;
	mov.b32 	%f769, %r248;
	selp.f32 	%f770, %f769, %f767, %p83;
	mov.f32 	%f771, 0fBF317218;
	fma.rn.f32 	%f772, %f770, %f771, %f764;
	mov.f32 	%f773, 0f3102E308;
	fma.rn.f32 	%f774, %f770, %f773, %f772;
	mul.f32 	%f775, %f774, 0f3FB8AA3B;
	add.f32 	%f776, %f770, 0f4B40007F;
	mov.b32 	%r249, %f776;
	shl.b32 	%r250, %r249, 23;
	mov.b32 	%f777, %r250;
	ex2.approx.ftz.f32 	%f778, %f775;
	mul.f32 	%f186, %f778, %f777;
	setp.eq.f32 	%p84, %f186, 0f7F800000;
	mov.f32 	%f1248, 0f7F800000;
	@%p84 bra 	$L__BB0_71;

	fma.rn.f32 	%f1248, %f186, %f185, %f186;

$L__BB0_71:
	setp.lt.f32 	%p85, %f158, 0f00000000;
	and.pred  	%p3, %p85, %p56;
	setp.eq.f32 	%p87, %f158, 0f00000000;
	@%p87 bra 	$L__BB0_75;
	bra.uni 	$L__BB0_72;

$L__BB0_75:
	add.f32 	%f783, %f158, %f158;
	selp.f32 	%f1250, %f783, 0f00000000, %p56;
	bra.uni 	$L__BB0_76;

$L__BB0_72:
	mov.b32 	%r251, %f1248;
	xor.b32  	%r252, %r251, -2147483648;
	mov.b32 	%f779, %r252;
	selp.f32 	%f1250, %f779, %f1248, %p3;
	setp.geu.f32 	%p88, %f158, 0f00000000;
	@%p88 bra 	$L__BB0_76;

	mov.f32 	%f780, 0f3EE66666;
	cvt.rzi.f32.f32 	%f781, %f780;
	setp.eq.f32 	%p89, %f781, 0f3EE66666;
	@%p89 bra 	$L__BB0_76;

	mov.f32 	%f1250, 0f7FFFFFFF;

$L__BB0_76:
	add.f32 	%f784, %f184, 0f3EE66666;
	mov.b32 	%r253, %f784;
	setp.lt.s32 	%p91, %r253, 2139095040;
	@%p91 bra 	$L__BB0_81;

	setp.gtu.f32 	%p92, %f184, 0f7F800000;
	@%p92 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_78;

$L__BB0_80:
	add.f32 	%f1250, %f158, 0f3EE66666;
	bra.uni 	$L__BB0_81;

$L__BB0_78:
	setp.neu.f32 	%p93, %f184, 0f7F800000;
	@%p93 bra 	$L__BB0_81;

	selp.f32 	%f1250, 0fFF800000, 0f7F800000, %p3;

$L__BB0_81:
	setp.eq.f32 	%p94, %f158, 0f3F800000;
	mov.f32 	%f786, 0f3F800000;
	selp.f32 	%f787, 0f3F800000, %f1250, %p94;
	min.f32 	%f788, %f171, %f786;
	mov.f32 	%f789, 0f00000000;
	max.f32 	%f195, %f789, %f788;
	min.f32 	%f790, %f183, %f786;
	max.f32 	%f196, %f789, %f790;
	min.f32 	%f791, %f787, %f786;
	max.f32 	%f197, %f789, %f791;
	mov.f32 	%f795, 0f3ED55555;
	abs.f32 	%f199, %f195;
	setp.lt.f32 	%p95, %f199, 0f00800000;
	mul.f32 	%f797, %f199, 0f4B800000;
	selp.f32 	%f798, %f797, %f199, %p95;
	selp.f32 	%f799, 0fC3170000, 0fC2FE0000, %p95;
	mov.b32 	%r256, %f798;
	and.b32  	%r257, %r256, 8388607;
	or.b32  	%r258, %r257, 1065353216;
	mov.b32 	%f800, %r258;
	shr.u32 	%r259, %r256, 23;
	cvt.rn.f32.u32 	%f801, %r259;
	add.f32 	%f802, %f799, %f801;
	setp.gt.f32 	%p96, %f800, 0f3FB504F3;
	mul.f32 	%f803, %f800, 0f3F000000;
	add.f32 	%f804, %f802, 0f3F800000;
	selp.f32 	%f805, %f804, %f802, %p96;
	selp.f32 	%f806, %f803, %f800, %p96;
	add.f32 	%f807, %f806, 0fBF800000;
	add.f32 	%f808, %f806, 0f3F800000;
	rcp.approx.ftz.f32 	%f809, %f808;
	add.f32 	%f810, %f807, %f807;
	mul.f32 	%f811, %f810, %f809;
	mul.f32 	%f812, %f811, %f811;
	mov.f32 	%f813, 0f3C4CAF63;
	mov.f32 	%f814, 0f3B18F0FE;
	fma.rn.f32 	%f815, %f814, %f812, %f813;
	mov.f32 	%f816, 0f3DAAAABD;
	fma.rn.f32 	%f817, %f815, %f812, %f816;
	mul.rn.f32 	%f818, %f817, %f812;
	mul.rn.f32 	%f819, %f818, %f811;
	sub.f32 	%f820, %f807, %f811;
	add.f32 	%f821, %f820, %f820;
	neg.f32 	%f822, %f811;
	fma.rn.f32 	%f823, %f822, %f807, %f821;
	mul.rn.f32 	%f824, %f809, %f823;
	add.f32 	%f825, %f819, %f811;
	sub.f32 	%f826, %f811, %f825;
	add.f32 	%f827, %f819, %f826;
	add.f32 	%f828, %f824, %f827;
	add.f32 	%f829, %f825, %f828;
	sub.f32 	%f830, %f825, %f829;
	add.f32 	%f831, %f828, %f830;
	mov.f32 	%f832, 0f3F317200;
	mul.rn.f32 	%f833, %f805, %f832;
	mov.f32 	%f834, 0f35BFBE8E;
	mul.rn.f32 	%f835, %f805, %f834;
	add.f32 	%f836, %f833, %f829;
	sub.f32 	%f837, %f833, %f836;
	add.f32 	%f838, %f829, %f837;
	add.f32 	%f839, %f831, %f838;
	add.f32 	%f840, %f835, %f839;
	add.f32 	%f841, %f836, %f840;
	sub.f32 	%f842, %f836, %f841;
	add.f32 	%f843, %f840, %f842;
	mul.rn.f32 	%f844, %f795, %f841;
	neg.f32 	%f845, %f844;
	fma.rn.f32 	%f846, %f795, %f841, %f845;
	fma.rn.f32 	%f847, %f795, %f843, %f846;
	fma.rn.f32 	%f848, %f789, %f841, %f847;
	add.rn.f32 	%f849, %f844, %f848;
	neg.f32 	%f850, %f849;
	add.rn.f32 	%f851, %f844, %f850;
	add.rn.f32 	%f852, %f851, %f848;
	mov.b32 	%r260, %f849;
	setp.eq.s32 	%p97, %r260, 1118925336;
	add.s32 	%r261, %r260, -1;
	mov.b32 	%f853, %r261;
	add.f32 	%f854, %f852, 0f37000000;
	selp.f32 	%f200, %f854, %f852, %p97;
	selp.f32 	%f855, %f853, %f849, %p97;
	mov.f32 	%f856, 0f3FB8AA3B;
	mul.rn.f32 	%f857, %f855, %f856;
	cvt.rzi.f32.f32 	%f858, %f857;
	abs.f32 	%f859, %f858;
	setp.gt.f32 	%p98, %f859, 0f42FC0000;
	mov.b32 	%r262, %f858;
	and.b32  	%r263, %r262, -2147483648;
	or.b32  	%r264, %r263, 1123811328;
	mov.b32 	%f860, %r264;
	selp.f32 	%f861, %f860, %f858, %p98;
	mov.f32 	%f862, 0fBF317218;
	fma.rn.f32 	%f863, %f861, %f862, %f855;
	mov.f32 	%f864, 0f3102E308;
	fma.rn.f32 	%f865, %f861, %f864, %f863;
	mul.f32 	%f866, %f865, 0f3FB8AA3B;
	add.f32 	%f867, %f861, 0f4B40007F;
	mov.b32 	%r265, %f867;
	shl.b32 	%r266, %r265, 23;
	mov.b32 	%f868, %r266;
	ex2.approx.ftz.f32 	%f869, %f866;
	mul.f32 	%f201, %f869, %f868;
	setp.eq.f32 	%p99, %f201, 0f7F800000;
	mov.f32 	%f1251, 0f7F800000;
	@%p99 bra 	$L__BB0_83;

	fma.rn.f32 	%f1251, %f201, %f200, %f201;

$L__BB0_83:
	mov.f32 	%f1175, 0f3E555555;
	cvt.rzi.f32.f32 	%f1174, %f1175;
	add.f32 	%f1173, %f1174, %f1174;
	mov.f32 	%f1172, 0f3ED55555;
	sub.f32 	%f1171, %f1172, %f1173;
	abs.f32 	%f1170, %f1171;
	setp.lt.f32 	%p100, %f195, 0f00000000;
	setp.eq.f32 	%p101, %f1170, 0f3F800000;
	and.pred  	%p4, %p100, %p101;
	setp.eq.f32 	%p102, %f195, 0f00000000;
	@%p102 bra 	$L__BB0_87;
	bra.uni 	$L__BB0_84;

$L__BB0_87:
	add.f32 	%f874, %f195, %f195;
	selp.f32 	%f1253, %f874, 0f00000000, %p101;
	bra.uni 	$L__BB0_88;

$L__BB0_84:
	mov.b32 	%r267, %f1251;
	xor.b32  	%r268, %r267, -2147483648;
	mov.b32 	%f870, %r268;
	selp.f32 	%f1253, %f870, %f1251, %p4;
	setp.geu.f32 	%p103, %f195, 0f00000000;
	@%p103 bra 	$L__BB0_88;

	mov.f32 	%f871, 0f3ED55555;
	cvt.rzi.f32.f32 	%f872, %f871;
	setp.eq.f32 	%p104, %f872, 0f3ED55555;
	@%p104 bra 	$L__BB0_88;

	mov.f32 	%f1253, 0f7FFFFFFF;

$L__BB0_88:
	add.f32 	%f875, %f199, 0f3ED55555;
	mov.b32 	%r269, %f875;
	setp.lt.s32 	%p106, %r269, 2139095040;
	@%p106 bra 	$L__BB0_93;

	setp.gtu.f32 	%p107, %f199, 0f7F800000;
	@%p107 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_90;

$L__BB0_92:
	add.f32 	%f1253, %f195, 0f3ED55555;
	bra.uni 	$L__BB0_93;

$L__BB0_90:
	setp.neu.f32 	%p108, %f199, 0f7F800000;
	@%p108 bra 	$L__BB0_93;

	selp.f32 	%f1253, 0fFF800000, 0f7F800000, %p4;

$L__BB0_93:
	abs.f32 	%f210, %f196;
	setp.lt.f32 	%p109, %f210, 0f00800000;
	mul.f32 	%f877, %f210, 0f4B800000;
	selp.f32 	%f878, %f877, %f210, %p109;
	selp.f32 	%f879, 0fC3170000, 0fC2FE0000, %p109;
	mov.b32 	%r270, %f878;
	and.b32  	%r271, %r270, 8388607;
	or.b32  	%r272, %r271, 1065353216;
	mov.b32 	%f880, %r272;
	shr.u32 	%r273, %r270, 23;
	cvt.rn.f32.u32 	%f881, %r273;
	add.f32 	%f882, %f879, %f881;
	setp.gt.f32 	%p110, %f880, 0f3FB504F3;
	mul.f32 	%f883, %f880, 0f3F000000;
	add.f32 	%f884, %f882, 0f3F800000;
	selp.f32 	%f885, %f884, %f882, %p110;
	selp.f32 	%f886, %f883, %f880, %p110;
	add.f32 	%f887, %f886, 0fBF800000;
	add.f32 	%f888, %f886, 0f3F800000;
	rcp.approx.ftz.f32 	%f889, %f888;
	add.f32 	%f890, %f887, %f887;
	mul.f32 	%f891, %f890, %f889;
	mul.f32 	%f892, %f891, %f891;
	mov.f32 	%f893, 0f3C4CAF63;
	mov.f32 	%f894, 0f3B18F0FE;
	fma.rn.f32 	%f895, %f894, %f892, %f893;
	mov.f32 	%f896, 0f3DAAAABD;
	fma.rn.f32 	%f897, %f895, %f892, %f896;
	mul.rn.f32 	%f898, %f897, %f892;
	mul.rn.f32 	%f899, %f898, %f891;
	sub.f32 	%f900, %f887, %f891;
	add.f32 	%f901, %f900, %f900;
	neg.f32 	%f902, %f891;
	fma.rn.f32 	%f903, %f902, %f887, %f901;
	mul.rn.f32 	%f904, %f889, %f903;
	add.f32 	%f905, %f899, %f891;
	sub.f32 	%f906, %f891, %f905;
	add.f32 	%f907, %f899, %f906;
	add.f32 	%f908, %f904, %f907;
	add.f32 	%f909, %f905, %f908;
	sub.f32 	%f910, %f905, %f909;
	add.f32 	%f911, %f908, %f910;
	mov.f32 	%f912, 0f3F317200;
	mul.rn.f32 	%f913, %f885, %f912;
	mov.f32 	%f914, 0f35BFBE8E;
	mul.rn.f32 	%f915, %f885, %f914;
	add.f32 	%f916, %f913, %f909;
	sub.f32 	%f917, %f913, %f916;
	add.f32 	%f918, %f909, %f917;
	add.f32 	%f919, %f911, %f918;
	add.f32 	%f920, %f915, %f919;
	add.f32 	%f921, %f916, %f920;
	sub.f32 	%f922, %f916, %f921;
	add.f32 	%f923, %f920, %f922;
	mov.f32 	%f924, 0f3ED55555;
	mul.rn.f32 	%f925, %f924, %f921;
	neg.f32 	%f926, %f925;
	fma.rn.f32 	%f927, %f924, %f921, %f926;
	fma.rn.f32 	%f928, %f924, %f923, %f927;
	mov.f32 	%f929, 0f00000000;
	fma.rn.f32 	%f930, %f929, %f921, %f928;
	add.rn.f32 	%f931, %f925, %f930;
	neg.f32 	%f932, %f931;
	add.rn.f32 	%f933, %f925, %f932;
	add.rn.f32 	%f934, %f933, %f930;
	mov.b32 	%r274, %f931;
	setp.eq.s32 	%p111, %r274, 1118925336;
	add.s32 	%r275, %r274, -1;
	mov.b32 	%f935, %r275;
	add.f32 	%f936, %f934, 0f37000000;
	selp.f32 	%f211, %f936, %f934, %p111;
	selp.f32 	%f937, %f935, %f931, %p111;
	mov.f32 	%f938, 0f3FB8AA3B;
	mul.rn.f32 	%f939, %f937, %f938;
	cvt.rzi.f32.f32 	%f940, %f939;
	abs.f32 	%f941, %f940;
	setp.gt.f32 	%p112, %f941, 0f42FC0000;
	mov.b32 	%r276, %f940;
	and.b32  	%r277, %r276, -2147483648;
	or.b32  	%r278, %r277, 1123811328;
	mov.b32 	%f942, %r278;
	selp.f32 	%f943, %f942, %f940, %p112;
	mov.f32 	%f944, 0fBF317218;
	fma.rn.f32 	%f945, %f943, %f944, %f937;
	mov.f32 	%f946, 0f3102E308;
	fma.rn.f32 	%f947, %f943, %f946, %f945;
	mul.f32 	%f948, %f947, 0f3FB8AA3B;
	add.f32 	%f949, %f943, 0f4B40007F;
	mov.b32 	%r279, %f949;
	shl.b32 	%r280, %r279, 23;
	mov.b32 	%f950, %r280;
	ex2.approx.ftz.f32 	%f951, %f948;
	mul.f32 	%f212, %f951, %f950;
	setp.eq.f32 	%p113, %f212, 0f7F800000;
	mov.f32 	%f1254, 0f7F800000;
	@%p113 bra 	$L__BB0_95;

	fma.rn.f32 	%f1254, %f212, %f211, %f212;

$L__BB0_95:
	setp.lt.f32 	%p114, %f196, 0f00000000;
	and.pred  	%p5, %p114, %p101;
	setp.eq.f32 	%p116, %f196, 0f00000000;
	@%p116 bra 	$L__BB0_99;
	bra.uni 	$L__BB0_96;

$L__BB0_99:
	add.f32 	%f956, %f196, %f196;
	selp.f32 	%f1256, %f956, 0f00000000, %p101;
	bra.uni 	$L__BB0_100;

$L__BB0_96:
	mov.b32 	%r281, %f1254;
	xor.b32  	%r282, %r281, -2147483648;
	mov.b32 	%f952, %r282;
	selp.f32 	%f1256, %f952, %f1254, %p5;
	setp.geu.f32 	%p117, %f196, 0f00000000;
	@%p117 bra 	$L__BB0_100;

	mov.f32 	%f953, 0f3ED55555;
	cvt.rzi.f32.f32 	%f954, %f953;
	setp.eq.f32 	%p118, %f954, 0f3ED55555;
	@%p118 bra 	$L__BB0_100;

	mov.f32 	%f1256, 0f7FFFFFFF;

$L__BB0_100:
	add.f32 	%f957, %f210, 0f3ED55555;
	mov.b32 	%r283, %f957;
	setp.lt.s32 	%p120, %r283, 2139095040;
	@%p120 bra 	$L__BB0_105;

	setp.gtu.f32 	%p121, %f210, 0f7F800000;
	@%p121 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_102;

$L__BB0_104:
	add.f32 	%f1256, %f196, 0f3ED55555;
	bra.uni 	$L__BB0_105;

$L__BB0_102:
	setp.neu.f32 	%p122, %f210, 0f7F800000;
	@%p122 bra 	$L__BB0_105;

	selp.f32 	%f1256, 0fFF800000, 0f7F800000, %p5;

$L__BB0_105:
	abs.f32 	%f221, %f197;
	setp.lt.f32 	%p123, %f221, 0f00800000;
	mul.f32 	%f959, %f221, 0f4B800000;
	selp.f32 	%f960, %f959, %f221, %p123;
	selp.f32 	%f961, 0fC3170000, 0fC2FE0000, %p123;
	mov.b32 	%r284, %f960;
	and.b32  	%r285, %r284, 8388607;
	or.b32  	%r286, %r285, 1065353216;
	mov.b32 	%f962, %r286;
	shr.u32 	%r287, %r284, 23;
	cvt.rn.f32.u32 	%f963, %r287;
	add.f32 	%f964, %f961, %f963;
	setp.gt.f32 	%p124, %f962, 0f3FB504F3;
	mul.f32 	%f965, %f962, 0f3F000000;
	add.f32 	%f966, %f964, 0f3F800000;
	selp.f32 	%f967, %f966, %f964, %p124;
	selp.f32 	%f968, %f965, %f962, %p124;
	add.f32 	%f969, %f968, 0fBF800000;
	add.f32 	%f970, %f968, 0f3F800000;
	rcp.approx.ftz.f32 	%f971, %f970;
	add.f32 	%f972, %f969, %f969;
	mul.f32 	%f973, %f972, %f971;
	mul.f32 	%f974, %f973, %f973;
	mov.f32 	%f975, 0f3C4CAF63;
	mov.f32 	%f976, 0f3B18F0FE;
	fma.rn.f32 	%f977, %f976, %f974, %f975;
	mov.f32 	%f978, 0f3DAAAABD;
	fma.rn.f32 	%f979, %f977, %f974, %f978;
	mul.rn.f32 	%f980, %f979, %f974;
	mul.rn.f32 	%f981, %f980, %f973;
	sub.f32 	%f982, %f969, %f973;
	add.f32 	%f983, %f982, %f982;
	neg.f32 	%f984, %f973;
	fma.rn.f32 	%f985, %f984, %f969, %f983;
	mul.rn.f32 	%f986, %f971, %f985;
	add.f32 	%f987, %f981, %f973;
	sub.f32 	%f988, %f973, %f987;
	add.f32 	%f989, %f981, %f988;
	add.f32 	%f990, %f986, %f989;
	add.f32 	%f991, %f987, %f990;
	sub.f32 	%f992, %f987, %f991;
	add.f32 	%f993, %f990, %f992;
	mov.f32 	%f994, 0f3F317200;
	mul.rn.f32 	%f995, %f967, %f994;
	mov.f32 	%f996, 0f35BFBE8E;
	mul.rn.f32 	%f997, %f967, %f996;
	add.f32 	%f998, %f995, %f991;
	sub.f32 	%f999, %f995, %f998;
	add.f32 	%f1000, %f991, %f999;
	add.f32 	%f1001, %f993, %f1000;
	add.f32 	%f1002, %f997, %f1001;
	add.f32 	%f1003, %f998, %f1002;
	sub.f32 	%f1004, %f998, %f1003;
	add.f32 	%f1005, %f1002, %f1004;
	mov.f32 	%f1006, 0f3ED55555;
	mul.rn.f32 	%f1007, %f1006, %f1003;
	neg.f32 	%f1008, %f1007;
	fma.rn.f32 	%f1009, %f1006, %f1003, %f1008;
	fma.rn.f32 	%f1010, %f1006, %f1005, %f1009;
	mov.f32 	%f1011, 0f00000000;
	fma.rn.f32 	%f1012, %f1011, %f1003, %f1010;
	add.rn.f32 	%f1013, %f1007, %f1012;
	neg.f32 	%f1014, %f1013;
	add.rn.f32 	%f1015, %f1007, %f1014;
	add.rn.f32 	%f1016, %f1015, %f1012;
	mov.b32 	%r288, %f1013;
	setp.eq.s32 	%p125, %r288, 1118925336;
	add.s32 	%r289, %r288, -1;
	mov.b32 	%f1017, %r289;
	add.f32 	%f1018, %f1016, 0f37000000;
	selp.f32 	%f222, %f1018, %f1016, %p125;
	selp.f32 	%f1019, %f1017, %f1013, %p125;
	mov.f32 	%f1020, 0f3FB8AA3B;
	mul.rn.f32 	%f1021, %f1019, %f1020;
	cvt.rzi.f32.f32 	%f1022, %f1021;
	abs.f32 	%f1023, %f1022;
	setp.gt.f32 	%p126, %f1023, 0f42FC0000;
	mov.b32 	%r290, %f1022;
	and.b32  	%r291, %r290, -2147483648;
	or.b32  	%r292, %r291, 1123811328;
	mov.b32 	%f1024, %r292;
	selp.f32 	%f1025, %f1024, %f1022, %p126;
	mov.f32 	%f1026, 0fBF317218;
	fma.rn.f32 	%f1027, %f1025, %f1026, %f1019;
	mov.f32 	%f1028, 0f3102E308;
	fma.rn.f32 	%f1029, %f1025, %f1028, %f1027;
	mul.f32 	%f1030, %f1029, 0f3FB8AA3B;
	add.f32 	%f1031, %f1025, 0f4B40007F;
	mov.b32 	%r293, %f1031;
	shl.b32 	%r294, %r293, 23;
	mov.b32 	%f1032, %r294;
	ex2.approx.ftz.f32 	%f1033, %f1030;
	mul.f32 	%f223, %f1033, %f1032;
	setp.eq.f32 	%p127, %f223, 0f7F800000;
	mov.f32 	%f1257, 0f7F800000;
	@%p127 bra 	$L__BB0_107;

	fma.rn.f32 	%f1257, %f223, %f222, %f223;

$L__BB0_107:
	setp.lt.f32 	%p128, %f197, 0f00000000;
	and.pred  	%p6, %p128, %p101;
	setp.eq.f32 	%p130, %f197, 0f00000000;
	@%p130 bra 	$L__BB0_111;
	bra.uni 	$L__BB0_108;

$L__BB0_111:
	add.f32 	%f1038, %f197, %f197;
	selp.f32 	%f1259, %f1038, 0f00000000, %p101;
	bra.uni 	$L__BB0_112;

$L__BB0_108:
	mov.b32 	%r295, %f1257;
	xor.b32  	%r296, %r295, -2147483648;
	mov.b32 	%f1034, %r296;
	selp.f32 	%f1259, %f1034, %f1257, %p6;
	setp.geu.f32 	%p131, %f197, 0f00000000;
	@%p131 bra 	$L__BB0_112;

	mov.f32 	%f1035, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1036, %f1035;
	setp.eq.f32 	%p132, %f1036, 0f3ED55555;
	@%p132 bra 	$L__BB0_112;

	mov.f32 	%f1259, 0f7FFFFFFF;

$L__BB0_112:
	add.f32 	%f1039, %f221, 0f3ED55555;
	mov.b32 	%r297, %f1039;
	setp.lt.s32 	%p134, %r297, 2139095040;
	@%p134 bra 	$L__BB0_117;

	setp.gtu.f32 	%p135, %f221, 0f7F800000;
	@%p135 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_114;

$L__BB0_116:
	add.f32 	%f1259, %f197, 0f3ED55555;
	bra.uni 	$L__BB0_117;

$L__BB0_114:
	setp.neu.f32 	%p136, %f221, 0f7F800000;
	@%p136 bra 	$L__BB0_117;

	selp.f32 	%f1259, 0fFF800000, 0f7F800000, %p6;

$L__BB0_117:
	ld.const.u64 	%rd100, [params+144];
	cvta.to.global.u64 	%rd99, %rd100;
	ld.const.u32 	%r344, [params+136];
	mad.lo.s32 	%r343, %r344, %r5, %r4;
	cvt.u64.u32 	%rd98, %r343;
	fma.rn.f32 	%f1040, %f1253, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p137, %f195, 0f3F800000;
	mov.f32 	%f1041, 0f3F800000;
	selp.f32 	%f1042, 0f3F7FFFFF, %f1040, %p137;
	mul.f32 	%f1043, %f195, 0f414EB852;
	setp.lt.f32 	%p138, %f195, 0f3B4D2E1C;
	selp.f32 	%f1044, %f1043, %f1042, %p138;
	fma.rn.f32 	%f1045, %f1256, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p139, %f196, 0f3F800000;
	selp.f32 	%f1046, 0f3F7FFFFF, %f1045, %p139;
	mul.f32 	%f1047, %f196, 0f414EB852;
	setp.lt.f32 	%p140, %f196, 0f3B4D2E1C;
	selp.f32 	%f1048, %f1047, %f1046, %p140;
	fma.rn.f32 	%f1049, %f1259, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p141, %f197, 0f3F800000;
	selp.f32 	%f1050, 0f3F7FFFFF, %f1049, %p141;
	mul.f32 	%f1051, %f197, 0f414EB852;
	setp.lt.f32 	%p142, %f197, 0f3B4D2E1C;
	selp.f32 	%f1052, %f1051, %f1050, %p142;
	min.f32 	%f1053, %f1044, %f1041;
	mov.f32 	%f1054, 0f00000000;
	max.f32 	%f1055, %f1054, %f1053;
	mul.f32 	%f1056, %f1055, 0f43800000;
	cvt.rzi.u32.f32 	%r298, %f1056;
	min.u32 	%r299, %r298, 255;
	min.f32 	%f1057, %f1048, %f1041;
	max.f32 	%f1058, %f1054, %f1057;
	mul.f32 	%f1059, %f1058, 0f43800000;
	cvt.rzi.u32.f32 	%r300, %f1059;
	min.u32 	%r301, %r300, 255;
	min.f32 	%f1060, %f1052, %f1041;
	max.f32 	%f1061, %f1054, %f1060;
	mul.f32 	%f1062, %f1061, 0f43800000;
	cvt.rzi.u32.f32 	%r302, %f1062;
	min.u32 	%r303, %r302, 255;
	shl.b64 	%rd68, %rd98, 2;
	add.s64 	%rd69, %rd99, %rd68;
	cvt.u16.u32 	%rs44, %r303;
	cvt.u16.u32 	%rs45, %r301;
	cvt.u16.u32 	%rs46, %r299;
	mov.u16 	%rs47, 255;
	st.global.v4.u8 	[%rd69], {%rs46, %rs45, %rs44, %rs47};

$L__BB0_118:
	ld.const.u32 	%r345, [params+104];
	and.b32  	%r304, %r345, 4;
	setp.eq.s32 	%p143, %r304, 0;
	ld.const.u32 	%r357, [params+108];
	@%p143 bra 	$L__BB0_122;

	setp.eq.s32 	%p144, %r357, 0;
	ld.const.u64 	%rd70, [params+224];
	cvta.to.global.u64 	%rd71, %rd70;
	ld.const.u32 	%r305, [params+216];
	mad.lo.s32 	%r306, %r305, %r5, %r4;
	mul.wide.u32 	%rd72, %r306, 8;
	add.s64 	%rd19, %rd71, %rd72;
	@%p144 bra 	$L__BB0_121;

	ld.global.v4.u16 	{%rs55, %rs56, %rs57, %rs58}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1063, %rs55;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1064, %rs56;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1065, %rs57;}

	// end inline asm
	add.f32 	%f1066, %f156, %f1063;
	add.f32 	%f1067, %f157, %f1064;
	add.f32 	%f1068, %f158, %f1065;
	mov.f32 	%f1069, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1068;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f1067;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1066;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f1069;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs51, %rs52, %rs53, %rs54};
	bra.uni 	$L__BB0_122;

$L__BB0_121:
	mov.f32 	%f1073, 0f3F800000;
	mov.u32 	%r357, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f1073;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f158;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f157;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f156;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs59, %rs60, %rs61, %rs62};

$L__BB0_122:
	mul.f32 	%f1074, %f147, %f531;
	mul.f32 	%f1075, %f144, %f531;
	add.f32 	%f1076, %f1075, %f1074;
	mul.f32 	%f1077, %f148, %f532;
	mul.f32 	%f1078, %f145, %f532;
	add.f32 	%f1079, %f1078, %f1077;
	mul.f32 	%f1080, %f149, %f533;
	mul.f32 	%f1081, %f146, %f533;
	add.f32 	%f1082, %f1081, %f1080;
	mul.f32 	%f1083, %f150, %f531;
	add.f32 	%f1084, %f1076, %f1083;
	mul.f32 	%f1085, %f151, %f532;
	add.f32 	%f1086, %f1079, %f1085;
	mul.f32 	%f1087, %f152, %f533;
	add.f32 	%f1088, %f1082, %f1087;
	mul.f32 	%f1089, %f1084, 0f3F13CD3A;
	mul.f32 	%f1090, %f1086, 0f3F13CD3A;
	mul.f32 	%f1091, %f1088, 0f3F13CD3A;
	div.rn.f32 	%f1092, %f156, %f1089;
	div.rn.f32 	%f1093, %f157, %f1090;
	div.rn.f32 	%f1094, %f158, %f1091;
	setp.eq.f32 	%p145, %f156, 0f00000000;
	selp.f32 	%f1095, 0f00000000, %f1092, %p145;
	setp.eq.f32 	%p146, %f157, 0f00000000;
	selp.f32 	%f1096, 0f00000000, %f1093, %p146;
	setp.eq.f32 	%p147, %f158, 0f00000000;
	selp.f32 	%f1097, 0f00000000, %f1094, %p147;
	mul.f32 	%f232, %f1075, %f1095;
	mul.f32 	%f233, %f1078, %f1096;
	mul.f32 	%f234, %f1081, %f1097;
	mul.f32 	%f235, %f1074, %f1095;
	mul.f32 	%f236, %f1077, %f1096;
	mul.f32 	%f237, %f1080, %f1097;
	mul.f32 	%f238, %f1083, %f1095;
	mul.f32 	%f239, %f1085, %f1096;
	mul.f32 	%f240, %f1087, %f1097;
	ld.const.u64 	%rd73, [params+256];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r308, [params+248];
	mad.lo.s32 	%r309, %r308, %r5, %r4;
	mul.wide.u32 	%rd75, %r309, 8;
	add.s64 	%rd20, %rd74, %rd75;
	setp.eq.s32 	%p148, %r357, 0;
	@%p148 bra 	$L__BB0_124;

	ld.global.v4.u16 	{%rs70, %rs71, %rs72, %rs73}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1098, %rs70;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1099, %rs71;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1100, %rs72;}

	// end inline asm
	add.f32 	%f1101, %f232, %f1098;
	add.f32 	%f1102, %f233, %f1099;
	add.f32 	%f1103, %f234, %f1100;
	mov.f32 	%f1104, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1103;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f1102;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f1101;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1104;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs66, %rs67, %rs68, %rs69};
	bra.uni 	$L__BB0_125;

$L__BB0_124:
	mov.f32 	%f1108, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f1108;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f234;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f232;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs74, %rs75, %rs76, %rs77};

$L__BB0_125:
	ld.const.u64 	%rd76, [params+272];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r310, [params+264];
	mad.lo.s32 	%r311, %r310, %r5, %r4;
	mul.wide.u32 	%rd78, %r311, 8;
	add.s64 	%rd21, %rd77, %rd78;
	@%p148 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs85, %rs86, %rs87, %rs88}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1109, %rs85;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1110, %rs86;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1111, %rs87;}

	// end inline asm
	add.f32 	%f1112, %f235, %f1109;
	add.f32 	%f1113, %f236, %f1110;
	add.f32 	%f1114, %f237, %f1111;
	mov.f32 	%f1115, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1114;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1113;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f1112;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1115;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs81, %rs82, %rs83, %rs84};
	bra.uni 	$L__BB0_128;

$L__BB0_127:
	mov.f32 	%f1119, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f1119;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f237;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f236;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f235;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs89, %rs90, %rs91, %rs92};

$L__BB0_128:
	ld.const.u64 	%rd79, [params+288];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r312, [params+280];
	mad.lo.s32 	%r313, %r312, %r5, %r4;
	mul.wide.u32 	%rd81, %r313, 8;
	add.s64 	%rd22, %rd80, %rd81;
	@%p148 bra 	$L__BB0_130;

	ld.global.v4.u16 	{%rs100, %rs101, %rs102, %rs103}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1120, %rs100;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1121, %rs101;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1122, %rs102;}

	// end inline asm
	add.f32 	%f1123, %f238, %f1120;
	add.f32 	%f1124, %f239, %f1121;
	add.f32 	%f1125, %f240, %f1122;
	mov.f32 	%f1126, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1125;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1124;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1123;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1126;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs96, %rs97, %rs98, %rs99};
	bra.uni 	$L__BB0_146;

$L__BB0_130:
	mov.f32 	%f1130, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1130;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f240;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f239;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f238;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs104, %rs105, %rs106, %rs107};

$L__BB0_146:
	ret;

}