//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<117>;
	.reg .b16 	%rs<171>;
	.reg .f32 	%f<697>;
	.reg .b32 	%r<311>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<106>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r52), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r53), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.f32 	%f1, [params+700];
	ld.const.u64 	%rd29, [params+400];
	cvta.to.global.u64 	%rd30, %rd29;
	ld.const.u32 	%r58, [params+392];
	mad.lo.s32 	%r59, %r58, %r53, %r52;
	mul.wide.u32 	%rd31, %r59, 4;
	add.s64 	%rd2, %rd30, %rd31;
	ld.global.v2.u8 	{%rs7, %rs170}, [%rd2];
	or.b16  	%rs9, %rs7, %rs170;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p4, %rs10, 0;
	@%p4 bra 	$L__BB0_2;

	ld.global.u8 	%rs169, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs169, [%rd2+2];
	setp.eq.s16 	%p5, %rs169, 0;
	mov.f32 	%f662, 0f00000000;
	mov.u16 	%rs170, 0;
	mov.f32 	%f663, %f662;
	mov.f32 	%f664, %f662;
	@%p5 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f132, %rs7;
	div.rn.f32 	%f133, %f132, 0f437F0000;
	fma.rn.f32 	%f134, %f133, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs170, 255;
	cvt.rn.f32.u16 	%f135, %rs13;
	div.rn.f32 	%f136, %f135, 0f437F0000;
	fma.rn.f32 	%f137, %f136, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f138, %rs169;
	div.rn.f32 	%f139, %f138, 0f437F0000;
	fma.rn.f32 	%f140, %f139, 0f40000000, 0fBF800000;
	mul.f32 	%f141, %f137, %f137;
	fma.rn.f32 	%f142, %f134, %f134, %f141;
	fma.rn.f32 	%f143, %f140, %f140, %f142;
	sqrt.rn.f32 	%f144, %f143;
	rcp.rn.f32 	%f145, %f144;
	mul.f32 	%f664, %f145, %f140;
	mul.f32 	%f663, %f145, %f137;
	mul.f32 	%f662, %f134, %f145;

$L__BB0_4:
	ld.const.v2.u32 	{%r60, %r61}, [params];
	add.s32 	%r3, %r60, %r52;
	add.s32 	%r4, %r61, %r53;
	setp.eq.f32 	%p6, %f662, 0f00000000;
	setp.eq.f32 	%p7, %f663, 0f00000000;
	and.pred  	%p8, %p6, %p7;
	setp.eq.f32 	%p9, %f664, 0f00000000;
	and.pred  	%p10, %p9, %p8;
	@%p10 bra 	$L__BB0_97;
	bra.uni 	$L__BB0_5;

$L__BB0_97:
	ld.const.u32 	%r50, [params+104];
	and.b32  	%r284, %r50, 4;
	setp.eq.s32 	%p110, %r284, 0;
	@%p110 bra 	$L__BB0_101;

	ld.const.u32 	%r285, [params+108];
	setp.eq.s32 	%p111, %r285, 0;
	ld.const.u64 	%rd82, [params+224];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r286, [params+216];
	mad.lo.s32 	%r287, %r286, %r4, %r3;
	mul.wide.u32 	%rd84, %r287, 8;
	add.s64 	%rd23, %rd83, %rd84;
	@%p111 bra 	$L__BB0_100;

	ld.global.v4.u16 	{%rs98, %rs99, %rs100, %rs101}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f596, %rs98;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f597, %rs99;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f598, %rs100;}

	// end inline asm
	add.f32 	%f599, %f596, 0f00000000;
	add.f32 	%f600, %f597, 0f00000000;
	add.f32 	%f601, %f598, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f601;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f600;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f599;}

	// end inline asm
	mov.u16 	%rs102, 0;
	st.global.v4.u16 	[%rd23], {%rs95, %rs96, %rs97, %rs102};
	bra.uni 	$L__BB0_101;

$L__BB0_5:
	ld.const.u64 	%rd32, [params+432];
	cvta.to.global.u64 	%rd33, %rd32;
	ld.const.u32 	%r64, [params+424];
	mad.lo.s32 	%r65, %r64, %r53, %r52;
	mul.wide.u32 	%rd34, %r65, 12;
	add.s64 	%rd35, %rd33, %rd34;
	ld.global.f32 	%f151, [%rd35];
	mul.f32 	%f152, %f151, 0f3456BF95;
	ld.global.f32 	%f153, [%rd35+4];
	mul.f32 	%f154, %f153, 0f3456BF95;
	ld.global.f32 	%f155, [%rd35+8];
	mul.f32 	%f156, %f155, 0f3456BF95;
	abs.f32 	%f157, %f662;
	div.rn.f32 	%f158, %f152, %f157;
	abs.f32 	%f159, %f663;
	div.rn.f32 	%f160, %f154, %f159;
	abs.f32 	%f161, %f664;
	div.rn.f32 	%f162, %f156, %f161;
	abs.f32 	%f163, %f158;
	abs.f32 	%f164, %f160;
	abs.f32 	%f165, %f162;
	mov.f32 	%f166, 0f38D1B717;
	max.f32 	%f167, %f163, %f166;
	max.f32 	%f168, %f164, %f166;
	max.f32 	%f169, %f165, %f166;
	fma.rn.f32 	%f11, %f662, %f167, %f151;
	fma.rn.f32 	%f12, %f663, %f168, %f153;
	fma.rn.f32 	%f13, %f664, %f169, %f155;
	setp.gt.f32 	%p11, %f157, %f161;
	neg.f32 	%f170, %f663;
	selp.f32 	%f171, %f170, 0f00000000, %p11;
	mov.f32 	%f674, 0f00000000;
	neg.f32 	%f172, %f664;
	selp.f32 	%f173, %f662, %f172, %p11;
	selp.f32 	%f174, 0f00000000, %f663, %p11;
	mul.f32 	%f175, %f173, %f173;
	fma.rn.f32 	%f176, %f171, %f171, %f175;
	fma.rn.f32 	%f177, %f174, %f174, %f176;
	sqrt.rn.f32 	%f178, %f177;
	rcp.rn.f32 	%f179, %f178;
	mul.f32 	%f14, %f171, %f179;
	mul.f32 	%f15, %f173, %f179;
	mul.f32 	%f16, %f174, %f179;
	ld.const.u64 	%rd36, [params+128];
	cvta.to.global.u64 	%rd37, %rd36;
	ld.const.u32 	%r66, [params+120];
	mad.lo.s32 	%r67, %r66, %r53, %r52;
	mul.wide.u32 	%rd38, %r67, 4;
	add.s64 	%rd3, %rd37, %rd38;
	ld.const.u32 	%r5, [params+540];
	setp.lt.s32 	%p12, %r5, 1;
	mov.f32 	%f673, %f674;
	mov.f32 	%f672, %f674;
	mov.f32 	%f671, %f674;
	mov.f32 	%f670, %f674;
	@%p12 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f185, %r5;
	rcp.rn.f32 	%f17, %f185;
	ld.global.u32 	%r303, [%rd3];
	mul.f32 	%f18, %f11, 0f3456BF95;
	mul.f32 	%f19, %f12, 0f3456BF95;
	mul.f32 	%f20, %f13, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f186, %f662, %f15;
	mul.f32 	%f187, %f663, %f14;
	sub.f32 	%f21, %f187, %f186;
	mul.f32 	%f188, %f664, %f14;
	mul.f32 	%f189, %f662, %f16;
	sub.f32 	%f22, %f189, %f188;
	mul.f32 	%f190, %f663, %f16;
	mul.f32 	%f191, %f664, %f15;
	sub.f32 	%f23, %f191, %f190;
	mov.u32 	%r68, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd39, __cudart_i2opi_f;
	abs.f32 	%f254, %f19;
	abs.f32 	%f255, %f18;
	max.f32 	%f256, %f255, %f254;
	abs.f32 	%f257, %f20;
	max.f32 	%f258, %f256, %f257;
	mov.u32 	%r300, %r68;

$L__BB0_7:
	cvt.rn.f32.s32 	%f29, %r300;
	mov.u32 	%r302, %r68;

$L__BB0_8:
	mad.lo.s32 	%r70, %r303, 1664525, 1013904223;
	and.b32  	%r71, %r70, 16777215;
	cvt.rn.f32.u32 	%f192, %r71;
	fma.rn.f32 	%f193, %f192, 0f33800000, %f29;
	mul.f32 	%f35, %f17, %f193;
	mad.lo.s32 	%r303, %r70, 1664525, 1013904223;
	and.b32  	%r72, %r303, 16777215;
	cvt.rn.f32.u32 	%f194, %r72;
	cvt.rn.f32.s32 	%f195, %r302;
	fma.rn.f32 	%f196, %f194, 0f33800000, %f195;
	mul.f32 	%f197, %f17, %f196;
	mul.f32 	%f198, %f35, %f35;
	mov.f32 	%f199, 0f3F800000;
	sub.f32 	%f200, %f199, %f198;
	mov.f32 	%f201, 0f00000000;
	max.f32 	%f202, %f201, %f200;
	sqrt.rn.f32 	%f36, %f202;
	mul.f32 	%f37, %f197, 0f40C90FDB;
	mul.f32 	%f203, %f37, 0f3F22F983;
	cvt.rni.s32.f32 	%r310, %f203;
	cvt.rn.f32.s32 	%f204, %r310;
	mov.f32 	%f205, 0fBFC90FDA;
	fma.rn.f32 	%f206, %f204, %f205, %f37;
	mov.f32 	%f207, 0fB3A22168;
	fma.rn.f32 	%f208, %f204, %f207, %f206;
	mov.f32 	%f209, 0fA7C234C5;
	fma.rn.f32 	%f678, %f204, %f209, %f208;
	abs.f32 	%f39, %f37;
	setp.ltu.f32 	%p13, %f39, 0f47CE4780;
	mov.u32 	%r307, %r310;
	mov.f32 	%f675, %f678;
	@%p13 bra 	$L__BB0_16;

	setp.eq.f32 	%p14, %f39, 0f7F800000;
	@%p14 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f212, 0f00000000;
	mul.rn.f32 	%f675, %f37, %f212;
	mov.u32 	%r307, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r13, %f37;
	bfe.u32 	%r74, %r13, 23, 8;
	add.s32 	%r14, %r74, -128;
	shl.b32 	%r75, %r13, 8;
	or.b32  	%r15, %r75, -2147483648;
	shr.u32 	%r16, %r14, 5;
	mov.u64 	%rd103, 0;
	mov.u32 	%r304, 0;
	mov.u64 	%rd101, %rd1;
	mov.u64 	%rd102, %rd39;

$L__BB0_11:
	.pragma "nounroll";
	ld.global.nc.u32 	%r76, [%rd102];
	mad.wide.u32 	%rd41, %r76, %r15, %rd103;
	shr.u64 	%rd103, %rd41, 32;
	st.local.u32 	[%rd101], %rd41;
	add.s64 	%rd102, %rd102, 4;
	add.s64 	%rd101, %rd101, 4;
	add.s32 	%r304, %r304, 1;
	setp.ne.s32 	%p15, %r304, 6;
	@%p15 bra 	$L__BB0_11;

	st.local.u32 	[%rd5], %rd103;
	mov.u32 	%r77, 4;
	sub.s32 	%r19, %r77, %r16;
	mov.u32 	%r78, 6;
	sub.s32 	%r79, %r78, %r16;
	mul.wide.s32 	%rd42, %r79, 4;
	add.s64 	%rd43, %rd1, %rd42;
	ld.local.u32 	%r305, [%rd43];
	ld.local.u32 	%r306, [%rd43+-4];
	and.b32  	%r22, %r14, 31;
	setp.eq.s32 	%p16, %r22, 0;
	@%p16 bra 	$L__BB0_14;

	mov.u32 	%r80, 32;
	sub.s32 	%r81, %r80, %r22;
	shr.u32 	%r82, %r306, %r81;
	shl.b32 	%r83, %r305, %r22;
	add.s32 	%r305, %r82, %r83;
	mul.wide.s32 	%rd44, %r19, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r84, [%rd45];
	shr.u32 	%r85, %r84, %r81;
	shl.b32 	%r86, %r306, %r22;
	add.s32 	%r306, %r85, %r86;

$L__BB0_14:
	and.b32  	%r87, %r13, -2147483648;
	shr.u32 	%r88, %r306, 30;
	shl.b32 	%r89, %r305, 2;
	or.b32  	%r90, %r88, %r89;
	shr.u32 	%r91, %r90, 31;
	shr.u32 	%r92, %r305, 30;
	add.s32 	%r93, %r91, %r92;
	neg.s32 	%r94, %r93;
	setp.eq.s32 	%p17, %r87, 0;
	selp.b32 	%r307, %r93, %r94, %p17;
	setp.ne.s32 	%p18, %r91, 0;
	xor.b32  	%r95, %r87, -2147483648;
	selp.b32 	%r96, %r95, %r87, %p18;
	selp.b32 	%r97, -1, 0, %p18;
	xor.b32  	%r98, %r90, %r97;
	shl.b32 	%r99, %r306, 2;
	xor.b32  	%r100, %r99, %r97;
	cvt.u64.u32 	%rd46, %r98;
	cvt.u64.u32 	%rd47, %r100;
	bfi.b64 	%rd48, %rd46, %rd47, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd48;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f210, %fd2;
	setp.eq.s32 	%p19, %r96, 0;
	neg.f32 	%f211, %f210;
	selp.f32 	%f675, %f210, %f211, %p19;

$L__BB0_16:
	add.s32 	%r29, %r307, 1;
	and.b32  	%r30, %r29, 1;
	setp.eq.s32 	%p20, %r30, 0;
	selp.f32 	%f43, %f675, 0f3F800000, %p20;
	mul.rn.f32 	%f44, %f675, %f675;
	mov.f32 	%f676, 0fB94D4153;
	@%p20 bra 	$L__BB0_18;

	mov.f32 	%f214, 0fBAB607ED;
	mov.f32 	%f215, 0f37CBAC00;
	fma.rn.f32 	%f676, %f215, %f44, %f214;

$L__BB0_18:
	selp.f32 	%f216, 0f3C0885E4, 0f3D2AAABB, %p20;
	fma.rn.f32 	%f217, %f676, %f44, %f216;
	selp.f32 	%f218, 0fBE2AAAA8, 0fBEFFFFFF, %p20;
	fma.rn.f32 	%f219, %f217, %f44, %f218;
	mov.f32 	%f220, 0f00000000;
	fma.rn.f32 	%f221, %f44, %f43, %f220;
	fma.rn.f32 	%f677, %f219, %f221, %f43;
	and.b32  	%r102, %r29, 2;
	setp.eq.s32 	%p22, %r102, 0;
	@%p22 bra 	$L__BB0_20;

	mov.f32 	%f223, 0fBF800000;
	fma.rn.f32 	%f677, %f677, %f223, %f220;

$L__BB0_20:
	@%p13 bra 	$L__BB0_28;

	setp.eq.f32 	%p24, %f39, 0f7F800000;
	@%p24 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f226, 0f00000000;
	mul.rn.f32 	%f678, %f37, %f226;
	mov.u32 	%r310, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r31, %f37;
	bfe.u32 	%r103, %r31, 23, 8;
	add.s32 	%r32, %r103, -128;
	shl.b32 	%r104, %r31, 8;
	or.b32  	%r33, %r104, -2147483648;
	shr.u32 	%r34, %r32, 5;
	mov.u64 	%rd104, 0;
	mov.u64 	%rd105, %rd104;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd51, %rd104, 2;
	mov.u64 	%rd52, __cudart_i2opi_f;
	add.s64 	%rd53, %rd52, %rd51;
	ld.global.nc.u32 	%r105, [%rd53];
	mad.wide.u32 	%rd54, %r105, %r33, %rd105;
	shr.u64 	%rd105, %rd54, 32;
	add.s64 	%rd55, %rd1, %rd51;
	st.local.u32 	[%rd55], %rd54;
	cvt.u32.u64 	%r106, %rd104;
	add.s32 	%r107, %r106, 1;
	cvt.s64.s32 	%rd104, %r107;
	setp.ne.s32 	%p25, %r107, 6;
	@%p25 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd105;
	mov.u32 	%r108, 4;
	sub.s32 	%r35, %r108, %r34;
	mov.u32 	%r109, 6;
	sub.s32 	%r110, %r109, %r34;
	mul.wide.s32 	%rd56, %r110, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r308, [%rd57];
	ld.local.u32 	%r309, [%rd57+-4];
	and.b32  	%r38, %r32, 31;
	setp.eq.s32 	%p26, %r38, 0;
	@%p26 bra 	$L__BB0_26;

	mov.u32 	%r111, 32;
	sub.s32 	%r112, %r111, %r38;
	shr.u32 	%r113, %r309, %r112;
	shl.b32 	%r114, %r308, %r38;
	add.s32 	%r308, %r113, %r114;
	mul.wide.s32 	%rd58, %r35, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r115, [%rd59];
	shr.u32 	%r116, %r115, %r112;
	shl.b32 	%r117, %r309, %r38;
	add.s32 	%r309, %r116, %r117;

$L__BB0_26:
	and.b32  	%r118, %r31, -2147483648;
	shr.u32 	%r119, %r309, 30;
	shl.b32 	%r120, %r308, 2;
	or.b32  	%r121, %r119, %r120;
	shr.u32 	%r122, %r121, 31;
	shr.u32 	%r123, %r308, 30;
	add.s32 	%r124, %r122, %r123;
	neg.s32 	%r125, %r124;
	setp.eq.s32 	%p27, %r118, 0;
	selp.b32 	%r310, %r124, %r125, %p27;
	setp.ne.s32 	%p28, %r122, 0;
	xor.b32  	%r126, %r118, -2147483648;
	selp.b32 	%r127, %r126, %r118, %p28;
	selp.b32 	%r128, -1, 0, %p28;
	xor.b32  	%r129, %r121, %r128;
	shl.b32 	%r130, %r309, 2;
	xor.b32  	%r131, %r130, %r128;
	cvt.u64.u32 	%rd60, %r129;
	cvt.u64.u32 	%rd61, %r131;
	bfi.b64 	%rd62, %rd60, %rd61, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd62;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f224, %fd4;
	setp.eq.s32 	%p29, %r127, 0;
	neg.f32 	%f225, %f224;
	selp.f32 	%f678, %f224, %f225, %p29;

$L__BB0_28:
	mul.f32 	%f53, %f36, %f677;
	and.b32  	%r45, %r310, 1;
	setp.eq.s32 	%p30, %r45, 0;
	selp.f32 	%f54, %f678, 0f3F800000, %p30;
	mul.rn.f32 	%f55, %f678, %f678;
	mov.f32 	%f679, 0fB94D4153;
	@%p30 bra 	$L__BB0_30;

	mov.f32 	%f228, 0fBAB607ED;
	mov.f32 	%f229, 0f37CBAC00;
	fma.rn.f32 	%f679, %f229, %f55, %f228;

$L__BB0_30:
	selp.f32 	%f230, 0f3C0885E4, 0f3D2AAABB, %p30;
	fma.rn.f32 	%f231, %f679, %f55, %f230;
	selp.f32 	%f232, 0fBE2AAAA8, 0fBEFFFFFF, %p30;
	fma.rn.f32 	%f233, %f231, %f55, %f232;
	mov.f32 	%f234, 0f00000000;
	fma.rn.f32 	%f235, %f55, %f54, %f234;
	fma.rn.f32 	%f680, %f233, %f235, %f54;
	and.b32  	%r133, %r310, 2;
	setp.eq.s32 	%p32, %r133, 0;
	@%p32 bra 	$L__BB0_32;

	mov.f32 	%f237, 0fBF800000;
	fma.rn.f32 	%f680, %f680, %f237, %f234;

$L__BB0_32:
	mul.f32 	%f247, %f36, %f680;
	mul.f32 	%f248, %f14, %f247;
	mul.f32 	%f249, %f15, %f247;
	mul.f32 	%f250, %f16, %f247;
	fma.rn.f32 	%f251, %f23, %f53, %f248;
	fma.rn.f32 	%f252, %f22, %f53, %f249;
	fma.rn.f32 	%f253, %f21, %f53, %f250;
	fma.rn.f32 	%f241, %f662, %f35, %f251;
	fma.rn.f32 	%f242, %f663, %f35, %f252;
	fma.rn.f32 	%f243, %f664, %f35, %f253;
	mov.f32 	%f259, 0f38D1B717;
	max.f32 	%f244, %f258, %f259;
	mov.u32 	%r170, 2;
	mov.u32 	%r172, 1;
	mov.u32 	%r173, 1065353216;
	mov.u32 	%r204, 0;
	// begin inline asm
	call(%r134,%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165),_optix_trace_typed_32,(%r204,%rd4,%f11,%f12,%f13,%f241,%f242,%f243,%f244,%f1,%f234,%r172,%r204,%r172,%r170,%r172,%r172,%r173,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204,%r204);
	// end inline asm
	mov.b32 	%f260, %r134;
	add.f32 	%f674, %f674, %f260;
	mul.f32 	%f261, %f663, %f242;
	fma.rn.f32 	%f262, %f662, %f241, %f261;
	fma.rn.f32 	%f263, %f664, %f243, %f262;
	mul.f32 	%f264, %f263, 0f40800000;
	cvt.sat.f32.f32 	%f265, %f264;
	mul.f32 	%f266, %f265, %f260;
	fma.rn.f32 	%f673, %f241, %f266, %f673;
	fma.rn.f32 	%f671, %f242, %f266, %f671;
	fma.rn.f32 	%f670, %f243, %f266, %f670;
	add.f32 	%f672, %f672, %f266;
	add.s32 	%r302, %r302, 1;
	setp.lt.s32 	%p33, %r302, %r5;
	@%p33 bra 	$L__BB0_8;

	add.s32 	%r300, %r300, 1;
	setp.lt.s32 	%p34, %r300, %r5;
	@%p34 bra 	$L__BB0_7;

$L__BB0_34:
	mul.lo.s32 	%r205, %r5, %r5;
	cvt.rn.f32.s32 	%f267, %r205;
	div.rn.f32 	%f71, %f674, %f267;
	div.rn.f32 	%f72, %f672, %f267;
	div.rn.f32 	%f73, %f673, %f267;
	div.rn.f32 	%f74, %f671, %f267;
	div.rn.f32 	%f75, %f670, %f267;
	ld.const.f32 	%f76, [params+704];
	setp.lt.f32 	%p35, %f76, 0f00000000;
	@%p35 bra 	$L__BB0_36;
	bra.uni 	$L__BB0_35;

$L__BB0_36:
	neg.f32 	%f79, %f76;
	setp.lt.f32 	%p36, %f76, 0fBF800000;
	@%p36 bra 	$L__BB0_38;
	bra.uni 	$L__BB0_37;

$L__BB0_38:
	mul.f32 	%f277, %f76, 0fBF000000;
	cvt.rzi.f32.f32 	%f278, %f277;
	add.f32 	%f279, %f278, %f278;
	sub.f32 	%f280, %f79, %f279;
	abs.f32 	%f82, %f280;
	abs.f32 	%f83, %f71;
	setp.lt.f32 	%p37, %f83, 0f00800000;
	mul.f32 	%f281, %f83, 0f4B800000;
	selp.f32 	%f282, %f281, %f83, %p37;
	selp.f32 	%f283, 0fC3170000, 0fC2FE0000, %p37;
	mov.b32 	%r206, %f282;
	and.b32  	%r207, %r206, 8388607;
	or.b32  	%r208, %r207, 1065353216;
	mov.b32 	%f284, %r208;
	shr.u32 	%r209, %r206, 23;
	cvt.rn.f32.u32 	%f285, %r209;
	add.f32 	%f286, %f283, %f285;
	setp.gt.f32 	%p38, %f284, 0f3FB504F3;
	mul.f32 	%f287, %f284, 0f3F000000;
	add.f32 	%f288, %f286, 0f3F800000;
	selp.f32 	%f289, %f288, %f286, %p38;
	selp.f32 	%f290, %f287, %f284, %p38;
	add.f32 	%f291, %f290, 0fBF800000;
	add.f32 	%f292, %f290, 0f3F800000;
	rcp.approx.ftz.f32 	%f293, %f292;
	add.f32 	%f294, %f291, %f291;
	mul.f32 	%f295, %f294, %f293;
	mul.f32 	%f296, %f295, %f295;
	mov.f32 	%f297, 0f3C4CAF63;
	mov.f32 	%f298, 0f3B18F0FE;
	fma.rn.f32 	%f299, %f298, %f296, %f297;
	mov.f32 	%f300, 0f3DAAAABD;
	fma.rn.f32 	%f301, %f299, %f296, %f300;
	mul.rn.f32 	%f302, %f301, %f296;
	mul.rn.f32 	%f303, %f302, %f295;
	sub.f32 	%f304, %f291, %f295;
	add.f32 	%f305, %f304, %f304;
	neg.f32 	%f306, %f295;
	fma.rn.f32 	%f307, %f306, %f291, %f305;
	mul.rn.f32 	%f308, %f293, %f307;
	add.f32 	%f309, %f303, %f295;
	sub.f32 	%f310, %f295, %f309;
	add.f32 	%f311, %f303, %f310;
	add.f32 	%f312, %f308, %f311;
	add.f32 	%f313, %f309, %f312;
	sub.f32 	%f314, %f309, %f313;
	add.f32 	%f315, %f312, %f314;
	mov.f32 	%f316, 0f3F317200;
	mul.rn.f32 	%f317, %f289, %f316;
	mov.f32 	%f318, 0f35BFBE8E;
	mul.rn.f32 	%f319, %f289, %f318;
	add.f32 	%f320, %f317, %f313;
	sub.f32 	%f321, %f317, %f320;
	add.f32 	%f322, %f313, %f321;
	add.f32 	%f323, %f315, %f322;
	add.f32 	%f324, %f319, %f323;
	add.f32 	%f325, %f320, %f324;
	sub.f32 	%f326, %f320, %f325;
	add.f32 	%f327, %f324, %f326;
	abs.f32 	%f84, %f79;
	setp.gt.f32 	%p39, %f84, 0f77F684DF;
	mul.f32 	%f328, %f76, 0fB9000000;
	selp.f32 	%f85, %f328, %f79, %p39;
	mul.rn.f32 	%f329, %f85, %f325;
	neg.f32 	%f330, %f329;
	fma.rn.f32 	%f331, %f85, %f325, %f330;
	fma.rn.f32 	%f332, %f85, %f327, %f331;
	mov.f32 	%f333, 0f00000000;
	fma.rn.f32 	%f334, %f333, %f325, %f332;
	add.rn.f32 	%f335, %f329, %f334;
	neg.f32 	%f336, %f335;
	add.rn.f32 	%f337, %f329, %f336;
	add.rn.f32 	%f338, %f337, %f334;
	mov.b32 	%r210, %f335;
	setp.eq.s32 	%p40, %r210, 1118925336;
	add.s32 	%r211, %r210, -1;
	mov.b32 	%f339, %r211;
	add.f32 	%f340, %f338, 0f37000000;
	selp.f32 	%f86, %f340, %f338, %p40;
	selp.f32 	%f341, %f339, %f335, %p40;
	mov.f32 	%f342, 0f3FB8AA3B;
	mul.rn.f32 	%f343, %f341, %f342;
	cvt.rzi.f32.f32 	%f344, %f343;
	abs.f32 	%f345, %f344;
	setp.gt.f32 	%p41, %f345, 0f42FC0000;
	mov.b32 	%r212, %f344;
	and.b32  	%r213, %r212, -2147483648;
	or.b32  	%r214, %r213, 1123811328;
	mov.b32 	%f346, %r214;
	selp.f32 	%f347, %f346, %f344, %p41;
	mov.f32 	%f348, 0fBF317218;
	fma.rn.f32 	%f349, %f347, %f348, %f341;
	mov.f32 	%f350, 0f3102E308;
	fma.rn.f32 	%f351, %f347, %f350, %f349;
	mul.f32 	%f352, %f351, 0f3FB8AA3B;
	add.f32 	%f353, %f347, 0f4B40007F;
	mov.b32 	%r215, %f353;
	shl.b32 	%r216, %r215, 23;
	mov.b32 	%f354, %r216;
	ex2.approx.ftz.f32 	%f355, %f352;
	mul.f32 	%f87, %f355, %f354;
	setp.eq.f32 	%p42, %f87, 0f7F800000;
	mov.f32 	%f686, 0f7F800000;
	@%p42 bra 	$L__BB0_40;

	fma.rn.f32 	%f686, %f87, %f86, %f87;

$L__BB0_40:
	setp.lt.f32 	%p43, %f71, 0f00000000;
	setp.eq.f32 	%p44, %f82, 0f3F800000;
	and.pred  	%p1, %p43, %p44;
	setp.eq.f32 	%p45, %f71, 0f00000000;
	@%p45 bra 	$L__BB0_44;
	bra.uni 	$L__BB0_41;

$L__BB0_44:
	ld.const.f32 	%f658, [params+704];
	add.f32 	%f359, %f71, %f71;
	mov.b32 	%r219, %f359;
	selp.b32 	%r220, %r219, 0, %p44;
	or.b32  	%r221, %r220, 2139095040;
	setp.gt.f32 	%p49, %f658, 0f80000000;
	selp.b32 	%r222, %r221, %r220, %p49;
	mov.b32 	%f688, %r222;
	bra.uni 	$L__BB0_45;

$L__BB0_35:
	add.f32 	%f268, %f71, 0fBF800000;
	fma.rn.f32 	%f269, %f76, %f268, 0f3F800000;
	cvt.sat.f32.f32 	%f692, %f269;
	add.f32 	%f270, %f72, 0fBF800000;
	fma.rn.f32 	%f271, %f76, %f270, 0f3F800000;
	cvt.sat.f32.f32 	%f693, %f271;
	bra.uni 	$L__BB0_67;

$L__BB0_37:
	add.f32 	%f272, %f71, 0fBF800000;
	fma.rn.f32 	%f273, %f272, %f79, 0f3F800000;
	cvt.sat.f32.f32 	%f692, %f273;
	add.f32 	%f274, %f72, 0fBF800000;
	fma.rn.f32 	%f275, %f274, %f79, 0f3F800000;
	cvt.sat.f32.f32 	%f693, %f275;
	bra.uni 	$L__BB0_67;

$L__BB0_100:
	mov.f32 	%f604, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f604;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs104, %f604;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs103, %f604;}

	// end inline asm
	mov.u16 	%rs106, 0;
	st.global.v4.u16 	[%rd23], {%rs103, %rs104, %rs105, %rs106};

$L__BB0_101:
	and.b32  	%r288, %r50, 8;
	setp.eq.s32 	%p112, %r288, 0;
	@%p112 bra 	$L__BB0_103;

	ld.const.u64 	%rd85, [params+192];
	cvta.to.global.u64 	%rd86, %rd85;
	ld.const.u32 	%r289, [params+184];
	mad.lo.s32 	%r290, %r289, %r4, %r3;
	mov.f32 	%f605, 0f00000000;
	cvt.rzi.u32.f32 	%r291, %f605;
	mul.wide.u32 	%rd87, %r290, 2;
	add.s64 	%rd88, %rd86, %rd87;
	mov.u16 	%rs107, 0;
	cvt.u16.u32 	%rs108, %r291;
	st.global.v2.u8 	[%rd88], {%rs108, %rs107};

$L__BB0_103:
	ld.const.u32 	%r51, [params+108];
	setp.eq.s32 	%p113, %r51, 0;
	ld.const.u64 	%rd89, [params+256];
	cvta.to.global.u64 	%rd90, %rd89;
	ld.const.u32 	%r292, [params+248];
	mad.lo.s32 	%r293, %r292, %r4, %r3;
	mul.wide.u32 	%rd91, %r293, 8;
	add.s64 	%rd24, %rd90, %rd91;
	@%p113 bra 	$L__BB0_105;

	ld.global.v4.u16 	{%rs115, %rs116, %rs117, %rs118}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f606, %rs115;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f607, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f608, %rs117;}

	// end inline asm
	add.f32 	%f609, %f606, 0f00000000;
	add.f32 	%f610, %f607, 0f00000000;
	add.f32 	%f611, %f608, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f611;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f610;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f609;}

	// end inline asm
	mov.u16 	%rs119, 0;
	st.global.v4.u16 	[%rd24], {%rs112, %rs113, %rs114, %rs119};
	bra.uni 	$L__BB0_106;

$L__BB0_105:
	mov.f32 	%f614, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f614;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f614;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f614;}

	// end inline asm
	mov.u16 	%rs123, 0;
	st.global.v4.u16 	[%rd24], {%rs120, %rs121, %rs122, %rs123};

$L__BB0_106:
	ld.const.u64 	%rd92, [params+272];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r294, [params+264];
	mad.lo.s32 	%r295, %r294, %r4, %r3;
	mul.wide.u32 	%rd94, %r295, 8;
	add.s64 	%rd25, %rd93, %rd94;
	@%p113 bra 	$L__BB0_108;

	ld.global.v4.u16 	{%rs130, %rs131, %rs132, %rs133}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f615, %rs130;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f616, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f617, %rs132;}

	// end inline asm
	add.f32 	%f618, %f615, 0f00000000;
	add.f32 	%f619, %f616, 0f00000000;
	add.f32 	%f620, %f617, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f620;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f619;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f618;}

	// end inline asm
	mov.u16 	%rs134, 0;
	st.global.v4.u16 	[%rd25], {%rs127, %rs128, %rs129, %rs134};
	bra.uni 	$L__BB0_109;

$L__BB0_108:
	mov.f32 	%f623, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f623;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f623;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f623;}

	// end inline asm
	mov.u16 	%rs138, 0;
	st.global.v4.u16 	[%rd25], {%rs135, %rs136, %rs137, %rs138};

$L__BB0_109:
	ld.const.u64 	%rd95, [params+288];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r296, [params+280];
	mad.lo.s32 	%r297, %r296, %r4, %r3;
	mul.wide.u32 	%rd97, %r297, 8;
	add.s64 	%rd26, %rd96, %rd97;
	@%p113 bra 	$L__BB0_111;

	ld.global.v4.u16 	{%rs145, %rs146, %rs147, %rs148}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f624, %rs145;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f625, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f626, %rs147;}

	// end inline asm
	add.f32 	%f627, %f624, 0f00000000;
	add.f32 	%f628, %f625, 0f00000000;
	add.f32 	%f629, %f626, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f629;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f628;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f627;}

	// end inline asm
	mov.u16 	%rs149, 0;
	st.global.v4.u16 	[%rd26], {%rs142, %rs143, %rs144, %rs149};
	bra.uni 	$L__BB0_112;

$L__BB0_111:
	mov.f32 	%f632, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f632;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f632;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f632;}

	// end inline asm
	mov.u16 	%rs153, 0;
	st.global.v4.u16 	[%rd26], {%rs150, %rs151, %rs152, %rs153};

$L__BB0_112:
	ld.const.u64 	%rd98, [params+304];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r298, [params+296];
	mad.lo.s32 	%r299, %r298, %r4, %r3;
	mul.wide.u32 	%rd100, %r299, 8;
	add.s64 	%rd27, %rd99, %rd100;
	@%p113 bra 	$L__BB0_114;

	ld.global.v4.u16 	{%rs160, %rs161, %rs162, %rs163}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f633, %rs160;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f634, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f635, %rs162;}

	// end inline asm
	add.f32 	%f636, %f633, 0f00000000;
	add.f32 	%f637, %f634, 0f00000000;
	add.f32 	%f638, %f635, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f638;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f637;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f636;}

	// end inline asm
	mov.u16 	%rs164, 0;
	st.global.v4.u16 	[%rd27], {%rs157, %rs158, %rs159, %rs164};
	bra.uni 	$L__BB0_115;

$L__BB0_114:
	mov.f32 	%f641, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f641;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f641;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f641;}

	// end inline asm
	mov.u16 	%rs168, 0;
	st.global.v4.u16 	[%rd27], {%rs165, %rs166, %rs167, %rs168};
	bra.uni 	$L__BB0_115;

$L__BB0_41:
	mov.b32 	%r217, %f686;
	xor.b32  	%r218, %r217, -2147483648;
	mov.b32 	%f356, %r218;
	selp.f32 	%f688, %f356, %f686, %p1;
	setp.geu.f32 	%p46, %f71, 0f00000000;
	@%p46 bra 	$L__BB0_45;

	ld.const.f32 	%f657, [params+704];
	neg.f32 	%f656, %f657;
	cvt.rzi.f32.f32 	%f357, %f656;
	setp.eq.f32 	%p47, %f357, %f656;
	@%p47 bra 	$L__BB0_45;

	mov.f32 	%f688, 0f7FFFFFFF;

$L__BB0_45:
	abs.f32 	%f642, %f71;
	add.f32 	%f360, %f642, %f84;
	mov.b32 	%r223, %f360;
	setp.lt.s32 	%p50, %r223, 2139095040;
	@%p50 bra 	$L__BB0_52;

	abs.f32 	%f650, %f71;
	setp.gtu.f32 	%p51, %f650, 0f7F800000;
	setp.gtu.f32 	%p52, %f84, 0f7F800000;
	or.pred  	%p53, %p51, %p52;
	@%p53 bra 	$L__BB0_51;
	bra.uni 	$L__BB0_47;

$L__BB0_51:
	ld.const.f32 	%f655, [params+704];
	sub.f32 	%f688, %f71, %f655;
	bra.uni 	$L__BB0_52;

$L__BB0_47:
	setp.eq.f32 	%p54, %f84, 0f7F800000;
	@%p54 bra 	$L__BB0_50;
	bra.uni 	$L__BB0_48;

$L__BB0_50:
	abs.f32 	%f654, %f71;
	ld.const.f32 	%f653, [params+704];
	setp.gt.f32 	%p57, %f654, 0f3F800000;
	selp.b32 	%r227, 2139095040, 0, %p57;
	xor.b32  	%r228, %r227, 2139095040;
	setp.gt.f32 	%p58, %f653, 0f80000000;
	selp.b32 	%r229, %r228, %r227, %p58;
	mov.b32 	%f361, %r229;
	setp.eq.f32 	%p59, %f71, 0fBF800000;
	selp.f32 	%f688, 0f3F800000, %f361, %p59;
	bra.uni 	$L__BB0_52;

$L__BB0_48:
	abs.f32 	%f651, %f71;
	setp.neu.f32 	%p55, %f651, 0f7F800000;
	@%p55 bra 	$L__BB0_52;

	ld.const.f32 	%f652, [params+704];
	setp.le.f32 	%p56, %f652, 0f80000000;
	selp.b32 	%r224, 2139095040, 0, %p56;
	or.b32  	%r225, %r224, -2147483648;
	selp.b32 	%r226, %r225, %r224, %p1;
	mov.b32 	%f688, %r226;

$L__BB0_52:
	ld.const.f32 	%f643, [params+704];
	setp.eq.f32 	%p60, %f643, 0f80000000;
	setp.eq.f32 	%p61, %f71, 0f3F800000;
	or.pred  	%p62, %p60, %p61;
	selp.f32 	%f363, 0f3F800000, %f688, %p62;
	cvt.sat.f32.f32 	%f692, %f363;
	abs.f32 	%f98, %f72;
	setp.lt.f32 	%p63, %f98, 0f00800000;
	mul.f32 	%f364, %f98, 0f4B800000;
	selp.f32 	%f365, %f364, %f98, %p63;
	selp.f32 	%f366, 0fC3170000, 0fC2FE0000, %p63;
	mov.b32 	%r230, %f365;
	and.b32  	%r231, %r230, 8388607;
	or.b32  	%r232, %r231, 1065353216;
	mov.b32 	%f367, %r232;
	shr.u32 	%r233, %r230, 23;
	cvt.rn.f32.u32 	%f368, %r233;
	add.f32 	%f369, %f366, %f368;
	setp.gt.f32 	%p64, %f367, 0f3FB504F3;
	mul.f32 	%f370, %f367, 0f3F000000;
	add.f32 	%f371, %f369, 0f3F800000;
	selp.f32 	%f372, %f371, %f369, %p64;
	selp.f32 	%f373, %f370, %f367, %p64;
	add.f32 	%f374, %f373, 0fBF800000;
	add.f32 	%f375, %f373, 0f3F800000;
	rcp.approx.ftz.f32 	%f376, %f375;
	add.f32 	%f377, %f374, %f374;
	mul.f32 	%f378, %f377, %f376;
	mul.f32 	%f379, %f378, %f378;
	mov.f32 	%f380, 0f3C4CAF63;
	mov.f32 	%f381, 0f3B18F0FE;
	fma.rn.f32 	%f382, %f381, %f379, %f380;
	mov.f32 	%f383, 0f3DAAAABD;
	fma.rn.f32 	%f384, %f382, %f379, %f383;
	mul.rn.f32 	%f385, %f384, %f379;
	mul.rn.f32 	%f386, %f385, %f378;
	sub.f32 	%f387, %f374, %f378;
	add.f32 	%f388, %f387, %f387;
	neg.f32 	%f389, %f378;
	fma.rn.f32 	%f390, %f389, %f374, %f388;
	mul.rn.f32 	%f391, %f376, %f390;
	add.f32 	%f392, %f386, %f378;
	sub.f32 	%f393, %f378, %f392;
	add.f32 	%f394, %f386, %f393;
	add.f32 	%f395, %f391, %f394;
	add.f32 	%f396, %f392, %f395;
	sub.f32 	%f397, %f392, %f396;
	add.f32 	%f398, %f395, %f397;
	mov.f32 	%f399, 0f3F317200;
	mul.rn.f32 	%f400, %f372, %f399;
	mov.f32 	%f401, 0f35BFBE8E;
	mul.rn.f32 	%f402, %f372, %f401;
	add.f32 	%f403, %f400, %f396;
	sub.f32 	%f404, %f400, %f403;
	add.f32 	%f405, %f396, %f404;
	add.f32 	%f406, %f398, %f405;
	add.f32 	%f407, %f402, %f406;
	add.f32 	%f408, %f403, %f407;
	sub.f32 	%f409, %f403, %f408;
	add.f32 	%f410, %f407, %f409;
	mul.rn.f32 	%f411, %f85, %f408;
	neg.f32 	%f412, %f411;
	fma.rn.f32 	%f413, %f85, %f408, %f412;
	fma.rn.f32 	%f414, %f85, %f410, %f413;
	mov.f32 	%f415, 0f00000000;
	fma.rn.f32 	%f416, %f415, %f408, %f414;
	add.rn.f32 	%f417, %f411, %f416;
	neg.f32 	%f418, %f417;
	add.rn.f32 	%f419, %f411, %f418;
	add.rn.f32 	%f420, %f419, %f416;
	mov.b32 	%r234, %f417;
	setp.eq.s32 	%p65, %r234, 1118925336;
	add.s32 	%r235, %r234, -1;
	mov.b32 	%f421, %r235;
	add.f32 	%f422, %f420, 0f37000000;
	selp.f32 	%f99, %f422, %f420, %p65;
	selp.f32 	%f423, %f421, %f417, %p65;
	mov.f32 	%f424, 0f3FB8AA3B;
	mul.rn.f32 	%f425, %f423, %f424;
	cvt.rzi.f32.f32 	%f426, %f425;
	abs.f32 	%f427, %f426;
	setp.gt.f32 	%p66, %f427, 0f42FC0000;
	mov.b32 	%r236, %f426;
	and.b32  	%r237, %r236, -2147483648;
	or.b32  	%r238, %r237, 1123811328;
	mov.b32 	%f428, %r238;
	selp.f32 	%f429, %f428, %f426, %p66;
	mov.f32 	%f430, 0fBF317218;
	fma.rn.f32 	%f431, %f429, %f430, %f423;
	mov.f32 	%f432, 0f3102E308;
	fma.rn.f32 	%f433, %f429, %f432, %f431;
	mul.f32 	%f434, %f433, 0f3FB8AA3B;
	add.f32 	%f435, %f429, 0f4B40007F;
	mov.b32 	%r239, %f435;
	shl.b32 	%r240, %r239, 23;
	mov.b32 	%f436, %r240;
	ex2.approx.ftz.f32 	%f437, %f434;
	mul.f32 	%f100, %f437, %f436;
	setp.eq.f32 	%p67, %f100, 0f7F800000;
	mov.f32 	%f689, 0f7F800000;
	@%p67 bra 	$L__BB0_54;

	fma.rn.f32 	%f689, %f100, %f99, %f100;

$L__BB0_54:
	setp.lt.f32 	%p68, %f72, 0f00000000;
	and.pred  	%p2, %p68, %p44;
	setp.eq.f32 	%p70, %f72, 0f00000000;
	@%p70 bra 	$L__BB0_58;
	bra.uni 	$L__BB0_55;

$L__BB0_58:
	ld.const.f32 	%f649, [params+704];
	add.f32 	%f441, %f72, %f72;
	mov.b32 	%r243, %f441;
	selp.b32 	%r244, %r243, 0, %p44;
	or.b32  	%r245, %r244, 2139095040;
	setp.gt.f32 	%p74, %f649, 0f80000000;
	selp.b32 	%r246, %r245, %r244, %p74;
	mov.b32 	%f691, %r246;
	bra.uni 	$L__BB0_59;

$L__BB0_55:
	mov.b32 	%r241, %f689;
	xor.b32  	%r242, %r241, -2147483648;
	mov.b32 	%f438, %r242;
	selp.f32 	%f691, %f438, %f689, %p2;
	setp.geu.f32 	%p71, %f72, 0f00000000;
	@%p71 bra 	$L__BB0_59;

	ld.const.f32 	%f648, [params+704];
	neg.f32 	%f647, %f648;
	cvt.rzi.f32.f32 	%f439, %f647;
	setp.eq.f32 	%p72, %f439, %f647;
	@%p72 bra 	$L__BB0_59;

	mov.f32 	%f691, 0f7FFFFFFF;

$L__BB0_59:
	add.f32 	%f442, %f98, %f84;
	mov.b32 	%r247, %f442;
	setp.lt.s32 	%p75, %r247, 2139095040;
	@%p75 bra 	$L__BB0_66;

	setp.gtu.f32 	%p76, %f98, 0f7F800000;
	setp.gtu.f32 	%p77, %f84, 0f7F800000;
	or.pred  	%p78, %p76, %p77;
	@%p78 bra 	$L__BB0_65;
	bra.uni 	$L__BB0_61;

$L__BB0_65:
	ld.const.f32 	%f646, [params+704];
	sub.f32 	%f691, %f72, %f646;
	bra.uni 	$L__BB0_66;

$L__BB0_61:
	setp.eq.f32 	%p79, %f84, 0f7F800000;
	@%p79 bra 	$L__BB0_64;
	bra.uni 	$L__BB0_62;

$L__BB0_64:
	ld.const.f32 	%f645, [params+704];
	setp.gt.f32 	%p82, %f98, 0f3F800000;
	selp.b32 	%r251, 2139095040, 0, %p82;
	xor.b32  	%r252, %r251, 2139095040;
	setp.gt.f32 	%p83, %f645, 0f80000000;
	selp.b32 	%r253, %r252, %r251, %p83;
	mov.b32 	%f443, %r253;
	setp.eq.f32 	%p84, %f72, 0fBF800000;
	selp.f32 	%f691, 0f3F800000, %f443, %p84;
	bra.uni 	$L__BB0_66;

$L__BB0_62:
	setp.neu.f32 	%p80, %f98, 0f7F800000;
	@%p80 bra 	$L__BB0_66;

	ld.const.f32 	%f644, [params+704];
	setp.le.f32 	%p81, %f644, 0f80000000;
	selp.b32 	%r248, 2139095040, 0, %p81;
	or.b32  	%r249, %r248, -2147483648;
	selp.b32 	%r250, %r249, %r248, %p2;
	mov.b32 	%f691, %r250;

$L__BB0_66:
	setp.eq.f32 	%p85, %f72, 0f3F800000;
	or.pred  	%p87, %p60, %p85;
	selp.f32 	%f444, 0f3F800000, %f691, %p87;
	cvt.sat.f32.f32 	%f693, %f444;

$L__BB0_67:
	ld.const.u32 	%r48, [params+104];
	and.b32  	%r254, %r48, 4;
	setp.eq.s32 	%p88, %r254, 0;
	@%p88 bra 	$L__BB0_71;

	ld.const.u32 	%r255, [params+108];
	setp.eq.s32 	%p89, %r255, 0;
	ld.const.u64 	%rd64, [params+224];
	cvta.to.global.u64 	%rd65, %rd64;
	ld.const.u32 	%r256, [params+216];
	mad.lo.s32 	%r257, %r256, %r4, %r3;
	mul.wide.u32 	%rd66, %r257, 8;
	add.s64 	%rd16, %rd65, %rd66;
	@%p89 bra 	$L__BB0_70;

	ld.global.v4.u16 	{%rs22, %rs23, %rs24, %rs25}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f445, %rs22;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f446, %rs23;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f447, %rs24;}

	// end inline asm
	add.f32 	%f448, %f692, %f445;
	add.f32 	%f449, %f692, %f446;
	add.f32 	%f450, %f692, %f447;
	mov.f32 	%f451, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs20, %f450;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs19, %f449;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs18, %f448;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs21, %f451;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs18, %rs19, %rs20, %rs21};
	bra.uni 	$L__BB0_71;

$L__BB0_70:
	mov.f32 	%f455, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f455;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f692;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f692;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f692;}

	// end inline asm
	st.global.v4.u16 	[%rd16], {%rs26, %rs27, %rs28, %rs29};

$L__BB0_71:
	and.b32  	%r258, %r48, 8;
	setp.eq.s32 	%p90, %r258, 0;
	@%p90 bra 	$L__BB0_85;

	ld.const.u64 	%rd67, [params+192];
	cvta.to.global.u64 	%rd17, %rd67;
	ld.const.u32 	%r259, [params+184];
	mad.lo.s32 	%r260, %r259, %r4, %r3;
	cvt.u64.u32 	%rd18, %r260;
	mov.f32 	%f457, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f458, %f457;
	add.f32 	%f459, %f458, %f458;
	mov.f32 	%f460, 0f3EE8BA2E;
	sub.f32 	%f461, %f460, %f459;
	abs.f32 	%f113, %f461;
	abs.f32 	%f114, %f692;
	setp.lt.f32 	%p91, %f114, 0f00800000;
	mul.f32 	%f462, %f114, 0f4B800000;
	selp.f32 	%f463, %f462, %f114, %p91;
	selp.f32 	%f464, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r261, %f463;
	and.b32  	%r262, %r261, 8388607;
	or.b32  	%r263, %r262, 1065353216;
	mov.b32 	%f465, %r263;
	shr.u32 	%r264, %r261, 23;
	cvt.rn.f32.u32 	%f466, %r264;
	add.f32 	%f467, %f464, %f466;
	setp.gt.f32 	%p92, %f465, 0f3FB504F3;
	mul.f32 	%f468, %f465, 0f3F000000;
	add.f32 	%f469, %f467, 0f3F800000;
	selp.f32 	%f470, %f469, %f467, %p92;
	selp.f32 	%f471, %f468, %f465, %p92;
	add.f32 	%f472, %f471, 0fBF800000;
	add.f32 	%f473, %f471, 0f3F800000;
	rcp.approx.ftz.f32 	%f474, %f473;
	add.f32 	%f475, %f472, %f472;
	mul.f32 	%f476, %f475, %f474;
	mul.f32 	%f477, %f476, %f476;
	mov.f32 	%f478, 0f3C4CAF63;
	mov.f32 	%f479, 0f3B18F0FE;
	fma.rn.f32 	%f480, %f479, %f477, %f478;
	mov.f32 	%f481, 0f3DAAAABD;
	fma.rn.f32 	%f482, %f480, %f477, %f481;
	mul.rn.f32 	%f483, %f482, %f477;
	mul.rn.f32 	%f484, %f483, %f476;
	sub.f32 	%f485, %f472, %f476;
	add.f32 	%f486, %f485, %f485;
	neg.f32 	%f487, %f476;
	fma.rn.f32 	%f488, %f487, %f472, %f486;
	mul.rn.f32 	%f489, %f474, %f488;
	add.f32 	%f490, %f484, %f476;
	sub.f32 	%f491, %f476, %f490;
	add.f32 	%f492, %f484, %f491;
	add.f32 	%f493, %f489, %f492;
	add.f32 	%f494, %f490, %f493;
	sub.f32 	%f495, %f490, %f494;
	add.f32 	%f496, %f493, %f495;
	mov.f32 	%f497, 0f3F317200;
	mul.rn.f32 	%f498, %f470, %f497;
	mov.f32 	%f499, 0f35BFBE8E;
	mul.rn.f32 	%f500, %f470, %f499;
	add.f32 	%f501, %f498, %f494;
	sub.f32 	%f502, %f498, %f501;
	add.f32 	%f503, %f494, %f502;
	add.f32 	%f504, %f496, %f503;
	add.f32 	%f505, %f500, %f504;
	add.f32 	%f506, %f501, %f505;
	sub.f32 	%f507, %f501, %f506;
	add.f32 	%f508, %f505, %f507;
	mul.rn.f32 	%f509, %f460, %f506;
	neg.f32 	%f510, %f509;
	fma.rn.f32 	%f511, %f460, %f506, %f510;
	fma.rn.f32 	%f512, %f460, %f508, %f511;
	mov.f32 	%f513, 0f00000000;
	fma.rn.f32 	%f514, %f513, %f506, %f512;
	add.rn.f32 	%f515, %f509, %f514;
	neg.f32 	%f516, %f515;
	add.rn.f32 	%f517, %f509, %f516;
	add.rn.f32 	%f518, %f517, %f514;
	mov.b32 	%r265, %f515;
	setp.eq.s32 	%p93, %r265, 1118925336;
	add.s32 	%r266, %r265, -1;
	mov.b32 	%f519, %r266;
	add.f32 	%f520, %f518, 0f37000000;
	selp.f32 	%f115, %f520, %f518, %p93;
	selp.f32 	%f521, %f519, %f515, %p93;
	mov.f32 	%f522, 0f3FB8AA3B;
	mul.rn.f32 	%f523, %f521, %f522;
	cvt.rzi.f32.f32 	%f524, %f523;
	abs.f32 	%f525, %f524;
	setp.gt.f32 	%p94, %f525, 0f42FC0000;
	mov.b32 	%r267, %f524;
	and.b32  	%r268, %r267, -2147483648;
	or.b32  	%r269, %r268, 1123811328;
	mov.b32 	%f526, %r269;
	selp.f32 	%f527, %f526, %f524, %p94;
	mov.f32 	%f528, 0fBF317218;
	fma.rn.f32 	%f529, %f527, %f528, %f521;
	mov.f32 	%f530, 0f3102E308;
	fma.rn.f32 	%f531, %f527, %f530, %f529;
	mul.f32 	%f532, %f531, 0f3FB8AA3B;
	add.f32 	%f533, %f527, 0f4B40007F;
	mov.b32 	%r270, %f533;
	shl.b32 	%r271, %r270, 23;
	mov.b32 	%f534, %r271;
	ex2.approx.ftz.f32 	%f535, %f532;
	mul.f32 	%f116, %f535, %f534;
	setp.eq.f32 	%p95, %f116, 0f7F800000;
	mov.f32 	%f694, 0f7F800000;
	@%p95 bra 	$L__BB0_74;

	fma.rn.f32 	%f694, %f116, %f115, %f116;

$L__BB0_74:
	setp.lt.f32 	%p96, %f692, 0f00000000;
	setp.eq.f32 	%p97, %f113, 0f3F800000;
	and.pred  	%p3, %p96, %p97;
	setp.eq.f32 	%p98, %f692, 0f00000000;
	@%p98 bra 	$L__BB0_78;
	bra.uni 	$L__BB0_75;

$L__BB0_78:
	add.f32 	%f540, %f692, %f692;
	selp.f32 	%f696, %f540, 0f00000000, %p97;
	bra.uni 	$L__BB0_79;

$L__BB0_75:
	mov.b32 	%r272, %f694;
	xor.b32  	%r273, %r272, -2147483648;
	mov.b32 	%f536, %r273;
	selp.f32 	%f696, %f536, %f694, %p3;
	setp.geu.f32 	%p99, %f692, 0f00000000;
	@%p99 bra 	$L__BB0_79;

	mov.f32 	%f537, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f538, %f537;
	setp.eq.f32 	%p100, %f538, 0f3EE8BA2E;
	@%p100 bra 	$L__BB0_79;

	mov.f32 	%f696, 0f7FFFFFFF;

$L__BB0_79:
	abs.f32 	%f659, %f692;
	add.f32 	%f541, %f659, 0f3EE8BA2E;
	mov.b32 	%r274, %f541;
	setp.lt.s32 	%p102, %r274, 2139095040;
	@%p102 bra 	$L__BB0_84;

	abs.f32 	%f660, %f692;
	setp.gtu.f32 	%p103, %f660, 0f7F800000;
	@%p103 bra 	$L__BB0_83;
	bra.uni 	$L__BB0_81;

$L__BB0_83:
	add.f32 	%f696, %f692, 0f3EE8BA2E;
	bra.uni 	$L__BB0_84;

$L__BB0_81:
	abs.f32 	%f661, %f692;
	setp.neu.f32 	%p104, %f661, 0f7F800000;
	@%p104 bra 	$L__BB0_84;

	selp.f32 	%f696, 0fFF800000, 0f7F800000, %p3;

$L__BB0_84:
	mul.f32 	%f542, %f696, 0f437F0000;
	setp.eq.f32 	%p105, %f692, 0f3F800000;
	selp.f32 	%f543, 0f437F0000, %f542, %p105;
	cvt.rzi.u32.f32 	%r275, %f543;
	shl.b64 	%rd68, %rd18, 1;
	add.s64 	%rd69, %rd17, %rd68;
	cvt.u16.u32 	%rs30, %r275;
	mov.u16 	%rs31, 255;
	st.global.v2.u8 	[%rd69], {%rs30, %rs31};

$L__BB0_85:
	mul.f32 	%f125, %f693, 0f3F000000;
	ld.const.u32 	%r49, [params+108];
	setp.eq.s32 	%p106, %r49, 0;
	ld.const.u64 	%rd70, [params+256];
	cvta.to.global.u64 	%rd71, %rd70;
	ld.const.u32 	%r276, [params+248];
	mad.lo.s32 	%r277, %r276, %r4, %r3;
	mul.wide.u32 	%rd72, %r277, 8;
	add.s64 	%rd19, %rd71, %rd72;
	@%p106 bra 	$L__BB0_87;

	ld.global.v4.u16 	{%rs39, %rs40, %rs41, %rs42}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f544, %rs39;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f545, %rs40;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f546, %rs41;}

	// end inline asm
	add.f32 	%f547, %f125, %f544;
	add.f32 	%f548, %f125, %f545;
	add.f32 	%f549, %f125, %f546;
	mov.f32 	%f550, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f549;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f548;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f547;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f550;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs35, %rs36, %rs37, %rs38};
	bra.uni 	$L__BB0_88;

$L__BB0_87:
	mov.f32 	%f554, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f554;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f125;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f125;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f125;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs43, %rs44, %rs45, %rs46};

$L__BB0_88:
	mov.f32 	%f555, 0f34000000;
	max.f32 	%f556, %f125, %f555;
	mul.f32 	%f557, %f73, 0f3F000000;
	div.rn.f32 	%f558, %f557, %f556;
	fma.rn.f32 	%f126, %f558, 0f3F000000, 0f3F000000;
	mul.f32 	%f559, %f74, 0f3F000000;
	div.rn.f32 	%f560, %f559, %f556;
	fma.rn.f32 	%f127, %f560, 0f3F000000, 0f3F000000;
	mul.f32 	%f561, %f75, 0f3F000000;
	div.rn.f32 	%f562, %f561, %f556;
	fma.rn.f32 	%f128, %f562, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd73, [params+272];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r278, [params+264];
	mad.lo.s32 	%r279, %r278, %r4, %r3;
	mul.wide.u32 	%rd75, %r279, 8;
	add.s64 	%rd20, %rd74, %rd75;
	@%p106 bra 	$L__BB0_90;

	ld.global.v4.u16 	{%rs54, %rs55, %rs56, %rs57}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f563, %rs54;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f564, %rs55;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f565, %rs56;}

	// end inline asm
	add.f32 	%f566, %f126, %f563;
	add.f32 	%f567, %f126, %f564;
	add.f32 	%f568, %f126, %f565;
	mov.f32 	%f569, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f568;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f567;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f566;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f569;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs50, %rs51, %rs52, %rs53};
	bra.uni 	$L__BB0_91;

$L__BB0_90:
	mov.f32 	%f573, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f573;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f126;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f126;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f126;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs58, %rs59, %rs60, %rs61};

$L__BB0_91:
	ld.const.u64 	%rd76, [params+288];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r280, [params+280];
	mad.lo.s32 	%r281, %r280, %r4, %r3;
	mul.wide.u32 	%rd78, %r281, 8;
	add.s64 	%rd21, %rd77, %rd78;
	@%p106 bra 	$L__BB0_93;

	ld.global.v4.u16 	{%rs69, %rs70, %rs71, %rs72}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f574, %rs69;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f575, %rs70;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f576, %rs71;}

	// end inline asm
	add.f32 	%f577, %f127, %f574;
	add.f32 	%f578, %f127, %f575;
	add.f32 	%f579, %f127, %f576;
	mov.f32 	%f580, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f579;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f578;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f577;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f580;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs65, %rs66, %rs67, %rs68};
	bra.uni 	$L__BB0_94;

$L__BB0_93:
	mov.f32 	%f584, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f584;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f127;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f127;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f127;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs73, %rs74, %rs75, %rs76};

$L__BB0_94:
	ld.const.u64 	%rd79, [params+304];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r282, [params+296];
	mad.lo.s32 	%r283, %r282, %r4, %r3;
	mul.wide.u32 	%rd81, %r283, 8;
	add.s64 	%rd22, %rd80, %rd81;
	@%p106 bra 	$L__BB0_96;

	ld.global.v4.u16 	{%rs84, %rs85, %rs86, %rs87}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f585, %rs84;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f586, %rs85;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f587, %rs86;}

	// end inline asm
	add.f32 	%f588, %f128, %f585;
	add.f32 	%f589, %f128, %f586;
	add.f32 	%f590, %f128, %f587;
	mov.f32 	%f591, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f590;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f589;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f588;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f591;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs80, %rs81, %rs82, %rs83};
	bra.uni 	$L__BB0_115;

$L__BB0_96:
	mov.f32 	%f595, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f595;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f128;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs88, %rs89, %rs90, %rs91};

$L__BB0_115:
	ret;

}