//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<165>;
	.reg .b16 	%rs<322>;
	.reg .f32 	%f<1264>;
	.reg .b32 	%r<382>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<149>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r56), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r57), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	shl.b32 	%r4, %r3, 1;
	ld.const.u64 	%rd39, [params+400];
	cvta.to.global.u64 	%rd40, %rd39;
	ld.const.u32 	%r62, [params+392];
	mad.lo.s32 	%r63, %r62, %r57, %r56;
	mul.wide.u32 	%rd41, %r63, 4;
	add.s64 	%rd2, %rd40, %rd41;
	ld.global.v2.u8 	{%rs7, %rs321}, [%rd2];
	or.b16  	%rs9, %rs7, %rs321;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p7, %rs10, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs320, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs320, [%rd2+2];
	setp.eq.s16 	%p8, %rs320, 0;
	mov.f32 	%f1197, 0f00000000;
	mov.u16 	%rs321, 0;
	mov.f32 	%f1198, %f1197;
	mov.f32 	%f1199, %f1197;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f224, %rs7;
	div.rn.f32 	%f225, %f224, 0f437F0000;
	fma.rn.f32 	%f226, %f225, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs321, 255;
	cvt.rn.f32.u16 	%f227, %rs13;
	div.rn.f32 	%f228, %f227, 0f437F0000;
	fma.rn.f32 	%f229, %f228, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f230, %rs320;
	div.rn.f32 	%f231, %f230, 0f437F0000;
	fma.rn.f32 	%f232, %f231, 0f40000000, 0fBF800000;
	mul.f32 	%f233, %f229, %f229;
	fma.rn.f32 	%f234, %f226, %f226, %f233;
	fma.rn.f32 	%f235, %f232, %f232, %f234;
	sqrt.rn.f32 	%f236, %f235;
	rcp.rn.f32 	%f237, %f236;
	mul.f32 	%f1199, %f237, %f232;
	mul.f32 	%f1198, %f237, %f229;
	mul.f32 	%f1197, %f226, %f237;

$L__BB0_4:
	ld.const.v2.u32 	{%r64, %r65}, [params];
	add.s32 	%r5, %r64, %r56;
	add.s32 	%r6, %r65, %r57;
	setp.eq.f32 	%p9, %f1197, 0f00000000;
	setp.eq.f32 	%p10, %f1198, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1199, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_141;
	bra.uni 	$L__BB0_5;

$L__BB0_141:
	ld.const.u32 	%r53, [params+104];
	and.b32  	%r325, %r53, 1;
	setp.eq.b32 	%p149, %r325, 1;
	mov.pred 	%p150, 0;
	xor.pred  	%p151, %p149, %p150;
	not.pred 	%p152, %p151;
	@%p152 bra 	$L__BB0_143;

	ld.const.u64 	%rd107, [params+144];
	cvta.to.global.u64 	%rd108, %rd107;
	ld.const.u32 	%r326, [params+136];
	mad.lo.s32 	%r327, %r326, %r6, %r5;
	mul.wide.u32 	%rd109, %r327, 4;
	add.s64 	%rd110, %rd108, %rd109;
	mov.u16 	%rs169, 0;
	st.global.v4.u8 	[%rd110], {%rs169, %rs169, %rs169, %rs169};

$L__BB0_143:
	and.b32  	%r328, %r53, 4;
	setp.eq.s32 	%p153, %r328, 0;
	ld.const.u32 	%r381, [params+108];
	@%p153 bra 	$L__BB0_147;

	setp.eq.s32 	%p154, %r381, 0;
	ld.const.u64 	%rd111, [params+224];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r329, [params+216];
	mad.lo.s32 	%r330, %r329, %r6, %r5;
	mul.wide.u32 	%rd113, %r330, 8;
	add.s64 	%rd28, %rd112, %rd113;
	@%p154 bra 	$L__BB0_146;

	ld.global.v4.u16 	{%rs176, %rs177, %rs178, %rs179}, [%rd28];
	// begin inline asm
	{  cvt.f32.f16 %f1048, %rs176;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1049, %rs177;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1050, %rs178;}

	// end inline asm
	add.f32 	%f1051, %f1048, 0f00000000;
	add.f32 	%f1052, %f1049, 0f00000000;
	add.f32 	%f1053, %f1050, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1053;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1052;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1051;}

	// end inline asm
	mov.u16 	%rs180, 0;
	st.global.v4.u16 	[%rd28], {%rs173, %rs174, %rs175, %rs180};
	bra.uni 	$L__BB0_147;

$L__BB0_5:
	ld.const.u64 	%rd42, [params+432];
	cvta.to.global.u64 	%rd43, %rd42;
	ld.const.u32 	%r68, [params+424];
	mad.lo.s32 	%r69, %r68, %r57, %r56;
	mul.wide.u32 	%rd44, %r69, 12;
	add.s64 	%rd45, %rd43, %rd44;
	ld.global.f32 	%f248, [%rd45];
	mul.f32 	%f249, %f248, 0f3456BF95;
	ld.global.f32 	%f250, [%rd45+4];
	mul.f32 	%f251, %f250, 0f3456BF95;
	ld.global.f32 	%f252, [%rd45+8];
	mul.f32 	%f253, %f252, 0f3456BF95;
	abs.f32 	%f254, %f1197;
	div.rn.f32 	%f255, %f249, %f254;
	abs.f32 	%f256, %f1198;
	div.rn.f32 	%f257, %f251, %f256;
	abs.f32 	%f258, %f1199;
	div.rn.f32 	%f259, %f253, %f258;
	abs.f32 	%f260, %f255;
	abs.f32 	%f261, %f257;
	abs.f32 	%f262, %f259;
	mov.f32 	%f263, 0f38D1B717;
	max.f32 	%f264, %f260, %f263;
	max.f32 	%f265, %f261, %f263;
	max.f32 	%f266, %f262, %f263;
	fma.rn.f32 	%f10, %f1197, %f264, %f248;
	fma.rn.f32 	%f11, %f1198, %f265, %f250;
	fma.rn.f32 	%f12, %f1199, %f266, %f252;
	setp.gt.f32 	%p14, %f254, %f258;
	neg.f32 	%f267, %f1198;
	selp.f32 	%f268, %f267, 0f00000000, %p14;
	mov.f32 	%f1226, 0f00000000;
	neg.f32 	%f269, %f1199;
	selp.f32 	%f270, %f1197, %f269, %p14;
	selp.f32 	%f271, 0f00000000, %f1198, %p14;
	mul.f32 	%f272, %f270, %f270;
	fma.rn.f32 	%f273, %f268, %f268, %f272;
	fma.rn.f32 	%f274, %f271, %f271, %f273;
	sqrt.rn.f32 	%f275, %f274;
	rcp.rn.f32 	%f276, %f275;
	mul.f32 	%f13, %f268, %f276;
	mul.f32 	%f14, %f270, %f276;
	mul.f32 	%f15, %f271, %f276;
	ld.const.u64 	%rd46, [params+128];
	cvta.to.global.u64 	%rd47, %rd46;
	ld.const.u32 	%r70, [params+120];
	mad.lo.s32 	%r71, %r70, %r57, %r56;
	mul.wide.u32 	%rd48, %r71, 4;
	add.s64 	%rd3, %rd47, %rd48;
	setp.lt.s32 	%p15, %r3, 1;
	mov.f32 	%f1227, %f1226;
	mov.f32 	%f1228, %f1226;
	mov.f32 	%f1229, %f1226;
	mov.f32 	%f1230, %f1226;
	mov.f32 	%f1231, %f1226;
	mov.f32 	%f1232, %f1226;
	mov.f32 	%f1233, %f1226;
	mov.f32 	%f1234, %f1226;
	mov.f32 	%f1235, %f1226;
	@%p15 bra 	$L__BB0_36;

	ld.const.u32 	%r7, [params+588];
	cvt.rn.f32.s32 	%f287, %r4;
	rcp.rn.f32 	%f16, %f287;
	ld.global.u32 	%r372, [%rd3];
	mul.f32 	%f17, %f10, 0f3456BF95;
	mul.f32 	%f18, %f11, 0f3456BF95;
	mul.f32 	%f19, %f12, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f288, %f1197, %f14;
	mul.f32 	%f289, %f1198, %f13;
	sub.f32 	%f20, %f289, %f288;
	mul.f32 	%f290, %f1199, %f13;
	mul.f32 	%f291, %f1197, %f15;
	sub.f32 	%f21, %f291, %f290;
	mul.f32 	%f292, %f1198, %f15;
	mul.f32 	%f293, %f1199, %f14;
	sub.f32 	%f22, %f293, %f292;
	mov.u32 	%r72, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd49, __cudart_i2opi_f;
	abs.f32 	%f358, %f17;
	abs.f32 	%f359, %f18;
	max.f32 	%f360, %f358, %f359;
	abs.f32 	%f361, %f19;
	max.f32 	%f362, %f360, %f361;
	mov.u32 	%r369, %r72;

$L__BB0_7:
	mov.u32 	%r371, %r72;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1168, %r369;
	mad.lo.s32 	%r74, %r372, 1664525, 1013904223;
	and.b32  	%r75, %r74, 16777215;
	cvt.rn.f32.u32 	%f294, %r75;
	fma.rn.f32 	%f295, %f294, 0f33800000, %f1168;
	mul.f32 	%f296, %f16, %f295;
	mad.lo.s32 	%r372, %r74, 1664525, 1013904223;
	and.b32  	%r76, %r372, 16777215;
	cvt.rn.f32.u32 	%f297, %r76;
	cvt.rn.f32.s32 	%f298, %r371;
	fma.rn.f32 	%f299, %f297, 0f33800000, %f298;
	mul.f32 	%f300, %f16, %f299;
	fma.rn.f32 	%f301, %f16, %f295, %f296;
	mov.f32 	%f302, 0f3F800000;
	sub.f32 	%f44, %f302, %f301;
	mul.f32 	%f303, %f44, %f44;
	sub.f32 	%f304, %f302, %f303;
	mov.f32 	%f305, 0f00000000;
	max.f32 	%f306, %f305, %f304;
	sqrt.rn.f32 	%f45, %f306;
	mul.f32 	%f46, %f300, 0f40C90FDB;
	mul.f32 	%f307, %f46, 0f3F22F983;
	cvt.rni.s32.f32 	%r376, %f307;
	cvt.rn.f32.s32 	%f308, %r376;
	mov.f32 	%f309, 0fBFC90FDA;
	fma.rn.f32 	%f310, %f308, %f309, %f46;
	mov.f32 	%f311, 0fB3A22168;
	fma.rn.f32 	%f312, %f308, %f311, %f310;
	mov.f32 	%f313, 0fA7C234C5;
	fma.rn.f32 	%f1223, %f308, %f313, %f312;
	abs.f32 	%f48, %f46;
	setp.ltu.f32 	%p16, %f48, 0f47CE4780;
	mov.f32 	%f1220, %f1223;
	@%p16 bra 	$L__BB0_16;

	setp.eq.f32 	%p17, %f48, 0f7F800000;
	@%p17 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f316, 0f00000000;
	mul.rn.f32 	%f1220, %f46, %f316;
	mov.u32 	%r376, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r15, %f46;
	bfe.u32 	%r78, %r15, 23, 8;
	mov.u64 	%rd146, 0;
	mov.u32 	%r373, 0;
	mov.u64 	%rd144, %rd1;
	mov.u64 	%rd145, %rd49;

$L__BB0_11:
	.pragma "nounroll";
	mov.b32 	%r356, %f46;
	shl.b32 	%r355, %r356, 8;
	or.b32  	%r354, %r355, -2147483648;
	ld.global.nc.u32 	%r80, [%rd145];
	mad.wide.u32 	%rd51, %r80, %r354, %rd146;
	shr.u64 	%rd146, %rd51, 32;
	st.local.u32 	[%rd144], %rd51;
	add.s64 	%rd145, %rd145, 4;
	add.s64 	%rd144, %rd144, 4;
	add.s32 	%r373, %r373, 1;
	setp.ne.s32 	%p18, %r373, 6;
	@%p18 bra 	$L__BB0_11;

	add.s32 	%r361, %r78, -128;
	mov.b32 	%r360, %f46;
	bfe.u32 	%r359, %r360, 23, 8;
	add.s32 	%r358, %r359, -128;
	shr.u32 	%r357, %r358, 5;
	st.local.u32 	[%rd5], %rd146;
	mov.u32 	%r82, 6;
	sub.s32 	%r83, %r82, %r357;
	mul.wide.s32 	%rd52, %r83, 4;
	add.s64 	%rd53, %rd1, %rd52;
	ld.local.u32 	%r374, [%rd53];
	ld.local.u32 	%r375, [%rd53+-4];
	and.b32  	%r24, %r358, 31;
	setp.eq.s32 	%p19, %r24, 0;
	@%p19 bra 	$L__BB0_14;

	mov.b32 	%r368, %f46;
	bfe.u32 	%r367, %r368, 23, 8;
	add.s32 	%r366, %r367, -128;
	shr.u32 	%r365, %r366, 5;
	mov.u32 	%r364, 4;
	sub.s32 	%r363, %r364, %r365;
	mov.u32 	%r84, 32;
	sub.s32 	%r85, %r84, %r24;
	shr.u32 	%r86, %r375, %r85;
	shl.b32 	%r87, %r374, %r24;
	add.s32 	%r374, %r86, %r87;
	mul.wide.s32 	%rd54, %r363, 4;
	add.s64 	%rd55, %rd1, %rd54;
	ld.local.u32 	%r88, [%rd55];
	shr.u32 	%r89, %r88, %r85;
	shl.b32 	%r90, %r375, %r24;
	add.s32 	%r375, %r89, %r90;

$L__BB0_14:
	mov.b32 	%r362, %f46;
	and.b32  	%r91, %r362, -2147483648;
	shr.u32 	%r92, %r375, 30;
	shl.b32 	%r93, %r374, 2;
	or.b32  	%r94, %r92, %r93;
	shr.u32 	%r95, %r94, 31;
	shr.u32 	%r96, %r374, 30;
	add.s32 	%r97, %r95, %r96;
	neg.s32 	%r98, %r97;
	setp.eq.s32 	%p20, %r91, 0;
	selp.b32 	%r376, %r97, %r98, %p20;
	setp.ne.s32 	%p21, %r95, 0;
	xor.b32  	%r99, %r91, -2147483648;
	selp.b32 	%r100, %r99, %r91, %p21;
	selp.b32 	%r101, -1, 0, %p21;
	xor.b32  	%r102, %r94, %r101;
	shl.b32 	%r103, %r375, 2;
	xor.b32  	%r104, %r103, %r101;
	cvt.u64.u32 	%rd56, %r102;
	cvt.u64.u32 	%rd57, %r104;
	bfi.b64 	%rd58, %rd56, %rd57, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd58;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f314, %fd2;
	setp.eq.s32 	%p22, %r100, 0;
	neg.f32 	%f315, %f314;
	selp.f32 	%f1220, %f314, %f315, %p22;

$L__BB0_16:
	add.s32 	%r31, %r376, 1;
	and.b32  	%r32, %r31, 1;
	setp.eq.s32 	%p23, %r32, 0;
	selp.f32 	%f52, %f1220, 0f3F800000, %p23;
	mul.rn.f32 	%f53, %f1220, %f1220;
	mov.f32 	%f1221, 0fB94D4153;
	@%p23 bra 	$L__BB0_18;

	mov.f32 	%f318, 0fBAB607ED;
	mov.f32 	%f319, 0f37CBAC00;
	fma.rn.f32 	%f1221, %f319, %f53, %f318;

$L__BB0_18:
	selp.f32 	%f320, 0f3C0885E4, 0f3D2AAABB, %p23;
	fma.rn.f32 	%f321, %f1221, %f53, %f320;
	selp.f32 	%f322, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
	fma.rn.f32 	%f323, %f321, %f53, %f322;
	mov.f32 	%f324, 0f00000000;
	fma.rn.f32 	%f325, %f53, %f52, %f324;
	fma.rn.f32 	%f1222, %f323, %f325, %f52;
	and.b32  	%r106, %r31, 2;
	setp.eq.s32 	%p25, %r106, 0;
	@%p25 bra 	$L__BB0_20;

	mov.f32 	%f327, 0fBF800000;
	fma.rn.f32 	%f1222, %f1222, %f327, %f324;

$L__BB0_20:
	mul.f32 	%f1167, %f46, 0f3F22F983;
	cvt.rni.s32.f32 	%r379, %f1167;
	setp.ltu.f32 	%p164, %f48, 0f47CE4780;
	@%p164 bra 	$L__BB0_28;

	setp.eq.f32 	%p27, %f48, 0f7F800000;
	@%p27 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f330, 0f00000000;
	mul.rn.f32 	%f1223, %f46, %f330;
	mov.u32 	%r379, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r33, %f46;
	bfe.u32 	%r107, %r33, 23, 8;
	add.s32 	%r34, %r107, -128;
	shl.b32 	%r108, %r33, 8;
	or.b32  	%r35, %r108, -2147483648;
	shr.u32 	%r36, %r34, 5;
	mov.u64 	%rd147, 0;
	mov.u64 	%rd148, %rd147;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd61, %rd147, 2;
	mov.u64 	%rd62, __cudart_i2opi_f;
	add.s64 	%rd63, %rd62, %rd61;
	ld.global.nc.u32 	%r109, [%rd63];
	mad.wide.u32 	%rd64, %r109, %r35, %rd148;
	shr.u64 	%rd148, %rd64, 32;
	add.s64 	%rd65, %rd1, %rd61;
	st.local.u32 	[%rd65], %rd64;
	cvt.u32.u64 	%r110, %rd147;
	add.s32 	%r111, %r110, 1;
	cvt.s64.s32 	%rd147, %r111;
	setp.ne.s32 	%p28, %r111, 6;
	@%p28 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd148;
	mov.u32 	%r112, 4;
	sub.s32 	%r37, %r112, %r36;
	mov.u32 	%r113, 6;
	sub.s32 	%r114, %r113, %r36;
	mul.wide.s32 	%rd66, %r114, 4;
	add.s64 	%rd67, %rd1, %rd66;
	ld.local.u32 	%r377, [%rd67];
	ld.local.u32 	%r378, [%rd67+-4];
	and.b32  	%r40, %r34, 31;
	setp.eq.s32 	%p29, %r40, 0;
	@%p29 bra 	$L__BB0_26;

	mov.u32 	%r115, 32;
	sub.s32 	%r116, %r115, %r40;
	shr.u32 	%r117, %r378, %r116;
	shl.b32 	%r118, %r377, %r40;
	add.s32 	%r377, %r117, %r118;
	mul.wide.s32 	%rd68, %r37, 4;
	add.s64 	%rd69, %rd1, %rd68;
	ld.local.u32 	%r119, [%rd69];
	shr.u32 	%r120, %r119, %r116;
	shl.b32 	%r121, %r378, %r40;
	add.s32 	%r378, %r120, %r121;

$L__BB0_26:
	and.b32  	%r122, %r33, -2147483648;
	shr.u32 	%r123, %r378, 30;
	shl.b32 	%r124, %r377, 2;
	or.b32  	%r125, %r123, %r124;
	shr.u32 	%r126, %r125, 31;
	shr.u32 	%r127, %r377, 30;
	add.s32 	%r128, %r126, %r127;
	neg.s32 	%r129, %r128;
	setp.eq.s32 	%p30, %r122, 0;
	selp.b32 	%r379, %r128, %r129, %p30;
	setp.ne.s32 	%p31, %r126, 0;
	xor.b32  	%r130, %r122, -2147483648;
	selp.b32 	%r131, %r130, %r122, %p31;
	selp.b32 	%r132, -1, 0, %p31;
	xor.b32  	%r133, %r125, %r132;
	shl.b32 	%r134, %r378, 2;
	xor.b32  	%r135, %r134, %r132;
	cvt.u64.u32 	%rd70, %r133;
	cvt.u64.u32 	%rd71, %r135;
	bfi.b64 	%rd72, %rd70, %rd71, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd72;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f328, %fd4;
	setp.eq.s32 	%p32, %r131, 0;
	neg.f32 	%f329, %f328;
	selp.f32 	%f1223, %f328, %f329, %p32;

$L__BB0_28:
	mul.f32 	%f62, %f45, %f1222;
	and.b32  	%r47, %r379, 1;
	setp.eq.s32 	%p33, %r47, 0;
	selp.f32 	%f63, %f1223, 0f3F800000, %p33;
	mul.rn.f32 	%f64, %f1223, %f1223;
	mov.f32 	%f1224, 0fB94D4153;
	@%p33 bra 	$L__BB0_30;

	mov.f32 	%f332, 0fBAB607ED;
	mov.f32 	%f333, 0f37CBAC00;
	fma.rn.f32 	%f1224, %f333, %f64, %f332;

$L__BB0_30:
	selp.f32 	%f334, 0f3C0885E4, 0f3D2AAABB, %p33;
	fma.rn.f32 	%f335, %f1224, %f64, %f334;
	selp.f32 	%f336, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
	fma.rn.f32 	%f337, %f335, %f64, %f336;
	mov.f32 	%f338, 0f00000000;
	fma.rn.f32 	%f339, %f64, %f63, %f338;
	fma.rn.f32 	%f1225, %f337, %f339, %f63;
	and.b32  	%r137, %r379, 2;
	setp.eq.s32 	%p35, %r137, 0;
	@%p35 bra 	$L__BB0_32;

	mov.f32 	%f341, 0fBF800000;
	fma.rn.f32 	%f1225, %f1225, %f341, %f338;

$L__BB0_32:
	mul.f32 	%f342, %f45, %f1225;
	mul.f32 	%f343, %f13, %f342;
	mul.f32 	%f344, %f14, %f342;
	mul.f32 	%f345, %f15, %f342;
	fma.rn.f32 	%f346, %f22, %f62, %f343;
	fma.rn.f32 	%f347, %f21, %f62, %f344;
	fma.rn.f32 	%f348, %f20, %f62, %f345;
	fma.rn.f32 	%f70, %f1197, %f44, %f346;
	fma.rn.f32 	%f71, %f1198, %f44, %f347;
	fma.rn.f32 	%f72, %f1199, %f44, %f348;
	setp.leu.f32 	%p36, %f71, 0f00000000;
	setp.ne.s32 	%p37, %r7, 0;
	and.pred  	%p38, %p37, %p36;
	@%p38 bra 	$L__BB0_34;

	mov.f32 	%f363, 0f38D1B717;
	max.f32 	%f355, %f362, %f363;
	mov.f32 	%f356, 0f6C4ECB8F;
	mov.f32 	%f357, 0f00000000;
	mov.u32 	%r174, 2;
	mov.u32 	%r176, 1;
	mov.u32 	%r177, 1065353216;
	mov.u32 	%r208, 0;
	// begin inline asm
	call(%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169),_optix_trace_typed_32,(%r208,%rd4,%f10,%f11,%f12,%f70,%f71,%f72,%f355,%f356,%f357,%r176,%r208,%r176,%r174,%r176,%r176,%r177,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208);
	// end inline asm
	mov.b32 	%f364, %r138;
	mul.f32 	%f365, %f1198, %f71;
	fma.rn.f32 	%f366, %f1197, %f70, %f365;
	fma.rn.f32 	%f367, %f1199, %f72, %f366;
	add.f32 	%f1230, %f1230, %f364;
	fma.rn.f32 	%f1229, %f71, %f364, %f1229;
	fma.rn.f32 	%f1228, %f72, %f364, %f1228;
	fma.rn.f32 	%f1227, %f70, %f364, %f1227;
	mul.f32 	%f368, %f70, %f71;
	fma.rn.f32 	%f1226, %f368, %f364, %f1226;
	mul.f32 	%f369, %f71, %f72;
	fma.rn.f32 	%f1231, %f369, %f364, %f1231;
	fma.rn.f32 	%f370, %f72, %f72, 0fBEAAAAAB;
	fma.rn.f32 	%f1233, %f370, %f364, %f1233;
	mul.f32 	%f371, %f70, %f72;
	fma.rn.f32 	%f1234, %f371, %f364, %f1234;
	mul.f32 	%f372, %f71, %f71;
	mul.f32 	%f373, %f70, %f70;
	sub.f32 	%f374, %f373, %f372;
	fma.rn.f32 	%f1235, %f374, %f364, %f1235;
	cvt.sat.f32.f32 	%f375, %f367;
	fma.rn.f32 	%f1232, %f375, %f364, %f1232;

$L__BB0_34:
	add.s32 	%r371, %r371, 1;
	setp.lt.s32 	%p39, %r371, %r4;
	@%p39 bra 	$L__BB0_8;

	add.s32 	%r369, %r369, 1;
	setp.lt.s32 	%p40, %r369, %r4;
	@%p40 bra 	$L__BB0_7;

$L__BB0_36:
	mul.lo.s32 	%r209, %r4, %r4;
	cvt.rn.f32.s32 	%f376, %r209;
	div.rn.f32 	%f377, %f1232, %f376;
	div.rn.f32 	%f103, %f1230, %f376;
	div.rn.f32 	%f104, %f1229, %f376;
	div.rn.f32 	%f105, %f1228, %f376;
	div.rn.f32 	%f106, %f1227, %f376;
	div.rn.f32 	%f107, %f1226, %f376;
	div.rn.f32 	%f108, %f1231, %f376;
	div.rn.f32 	%f109, %f1233, %f376;
	div.rn.f32 	%f110, %f1234, %f376;
	div.rn.f32 	%f111, %f1235, %f376;
	add.f32 	%f378, %f377, %f377;
	ld.const.v4.f32 	{%f379, %f380, %f381, %f382}, [params+576];
	mul.f32 	%f115, %f378, %f379;
	mul.f32 	%f116, %f378, %f380;
	mul.f32 	%f117, %f378, %f381;
	ld.const.u32 	%r50, [params+104];
	and.b32  	%r210, %r50, 1;
	setp.eq.b32 	%p41, %r210, 1;
	mov.pred 	%p42, 0;
	xor.pred  	%p43, %p41, %p42;
	not.pred 	%p44, %p43;
	@%p44 bra 	$L__BB0_110;

	mov.f32 	%f387, 0f3EE66666;
	abs.f32 	%f119, %f115;
	setp.lt.f32 	%p45, %f119, 0f00800000;
	mul.f32 	%f389, %f119, 0f4B800000;
	selp.f32 	%f390, %f389, %f119, %p45;
	selp.f32 	%f391, 0fC3170000, 0fC2FE0000, %p45;
	mov.b32 	%r211, %f390;
	and.b32  	%r212, %r211, 8388607;
	or.b32  	%r213, %r212, 1065353216;
	mov.b32 	%f392, %r213;
	shr.u32 	%r214, %r211, 23;
	cvt.rn.f32.u32 	%f393, %r214;
	add.f32 	%f394, %f391, %f393;
	setp.gt.f32 	%p46, %f392, 0f3FB504F3;
	mul.f32 	%f395, %f392, 0f3F000000;
	add.f32 	%f396, %f394, 0f3F800000;
	selp.f32 	%f397, %f396, %f394, %p46;
	selp.f32 	%f398, %f395, %f392, %p46;
	add.f32 	%f399, %f398, 0fBF800000;
	add.f32 	%f400, %f398, 0f3F800000;
	rcp.approx.ftz.f32 	%f401, %f400;
	add.f32 	%f402, %f399, %f399;
	mul.f32 	%f403, %f402, %f401;
	mul.f32 	%f404, %f403, %f403;
	mov.f32 	%f405, 0f3C4CAF63;
	mov.f32 	%f406, 0f3B18F0FE;
	fma.rn.f32 	%f407, %f406, %f404, %f405;
	mov.f32 	%f408, 0f3DAAAABD;
	fma.rn.f32 	%f409, %f407, %f404, %f408;
	mul.rn.f32 	%f410, %f409, %f404;
	mul.rn.f32 	%f411, %f410, %f403;
	sub.f32 	%f412, %f399, %f403;
	add.f32 	%f413, %f412, %f412;
	neg.f32 	%f414, %f403;
	fma.rn.f32 	%f415, %f414, %f399, %f413;
	mul.rn.f32 	%f416, %f401, %f415;
	add.f32 	%f417, %f411, %f403;
	sub.f32 	%f418, %f403, %f417;
	add.f32 	%f419, %f411, %f418;
	add.f32 	%f420, %f416, %f419;
	add.f32 	%f421, %f417, %f420;
	sub.f32 	%f422, %f417, %f421;
	add.f32 	%f423, %f420, %f422;
	mov.f32 	%f424, 0f3F317200;
	mul.rn.f32 	%f425, %f397, %f424;
	mov.f32 	%f426, 0f35BFBE8E;
	mul.rn.f32 	%f427, %f397, %f426;
	add.f32 	%f428, %f425, %f421;
	sub.f32 	%f429, %f425, %f428;
	add.f32 	%f430, %f421, %f429;
	add.f32 	%f431, %f423, %f430;
	add.f32 	%f432, %f427, %f431;
	add.f32 	%f433, %f428, %f432;
	sub.f32 	%f434, %f428, %f433;
	add.f32 	%f435, %f432, %f434;
	mul.rn.f32 	%f436, %f387, %f433;
	neg.f32 	%f437, %f436;
	fma.rn.f32 	%f438, %f387, %f433, %f437;
	fma.rn.f32 	%f439, %f387, %f435, %f438;
	mov.f32 	%f440, 0f00000000;
	fma.rn.f32 	%f441, %f440, %f433, %f439;
	add.rn.f32 	%f442, %f436, %f441;
	neg.f32 	%f443, %f442;
	add.rn.f32 	%f444, %f436, %f443;
	add.rn.f32 	%f445, %f444, %f441;
	mov.b32 	%r215, %f442;
	setp.eq.s32 	%p47, %r215, 1118925336;
	add.s32 	%r216, %r215, -1;
	mov.b32 	%f446, %r216;
	add.f32 	%f447, %f445, 0f37000000;
	selp.f32 	%f120, %f447, %f445, %p47;
	selp.f32 	%f448, %f446, %f442, %p47;
	mov.f32 	%f449, 0f3FB8AA3B;
	mul.rn.f32 	%f450, %f448, %f449;
	cvt.rzi.f32.f32 	%f451, %f450;
	abs.f32 	%f452, %f451;
	setp.gt.f32 	%p48, %f452, 0f42FC0000;
	mov.b32 	%r217, %f451;
	and.b32  	%r218, %r217, -2147483648;
	or.b32  	%r219, %r218, 1123811328;
	mov.b32 	%f453, %r219;
	selp.f32 	%f454, %f453, %f451, %p48;
	mov.f32 	%f455, 0fBF317218;
	fma.rn.f32 	%f456, %f454, %f455, %f448;
	mov.f32 	%f457, 0f3102E308;
	fma.rn.f32 	%f458, %f454, %f457, %f456;
	mul.f32 	%f459, %f458, 0f3FB8AA3B;
	add.f32 	%f460, %f454, 0f4B40007F;
	mov.b32 	%r220, %f460;
	shl.b32 	%r221, %r220, 23;
	mov.b32 	%f461, %r221;
	ex2.approx.ftz.f32 	%f462, %f459;
	mul.f32 	%f121, %f462, %f461;
	setp.eq.f32 	%p49, %f121, 0f7F800000;
	mov.f32 	%f1246, 0f7F800000;
	@%p49 bra 	$L__BB0_39;

	fma.rn.f32 	%f1246, %f121, %f120, %f121;

$L__BB0_39:
	mov.f32 	%f1174, 0f3E666666;
	cvt.rzi.f32.f32 	%f1173, %f1174;
	add.f32 	%f1172, %f1173, %f1173;
	mov.f32 	%f1171, 0f3EE66666;
	sub.f32 	%f1170, %f1171, %f1172;
	abs.f32 	%f1169, %f1170;
	setp.lt.f32 	%p50, %f115, 0f00000000;
	setp.eq.f32 	%p51, %f1169, 0f3F800000;
	and.pred  	%p1, %p50, %p51;
	setp.eq.f32 	%p52, %f115, 0f00000000;
	@%p52 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f467, %f115, %f115;
	selp.f32 	%f1248, %f467, 0f00000000, %p51;
	bra.uni 	$L__BB0_44;

$L__BB0_146:
	mov.f32 	%f1056, 0f00000000;
	mov.u32 	%r381, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs183, %f1056;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs182, %f1056;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs181, %f1056;}

	// end inline asm
	mov.u16 	%rs184, 0;
	st.global.v4.u16 	[%rd28], {%rs181, %rs182, %rs183, %rs184};

$L__BB0_147:
	ld.const.u64 	%rd114, [params+256];
	cvta.to.global.u64 	%rd115, %rd114;
	ld.const.u32 	%r332, [params+248];
	mad.lo.s32 	%r333, %r332, %r6, %r5;
	mul.wide.u32 	%rd116, %r333, 8;
	add.s64 	%rd29, %rd115, %rd116;
	setp.eq.s32 	%p155, %r381, 0;
	@%p155 bra 	$L__BB0_149;

	ld.global.v4.u16 	{%rs191, %rs192, %rs193, %rs194}, [%rd29];
	// begin inline asm
	{  cvt.f32.f16 %f1057, %rs191;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1058, %rs192;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1059, %rs193;}

	// end inline asm
	add.f32 	%f1060, %f1057, 0f00000000;
	add.f32 	%f1061, %f1058, 0f00000000;
	add.f32 	%f1062, %f1059, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs190, %f1062;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs189, %f1061;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs188, %f1060;}

	// end inline asm
	mov.u16 	%rs195, 0;
	st.global.v4.u16 	[%rd29], {%rs188, %rs189, %rs190, %rs195};
	bra.uni 	$L__BB0_150;

$L__BB0_149:
	mov.f32 	%f1065, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs198, %f1065;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs197, %f1065;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs196, %f1065;}

	// end inline asm
	mov.u16 	%rs199, 0;
	st.global.v4.u16 	[%rd29], {%rs196, %rs197, %rs198, %rs199};

$L__BB0_150:
	ld.const.u64 	%rd117, [params+272];
	cvta.to.global.u64 	%rd118, %rd117;
	ld.const.u32 	%r334, [params+264];
	mad.lo.s32 	%r335, %r334, %r6, %r5;
	mul.wide.u32 	%rd119, %r335, 8;
	add.s64 	%rd30, %rd118, %rd119;
	@%p155 bra 	$L__BB0_152;

	ld.global.v4.u16 	{%rs206, %rs207, %rs208, %rs209}, [%rd30];
	// begin inline asm
	{  cvt.f32.f16 %f1066, %rs206;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1067, %rs207;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1068, %rs208;}

	// end inline asm
	add.f32 	%f1069, %f1066, 0f00000000;
	add.f32 	%f1070, %f1067, 0f00000000;
	add.f32 	%f1071, %f1068, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs205, %f1071;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs204, %f1070;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs203, %f1069;}

	// end inline asm
	mov.u16 	%rs210, 0;
	st.global.v4.u16 	[%rd30], {%rs203, %rs204, %rs205, %rs210};
	bra.uni 	$L__BB0_153;

$L__BB0_152:
	mov.f32 	%f1074, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs213, %f1074;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs212, %f1074;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs211, %f1074;}

	// end inline asm
	mov.u16 	%rs214, 0;
	st.global.v4.u16 	[%rd30], {%rs211, %rs212, %rs213, %rs214};

$L__BB0_153:
	ld.const.u64 	%rd120, [params+288];
	cvta.to.global.u64 	%rd121, %rd120;
	ld.const.u32 	%r336, [params+280];
	mad.lo.s32 	%r337, %r336, %r6, %r5;
	mul.wide.u32 	%rd122, %r337, 8;
	add.s64 	%rd31, %rd121, %rd122;
	@%p155 bra 	$L__BB0_155;

	ld.global.v4.u16 	{%rs221, %rs222, %rs223, %rs224}, [%rd31];
	// begin inline asm
	{  cvt.f32.f16 %f1075, %rs221;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1076, %rs222;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1077, %rs223;}

	// end inline asm
	add.f32 	%f1078, %f1075, 0f00000000;
	add.f32 	%f1079, %f1076, 0f00000000;
	add.f32 	%f1080, %f1077, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs220, %f1080;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs219, %f1079;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs218, %f1078;}

	// end inline asm
	mov.u16 	%rs225, 0;
	st.global.v4.u16 	[%rd31], {%rs218, %rs219, %rs220, %rs225};
	bra.uni 	$L__BB0_156;

$L__BB0_155:
	mov.f32 	%f1083, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs228, %f1083;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs227, %f1083;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs226, %f1083;}

	// end inline asm
	mov.u16 	%rs229, 0;
	st.global.v4.u16 	[%rd31], {%rs226, %rs227, %rs228, %rs229};

$L__BB0_156:
	ld.const.u64 	%rd123, [params+304];
	cvta.to.global.u64 	%rd124, %rd123;
	ld.const.u32 	%r338, [params+296];
	mad.lo.s32 	%r339, %r338, %r6, %r5;
	mul.wide.u32 	%rd125, %r339, 8;
	add.s64 	%rd32, %rd124, %rd125;
	@%p155 bra 	$L__BB0_158;

	ld.global.v4.u16 	{%rs236, %rs237, %rs238, %rs239}, [%rd32];
	// begin inline asm
	{  cvt.f32.f16 %f1084, %rs236;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1085, %rs237;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1086, %rs238;}

	// end inline asm
	add.f32 	%f1087, %f1084, 0f00000000;
	add.f32 	%f1088, %f1085, 0f00000000;
	add.f32 	%f1089, %f1086, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs235, %f1089;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs234, %f1088;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs233, %f1087;}

	// end inline asm
	mov.u16 	%rs240, 0;
	st.global.v4.u16 	[%rd32], {%rs233, %rs234, %rs235, %rs240};
	bra.uni 	$L__BB0_159;

$L__BB0_158:
	mov.f32 	%f1092, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs243, %f1092;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs242, %f1092;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs241, %f1092;}

	// end inline asm
	mov.u16 	%rs244, 0;
	st.global.v4.u16 	[%rd32], {%rs241, %rs242, %rs243, %rs244};

$L__BB0_159:
	ld.const.u64 	%rd126, [params+320];
	cvta.to.global.u64 	%rd127, %rd126;
	ld.const.u32 	%r340, [params+312];
	mad.lo.s32 	%r341, %r340, %r6, %r5;
	mul.wide.u32 	%rd128, %r341, 8;
	add.s64 	%rd33, %rd127, %rd128;
	@%p155 bra 	$L__BB0_161;

	ld.global.v4.u16 	{%rs251, %rs252, %rs253, %rs254}, [%rd33];
	// begin inline asm
	{  cvt.f32.f16 %f1093, %rs251;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1094, %rs252;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1095, %rs253;}

	// end inline asm
	add.f32 	%f1096, %f1093, 0f00000000;
	add.f32 	%f1097, %f1094, 0f00000000;
	add.f32 	%f1098, %f1095, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs250, %f1098;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs249, %f1097;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs248, %f1096;}

	// end inline asm
	mov.u16 	%rs255, 0;
	st.global.v4.u16 	[%rd33], {%rs248, %rs249, %rs250, %rs255};
	bra.uni 	$L__BB0_162;

$L__BB0_161:
	mov.f32 	%f1101, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs258, %f1101;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs257, %f1101;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs256, %f1101;}

	// end inline asm
	mov.u16 	%rs259, 0;
	st.global.v4.u16 	[%rd33], {%rs256, %rs257, %rs258, %rs259};

$L__BB0_162:
	ld.const.u64 	%rd129, [params+336];
	cvta.to.global.u64 	%rd130, %rd129;
	ld.const.u32 	%r342, [params+328];
	mad.lo.s32 	%r343, %r342, %r6, %r5;
	mul.wide.u32 	%rd131, %r343, 8;
	add.s64 	%rd34, %rd130, %rd131;
	@%p155 bra 	$L__BB0_164;

	ld.global.v4.u16 	{%rs266, %rs267, %rs268, %rs269}, [%rd34];
	// begin inline asm
	{  cvt.f32.f16 %f1102, %rs266;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1103, %rs267;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1104, %rs268;}

	// end inline asm
	add.f32 	%f1105, %f1102, 0f00000000;
	add.f32 	%f1106, %f1103, 0f00000000;
	add.f32 	%f1107, %f1104, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs265, %f1107;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs264, %f1106;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs263, %f1105;}

	// end inline asm
	mov.u16 	%rs270, 0;
	st.global.v4.u16 	[%rd34], {%rs263, %rs264, %rs265, %rs270};
	bra.uni 	$L__BB0_165;

$L__BB0_164:
	mov.f32 	%f1110, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs273, %f1110;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs272, %f1110;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs271, %f1110;}

	// end inline asm
	mov.u16 	%rs274, 0;
	st.global.v4.u16 	[%rd34], {%rs271, %rs272, %rs273, %rs274};

$L__BB0_165:
	ld.const.u64 	%rd132, [params+352];
	cvta.to.global.u64 	%rd133, %rd132;
	ld.const.u32 	%r344, [params+344];
	mad.lo.s32 	%r345, %r344, %r6, %r5;
	mul.wide.u32 	%rd134, %r345, 8;
	add.s64 	%rd35, %rd133, %rd134;
	@%p155 bra 	$L__BB0_167;

	ld.global.v4.u16 	{%rs281, %rs282, %rs283, %rs284}, [%rd35];
	// begin inline asm
	{  cvt.f32.f16 %f1111, %rs281;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1112, %rs282;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1113, %rs283;}

	// end inline asm
	add.f32 	%f1114, %f1111, 0f00000000;
	add.f32 	%f1115, %f1112, 0f00000000;
	add.f32 	%f1116, %f1113, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs280, %f1116;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs279, %f1115;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs278, %f1114;}

	// end inline asm
	mov.u16 	%rs285, 0;
	st.global.v4.u16 	[%rd35], {%rs278, %rs279, %rs280, %rs285};
	bra.uni 	$L__BB0_168;

$L__BB0_167:
	mov.f32 	%f1119, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs288, %f1119;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs287, %f1119;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs286, %f1119;}

	// end inline asm
	mov.u16 	%rs289, 0;
	st.global.v4.u16 	[%rd35], {%rs286, %rs287, %rs288, %rs289};

$L__BB0_168:
	ld.const.u64 	%rd135, [params+368];
	cvta.to.global.u64 	%rd136, %rd135;
	ld.const.u32 	%r346, [params+360];
	mad.lo.s32 	%r347, %r346, %r6, %r5;
	mul.wide.u32 	%rd137, %r347, 8;
	add.s64 	%rd36, %rd136, %rd137;
	@%p155 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs296, %rs297, %rs298, %rs299}, [%rd36];
	// begin inline asm
	{  cvt.f32.f16 %f1120, %rs296;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1121, %rs297;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1122, %rs298;}

	// end inline asm
	add.f32 	%f1123, %f1120, 0f00000000;
	add.f32 	%f1124, %f1121, 0f00000000;
	add.f32 	%f1125, %f1122, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs295, %f1125;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs294, %f1124;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs293, %f1123;}

	// end inline asm
	mov.u16 	%rs300, 0;
	st.global.v4.u16 	[%rd36], {%rs293, %rs294, %rs295, %rs300};
	bra.uni 	$L__BB0_171;

$L__BB0_170:
	mov.f32 	%f1128, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs303, %f1128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs302, %f1128;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs301, %f1128;}

	// end inline asm
	mov.u16 	%rs304, 0;
	st.global.v4.u16 	[%rd36], {%rs301, %rs302, %rs303, %rs304};

$L__BB0_171:
	ld.const.u64 	%rd138, [params+384];
	cvta.to.global.u64 	%rd139, %rd138;
	ld.const.u32 	%r348, [params+376];
	mad.lo.s32 	%r349, %r348, %r6, %r5;
	mul.wide.u32 	%rd140, %r349, 8;
	add.s64 	%rd37, %rd139, %rd140;
	@%p155 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs311, %rs312, %rs313, %rs314}, [%rd37];
	// begin inline asm
	{  cvt.f32.f16 %f1129, %rs311;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1130, %rs312;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1131, %rs313;}

	// end inline asm
	add.f32 	%f1132, %f1129, 0f00000000;
	add.f32 	%f1133, %f1130, 0f00000000;
	add.f32 	%f1134, %f1131, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs310, %f1134;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs309, %f1133;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs308, %f1132;}

	// end inline asm
	mov.u16 	%rs315, 0;
	st.global.v4.u16 	[%rd37], {%rs308, %rs309, %rs310, %rs315};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1137, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs318, %f1137;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs317, %f1137;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs316, %f1137;}

	// end inline asm
	mov.u16 	%rs319, 0;
	st.global.v4.u16 	[%rd37], {%rs316, %rs317, %rs318, %rs319};
	bra.uni 	$L__BB0_174;

$L__BB0_40:
	mov.b32 	%r222, %f1246;
	xor.b32  	%r223, %r222, -2147483648;
	mov.b32 	%f463, %r223;
	selp.f32 	%f1248, %f463, %f1246, %p1;
	setp.geu.f32 	%p53, %f115, 0f00000000;
	@%p53 bra 	$L__BB0_44;

	mov.f32 	%f464, 0f3EE66666;
	cvt.rzi.f32.f32 	%f465, %f464;
	setp.eq.f32 	%p54, %f465, 0f3EE66666;
	@%p54 bra 	$L__BB0_44;

	mov.f32 	%f1248, 0f7FFFFFFF;

$L__BB0_44:
	add.f32 	%f468, %f119, 0f3EE66666;
	mov.b32 	%r224, %f468;
	setp.lt.s32 	%p56, %r224, 2139095040;
	@%p56 bra 	$L__BB0_49;

	setp.gtu.f32 	%p57, %f119, 0f7F800000;
	@%p57 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1248, %f115, 0f3EE66666;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	setp.neu.f32 	%p58, %f119, 0f7F800000;
	@%p58 bra 	$L__BB0_49;

	selp.f32 	%f1248, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	setp.eq.f32 	%p59, %f115, 0f3F800000;
	selp.f32 	%f130, 0f3F800000, %f1248, %p59;
	abs.f32 	%f131, %f116;
	setp.lt.f32 	%p60, %f131, 0f00800000;
	mul.f32 	%f470, %f131, 0f4B800000;
	selp.f32 	%f471, %f470, %f131, %p60;
	selp.f32 	%f472, 0fC3170000, 0fC2FE0000, %p60;
	mov.b32 	%r225, %f471;
	and.b32  	%r226, %r225, 8388607;
	or.b32  	%r227, %r226, 1065353216;
	mov.b32 	%f473, %r227;
	shr.u32 	%r228, %r225, 23;
	cvt.rn.f32.u32 	%f474, %r228;
	add.f32 	%f475, %f472, %f474;
	setp.gt.f32 	%p61, %f473, 0f3FB504F3;
	mul.f32 	%f476, %f473, 0f3F000000;
	add.f32 	%f477, %f475, 0f3F800000;
	selp.f32 	%f478, %f477, %f475, %p61;
	selp.f32 	%f479, %f476, %f473, %p61;
	add.f32 	%f480, %f479, 0fBF800000;
	add.f32 	%f481, %f479, 0f3F800000;
	rcp.approx.ftz.f32 	%f482, %f481;
	add.f32 	%f483, %f480, %f480;
	mul.f32 	%f484, %f483, %f482;
	mul.f32 	%f485, %f484, %f484;
	mov.f32 	%f486, 0f3C4CAF63;
	mov.f32 	%f487, 0f3B18F0FE;
	fma.rn.f32 	%f488, %f487, %f485, %f486;
	mov.f32 	%f489, 0f3DAAAABD;
	fma.rn.f32 	%f490, %f488, %f485, %f489;
	mul.rn.f32 	%f491, %f490, %f485;
	mul.rn.f32 	%f492, %f491, %f484;
	sub.f32 	%f493, %f480, %f484;
	add.f32 	%f494, %f493, %f493;
	neg.f32 	%f495, %f484;
	fma.rn.f32 	%f496, %f495, %f480, %f494;
	mul.rn.f32 	%f497, %f482, %f496;
	add.f32 	%f498, %f492, %f484;
	sub.f32 	%f499, %f484, %f498;
	add.f32 	%f500, %f492, %f499;
	add.f32 	%f501, %f497, %f500;
	add.f32 	%f502, %f498, %f501;
	sub.f32 	%f503, %f498, %f502;
	add.f32 	%f504, %f501, %f503;
	mov.f32 	%f505, 0f3F317200;
	mul.rn.f32 	%f506, %f478, %f505;
	mov.f32 	%f507, 0f35BFBE8E;
	mul.rn.f32 	%f508, %f478, %f507;
	add.f32 	%f509, %f506, %f502;
	sub.f32 	%f510, %f506, %f509;
	add.f32 	%f511, %f502, %f510;
	add.f32 	%f512, %f504, %f511;
	add.f32 	%f513, %f508, %f512;
	add.f32 	%f514, %f509, %f513;
	sub.f32 	%f515, %f509, %f514;
	add.f32 	%f516, %f513, %f515;
	mov.f32 	%f517, 0f3EE66666;
	mul.rn.f32 	%f518, %f517, %f514;
	neg.f32 	%f519, %f518;
	fma.rn.f32 	%f520, %f517, %f514, %f519;
	fma.rn.f32 	%f521, %f517, %f516, %f520;
	mov.f32 	%f522, 0f00000000;
	fma.rn.f32 	%f523, %f522, %f514, %f521;
	add.rn.f32 	%f524, %f518, %f523;
	neg.f32 	%f525, %f524;
	add.rn.f32 	%f526, %f518, %f525;
	add.rn.f32 	%f527, %f526, %f523;
	mov.b32 	%r229, %f524;
	setp.eq.s32 	%p62, %r229, 1118925336;
	add.s32 	%r230, %r229, -1;
	mov.b32 	%f528, %r230;
	add.f32 	%f529, %f527, 0f37000000;
	selp.f32 	%f132, %f529, %f527, %p62;
	selp.f32 	%f530, %f528, %f524, %p62;
	mov.f32 	%f531, 0f3FB8AA3B;
	mul.rn.f32 	%f532, %f530, %f531;
	cvt.rzi.f32.f32 	%f533, %f532;
	abs.f32 	%f534, %f533;
	setp.gt.f32 	%p63, %f534, 0f42FC0000;
	mov.b32 	%r231, %f533;
	and.b32  	%r232, %r231, -2147483648;
	or.b32  	%r233, %r232, 1123811328;
	mov.b32 	%f535, %r233;
	selp.f32 	%f536, %f535, %f533, %p63;
	mov.f32 	%f537, 0fBF317218;
	fma.rn.f32 	%f538, %f536, %f537, %f530;
	mov.f32 	%f539, 0f3102E308;
	fma.rn.f32 	%f540, %f536, %f539, %f538;
	mul.f32 	%f541, %f540, 0f3FB8AA3B;
	add.f32 	%f542, %f536, 0f4B40007F;
	mov.b32 	%r234, %f542;
	shl.b32 	%r235, %r234, 23;
	mov.b32 	%f543, %r235;
	ex2.approx.ftz.f32 	%f544, %f541;
	mul.f32 	%f133, %f544, %f543;
	setp.eq.f32 	%p64, %f133, 0f7F800000;
	mov.f32 	%f1249, 0f7F800000;
	@%p64 bra 	$L__BB0_51;

	fma.rn.f32 	%f1249, %f133, %f132, %f133;

$L__BB0_51:
	setp.lt.f32 	%p65, %f116, 0f00000000;
	and.pred  	%p2, %p65, %p51;
	setp.eq.f32 	%p67, %f116, 0f00000000;
	@%p67 bra 	$L__BB0_55;
	bra.uni 	$L__BB0_52;

$L__BB0_55:
	add.f32 	%f549, %f116, %f116;
	selp.f32 	%f1251, %f549, 0f00000000, %p51;
	bra.uni 	$L__BB0_56;

$L__BB0_52:
	mov.b32 	%r236, %f1249;
	xor.b32  	%r237, %r236, -2147483648;
	mov.b32 	%f545, %r237;
	selp.f32 	%f1251, %f545, %f1249, %p2;
	setp.geu.f32 	%p68, %f116, 0f00000000;
	@%p68 bra 	$L__BB0_56;

	mov.f32 	%f546, 0f3EE66666;
	cvt.rzi.f32.f32 	%f547, %f546;
	setp.eq.f32 	%p69, %f547, 0f3EE66666;
	@%p69 bra 	$L__BB0_56;

	mov.f32 	%f1251, 0f7FFFFFFF;

$L__BB0_56:
	add.f32 	%f550, %f131, 0f3EE66666;
	mov.b32 	%r238, %f550;
	setp.lt.s32 	%p71, %r238, 2139095040;
	@%p71 bra 	$L__BB0_61;

	setp.gtu.f32 	%p72, %f131, 0f7F800000;
	@%p72 bra 	$L__BB0_60;
	bra.uni 	$L__BB0_58;

$L__BB0_60:
	add.f32 	%f1251, %f116, 0f3EE66666;
	bra.uni 	$L__BB0_61;

$L__BB0_58:
	setp.neu.f32 	%p73, %f131, 0f7F800000;
	@%p73 bra 	$L__BB0_61;

	selp.f32 	%f1251, 0fFF800000, 0f7F800000, %p2;

$L__BB0_61:
	setp.eq.f32 	%p74, %f116, 0f3F800000;
	selp.f32 	%f142, 0f3F800000, %f1251, %p74;
	abs.f32 	%f143, %f117;
	setp.lt.f32 	%p75, %f143, 0f00800000;
	mul.f32 	%f552, %f143, 0f4B800000;
	selp.f32 	%f553, %f552, %f143, %p75;
	selp.f32 	%f554, 0fC3170000, 0fC2FE0000, %p75;
	mov.b32 	%r239, %f553;
	and.b32  	%r240, %r239, 8388607;
	or.b32  	%r241, %r240, 1065353216;
	mov.b32 	%f555, %r241;
	shr.u32 	%r242, %r239, 23;
	cvt.rn.f32.u32 	%f556, %r242;
	add.f32 	%f557, %f554, %f556;
	setp.gt.f32 	%p76, %f555, 0f3FB504F3;
	mul.f32 	%f558, %f555, 0f3F000000;
	add.f32 	%f559, %f557, 0f3F800000;
	selp.f32 	%f560, %f559, %f557, %p76;
	selp.f32 	%f561, %f558, %f555, %p76;
	add.f32 	%f562, %f561, 0fBF800000;
	add.f32 	%f563, %f561, 0f3F800000;
	rcp.approx.ftz.f32 	%f564, %f563;
	add.f32 	%f565, %f562, %f562;
	mul.f32 	%f566, %f565, %f564;
	mul.f32 	%f567, %f566, %f566;
	mov.f32 	%f568, 0f3C4CAF63;
	mov.f32 	%f569, 0f3B18F0FE;
	fma.rn.f32 	%f570, %f569, %f567, %f568;
	mov.f32 	%f571, 0f3DAAAABD;
	fma.rn.f32 	%f572, %f570, %f567, %f571;
	mul.rn.f32 	%f573, %f572, %f567;
	mul.rn.f32 	%f574, %f573, %f566;
	sub.f32 	%f575, %f562, %f566;
	add.f32 	%f576, %f575, %f575;
	neg.f32 	%f577, %f566;
	fma.rn.f32 	%f578, %f577, %f562, %f576;
	mul.rn.f32 	%f579, %f564, %f578;
	add.f32 	%f580, %f574, %f566;
	sub.f32 	%f581, %f566, %f580;
	add.f32 	%f582, %f574, %f581;
	add.f32 	%f583, %f579, %f582;
	add.f32 	%f584, %f580, %f583;
	sub.f32 	%f585, %f580, %f584;
	add.f32 	%f586, %f583, %f585;
	mov.f32 	%f587, 0f3F317200;
	mul.rn.f32 	%f588, %f560, %f587;
	mov.f32 	%f589, 0f35BFBE8E;
	mul.rn.f32 	%f590, %f560, %f589;
	add.f32 	%f591, %f588, %f584;
	sub.f32 	%f592, %f588, %f591;
	add.f32 	%f593, %f584, %f592;
	add.f32 	%f594, %f586, %f593;
	add.f32 	%f595, %f590, %f594;
	add.f32 	%f596, %f591, %f595;
	sub.f32 	%f597, %f591, %f596;
	add.f32 	%f598, %f595, %f597;
	mov.f32 	%f599, 0f3EE66666;
	mul.rn.f32 	%f600, %f599, %f596;
	neg.f32 	%f601, %f600;
	fma.rn.f32 	%f602, %f599, %f596, %f601;
	fma.rn.f32 	%f603, %f599, %f598, %f602;
	mov.f32 	%f604, 0f00000000;
	fma.rn.f32 	%f605, %f604, %f596, %f603;
	add.rn.f32 	%f606, %f600, %f605;
	neg.f32 	%f607, %f606;
	add.rn.f32 	%f608, %f600, %f607;
	add.rn.f32 	%f609, %f608, %f605;
	mov.b32 	%r243, %f606;
	setp.eq.s32 	%p77, %r243, 1118925336;
	add.s32 	%r244, %r243, -1;
	mov.b32 	%f610, %r244;
	add.f32 	%f611, %f609, 0f37000000;
	selp.f32 	%f144, %f611, %f609, %p77;
	selp.f32 	%f612, %f610, %f606, %p77;
	mov.f32 	%f613, 0f3FB8AA3B;
	mul.rn.f32 	%f614, %f612, %f613;
	cvt.rzi.f32.f32 	%f615, %f614;
	abs.f32 	%f616, %f615;
	setp.gt.f32 	%p78, %f616, 0f42FC0000;
	mov.b32 	%r245, %f615;
	and.b32  	%r246, %r245, -2147483648;
	or.b32  	%r247, %r246, 1123811328;
	mov.b32 	%f617, %r247;
	selp.f32 	%f618, %f617, %f615, %p78;
	mov.f32 	%f619, 0fBF317218;
	fma.rn.f32 	%f620, %f618, %f619, %f612;
	mov.f32 	%f621, 0f3102E308;
	fma.rn.f32 	%f622, %f618, %f621, %f620;
	mul.f32 	%f623, %f622, 0f3FB8AA3B;
	add.f32 	%f624, %f618, 0f4B40007F;
	mov.b32 	%r248, %f624;
	shl.b32 	%r249, %r248, 23;
	mov.b32 	%f625, %r249;
	ex2.approx.ftz.f32 	%f626, %f623;
	mul.f32 	%f145, %f626, %f625;
	setp.eq.f32 	%p79, %f145, 0f7F800000;
	mov.f32 	%f1252, 0f7F800000;
	@%p79 bra 	$L__BB0_63;

	fma.rn.f32 	%f1252, %f145, %f144, %f145;

$L__BB0_63:
	setp.lt.f32 	%p80, %f117, 0f00000000;
	and.pred  	%p3, %p80, %p51;
	setp.eq.f32 	%p82, %f117, 0f00000000;
	@%p82 bra 	$L__BB0_67;
	bra.uni 	$L__BB0_64;

$L__BB0_67:
	add.f32 	%f631, %f117, %f117;
	selp.f32 	%f1254, %f631, 0f00000000, %p51;
	bra.uni 	$L__BB0_68;

$L__BB0_64:
	mov.b32 	%r250, %f1252;
	xor.b32  	%r251, %r250, -2147483648;
	mov.b32 	%f627, %r251;
	selp.f32 	%f1254, %f627, %f1252, %p3;
	setp.geu.f32 	%p83, %f117, 0f00000000;
	@%p83 bra 	$L__BB0_68;

	mov.f32 	%f628, 0f3EE66666;
	cvt.rzi.f32.f32 	%f629, %f628;
	setp.eq.f32 	%p84, %f629, 0f3EE66666;
	@%p84 bra 	$L__BB0_68;

	mov.f32 	%f1254, 0f7FFFFFFF;

$L__BB0_68:
	add.f32 	%f632, %f143, 0f3EE66666;
	mov.b32 	%r252, %f632;
	setp.lt.s32 	%p86, %r252, 2139095040;
	@%p86 bra 	$L__BB0_73;

	setp.gtu.f32 	%p87, %f143, 0f7F800000;
	@%p87 bra 	$L__BB0_72;
	bra.uni 	$L__BB0_70;

$L__BB0_72:
	add.f32 	%f1254, %f117, 0f3EE66666;
	bra.uni 	$L__BB0_73;

$L__BB0_70:
	setp.neu.f32 	%p88, %f143, 0f7F800000;
	@%p88 bra 	$L__BB0_73;

	selp.f32 	%f1254, 0fFF800000, 0f7F800000, %p3;

$L__BB0_73:
	setp.eq.f32 	%p89, %f117, 0f3F800000;
	mov.f32 	%f634, 0f3F800000;
	selp.f32 	%f635, 0f3F800000, %f1254, %p89;
	min.f32 	%f636, %f130, %f634;
	mov.f32 	%f637, 0f00000000;
	max.f32 	%f154, %f637, %f636;
	min.f32 	%f638, %f142, %f634;
	max.f32 	%f155, %f637, %f638;
	min.f32 	%f639, %f635, %f634;
	max.f32 	%f156, %f637, %f639;
	mov.f32 	%f643, 0f3ED55555;
	abs.f32 	%f158, %f154;
	setp.lt.f32 	%p90, %f158, 0f00800000;
	mul.f32 	%f645, %f158, 0f4B800000;
	selp.f32 	%f646, %f645, %f158, %p90;
	selp.f32 	%f647, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r255, %f646;
	and.b32  	%r256, %r255, 8388607;
	or.b32  	%r257, %r256, 1065353216;
	mov.b32 	%f648, %r257;
	shr.u32 	%r258, %r255, 23;
	cvt.rn.f32.u32 	%f649, %r258;
	add.f32 	%f650, %f647, %f649;
	setp.gt.f32 	%p91, %f648, 0f3FB504F3;
	mul.f32 	%f651, %f648, 0f3F000000;
	add.f32 	%f652, %f650, 0f3F800000;
	selp.f32 	%f653, %f652, %f650, %p91;
	selp.f32 	%f654, %f651, %f648, %p91;
	add.f32 	%f655, %f654, 0fBF800000;
	add.f32 	%f656, %f654, 0f3F800000;
	rcp.approx.ftz.f32 	%f657, %f656;
	add.f32 	%f658, %f655, %f655;
	mul.f32 	%f659, %f658, %f657;
	mul.f32 	%f660, %f659, %f659;
	mov.f32 	%f661, 0f3C4CAF63;
	mov.f32 	%f662, 0f3B18F0FE;
	fma.rn.f32 	%f663, %f662, %f660, %f661;
	mov.f32 	%f664, 0f3DAAAABD;
	fma.rn.f32 	%f665, %f663, %f660, %f664;
	mul.rn.f32 	%f666, %f665, %f660;
	mul.rn.f32 	%f667, %f666, %f659;
	sub.f32 	%f668, %f655, %f659;
	add.f32 	%f669, %f668, %f668;
	neg.f32 	%f670, %f659;
	fma.rn.f32 	%f671, %f670, %f655, %f669;
	mul.rn.f32 	%f672, %f657, %f671;
	add.f32 	%f673, %f667, %f659;
	sub.f32 	%f674, %f659, %f673;
	add.f32 	%f675, %f667, %f674;
	add.f32 	%f676, %f672, %f675;
	add.f32 	%f677, %f673, %f676;
	sub.f32 	%f678, %f673, %f677;
	add.f32 	%f679, %f676, %f678;
	mov.f32 	%f680, 0f3F317200;
	mul.rn.f32 	%f681, %f653, %f680;
	mov.f32 	%f682, 0f35BFBE8E;
	mul.rn.f32 	%f683, %f653, %f682;
	add.f32 	%f684, %f681, %f677;
	sub.f32 	%f685, %f681, %f684;
	add.f32 	%f686, %f677, %f685;
	add.f32 	%f687, %f679, %f686;
	add.f32 	%f688, %f683, %f687;
	add.f32 	%f689, %f684, %f688;
	sub.f32 	%f690, %f684, %f689;
	add.f32 	%f691, %f688, %f690;
	mul.rn.f32 	%f692, %f643, %f689;
	neg.f32 	%f693, %f692;
	fma.rn.f32 	%f694, %f643, %f689, %f693;
	fma.rn.f32 	%f695, %f643, %f691, %f694;
	fma.rn.f32 	%f696, %f637, %f689, %f695;
	add.rn.f32 	%f697, %f692, %f696;
	neg.f32 	%f698, %f697;
	add.rn.f32 	%f699, %f692, %f698;
	add.rn.f32 	%f700, %f699, %f696;
	mov.b32 	%r259, %f697;
	setp.eq.s32 	%p92, %r259, 1118925336;
	add.s32 	%r260, %r259, -1;
	mov.b32 	%f701, %r260;
	add.f32 	%f702, %f700, 0f37000000;
	selp.f32 	%f159, %f702, %f700, %p92;
	selp.f32 	%f703, %f701, %f697, %p92;
	mov.f32 	%f704, 0f3FB8AA3B;
	mul.rn.f32 	%f705, %f703, %f704;
	cvt.rzi.f32.f32 	%f706, %f705;
	abs.f32 	%f707, %f706;
	setp.gt.f32 	%p93, %f707, 0f42FC0000;
	mov.b32 	%r261, %f706;
	and.b32  	%r262, %r261, -2147483648;
	or.b32  	%r263, %r262, 1123811328;
	mov.b32 	%f708, %r263;
	selp.f32 	%f709, %f708, %f706, %p93;
	mov.f32 	%f710, 0fBF317218;
	fma.rn.f32 	%f711, %f709, %f710, %f703;
	mov.f32 	%f712, 0f3102E308;
	fma.rn.f32 	%f713, %f709, %f712, %f711;
	mul.f32 	%f714, %f713, 0f3FB8AA3B;
	add.f32 	%f715, %f709, 0f4B40007F;
	mov.b32 	%r264, %f715;
	shl.b32 	%r265, %r264, 23;
	mov.b32 	%f716, %r265;
	ex2.approx.ftz.f32 	%f717, %f714;
	mul.f32 	%f160, %f717, %f716;
	setp.eq.f32 	%p94, %f160, 0f7F800000;
	mov.f32 	%f1255, 0f7F800000;
	@%p94 bra 	$L__BB0_75;

	fma.rn.f32 	%f1255, %f160, %f159, %f160;

$L__BB0_75:
	mov.f32 	%f1145, 0f00000000;
	max.f32 	%f1144, %f1145, %f636;
	mov.f32 	%f1143, 0f3E555555;
	cvt.rzi.f32.f32 	%f1142, %f1143;
	add.f32 	%f1141, %f1142, %f1142;
	mov.f32 	%f1140, 0f3ED55555;
	sub.f32 	%f1139, %f1140, %f1141;
	abs.f32 	%f1138, %f1139;
	setp.lt.f32 	%p95, %f1144, 0f00000000;
	setp.eq.f32 	%p96, %f1138, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f1144, 0f00000000;
	@%p97 bra 	$L__BB0_79;
	bra.uni 	$L__BB0_76;

$L__BB0_79:
	mov.f32 	%f1166, 0f00000000;
	max.f32 	%f1165, %f1166, %f636;
	add.f32 	%f722, %f1165, %f1165;
	selp.f32 	%f1257, %f722, 0f00000000, %p96;
	bra.uni 	$L__BB0_80;

$L__BB0_76:
	mov.f32 	%f1147, 0f00000000;
	max.f32 	%f1146, %f1147, %f636;
	mov.b32 	%r266, %f1255;
	xor.b32  	%r267, %r266, -2147483648;
	mov.b32 	%f718, %r267;
	selp.f32 	%f1257, %f718, %f1255, %p4;
	setp.geu.f32 	%p98, %f1146, 0f00000000;
	@%p98 bra 	$L__BB0_80;

	mov.f32 	%f719, 0f3ED55555;
	cvt.rzi.f32.f32 	%f720, %f719;
	setp.eq.f32 	%p99, %f720, 0f3ED55555;
	@%p99 bra 	$L__BB0_80;

	mov.f32 	%f1257, 0f7FFFFFFF;

$L__BB0_80:
	mov.f32 	%f1150, 0f00000000;
	max.f32 	%f1149, %f1150, %f636;
	abs.f32 	%f1148, %f1149;
	add.f32 	%f723, %f1148, 0f3ED55555;
	mov.b32 	%r268, %f723;
	setp.lt.s32 	%p101, %r268, 2139095040;
	@%p101 bra 	$L__BB0_85;

	mov.f32 	%f1159, 0f00000000;
	max.f32 	%f1158, %f1159, %f636;
	abs.f32 	%f1157, %f1158;
	setp.gtu.f32 	%p102, %f1157, 0f7F800000;
	@%p102 bra 	$L__BB0_84;
	bra.uni 	$L__BB0_82;

$L__BB0_84:
	mov.f32 	%f1164, 0f00000000;
	max.f32 	%f1163, %f1164, %f636;
	add.f32 	%f1257, %f1163, 0f3ED55555;
	bra.uni 	$L__BB0_85;

$L__BB0_82:
	mov.f32 	%f1162, 0f00000000;
	max.f32 	%f1161, %f1162, %f636;
	abs.f32 	%f1160, %f1161;
	setp.neu.f32 	%p103, %f1160, 0f7F800000;
	@%p103 bra 	$L__BB0_85;

	selp.f32 	%f1257, 0fFF800000, 0f7F800000, %p4;

$L__BB0_85:
	abs.f32 	%f169, %f155;
	setp.lt.f32 	%p104, %f169, 0f00800000;
	mul.f32 	%f725, %f169, 0f4B800000;
	selp.f32 	%f726, %f725, %f169, %p104;
	selp.f32 	%f727, 0fC3170000, 0fC2FE0000, %p104;
	mov.b32 	%r269, %f726;
	and.b32  	%r270, %r269, 8388607;
	or.b32  	%r271, %r270, 1065353216;
	mov.b32 	%f728, %r271;
	shr.u32 	%r272, %r269, 23;
	cvt.rn.f32.u32 	%f729, %r272;
	add.f32 	%f730, %f727, %f729;
	setp.gt.f32 	%p105, %f728, 0f3FB504F3;
	mul.f32 	%f731, %f728, 0f3F000000;
	add.f32 	%f732, %f730, 0f3F800000;
	selp.f32 	%f733, %f732, %f730, %p105;
	selp.f32 	%f734, %f731, %f728, %p105;
	add.f32 	%f735, %f734, 0fBF800000;
	add.f32 	%f736, %f734, 0f3F800000;
	rcp.approx.ftz.f32 	%f737, %f736;
	add.f32 	%f738, %f735, %f735;
	mul.f32 	%f739, %f738, %f737;
	mul.f32 	%f740, %f739, %f739;
	mov.f32 	%f741, 0f3C4CAF63;
	mov.f32 	%f742, 0f3B18F0FE;
	fma.rn.f32 	%f743, %f742, %f740, %f741;
	mov.f32 	%f744, 0f3DAAAABD;
	fma.rn.f32 	%f745, %f743, %f740, %f744;
	mul.rn.f32 	%f746, %f745, %f740;
	mul.rn.f32 	%f747, %f746, %f739;
	sub.f32 	%f748, %f735, %f739;
	add.f32 	%f749, %f748, %f748;
	neg.f32 	%f750, %f739;
	fma.rn.f32 	%f751, %f750, %f735, %f749;
	mul.rn.f32 	%f752, %f737, %f751;
	add.f32 	%f753, %f747, %f739;
	sub.f32 	%f754, %f739, %f753;
	add.f32 	%f755, %f747, %f754;
	add.f32 	%f756, %f752, %f755;
	add.f32 	%f757, %f753, %f756;
	sub.f32 	%f758, %f753, %f757;
	add.f32 	%f759, %f756, %f758;
	mov.f32 	%f760, 0f3F317200;
	mul.rn.f32 	%f761, %f733, %f760;
	mov.f32 	%f762, 0f35BFBE8E;
	mul.rn.f32 	%f763, %f733, %f762;
	add.f32 	%f764, %f761, %f757;
	sub.f32 	%f765, %f761, %f764;
	add.f32 	%f766, %f757, %f765;
	add.f32 	%f767, %f759, %f766;
	add.f32 	%f768, %f763, %f767;
	add.f32 	%f769, %f764, %f768;
	sub.f32 	%f770, %f764, %f769;
	add.f32 	%f771, %f768, %f770;
	mov.f32 	%f772, 0f3ED55555;
	mul.rn.f32 	%f773, %f772, %f769;
	neg.f32 	%f774, %f773;
	fma.rn.f32 	%f775, %f772, %f769, %f774;
	fma.rn.f32 	%f776, %f772, %f771, %f775;
	mov.f32 	%f777, 0f00000000;
	fma.rn.f32 	%f778, %f777, %f769, %f776;
	add.rn.f32 	%f779, %f773, %f778;
	neg.f32 	%f780, %f779;
	add.rn.f32 	%f781, %f773, %f780;
	add.rn.f32 	%f782, %f781, %f778;
	mov.b32 	%r273, %f779;
	setp.eq.s32 	%p106, %r273, 1118925336;
	add.s32 	%r274, %r273, -1;
	mov.b32 	%f783, %r274;
	add.f32 	%f784, %f782, 0f37000000;
	selp.f32 	%f170, %f784, %f782, %p106;
	selp.f32 	%f785, %f783, %f779, %p106;
	mov.f32 	%f786, 0f3FB8AA3B;
	mul.rn.f32 	%f787, %f785, %f786;
	cvt.rzi.f32.f32 	%f788, %f787;
	abs.f32 	%f789, %f788;
	setp.gt.f32 	%p107, %f789, 0f42FC0000;
	mov.b32 	%r275, %f788;
	and.b32  	%r276, %r275, -2147483648;
	or.b32  	%r277, %r276, 1123811328;
	mov.b32 	%f790, %r277;
	selp.f32 	%f791, %f790, %f788, %p107;
	mov.f32 	%f792, 0fBF317218;
	fma.rn.f32 	%f793, %f791, %f792, %f785;
	mov.f32 	%f794, 0f3102E308;
	fma.rn.f32 	%f795, %f791, %f794, %f793;
	mul.f32 	%f796, %f795, 0f3FB8AA3B;
	add.f32 	%f797, %f791, 0f4B40007F;
	mov.b32 	%r278, %f797;
	shl.b32 	%r279, %r278, 23;
	mov.b32 	%f798, %r279;
	ex2.approx.ftz.f32 	%f799, %f796;
	mul.f32 	%f171, %f799, %f798;
	setp.eq.f32 	%p108, %f171, 0f7F800000;
	mov.f32 	%f1258, 0f7F800000;
	@%p108 bra 	$L__BB0_87;

	fma.rn.f32 	%f1258, %f171, %f170, %f171;

$L__BB0_87:
	setp.lt.f32 	%p109, %f155, 0f00000000;
	and.pred  	%p5, %p109, %p96;
	setp.eq.f32 	%p111, %f155, 0f00000000;
	@%p111 bra 	$L__BB0_91;
	bra.uni 	$L__BB0_88;

$L__BB0_91:
	add.f32 	%f804, %f155, %f155;
	selp.f32 	%f1260, %f804, 0f00000000, %p96;
	bra.uni 	$L__BB0_92;

$L__BB0_88:
	mov.b32 	%r280, %f1258;
	xor.b32  	%r281, %r280, -2147483648;
	mov.b32 	%f800, %r281;
	selp.f32 	%f1260, %f800, %f1258, %p5;
	setp.geu.f32 	%p112, %f155, 0f00000000;
	@%p112 bra 	$L__BB0_92;

	mov.f32 	%f801, 0f3ED55555;
	cvt.rzi.f32.f32 	%f802, %f801;
	setp.eq.f32 	%p113, %f802, 0f3ED55555;
	@%p113 bra 	$L__BB0_92;

	mov.f32 	%f1260, 0f7FFFFFFF;

$L__BB0_92:
	mov.f32 	%f1181, 0f00000000;
	max.f32 	%f1180, %f1181, %f638;
	abs.f32 	%f1179, %f1180;
	add.f32 	%f805, %f1179, 0f3ED55555;
	mov.b32 	%r282, %f805;
	setp.lt.s32 	%p115, %r282, 2139095040;
	@%p115 bra 	$L__BB0_97;

	mov.f32 	%f1184, 0f00000000;
	max.f32 	%f1183, %f1184, %f638;
	abs.f32 	%f1182, %f1183;
	setp.gtu.f32 	%p116, %f1182, 0f7F800000;
	@%p116 bra 	$L__BB0_96;
	bra.uni 	$L__BB0_94;

$L__BB0_96:
	add.f32 	%f1260, %f155, 0f3ED55555;
	bra.uni 	$L__BB0_97;

$L__BB0_94:
	mov.f32 	%f1187, 0f00000000;
	max.f32 	%f1186, %f1187, %f638;
	abs.f32 	%f1185, %f1186;
	setp.neu.f32 	%p117, %f1185, 0f7F800000;
	@%p117 bra 	$L__BB0_97;

	selp.f32 	%f1260, 0fFF800000, 0f7F800000, %p5;

$L__BB0_97:
	abs.f32 	%f180, %f156;
	setp.lt.f32 	%p118, %f180, 0f00800000;
	mul.f32 	%f807, %f180, 0f4B800000;
	selp.f32 	%f808, %f807, %f180, %p118;
	selp.f32 	%f809, 0fC3170000, 0fC2FE0000, %p118;
	mov.b32 	%r283, %f808;
	and.b32  	%r284, %r283, 8388607;
	or.b32  	%r285, %r284, 1065353216;
	mov.b32 	%f810, %r285;
	shr.u32 	%r286, %r283, 23;
	cvt.rn.f32.u32 	%f811, %r286;
	add.f32 	%f812, %f809, %f811;
	setp.gt.f32 	%p119, %f810, 0f3FB504F3;
	mul.f32 	%f813, %f810, 0f3F000000;
	add.f32 	%f814, %f812, 0f3F800000;
	selp.f32 	%f815, %f814, %f812, %p119;
	selp.f32 	%f816, %f813, %f810, %p119;
	add.f32 	%f817, %f816, 0fBF800000;
	add.f32 	%f818, %f816, 0f3F800000;
	rcp.approx.ftz.f32 	%f819, %f818;
	add.f32 	%f820, %f817, %f817;
	mul.f32 	%f821, %f820, %f819;
	mul.f32 	%f822, %f821, %f821;
	mov.f32 	%f823, 0f3C4CAF63;
	mov.f32 	%f824, 0f3B18F0FE;
	fma.rn.f32 	%f825, %f824, %f822, %f823;
	mov.f32 	%f826, 0f3DAAAABD;
	fma.rn.f32 	%f827, %f825, %f822, %f826;
	mul.rn.f32 	%f828, %f827, %f822;
	mul.rn.f32 	%f829, %f828, %f821;
	sub.f32 	%f830, %f817, %f821;
	add.f32 	%f831, %f830, %f830;
	neg.f32 	%f832, %f821;
	fma.rn.f32 	%f833, %f832, %f817, %f831;
	mul.rn.f32 	%f834, %f819, %f833;
	add.f32 	%f835, %f829, %f821;
	sub.f32 	%f836, %f821, %f835;
	add.f32 	%f837, %f829, %f836;
	add.f32 	%f838, %f834, %f837;
	add.f32 	%f839, %f835, %f838;
	sub.f32 	%f840, %f835, %f839;
	add.f32 	%f841, %f838, %f840;
	mov.f32 	%f842, 0f3F317200;
	mul.rn.f32 	%f843, %f815, %f842;
	mov.f32 	%f844, 0f35BFBE8E;
	mul.rn.f32 	%f845, %f815, %f844;
	add.f32 	%f846, %f843, %f839;
	sub.f32 	%f847, %f843, %f846;
	add.f32 	%f848, %f839, %f847;
	add.f32 	%f849, %f841, %f848;
	add.f32 	%f850, %f845, %f849;
	add.f32 	%f851, %f846, %f850;
	sub.f32 	%f852, %f846, %f851;
	add.f32 	%f853, %f850, %f852;
	mov.f32 	%f854, 0f3ED55555;
	mul.rn.f32 	%f855, %f854, %f851;
	neg.f32 	%f856, %f855;
	fma.rn.f32 	%f857, %f854, %f851, %f856;
	fma.rn.f32 	%f858, %f854, %f853, %f857;
	mov.f32 	%f859, 0f00000000;
	fma.rn.f32 	%f860, %f859, %f851, %f858;
	add.rn.f32 	%f861, %f855, %f860;
	neg.f32 	%f862, %f861;
	add.rn.f32 	%f863, %f855, %f862;
	add.rn.f32 	%f864, %f863, %f860;
	mov.b32 	%r287, %f861;
	setp.eq.s32 	%p120, %r287, 1118925336;
	add.s32 	%r288, %r287, -1;
	mov.b32 	%f865, %r288;
	add.f32 	%f866, %f864, 0f37000000;
	selp.f32 	%f181, %f866, %f864, %p120;
	selp.f32 	%f867, %f865, %f861, %p120;
	mov.f32 	%f868, 0f3FB8AA3B;
	mul.rn.f32 	%f869, %f867, %f868;
	cvt.rzi.f32.f32 	%f870, %f869;
	abs.f32 	%f871, %f870;
	setp.gt.f32 	%p121, %f871, 0f42FC0000;
	mov.b32 	%r289, %f870;
	and.b32  	%r290, %r289, -2147483648;
	or.b32  	%r291, %r290, 1123811328;
	mov.b32 	%f872, %r291;
	selp.f32 	%f873, %f872, %f870, %p121;
	mov.f32 	%f874, 0fBF317218;
	fma.rn.f32 	%f875, %f873, %f874, %f867;
	mov.f32 	%f876, 0f3102E308;
	fma.rn.f32 	%f877, %f873, %f876, %f875;
	mul.f32 	%f878, %f877, 0f3FB8AA3B;
	add.f32 	%f879, %f873, 0f4B40007F;
	mov.b32 	%r292, %f879;
	shl.b32 	%r293, %r292, 23;
	mov.b32 	%f880, %r293;
	ex2.approx.ftz.f32 	%f881, %f878;
	mul.f32 	%f182, %f881, %f880;
	setp.eq.f32 	%p122, %f182, 0f7F800000;
	mov.f32 	%f1261, 0f7F800000;
	@%p122 bra 	$L__BB0_99;

	fma.rn.f32 	%f1261, %f182, %f181, %f182;

$L__BB0_99:
	setp.lt.f32 	%p123, %f156, 0f00000000;
	and.pred  	%p6, %p123, %p96;
	setp.eq.f32 	%p125, %f156, 0f00000000;
	@%p125 bra 	$L__BB0_103;
	bra.uni 	$L__BB0_100;

$L__BB0_103:
	add.f32 	%f886, %f156, %f156;
	selp.f32 	%f1263, %f886, 0f00000000, %p96;
	bra.uni 	$L__BB0_104;

$L__BB0_100:
	mov.b32 	%r294, %f1261;
	xor.b32  	%r295, %r294, -2147483648;
	mov.b32 	%f882, %r295;
	selp.f32 	%f1263, %f882, %f1261, %p6;
	setp.geu.f32 	%p126, %f156, 0f00000000;
	@%p126 bra 	$L__BB0_104;

	mov.f32 	%f883, 0f3ED55555;
	cvt.rzi.f32.f32 	%f884, %f883;
	setp.eq.f32 	%p127, %f884, 0f3ED55555;
	@%p127 bra 	$L__BB0_104;

	mov.f32 	%f1263, 0f7FFFFFFF;

$L__BB0_104:
	mov.f32 	%f1190, 0f00000000;
	max.f32 	%f1189, %f1190, %f639;
	abs.f32 	%f1188, %f1189;
	add.f32 	%f887, %f1188, 0f3ED55555;
	mov.b32 	%r296, %f887;
	setp.lt.s32 	%p129, %r296, 2139095040;
	@%p129 bra 	$L__BB0_109;

	mov.f32 	%f1193, 0f00000000;
	max.f32 	%f1192, %f1193, %f639;
	abs.f32 	%f1191, %f1192;
	setp.gtu.f32 	%p130, %f1191, 0f7F800000;
	@%p130 bra 	$L__BB0_108;
	bra.uni 	$L__BB0_106;

$L__BB0_108:
	add.f32 	%f1263, %f156, 0f3ED55555;
	bra.uni 	$L__BB0_109;

$L__BB0_106:
	mov.f32 	%f1196, 0f00000000;
	max.f32 	%f1195, %f1196, %f639;
	abs.f32 	%f1194, %f1195;
	setp.neu.f32 	%p131, %f1194, 0f7F800000;
	@%p131 bra 	$L__BB0_109;

	selp.f32 	%f1263, 0fFF800000, 0f7F800000, %p6;

$L__BB0_109:
	mov.f32 	%f1152, 0f00000000;
	max.f32 	%f1151, %f1152, %f636;
	ld.const.u64 	%rd143, [params+144];
	cvta.to.global.u64 	%rd142, %rd143;
	ld.const.u32 	%r351, [params+136];
	mad.lo.s32 	%r350, %r351, %r6, %r5;
	cvt.u64.u32 	%rd141, %r350;
	fma.rn.f32 	%f888, %f1257, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p132, %f1151, 0f3F800000;
	mov.f32 	%f889, 0f3F800000;
	selp.f32 	%f890, 0f3F7FFFFF, %f888, %p132;
	mul.f32 	%f891, %f1151, 0f414EB852;
	setp.lt.f32 	%p133, %f1151, 0f3B4D2E1C;
	selp.f32 	%f892, %f891, %f890, %p133;
	fma.rn.f32 	%f893, %f1260, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p134, %f155, 0f3F800000;
	selp.f32 	%f894, 0f3F7FFFFF, %f893, %p134;
	mul.f32 	%f895, %f155, 0f414EB852;
	setp.lt.f32 	%p135, %f155, 0f3B4D2E1C;
	selp.f32 	%f896, %f895, %f894, %p135;
	fma.rn.f32 	%f897, %f1263, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p136, %f156, 0f3F800000;
	selp.f32 	%f898, 0f3F7FFFFF, %f897, %p136;
	mul.f32 	%f899, %f156, 0f414EB852;
	setp.lt.f32 	%p137, %f156, 0f3B4D2E1C;
	selp.f32 	%f900, %f899, %f898, %p137;
	min.f32 	%f901, %f892, %f889;
	mov.f32 	%f902, 0f00000000;
	max.f32 	%f903, %f902, %f901;
	mul.f32 	%f904, %f903, 0f43800000;
	cvt.rzi.u32.f32 	%r297, %f904;
	min.u32 	%r298, %r297, 255;
	min.f32 	%f905, %f896, %f889;
	max.f32 	%f906, %f902, %f905;
	mul.f32 	%f907, %f906, 0f43800000;
	cvt.rzi.u32.f32 	%r299, %f907;
	min.u32 	%r300, %r299, 255;
	min.f32 	%f908, %f900, %f889;
	max.f32 	%f909, %f902, %f908;
	mul.f32 	%f910, %f909, 0f43800000;
	cvt.rzi.u32.f32 	%r301, %f910;
	min.u32 	%r302, %r301, 255;
	shl.b64 	%rd75, %rd141, 2;
	add.s64 	%rd76, %rd142, %rd75;
	cvt.u16.u32 	%rs15, %r302;
	cvt.u16.u32 	%rs16, %r300;
	cvt.u16.u32 	%rs17, %r298;
	mov.u16 	%rs18, 255;
	st.global.v4.u8 	[%rd76], {%rs17, %rs16, %rs15, %rs18};

$L__BB0_110:
	ld.const.u32 	%r352, [params+104];
	and.b32  	%r303, %r352, 4;
	setp.eq.s32 	%p138, %r303, 0;
	ld.const.u32 	%r380, [params+108];
	@%p138 bra 	$L__BB0_114;

	setp.eq.s32 	%p139, %r380, 0;
	ld.const.u64 	%rd77, [params+224];
	cvta.to.global.u64 	%rd78, %rd77;
	ld.const.u32 	%r304, [params+216];
	mad.lo.s32 	%r305, %r304, %r6, %r5;
	mul.wide.u32 	%rd79, %r305, 8;
	add.s64 	%rd18, %rd78, %rd79;
	@%p139 bra 	$L__BB0_113;

	add.f32 	%f1176, %f377, %f377;
	mul.f32 	%f1175, %f1176, %f379;
	add.f32 	%f1154, %f377, %f377;
	mul.f32 	%f1153, %f1154, %f380;
	ld.global.v4.u16 	{%rs26, %rs27, %rs28, %rs29}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f911, %rs26;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f912, %rs27;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f913, %rs28;}

	// end inline asm
	add.f32 	%f914, %f1175, %f911;
	add.f32 	%f915, %f1153, %f912;
	add.f32 	%f916, %f117, %f913;
	mov.f32 	%f917, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs24, %f916;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs23, %f915;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs22, %f914;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f917;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs22, %rs23, %rs24, %rs25};
	bra.uni 	$L__BB0_114;

$L__BB0_113:
	add.f32 	%f1178, %f377, %f377;
	mul.f32 	%f1177, %f1178, %f379;
	add.f32 	%f1156, %f377, %f377;
	mul.f32 	%f1155, %f1156, %f380;
	mov.f32 	%f921, 0f3F800000;
	mov.u32 	%r380, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f921;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f117;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs31, %f1155;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1177;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs30, %rs31, %rs32, %rs33};

$L__BB0_114:
	mul.f32 	%f191, %f379, 0f40800000;
	mul.f32 	%f922, %f103, %f191;
	mul.f32 	%f192, %f380, 0f40800000;
	mul.f32 	%f923, %f103, %f192;
	mul.f32 	%f193, %f381, 0f40800000;
	mul.f32 	%f924, %f103, %f193;
	mul.f32 	%f194, %f922, 0f3F558750;
	mul.f32 	%f195, %f923, 0f3F558750;
	mul.f32 	%f196, %f924, 0f3F558750;
	ld.const.u64 	%rd80, [params+256];
	cvta.to.global.u64 	%rd81, %rd80;
	ld.const.u32 	%r307, [params+248];
	mad.lo.s32 	%r308, %r307, %r6, %r5;
	mul.wide.u32 	%rd82, %r308, 8;
	add.s64 	%rd19, %rd81, %rd82;
	setp.eq.s32 	%p140, %r380, 0;
	@%p140 bra 	$L__BB0_116;

	ld.global.v4.u16 	{%rs41, %rs42, %rs43, %rs44}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f925, %rs41;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f926, %rs42;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f927, %rs43;}

	// end inline asm
	add.f32 	%f928, %f194, %f925;
	add.f32 	%f929, %f195, %f926;
	add.f32 	%f930, %f196, %f927;
	mov.f32 	%f931, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs39, %f930;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f929;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f928;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f931;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs37, %rs38, %rs39, %rs40};
	bra.uni 	$L__BB0_117;

$L__BB0_116:
	mov.f32 	%f935, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f935;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs47, %f196;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f195;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f194;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs45, %rs46, %rs47, %rs48};

$L__BB0_117:
	mul.f32 	%f936, %f104, %f191;
	mul.f32 	%f197, %f936, 0f3FB8EBD1;
	mul.f32 	%f937, %f104, %f192;
	mul.f32 	%f198, %f937, 0f3FB8EBD1;
	mul.f32 	%f938, %f104, %f193;
	mul.f32 	%f199, %f938, 0f3FB8EBD1;
	ld.const.u64 	%rd83, [params+272];
	cvta.to.global.u64 	%rd84, %rd83;
	ld.const.u32 	%r309, [params+264];
	mad.lo.s32 	%r310, %r309, %r6, %r5;
	mul.wide.u32 	%rd85, %r310, 8;
	add.s64 	%rd20, %rd84, %rd85;
	@%p140 bra 	$L__BB0_119;

	ld.global.v4.u16 	{%rs56, %rs57, %rs58, %rs59}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f939, %rs56;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f940, %rs57;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f941, %rs58;}

	// end inline asm
	add.f32 	%f942, %f197, %f939;
	add.f32 	%f943, %f198, %f940;
	add.f32 	%f944, %f199, %f941;
	mov.f32 	%f945, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f944;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f943;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f942;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f945;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs52, %rs53, %rs54, %rs55};
	bra.uni 	$L__BB0_120;

$L__BB0_119:
	mov.f32 	%f949, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f949;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f199;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f198;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f197;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs60, %rs61, %rs62, %rs63};

$L__BB0_120:
	mul.f32 	%f950, %f105, %f191;
	mul.f32 	%f200, %f950, 0f3FB8EBD1;
	mul.f32 	%f951, %f105, %f192;
	mul.f32 	%f201, %f951, 0f3FB8EBD1;
	mul.f32 	%f952, %f105, %f193;
	mul.f32 	%f202, %f952, 0f3FB8EBD1;
	ld.const.u64 	%rd86, [params+288];
	cvta.to.global.u64 	%rd87, %rd86;
	ld.const.u32 	%r311, [params+280];
	mad.lo.s32 	%r312, %r311, %r6, %r5;
	mul.wide.u32 	%rd88, %r312, 8;
	add.s64 	%rd21, %rd87, %rd88;
	@%p140 bra 	$L__BB0_122;

	ld.global.v4.u16 	{%rs71, %rs72, %rs73, %rs74}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f953, %rs71;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f954, %rs72;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f955, %rs73;}

	// end inline asm
	add.f32 	%f956, %f200, %f953;
	add.f32 	%f957, %f201, %f954;
	add.f32 	%f958, %f202, %f955;
	mov.f32 	%f959, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f958;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f957;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f956;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f959;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs67, %rs68, %rs69, %rs70};
	bra.uni 	$L__BB0_123;

$L__BB0_122:
	mov.f32 	%f963, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f963;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f202;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f201;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f200;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs75, %rs76, %rs77, %rs78};

$L__BB0_123:
	mul.f32 	%f964, %f106, %f191;
	mul.f32 	%f203, %f964, 0f3FB8EBD1;
	mul.f32 	%f965, %f106, %f192;
	mul.f32 	%f204, %f965, 0f3FB8EBD1;
	mul.f32 	%f966, %f106, %f193;
	mul.f32 	%f205, %f966, 0f3FB8EBD1;
	ld.const.u64 	%rd89, [params+304];
	cvta.to.global.u64 	%rd90, %rd89;
	ld.const.u32 	%r313, [params+296];
	mad.lo.s32 	%r314, %r313, %r6, %r5;
	mul.wide.u32 	%rd91, %r314, 8;
	add.s64 	%rd22, %rd90, %rd91;
	@%p140 bra 	$L__BB0_125;

	ld.global.v4.u16 	{%rs86, %rs87, %rs88, %rs89}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f967, %rs86;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f968, %rs87;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f969, %rs88;}

	// end inline asm
	add.f32 	%f970, %f203, %f967;
	add.f32 	%f971, %f204, %f968;
	add.f32 	%f972, %f205, %f969;
	mov.f32 	%f973, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f972;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f971;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f970;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f973;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs82, %rs83, %rs84, %rs85};
	bra.uni 	$L__BB0_126;

$L__BB0_125:
	mov.f32 	%f977, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f977;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f205;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f204;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f203;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs90, %rs91, %rs92, %rs93};

$L__BB0_126:
	mul.f32 	%f978, %f107, %f191;
	mul.f32 	%f206, %f978, 0f404EBF87;
	mul.f32 	%f979, %f107, %f192;
	mul.f32 	%f207, %f979, 0f404EBF87;
	mul.f32 	%f980, %f107, %f193;
	mul.f32 	%f208, %f980, 0f404EBF87;
	ld.const.u64 	%rd92, [params+320];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r315, [params+312];
	mad.lo.s32 	%r316, %r315, %r6, %r5;
	mul.wide.u32 	%rd94, %r316, 8;
	add.s64 	%rd23, %rd93, %rd94;
	@%p140 bra 	$L__BB0_128;

	ld.global.v4.u16 	{%rs101, %rs102, %rs103, %rs104}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f981, %rs101;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f982, %rs102;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f983, %rs103;}

	// end inline asm
	add.f32 	%f984, %f206, %f981;
	add.f32 	%f985, %f207, %f982;
	add.f32 	%f986, %f208, %f983;
	mov.f32 	%f987, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f986;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f985;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f984;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f987;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs97, %rs98, %rs99, %rs100};
	bra.uni 	$L__BB0_129;

$L__BB0_128:
	mov.f32 	%f991, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f991;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f208;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f207;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f206;}

	// end inline asm
	st.global.v4.u16 	[%rd23], {%rs105, %rs106, %rs107, %rs108};

$L__BB0_129:
	mul.f32 	%f992, %f108, %f191;
	mul.f32 	%f209, %f992, 0f404EBF87;
	mul.f32 	%f993, %f108, %f192;
	mul.f32 	%f210, %f993, 0f404EBF87;
	mul.f32 	%f994, %f108, %f193;
	mul.f32 	%f211, %f994, 0f404EBF87;
	ld.const.u64 	%rd95, [params+336];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r317, [params+328];
	mad.lo.s32 	%r318, %r317, %r6, %r5;
	mul.wide.u32 	%rd97, %r318, 8;
	add.s64 	%rd24, %rd96, %rd97;
	@%p140 bra 	$L__BB0_131;

	ld.global.v4.u16 	{%rs116, %rs117, %rs118, %rs119}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f995, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f996, %rs117;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f997, %rs118;}

	// end inline asm
	add.f32 	%f998, %f209, %f995;
	add.f32 	%f999, %f210, %f996;
	add.f32 	%f1000, %f211, %f997;
	mov.f32 	%f1001, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1000;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f999;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs112, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1001;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs112, %rs113, %rs114, %rs115};
	bra.uni 	$L__BB0_132;

$L__BB0_131:
	mov.f32 	%f1005, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f1005;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f211;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f210;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f209;}

	// end inline asm
	st.global.v4.u16 	[%rd24], {%rs120, %rs121, %rs122, %rs123};

$L__BB0_132:
	mul.f32 	%f1006, %f109, %f191;
	mul.f32 	%f212, %f1006, 0f40330C94;
	mul.f32 	%f1007, %f109, %f192;
	mul.f32 	%f213, %f1007, 0f40330C94;
	mul.f32 	%f1008, %f109, %f193;
	mul.f32 	%f214, %f1008, 0f40330C94;
	ld.const.u64 	%rd98, [params+352];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r319, [params+344];
	mad.lo.s32 	%r320, %r319, %r6, %r5;
	mul.wide.u32 	%rd100, %r320, 8;
	add.s64 	%rd25, %rd99, %rd100;
	@%p140 bra 	$L__BB0_134;

	ld.global.v4.u16 	{%rs131, %rs132, %rs133, %rs134}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1009, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1010, %rs132;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1011, %rs133;}

	// end inline asm
	add.f32 	%f1012, %f212, %f1009;
	add.f32 	%f1013, %f213, %f1010;
	add.f32 	%f1014, %f214, %f1011;
	mov.f32 	%f1015, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1014;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1013;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs127, %f1012;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1015;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs127, %rs128, %rs129, %rs130};
	bra.uni 	$L__BB0_135;

$L__BB0_134:
	mov.f32 	%f1019, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f214;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f213;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f212;}

	// end inline asm
	st.global.v4.u16 	[%rd25], {%rs135, %rs136, %rs137, %rs138};

$L__BB0_135:
	mul.f32 	%f1020, %f110, %f191;
	mul.f32 	%f215, %f1020, 0f404EBF87;
	mul.f32 	%f1021, %f110, %f192;
	mul.f32 	%f216, %f1021, 0f404EBF87;
	mul.f32 	%f1022, %f110, %f193;
	mul.f32 	%f217, %f1022, 0f404EBF87;
	ld.const.u64 	%rd101, [params+368];
	cvta.to.global.u64 	%rd102, %rd101;
	ld.const.u32 	%r321, [params+360];
	mad.lo.s32 	%r322, %r321, %r6, %r5;
	mul.wide.u32 	%rd103, %r322, 8;
	add.s64 	%rd26, %rd102, %rd103;
	@%p140 bra 	$L__BB0_137;

	ld.global.v4.u16 	{%rs146, %rs147, %rs148, %rs149}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1023, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1024, %rs147;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1025, %rs148;}

	// end inline asm
	add.f32 	%f1026, %f215, %f1023;
	add.f32 	%f1027, %f216, %f1024;
	add.f32 	%f1028, %f217, %f1025;
	mov.f32 	%f1029, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1028;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1027;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs142, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1029;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs142, %rs143, %rs144, %rs145};
	bra.uni 	$L__BB0_138;

$L__BB0_137:
	mov.f32 	%f1033, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f1033;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f217;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f216;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f215;}

	// end inline asm
	st.global.v4.u16 	[%rd26], {%rs150, %rs151, %rs152, %rs153};

$L__BB0_138:
	mul.f32 	%f1034, %f111, %f191;
	mul.f32 	%f218, %f1034, 0f3FCEBF87;
	mul.f32 	%f1035, %f111, %f192;
	mul.f32 	%f219, %f1035, 0f3FCEBF87;
	mul.f32 	%f1036, %f111, %f193;
	mul.f32 	%f220, %f1036, 0f3FCEBF87;
	ld.const.u64 	%rd104, [params+384];
	cvta.to.global.u64 	%rd105, %rd104;
	ld.const.u32 	%r323, [params+376];
	mad.lo.s32 	%r324, %r323, %r6, %r5;
	mul.wide.u32 	%rd106, %r324, 8;
	add.s64 	%rd27, %rd105, %rd106;
	@%p140 bra 	$L__BB0_140;

	ld.global.v4.u16 	{%rs161, %rs162, %rs163, %rs164}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1037, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1038, %rs162;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1039, %rs163;}

	// end inline asm
	add.f32 	%f1040, %f218, %f1037;
	add.f32 	%f1041, %f219, %f1038;
	add.f32 	%f1042, %f220, %f1039;
	mov.f32 	%f1043, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1042;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs157, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1043;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs157, %rs158, %rs159, %rs160};
	bra.uni 	$L__BB0_174;

$L__BB0_140:
	mov.f32 	%f1047, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f1047;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f220;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f219;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f218;}

	// end inline asm
	st.global.v4.u16 	[%rd27], {%rs165, %rs166, %rs167, %rs168};

$L__BB0_174:
	ret;

}