//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__closesthit__oxMain
.const .align 16 .b8 params[1184];

.visible .entry __closesthit__oxMain()
{
	.reg .pred 	%p<20>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<139>;
	.reg .b32 	%r<50>;
	.reg .b64 	%rd<2>;


	// begin inline asm
	call (%r5), _optix_read_primitive_idx, ();
	// end inline asm
	// begin inline asm
	call (%f21, %f22), _optix_get_triangle_barycentrics, ();
	// end inline asm
	mov.u32 	%r20, 0;
	// begin inline asm
	call (%rd1), _optix_call_direct_callable,(%r20);
	// end inline asm
	{ // callseq 0, 0
	.reg .b32 temp_param_reg;
	.param .b32 param0;
	st.param.b32 	[param0+0], %r5;
	.param .align 8 .b8 param1[8];
	st.param.v2.f32 	[param1+0], {%f21, %f22};
	.param .align 8 .b8 retval0[32];
	prototype_0 : .callprototype (.param .align 8 .b8 _[32]) _ (.param .b32 _, .param .align 8 .b8 _[8]);
	call (retval0), 
	%rd1, 
	(
	param0, 
	param1
	)
	, prototype_0;
	ld.param.v2.f32 	{%f1, %f2}, [retval0+0];
	ld.param.f32 	%f3, [retval0+8];
	ld.param.v4.b8 	{%rs1, %rs2, %rs3, %rs4}, [retval0+12];
	ld.param.v2.f32 	{%f4, %f5}, [retval0+16];
	ld.param.f32 	%f6, [retval0+24];
	ld.param.v4.b8 	{%rs5, %rs6, %rs7, %rs8}, [retval0+28];
	} // callseq 0
	mov.u32 	%r17, 1;
	// begin inline asm
	call (%f23), _optix_get_world_ray_direction_x, ();
	// end inline asm
	// begin inline asm
	call (%f24), _optix_get_world_ray_direction_y, ();
	// end inline asm
	// begin inline asm
	call (%f25), _optix_get_world_ray_direction_z, ();
	// end inline asm
	mul.f32 	%f27, %f2, %f24;
	fma.rn.f32 	%f28, %f1, %f23, %f27;
	fma.rn.f32 	%f29, %f3, %f25, %f28;
	setp.gt.f32 	%p2, %f29, 0f00000000;
	// begin inline asm
	call (%f26), _optix_get_ray_tmax, ();
	// end inline asm
	// begin inline asm
	call (%r7), _optix_get_payload, (%r20);
	// end inline asm
	// begin inline asm
	call (%r9), _optix_get_payload, (%r17);
	// end inline asm
	mov.u32 	%r19, 2;
	// begin inline asm
	call (%r11), _optix_get_payload, (%r19);
	// end inline asm
	mov.u32 	%r21, 3;
	// begin inline asm
	call (%r13), _optix_get_payload, (%r21);
	// end inline asm
	// begin inline asm
	call _optix_set_payload, (%r20, %r20);
	// end inline asm
	// begin inline asm
	call _optix_set_payload, (%r17, %r20);
	// end inline asm
	// begin inline asm
	call _optix_set_payload, (%r19, %r20);
	// end inline asm
	mov.u32 	%r22, 2139095039;
	// begin inline asm
	call _optix_set_payload, (%r21, %r22);
	// end inline asm
	@%p2 bra 	$L__BB0_15;

	div.rn.f32 	%f30, %f4, 0f41200000;
	mov.b32 	%r23, %f30;
	and.b32  	%r24, %r23, -2147483648;
	or.b32  	%r25, %r24, 1056964608;
	mov.b32 	%f31, %r25;
	add.rz.f32 	%f32, %f30, %f31;
	cvt.rzi.f32.f32 	%f33, %f32;
	cvt.rzi.s32.f32 	%r26, %f33;
	ld.const.u32 	%r27, [params+664];
	setp.ne.s32 	%p3, %r26, %r27;
	@%p3 bra 	$L__BB0_15;

	ld.const.f32 	%f35, [params+660];
	mul.f32 	%f8, %f26, %f35;
	mov.f32 	%f36, 0f40000000;
	cvt.rzi.f32.f32 	%f37, %f36;
	add.f32 	%f38, %f37, %f37;
	mov.f32 	%f39, 0f40800000;
	sub.f32 	%f40, %f39, %f38;
	abs.f32 	%f9, %f40;
	abs.f32 	%f10, %f8;
	setp.lt.f32 	%p4, %f10, 0f00800000;
	mul.f32 	%f41, %f10, 0f4B800000;
	selp.f32 	%f42, %f41, %f10, %p4;
	selp.f32 	%f43, 0fC3170000, 0fC2FE0000, %p4;
	mov.b32 	%r28, %f42;
	and.b32  	%r29, %r28, 8388607;
	or.b32  	%r30, %r29, 1065353216;
	mov.b32 	%f44, %r30;
	shr.u32 	%r31, %r28, 23;
	cvt.rn.f32.u32 	%f45, %r31;
	add.f32 	%f46, %f43, %f45;
	setp.gt.f32 	%p5, %f44, 0f3FB504F3;
	mul.f32 	%f47, %f44, 0f3F000000;
	add.f32 	%f48, %f46, 0f3F800000;
	selp.f32 	%f49, %f48, %f46, %p5;
	selp.f32 	%f50, %f47, %f44, %p5;
	add.f32 	%f51, %f50, 0fBF800000;
	add.f32 	%f52, %f50, 0f3F800000;
	rcp.approx.ftz.f32 	%f53, %f52;
	add.f32 	%f54, %f51, %f51;
	mul.f32 	%f55, %f54, %f53;
	mul.f32 	%f56, %f55, %f55;
	mov.f32 	%f57, 0f3C4CAF63;
	mov.f32 	%f58, 0f3B18F0FE;
	fma.rn.f32 	%f59, %f58, %f56, %f57;
	mov.f32 	%f60, 0f3DAAAABD;
	fma.rn.f32 	%f61, %f59, %f56, %f60;
	mul.rn.f32 	%f62, %f61, %f56;
	mul.rn.f32 	%f63, %f62, %f55;
	sub.f32 	%f64, %f51, %f55;
	add.f32 	%f65, %f64, %f64;
	neg.f32 	%f66, %f55;
	fma.rn.f32 	%f67, %f66, %f51, %f65;
	mul.rn.f32 	%f68, %f53, %f67;
	add.f32 	%f69, %f63, %f55;
	sub.f32 	%f70, %f55, %f69;
	add.f32 	%f71, %f63, %f70;
	add.f32 	%f72, %f68, %f71;
	add.f32 	%f73, %f69, %f72;
	sub.f32 	%f74, %f69, %f73;
	add.f32 	%f75, %f72, %f74;
	mov.f32 	%f76, 0f3F317200;
	mul.rn.f32 	%f77, %f49, %f76;
	mov.f32 	%f78, 0f35BFBE8E;
	mul.rn.f32 	%f79, %f49, %f78;
	add.f32 	%f80, %f77, %f73;
	sub.f32 	%f81, %f77, %f80;
	add.f32 	%f82, %f73, %f81;
	add.f32 	%f83, %f75, %f82;
	add.f32 	%f84, %f79, %f83;
	add.f32 	%f85, %f80, %f84;
	sub.f32 	%f86, %f80, %f85;
	add.f32 	%f87, %f84, %f86;
	mul.rn.f32 	%f88, %f39, %f85;
	neg.f32 	%f89, %f88;
	fma.rn.f32 	%f90, %f39, %f85, %f89;
	fma.rn.f32 	%f91, %f39, %f87, %f90;
	mov.f32 	%f92, 0f00000000;
	fma.rn.f32 	%f93, %f92, %f85, %f91;
	add.rn.f32 	%f94, %f88, %f93;
	neg.f32 	%f95, %f94;
	add.rn.f32 	%f96, %f88, %f95;
	add.rn.f32 	%f97, %f96, %f93;
	mov.b32 	%r32, %f94;
	setp.eq.s32 	%p6, %r32, 1118925336;
	add.s32 	%r33, %r32, -1;
	mov.b32 	%f98, %r33;
	add.f32 	%f99, %f97, 0f37000000;
	selp.f32 	%f11, %f99, %f97, %p6;
	selp.f32 	%f100, %f98, %f94, %p6;
	mov.f32 	%f101, 0f3FB8AA3B;
	mul.rn.f32 	%f102, %f100, %f101;
	cvt.rzi.f32.f32 	%f103, %f102;
	abs.f32 	%f104, %f103;
	setp.gt.f32 	%p7, %f104, 0f42FC0000;
	mov.b32 	%r34, %f103;
	and.b32  	%r35, %r34, -2147483648;
	or.b32  	%r36, %r35, 1123811328;
	mov.b32 	%f105, %r36;
	selp.f32 	%f106, %f105, %f103, %p7;
	mov.f32 	%f107, 0fBF317218;
	fma.rn.f32 	%f108, %f106, %f107, %f100;
	mov.f32 	%f109, 0f3102E308;
	fma.rn.f32 	%f110, %f106, %f109, %f108;
	mul.f32 	%f111, %f110, 0f3FB8AA3B;
	add.f32 	%f112, %f106, 0f4B40007F;
	mov.b32 	%r37, %f112;
	shl.b32 	%r38, %r37, 23;
	mov.b32 	%f113, %r38;
	ex2.approx.ftz.f32 	%f114, %f111;
	mul.f32 	%f12, %f114, %f113;
	setp.eq.f32 	%p8, %f12, 0f7F800000;
	mov.f32 	%f136, 0f7F800000;
	@%p8 bra 	$L__BB0_4;

	fma.rn.f32 	%f136, %f12, %f11, %f12;

$L__BB0_4:
	setp.lt.f32 	%p9, %f8, 0f00000000;
	setp.eq.f32 	%p10, %f9, 0f3F800000;
	and.pred  	%p1, %p9, %p10;
	setp.eq.f32 	%p11, %f8, 0f00000000;
	@%p11 bra 	$L__BB0_8;
	bra.uni 	$L__BB0_5;

$L__BB0_8:
	add.f32 	%f119, %f8, %f8;
	selp.f32 	%f138, %f119, 0f00000000, %p10;
	bra.uni 	$L__BB0_9;

$L__BB0_5:
	mov.b32 	%r39, %f136;
	xor.b32  	%r40, %r39, -2147483648;
	mov.b32 	%f115, %r40;
	selp.f32 	%f138, %f115, %f136, %p1;
	setp.geu.f32 	%p12, %f8, 0f00000000;
	@%p12 bra 	$L__BB0_9;

	mov.f32 	%f116, 0f40800000;
	cvt.rzi.f32.f32 	%f117, %f116;
	setp.eq.f32 	%p13, %f117, 0f40800000;
	@%p13 bra 	$L__BB0_9;

	mov.f32 	%f138, 0f7FFFFFFF;

$L__BB0_9:
	add.f32 	%f120, %f10, 0f40800000;
	mov.b32 	%r41, %f120;
	setp.lt.s32 	%p15, %r41, 2139095040;
	@%p15 bra 	$L__BB0_14;

	setp.gtu.f32 	%p16, %f10, 0f7F800000;
	@%p16 bra 	$L__BB0_13;
	bra.uni 	$L__BB0_11;

$L__BB0_13:
	add.f32 	%f138, %f8, 0f40800000;
	bra.uni 	$L__BB0_14;

$L__BB0_11:
	setp.neu.f32 	%p17, %f10, 0f7F800000;
	@%p17 bra 	$L__BB0_14;

	selp.f32 	%f138, 0fFF800000, 0f7F800000, %p1;

$L__BB0_14:
	mov.f32 	%f121, 0f3F800000;
	sub.f32 	%f122, %f121, %f138;
	setp.eq.f32 	%p18, %f8, 0f3F800000;
	selp.f32 	%f123, 0f00000000, %f122, %p18;
	cvt.sat.f32.f32 	%f124, %f123;
	mov.b32 	%f125, %r13;
	setp.gt.f32 	%p19, %f26, %f125;
	mov.b32 	%f126, %r11;
	selp.f32 	%f127, %f126, 0f3F800000, %p19;
	mov.b32 	%f128, %r9;
	selp.f32 	%f129, %f128, 0f3F800000, %p19;
	mov.b32 	%f130, %r7;
	selp.f32 	%f131, %f130, 0f3F800000, %p19;
	mul.f32 	%f132, %f124, %f131;
	mul.f32 	%f133, %f124, %f129;
	mul.f32 	%f134, %f124, %f127;
	mov.b32 	%r43, %f132;
	mov.u32 	%r42, 0;
	// begin inline asm
	call _optix_set_payload, (%r42, %r43);
	// end inline asm
	mov.b32 	%r45, %f133;
	mov.u32 	%r44, 1;
	// begin inline asm
	call _optix_set_payload, (%r44, %r45);
	// end inline asm
	mov.b32 	%r47, %f134;
	mov.u32 	%r46, 2;
	// begin inline asm
	call _optix_set_payload, (%r46, %r47);
	// end inline asm
	neg.f32 	%f135, %f26;
	mov.b32 	%r49, %f135;
	mov.u32 	%r48, 3;
	// begin inline asm
	call _optix_set_payload, (%r48, %r49);
	// end inline asm

$L__BB0_15:
	ret;

}