//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];

.visible .entry __raygen__oxMain()
{
	.reg .pred 	%p<210>;
	.reg .b16 	%rs<180>;
	.reg .f32 	%f<1769>;
	.reg .b32 	%r<454>;
	.reg .b64 	%rd<78>;


	// begin inline asm
	call (%r26), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r27), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u64 	%rd21, [params+400];
	cvta.to.global.u64 	%rd22, %rd21;
	ld.const.u32 	%r32, [params+392];
	mad.lo.s32 	%r33, %r32, %r27, %r26;
	mul.wide.u32 	%rd23, %r33, 4;
	add.s64 	%rd1, %rd22, %rd23;
	ld.global.v2.u8 	{%rs9, %rs178}, [%rd1];
	or.b16  	%rs11, %rs9, %rs178;
	and.b16  	%rs12, %rs11, 255;
	setp.eq.s16 	%p11, %rs12, 0;
	@%p11 bra 	$L__BB0_2;

	ld.global.u8 	%rs177, [%rd1+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs177, [%rd1+2];
	setp.eq.s16 	%p12, %rs177, 0;
	mov.f32 	%f1652, 0f00000000;
	mov.u16 	%rs178, 0;
	mov.f32 	%f1653, %f1652;
	mov.f32 	%f1654, %f1652;
	@%p12 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f331, %rs9;
	div.rn.f32 	%f332, %f331, 0f437F0000;
	fma.rn.f32 	%f333, %f332, 0f40000000, 0fBF800000;
	and.b16  	%rs15, %rs178, 255;
	cvt.rn.f32.u16 	%f334, %rs15;
	div.rn.f32 	%f335, %f334, 0f437F0000;
	fma.rn.f32 	%f336, %f335, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f337, %rs177;
	div.rn.f32 	%f338, %f337, 0f437F0000;
	fma.rn.f32 	%f339, %f338, 0f40000000, 0fBF800000;
	mul.f32 	%f340, %f336, %f336;
	fma.rn.f32 	%f341, %f333, %f333, %f340;
	fma.rn.f32 	%f342, %f339, %f339, %f341;
	sqrt.rn.f32 	%f343, %f342;
	rcp.rn.f32 	%f344, %f343;
	mul.f32 	%f1654, %f344, %f339;
	mul.f32 	%f1653, %f344, %f336;
	mul.f32 	%f1652, %f333, %f344;

$L__BB0_4:
	ld.const.v2.u32 	{%r34, %r35}, [params];
	add.s32 	%r3, %r34, %r26;
	add.s32 	%r4, %r35, %r27;
	setp.eq.f32 	%p13, %f1652, 0f00000000;
	setp.eq.f32 	%p14, %f1653, 0f00000000;
	and.pred  	%p15, %p13, %p14;
	setp.eq.f32 	%p16, %f1654, 0f00000000;
	and.pred  	%p17, %p16, %p15;
	@%p17 bra 	$L__BB0_163;
	bra.uni 	$L__BB0_5;

$L__BB0_163:
	ld.const.u32 	%r23, [params+104];
	and.b32  	%r428, %r23, 1;
	setp.eq.b32 	%p198, %r428, 1;
	mov.pred 	%p199, 0;
	xor.pred  	%p200, %p198, %p199;
	not.pred 	%p201, %p200;
	@%p201 bra 	$L__BB0_165;

	ld.const.u64 	%rd54, [params+144];
	cvta.to.global.u64 	%rd55, %rd54;
	ld.const.u32 	%r429, [params+136];
	mad.lo.s32 	%r430, %r429, %r4, %r3;
	mul.wide.u32 	%rd56, %r430, 4;
	add.s64 	%rd57, %rd55, %rd56;
	mov.u16 	%rs99, 0;
	st.global.v4.u8 	[%rd57], {%rs99, %rs99, %rs99, %rs99};

$L__BB0_165:
	and.b32  	%r431, %r23, 8;
	setp.eq.s32 	%p202, %r431, 0;
	@%p202 bra 	$L__BB0_167;

	ld.const.u64 	%rd58, [params+192];
	cvta.to.global.u64 	%rd59, %rd58;
	ld.const.u32 	%r432, [params+184];
	mad.lo.s32 	%r433, %r432, %r4, %r3;
	mov.f32 	%f1603, 0f00000000;
	cvt.rzi.u32.f32 	%r434, %f1603;
	mul.wide.u32 	%rd60, %r433, 2;
	add.s64 	%rd61, %rd59, %rd60;
	mov.u16 	%rs100, 0;
	cvt.u16.u32 	%rs101, %r434;
	st.global.v2.u8 	[%rd61], {%rs101, %rs100};

$L__BB0_167:
	and.b32  	%r435, %r23, 4;
	setp.eq.s32 	%p203, %r435, 0;
	ld.const.u32 	%r453, [params+108];
	@%p203 bra 	$L__BB0_171;

	setp.eq.s32 	%p204, %r453, 0;
	ld.const.u64 	%rd62, [params+224];
	cvta.to.global.u64 	%rd63, %rd62;
	ld.const.u32 	%r436, [params+216];
	mad.lo.s32 	%r437, %r436, %r4, %r3;
	mul.wide.u32 	%rd64, %r437, 8;
	add.s64 	%rd16, %rd63, %rd64;
	@%p204 bra 	$L__BB0_170;

	ld.global.v4.u16 	{%rs108, %rs109, %rs110, %rs111}, [%rd16];
	// begin inline asm
	{  cvt.f32.f16 %f1604, %rs108;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1605, %rs109;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1606, %rs110;}

	// end inline asm
	add.f32 	%f1607, %f1604, 0f00000000;
	add.f32 	%f1608, %f1605, 0f00000000;
	add.f32 	%f1609, %f1606, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1609;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1608;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs105, %f1607;}

	// end inline asm
	mov.u16 	%rs112, 0;
	st.global.v4.u16 	[%rd16], {%rs105, %rs106, %rs107, %rs112};
	bra.uni 	$L__BB0_171;

$L__BB0_5:
	ld.const.u64 	%rd24, [params+432];
	cvta.to.global.u64 	%rd25, %rd24;
	ld.const.u32 	%r38, [params+424];
	mad.lo.s32 	%r39, %r38, %r27, %r26;
	mul.wide.u32 	%rd26, %r39, 12;
	add.s64 	%rd27, %rd25, %rd26;
	ld.global.f32 	%f10, [%rd27];
	mul.f32 	%f345, %f10, 0f3456BF95;
	ld.global.f32 	%f11, [%rd27+4];
	mul.f32 	%f346, %f11, 0f3456BF95;
	ld.global.f32 	%f12, [%rd27+8];
	mul.f32 	%f347, %f12, 0f3456BF95;
	abs.f32 	%f348, %f1652;
	div.rn.f32 	%f349, %f345, %f348;
	abs.f32 	%f350, %f1653;
	div.rn.f32 	%f351, %f346, %f350;
	abs.f32 	%f352, %f1654;
	div.rn.f32 	%f353, %f347, %f352;
	abs.f32 	%f354, %f349;
	abs.f32 	%f355, %f351;
	abs.f32 	%f356, %f353;
	mov.f32 	%f357, 0f38D1B717;
	max.f32 	%f358, %f354, %f357;
	max.f32 	%f359, %f355, %f357;
	max.f32 	%f360, %f356, %f357;
	fma.rn.f32 	%f13, %f1652, %f358, %f10;
	fma.rn.f32 	%f14, %f1653, %f359, %f11;
	fma.rn.f32 	%f15, %f1654, %f360, %f12;
	cvt.rn.f32.u32 	%f16, %r26;
	cvt.rn.f32.u32 	%f17, %r27;
	ld.const.u32 	%r5, [params+600];
	setp.eq.s32 	%p18, %r5, 0;
	@%p18 bra 	$L__BB0_58;

	ld.const.u64 	%rd28, [params+608];
	cvta.to.global.u64 	%rd2, %rd28;
	mov.f32 	%f377, 0f40000000;
	cvt.rzi.f32.f32 	%f378, %f377;
	add.f32 	%f379, %f378, %f378;
	mov.f32 	%f380, 0f40800000;
	sub.f32 	%f381, %f380, %f379;
	abs.f32 	%f18, %f381;
	ld.const.u32 	%r6, [params+544];
	ld.const.u32 	%r451, [params+104];
	mul.f32 	%f19, %f13, 0f3456BF95;
	mul.f32 	%f20, %f14, 0f3456BF95;
	mul.f32 	%f21, %f15, 0f3456BF95;
	mov.f32 	%f376, 0f00000000;
	mov.u32 	%r447, 0;
	ld.const.u64 	%rd3, [params+96];
	abs.f32 	%f589, %f19;
	abs.f32 	%f590, %f20;
	max.f32 	%f591, %f589, %f590;
	abs.f32 	%f592, %f21;
	max.f32 	%f593, %f591, %f592;
	mov.f32 	%f1731, %f376;
	mov.f32 	%f1730, %f376;
	mov.f32 	%f1729, %f376;
	mov.f32 	%f1728, %f376;
	mov.f32 	%f1727, %f376;
	mov.f32 	%f1726, %f376;
	mov.f32 	%f1725, %f376;
	mov.f32 	%f1724, %f376;
	mov.f32 	%f1723, %f376;
	mov.f32 	%f1722, %f376;
	mov.f32 	%f1721, %f376;
	mov.f32 	%f1720, %f376;
	mov.f32 	%f1719, %f376;
	mov.f32 	%f1718, %f376;
	mov.f32 	%f1717, %f376;
	mov.f32 	%f1716, %f376;

$L__BB0_7:
	mul.wide.u32 	%rd29, %r447, 112;
	add.s64 	%rd5, %rd2, %rd29;
	ld.global.v4.f32 	{%f383, %f384, %f385, %f386}, [%rd5];
	ld.global.v4.f32 	{%f387, %f388, %f389, %f390}, [%rd5+16];
	ld.global.v4.f32 	{%f393, %f1679, %f1680, %f396}, [%rd5+32];
	ld.global.v4.f32 	{%f397, %f398, %f399, %f1677}, [%rd5+48];
	ld.global.v4.f32 	{%f401, %f402, %f403, %f404}, [%rd5+64];
	ld.global.v4.u32 	{%r41, %r42, %r43, %r44}, [%rd5+80];
	mov.b32 	%f57, %r43;
	mov.b32 	%f56, %r42;
	mov.b32 	%f55, %r41;
	ld.global.u64 	%rd6, [%rd5+96];
	sub.f32 	%f405, %f384, %f10;
	sub.f32 	%f406, %f385, %f11;
	sub.f32 	%f407, %f386, %f12;
	mul.f32 	%f408, %f406, %f406;
	fma.rn.f32 	%f409, %f405, %f405, %f408;
	fma.rn.f32 	%f410, %f407, %f407, %f409;
	sqrt.rn.f32 	%f411, %f410;
	rcp.rn.f32 	%f412, %f411;
	mul.f32 	%f59, %f405, %f412;
	mul.f32 	%f60, %f406, %f412;
	mul.f32 	%f61, %f407, %f412;
	mul.f32 	%f62, %f411, %f388;
	mul.f32 	%f63, %f411, %f390;
	abs.f32 	%f64, %f63;
	setp.lt.f32 	%p19, %f64, 0f00800000;
	mul.f32 	%f413, %f64, 0f4B800000;
	selp.f32 	%f414, %f413, %f64, %p19;
	selp.f32 	%f415, 0fC3170000, 0fC2FE0000, %p19;
	mov.b32 	%r48, %f414;
	and.b32  	%r49, %r48, 8388607;
	or.b32  	%r50, %r49, 1065353216;
	mov.b32 	%f416, %r50;
	shr.u32 	%r51, %r48, 23;
	cvt.rn.f32.u32 	%f417, %r51;
	add.f32 	%f418, %f415, %f417;
	setp.gt.f32 	%p20, %f416, 0f3FB504F3;
	mul.f32 	%f419, %f416, 0f3F000000;
	add.f32 	%f420, %f418, 0f3F800000;
	selp.f32 	%f421, %f420, %f418, %p20;
	selp.f32 	%f422, %f419, %f416, %p20;
	add.f32 	%f423, %f422, 0fBF800000;
	add.f32 	%f424, %f422, 0f3F800000;
	rcp.approx.ftz.f32 	%f425, %f424;
	add.f32 	%f426, %f423, %f423;
	mul.f32 	%f427, %f426, %f425;
	mul.f32 	%f428, %f427, %f427;
	mov.f32 	%f429, 0f3C4CAF63;
	mov.f32 	%f430, 0f3B18F0FE;
	fma.rn.f32 	%f431, %f430, %f428, %f429;
	mov.f32 	%f432, 0f3DAAAABD;
	fma.rn.f32 	%f433, %f431, %f428, %f432;
	mul.rn.f32 	%f434, %f433, %f428;
	mul.rn.f32 	%f435, %f434, %f427;
	sub.f32 	%f436, %f423, %f427;
	add.f32 	%f437, %f436, %f436;
	neg.f32 	%f438, %f427;
	fma.rn.f32 	%f439, %f438, %f423, %f437;
	mul.rn.f32 	%f440, %f425, %f439;
	add.f32 	%f441, %f435, %f427;
	sub.f32 	%f442, %f427, %f441;
	add.f32 	%f443, %f435, %f442;
	add.f32 	%f444, %f440, %f443;
	add.f32 	%f445, %f441, %f444;
	sub.f32 	%f446, %f441, %f445;
	add.f32 	%f447, %f444, %f446;
	mov.f32 	%f448, 0f3F317200;
	mul.rn.f32 	%f449, %f421, %f448;
	mov.f32 	%f450, 0f35BFBE8E;
	mul.rn.f32 	%f451, %f421, %f450;
	add.f32 	%f452, %f449, %f445;
	sub.f32 	%f453, %f449, %f452;
	add.f32 	%f454, %f445, %f453;
	add.f32 	%f455, %f447, %f454;
	add.f32 	%f456, %f451, %f455;
	add.f32 	%f457, %f452, %f456;
	sub.f32 	%f458, %f452, %f457;
	add.f32 	%f459, %f456, %f458;
	mul.rn.f32 	%f461, %f380, %f457;
	neg.f32 	%f462, %f461;
	fma.rn.f32 	%f463, %f380, %f457, %f462;
	fma.rn.f32 	%f464, %f380, %f459, %f463;
	fma.rn.f32 	%f466, %f376, %f457, %f464;
	add.rn.f32 	%f467, %f461, %f466;
	neg.f32 	%f468, %f467;
	add.rn.f32 	%f469, %f461, %f468;
	add.rn.f32 	%f470, %f469, %f466;
	mov.b32 	%r52, %f467;
	setp.eq.s32 	%p21, %r52, 1118925336;
	add.s32 	%r53, %r52, -1;
	mov.b32 	%f471, %r53;
	add.f32 	%f472, %f470, 0f37000000;
	selp.f32 	%f65, %f472, %f470, %p21;
	selp.f32 	%f473, %f471, %f467, %p21;
	mov.f32 	%f474, 0f3FB8AA3B;
	mul.rn.f32 	%f475, %f473, %f474;
	cvt.rzi.f32.f32 	%f476, %f475;
	abs.f32 	%f477, %f476;
	setp.gt.f32 	%p22, %f477, 0f42FC0000;
	mov.b32 	%r54, %f476;
	and.b32  	%r55, %r54, -2147483648;
	or.b32  	%r56, %r55, 1123811328;
	mov.b32 	%f478, %r56;
	selp.f32 	%f479, %f478, %f476, %p22;
	mov.f32 	%f480, 0fBF317218;
	fma.rn.f32 	%f481, %f479, %f480, %f473;
	mov.f32 	%f482, 0f3102E308;
	fma.rn.f32 	%f483, %f479, %f482, %f481;
	mul.f32 	%f484, %f483, 0f3FB8AA3B;
	add.f32 	%f485, %f479, 0f4B40007F;
	mov.b32 	%r57, %f485;
	shl.b32 	%r58, %r57, 23;
	mov.b32 	%f486, %r58;
	ex2.approx.ftz.f32 	%f487, %f484;
	mul.f32 	%f66, %f487, %f486;
	setp.eq.f32 	%p23, %f66, 0f7F800000;
	mov.f32 	%f1671, 0f7F800000;
	@%p23 bra 	$L__BB0_9;

	fma.rn.f32 	%f1671, %f66, %f65, %f66;

$L__BB0_9:
	setp.lt.f32 	%p24, %f63, 0f00000000;
	setp.eq.f32 	%p25, %f18, 0f3F800000;
	and.pred  	%p1, %p24, %p25;
	setp.eq.f32 	%p26, %f63, 0f00000000;
	@%p26 bra 	$L__BB0_13;
	bra.uni 	$L__BB0_10;

$L__BB0_13:
	add.f32 	%f492, %f63, %f63;
	selp.f32 	%f1673, %f492, 0f00000000, %p25;
	bra.uni 	$L__BB0_14;

$L__BB0_10:
	mov.b32 	%r59, %f1671;
	xor.b32  	%r60, %r59, -2147483648;
	mov.b32 	%f488, %r60;
	selp.f32 	%f1673, %f488, %f1671, %p1;
	setp.geu.f32 	%p27, %f63, 0f00000000;
	@%p27 bra 	$L__BB0_14;

	mov.f32 	%f489, 0f40800000;
	cvt.rzi.f32.f32 	%f490, %f489;
	setp.eq.f32 	%p28, %f490, 0f40800000;
	@%p28 bra 	$L__BB0_14;

	mov.f32 	%f1673, 0f7FFFFFFF;

$L__BB0_14:
	abs.f32 	%f1649, %f63;
	add.f32 	%f493, %f1649, 0f40800000;
	mov.b32 	%r61, %f493;
	setp.lt.s32 	%p30, %r61, 2139095040;
	@%p30 bra 	$L__BB0_19;

	abs.f32 	%f1650, %f63;
	setp.gtu.f32 	%p31, %f1650, 0f7F800000;
	@%p31 bra 	$L__BB0_18;
	bra.uni 	$L__BB0_16;

$L__BB0_18:
	add.f32 	%f1673, %f63, 0f40800000;
	bra.uni 	$L__BB0_19;

$L__BB0_16:
	abs.f32 	%f1651, %f63;
	setp.neu.f32 	%p32, %f1651, 0f7F800000;
	@%p32 bra 	$L__BB0_19;

	selp.f32 	%f1673, 0fFF800000, 0f7F800000, %p1;

$L__BB0_19:
	mov.f32 	%f494, 0f3F800000;
	sub.f32 	%f495, %f494, %f1673;
	setp.eq.f32 	%p33, %f63, 0f3F800000;
	selp.f32 	%f496, 0f00000000, %f495, %p33;
	cvt.sat.f32.f32 	%f497, %f496;
	fma.rn.f32 	%f498, %f62, %f62, %f389;
	div.rn.f32 	%f75, %f497, %f498;
	mul.f32 	%f499, %f1653, %f60;
	fma.rn.f32 	%f500, %f1652, %f59, %f499;
	fma.rn.f32 	%f501, %f1654, %f61, %f500;
	setp.eq.s32 	%p34, %r6, 0;
	selp.f32 	%f76, %f501, 0f3F800000, %p34;
	mul.f32 	%f502, %f76, 0f40800000;
	cvt.sat.f32.f32 	%f77, %f502;
	setp.eq.f32 	%p35, %f383, 0f3F800000;
	@%p35 bra 	$L__BB0_25;
	bra.uni 	$L__BB0_20;

$L__BB0_25:
	setp.eq.s64 	%p39, %rd6, 0;
	mov.f32 	%f1678, %f393;
	mov.f32 	%f1681, %f75;
	@%p39 bra 	$L__BB0_29;

	setp.geu.f32 	%p40, %f1677, 0f00000000;
	mov.f32 	%f1674, %f59;
	mov.f32 	%f1675, %f60;
	mov.f32 	%f1676, %f61;
	@%p40 bra 	$L__BB0_28;

	mul.f32 	%f527, %f56, %f406;
	fma.rn.f32 	%f528, %f55, %f405, %f527;
	fma.rn.f32 	%f530, %f57, %f407, %f528;
	rcp.rn.f32 	%f531, %f530;
	mul.f32 	%f1674, %f405, %f531;
	mul.f32 	%f1675, %f406, %f531;
	mul.f32 	%f1676, %f407, %f531;
	neg.f32 	%f1677, %f1677;

$L__BB0_28:
	mul.f32 	%f532, %f57, %f61;
	mul.f32 	%f533, %f56, %f60;
	neg.f32 	%f534, %f533;
	mul.f32 	%f535, %f55, %f59;
	sub.f32 	%f536, %f534, %f535;
	sub.f32 	%f537, %f536, %f532;
	setp.gt.f32 	%p41, %f537, 0f00000000;
	selp.f32 	%f538, 0f3F800000, 0f00000000, %p41;
	mov.f32 	%f539, 0f3F800000;
	mul.f32 	%f540, %f398, %f1675;
	mul.f32 	%f541, %f402, %f1675;
	fma.rn.f32 	%f542, %f397, %f1674, %f540;
	fma.rn.f32 	%f543, %f401, %f1674, %f541;
	fma.rn.f32 	%f544, %f399, %f1676, %f542;
	fma.rn.f32 	%f545, %f403, %f1676, %f543;
	fma.rn.f32 	%f546, %f1677, %f544, 0f3F000000;
	sub.f32 	%f547, %f539, %f546;
	fma.rn.f32 	%f548, %f1677, %f545, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f549, %f550, %f551, %f552}, [%rd6, {%f547, %f548}];
	mul.f32 	%f553, %f538, %f549;
	mul.f32 	%f554, %f538, %f550;
	mul.f32 	%f555, %f538, %f551;
	mul.f32 	%f1678, %f393, %f553;
	mul.f32 	%f1679, %f1679, %f554;
	mul.f32 	%f1680, %f1680, %f555;
	mov.f32 	%f1681, %f75;
	bra.uni 	$L__BB0_29;

$L__BB0_20:
	setp.eq.f32 	%p36, %f383, 0f40000000;
	@%p36 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_21;

$L__BB0_23:
	setp.eq.s64 	%p38, %rd6, 0;
	mov.f32 	%f1678, %f393;
	mov.f32 	%f1681, %f75;
	@%p38 bra 	$L__BB0_29;

	mul.f32 	%f512, %f398, %f60;
	mul.f32 	%f513, %f402, %f60;
	mul.f32 	%f514, %f56, %f60;
	fma.rn.f32 	%f515, %f397, %f59, %f512;
	fma.rn.f32 	%f516, %f401, %f59, %f513;
	fma.rn.f32 	%f517, %f55, %f59, %f514;
	fma.rn.f32 	%f518, %f399, %f61, %f515;
	fma.rn.f32 	%f519, %f403, %f61, %f516;
	fma.rn.f32 	%f520, %f57, %f61, %f517;
	tex.cube.v4.f32.f32 	{%f521, %f522, %f523, %f524}, [%rd6, {%f518, %f519, %f520, %f520}];
	mul.f32 	%f1678, %f393, %f521;
	mul.f32 	%f1679, %f1679, %f522;
	mul.f32 	%f1680, %f1680, %f523;
	mov.f32 	%f1681, %f75;
	bra.uni 	$L__BB0_29;

$L__BB0_21:
	setp.neu.f32 	%p37, %f383, 0f40800000;
	mov.f32 	%f1678, %f393;
	mov.f32 	%f1681, %f75;
	@%p37 bra 	$L__BB0_29;

	mul.f32 	%f503, %f55, %f59;
	mul.f32 	%f504, %f56, %f60;
	neg.f32 	%f505, %f504;
	sub.f32 	%f506, %f505, %f503;
	mul.f32 	%f507, %f57, %f61;
	sub.f32 	%f508, %f506, %f507;
	fma.rn.f32 	%f509, %f396, %f508, %f1677;
	cvt.sat.f32.f32 	%f510, %f509;
	mul.f32 	%f511, %f510, %f510;
	mul.f32 	%f1681, %f75, %f511;
	mov.f32 	%f1678, %f393;

$L__BB0_29:
	max.f32 	%f571, %f1678, %f1679;
	max.f32 	%f572, %f571, %f1680;
	mul.f32 	%f573, %f77, %f1681;
	mul.f32 	%f574, %f573, %f572;
	setp.lt.f32 	%p43, %f574, 0f3727C5AC;
	mov.pred 	%p209, -1;
	mov.f32 	%f1682, 0f00000000;
	mov.f32 	%f1683, %f1682;
	mov.f32 	%f1684, %f1682;
	mov.f32 	%f1685, %f1682;
	mov.f32 	%f1686, %f1682;
	mov.f32 	%f1687, %f1682;
	mov.f32 	%f1688, %f1682;
	mov.f32 	%f1689, %f1682;
	mov.f32 	%f1690, %f1682;
	mov.f32 	%f1691, %f1682;
	mov.f32 	%f1692, %f1682;
	mov.f32 	%f1693, %f1682;
	mov.f32 	%f1694, %f1682;
	mov.f32 	%f1695, %f1682;
	mov.f32 	%f1696, %f1682;
	@%p43 bra 	$L__BB0_31;

	cvt.sat.f32.f32 	%f575, %f76;
	mul.f32 	%f576, %f1681, %f575;
	mul.f32 	%f1682, %f1678, %f576;
	mul.f32 	%f1683, %f1679, %f576;
	mul.f32 	%f1684, %f1680, %f576;
	mul.f32 	%f577, %f1681, 0f3E800000;
	mul.f32 	%f578, %f77, %f577;
	mul.f32 	%f1685, %f1678, %f578;
	mul.f32 	%f1686, %f1679, %f578;
	mul.f32 	%f1687, %f1680, %f578;
	mul.f32 	%f1688, %f59, %f1685;
	mul.f32 	%f1689, %f59, %f1686;
	mul.f32 	%f1690, %f59, %f1687;
	mul.f32 	%f1691, %f60, %f1685;
	mul.f32 	%f1692, %f60, %f1686;
	mul.f32 	%f1693, %f60, %f1687;
	mul.f32 	%f1694, %f61, %f1685;
	mul.f32 	%f1695, %f61, %f1686;
	mul.f32 	%f1696, %f61, %f1687;
	mov.pred 	%p209, 0;

$L__BB0_31:
	@%p209 bra 	$L__BB0_57;

	setp.eq.s32 	%p45, %r44, 0;
	mov.u16 	%rs179, 0;
	mov.f32 	%f1715, 0f3F800000;
	mov.f32 	%f1710, %f1715;
	mov.f32 	%f1711, %f1715;
	@%p45 bra 	$L__BB0_40;

	abs.s32 	%r10, %r44;
	setp.lt.s32 	%p46, %r10, 1;
	mov.f32 	%f1700, 0f00000000;
	mov.f32 	%f1701, %f1700;
	mov.f32 	%f1702, %f1700;
	@%p46 bra 	$L__BB0_39;

	mov.f32 	%f594, 0f38D1B717;
	max.f32 	%f595, %f593, %f594;
	and.b32  	%r63, %r451, 32;
	setp.eq.s32 	%p47, %r63, 0;
	mov.u32 	%r450, 0;
	selp.f32 	%f596, 0f3F800000, 0f41200000, %p47;
	mul.f32 	%f140, %f596, %f595;
	and.b32  	%r11, %r10, 1;
	setp.eq.s32 	%p48, %r10, 1;
	mov.f32 	%f1702, 0f00000000;
	mov.f32 	%f1701, %f1702;
	mov.f32 	%f1700, %f1702;
	@%p48 bra 	$L__BB0_37;

	sub.s32 	%r449, %r10, %r11;

$L__BB0_36:
	cvt.rn.f32.s32 	%f618, %r450;
	add.f32 	%f619, %f16, %f618;
	sub.f32 	%f620, %f17, %f618;
	mul.f32 	%f621, %f619, 0f3DD32618;
	cvt.rmi.f32.f32 	%f622, %f621;
	sub.f32 	%f623, %f621, %f622;
	mul.f32 	%f624, %f620, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f625, %f624;
	sub.f32 	%f626, %f624, %f625;
	mul.f32 	%f627, %f618, 0f3DC74539;
	cvt.rmi.f32.f32 	%f628, %f627;
	sub.f32 	%f629, %f627, %f628;
	add.f32 	%f630, %f626, 0f420551EC;
	add.f32 	%f631, %f623, 0f420551EC;
	add.f32 	%f632, %f629, 0f420551EC;
	mul.f32 	%f633, %f623, %f630;
	fma.rn.f32 	%f634, %f626, %f631, %f633;
	fma.rn.f32 	%f635, %f629, %f632, %f634;
	add.f32 	%f636, %f623, %f635;
	add.f32 	%f637, %f626, %f635;
	add.f32 	%f638, %f629, %f635;
	add.f32 	%f639, %f636, %f637;
	mul.f32 	%f640, %f638, %f639;
	cvt.rmi.f32.f32 	%f641, %f640;
	sub.f32 	%f642, %f640, %f641;
	add.f32 	%f643, %f636, %f636;
	mul.f32 	%f644, %f637, %f643;
	cvt.rmi.f32.f32 	%f645, %f644;
	sub.f32 	%f646, %f644, %f645;
	mul.f32 	%f647, %f636, %f639;
	cvt.rmi.f32.f32 	%f648, %f647;
	sub.f32 	%f649, %f647, %f648;
	fma.rn.f32 	%f650, %f642, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f651, %f646, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f652, %f649, 0f40000000, 0fBF800000;
	ld.global.f32 	%f653, [%rd5+16];
	ld.global.f32 	%f654, [%rd5+4];
	fma.rn.f32 	%f655, %f653, %f650, %f654;
	ld.global.f32 	%f656, [%rd5+8];
	fma.rn.f32 	%f657, %f653, %f651, %f656;
	ld.global.f32 	%f658, [%rd5+12];
	fma.rn.f32 	%f659, %f653, %f652, %f658;
	sub.f32 	%f660, %f655, %f10;
	sub.f32 	%f661, %f657, %f11;
	sub.f32 	%f662, %f659, %f12;
	mul.f32 	%f663, %f661, %f661;
	fma.rn.f32 	%f664, %f660, %f660, %f663;
	fma.rn.f32 	%f665, %f662, %f662, %f664;
	sqrt.rn.f32 	%f607, %f665;
	rcp.rn.f32 	%f666, %f607;
	mul.f32 	%f603, %f666, %f660;
	mul.f32 	%f604, %f666, %f661;
	mul.f32 	%f605, %f666, %f662;
	mov.f32 	%f617, 0f00000000;
	mov.u32 	%r172, 2;
	mov.u32 	%r173, 1;
	mov.u32 	%r174, 3;
	mov.u32 	%r177, 1065353216;
	mov.u32 	%r206, 0;
	// begin inline asm
	call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f603,%f604,%f605,%f140,%f607,%f617,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f667, %r65;
	mov.b32 	%f668, %r66;
	mov.b32 	%f669, %r67;
	add.f32 	%f670, %f1700, %f667;
	add.f32 	%f671, %f1701, %f668;
	add.f32 	%f672, %f1702, %f669;
	add.s32 	%r207, %r450, 1;
	cvt.rn.f32.s32 	%f673, %r207;
	add.f32 	%f674, %f16, %f673;
	sub.f32 	%f675, %f17, %f673;
	mul.f32 	%f676, %f674, 0f3DD32618;
	cvt.rmi.f32.f32 	%f677, %f676;
	sub.f32 	%f678, %f676, %f677;
	mul.f32 	%f679, %f675, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f680, %f679;
	sub.f32 	%f681, %f679, %f680;
	mul.f32 	%f682, %f673, 0f3DC74539;
	cvt.rmi.f32.f32 	%f683, %f682;
	sub.f32 	%f684, %f682, %f683;
	add.f32 	%f685, %f681, 0f420551EC;
	add.f32 	%f686, %f678, 0f420551EC;
	add.f32 	%f687, %f684, 0f420551EC;
	mul.f32 	%f688, %f678, %f685;
	fma.rn.f32 	%f689, %f681, %f686, %f688;
	fma.rn.f32 	%f690, %f684, %f687, %f689;
	add.f32 	%f691, %f678, %f690;
	add.f32 	%f692, %f681, %f690;
	add.f32 	%f693, %f684, %f690;
	add.f32 	%f694, %f691, %f692;
	mul.f32 	%f695, %f693, %f694;
	cvt.rmi.f32.f32 	%f696, %f695;
	sub.f32 	%f697, %f695, %f696;
	add.f32 	%f698, %f691, %f691;
	mul.f32 	%f699, %f692, %f698;
	cvt.rmi.f32.f32 	%f700, %f699;
	sub.f32 	%f701, %f699, %f700;
	mul.f32 	%f702, %f691, %f694;
	cvt.rmi.f32.f32 	%f703, %f702;
	sub.f32 	%f704, %f702, %f703;
	fma.rn.f32 	%f705, %f697, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f706, %f701, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f707, %f704, 0f40000000, 0fBF800000;
	ld.global.f32 	%f708, [%rd5+16];
	ld.global.f32 	%f709, [%rd5+4];
	fma.rn.f32 	%f710, %f708, %f705, %f709;
	ld.global.f32 	%f711, [%rd5+8];
	fma.rn.f32 	%f712, %f708, %f706, %f711;
	ld.global.f32 	%f713, [%rd5+12];
	fma.rn.f32 	%f714, %f708, %f707, %f713;
	sub.f32 	%f715, %f710, %f10;
	sub.f32 	%f716, %f712, %f11;
	sub.f32 	%f717, %f714, %f12;
	mul.f32 	%f718, %f716, %f716;
	fma.rn.f32 	%f719, %f715, %f715, %f718;
	fma.rn.f32 	%f720, %f717, %f717, %f719;
	sqrt.rn.f32 	%f616, %f720;
	rcp.rn.f32 	%f721, %f616;
	mul.f32 	%f612, %f721, %f715;
	mul.f32 	%f613, %f721, %f716;
	mul.f32 	%f614, %f721, %f717;
	// begin inline asm
	call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f612,%f613,%f614,%f140,%f616,%f617,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
	// end inline asm
	mov.b32 	%f722, %r136;
	mov.b32 	%f723, %r137;
	mov.b32 	%f724, %r138;
	add.f32 	%f1700, %f670, %f722;
	add.f32 	%f1701, %f671, %f723;
	add.f32 	%f1702, %f672, %f724;
	add.s32 	%r450, %r450, 2;
	add.s32 	%r449, %r449, -2;
	setp.ne.s32 	%p49, %r449, 0;
	@%p49 bra 	$L__BB0_36;

$L__BB0_37:
	setp.eq.s32 	%p50, %r11, 0;
	@%p50 bra 	$L__BB0_39;

	cvt.rn.f32.s32 	%f734, %r450;
	add.f32 	%f735, %f16, %f734;
	sub.f32 	%f736, %f17, %f734;
	mul.f32 	%f737, %f735, 0f3DD32618;
	cvt.rmi.f32.f32 	%f738, %f737;
	sub.f32 	%f739, %f737, %f738;
	mul.f32 	%f740, %f736, 0f3DD2F1AA;
	cvt.rmi.f32.f32 	%f741, %f740;
	sub.f32 	%f742, %f740, %f741;
	mul.f32 	%f743, %f734, 0f3DC74539;
	cvt.rmi.f32.f32 	%f744, %f743;
	sub.f32 	%f745, %f743, %f744;
	add.f32 	%f746, %f742, 0f420551EC;
	add.f32 	%f747, %f739, 0f420551EC;
	add.f32 	%f748, %f745, 0f420551EC;
	mul.f32 	%f749, %f739, %f746;
	fma.rn.f32 	%f750, %f742, %f747, %f749;
	fma.rn.f32 	%f751, %f745, %f748, %f750;
	add.f32 	%f752, %f739, %f751;
	add.f32 	%f753, %f742, %f751;
	add.f32 	%f754, %f745, %f751;
	add.f32 	%f755, %f752, %f753;
	mul.f32 	%f756, %f754, %f755;
	cvt.rmi.f32.f32 	%f757, %f756;
	sub.f32 	%f758, %f756, %f757;
	add.f32 	%f759, %f752, %f752;
	mul.f32 	%f760, %f753, %f759;
	cvt.rmi.f32.f32 	%f761, %f760;
	sub.f32 	%f762, %f760, %f761;
	mul.f32 	%f763, %f752, %f755;
	cvt.rmi.f32.f32 	%f764, %f763;
	sub.f32 	%f765, %f763, %f764;
	fma.rn.f32 	%f766, %f758, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f767, %f762, 0f40000000, 0fBF800000;
	fma.rn.f32 	%f768, %f765, 0f40000000, 0fBF800000;
	ld.global.f32 	%f769, [%rd5+16];
	ld.global.f32 	%f770, [%rd5+4];
	fma.rn.f32 	%f771, %f769, %f766, %f770;
	ld.global.f32 	%f772, [%rd5+8];
	fma.rn.f32 	%f773, %f769, %f767, %f772;
	ld.global.f32 	%f774, [%rd5+12];
	fma.rn.f32 	%f775, %f769, %f768, %f774;
	sub.f32 	%f776, %f771, %f10;
	sub.f32 	%f777, %f773, %f11;
	sub.f32 	%f778, %f775, %f12;
	mul.f32 	%f779, %f777, %f777;
	fma.rn.f32 	%f780, %f776, %f776, %f779;
	fma.rn.f32 	%f781, %f778, %f778, %f780;
	sqrt.rn.f32 	%f732, %f781;
	rcp.rn.f32 	%f782, %f732;
	mul.f32 	%f728, %f782, %f776;
	mul.f32 	%f729, %f782, %f777;
	mul.f32 	%f730, %f782, %f778;
	mov.f32 	%f733, 0f00000000;
	mov.u32 	%r244, 2;
	mov.u32 	%r245, 1;
	mov.u32 	%r246, 3;
	mov.u32 	%r249, 1065353216;
	mov.u32 	%r278, 0;
	// begin inline asm
	call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f728,%f729,%f730,%f140,%f732,%f733,%r245,%r278,%r245,%r244,%r245,%r246,%r249,%r249,%r249,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
	// end inline asm
	mov.b32 	%f783, %r208;
	mov.b32 	%f784, %r209;
	mov.b32 	%f785, %r210;
	add.f32 	%f1700, %f1700, %f783;
	add.f32 	%f1701, %f1701, %f784;
	add.f32 	%f1702, %f1702, %f785;

$L__BB0_39:
	cvt.rn.f32.s32 	%f786, %r10;
	rcp.rn.f32 	%f787, %f786;
	mul.f32 	%f1715, %f787, %f1700;
	mul.f32 	%f1710, %f787, %f1701;
	mul.f32 	%f1711, %f787, %f1702;
	shr.u32 	%r279, %r44, 31;
	cvt.u16.u32 	%rs179, %r279;

$L__BB0_40:
	fma.rn.f32 	%f1716, %f1682, %f1715, %f1716;
	fma.rn.f32 	%f1717, %f1683, %f1710, %f1717;
	fma.rn.f32 	%f1718, %f1684, %f1711, %f1718;
	fma.rn.f32 	%f1719, %f1685, %f1715, %f1719;
	fma.rn.f32 	%f1720, %f1686, %f1710, %f1720;
	fma.rn.f32 	%f1721, %f1687, %f1711, %f1721;
	fma.rn.f32 	%f1722, %f1688, %f1715, %f1722;
	fma.rn.f32 	%f1723, %f1689, %f1710, %f1723;
	fma.rn.f32 	%f1724, %f1690, %f1711, %f1724;
	fma.rn.f32 	%f1725, %f1691, %f1715, %f1725;
	fma.rn.f32 	%f1726, %f1692, %f1710, %f1726;
	fma.rn.f32 	%f1727, %f1693, %f1711, %f1727;
	fma.rn.f32 	%f1728, %f1694, %f1715, %f1728;
	fma.rn.f32 	%f1729, %f1695, %f1710, %f1729;
	fma.rn.f32 	%f1730, %f1696, %f1711, %f1730;
	setp.eq.s16 	%p51, %rs179, 0;
	@%p51 bra 	$L__BB0_56;

	mul.f32 	%f789, %f1688, 0f3F000000;
	mul.f32 	%f790, %f1691, 0f3F000000;
	mul.f32 	%f791, %f790, %f790;
	fma.rn.f32 	%f792, %f789, %f789, %f791;
	mul.f32 	%f793, %f1694, 0f3F000000;
	fma.rn.f32 	%f794, %f793, %f793, %f792;
	sqrt.rn.f32 	%f795, %f794;
	rcp.rn.f32 	%f796, %f795;
	mov.f32 	%f797, 0f3F800000;
	mul.f32 	%f798, %f789, %f796;
	mul.f32 	%f799, %f790, %f796;
	mul.f32 	%f800, %f793, %f796;
	mul.f32 	%f801, %f1653, %f799;
	fma.rn.f32 	%f802, %f1652, %f798, %f801;
	fma.rn.f32 	%f803, %f1654, %f800, %f802;
	fma.rn.f32 	%f180, %f803, 0f3F000000, 0f3F000000;
	add.f32 	%f804, %f795, %f795;
	div.rn.f32 	%f805, %f804, %f1685;
	add.f32 	%f181, %f805, 0f3F800000;
	div.rn.f32 	%f806, %f795, %f1685;
	sub.f32 	%f807, %f797, %f806;
	add.f32 	%f808, %f806, 0f3F800000;
	div.rn.f32 	%f182, %f807, %f808;
	sub.f32 	%f809, %f797, %f182;
	add.f32 	%f810, %f181, 0f3F800000;
	mul.f32 	%f183, %f809, %f810;
	mul.f32 	%f811, %f181, 0f3F000000;
	cvt.rzi.f32.f32 	%f812, %f811;
	add.f32 	%f813, %f812, %f812;
	sub.f32 	%f814, %f181, %f813;
	abs.f32 	%f184, %f814;
	abs.f32 	%f185, %f180;
	setp.lt.f32 	%p52, %f185, 0f00800000;
	mul.f32 	%f815, %f185, 0f4B800000;
	selp.f32 	%f816, %f815, %f185, %p52;
	selp.f32 	%f817, 0fC3170000, 0fC2FE0000, %p52;
	mov.b32 	%r280, %f816;
	and.b32  	%r281, %r280, 8388607;
	or.b32  	%r282, %r281, 1065353216;
	mov.b32 	%f818, %r282;
	shr.u32 	%r283, %r280, 23;
	cvt.rn.f32.u32 	%f819, %r283;
	add.f32 	%f820, %f817, %f819;
	setp.gt.f32 	%p53, %f818, 0f3FB504F3;
	mul.f32 	%f821, %f818, 0f3F000000;
	add.f32 	%f822, %f820, 0f3F800000;
	selp.f32 	%f823, %f822, %f820, %p53;
	selp.f32 	%f824, %f821, %f818, %p53;
	add.f32 	%f825, %f824, 0fBF800000;
	add.f32 	%f826, %f824, 0f3F800000;
	rcp.approx.ftz.f32 	%f827, %f826;
	add.f32 	%f828, %f825, %f825;
	mul.f32 	%f829, %f828, %f827;
	mul.f32 	%f830, %f829, %f829;
	mov.f32 	%f831, 0f3C4CAF63;
	mov.f32 	%f832, 0f3B18F0FE;
	fma.rn.f32 	%f833, %f832, %f830, %f831;
	mov.f32 	%f834, 0f3DAAAABD;
	fma.rn.f32 	%f835, %f833, %f830, %f834;
	mul.rn.f32 	%f836, %f835, %f830;
	mul.rn.f32 	%f837, %f836, %f829;
	sub.f32 	%f838, %f825, %f829;
	add.f32 	%f839, %f838, %f838;
	neg.f32 	%f840, %f829;
	fma.rn.f32 	%f841, %f840, %f825, %f839;
	mul.rn.f32 	%f842, %f827, %f841;
	add.f32 	%f843, %f837, %f829;
	sub.f32 	%f844, %f829, %f843;
	add.f32 	%f845, %f837, %f844;
	add.f32 	%f846, %f842, %f845;
	add.f32 	%f847, %f843, %f846;
	sub.f32 	%f848, %f843, %f847;
	add.f32 	%f849, %f846, %f848;
	mov.f32 	%f850, 0f3F317200;
	mul.rn.f32 	%f851, %f823, %f850;
	mov.f32 	%f852, 0f35BFBE8E;
	mul.rn.f32 	%f853, %f823, %f852;
	add.f32 	%f854, %f851, %f847;
	sub.f32 	%f855, %f851, %f854;
	add.f32 	%f856, %f847, %f855;
	add.f32 	%f857, %f849, %f856;
	add.f32 	%f858, %f853, %f857;
	add.f32 	%f859, %f854, %f858;
	sub.f32 	%f860, %f854, %f859;
	add.f32 	%f861, %f858, %f860;
	abs.f32 	%f186, %f181;
	setp.gt.f32 	%p54, %f186, 0f77F684DF;
	mul.f32 	%f862, %f181, 0f39000000;
	selp.f32 	%f863, %f862, %f181, %p54;
	mul.rn.f32 	%f864, %f863, %f859;
	neg.f32 	%f865, %f864;
	fma.rn.f32 	%f866, %f863, %f859, %f865;
	fma.rn.f32 	%f867, %f863, %f861, %f866;
	mov.f32 	%f868, 0f00000000;
	fma.rn.f32 	%f869, %f868, %f859, %f867;
	add.rn.f32 	%f870, %f864, %f869;
	neg.f32 	%f871, %f870;
	add.rn.f32 	%f872, %f864, %f871;
	add.rn.f32 	%f873, %f872, %f869;
	mov.b32 	%r284, %f870;
	setp.eq.s32 	%p55, %r284, 1118925336;
	add.s32 	%r285, %r284, -1;
	mov.b32 	%f874, %r285;
	add.f32 	%f875, %f873, 0f37000000;
	selp.f32 	%f187, %f875, %f873, %p55;
	selp.f32 	%f876, %f874, %f870, %p55;
	mov.f32 	%f877, 0f3FB8AA3B;
	mul.rn.f32 	%f878, %f876, %f877;
	cvt.rzi.f32.f32 	%f879, %f878;
	abs.f32 	%f880, %f879;
	setp.gt.f32 	%p56, %f880, 0f42FC0000;
	mov.b32 	%r286, %f879;
	and.b32  	%r287, %r286, -2147483648;
	or.b32  	%r288, %r287, 1123811328;
	mov.b32 	%f881, %r288;
	selp.f32 	%f882, %f881, %f879, %p56;
	mov.f32 	%f883, 0fBF317218;
	fma.rn.f32 	%f884, %f882, %f883, %f876;
	mov.f32 	%f885, 0f3102E308;
	fma.rn.f32 	%f886, %f882, %f885, %f884;
	mul.f32 	%f887, %f886, 0f3FB8AA3B;
	add.f32 	%f888, %f882, 0f4B40007F;
	mov.b32 	%r289, %f888;
	shl.b32 	%r290, %r289, 23;
	mov.b32 	%f889, %r290;
	ex2.approx.ftz.f32 	%f890, %f887;
	mul.f32 	%f188, %f890, %f889;
	setp.eq.f32 	%p57, %f188, 0f7F800000;
	mov.f32 	%f1712, 0f7F800000;
	@%p57 bra 	$L__BB0_43;

	fma.rn.f32 	%f1712, %f188, %f187, %f188;

$L__BB0_43:
	setp.lt.f32 	%p58, %f180, 0f00000000;
	setp.eq.f32 	%p59, %f184, 0f3F800000;
	and.pred  	%p3, %p59, %p58;
	setp.eq.f32 	%p60, %f180, 0f00000000;
	@%p60 bra 	$L__BB0_47;
	bra.uni 	$L__BB0_44;

$L__BB0_47:
	add.f32 	%f894, %f180, %f180;
	mov.b32 	%r293, %f894;
	selp.b32 	%r294, %r293, 0, %p59;
	or.b32  	%r295, %r294, 2139095040;
	setp.lt.f32 	%p64, %f181, 0f00000000;
	selp.b32 	%r296, %r295, %r294, %p64;
	mov.b32 	%f1714, %r296;
	bra.uni 	$L__BB0_48;

$L__BB0_44:
	mov.b32 	%r291, %f1712;
	xor.b32  	%r292, %r291, -2147483648;
	mov.b32 	%f891, %r292;
	selp.f32 	%f1714, %f891, %f1712, %p3;
	setp.geu.f32 	%p61, %f180, 0f00000000;
	@%p61 bra 	$L__BB0_48;

	cvt.rzi.f32.f32 	%f892, %f181;
	setp.eq.f32 	%p62, %f892, %f181;
	@%p62 bra 	$L__BB0_48;

	mov.f32 	%f1714, 0f7FFFFFFF;

$L__BB0_48:
	add.f32 	%f895, %f185, %f186;
	mov.b32 	%r297, %f895;
	setp.lt.s32 	%p65, %r297, 2139095040;
	@%p65 bra 	$L__BB0_55;

	setp.gtu.f32 	%p66, %f185, 0f7F800000;
	setp.gtu.f32 	%p67, %f186, 0f7F800000;
	or.pred  	%p68, %p66, %p67;
	@%p68 bra 	$L__BB0_54;
	bra.uni 	$L__BB0_50;

$L__BB0_54:
	add.f32 	%f1714, %f181, %f180;
	bra.uni 	$L__BB0_55;

$L__BB0_50:
	setp.eq.f32 	%p69, %f186, 0f7F800000;
	@%p69 bra 	$L__BB0_53;
	bra.uni 	$L__BB0_51;

$L__BB0_53:
	setp.gt.f32 	%p72, %f185, 0f3F800000;
	selp.b32 	%r301, 2139095040, 0, %p72;
	xor.b32  	%r302, %r301, 2139095040;
	setp.lt.f32 	%p73, %f181, 0f00000000;
	selp.b32 	%r303, %r302, %r301, %p73;
	mov.b32 	%f896, %r303;
	setp.eq.f32 	%p74, %f180, 0fBF800000;
	selp.f32 	%f1714, 0f3F800000, %f896, %p74;
	bra.uni 	$L__BB0_55;

$L__BB0_51:
	setp.neu.f32 	%p70, %f185, 0f7F800000;
	@%p70 bra 	$L__BB0_55;

	setp.ge.f32 	%p71, %f181, 0f00000000;
	selp.b32 	%r298, 2139095040, 0, %p71;
	or.b32  	%r299, %r298, -2147483648;
	selp.b32 	%r300, %r299, %r298, %p3;
	mov.b32 	%f1714, %r300;

$L__BB0_55:
	setp.eq.f32 	%p75, %f181, 0f00000000;
	setp.eq.f32 	%p76, %f180, 0f3F800000;
	or.pred  	%p77, %p75, %p76;
	selp.f32 	%f897, 0f3F800000, %f1714, %p77;
	fma.rn.f32 	%f898, %f183, %f897, %f182;
	mul.f32 	%f899, %f1685, %f898;
	div.rn.f32 	%f900, %f899, %f393;
	div.rn.f32 	%f901, %f900, %f75;
	cvt.sat.f32.f32 	%f902, %f901;
	mul.f32 	%f1715, %f1715, %f902;

$L__BB0_56:
	add.f32 	%f1731, %f1731, %f1715;

$L__BB0_57:
	cvt.u64.u32 	%rd77, %r447;
	cvt.u32.u64 	%r304, %rd77;
	add.s32 	%r447, %r304, 1;
	setp.lt.u32 	%p78, %r447, %r5;
	@%p78 bra 	$L__BB0_7;
	bra.uni 	$L__BB0_59;

$L__BB0_58:
	mov.f32 	%f1716, 0f00000000;
	ld.const.u32 	%r451, [params+104];
	mov.f32 	%f1717, %f1716;
	mov.f32 	%f1718, %f1716;
	mov.f32 	%f1719, %f1716;
	mov.f32 	%f1720, %f1716;
	mov.f32 	%f1721, %f1716;
	mov.f32 	%f1722, %f1716;
	mov.f32 	%f1723, %f1716;
	mov.f32 	%f1724, %f1716;
	mov.f32 	%f1725, %f1716;
	mov.f32 	%f1726, %f1716;
	mov.f32 	%f1727, %f1716;
	mov.f32 	%f1728, %f1716;
	mov.f32 	%f1729, %f1716;
	mov.f32 	%f1730, %f1716;
	mov.f32 	%f1731, %f1716;

$L__BB0_59:
	and.b32  	%r305, %r451, 8;
	setp.eq.s32 	%p79, %r305, 0;
	@%p79 bra 	$L__BB0_73;

	cvt.sat.f32.f32 	%f233, %f1731;
	ld.const.u64 	%rd33, [params+192];
	cvta.to.global.u64 	%rd7, %rd33;
	ld.const.u32 	%r306, [params+184];
	mad.lo.s32 	%r307, %r306, %r4, %r3;
	cvt.u64.u32 	%rd8, %r307;
	mov.f32 	%f920, 0f3E68BA2E;
	cvt.rzi.f32.f32 	%f921, %f920;
	add.f32 	%f922, %f921, %f921;
	mov.f32 	%f923, 0f3EE8BA2E;
	sub.f32 	%f924, %f923, %f922;
	abs.f32 	%f234, %f924;
	abs.f32 	%f235, %f233;
	setp.lt.f32 	%p80, %f235, 0f00800000;
	mul.f32 	%f925, %f235, 0f4B800000;
	selp.f32 	%f926, %f925, %f235, %p80;
	selp.f32 	%f927, 0fC3170000, 0fC2FE0000, %p80;
	mov.b32 	%r308, %f926;
	and.b32  	%r309, %r308, 8388607;
	or.b32  	%r310, %r309, 1065353216;
	mov.b32 	%f928, %r310;
	shr.u32 	%r311, %r308, 23;
	cvt.rn.f32.u32 	%f929, %r311;
	add.f32 	%f930, %f927, %f929;
	setp.gt.f32 	%p81, %f928, 0f3FB504F3;
	mul.f32 	%f931, %f928, 0f3F000000;
	add.f32 	%f932, %f930, 0f3F800000;
	selp.f32 	%f933, %f932, %f930, %p81;
	selp.f32 	%f934, %f931, %f928, %p81;
	add.f32 	%f935, %f934, 0fBF800000;
	add.f32 	%f936, %f934, 0f3F800000;
	rcp.approx.ftz.f32 	%f937, %f936;
	add.f32 	%f938, %f935, %f935;
	mul.f32 	%f939, %f938, %f937;
	mul.f32 	%f940, %f939, %f939;
	mov.f32 	%f941, 0f3C4CAF63;
	mov.f32 	%f942, 0f3B18F0FE;
	fma.rn.f32 	%f943, %f942, %f940, %f941;
	mov.f32 	%f944, 0f3DAAAABD;
	fma.rn.f32 	%f945, %f943, %f940, %f944;
	mul.rn.f32 	%f946, %f945, %f940;
	mul.rn.f32 	%f947, %f946, %f939;
	sub.f32 	%f948, %f935, %f939;
	add.f32 	%f949, %f948, %f948;
	neg.f32 	%f950, %f939;
	fma.rn.f32 	%f951, %f950, %f935, %f949;
	mul.rn.f32 	%f952, %f937, %f951;
	add.f32 	%f953, %f947, %f939;
	sub.f32 	%f954, %f939, %f953;
	add.f32 	%f955, %f947, %f954;
	add.f32 	%f956, %f952, %f955;
	add.f32 	%f957, %f953, %f956;
	sub.f32 	%f958, %f953, %f957;
	add.f32 	%f959, %f956, %f958;
	mov.f32 	%f960, 0f3F317200;
	mul.rn.f32 	%f961, %f933, %f960;
	mov.f32 	%f962, 0f35BFBE8E;
	mul.rn.f32 	%f963, %f933, %f962;
	add.f32 	%f964, %f961, %f957;
	sub.f32 	%f965, %f961, %f964;
	add.f32 	%f966, %f957, %f965;
	add.f32 	%f967, %f959, %f966;
	add.f32 	%f968, %f963, %f967;
	add.f32 	%f969, %f964, %f968;
	sub.f32 	%f970, %f964, %f969;
	add.f32 	%f971, %f968, %f970;
	mul.rn.f32 	%f972, %f923, %f969;
	neg.f32 	%f973, %f972;
	fma.rn.f32 	%f974, %f923, %f969, %f973;
	fma.rn.f32 	%f975, %f923, %f971, %f974;
	mov.f32 	%f976, 0f00000000;
	fma.rn.f32 	%f977, %f976, %f969, %f975;
	add.rn.f32 	%f978, %f972, %f977;
	neg.f32 	%f979, %f978;
	add.rn.f32 	%f980, %f972, %f979;
	add.rn.f32 	%f981, %f980, %f977;
	mov.b32 	%r312, %f978;
	setp.eq.s32 	%p82, %r312, 1118925336;
	add.s32 	%r313, %r312, -1;
	mov.b32 	%f982, %r313;
	add.f32 	%f983, %f981, 0f37000000;
	selp.f32 	%f236, %f983, %f981, %p82;
	selp.f32 	%f984, %f982, %f978, %p82;
	mov.f32 	%f985, 0f3FB8AA3B;
	mul.rn.f32 	%f986, %f984, %f985;
	cvt.rzi.f32.f32 	%f987, %f986;
	abs.f32 	%f988, %f987;
	setp.gt.f32 	%p83, %f988, 0f42FC0000;
	mov.b32 	%r314, %f987;
	and.b32  	%r315, %r314, -2147483648;
	or.b32  	%r316, %r315, 1123811328;
	mov.b32 	%f989, %r316;
	selp.f32 	%f990, %f989, %f987, %p83;
	mov.f32 	%f991, 0fBF317218;
	fma.rn.f32 	%f992, %f990, %f991, %f984;
	mov.f32 	%f993, 0f3102E308;
	fma.rn.f32 	%f994, %f990, %f993, %f992;
	mul.f32 	%f995, %f994, 0f3FB8AA3B;
	add.f32 	%f996, %f990, 0f4B40007F;
	mov.b32 	%r317, %f996;
	shl.b32 	%r318, %r317, 23;
	mov.b32 	%f997, %r318;
	ex2.approx.ftz.f32 	%f998, %f995;
	mul.f32 	%f237, %f998, %f997;
	setp.eq.f32 	%p84, %f237, 0f7F800000;
	mov.f32 	%f1748, 0f7F800000;
	@%p84 bra 	$L__BB0_62;

	fma.rn.f32 	%f1748, %f237, %f236, %f237;

$L__BB0_62:
	setp.lt.f32 	%p85, %f233, 0f00000000;
	setp.eq.f32 	%p86, %f234, 0f3F800000;
	and.pred  	%p4, %p85, %p86;
	setp.eq.f32 	%p87, %f233, 0f00000000;
	@%p87 bra 	$L__BB0_66;
	bra.uni 	$L__BB0_63;

$L__BB0_66:
	add.f32 	%f1003, %f233, %f233;
	selp.f32 	%f1750, %f1003, 0f00000000, %p86;
	bra.uni 	$L__BB0_67;

$L__BB0_170:
	mov.f32 	%f1612, 0f00000000;
	mov.u32 	%r453, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1612;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1612;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1612;}

	// end inline asm
	mov.u16 	%rs116, 0;
	st.global.v4.u16 	[%rd16], {%rs113, %rs114, %rs115, %rs116};

$L__BB0_171:
	ld.const.u64 	%rd65, [params+256];
	cvta.to.global.u64 	%rd66, %rd65;
	ld.const.u32 	%r439, [params+248];
	mad.lo.s32 	%r440, %r439, %r4, %r3;
	mul.wide.u32 	%rd67, %r440, 8;
	add.s64 	%rd17, %rd66, %rd67;
	setp.eq.s32 	%p205, %r453, 0;
	@%p205 bra 	$L__BB0_173;

	ld.global.v4.u16 	{%rs123, %rs124, %rs125, %rs126}, [%rd17];
	// begin inline asm
	{  cvt.f32.f16 %f1613, %rs123;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1614, %rs124;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1615, %rs125;}

	// end inline asm
	add.f32 	%f1616, %f1613, 0f00000000;
	add.f32 	%f1617, %f1614, 0f00000000;
	add.f32 	%f1618, %f1615, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1618;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1617;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs120, %f1616;}

	// end inline asm
	mov.u16 	%rs127, 0;
	st.global.v4.u16 	[%rd17], {%rs120, %rs121, %rs122, %rs127};
	bra.uni 	$L__BB0_174;

$L__BB0_173:
	mov.f32 	%f1621, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1621;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1621;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1621;}

	// end inline asm
	mov.u16 	%rs131, 0;
	st.global.v4.u16 	[%rd17], {%rs128, %rs129, %rs130, %rs131};

$L__BB0_174:
	ld.const.u64 	%rd68, [params+272];
	cvta.to.global.u64 	%rd69, %rd68;
	ld.const.u32 	%r441, [params+264];
	mad.lo.s32 	%r442, %r441, %r4, %r3;
	mul.wide.u32 	%rd70, %r442, 8;
	add.s64 	%rd18, %rd69, %rd70;
	@%p205 bra 	$L__BB0_176;

	ld.global.v4.u16 	{%rs138, %rs139, %rs140, %rs141}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f1622, %rs138;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1623, %rs139;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1624, %rs140;}

	// end inline asm
	add.f32 	%f1625, %f1622, 0f00000000;
	add.f32 	%f1626, %f1623, 0f00000000;
	add.f32 	%f1627, %f1624, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1627;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1626;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs135, %f1625;}

	// end inline asm
	mov.u16 	%rs142, 0;
	st.global.v4.u16 	[%rd18], {%rs135, %rs136, %rs137, %rs142};
	bra.uni 	$L__BB0_177;

$L__BB0_176:
	mov.f32 	%f1630, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1630;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1630;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1630;}

	// end inline asm
	mov.u16 	%rs146, 0;
	st.global.v4.u16 	[%rd18], {%rs143, %rs144, %rs145, %rs146};

$L__BB0_177:
	ld.const.u64 	%rd71, [params+288];
	cvta.to.global.u64 	%rd72, %rd71;
	ld.const.u32 	%r443, [params+280];
	mad.lo.s32 	%r444, %r443, %r4, %r3;
	mul.wide.u32 	%rd73, %r444, 8;
	add.s64 	%rd19, %rd72, %rd73;
	@%p205 bra 	$L__BB0_179;

	ld.global.v4.u16 	{%rs153, %rs154, %rs155, %rs156}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f1631, %rs153;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1632, %rs154;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1633, %rs155;}

	// end inline asm
	add.f32 	%f1634, %f1631, 0f00000000;
	add.f32 	%f1635, %f1632, 0f00000000;
	add.f32 	%f1636, %f1633, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1636;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1635;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs150, %f1634;}

	// end inline asm
	mov.u16 	%rs157, 0;
	st.global.v4.u16 	[%rd19], {%rs150, %rs151, %rs152, %rs157};
	bra.uni 	$L__BB0_180;

$L__BB0_179:
	mov.f32 	%f1639, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1639;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1639;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1639;}

	// end inline asm
	mov.u16 	%rs161, 0;
	st.global.v4.u16 	[%rd19], {%rs158, %rs159, %rs160, %rs161};

$L__BB0_180:
	ld.const.u64 	%rd74, [params+304];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r445, [params+296];
	mad.lo.s32 	%r446, %r445, %r4, %r3;
	mul.wide.u32 	%rd76, %r446, 8;
	add.s64 	%rd20, %rd75, %rd76;
	@%p205 bra 	$L__BB0_182;

	ld.global.v4.u16 	{%rs168, %rs169, %rs170, %rs171}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f1640, %rs168;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1641, %rs169;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1642, %rs170;}

	// end inline asm
	add.f32 	%f1643, %f1640, 0f00000000;
	add.f32 	%f1644, %f1641, 0f00000000;
	add.f32 	%f1645, %f1642, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1645;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1644;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs165, %f1643;}

	// end inline asm
	mov.u16 	%rs172, 0;
	st.global.v4.u16 	[%rd20], {%rs165, %rs166, %rs167, %rs172};
	bra.uni 	$L__BB0_183;

$L__BB0_182:
	mov.f32 	%f1648, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs175, %f1648;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs174, %f1648;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs173, %f1648;}

	// end inline asm
	mov.u16 	%rs176, 0;
	st.global.v4.u16 	[%rd20], {%rs173, %rs174, %rs175, %rs176};
	bra.uni 	$L__BB0_183;

$L__BB0_63:
	mov.b32 	%r319, %f1748;
	xor.b32  	%r320, %r319, -2147483648;
	mov.b32 	%f999, %r320;
	selp.f32 	%f1750, %f999, %f1748, %p4;
	setp.geu.f32 	%p88, %f233, 0f00000000;
	@%p88 bra 	$L__BB0_67;

	mov.f32 	%f1000, 0f3EE8BA2E;
	cvt.rzi.f32.f32 	%f1001, %f1000;
	setp.eq.f32 	%p89, %f1001, 0f3EE8BA2E;
	@%p89 bra 	$L__BB0_67;

	mov.f32 	%f1750, 0f7FFFFFFF;

$L__BB0_67:
	add.f32 	%f1004, %f235, 0f3EE8BA2E;
	mov.b32 	%r321, %f1004;
	setp.lt.s32 	%p91, %r321, 2139095040;
	@%p91 bra 	$L__BB0_72;

	setp.gtu.f32 	%p92, %f235, 0f7F800000;
	@%p92 bra 	$L__BB0_71;
	bra.uni 	$L__BB0_69;

$L__BB0_71:
	add.f32 	%f1750, %f233, 0f3EE8BA2E;
	bra.uni 	$L__BB0_72;

$L__BB0_69:
	setp.neu.f32 	%p93, %f235, 0f7F800000;
	@%p93 bra 	$L__BB0_72;

	selp.f32 	%f1750, 0fFF800000, 0f7F800000, %p4;

$L__BB0_72:
	mul.f32 	%f1005, %f1750, 0f437F0000;
	setp.eq.f32 	%p94, %f233, 0f3F800000;
	selp.f32 	%f1006, 0f437F0000, %f1005, %p94;
	cvt.rzi.u32.f32 	%r322, %f1006;
	shl.b64 	%rd34, %rd8, 1;
	add.s64 	%rd35, %rd7, %rd34;
	cvt.u16.u32 	%rs18, %r322;
	mov.u16 	%rs19, 255;
	st.global.v2.u8 	[%rd35], {%rs18, %rs19};

$L__BB0_73:
	and.b32  	%r323, %r451, 1;
	setp.eq.b32 	%p95, %r323, 1;
	mov.pred 	%p96, 0;
	xor.pred  	%p97, %p95, %p96;
	not.pred 	%p98, %p97;
	@%p98 bra 	$L__BB0_147;

	mov.f32 	%f1008, 0f3E666666;
	cvt.rzi.f32.f32 	%f1009, %f1008;
	add.f32 	%f1010, %f1009, %f1009;
	mov.f32 	%f1011, 0f3EE66666;
	sub.f32 	%f1012, %f1011, %f1010;
	abs.f32 	%f246, %f1012;
	abs.f32 	%f247, %f1716;
	setp.lt.f32 	%p99, %f247, 0f00800000;
	mul.f32 	%f1013, %f247, 0f4B800000;
	selp.f32 	%f1014, %f1013, %f247, %p99;
	selp.f32 	%f1015, 0fC3170000, 0fC2FE0000, %p99;
	mov.b32 	%r324, %f1014;
	and.b32  	%r325, %r324, 8388607;
	or.b32  	%r326, %r325, 1065353216;
	mov.b32 	%f1016, %r326;
	shr.u32 	%r327, %r324, 23;
	cvt.rn.f32.u32 	%f1017, %r327;
	add.f32 	%f1018, %f1015, %f1017;
	setp.gt.f32 	%p100, %f1016, 0f3FB504F3;
	mul.f32 	%f1019, %f1016, 0f3F000000;
	add.f32 	%f1020, %f1018, 0f3F800000;
	selp.f32 	%f1021, %f1020, %f1018, %p100;
	selp.f32 	%f1022, %f1019, %f1016, %p100;
	add.f32 	%f1023, %f1022, 0fBF800000;
	add.f32 	%f1024, %f1022, 0f3F800000;
	rcp.approx.ftz.f32 	%f1025, %f1024;
	add.f32 	%f1026, %f1023, %f1023;
	mul.f32 	%f1027, %f1026, %f1025;
	mul.f32 	%f1028, %f1027, %f1027;
	mov.f32 	%f1029, 0f3C4CAF63;
	mov.f32 	%f1030, 0f3B18F0FE;
	fma.rn.f32 	%f1031, %f1030, %f1028, %f1029;
	mov.f32 	%f1032, 0f3DAAAABD;
	fma.rn.f32 	%f1033, %f1031, %f1028, %f1032;
	mul.rn.f32 	%f1034, %f1033, %f1028;
	mul.rn.f32 	%f1035, %f1034, %f1027;
	sub.f32 	%f1036, %f1023, %f1027;
	add.f32 	%f1037, %f1036, %f1036;
	neg.f32 	%f1038, %f1027;
	fma.rn.f32 	%f1039, %f1038, %f1023, %f1037;
	mul.rn.f32 	%f1040, %f1025, %f1039;
	add.f32 	%f1041, %f1035, %f1027;
	sub.f32 	%f1042, %f1027, %f1041;
	add.f32 	%f1043, %f1035, %f1042;
	add.f32 	%f1044, %f1040, %f1043;
	add.f32 	%f1045, %f1041, %f1044;
	sub.f32 	%f1046, %f1041, %f1045;
	add.f32 	%f1047, %f1044, %f1046;
	mov.f32 	%f1048, 0f3F317200;
	mul.rn.f32 	%f1049, %f1021, %f1048;
	mov.f32 	%f1050, 0f35BFBE8E;
	mul.rn.f32 	%f1051, %f1021, %f1050;
	add.f32 	%f1052, %f1049, %f1045;
	sub.f32 	%f1053, %f1049, %f1052;
	add.f32 	%f1054, %f1045, %f1053;
	add.f32 	%f1055, %f1047, %f1054;
	add.f32 	%f1056, %f1051, %f1055;
	add.f32 	%f1057, %f1052, %f1056;
	sub.f32 	%f1058, %f1052, %f1057;
	add.f32 	%f1059, %f1056, %f1058;
	mul.rn.f32 	%f1060, %f1011, %f1057;
	neg.f32 	%f1061, %f1060;
	fma.rn.f32 	%f1062, %f1011, %f1057, %f1061;
	fma.rn.f32 	%f1063, %f1011, %f1059, %f1062;
	mov.f32 	%f1064, 0f00000000;
	fma.rn.f32 	%f1065, %f1064, %f1057, %f1063;
	add.rn.f32 	%f1066, %f1060, %f1065;
	neg.f32 	%f1067, %f1066;
	add.rn.f32 	%f1068, %f1060, %f1067;
	add.rn.f32 	%f1069, %f1068, %f1065;
	mov.b32 	%r328, %f1066;
	setp.eq.s32 	%p101, %r328, 1118925336;
	add.s32 	%r329, %r328, -1;
	mov.b32 	%f1070, %r329;
	add.f32 	%f1071, %f1069, 0f37000000;
	selp.f32 	%f248, %f1071, %f1069, %p101;
	selp.f32 	%f1072, %f1070, %f1066, %p101;
	mov.f32 	%f1073, 0f3FB8AA3B;
	mul.rn.f32 	%f1074, %f1072, %f1073;
	cvt.rzi.f32.f32 	%f1075, %f1074;
	abs.f32 	%f1076, %f1075;
	setp.gt.f32 	%p102, %f1076, 0f42FC0000;
	mov.b32 	%r330, %f1075;
	and.b32  	%r331, %r330, -2147483648;
	or.b32  	%r332, %r331, 1123811328;
	mov.b32 	%f1077, %r332;
	selp.f32 	%f1078, %f1077, %f1075, %p102;
	mov.f32 	%f1079, 0fBF317218;
	fma.rn.f32 	%f1080, %f1078, %f1079, %f1072;
	mov.f32 	%f1081, 0f3102E308;
	fma.rn.f32 	%f1082, %f1078, %f1081, %f1080;
	mul.f32 	%f1083, %f1082, 0f3FB8AA3B;
	add.f32 	%f1084, %f1078, 0f4B40007F;
	mov.b32 	%r333, %f1084;
	shl.b32 	%r334, %r333, 23;
	mov.b32 	%f1085, %r334;
	ex2.approx.ftz.f32 	%f1086, %f1083;
	mul.f32 	%f249, %f1086, %f1085;
	setp.eq.f32 	%p103, %f249, 0f7F800000;
	mov.f32 	%f1751, 0f7F800000;
	@%p103 bra 	$L__BB0_76;

	fma.rn.f32 	%f1751, %f249, %f248, %f249;

$L__BB0_76:
	setp.lt.f32 	%p104, %f1716, 0f00000000;
	setp.eq.f32 	%p105, %f246, 0f3F800000;
	and.pred  	%p5, %p104, %p105;
	setp.eq.f32 	%p106, %f1716, 0f00000000;
	@%p106 bra 	$L__BB0_80;
	bra.uni 	$L__BB0_77;

$L__BB0_80:
	add.f32 	%f1091, %f1716, %f1716;
	selp.f32 	%f1753, %f1091, 0f00000000, %p105;
	bra.uni 	$L__BB0_81;

$L__BB0_77:
	mov.b32 	%r335, %f1751;
	xor.b32  	%r336, %r335, -2147483648;
	mov.b32 	%f1087, %r336;
	selp.f32 	%f1753, %f1087, %f1751, %p5;
	setp.geu.f32 	%p107, %f1716, 0f00000000;
	@%p107 bra 	$L__BB0_81;

	mov.f32 	%f1088, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1089, %f1088;
	setp.eq.f32 	%p108, %f1089, 0f3EE66666;
	@%p108 bra 	$L__BB0_81;

	mov.f32 	%f1753, 0f7FFFFFFF;

$L__BB0_81:
	add.f32 	%f1092, %f247, 0f3EE66666;
	mov.b32 	%r337, %f1092;
	setp.lt.s32 	%p110, %r337, 2139095040;
	@%p110 bra 	$L__BB0_86;

	setp.gtu.f32 	%p111, %f247, 0f7F800000;
	@%p111 bra 	$L__BB0_85;
	bra.uni 	$L__BB0_83;

$L__BB0_85:
	add.f32 	%f1753, %f1716, 0f3EE66666;
	bra.uni 	$L__BB0_86;

$L__BB0_83:
	setp.neu.f32 	%p112, %f247, 0f7F800000;
	@%p112 bra 	$L__BB0_86;

	selp.f32 	%f1753, 0fFF800000, 0f7F800000, %p5;

$L__BB0_86:
	setp.eq.f32 	%p113, %f1716, 0f3F800000;
	selp.f32 	%f258, 0f3F800000, %f1753, %p113;
	abs.f32 	%f259, %f1717;
	setp.lt.f32 	%p114, %f259, 0f00800000;
	mul.f32 	%f1094, %f259, 0f4B800000;
	selp.f32 	%f1095, %f1094, %f259, %p114;
	selp.f32 	%f1096, 0fC3170000, 0fC2FE0000, %p114;
	mov.b32 	%r338, %f1095;
	and.b32  	%r339, %r338, 8388607;
	or.b32  	%r340, %r339, 1065353216;
	mov.b32 	%f1097, %r340;
	shr.u32 	%r341, %r338, 23;
	cvt.rn.f32.u32 	%f1098, %r341;
	add.f32 	%f1099, %f1096, %f1098;
	setp.gt.f32 	%p115, %f1097, 0f3FB504F3;
	mul.f32 	%f1100, %f1097, 0f3F000000;
	add.f32 	%f1101, %f1099, 0f3F800000;
	selp.f32 	%f1102, %f1101, %f1099, %p115;
	selp.f32 	%f1103, %f1100, %f1097, %p115;
	add.f32 	%f1104, %f1103, 0fBF800000;
	add.f32 	%f1105, %f1103, 0f3F800000;
	rcp.approx.ftz.f32 	%f1106, %f1105;
	add.f32 	%f1107, %f1104, %f1104;
	mul.f32 	%f1108, %f1107, %f1106;
	mul.f32 	%f1109, %f1108, %f1108;
	mov.f32 	%f1110, 0f3C4CAF63;
	mov.f32 	%f1111, 0f3B18F0FE;
	fma.rn.f32 	%f1112, %f1111, %f1109, %f1110;
	mov.f32 	%f1113, 0f3DAAAABD;
	fma.rn.f32 	%f1114, %f1112, %f1109, %f1113;
	mul.rn.f32 	%f1115, %f1114, %f1109;
	mul.rn.f32 	%f1116, %f1115, %f1108;
	sub.f32 	%f1117, %f1104, %f1108;
	add.f32 	%f1118, %f1117, %f1117;
	neg.f32 	%f1119, %f1108;
	fma.rn.f32 	%f1120, %f1119, %f1104, %f1118;
	mul.rn.f32 	%f1121, %f1106, %f1120;
	add.f32 	%f1122, %f1116, %f1108;
	sub.f32 	%f1123, %f1108, %f1122;
	add.f32 	%f1124, %f1116, %f1123;
	add.f32 	%f1125, %f1121, %f1124;
	add.f32 	%f1126, %f1122, %f1125;
	sub.f32 	%f1127, %f1122, %f1126;
	add.f32 	%f1128, %f1125, %f1127;
	mov.f32 	%f1129, 0f3F317200;
	mul.rn.f32 	%f1130, %f1102, %f1129;
	mov.f32 	%f1131, 0f35BFBE8E;
	mul.rn.f32 	%f1132, %f1102, %f1131;
	add.f32 	%f1133, %f1130, %f1126;
	sub.f32 	%f1134, %f1130, %f1133;
	add.f32 	%f1135, %f1126, %f1134;
	add.f32 	%f1136, %f1128, %f1135;
	add.f32 	%f1137, %f1132, %f1136;
	add.f32 	%f1138, %f1133, %f1137;
	sub.f32 	%f1139, %f1133, %f1138;
	add.f32 	%f1140, %f1137, %f1139;
	mov.f32 	%f1141, 0f3EE66666;
	mul.rn.f32 	%f1142, %f1141, %f1138;
	neg.f32 	%f1143, %f1142;
	fma.rn.f32 	%f1144, %f1141, %f1138, %f1143;
	fma.rn.f32 	%f1145, %f1141, %f1140, %f1144;
	mov.f32 	%f1146, 0f00000000;
	fma.rn.f32 	%f1147, %f1146, %f1138, %f1145;
	add.rn.f32 	%f1148, %f1142, %f1147;
	neg.f32 	%f1149, %f1148;
	add.rn.f32 	%f1150, %f1142, %f1149;
	add.rn.f32 	%f1151, %f1150, %f1147;
	mov.b32 	%r342, %f1148;
	setp.eq.s32 	%p116, %r342, 1118925336;
	add.s32 	%r343, %r342, -1;
	mov.b32 	%f1152, %r343;
	add.f32 	%f1153, %f1151, 0f37000000;
	selp.f32 	%f260, %f1153, %f1151, %p116;
	selp.f32 	%f1154, %f1152, %f1148, %p116;
	mov.f32 	%f1155, 0f3FB8AA3B;
	mul.rn.f32 	%f1156, %f1154, %f1155;
	cvt.rzi.f32.f32 	%f1157, %f1156;
	abs.f32 	%f1158, %f1157;
	setp.gt.f32 	%p117, %f1158, 0f42FC0000;
	mov.b32 	%r344, %f1157;
	and.b32  	%r345, %r344, -2147483648;
	or.b32  	%r346, %r345, 1123811328;
	mov.b32 	%f1159, %r346;
	selp.f32 	%f1160, %f1159, %f1157, %p117;
	mov.f32 	%f1161, 0fBF317218;
	fma.rn.f32 	%f1162, %f1160, %f1161, %f1154;
	mov.f32 	%f1163, 0f3102E308;
	fma.rn.f32 	%f1164, %f1160, %f1163, %f1162;
	mul.f32 	%f1165, %f1164, 0f3FB8AA3B;
	add.f32 	%f1166, %f1160, 0f4B40007F;
	mov.b32 	%r347, %f1166;
	shl.b32 	%r348, %r347, 23;
	mov.b32 	%f1167, %r348;
	ex2.approx.ftz.f32 	%f1168, %f1165;
	mul.f32 	%f261, %f1168, %f1167;
	setp.eq.f32 	%p118, %f261, 0f7F800000;
	mov.f32 	%f1754, 0f7F800000;
	@%p118 bra 	$L__BB0_88;

	fma.rn.f32 	%f1754, %f261, %f260, %f261;

$L__BB0_88:
	setp.lt.f32 	%p119, %f1717, 0f00000000;
	and.pred  	%p6, %p119, %p105;
	setp.eq.f32 	%p121, %f1717, 0f00000000;
	@%p121 bra 	$L__BB0_92;
	bra.uni 	$L__BB0_89;

$L__BB0_92:
	add.f32 	%f1173, %f1717, %f1717;
	selp.f32 	%f1756, %f1173, 0f00000000, %p105;
	bra.uni 	$L__BB0_93;

$L__BB0_89:
	mov.b32 	%r349, %f1754;
	xor.b32  	%r350, %r349, -2147483648;
	mov.b32 	%f1169, %r350;
	selp.f32 	%f1756, %f1169, %f1754, %p6;
	setp.geu.f32 	%p122, %f1717, 0f00000000;
	@%p122 bra 	$L__BB0_93;

	mov.f32 	%f1170, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1171, %f1170;
	setp.eq.f32 	%p123, %f1171, 0f3EE66666;
	@%p123 bra 	$L__BB0_93;

	mov.f32 	%f1756, 0f7FFFFFFF;

$L__BB0_93:
	add.f32 	%f1174, %f259, 0f3EE66666;
	mov.b32 	%r351, %f1174;
	setp.lt.s32 	%p125, %r351, 2139095040;
	@%p125 bra 	$L__BB0_98;

	setp.gtu.f32 	%p126, %f259, 0f7F800000;
	@%p126 bra 	$L__BB0_97;
	bra.uni 	$L__BB0_95;

$L__BB0_97:
	add.f32 	%f1756, %f1717, 0f3EE66666;
	bra.uni 	$L__BB0_98;

$L__BB0_95:
	setp.neu.f32 	%p127, %f259, 0f7F800000;
	@%p127 bra 	$L__BB0_98;

	selp.f32 	%f1756, 0fFF800000, 0f7F800000, %p6;

$L__BB0_98:
	setp.eq.f32 	%p128, %f1717, 0f3F800000;
	selp.f32 	%f270, 0f3F800000, %f1756, %p128;
	abs.f32 	%f271, %f1718;
	setp.lt.f32 	%p129, %f271, 0f00800000;
	mul.f32 	%f1176, %f271, 0f4B800000;
	selp.f32 	%f1177, %f1176, %f271, %p129;
	selp.f32 	%f1178, 0fC3170000, 0fC2FE0000, %p129;
	mov.b32 	%r352, %f1177;
	and.b32  	%r353, %r352, 8388607;
	or.b32  	%r354, %r353, 1065353216;
	mov.b32 	%f1179, %r354;
	shr.u32 	%r355, %r352, 23;
	cvt.rn.f32.u32 	%f1180, %r355;
	add.f32 	%f1181, %f1178, %f1180;
	setp.gt.f32 	%p130, %f1179, 0f3FB504F3;
	mul.f32 	%f1182, %f1179, 0f3F000000;
	add.f32 	%f1183, %f1181, 0f3F800000;
	selp.f32 	%f1184, %f1183, %f1181, %p130;
	selp.f32 	%f1185, %f1182, %f1179, %p130;
	add.f32 	%f1186, %f1185, 0fBF800000;
	add.f32 	%f1187, %f1185, 0f3F800000;
	rcp.approx.ftz.f32 	%f1188, %f1187;
	add.f32 	%f1189, %f1186, %f1186;
	mul.f32 	%f1190, %f1189, %f1188;
	mul.f32 	%f1191, %f1190, %f1190;
	mov.f32 	%f1192, 0f3C4CAF63;
	mov.f32 	%f1193, 0f3B18F0FE;
	fma.rn.f32 	%f1194, %f1193, %f1191, %f1192;
	mov.f32 	%f1195, 0f3DAAAABD;
	fma.rn.f32 	%f1196, %f1194, %f1191, %f1195;
	mul.rn.f32 	%f1197, %f1196, %f1191;
	mul.rn.f32 	%f1198, %f1197, %f1190;
	sub.f32 	%f1199, %f1186, %f1190;
	add.f32 	%f1200, %f1199, %f1199;
	neg.f32 	%f1201, %f1190;
	fma.rn.f32 	%f1202, %f1201, %f1186, %f1200;
	mul.rn.f32 	%f1203, %f1188, %f1202;
	add.f32 	%f1204, %f1198, %f1190;
	sub.f32 	%f1205, %f1190, %f1204;
	add.f32 	%f1206, %f1198, %f1205;
	add.f32 	%f1207, %f1203, %f1206;
	add.f32 	%f1208, %f1204, %f1207;
	sub.f32 	%f1209, %f1204, %f1208;
	add.f32 	%f1210, %f1207, %f1209;
	mov.f32 	%f1211, 0f3F317200;
	mul.rn.f32 	%f1212, %f1184, %f1211;
	mov.f32 	%f1213, 0f35BFBE8E;
	mul.rn.f32 	%f1214, %f1184, %f1213;
	add.f32 	%f1215, %f1212, %f1208;
	sub.f32 	%f1216, %f1212, %f1215;
	add.f32 	%f1217, %f1208, %f1216;
	add.f32 	%f1218, %f1210, %f1217;
	add.f32 	%f1219, %f1214, %f1218;
	add.f32 	%f1220, %f1215, %f1219;
	sub.f32 	%f1221, %f1215, %f1220;
	add.f32 	%f1222, %f1219, %f1221;
	mov.f32 	%f1223, 0f3EE66666;
	mul.rn.f32 	%f1224, %f1223, %f1220;
	neg.f32 	%f1225, %f1224;
	fma.rn.f32 	%f1226, %f1223, %f1220, %f1225;
	fma.rn.f32 	%f1227, %f1223, %f1222, %f1226;
	mov.f32 	%f1228, 0f00000000;
	fma.rn.f32 	%f1229, %f1228, %f1220, %f1227;
	add.rn.f32 	%f1230, %f1224, %f1229;
	neg.f32 	%f1231, %f1230;
	add.rn.f32 	%f1232, %f1224, %f1231;
	add.rn.f32 	%f1233, %f1232, %f1229;
	mov.b32 	%r356, %f1230;
	setp.eq.s32 	%p131, %r356, 1118925336;
	add.s32 	%r357, %r356, -1;
	mov.b32 	%f1234, %r357;
	add.f32 	%f1235, %f1233, 0f37000000;
	selp.f32 	%f272, %f1235, %f1233, %p131;
	selp.f32 	%f1236, %f1234, %f1230, %p131;
	mov.f32 	%f1237, 0f3FB8AA3B;
	mul.rn.f32 	%f1238, %f1236, %f1237;
	cvt.rzi.f32.f32 	%f1239, %f1238;
	abs.f32 	%f1240, %f1239;
	setp.gt.f32 	%p132, %f1240, 0f42FC0000;
	mov.b32 	%r358, %f1239;
	and.b32  	%r359, %r358, -2147483648;
	or.b32  	%r360, %r359, 1123811328;
	mov.b32 	%f1241, %r360;
	selp.f32 	%f1242, %f1241, %f1239, %p132;
	mov.f32 	%f1243, 0fBF317218;
	fma.rn.f32 	%f1244, %f1242, %f1243, %f1236;
	mov.f32 	%f1245, 0f3102E308;
	fma.rn.f32 	%f1246, %f1242, %f1245, %f1244;
	mul.f32 	%f1247, %f1246, 0f3FB8AA3B;
	add.f32 	%f1248, %f1242, 0f4B40007F;
	mov.b32 	%r361, %f1248;
	shl.b32 	%r362, %r361, 23;
	mov.b32 	%f1249, %r362;
	ex2.approx.ftz.f32 	%f1250, %f1247;
	mul.f32 	%f273, %f1250, %f1249;
	setp.eq.f32 	%p133, %f273, 0f7F800000;
	mov.f32 	%f1757, 0f7F800000;
	@%p133 bra 	$L__BB0_100;

	fma.rn.f32 	%f1757, %f273, %f272, %f273;

$L__BB0_100:
	setp.lt.f32 	%p134, %f1718, 0f00000000;
	and.pred  	%p7, %p134, %p105;
	setp.eq.f32 	%p136, %f1718, 0f00000000;
	@%p136 bra 	$L__BB0_104;
	bra.uni 	$L__BB0_101;

$L__BB0_104:
	add.f32 	%f1255, %f1718, %f1718;
	selp.f32 	%f1759, %f1255, 0f00000000, %p105;
	bra.uni 	$L__BB0_105;

$L__BB0_101:
	mov.b32 	%r363, %f1757;
	xor.b32  	%r364, %r363, -2147483648;
	mov.b32 	%f1251, %r364;
	selp.f32 	%f1759, %f1251, %f1757, %p7;
	setp.geu.f32 	%p137, %f1718, 0f00000000;
	@%p137 bra 	$L__BB0_105;

	mov.f32 	%f1252, 0f3EE66666;
	cvt.rzi.f32.f32 	%f1253, %f1252;
	setp.eq.f32 	%p138, %f1253, 0f3EE66666;
	@%p138 bra 	$L__BB0_105;

	mov.f32 	%f1759, 0f7FFFFFFF;

$L__BB0_105:
	add.f32 	%f1256, %f271, 0f3EE66666;
	mov.b32 	%r365, %f1256;
	setp.lt.s32 	%p140, %r365, 2139095040;
	@%p140 bra 	$L__BB0_110;

	setp.gtu.f32 	%p141, %f271, 0f7F800000;
	@%p141 bra 	$L__BB0_109;
	bra.uni 	$L__BB0_107;

$L__BB0_109:
	add.f32 	%f1759, %f1718, 0f3EE66666;
	bra.uni 	$L__BB0_110;

$L__BB0_107:
	setp.neu.f32 	%p142, %f271, 0f7F800000;
	@%p142 bra 	$L__BB0_110;

	selp.f32 	%f1759, 0fFF800000, 0f7F800000, %p7;

$L__BB0_110:
	setp.eq.f32 	%p143, %f1718, 0f3F800000;
	mov.f32 	%f1258, 0f3F800000;
	selp.f32 	%f1259, 0f3F800000, %f1759, %p143;
	ld.const.u64 	%rd36, [params+144];
	cvta.to.global.u64 	%rd9, %rd36;
	ld.const.u32 	%r366, [params+136];
	mad.lo.s32 	%r367, %r366, %r4, %r3;
	cvt.u64.u32 	%rd10, %r367;
	min.f32 	%f1260, %f258, %f1258;
	mov.f32 	%f1261, 0f00000000;
	max.f32 	%f282, %f1261, %f1260;
	min.f32 	%f1262, %f270, %f1258;
	max.f32 	%f283, %f1261, %f1262;
	min.f32 	%f1263, %f1259, %f1258;
	max.f32 	%f284, %f1261, %f1263;
	mov.f32 	%f1264, 0f3E555555;
	cvt.rzi.f32.f32 	%f1265, %f1264;
	add.f32 	%f1266, %f1265, %f1265;
	mov.f32 	%f1267, 0f3ED55555;
	sub.f32 	%f1268, %f1267, %f1266;
	abs.f32 	%f285, %f1268;
	abs.f32 	%f286, %f282;
	setp.lt.f32 	%p144, %f286, 0f00800000;
	mul.f32 	%f1269, %f286, 0f4B800000;
	selp.f32 	%f1270, %f1269, %f286, %p144;
	selp.f32 	%f1271, 0fC3170000, 0fC2FE0000, %p144;
	mov.b32 	%r368, %f1270;
	and.b32  	%r369, %r368, 8388607;
	or.b32  	%r370, %r369, 1065353216;
	mov.b32 	%f1272, %r370;
	shr.u32 	%r371, %r368, 23;
	cvt.rn.f32.u32 	%f1273, %r371;
	add.f32 	%f1274, %f1271, %f1273;
	setp.gt.f32 	%p145, %f1272, 0f3FB504F3;
	mul.f32 	%f1275, %f1272, 0f3F000000;
	add.f32 	%f1276, %f1274, 0f3F800000;
	selp.f32 	%f1277, %f1276, %f1274, %p145;
	selp.f32 	%f1278, %f1275, %f1272, %p145;
	add.f32 	%f1279, %f1278, 0fBF800000;
	add.f32 	%f1280, %f1278, 0f3F800000;
	rcp.approx.ftz.f32 	%f1281, %f1280;
	add.f32 	%f1282, %f1279, %f1279;
	mul.f32 	%f1283, %f1282, %f1281;
	mul.f32 	%f1284, %f1283, %f1283;
	mov.f32 	%f1285, 0f3C4CAF63;
	mov.f32 	%f1286, 0f3B18F0FE;
	fma.rn.f32 	%f1287, %f1286, %f1284, %f1285;
	mov.f32 	%f1288, 0f3DAAAABD;
	fma.rn.f32 	%f1289, %f1287, %f1284, %f1288;
	mul.rn.f32 	%f1290, %f1289, %f1284;
	mul.rn.f32 	%f1291, %f1290, %f1283;
	sub.f32 	%f1292, %f1279, %f1283;
	add.f32 	%f1293, %f1292, %f1292;
	neg.f32 	%f1294, %f1283;
	fma.rn.f32 	%f1295, %f1294, %f1279, %f1293;
	mul.rn.f32 	%f1296, %f1281, %f1295;
	add.f32 	%f1297, %f1291, %f1283;
	sub.f32 	%f1298, %f1283, %f1297;
	add.f32 	%f1299, %f1291, %f1298;
	add.f32 	%f1300, %f1296, %f1299;
	add.f32 	%f1301, %f1297, %f1300;
	sub.f32 	%f1302, %f1297, %f1301;
	add.f32 	%f1303, %f1300, %f1302;
	mov.f32 	%f1304, 0f3F317200;
	mul.rn.f32 	%f1305, %f1277, %f1304;
	mov.f32 	%f1306, 0f35BFBE8E;
	mul.rn.f32 	%f1307, %f1277, %f1306;
	add.f32 	%f1308, %f1305, %f1301;
	sub.f32 	%f1309, %f1305, %f1308;
	add.f32 	%f1310, %f1301, %f1309;
	add.f32 	%f1311, %f1303, %f1310;
	add.f32 	%f1312, %f1307, %f1311;
	add.f32 	%f1313, %f1308, %f1312;
	sub.f32 	%f1314, %f1308, %f1313;
	add.f32 	%f1315, %f1312, %f1314;
	mul.rn.f32 	%f1316, %f1267, %f1313;
	neg.f32 	%f1317, %f1316;
	fma.rn.f32 	%f1318, %f1267, %f1313, %f1317;
	fma.rn.f32 	%f1319, %f1267, %f1315, %f1318;
	fma.rn.f32 	%f1320, %f1261, %f1313, %f1319;
	add.rn.f32 	%f1321, %f1316, %f1320;
	neg.f32 	%f1322, %f1321;
	add.rn.f32 	%f1323, %f1316, %f1322;
	add.rn.f32 	%f1324, %f1323, %f1320;
	mov.b32 	%r372, %f1321;
	setp.eq.s32 	%p146, %r372, 1118925336;
	add.s32 	%r373, %r372, -1;
	mov.b32 	%f1325, %r373;
	add.f32 	%f1326, %f1324, 0f37000000;
	selp.f32 	%f287, %f1326, %f1324, %p146;
	selp.f32 	%f1327, %f1325, %f1321, %p146;
	mov.f32 	%f1328, 0f3FB8AA3B;
	mul.rn.f32 	%f1329, %f1327, %f1328;
	cvt.rzi.f32.f32 	%f1330, %f1329;
	abs.f32 	%f1331, %f1330;
	setp.gt.f32 	%p147, %f1331, 0f42FC0000;
	mov.b32 	%r374, %f1330;
	and.b32  	%r375, %r374, -2147483648;
	or.b32  	%r376, %r375, 1123811328;
	mov.b32 	%f1332, %r376;
	selp.f32 	%f1333, %f1332, %f1330, %p147;
	mov.f32 	%f1334, 0fBF317218;
	fma.rn.f32 	%f1335, %f1333, %f1334, %f1327;
	mov.f32 	%f1336, 0f3102E308;
	fma.rn.f32 	%f1337, %f1333, %f1336, %f1335;
	mul.f32 	%f1338, %f1337, 0f3FB8AA3B;
	add.f32 	%f1339, %f1333, 0f4B40007F;
	mov.b32 	%r377, %f1339;
	shl.b32 	%r378, %r377, 23;
	mov.b32 	%f1340, %r378;
	ex2.approx.ftz.f32 	%f1341, %f1338;
	mul.f32 	%f288, %f1341, %f1340;
	setp.eq.f32 	%p148, %f288, 0f7F800000;
	mov.f32 	%f1760, 0f7F800000;
	@%p148 bra 	$L__BB0_112;

	fma.rn.f32 	%f1760, %f288, %f287, %f288;

$L__BB0_112:
	setp.lt.f32 	%p149, %f282, 0f00000000;
	setp.eq.f32 	%p150, %f285, 0f3F800000;
	and.pred  	%p8, %p149, %p150;
	setp.eq.f32 	%p151, %f282, 0f00000000;
	@%p151 bra 	$L__BB0_116;
	bra.uni 	$L__BB0_113;

$L__BB0_116:
	add.f32 	%f1346, %f282, %f282;
	selp.f32 	%f1762, %f1346, 0f00000000, %p150;
	bra.uni 	$L__BB0_117;

$L__BB0_113:
	mov.b32 	%r379, %f1760;
	xor.b32  	%r380, %r379, -2147483648;
	mov.b32 	%f1342, %r380;
	selp.f32 	%f1762, %f1342, %f1760, %p8;
	setp.geu.f32 	%p152, %f282, 0f00000000;
	@%p152 bra 	$L__BB0_117;

	mov.f32 	%f1343, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1344, %f1343;
	setp.eq.f32 	%p153, %f1344, 0f3ED55555;
	@%p153 bra 	$L__BB0_117;

	mov.f32 	%f1762, 0f7FFFFFFF;

$L__BB0_117:
	add.f32 	%f1347, %f286, 0f3ED55555;
	mov.b32 	%r381, %f1347;
	setp.lt.s32 	%p155, %r381, 2139095040;
	@%p155 bra 	$L__BB0_122;

	setp.gtu.f32 	%p156, %f286, 0f7F800000;
	@%p156 bra 	$L__BB0_121;
	bra.uni 	$L__BB0_119;

$L__BB0_121:
	add.f32 	%f1762, %f282, 0f3ED55555;
	bra.uni 	$L__BB0_122;

$L__BB0_119:
	setp.neu.f32 	%p157, %f286, 0f7F800000;
	@%p157 bra 	$L__BB0_122;

	selp.f32 	%f1762, 0fFF800000, 0f7F800000, %p8;

$L__BB0_122:
	abs.f32 	%f297, %f283;
	setp.lt.f32 	%p158, %f297, 0f00800000;
	mul.f32 	%f1349, %f297, 0f4B800000;
	selp.f32 	%f1350, %f1349, %f297, %p158;
	selp.f32 	%f1351, 0fC3170000, 0fC2FE0000, %p158;
	mov.b32 	%r382, %f1350;
	and.b32  	%r383, %r382, 8388607;
	or.b32  	%r384, %r383, 1065353216;
	mov.b32 	%f1352, %r384;
	shr.u32 	%r385, %r382, 23;
	cvt.rn.f32.u32 	%f1353, %r385;
	add.f32 	%f1354, %f1351, %f1353;
	setp.gt.f32 	%p159, %f1352, 0f3FB504F3;
	mul.f32 	%f1355, %f1352, 0f3F000000;
	add.f32 	%f1356, %f1354, 0f3F800000;
	selp.f32 	%f1357, %f1356, %f1354, %p159;
	selp.f32 	%f1358, %f1355, %f1352, %p159;
	add.f32 	%f1359, %f1358, 0fBF800000;
	add.f32 	%f1360, %f1358, 0f3F800000;
	rcp.approx.ftz.f32 	%f1361, %f1360;
	add.f32 	%f1362, %f1359, %f1359;
	mul.f32 	%f1363, %f1362, %f1361;
	mul.f32 	%f1364, %f1363, %f1363;
	mov.f32 	%f1365, 0f3C4CAF63;
	mov.f32 	%f1366, 0f3B18F0FE;
	fma.rn.f32 	%f1367, %f1366, %f1364, %f1365;
	mov.f32 	%f1368, 0f3DAAAABD;
	fma.rn.f32 	%f1369, %f1367, %f1364, %f1368;
	mul.rn.f32 	%f1370, %f1369, %f1364;
	mul.rn.f32 	%f1371, %f1370, %f1363;
	sub.f32 	%f1372, %f1359, %f1363;
	add.f32 	%f1373, %f1372, %f1372;
	neg.f32 	%f1374, %f1363;
	fma.rn.f32 	%f1375, %f1374, %f1359, %f1373;
	mul.rn.f32 	%f1376, %f1361, %f1375;
	add.f32 	%f1377, %f1371, %f1363;
	sub.f32 	%f1378, %f1363, %f1377;
	add.f32 	%f1379, %f1371, %f1378;
	add.f32 	%f1380, %f1376, %f1379;
	add.f32 	%f1381, %f1377, %f1380;
	sub.f32 	%f1382, %f1377, %f1381;
	add.f32 	%f1383, %f1380, %f1382;
	mov.f32 	%f1384, 0f3F317200;
	mul.rn.f32 	%f1385, %f1357, %f1384;
	mov.f32 	%f1386, 0f35BFBE8E;
	mul.rn.f32 	%f1387, %f1357, %f1386;
	add.f32 	%f1388, %f1385, %f1381;
	sub.f32 	%f1389, %f1385, %f1388;
	add.f32 	%f1390, %f1381, %f1389;
	add.f32 	%f1391, %f1383, %f1390;
	add.f32 	%f1392, %f1387, %f1391;
	add.f32 	%f1393, %f1388, %f1392;
	sub.f32 	%f1394, %f1388, %f1393;
	add.f32 	%f1395, %f1392, %f1394;
	mov.f32 	%f1396, 0f3ED55555;
	mul.rn.f32 	%f1397, %f1396, %f1393;
	neg.f32 	%f1398, %f1397;
	fma.rn.f32 	%f1399, %f1396, %f1393, %f1398;
	fma.rn.f32 	%f1400, %f1396, %f1395, %f1399;
	mov.f32 	%f1401, 0f00000000;
	fma.rn.f32 	%f1402, %f1401, %f1393, %f1400;
	add.rn.f32 	%f1403, %f1397, %f1402;
	neg.f32 	%f1404, %f1403;
	add.rn.f32 	%f1405, %f1397, %f1404;
	add.rn.f32 	%f1406, %f1405, %f1402;
	mov.b32 	%r386, %f1403;
	setp.eq.s32 	%p160, %r386, 1118925336;
	add.s32 	%r387, %r386, -1;
	mov.b32 	%f1407, %r387;
	add.f32 	%f1408, %f1406, 0f37000000;
	selp.f32 	%f298, %f1408, %f1406, %p160;
	selp.f32 	%f1409, %f1407, %f1403, %p160;
	mov.f32 	%f1410, 0f3FB8AA3B;
	mul.rn.f32 	%f1411, %f1409, %f1410;
	cvt.rzi.f32.f32 	%f1412, %f1411;
	abs.f32 	%f1413, %f1412;
	setp.gt.f32 	%p161, %f1413, 0f42FC0000;
	mov.b32 	%r388, %f1412;
	and.b32  	%r389, %r388, -2147483648;
	or.b32  	%r390, %r389, 1123811328;
	mov.b32 	%f1414, %r390;
	selp.f32 	%f1415, %f1414, %f1412, %p161;
	mov.f32 	%f1416, 0fBF317218;
	fma.rn.f32 	%f1417, %f1415, %f1416, %f1409;
	mov.f32 	%f1418, 0f3102E308;
	fma.rn.f32 	%f1419, %f1415, %f1418, %f1417;
	mul.f32 	%f1420, %f1419, 0f3FB8AA3B;
	add.f32 	%f1421, %f1415, 0f4B40007F;
	mov.b32 	%r391, %f1421;
	shl.b32 	%r392, %r391, 23;
	mov.b32 	%f1422, %r392;
	ex2.approx.ftz.f32 	%f1423, %f1420;
	mul.f32 	%f299, %f1423, %f1422;
	setp.eq.f32 	%p162, %f299, 0f7F800000;
	mov.f32 	%f1763, 0f7F800000;
	@%p162 bra 	$L__BB0_124;

	fma.rn.f32 	%f1763, %f299, %f298, %f299;

$L__BB0_124:
	setp.lt.f32 	%p163, %f283, 0f00000000;
	and.pred  	%p9, %p163, %p150;
	setp.eq.f32 	%p165, %f283, 0f00000000;
	@%p165 bra 	$L__BB0_128;
	bra.uni 	$L__BB0_125;

$L__BB0_128:
	add.f32 	%f1428, %f283, %f283;
	selp.f32 	%f1765, %f1428, 0f00000000, %p150;
	bra.uni 	$L__BB0_129;

$L__BB0_125:
	mov.b32 	%r393, %f1763;
	xor.b32  	%r394, %r393, -2147483648;
	mov.b32 	%f1424, %r394;
	selp.f32 	%f1765, %f1424, %f1763, %p9;
	setp.geu.f32 	%p166, %f283, 0f00000000;
	@%p166 bra 	$L__BB0_129;

	mov.f32 	%f1425, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1426, %f1425;
	setp.eq.f32 	%p167, %f1426, 0f3ED55555;
	@%p167 bra 	$L__BB0_129;

	mov.f32 	%f1765, 0f7FFFFFFF;

$L__BB0_129:
	add.f32 	%f1429, %f297, 0f3ED55555;
	mov.b32 	%r395, %f1429;
	setp.lt.s32 	%p169, %r395, 2139095040;
	@%p169 bra 	$L__BB0_134;

	setp.gtu.f32 	%p170, %f297, 0f7F800000;
	@%p170 bra 	$L__BB0_133;
	bra.uni 	$L__BB0_131;

$L__BB0_133:
	add.f32 	%f1765, %f283, 0f3ED55555;
	bra.uni 	$L__BB0_134;

$L__BB0_131:
	setp.neu.f32 	%p171, %f297, 0f7F800000;
	@%p171 bra 	$L__BB0_134;

	selp.f32 	%f1765, 0fFF800000, 0f7F800000, %p9;

$L__BB0_134:
	abs.f32 	%f308, %f284;
	setp.lt.f32 	%p172, %f308, 0f00800000;
	mul.f32 	%f1431, %f308, 0f4B800000;
	selp.f32 	%f1432, %f1431, %f308, %p172;
	selp.f32 	%f1433, 0fC3170000, 0fC2FE0000, %p172;
	mov.b32 	%r396, %f1432;
	and.b32  	%r397, %r396, 8388607;
	or.b32  	%r398, %r397, 1065353216;
	mov.b32 	%f1434, %r398;
	shr.u32 	%r399, %r396, 23;
	cvt.rn.f32.u32 	%f1435, %r399;
	add.f32 	%f1436, %f1433, %f1435;
	setp.gt.f32 	%p173, %f1434, 0f3FB504F3;
	mul.f32 	%f1437, %f1434, 0f3F000000;
	add.f32 	%f1438, %f1436, 0f3F800000;
	selp.f32 	%f1439, %f1438, %f1436, %p173;
	selp.f32 	%f1440, %f1437, %f1434, %p173;
	add.f32 	%f1441, %f1440, 0fBF800000;
	add.f32 	%f1442, %f1440, 0f3F800000;
	rcp.approx.ftz.f32 	%f1443, %f1442;
	add.f32 	%f1444, %f1441, %f1441;
	mul.f32 	%f1445, %f1444, %f1443;
	mul.f32 	%f1446, %f1445, %f1445;
	mov.f32 	%f1447, 0f3C4CAF63;
	mov.f32 	%f1448, 0f3B18F0FE;
	fma.rn.f32 	%f1449, %f1448, %f1446, %f1447;
	mov.f32 	%f1450, 0f3DAAAABD;
	fma.rn.f32 	%f1451, %f1449, %f1446, %f1450;
	mul.rn.f32 	%f1452, %f1451, %f1446;
	mul.rn.f32 	%f1453, %f1452, %f1445;
	sub.f32 	%f1454, %f1441, %f1445;
	add.f32 	%f1455, %f1454, %f1454;
	neg.f32 	%f1456, %f1445;
	fma.rn.f32 	%f1457, %f1456, %f1441, %f1455;
	mul.rn.f32 	%f1458, %f1443, %f1457;
	add.f32 	%f1459, %f1453, %f1445;
	sub.f32 	%f1460, %f1445, %f1459;
	add.f32 	%f1461, %f1453, %f1460;
	add.f32 	%f1462, %f1458, %f1461;
	add.f32 	%f1463, %f1459, %f1462;
	sub.f32 	%f1464, %f1459, %f1463;
	add.f32 	%f1465, %f1462, %f1464;
	mov.f32 	%f1466, 0f3F317200;
	mul.rn.f32 	%f1467, %f1439, %f1466;
	mov.f32 	%f1468, 0f35BFBE8E;
	mul.rn.f32 	%f1469, %f1439, %f1468;
	add.f32 	%f1470, %f1467, %f1463;
	sub.f32 	%f1471, %f1467, %f1470;
	add.f32 	%f1472, %f1463, %f1471;
	add.f32 	%f1473, %f1465, %f1472;
	add.f32 	%f1474, %f1469, %f1473;
	add.f32 	%f1475, %f1470, %f1474;
	sub.f32 	%f1476, %f1470, %f1475;
	add.f32 	%f1477, %f1474, %f1476;
	mov.f32 	%f1478, 0f3ED55555;
	mul.rn.f32 	%f1479, %f1478, %f1475;
	neg.f32 	%f1480, %f1479;
	fma.rn.f32 	%f1481, %f1478, %f1475, %f1480;
	fma.rn.f32 	%f1482, %f1478, %f1477, %f1481;
	mov.f32 	%f1483, 0f00000000;
	fma.rn.f32 	%f1484, %f1483, %f1475, %f1482;
	add.rn.f32 	%f1485, %f1479, %f1484;
	neg.f32 	%f1486, %f1485;
	add.rn.f32 	%f1487, %f1479, %f1486;
	add.rn.f32 	%f1488, %f1487, %f1484;
	mov.b32 	%r400, %f1485;
	setp.eq.s32 	%p174, %r400, 1118925336;
	add.s32 	%r401, %r400, -1;
	mov.b32 	%f1489, %r401;
	add.f32 	%f1490, %f1488, 0f37000000;
	selp.f32 	%f309, %f1490, %f1488, %p174;
	selp.f32 	%f1491, %f1489, %f1485, %p174;
	mov.f32 	%f1492, 0f3FB8AA3B;
	mul.rn.f32 	%f1493, %f1491, %f1492;
	cvt.rzi.f32.f32 	%f1494, %f1493;
	abs.f32 	%f1495, %f1494;
	setp.gt.f32 	%p175, %f1495, 0f42FC0000;
	mov.b32 	%r402, %f1494;
	and.b32  	%r403, %r402, -2147483648;
	or.b32  	%r404, %r403, 1123811328;
	mov.b32 	%f1496, %r404;
	selp.f32 	%f1497, %f1496, %f1494, %p175;
	mov.f32 	%f1498, 0fBF317218;
	fma.rn.f32 	%f1499, %f1497, %f1498, %f1491;
	mov.f32 	%f1500, 0f3102E308;
	fma.rn.f32 	%f1501, %f1497, %f1500, %f1499;
	mul.f32 	%f1502, %f1501, 0f3FB8AA3B;
	add.f32 	%f1503, %f1497, 0f4B40007F;
	mov.b32 	%r405, %f1503;
	shl.b32 	%r406, %r405, 23;
	mov.b32 	%f1504, %r406;
	ex2.approx.ftz.f32 	%f1505, %f1502;
	mul.f32 	%f310, %f1505, %f1504;
	setp.eq.f32 	%p176, %f310, 0f7F800000;
	mov.f32 	%f1766, 0f7F800000;
	@%p176 bra 	$L__BB0_136;

	fma.rn.f32 	%f1766, %f310, %f309, %f310;

$L__BB0_136:
	setp.lt.f32 	%p177, %f284, 0f00000000;
	and.pred  	%p10, %p177, %p150;
	setp.eq.f32 	%p179, %f284, 0f00000000;
	@%p179 bra 	$L__BB0_140;
	bra.uni 	$L__BB0_137;

$L__BB0_140:
	add.f32 	%f1510, %f284, %f284;
	selp.f32 	%f1768, %f1510, 0f00000000, %p150;
	bra.uni 	$L__BB0_141;

$L__BB0_137:
	mov.b32 	%r407, %f1766;
	xor.b32  	%r408, %r407, -2147483648;
	mov.b32 	%f1506, %r408;
	selp.f32 	%f1768, %f1506, %f1766, %p10;
	setp.geu.f32 	%p180, %f284, 0f00000000;
	@%p180 bra 	$L__BB0_141;

	mov.f32 	%f1507, 0f3ED55555;
	cvt.rzi.f32.f32 	%f1508, %f1507;
	setp.eq.f32 	%p181, %f1508, 0f3ED55555;
	@%p181 bra 	$L__BB0_141;

	mov.f32 	%f1768, 0f7FFFFFFF;

$L__BB0_141:
	add.f32 	%f1511, %f308, 0f3ED55555;
	mov.b32 	%r409, %f1511;
	setp.lt.s32 	%p183, %r409, 2139095040;
	@%p183 bra 	$L__BB0_146;

	setp.gtu.f32 	%p184, %f308, 0f7F800000;
	@%p184 bra 	$L__BB0_145;
	bra.uni 	$L__BB0_143;

$L__BB0_145:
	add.f32 	%f1768, %f284, 0f3ED55555;
	bra.uni 	$L__BB0_146;

$L__BB0_143:
	setp.neu.f32 	%p185, %f308, 0f7F800000;
	@%p185 bra 	$L__BB0_146;

	selp.f32 	%f1768, 0fFF800000, 0f7F800000, %p10;

$L__BB0_146:
	fma.rn.f32 	%f1512, %f1762, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p186, %f282, 0f3F800000;
	mov.f32 	%f1513, 0f3F800000;
	selp.f32 	%f1514, 0f3F7FFFFF, %f1512, %p186;
	mul.f32 	%f1515, %f282, 0f414EB852;
	setp.lt.f32 	%p187, %f282, 0f3B4D2E1C;
	selp.f32 	%f1516, %f1515, %f1514, %p187;
	fma.rn.f32 	%f1517, %f1765, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p188, %f283, 0f3F800000;
	selp.f32 	%f1518, 0f3F7FFFFF, %f1517, %p188;
	mul.f32 	%f1519, %f283, 0f414EB852;
	setp.lt.f32 	%p189, %f283, 0f3B4D2E1C;
	selp.f32 	%f1520, %f1519, %f1518, %p189;
	fma.rn.f32 	%f1521, %f1768, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p190, %f284, 0f3F800000;
	selp.f32 	%f1522, 0f3F7FFFFF, %f1521, %p190;
	mul.f32 	%f1523, %f284, 0f414EB852;
	setp.lt.f32 	%p191, %f284, 0f3B4D2E1C;
	selp.f32 	%f1524, %f1523, %f1522, %p191;
	min.f32 	%f1525, %f1516, %f1513;
	mov.f32 	%f1526, 0f00000000;
	max.f32 	%f1527, %f1526, %f1525;
	mul.f32 	%f1528, %f1527, 0f43800000;
	cvt.rzi.u32.f32 	%r410, %f1528;
	min.u32 	%r411, %r410, 255;
	min.f32 	%f1529, %f1520, %f1513;
	max.f32 	%f1530, %f1526, %f1529;
	mul.f32 	%f1531, %f1530, 0f43800000;
	cvt.rzi.u32.f32 	%r412, %f1531;
	min.u32 	%r413, %r412, 255;
	min.f32 	%f1532, %f1524, %f1513;
	max.f32 	%f1533, %f1526, %f1532;
	mul.f32 	%f1534, %f1533, 0f43800000;
	cvt.rzi.u32.f32 	%r414, %f1534;
	min.u32 	%r415, %r414, 255;
	shl.b64 	%rd37, %rd10, 2;
	add.s64 	%rd38, %rd9, %rd37;
	cvt.u16.u32 	%rs20, %r415;
	cvt.u16.u32 	%rs21, %r413;
	cvt.u16.u32 	%rs22, %r411;
	mov.u16 	%rs23, 255;
	st.global.v4.u8 	[%rd38], {%rs22, %rs21, %rs20, %rs23};

$L__BB0_147:
	and.b32  	%r416, %r451, 4;
	setp.eq.s32 	%p192, %r416, 0;
	ld.const.u32 	%r452, [params+108];
	@%p192 bra 	$L__BB0_151;

	setp.eq.s32 	%p193, %r452, 0;
	ld.const.u64 	%rd39, [params+224];
	cvta.to.global.u64 	%rd40, %rd39;
	ld.const.u32 	%r417, [params+216];
	mad.lo.s32 	%r418, %r417, %r4, %r3;
	mul.wide.u32 	%rd41, %r418, 8;
	add.s64 	%rd11, %rd40, %rd41;
	@%p193 bra 	$L__BB0_150;

	ld.global.v4.u16 	{%rs31, %rs32, %rs33, %rs34}, [%rd11];
	// begin inline asm
	{  cvt.f32.f16 %f1535, %rs31;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1536, %rs32;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1537, %rs33;}

	// end inline asm
	add.f32 	%f1538, %f1716, %f1535;
	add.f32 	%f1539, %f1717, %f1536;
	add.f32 	%f1540, %f1718, %f1537;
	mov.f32 	%f1541, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1540;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1539;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1538;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f1541;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs27, %rs28, %rs29, %rs30};
	bra.uni 	$L__BB0_151;

$L__BB0_150:
	mov.f32 	%f1545, 0f3F800000;
	mov.u32 	%r452, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f1545;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f1718;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs36, %f1717;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs35, %f1716;}

	// end inline asm
	st.global.v4.u16 	[%rd11], {%rs35, %rs36, %rs37, %rs38};

$L__BB0_151:
	mov.f32 	%f1546, 0f34000000;
	max.f32 	%f1547, %f1719, %f1546;
	div.rn.f32 	%f1548, %f1722, %f1547;
	max.f32 	%f1549, %f1720, %f1546;
	div.rn.f32 	%f1550, %f1723, %f1549;
	max.f32 	%f1551, %f1721, %f1546;
	div.rn.f32 	%f1552, %f1724, %f1551;
	fma.rn.f32 	%f319, %f1548, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f320, %f1550, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f321, %f1552, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1553, %f1725, %f1547;
	div.rn.f32 	%f1554, %f1726, %f1549;
	div.rn.f32 	%f1555, %f1727, %f1551;
	fma.rn.f32 	%f322, %f1553, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f323, %f1554, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f324, %f1555, 0f3F000000, 0f3F000000;
	div.rn.f32 	%f1556, %f1728, %f1547;
	div.rn.f32 	%f1557, %f1729, %f1549;
	div.rn.f32 	%f1558, %f1730, %f1551;
	fma.rn.f32 	%f325, %f1556, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f326, %f1557, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f327, %f1558, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd42, [params+256];
	cvta.to.global.u64 	%rd43, %rd42;
	ld.const.u32 	%r420, [params+248];
	mad.lo.s32 	%r421, %r420, %r4, %r3;
	mul.wide.u32 	%rd44, %r421, 8;
	add.s64 	%rd12, %rd43, %rd44;
	setp.eq.s32 	%p194, %r452, 0;
	@%p194 bra 	$L__BB0_153;

	ld.global.v4.u16 	{%rs46, %rs47, %rs48, %rs49}, [%rd12];
	// begin inline asm
	{  cvt.f32.f16 %f1559, %rs46;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1560, %rs47;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1561, %rs48;}

	// end inline asm
	add.f32 	%f1562, %f1719, %f1559;
	add.f32 	%f1563, %f1720, %f1560;
	add.f32 	%f1564, %f1721, %f1561;
	mov.f32 	%f1565, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs44, %f1564;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs43, %f1563;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs42, %f1562;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f1565;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs42, %rs43, %rs44, %rs45};
	bra.uni 	$L__BB0_154;

$L__BB0_153:
	mov.f32 	%f1569, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f1569;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f1721;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs51, %f1720;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs50, %f1719;}

	// end inline asm
	st.global.v4.u16 	[%rd12], {%rs50, %rs51, %rs52, %rs53};

$L__BB0_154:
	ld.const.u64 	%rd45, [params+272];
	cvta.to.global.u64 	%rd46, %rd45;
	ld.const.u32 	%r422, [params+264];
	mad.lo.s32 	%r423, %r422, %r4, %r3;
	mul.wide.u32 	%rd47, %r423, 8;
	add.s64 	%rd13, %rd46, %rd47;
	@%p194 bra 	$L__BB0_156;

	ld.global.v4.u16 	{%rs61, %rs62, %rs63, %rs64}, [%rd13];
	// begin inline asm
	{  cvt.f32.f16 %f1570, %rs61;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1571, %rs62;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1572, %rs63;}

	// end inline asm
	add.f32 	%f1573, %f319, %f1570;
	add.f32 	%f1574, %f320, %f1571;
	add.f32 	%f1575, %f321, %f1572;
	mov.f32 	%f1576, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs59, %f1575;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs58, %f1574;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs57, %f1573;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f1576;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs57, %rs58, %rs59, %rs60};
	bra.uni 	$L__BB0_157;

$L__BB0_156:
	mov.f32 	%f1580, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1580;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f321;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs66, %f320;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs65, %f319;}

	// end inline asm
	st.global.v4.u16 	[%rd13], {%rs65, %rs66, %rs67, %rs68};

$L__BB0_157:
	ld.const.u64 	%rd48, [params+288];
	cvta.to.global.u64 	%rd49, %rd48;
	ld.const.u32 	%r424, [params+280];
	mad.lo.s32 	%r425, %r424, %r4, %r3;
	mul.wide.u32 	%rd50, %r425, 8;
	add.s64 	%rd14, %rd49, %rd50;
	@%p194 bra 	$L__BB0_159;

	ld.global.v4.u16 	{%rs76, %rs77, %rs78, %rs79}, [%rd14];
	// begin inline asm
	{  cvt.f32.f16 %f1581, %rs76;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1582, %rs77;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1583, %rs78;}

	// end inline asm
	add.f32 	%f1584, %f322, %f1581;
	add.f32 	%f1585, %f323, %f1582;
	add.f32 	%f1586, %f324, %f1583;
	mov.f32 	%f1587, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs74, %f1586;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs73, %f1585;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs72, %f1584;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f1587;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs72, %rs73, %rs74, %rs75};
	bra.uni 	$L__BB0_160;

$L__BB0_159:
	mov.f32 	%f1591, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1591;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f324;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs81, %f323;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs80, %f322;}

	// end inline asm
	st.global.v4.u16 	[%rd14], {%rs80, %rs81, %rs82, %rs83};

$L__BB0_160:
	ld.const.u64 	%rd51, [params+304];
	cvta.to.global.u64 	%rd52, %rd51;
	ld.const.u32 	%r426, [params+296];
	mad.lo.s32 	%r427, %r426, %r4, %r3;
	mul.wide.u32 	%rd53, %r427, 8;
	add.s64 	%rd15, %rd52, %rd53;
	@%p194 bra 	$L__BB0_162;

	ld.global.v4.u16 	{%rs91, %rs92, %rs93, %rs94}, [%rd15];
	// begin inline asm
	{  cvt.f32.f16 %f1592, %rs91;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1593, %rs92;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1594, %rs93;}

	// end inline asm
	add.f32 	%f1595, %f325, %f1592;
	add.f32 	%f1596, %f326, %f1593;
	add.f32 	%f1597, %f327, %f1594;
	mov.f32 	%f1598, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs89, %f1597;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs88, %f1596;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs87, %f1595;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f1598;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs87, %rs88, %rs89, %rs90};
	bra.uni 	$L__BB0_183;

$L__BB0_162:
	mov.f32 	%f1602, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1602;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f327;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f326;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs95, %f325;}

	// end inline asm
	st.global.v4.u16 	[%rd15], {%rs95, %rs96, %rs97, %rs98};

$L__BB0_183:
	ret;

}