//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<155>;
	.reg .b16 	%rs<172>;
	.reg .f32 	%f<1192>;
	.reg .b32 	%r<361>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<109>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r55), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r56), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	ld.const.u64 	%rd29, [params+400];
	cvta.to.global.u64 	%rd30, %rd29;
	ld.const.u32 	%r61, [params+392];
	mad.lo.s32 	%r62, %r61, %r56, %r55;
	mul.wide.u32 	%rd31, %r62, 4;
	add.s64 	%rd2, %rd30, %rd31;
	ld.global.v2.u8 	{%rs7, %rs171}, [%rd2];
	or.b16  	%rs9, %rs7, %rs171;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p7, %rs10, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs170, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs170, [%rd2+2];
	setp.eq.s16 	%p8, %rs170, 0;
	mov.f32 	%f1105, 0f00000000;
	mov.u16 	%rs171, 0;
	mov.f32 	%f1106, %f1105;
	mov.f32 	%f1107, %f1105;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f237, %rs7;
	div.rn.f32 	%f238, %f237, 0f437F0000;
	fma.rn.f32 	%f239, %f238, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs171, 255;
	cvt.rn.f32.u16 	%f240, %rs13;
	div.rn.f32 	%f241, %f240, 0f437F0000;
	fma.rn.f32 	%f242, %f241, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f243, %rs170;
	div.rn.f32 	%f244, %f243, 0f437F0000;
	fma.rn.f32 	%f245, %f244, 0f40000000, 0fBF800000;
	mul.f32 	%f246, %f242, %f242;
	fma.rn.f32 	%f247, %f239, %f239, %f246;
	fma.rn.f32 	%f248, %f245, %f245, %f247;
	sqrt.rn.f32 	%f249, %f248;
	rcp.rn.f32 	%f250, %f249;
	mul.f32 	%f1107, %f250, %f245;
	mul.f32 	%f1106, %f250, %f242;
	mul.f32 	%f1105, %f239, %f250;

$L__BB0_4:
	ld.const.v2.u32 	{%r63, %r64}, [params];
	add.s32 	%r4, %r63, %r55;
	add.s32 	%r5, %r64, %r56;
	setp.eq.f32 	%p9, %f1105, 0f00000000;
	setp.eq.f32 	%p10, %f1106, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1107, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_126;
	bra.uni 	$L__BB0_5;

$L__BB0_126:
	ld.const.u32 	%r52, [params+104];
	and.b32  	%r314, %r52, 1;
	setp.eq.b32 	%p144, %r314, 1;
	mov.pred 	%p145, 0;
	xor.pred  	%p146, %p144, %p145;
	not.pred 	%p147, %p146;
	@%p147 bra 	$L__BB0_128;

	ld.const.u64 	%rd82, [params+144];
	cvta.to.global.u64 	%rd83, %rd82;
	ld.const.u32 	%r315, [params+136];
	mad.lo.s32 	%r316, %r315, %r5, %r4;
	mul.wide.u32 	%rd84, %r316, 4;
	add.s64 	%rd85, %rd83, %rd84;
	mov.u16 	%rs94, 0;
	st.global.v4.u8 	[%rd85], {%rs94, %rs94, %rs94, %rs94};

$L__BB0_128:
	and.b32  	%r317, %r52, 4;
	setp.eq.s32 	%p148, %r317, 0;
	ld.const.u32 	%r360, [params+108];
	@%p148 bra 	$L__BB0_132;

	setp.eq.s32 	%p149, %r360, 0;
	ld.const.u64 	%rd86, [params+224];
	cvta.to.global.u64 	%rd87, %rd86;
	ld.const.u32 	%r318, [params+216];
	mad.lo.s32 	%r319, %r318, %r5, %r4;
	mul.wide.u32 	%rd88, %r319, 8;
	add.s64 	%rd23, %rd87, %rd88;
	@%p149 bra 	$L__BB0_131;

	ld.global.v4.u16 	{%rs101, %rs102, %rs103, %rs104}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1014, %rs101;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1015, %rs102;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1016, %rs103;}

	// end inline asm
	add.f32 	%f1017, %f1014, 0f00000000;
	add.f32 	%f1018, %f1015, 0f00000000;
	add.f32 	%f1019, %f1016, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1019;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs99, %f1018;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1017;}

	// end inline asm
	mov.u16 	%rs105, 0;
	st.global.v4.u16 	[%rd23], {%rs98, %rs99, %rs100, %rs105};
	bra.uni 	$L__BB0_132;

$L__BB0_5:
	ld.const.u64 	%rd32, [params+432];
	cvta.to.global.u64 	%rd33, %rd32;
	ld.const.u32 	%r67, [params+424];
	mad.lo.s32 	%r68, %r67, %r56, %r55;
	mul.wide.u32 	%rd34, %r68, 12;
	add.s64 	%rd35, %rd33, %rd34;
	ld.global.f32 	%f266, [%rd35];
	mul.f32 	%f267, %f266, 0f3456BF95;
	ld.global.f32 	%f268, [%rd35+4];
	mul.f32 	%f269, %f268, 0f3456BF95;
	ld.global.f32 	%f270, [%rd35+8];
	mul.f32 	%f271, %f270, 0f3456BF95;
	abs.f32 	%f272, %f1105;
	div.rn.f32 	%f273, %f267, %f272;
	abs.f32 	%f274, %f1106;
	div.rn.f32 	%f275, %f269, %f274;
	abs.f32 	%f276, %f1107;
	div.rn.f32 	%f277, %f271, %f276;
	abs.f32 	%f278, %f273;
	abs.f32 	%f279, %f275;
	abs.f32 	%f280, %f277;
	mov.f32 	%f281, 0f38D1B717;
	max.f32 	%f282, %f278, %f281;
	max.f32 	%f283, %f279, %f281;
	max.f32 	%f284, %f280, %f281;
	fma.rn.f32 	%f10, %f1105, %f282, %f266;
	fma.rn.f32 	%f11, %f1106, %f283, %f268;
	fma.rn.f32 	%f12, %f1107, %f284, %f270;
	setp.gt.f32 	%p14, %f272, %f276;
	neg.f32 	%f285, %f1106;
	selp.f32 	%f286, %f285, 0f00000000, %p14;
	mov.f32 	%f1144, 0f00000000;
	neg.f32 	%f287, %f1107;
	selp.f32 	%f288, %f1105, %f287, %p14;
	selp.f32 	%f289, 0f00000000, %f1106, %p14;
	mul.f32 	%f290, %f288, %f288;
	fma.rn.f32 	%f291, %f286, %f286, %f290;
	fma.rn.f32 	%f292, %f289, %f289, %f291;
	sqrt.rn.f32 	%f293, %f292;
	rcp.rn.f32 	%f294, %f293;
	mul.f32 	%f13, %f286, %f294;
	mul.f32 	%f14, %f288, %f294;
	mul.f32 	%f15, %f289, %f294;
	ld.const.u64 	%rd36, [params+128];
	cvta.to.global.u64 	%rd37, %rd36;
	ld.const.u32 	%r69, [params+120];
	mad.lo.s32 	%r70, %r69, %r56, %r55;
	mul.wide.u32 	%rd38, %r70, 4;
	add.s64 	%rd3, %rd37, %rd38;
	setp.lt.s32 	%p15, %r3, 1;
	mov.f32 	%f1145, %f1144;
	mov.f32 	%f1146, %f1144;
	mov.f32 	%f1147, %f1144;
	mov.f32 	%f1148, %f1144;
	mov.f32 	%f1149, %f1144;
	mov.f32 	%f1150, %f1144;
	mov.f32 	%f1151, %f1144;
	mov.f32 	%f1152, %f1144;
	mov.f32 	%f1153, %f1144;
	mov.f32 	%f1154, %f1144;
	mov.f32 	%f1155, %f1144;
	mov.f32 	%f1156, %f1144;
	mov.f32 	%f1157, %f1144;
	mov.f32 	%f1158, %f1144;
	@%p15 bra 	$L__BB0_36;

	ld.const.u32 	%r6, [params+588];
	cvt.rn.f32.s32 	%f310, %r3;
	rcp.rn.f32 	%f16, %f310;
	ld.global.u32 	%r351, [%rd3];
	mul.f32 	%f17, %f10, 0f3456BF95;
	mul.f32 	%f18, %f11, 0f3456BF95;
	mul.f32 	%f19, %f12, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f311, %f1105, %f14;
	mul.f32 	%f312, %f1106, %f13;
	sub.f32 	%f20, %f312, %f311;
	mul.f32 	%f313, %f1107, %f13;
	mul.f32 	%f314, %f1105, %f15;
	sub.f32 	%f21, %f314, %f313;
	mul.f32 	%f315, %f1106, %f15;
	mul.f32 	%f316, %f1107, %f14;
	sub.f32 	%f22, %f316, %f315;
	mov.u32 	%r71, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd39, __cudart_i2opi_f;
	abs.f32 	%f379, %f17;
	abs.f32 	%f380, %f18;
	max.f32 	%f381, %f379, %f380;
	abs.f32 	%f382, %f19;
	max.f32 	%f383, %f381, %f382;
	mov.u32 	%r348, %r71;

$L__BB0_7:
	mov.u32 	%r350, %r71;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1060, %r348;
	mad.lo.s32 	%r73, %r351, 1664525, 1013904223;
	and.b32  	%r74, %r73, 16777215;
	cvt.rn.f32.u32 	%f317, %r74;
	fma.rn.f32 	%f318, %f317, 0f33800000, %f1060;
	mul.f32 	%f54, %f16, %f318;
	mad.lo.s32 	%r351, %r73, 1664525, 1013904223;
	and.b32  	%r75, %r351, 16777215;
	cvt.rn.f32.u32 	%f319, %r75;
	cvt.rn.f32.s32 	%f320, %r350;
	fma.rn.f32 	%f321, %f319, 0f33800000, %f320;
	mul.f32 	%f322, %f16, %f321;
	mul.f32 	%f323, %f54, %f54;
	mov.f32 	%f324, 0f3F800000;
	sub.f32 	%f325, %f324, %f323;
	mov.f32 	%f326, 0f00000000;
	max.f32 	%f327, %f326, %f325;
	sqrt.rn.f32 	%f55, %f327;
	mul.f32 	%f56, %f322, 0f40C90FDB;
	mul.f32 	%f328, %f56, 0f3F22F983;
	cvt.rni.s32.f32 	%r355, %f328;
	cvt.rn.f32.s32 	%f329, %r355;
	mov.f32 	%f330, 0fBFC90FDA;
	fma.rn.f32 	%f331, %f329, %f330, %f56;
	mov.f32 	%f332, 0fB3A22168;
	fma.rn.f32 	%f333, %f329, %f332, %f331;
	mov.f32 	%f334, 0fA7C234C5;
	fma.rn.f32 	%f1141, %f329, %f334, %f333;
	abs.f32 	%f58, %f56;
	setp.ltu.f32 	%p16, %f58, 0f47CE4780;
	mov.f32 	%f1138, %f1141;
	@%p16 bra 	$L__BB0_16;

	setp.eq.f32 	%p17, %f58, 0f7F800000;
	@%p17 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f337, 0f00000000;
	mul.rn.f32 	%f1138, %f56, %f337;
	mov.u32 	%r355, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r14, %f56;
	bfe.u32 	%r77, %r14, 23, 8;
	mov.u64 	%rd106, 0;
	mov.u32 	%r352, 0;
	mov.u64 	%rd104, %rd1;
	mov.u64 	%rd105, %rd39;

$L__BB0_11:
	.pragma "nounroll";
	mov.b32 	%r331, %f56;
	shl.b32 	%r330, %r331, 8;
	or.b32  	%r329, %r330, -2147483648;
	ld.global.nc.u32 	%r79, [%rd105];
	mad.wide.u32 	%rd41, %r79, %r329, %rd106;
	shr.u64 	%rd106, %rd41, 32;
	st.local.u32 	[%rd104], %rd41;
	add.s64 	%rd105, %rd105, 4;
	add.s64 	%rd104, %rd104, 4;
	add.s32 	%r352, %r352, 1;
	setp.ne.s32 	%p18, %r352, 6;
	@%p18 bra 	$L__BB0_11;

	add.s32 	%r336, %r77, -128;
	mov.b32 	%r335, %f56;
	bfe.u32 	%r334, %r335, 23, 8;
	add.s32 	%r333, %r334, -128;
	shr.u32 	%r332, %r333, 5;
	st.local.u32 	[%rd5], %rd106;
	mov.u32 	%r81, 6;
	sub.s32 	%r82, %r81, %r332;
	mul.wide.s32 	%rd42, %r82, 4;
	add.s64 	%rd43, %rd1, %rd42;
	ld.local.u32 	%r353, [%rd43];
	ld.local.u32 	%r354, [%rd43+-4];
	and.b32  	%r23, %r333, 31;
	setp.eq.s32 	%p19, %r23, 0;
	@%p19 bra 	$L__BB0_14;

	mov.b32 	%r344, %f56;
	bfe.u32 	%r343, %r344, 23, 8;
	add.s32 	%r342, %r343, -128;
	shr.u32 	%r341, %r342, 5;
	mov.u32 	%r340, 4;
	sub.s32 	%r339, %r340, %r341;
	mov.u32 	%r83, 32;
	sub.s32 	%r84, %r83, %r23;
	shr.u32 	%r85, %r354, %r84;
	shl.b32 	%r86, %r353, %r23;
	add.s32 	%r353, %r85, %r86;
	mul.wide.s32 	%rd44, %r339, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r87, [%rd45];
	shr.u32 	%r88, %r87, %r84;
	shl.b32 	%r89, %r354, %r23;
	add.s32 	%r354, %r88, %r89;

$L__BB0_14:
	mov.b32 	%r337, %f56;
	and.b32  	%r90, %r337, -2147483648;
	shr.u32 	%r91, %r354, 30;
	shl.b32 	%r92, %r353, 2;
	or.b32  	%r93, %r91, %r92;
	shr.u32 	%r94, %r93, 31;
	shr.u32 	%r95, %r353, 30;
	add.s32 	%r96, %r94, %r95;
	neg.s32 	%r97, %r96;
	setp.eq.s32 	%p20, %r90, 0;
	selp.b32 	%r355, %r96, %r97, %p20;
	setp.ne.s32 	%p21, %r94, 0;
	xor.b32  	%r98, %r90, -2147483648;
	selp.b32 	%r99, %r98, %r90, %p21;
	selp.b32 	%r100, -1, 0, %p21;
	xor.b32  	%r101, %r93, %r100;
	shl.b32 	%r102, %r354, 2;
	xor.b32  	%r103, %r102, %r100;
	cvt.u64.u32 	%rd46, %r101;
	cvt.u64.u32 	%rd47, %r103;
	bfi.b64 	%rd48, %rd46, %rd47, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd48;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f335, %fd2;
	setp.eq.s32 	%p22, %r99, 0;
	neg.f32 	%f336, %f335;
	selp.f32 	%f1138, %f335, %f336, %p22;

$L__BB0_16:
	add.s32 	%r30, %r355, 1;
	and.b32  	%r31, %r30, 1;
	setp.eq.s32 	%p23, %r31, 0;
	selp.f32 	%f62, %f1138, 0f3F800000, %p23;
	mul.rn.f32 	%f63, %f1138, %f1138;
	mov.f32 	%f1139, 0fB94D4153;
	@%p23 bra 	$L__BB0_18;

	mov.f32 	%f339, 0fBAB607ED;
	mov.f32 	%f340, 0f37CBAC00;
	fma.rn.f32 	%f1139, %f340, %f63, %f339;

$L__BB0_18:
	selp.f32 	%f341, 0f3C0885E4, 0f3D2AAABB, %p23;
	fma.rn.f32 	%f342, %f1139, %f63, %f341;
	selp.f32 	%f343, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
	fma.rn.f32 	%f344, %f342, %f63, %f343;
	mov.f32 	%f345, 0f00000000;
	fma.rn.f32 	%f346, %f63, %f62, %f345;
	fma.rn.f32 	%f1140, %f344, %f346, %f62;
	and.b32  	%r105, %r30, 2;
	setp.eq.s32 	%p25, %r105, 0;
	@%p25 bra 	$L__BB0_20;

	mov.f32 	%f348, 0fBF800000;
	fma.rn.f32 	%f1140, %f1140, %f348, %f345;

$L__BB0_20:
	mul.f32 	%f1059, %f56, 0f3F22F983;
	cvt.rni.s32.f32 	%r358, %f1059;
	setp.ltu.f32 	%p154, %f58, 0f47CE4780;
	@%p154 bra 	$L__BB0_28;

	setp.eq.f32 	%p27, %f58, 0f7F800000;
	@%p27 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f351, 0f00000000;
	mul.rn.f32 	%f1141, %f56, %f351;
	mov.u32 	%r358, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r32, %f56;
	bfe.u32 	%r106, %r32, 23, 8;
	add.s32 	%r33, %r106, -128;
	shl.b32 	%r107, %r32, 8;
	or.b32  	%r34, %r107, -2147483648;
	shr.u32 	%r35, %r33, 5;
	mov.u64 	%rd107, 0;
	mov.u64 	%rd108, %rd107;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd51, %rd107, 2;
	mov.u64 	%rd52, __cudart_i2opi_f;
	add.s64 	%rd53, %rd52, %rd51;
	ld.global.nc.u32 	%r108, [%rd53];
	mad.wide.u32 	%rd54, %r108, %r34, %rd108;
	shr.u64 	%rd108, %rd54, 32;
	add.s64 	%rd55, %rd1, %rd51;
	st.local.u32 	[%rd55], %rd54;
	cvt.u32.u64 	%r109, %rd107;
	add.s32 	%r110, %r109, 1;
	cvt.s64.s32 	%rd107, %r110;
	setp.ne.s32 	%p28, %r110, 6;
	@%p28 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd108;
	mov.u32 	%r111, 4;
	sub.s32 	%r36, %r111, %r35;
	mov.u32 	%r112, 6;
	sub.s32 	%r113, %r112, %r35;
	mul.wide.s32 	%rd56, %r113, 4;
	add.s64 	%rd57, %rd1, %rd56;
	ld.local.u32 	%r356, [%rd57];
	ld.local.u32 	%r357, [%rd57+-4];
	and.b32  	%r39, %r33, 31;
	setp.eq.s32 	%p29, %r39, 0;
	@%p29 bra 	$L__BB0_26;

	mov.u32 	%r114, 32;
	sub.s32 	%r115, %r114, %r39;
	shr.u32 	%r116, %r357, %r115;
	shl.b32 	%r117, %r356, %r39;
	add.s32 	%r356, %r116, %r117;
	mul.wide.s32 	%rd58, %r36, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r118, [%rd59];
	shr.u32 	%r119, %r118, %r115;
	shl.b32 	%r120, %r357, %r39;
	add.s32 	%r357, %r119, %r120;

$L__BB0_26:
	and.b32  	%r121, %r32, -2147483648;
	shr.u32 	%r122, %r357, 30;
	shl.b32 	%r123, %r356, 2;
	or.b32  	%r124, %r122, %r123;
	shr.u32 	%r125, %r124, 31;
	shr.u32 	%r126, %r356, 30;
	add.s32 	%r127, %r125, %r126;
	neg.s32 	%r128, %r127;
	setp.eq.s32 	%p30, %r121, 0;
	selp.b32 	%r358, %r127, %r128, %p30;
	setp.ne.s32 	%p31, %r125, 0;
	xor.b32  	%r129, %r121, -2147483648;
	selp.b32 	%r130, %r129, %r121, %p31;
	selp.b32 	%r131, -1, 0, %p31;
	xor.b32  	%r132, %r124, %r131;
	shl.b32 	%r133, %r357, 2;
	xor.b32  	%r134, %r133, %r131;
	cvt.u64.u32 	%rd60, %r132;
	cvt.u64.u32 	%rd61, %r134;
	bfi.b64 	%rd62, %rd60, %rd61, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd62;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f349, %fd4;
	setp.eq.s32 	%p32, %r130, 0;
	neg.f32 	%f350, %f349;
	selp.f32 	%f1141, %f349, %f350, %p32;

$L__BB0_28:
	mul.f32 	%f72, %f55, %f1140;
	and.b32  	%r46, %r358, 1;
	setp.eq.s32 	%p33, %r46, 0;
	mul.rn.f32 	%f74, %f1141, %f1141;
	mov.f32 	%f1142, 0fB94D4153;
	@%p33 bra 	$L__BB0_30;

	mov.f32 	%f353, 0fBAB607ED;
	mov.f32 	%f354, 0f37CBAC00;
	fma.rn.f32 	%f1142, %f354, %f74, %f353;

$L__BB0_30:
	selp.f32 	%f1061, %f1141, 0f3F800000, %p33;
	selp.f32 	%f355, 0f3C0885E4, 0f3D2AAABB, %p33;
	fma.rn.f32 	%f356, %f1142, %f74, %f355;
	selp.f32 	%f357, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
	fma.rn.f32 	%f358, %f356, %f74, %f357;
	mov.f32 	%f359, 0f00000000;
	fma.rn.f32 	%f360, %f74, %f1061, %f359;
	fma.rn.f32 	%f1143, %f358, %f360, %f1061;
	and.b32  	%r136, %r358, 2;
	setp.eq.s32 	%p35, %r136, 0;
	@%p35 bra 	$L__BB0_32;

	mov.f32 	%f362, 0fBF800000;
	fma.rn.f32 	%f1143, %f1143, %f362, %f359;

$L__BB0_32:
	mul.f32 	%f363, %f55, %f1143;
	mul.f32 	%f364, %f13, %f363;
	mul.f32 	%f365, %f14, %f363;
	mul.f32 	%f366, %f15, %f363;
	fma.rn.f32 	%f367, %f22, %f72, %f364;
	fma.rn.f32 	%f368, %f21, %f72, %f365;
	fma.rn.f32 	%f369, %f20, %f72, %f366;
	fma.rn.f32 	%f80, %f1105, %f54, %f367;
	fma.rn.f32 	%f81, %f1106, %f54, %f368;
	fma.rn.f32 	%f82, %f1107, %f54, %f369;
	setp.leu.f32 	%p36, %f81, 0f00000000;
	setp.ne.s32 	%p37, %r6, 0;
	and.pred  	%p38, %p37, %p36;
	@%p38 bra 	$L__BB0_34;

	mov.f32 	%f384, 0f38D1B717;
	max.f32 	%f376, %f383, %f384;
	mov.f32 	%f377, 0f6C4ECB8F;
	mov.f32 	%f378, 0f00000000;
	mov.u32 	%r173, 2;
	mov.u32 	%r174, 1;
	mov.u32 	%r175, 3;
	mov.u32 	%r178, 1065353216;
	mov.u32 	%r207, 0;
	// begin inline asm
	call(%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168),_optix_trace_typed_32,(%r207,%rd4,%f10,%f11,%f12,%f80,%f81,%f82,%f376,%f377,%f378,%r174,%r207,%r174,%r173,%r174,%r175,%r178,%r178,%r178,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207);
	// end inline asm
	mov.b32 	%f385, %r137;
	mov.b32 	%f386, %r138;
	mov.b32 	%f387, %r139;
	mul.f32 	%f388, %f1106, %f81;
	fma.rn.f32 	%f389, %f1105, %f80, %f388;
	fma.rn.f32 	%f390, %f1107, %f82, %f389;
	mul.f32 	%f391, %f390, 0f40800000;
	cvt.sat.f32.f32 	%f392, %f391;
	mul.f32 	%f393, %f392, %f385;
	mul.f32 	%f394, %f392, %f386;
	mul.f32 	%f395, %f392, %f387;
	fma.rn.f32 	%f1150, %f80, %f393, %f1150;
	fma.rn.f32 	%f1151, %f80, %f394, %f1151;
	fma.rn.f32 	%f1152, %f80, %f395, %f1152;
	fma.rn.f32 	%f1147, %f81, %f393, %f1147;
	fma.rn.f32 	%f1148, %f81, %f394, %f1148;
	fma.rn.f32 	%f1149, %f81, %f395, %f1149;
	fma.rn.f32 	%f1144, %f82, %f393, %f1144;
	fma.rn.f32 	%f1145, %f82, %f394, %f1145;
	fma.rn.f32 	%f1146, %f82, %f395, %f1146;
	add.f32 	%f1153, %f1153, %f393;
	add.f32 	%f1154, %f1154, %f394;
	add.f32 	%f1155, %f1155, %f395;
	cvt.sat.f32.f32 	%f396, %f390;
	fma.rn.f32 	%f1156, %f396, %f385, %f1156;
	fma.rn.f32 	%f1157, %f396, %f386, %f1157;
	fma.rn.f32 	%f1158, %f396, %f387, %f1158;

$L__BB0_34:
	add.s32 	%r350, %r350, 1;
	setp.lt.s32 	%p39, %r350, %r3;
	@%p39 bra 	$L__BB0_8;

	add.s32 	%r348, %r348, 1;
	setp.lt.s32 	%p40, %r348, %r3;
	@%p40 bra 	$L__BB0_7;

$L__BB0_36:
	mul.lo.s32 	%r208, %r3, %r3;
	cvt.rn.f32.s32 	%f397, %r208;
	rcp.rn.f32 	%f398, %f397;
	mul.f32 	%f399, %f398, %f1156;
	mul.f32 	%f400, %f398, %f1157;
	mul.f32 	%f401, %f398, %f1158;
	mul.f32 	%f128, %f398, %f1153;
	mul.f32 	%f129, %f398, %f1154;
	mul.f32 	%f130, %f398, %f1155;
	mul.f32 	%f131, %f398, %f1150;
	mul.f32 	%f132, %f398, %f1151;
	mul.f32 	%f133, %f398, %f1152;
	mul.f32 	%f134, %f398, %f1147;
	mul.f32 	%f135, %f398, %f1148;
	mul.f32 	%f136, %f398, %f1149;
	mul.f32 	%f137, %f398, %f1144;
	mul.f32 	%f138, %f398, %f1145;
	mul.f32 	%f139, %f398, %f1146;
	fma.rn.f32 	%f402, %f398, %f1156, %f399;
	fma.rn.f32 	%f403, %f398, %f1157, %f400;
	fma.rn.f32 	%f404, %f398, %f1158, %f401;
	ld.const.v4.f32 	{%f405, %f406, %f407, %f408}, [params+576];
	mul.f32 	%f143, %f402, %f405;
	mul.f32 	%f144, %f403, %f406;
	mul.f32 	%f145, %f404, %f407;
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r209, %r49, 1;
	setp.eq.b32 	%p41, %r209, 1;
	mov.pred 	%p42, 0;
	xor.pred  	%p43, %p41, %p42;
	not.pred 	%p44, %p43;
	@%p44 bra 	$L__BB0_110;

	mov.f32 	%f410, 0f3E666666;
	cvt.rzi.f32.f32 	%f411, %f410;
	add.f32 	%f412, %f411, %f411;
	mov.f32 	%f413, 0f3EE66666;
	sub.f32 	%f414, %f413, %f412;
	abs.f32 	%f146, %f414;
	abs.f32 	%f147, %f143;
	setp.lt.f32 	%p45, %f147, 0f00800000;
	mul.f32 	%f415, %f147, 0f4B800000;
	selp.f32 	%f416, %f415, %f147, %p45;
	selp.f32 	%f417, 0fC3170000, 0fC2FE0000, %p45;
	mov.b32 	%r210, %f416;
	and.b32  	%r211, %r210, 8388607;
	or.b32  	%r212, %r211, 1065353216;
	mov.b32 	%f418, %r212;
	shr.u32 	%r213, %r210, 23;
	cvt.rn.f32.u32 	%f419, %r213;
	add.f32 	%f420, %f417, %f419;
	setp.gt.f32 	%p46, %f418, 0f3FB504F3;
	mul.f32 	%f421, %f418, 0f3F000000;
	add.f32 	%f422, %f420, 0f3F800000;
	selp.f32 	%f423, %f422, %f420, %p46;
	selp.f32 	%f424, %f421, %f418, %p46;
	add.f32 	%f425, %f424, 0fBF800000;
	add.f32 	%f426, %f424, 0f3F800000;
	rcp.approx.ftz.f32 	%f427, %f426;
	add.f32 	%f428, %f425, %f425;
	mul.f32 	%f429, %f428, %f427;
	mul.f32 	%f430, %f429, %f429;
	mov.f32 	%f431, 0f3C4CAF63;
	mov.f32 	%f432, 0f3B18F0FE;
	fma.rn.f32 	%f433, %f432, %f430, %f431;
	mov.f32 	%f434, 0f3DAAAABD;
	fma.rn.f32 	%f435, %f433, %f430, %f434;
	mul.rn.f32 	%f436, %f435, %f430;
	mul.rn.f32 	%f437, %f436, %f429;
	sub.f32 	%f438, %f425, %f429;
	add.f32 	%f439, %f438, %f438;
	neg.f32 	%f440, %f429;
	fma.rn.f32 	%f441, %f440, %f425, %f439;
	mul.rn.f32 	%f442, %f427, %f441;
	add.f32 	%f443, %f437, %f429;
	sub.f32 	%f444, %f429, %f443;
	add.f32 	%f445, %f437, %f444;
	add.f32 	%f446, %f442, %f445;
	add.f32 	%f447, %f443, %f446;
	sub.f32 	%f448, %f443, %f447;
	add.f32 	%f449, %f446, %f448;
	mov.f32 	%f450, 0f3F317200;
	mul.rn.f32 	%f451, %f423, %f450;
	mov.f32 	%f452, 0f35BFBE8E;
	mul.rn.f32 	%f453, %f423, %f452;
	add.f32 	%f454, %f451, %f447;
	sub.f32 	%f455, %f451, %f454;
	add.f32 	%f456, %f447, %f455;
	add.f32 	%f457, %f449, %f456;
	add.f32 	%f458, %f453, %f457;
	add.f32 	%f459, %f454, %f458;
	sub.f32 	%f460, %f454, %f459;
	add.f32 	%f461, %f458, %f460;
	mul.rn.f32 	%f462, %f413, %f459;
	neg.f32 	%f463, %f462;
	fma.rn.f32 	%f464, %f413, %f459, %f463;
	fma.rn.f32 	%f465, %f413, %f461, %f464;
	mov.f32 	%f466, 0f00000000;
	fma.rn.f32 	%f467, %f466, %f459, %f465;
	add.rn.f32 	%f468, %f462, %f467;
	neg.f32 	%f469, %f468;
	add.rn.f32 	%f470, %f462, %f469;
	add.rn.f32 	%f471, %f470, %f467;
	mov.b32 	%r214, %f468;
	setp.eq.s32 	%p47, %r214, 1118925336;
	add.s32 	%r215, %r214, -1;
	mov.b32 	%f472, %r215;
	add.f32 	%f473, %f471, 0f37000000;
	selp.f32 	%f148, %f473, %f471, %p47;
	selp.f32 	%f474, %f472, %f468, %p47;
	mov.f32 	%f475, 0f3FB8AA3B;
	mul.rn.f32 	%f476, %f474, %f475;
	cvt.rzi.f32.f32 	%f477, %f476;
	abs.f32 	%f478, %f477;
	setp.gt.f32 	%p48, %f478, 0f42FC0000;
	mov.b32 	%r216, %f477;
	and.b32  	%r217, %r216, -2147483648;
	or.b32  	%r218, %r217, 1123811328;
	mov.b32 	%f479, %r218;
	selp.f32 	%f480, %f479, %f477, %p48;
	mov.f32 	%f481, 0fBF317218;
	fma.rn.f32 	%f482, %f480, %f481, %f474;
	mov.f32 	%f483, 0f3102E308;
	fma.rn.f32 	%f484, %f480, %f483, %f482;
	mul.f32 	%f485, %f484, 0f3FB8AA3B;
	add.f32 	%f486, %f480, 0f4B40007F;
	mov.b32 	%r219, %f486;
	shl.b32 	%r220, %r219, 23;
	mov.b32 	%f487, %r220;
	ex2.approx.ftz.f32 	%f488, %f485;
	mul.f32 	%f149, %f488, %f487;
	setp.eq.f32 	%p49, %f149, 0f7F800000;
	mov.f32 	%f1174, 0f7F800000;
	@%p49 bra 	$L__BB0_39;

	fma.rn.f32 	%f1174, %f149, %f148, %f149;

$L__BB0_39:
	setp.lt.f32 	%p50, %f143, 0f00000000;
	setp.eq.f32 	%p51, %f146, 0f3F800000;
	and.pred  	%p1, %p50, %p51;
	setp.eq.f32 	%p52, %f143, 0f00000000;
	@%p52 bra 	$L__BB0_43;
	bra.uni 	$L__BB0_40;

$L__BB0_43:
	add.f32 	%f493, %f143, %f143;
	selp.f32 	%f1176, %f493, 0f00000000, %p51;
	bra.uni 	$L__BB0_44;

$L__BB0_131:
	mov.f32 	%f1022, 0f00000000;
	mov.u32 	%r360, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f1022;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1022;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs106, %f1022;}

	// end inline asm
	mov.u16 	%rs109, 0;
	st.global.v4.u16 	[%rd23], {%rs106, %rs107, %rs108, %rs109};

$L__BB0_132:
	ld.const.u64 	%rd89, [params+256];
	cvta.to.global.u64 	%rd90, %rd89;
	ld.const.u32 	%r321, [params+248];
	mad.lo.s32 	%r322, %r321, %r5, %r4;
	mul.wide.u32 	%rd91, %r322, 8;
	add.s64 	%rd24, %rd90, %rd91;
	setp.eq.s32 	%p150, %r360, 0;
	@%p150 bra 	$L__BB0_134;

	ld.global.v4.u16 	{%rs116, %rs117, %rs118, %rs119}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1023, %rs116;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1024, %rs117;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1025, %rs118;}

	// end inline asm
	add.f32 	%f1026, %f1023, 0f00000000;
	add.f32 	%f1027, %f1024, 0f00000000;
	add.f32 	%f1028, %f1025, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1028;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs114, %f1027;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs113, %f1026;}

	// end inline asm
	mov.u16 	%rs120, 0;
	st.global.v4.u16 	[%rd24], {%rs113, %rs114, %rs115, %rs120};
	bra.uni 	$L__BB0_135;

$L__BB0_134:
	mov.f32 	%f1031, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs121, %f1031;}

	// end inline asm
	mov.u16 	%rs124, 0;
	st.global.v4.u16 	[%rd24], {%rs121, %rs122, %rs123, %rs124};

$L__BB0_135:
	ld.const.u64 	%rd92, [params+272];
	cvta.to.global.u64 	%rd93, %rd92;
	ld.const.u32 	%r323, [params+264];
	mad.lo.s32 	%r324, %r323, %r5, %r4;
	mul.wide.u32 	%rd94, %r324, 8;
	add.s64 	%rd25, %rd93, %rd94;
	@%p150 bra 	$L__BB0_137;

	ld.global.v4.u16 	{%rs131, %rs132, %rs133, %rs134}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1032, %rs131;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1033, %rs132;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1034, %rs133;}

	// end inline asm
	add.f32 	%f1035, %f1032, 0f00000000;
	add.f32 	%f1036, %f1033, 0f00000000;
	add.f32 	%f1037, %f1034, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1037;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs129, %f1036;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs128, %f1035;}

	// end inline asm
	mov.u16 	%rs135, 0;
	st.global.v4.u16 	[%rd25], {%rs128, %rs129, %rs130, %rs135};
	bra.uni 	$L__BB0_138;

$L__BB0_137:
	mov.f32 	%f1040, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs136, %f1040;}

	// end inline asm
	mov.u16 	%rs139, 0;
	st.global.v4.u16 	[%rd25], {%rs136, %rs137, %rs138, %rs139};

$L__BB0_138:
	ld.const.u64 	%rd95, [params+288];
	cvta.to.global.u64 	%rd96, %rd95;
	ld.const.u32 	%r325, [params+280];
	mad.lo.s32 	%r326, %r325, %r5, %r4;
	mul.wide.u32 	%rd97, %r326, 8;
	add.s64 	%rd26, %rd96, %rd97;
	@%p150 bra 	$L__BB0_140;

	ld.global.v4.u16 	{%rs146, %rs147, %rs148, %rs149}, [%rd26];
	// begin inline asm
	{  cvt.f32.f16 %f1041, %rs146;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1042, %rs147;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1043, %rs148;}

	// end inline asm
	add.f32 	%f1044, %f1041, 0f00000000;
	add.f32 	%f1045, %f1042, 0f00000000;
	add.f32 	%f1046, %f1043, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1046;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs144, %f1045;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs143, %f1044;}

	// end inline asm
	mov.u16 	%rs150, 0;
	st.global.v4.u16 	[%rd26], {%rs143, %rs144, %rs145, %rs150};
	bra.uni 	$L__BB0_141;

$L__BB0_140:
	mov.f32 	%f1049, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f1049;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1049;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs151, %f1049;}

	// end inline asm
	mov.u16 	%rs154, 0;
	st.global.v4.u16 	[%rd26], {%rs151, %rs152, %rs153, %rs154};

$L__BB0_141:
	ld.const.u64 	%rd98, [params+304];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r327, [params+296];
	mad.lo.s32 	%r328, %r327, %r5, %r4;
	mul.wide.u32 	%rd100, %r328, 8;
	add.s64 	%rd27, %rd99, %rd100;
	@%p150 bra 	$L__BB0_143;

	ld.global.v4.u16 	{%rs161, %rs162, %rs163, %rs164}, [%rd27];
	// begin inline asm
	{  cvt.f32.f16 %f1050, %rs161;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1051, %rs162;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1052, %rs163;}

	// end inline asm
	add.f32 	%f1053, %f1050, 0f00000000;
	add.f32 	%f1054, %f1051, 0f00000000;
	add.f32 	%f1055, %f1052, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1055;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs159, %f1054;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs158, %f1053;}

	// end inline asm
	mov.u16 	%rs165, 0;
	st.global.v4.u16 	[%rd27], {%rs158, %rs159, %rs160, %rs165};
	bra.uni 	$L__BB0_144;

$L__BB0_143:
	mov.f32 	%f1058, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs168, %f1058;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs167, %f1058;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs166, %f1058;}

	// end inline asm
	mov.u16 	%rs169, 0;
	st.global.v4.u16 	[%rd27], {%rs166, %rs167, %rs168, %rs169};
	bra.uni 	$L__BB0_144;

$L__BB0_40:
	mov.b32 	%r221, %f1174;
	xor.b32  	%r222, %r221, -2147483648;
	mov.b32 	%f489, %r222;
	selp.f32 	%f1176, %f489, %f1174, %p1;
	setp.geu.f32 	%p53, %f143, 0f00000000;
	@%p53 bra 	$L__BB0_44;

	mov.f32 	%f490, 0f3EE66666;
	cvt.rzi.f32.f32 	%f491, %f490;
	setp.eq.f32 	%p54, %f491, 0f3EE66666;
	@%p54 bra 	$L__BB0_44;

	mov.f32 	%f1176, 0f7FFFFFFF;

$L__BB0_44:
	add.f32 	%f494, %f147, 0f3EE66666;
	mov.b32 	%r223, %f494;
	setp.lt.s32 	%p56, %r223, 2139095040;
	@%p56 bra 	$L__BB0_49;

	setp.gtu.f32 	%p57, %f147, 0f7F800000;
	@%p57 bra 	$L__BB0_48;
	bra.uni 	$L__BB0_46;

$L__BB0_48:
	add.f32 	%f1176, %f143, 0f3EE66666;
	bra.uni 	$L__BB0_49;

$L__BB0_46:
	setp.neu.f32 	%p58, %f147, 0f7F800000;
	@%p58 bra 	$L__BB0_49;

	selp.f32 	%f1176, 0fFF800000, 0f7F800000, %p1;

$L__BB0_49:
	setp.eq.f32 	%p59, %f143, 0f3F800000;
	selp.f32 	%f158, 0f3F800000, %f1176, %p59;
	abs.f32 	%f159, %f144;
	setp.lt.f32 	%p60, %f159, 0f00800000;
	mul.f32 	%f496, %f159, 0f4B800000;
	selp.f32 	%f497, %f496, %f159, %p60;
	selp.f32 	%f498, 0fC3170000, 0fC2FE0000, %p60;
	mov.b32 	%r224, %f497;
	and.b32  	%r225, %r224, 8388607;
	or.b32  	%r226, %r225, 1065353216;
	mov.b32 	%f499, %r226;
	shr.u32 	%r227, %r224, 23;
	cvt.rn.f32.u32 	%f500, %r227;
	add.f32 	%f501, %f498, %f500;
	setp.gt.f32 	%p61, %f499, 0f3FB504F3;
	mul.f32 	%f502, %f499, 0f3F000000;
	add.f32 	%f503, %f501, 0f3F800000;
	selp.f32 	%f504, %f503, %f501, %p61;
	selp.f32 	%f505, %f502, %f499, %p61;
	add.f32 	%f506, %f505, 0fBF800000;
	add.f32 	%f507, %f505, 0f3F800000;
	rcp.approx.ftz.f32 	%f508, %f507;
	add.f32 	%f509, %f506, %f506;
	mul.f32 	%f510, %f509, %f508;
	mul.f32 	%f511, %f510, %f510;
	mov.f32 	%f512, 0f3C4CAF63;
	mov.f32 	%f513, 0f3B18F0FE;
	fma.rn.f32 	%f514, %f513, %f511, %f512;
	mov.f32 	%f515, 0f3DAAAABD;
	fma.rn.f32 	%f516, %f514, %f511, %f515;
	mul.rn.f32 	%f517, %f516, %f511;
	mul.rn.f32 	%f518, %f517, %f510;
	sub.f32 	%f519, %f506, %f510;
	add.f32 	%f520, %f519, %f519;
	neg.f32 	%f521, %f510;
	fma.rn.f32 	%f522, %f521, %f506, %f520;
	mul.rn.f32 	%f523, %f508, %f522;
	add.f32 	%f524, %f518, %f510;
	sub.f32 	%f525, %f510, %f524;
	add.f32 	%f526, %f518, %f525;
	add.f32 	%f527, %f523, %f526;
	add.f32 	%f528, %f524, %f527;
	sub.f32 	%f529, %f524, %f528;
	add.f32 	%f530, %f527, %f529;
	mov.f32 	%f531, 0f3F317200;
	mul.rn.f32 	%f532, %f504, %f531;
	mov.f32 	%f533, 0f35BFBE8E;
	mul.rn.f32 	%f534, %f504, %f533;
	add.f32 	%f535, %f532, %f528;
	sub.f32 	%f536, %f532, %f535;
	add.f32 	%f537, %f528, %f536;
	add.f32 	%f538, %f530, %f537;
	add.f32 	%f539, %f534, %f538;
	add.f32 	%f540, %f535, %f539;
	sub.f32 	%f541, %f535, %f540;
	add.f32 	%f542, %f539, %f541;
	mov.f32 	%f543, 0f3EE66666;
	mul.rn.f32 	%f544, %f543, %f540;
	neg.f32 	%f545, %f544;
	fma.rn.f32 	%f546, %f543, %f540, %f545;
	fma.rn.f32 	%f547, %f543, %f542, %f546;
	mov.f32 	%f548, 0f00000000;
	fma.rn.f32 	%f549, %f548, %f540, %f547;
	add.rn.f32 	%f550, %f544, %f549;
	neg.f32 	%f551, %f550;
	add.rn.f32 	%f552, %f544, %f551;
	add.rn.f32 	%f553, %f552, %f549;
	mov.b32 	%r228, %f550;
	setp.eq.s32 	%p62, %r228, 1118925336;
	add.s32 	%r229, %r228, -1;
	mov.b32 	%f554, %r229;
	add.f32 	%f555, %f553, 0f37000000;
	selp.f32 	%f160, %f555, %f553, %p62;
	selp.f32 	%f556, %f554, %f550, %p62;
	mov.f32 	%f557, 0f3FB8AA3B;
	mul.rn.f32 	%f558, %f556, %f557;
	cvt.rzi.f32.f32 	%f559, %f558;
	abs.f32 	%f560, %f559;
	setp.gt.f32 	%p63, %f560, 0f42FC0000;
	mov.b32 	%r230, %f559;
	and.b32  	%r231, %r230, -2147483648;
	or.b32  	%r232, %r231, 1123811328;
	mov.b32 	%f561, %r232;
	selp.f32 	%f562, %f561, %f559, %p63;
	mov.f32 	%f563, 0fBF317218;
	fma.rn.f32 	%f564, %f562, %f563, %f556;
	mov.f32 	%f565, 0f3102E308;
	fma.rn.f32 	%f566, %f562, %f565, %f564;
	mul.f32 	%f567, %f566, 0f3FB8AA3B;
	add.f32 	%f568, %f562, 0f4B40007F;
	mov.b32 	%r233, %f568;
	shl.b32 	%r234, %r233, 23;
	mov.b32 	%f569, %r234;
	ex2.approx.ftz.f32 	%f570, %f567;
	mul.f32 	%f161, %f570, %f569;
	setp.eq.f32 	%p64, %f161, 0f7F800000;
	mov.f32 	%f1177, 0f7F800000;
	@%p64 bra 	$L__BB0_51;

	fma.rn.f32 	%f1177, %f161, %f160, %f161;

$L__BB0_51:
	setp.lt.f32 	%p65, %f144, 0f00000000;
	and.pred  	%p2, %p65, %p51;
	setp.eq.f32 	%p67, %f144, 0f00000000;
	@%p67 bra 	$L__BB0_55;
	bra.uni 	$L__BB0_52;

$L__BB0_55:
	add.f32 	%f575, %f144, %f144;
	selp.f32 	%f1179, %f575, 0f00000000, %p51;
	bra.uni 	$L__BB0_56;

$L__BB0_52:
	mov.b32 	%r235, %f1177;
	xor.b32  	%r236, %r235, -2147483648;
	mov.b32 	%f571, %r236;
	selp.f32 	%f1179, %f571, %f1177, %p2;
	setp.geu.f32 	%p68, %f144, 0f00000000;
	@%p68 bra 	$L__BB0_56;

	mov.f32 	%f572, 0f3EE66666;
	cvt.rzi.f32.f32 	%f573, %f572;
	setp.eq.f32 	%p69, %f573, 0f3EE66666;
	@%p69 bra 	$L__BB0_56;

	mov.f32 	%f1179, 0f7FFFFFFF;

$L__BB0_56:
	add.f32 	%f576, %f159, 0f3EE66666;
	mov.b32 	%r237, %f576;
	setp.lt.s32 	%p71, %r237, 2139095040;
	@%p71 bra 	$L__BB0_61;

	setp.gtu.f32 	%p72, %f159, 0f7F800000;
	@%p72 bra 	$L__BB0_60;
	bra.uni 	$L__BB0_58;

$L__BB0_60:
	add.f32 	%f1179, %f144, 0f3EE66666;
	bra.uni 	$L__BB0_61;

$L__BB0_58:
	setp.neu.f32 	%p73, %f159, 0f7F800000;
	@%p73 bra 	$L__BB0_61;

	selp.f32 	%f1179, 0fFF800000, 0f7F800000, %p2;

$L__BB0_61:
	setp.eq.f32 	%p74, %f144, 0f3F800000;
	selp.f32 	%f170, 0f3F800000, %f1179, %p74;
	abs.f32 	%f171, %f145;
	setp.lt.f32 	%p75, %f171, 0f00800000;
	mul.f32 	%f578, %f171, 0f4B800000;
	selp.f32 	%f579, %f578, %f171, %p75;
	selp.f32 	%f580, 0fC3170000, 0fC2FE0000, %p75;
	mov.b32 	%r238, %f579;
	and.b32  	%r239, %r238, 8388607;
	or.b32  	%r240, %r239, 1065353216;
	mov.b32 	%f581, %r240;
	shr.u32 	%r241, %r238, 23;
	cvt.rn.f32.u32 	%f582, %r241;
	add.f32 	%f583, %f580, %f582;
	setp.gt.f32 	%p76, %f581, 0f3FB504F3;
	mul.f32 	%f584, %f581, 0f3F000000;
	add.f32 	%f585, %f583, 0f3F800000;
	selp.f32 	%f586, %f585, %f583, %p76;
	selp.f32 	%f587, %f584, %f581, %p76;
	add.f32 	%f588, %f587, 0fBF800000;
	add.f32 	%f589, %f587, 0f3F800000;
	rcp.approx.ftz.f32 	%f590, %f589;
	add.f32 	%f591, %f588, %f588;
	mul.f32 	%f592, %f591, %f590;
	mul.f32 	%f593, %f592, %f592;
	mov.f32 	%f594, 0f3C4CAF63;
	mov.f32 	%f595, 0f3B18F0FE;
	fma.rn.f32 	%f596, %f595, %f593, %f594;
	mov.f32 	%f597, 0f3DAAAABD;
	fma.rn.f32 	%f598, %f596, %f593, %f597;
	mul.rn.f32 	%f599, %f598, %f593;
	mul.rn.f32 	%f600, %f599, %f592;
	sub.f32 	%f601, %f588, %f592;
	add.f32 	%f602, %f601, %f601;
	neg.f32 	%f603, %f592;
	fma.rn.f32 	%f604, %f603, %f588, %f602;
	mul.rn.f32 	%f605, %f590, %f604;
	add.f32 	%f606, %f600, %f592;
	sub.f32 	%f607, %f592, %f606;
	add.f32 	%f608, %f600, %f607;
	add.f32 	%f609, %f605, %f608;
	add.f32 	%f610, %f606, %f609;
	sub.f32 	%f611, %f606, %f610;
	add.f32 	%f612, %f609, %f611;
	mov.f32 	%f613, 0f3F317200;
	mul.rn.f32 	%f614, %f586, %f613;
	mov.f32 	%f615, 0f35BFBE8E;
	mul.rn.f32 	%f616, %f586, %f615;
	add.f32 	%f617, %f614, %f610;
	sub.f32 	%f618, %f614, %f617;
	add.f32 	%f619, %f610, %f618;
	add.f32 	%f620, %f612, %f619;
	add.f32 	%f621, %f616, %f620;
	add.f32 	%f622, %f617, %f621;
	sub.f32 	%f623, %f617, %f622;
	add.f32 	%f624, %f621, %f623;
	mov.f32 	%f625, 0f3EE66666;
	mul.rn.f32 	%f626, %f625, %f622;
	neg.f32 	%f627, %f626;
	fma.rn.f32 	%f628, %f625, %f622, %f627;
	fma.rn.f32 	%f629, %f625, %f624, %f628;
	mov.f32 	%f630, 0f00000000;
	fma.rn.f32 	%f631, %f630, %f622, %f629;
	add.rn.f32 	%f632, %f626, %f631;
	neg.f32 	%f633, %f632;
	add.rn.f32 	%f634, %f626, %f633;
	add.rn.f32 	%f635, %f634, %f631;
	mov.b32 	%r242, %f632;
	setp.eq.s32 	%p77, %r242, 1118925336;
	add.s32 	%r243, %r242, -1;
	mov.b32 	%f636, %r243;
	add.f32 	%f637, %f635, 0f37000000;
	selp.f32 	%f172, %f637, %f635, %p77;
	selp.f32 	%f638, %f636, %f632, %p77;
	mov.f32 	%f639, 0f3FB8AA3B;
	mul.rn.f32 	%f640, %f638, %f639;
	cvt.rzi.f32.f32 	%f641, %f640;
	abs.f32 	%f642, %f641;
	setp.gt.f32 	%p78, %f642, 0f42FC0000;
	mov.b32 	%r244, %f641;
	and.b32  	%r245, %r244, -2147483648;
	or.b32  	%r246, %r245, 1123811328;
	mov.b32 	%f643, %r246;
	selp.f32 	%f644, %f643, %f641, %p78;
	mov.f32 	%f645, 0fBF317218;
	fma.rn.f32 	%f646, %f644, %f645, %f638;
	mov.f32 	%f647, 0f3102E308;
	fma.rn.f32 	%f648, %f644, %f647, %f646;
	mul.f32 	%f649, %f648, 0f3FB8AA3B;
	add.f32 	%f650, %f644, 0f4B40007F;
	mov.b32 	%r247, %f650;
	shl.b32 	%r248, %r247, 23;
	mov.b32 	%f651, %r248;
	ex2.approx.ftz.f32 	%f652, %f649;
	mul.f32 	%f173, %f652, %f651;
	setp.eq.f32 	%p79, %f173, 0f7F800000;
	mov.f32 	%f1180, 0f7F800000;
	@%p79 bra 	$L__BB0_63;

	fma.rn.f32 	%f1180, %f173, %f172, %f173;

$L__BB0_63:
	setp.lt.f32 	%p80, %f145, 0f00000000;
	and.pred  	%p3, %p80, %p51;
	setp.eq.f32 	%p82, %f145, 0f00000000;
	@%p82 bra 	$L__BB0_67;
	bra.uni 	$L__BB0_64;

$L__BB0_67:
	add.f32 	%f657, %f145, %f145;
	selp.f32 	%f1182, %f657, 0f00000000, %p51;
	bra.uni 	$L__BB0_68;

$L__BB0_64:
	mov.b32 	%r249, %f1180;
	xor.b32  	%r250, %r249, -2147483648;
	mov.b32 	%f653, %r250;
	selp.f32 	%f1182, %f653, %f1180, %p3;
	setp.geu.f32 	%p83, %f145, 0f00000000;
	@%p83 bra 	$L__BB0_68;

	mov.f32 	%f654, 0f3EE66666;
	cvt.rzi.f32.f32 	%f655, %f654;
	setp.eq.f32 	%p84, %f655, 0f3EE66666;
	@%p84 bra 	$L__BB0_68;

	mov.f32 	%f1182, 0f7FFFFFFF;

$L__BB0_68:
	add.f32 	%f658, %f171, 0f3EE66666;
	mov.b32 	%r251, %f658;
	setp.lt.s32 	%p86, %r251, 2139095040;
	@%p86 bra 	$L__BB0_73;

	setp.gtu.f32 	%p87, %f171, 0f7F800000;
	@%p87 bra 	$L__BB0_72;
	bra.uni 	$L__BB0_70;

$L__BB0_72:
	add.f32 	%f1182, %f145, 0f3EE66666;
	bra.uni 	$L__BB0_73;

$L__BB0_70:
	setp.neu.f32 	%p88, %f171, 0f7F800000;
	@%p88 bra 	$L__BB0_73;

	selp.f32 	%f1182, 0fFF800000, 0f7F800000, %p3;

$L__BB0_73:
	setp.eq.f32 	%p89, %f145, 0f3F800000;
	mov.f32 	%f660, 0f3F800000;
	selp.f32 	%f661, 0f3F800000, %f1182, %p89;
	min.f32 	%f662, %f158, %f660;
	mov.f32 	%f663, 0f00000000;
	max.f32 	%f182, %f663, %f662;
	min.f32 	%f664, %f170, %f660;
	max.f32 	%f183, %f663, %f664;
	min.f32 	%f665, %f661, %f660;
	max.f32 	%f184, %f663, %f665;
	mov.f32 	%f669, 0f3ED55555;
	abs.f32 	%f186, %f182;
	setp.lt.f32 	%p90, %f186, 0f00800000;
	mul.f32 	%f671, %f186, 0f4B800000;
	selp.f32 	%f672, %f671, %f186, %p90;
	selp.f32 	%f673, 0fC3170000, 0fC2FE0000, %p90;
	mov.b32 	%r254, %f672;
	and.b32  	%r255, %r254, 8388607;
	or.b32  	%r256, %r255, 1065353216;
	mov.b32 	%f674, %r256;
	shr.u32 	%r257, %r254, 23;
	cvt.rn.f32.u32 	%f675, %r257;
	add.f32 	%f676, %f673, %f675;
	setp.gt.f32 	%p91, %f674, 0f3FB504F3;
	mul.f32 	%f677, %f674, 0f3F000000;
	add.f32 	%f678, %f676, 0f3F800000;
	selp.f32 	%f679, %f678, %f676, %p91;
	selp.f32 	%f680, %f677, %f674, %p91;
	add.f32 	%f681, %f680, 0fBF800000;
	add.f32 	%f682, %f680, 0f3F800000;
	rcp.approx.ftz.f32 	%f683, %f682;
	add.f32 	%f684, %f681, %f681;
	mul.f32 	%f685, %f684, %f683;
	mul.f32 	%f686, %f685, %f685;
	mov.f32 	%f687, 0f3C4CAF63;
	mov.f32 	%f688, 0f3B18F0FE;
	fma.rn.f32 	%f689, %f688, %f686, %f687;
	mov.f32 	%f690, 0f3DAAAABD;
	fma.rn.f32 	%f691, %f689, %f686, %f690;
	mul.rn.f32 	%f692, %f691, %f686;
	mul.rn.f32 	%f693, %f692, %f685;
	sub.f32 	%f694, %f681, %f685;
	add.f32 	%f695, %f694, %f694;
	neg.f32 	%f696, %f685;
	fma.rn.f32 	%f697, %f696, %f681, %f695;
	mul.rn.f32 	%f698, %f683, %f697;
	add.f32 	%f699, %f693, %f685;
	sub.f32 	%f700, %f685, %f699;
	add.f32 	%f701, %f693, %f700;
	add.f32 	%f702, %f698, %f701;
	add.f32 	%f703, %f699, %f702;
	sub.f32 	%f704, %f699, %f703;
	add.f32 	%f705, %f702, %f704;
	mov.f32 	%f706, 0f3F317200;
	mul.rn.f32 	%f707, %f679, %f706;
	mov.f32 	%f708, 0f35BFBE8E;
	mul.rn.f32 	%f709, %f679, %f708;
	add.f32 	%f710, %f707, %f703;
	sub.f32 	%f711, %f707, %f710;
	add.f32 	%f712, %f703, %f711;
	add.f32 	%f713, %f705, %f712;
	add.f32 	%f714, %f709, %f713;
	add.f32 	%f715, %f710, %f714;
	sub.f32 	%f716, %f710, %f715;
	add.f32 	%f717, %f714, %f716;
	mul.rn.f32 	%f718, %f669, %f715;
	neg.f32 	%f719, %f718;
	fma.rn.f32 	%f720, %f669, %f715, %f719;
	fma.rn.f32 	%f721, %f669, %f717, %f720;
	fma.rn.f32 	%f722, %f663, %f715, %f721;
	add.rn.f32 	%f723, %f718, %f722;
	neg.f32 	%f724, %f723;
	add.rn.f32 	%f725, %f718, %f724;
	add.rn.f32 	%f726, %f725, %f722;
	mov.b32 	%r258, %f723;
	setp.eq.s32 	%p92, %r258, 1118925336;
	add.s32 	%r259, %r258, -1;
	mov.b32 	%f727, %r259;
	add.f32 	%f728, %f726, 0f37000000;
	selp.f32 	%f187, %f728, %f726, %p92;
	selp.f32 	%f729, %f727, %f723, %p92;
	mov.f32 	%f730, 0f3FB8AA3B;
	mul.rn.f32 	%f731, %f729, %f730;
	cvt.rzi.f32.f32 	%f732, %f731;
	abs.f32 	%f733, %f732;
	setp.gt.f32 	%p93, %f733, 0f42FC0000;
	mov.b32 	%r260, %f732;
	and.b32  	%r261, %r260, -2147483648;
	or.b32  	%r262, %r261, 1123811328;
	mov.b32 	%f734, %r262;
	selp.f32 	%f735, %f734, %f732, %p93;
	mov.f32 	%f736, 0fBF317218;
	fma.rn.f32 	%f737, %f735, %f736, %f729;
	mov.f32 	%f738, 0f3102E308;
	fma.rn.f32 	%f739, %f735, %f738, %f737;
	mul.f32 	%f740, %f739, 0f3FB8AA3B;
	add.f32 	%f741, %f735, 0f4B40007F;
	mov.b32 	%r263, %f741;
	shl.b32 	%r264, %r263, 23;
	mov.b32 	%f742, %r264;
	ex2.approx.ftz.f32 	%f743, %f740;
	mul.f32 	%f188, %f743, %f742;
	setp.eq.f32 	%p94, %f188, 0f7F800000;
	mov.f32 	%f1183, 0f7F800000;
	@%p94 bra 	$L__BB0_75;

	fma.rn.f32 	%f1183, %f188, %f187, %f188;

$L__BB0_75:
	mov.f32 	%f1087, 0f00000000;
	max.f32 	%f1086, %f1087, %f662;
	mov.f32 	%f1067, 0f3E555555;
	cvt.rzi.f32.f32 	%f1066, %f1067;
	add.f32 	%f1065, %f1066, %f1066;
	mov.f32 	%f1064, 0f3ED55555;
	sub.f32 	%f1063, %f1064, %f1065;
	abs.f32 	%f1062, %f1063;
	setp.lt.f32 	%p95, %f1086, 0f00000000;
	setp.eq.f32 	%p96, %f1062, 0f3F800000;
	and.pred  	%p4, %p95, %p96;
	setp.eq.f32 	%p97, %f1086, 0f00000000;
	@%p97 bra 	$L__BB0_79;
	bra.uni 	$L__BB0_76;

$L__BB0_79:
	mov.f32 	%f1104, 0f00000000;
	max.f32 	%f1103, %f1104, %f662;
	add.f32 	%f748, %f1103, %f1103;
	selp.f32 	%f1185, %f748, 0f00000000, %p96;
	bra.uni 	$L__BB0_80;

$L__BB0_76:
	mov.f32 	%f1089, 0f00000000;
	max.f32 	%f1088, %f1089, %f662;
	mov.b32 	%r265, %f1183;
	xor.b32  	%r266, %r265, -2147483648;
	mov.b32 	%f744, %r266;
	selp.f32 	%f1185, %f744, %f1183, %p4;
	setp.geu.f32 	%p98, %f1088, 0f00000000;
	@%p98 bra 	$L__BB0_80;

	mov.f32 	%f745, 0f3ED55555;
	cvt.rzi.f32.f32 	%f746, %f745;
	setp.eq.f32 	%p99, %f746, 0f3ED55555;
	@%p99 bra 	$L__BB0_80;

	mov.f32 	%f1185, 0f7FFFFFFF;

$L__BB0_80:
	mov.f32 	%f1092, 0f00000000;
	max.f32 	%f1091, %f1092, %f662;
	abs.f32 	%f1090, %f1091;
	add.f32 	%f749, %f1090, 0f3ED55555;
	mov.b32 	%r267, %f749;
	setp.lt.s32 	%p101, %r267, 2139095040;
	@%p101 bra 	$L__BB0_85;

	mov.f32 	%f1097, 0f00000000;
	max.f32 	%f1096, %f1097, %f662;
	abs.f32 	%f1095, %f1096;
	setp.gtu.f32 	%p102, %f1095, 0f7F800000;
	@%p102 bra 	$L__BB0_84;
	bra.uni 	$L__BB0_82;

$L__BB0_84:
	mov.f32 	%f1102, 0f00000000;
	max.f32 	%f1101, %f1102, %f662;
	add.f32 	%f1185, %f1101, 0f3ED55555;
	bra.uni 	$L__BB0_85;

$L__BB0_82:
	mov.f32 	%f1100, 0f00000000;
	max.f32 	%f1099, %f1100, %f662;
	abs.f32 	%f1098, %f1099;
	setp.neu.f32 	%p103, %f1098, 0f7F800000;
	@%p103 bra 	$L__BB0_85;

	selp.f32 	%f1185, 0fFF800000, 0f7F800000, %p4;

$L__BB0_85:
	abs.f32 	%f197, %f183;
	setp.lt.f32 	%p104, %f197, 0f00800000;
	mul.f32 	%f751, %f197, 0f4B800000;
	selp.f32 	%f752, %f751, %f197, %p104;
	selp.f32 	%f753, 0fC3170000, 0fC2FE0000, %p104;
	mov.b32 	%r268, %f752;
	and.b32  	%r269, %r268, 8388607;
	or.b32  	%r270, %r269, 1065353216;
	mov.b32 	%f754, %r270;
	shr.u32 	%r271, %r268, 23;
	cvt.rn.f32.u32 	%f755, %r271;
	add.f32 	%f756, %f753, %f755;
	setp.gt.f32 	%p105, %f754, 0f3FB504F3;
	mul.f32 	%f757, %f754, 0f3F000000;
	add.f32 	%f758, %f756, 0f3F800000;
	selp.f32 	%f759, %f758, %f756, %p105;
	selp.f32 	%f760, %f757, %f754, %p105;
	add.f32 	%f761, %f760, 0fBF800000;
	add.f32 	%f762, %f760, 0f3F800000;
	rcp.approx.ftz.f32 	%f763, %f762;
	add.f32 	%f764, %f761, %f761;
	mul.f32 	%f765, %f764, %f763;
	mul.f32 	%f766, %f765, %f765;
	mov.f32 	%f767, 0f3C4CAF63;
	mov.f32 	%f768, 0f3B18F0FE;
	fma.rn.f32 	%f769, %f768, %f766, %f767;
	mov.f32 	%f770, 0f3DAAAABD;
	fma.rn.f32 	%f771, %f769, %f766, %f770;
	mul.rn.f32 	%f772, %f771, %f766;
	mul.rn.f32 	%f773, %f772, %f765;
	sub.f32 	%f774, %f761, %f765;
	add.f32 	%f775, %f774, %f774;
	neg.f32 	%f776, %f765;
	fma.rn.f32 	%f777, %f776, %f761, %f775;
	mul.rn.f32 	%f778, %f763, %f777;
	add.f32 	%f779, %f773, %f765;
	sub.f32 	%f780, %f765, %f779;
	add.f32 	%f781, %f773, %f780;
	add.f32 	%f782, %f778, %f781;
	add.f32 	%f783, %f779, %f782;
	sub.f32 	%f784, %f779, %f783;
	add.f32 	%f785, %f782, %f784;
	mov.f32 	%f786, 0f3F317200;
	mul.rn.f32 	%f787, %f759, %f786;
	mov.f32 	%f788, 0f35BFBE8E;
	mul.rn.f32 	%f789, %f759, %f788;
	add.f32 	%f790, %f787, %f783;
	sub.f32 	%f791, %f787, %f790;
	add.f32 	%f792, %f783, %f791;
	add.f32 	%f793, %f785, %f792;
	add.f32 	%f794, %f789, %f793;
	add.f32 	%f795, %f790, %f794;
	sub.f32 	%f796, %f790, %f795;
	add.f32 	%f797, %f794, %f796;
	mov.f32 	%f798, 0f3ED55555;
	mul.rn.f32 	%f799, %f798, %f795;
	neg.f32 	%f800, %f799;
	fma.rn.f32 	%f801, %f798, %f795, %f800;
	fma.rn.f32 	%f802, %f798, %f797, %f801;
	mov.f32 	%f803, 0f00000000;
	fma.rn.f32 	%f804, %f803, %f795, %f802;
	add.rn.f32 	%f805, %f799, %f804;
	neg.f32 	%f806, %f805;
	add.rn.f32 	%f807, %f799, %f806;
	add.rn.f32 	%f808, %f807, %f804;
	mov.b32 	%r272, %f805;
	setp.eq.s32 	%p106, %r272, 1118925336;
	add.s32 	%r273, %r272, -1;
	mov.b32 	%f809, %r273;
	add.f32 	%f810, %f808, 0f37000000;
	selp.f32 	%f198, %f810, %f808, %p106;
	selp.f32 	%f811, %f809, %f805, %p106;
	mov.f32 	%f812, 0f3FB8AA3B;
	mul.rn.f32 	%f813, %f811, %f812;
	cvt.rzi.f32.f32 	%f814, %f813;
	abs.f32 	%f815, %f814;
	setp.gt.f32 	%p107, %f815, 0f42FC0000;
	mov.b32 	%r274, %f814;
	and.b32  	%r275, %r274, -2147483648;
	or.b32  	%r276, %r275, 1123811328;
	mov.b32 	%f816, %r276;
	selp.f32 	%f817, %f816, %f814, %p107;
	mov.f32 	%f818, 0fBF317218;
	fma.rn.f32 	%f819, %f817, %f818, %f811;
	mov.f32 	%f820, 0f3102E308;
	fma.rn.f32 	%f821, %f817, %f820, %f819;
	mul.f32 	%f822, %f821, 0f3FB8AA3B;
	add.f32 	%f823, %f817, 0f4B40007F;
	mov.b32 	%r277, %f823;
	shl.b32 	%r278, %r277, 23;
	mov.b32 	%f824, %r278;
	ex2.approx.ftz.f32 	%f825, %f822;
	mul.f32 	%f199, %f825, %f824;
	setp.eq.f32 	%p108, %f199, 0f7F800000;
	mov.f32 	%f1186, 0f7F800000;
	@%p108 bra 	$L__BB0_87;

	fma.rn.f32 	%f1186, %f199, %f198, %f199;

$L__BB0_87:
	setp.lt.f32 	%p109, %f183, 0f00000000;
	and.pred  	%p5, %p109, %p96;
	setp.eq.f32 	%p111, %f183, 0f00000000;
	@%p111 bra 	$L__BB0_91;
	bra.uni 	$L__BB0_88;

$L__BB0_91:
	add.f32 	%f830, %f183, %f183;
	selp.f32 	%f1188, %f830, 0f00000000, %p96;
	bra.uni 	$L__BB0_92;

$L__BB0_88:
	mov.b32 	%r279, %f1186;
	xor.b32  	%r280, %r279, -2147483648;
	mov.b32 	%f826, %r280;
	selp.f32 	%f1188, %f826, %f1186, %p5;
	setp.geu.f32 	%p112, %f183, 0f00000000;
	@%p112 bra 	$L__BB0_92;

	mov.f32 	%f827, 0f3ED55555;
	cvt.rzi.f32.f32 	%f828, %f827;
	setp.eq.f32 	%p113, %f828, 0f3ED55555;
	@%p113 bra 	$L__BB0_92;

	mov.f32 	%f1188, 0f7FFFFFFF;

$L__BB0_92:
	mov.f32 	%f1070, 0f00000000;
	max.f32 	%f1069, %f1070, %f664;
	abs.f32 	%f1068, %f1069;
	add.f32 	%f831, %f1068, 0f3ED55555;
	mov.b32 	%r281, %f831;
	setp.lt.s32 	%p115, %r281, 2139095040;
	@%p115 bra 	$L__BB0_97;

	mov.f32 	%f1073, 0f00000000;
	max.f32 	%f1072, %f1073, %f664;
	abs.f32 	%f1071, %f1072;
	setp.gtu.f32 	%p116, %f1071, 0f7F800000;
	@%p116 bra 	$L__BB0_96;
	bra.uni 	$L__BB0_94;

$L__BB0_96:
	add.f32 	%f1188, %f183, 0f3ED55555;
	bra.uni 	$L__BB0_97;

$L__BB0_94:
	mov.f32 	%f1076, 0f00000000;
	max.f32 	%f1075, %f1076, %f664;
	abs.f32 	%f1074, %f1075;
	setp.neu.f32 	%p117, %f1074, 0f7F800000;
	@%p117 bra 	$L__BB0_97;

	selp.f32 	%f1188, 0fFF800000, 0f7F800000, %p5;

$L__BB0_97:
	abs.f32 	%f208, %f184;
	setp.lt.f32 	%p118, %f208, 0f00800000;
	mul.f32 	%f833, %f208, 0f4B800000;
	selp.f32 	%f834, %f833, %f208, %p118;
	selp.f32 	%f835, 0fC3170000, 0fC2FE0000, %p118;
	mov.b32 	%r282, %f834;
	and.b32  	%r283, %r282, 8388607;
	or.b32  	%r284, %r283, 1065353216;
	mov.b32 	%f836, %r284;
	shr.u32 	%r285, %r282, 23;
	cvt.rn.f32.u32 	%f837, %r285;
	add.f32 	%f838, %f835, %f837;
	setp.gt.f32 	%p119, %f836, 0f3FB504F3;
	mul.f32 	%f839, %f836, 0f3F000000;
	add.f32 	%f840, %f838, 0f3F800000;
	selp.f32 	%f841, %f840, %f838, %p119;
	selp.f32 	%f842, %f839, %f836, %p119;
	add.f32 	%f843, %f842, 0fBF800000;
	add.f32 	%f844, %f842, 0f3F800000;
	rcp.approx.ftz.f32 	%f845, %f844;
	add.f32 	%f846, %f843, %f843;
	mul.f32 	%f847, %f846, %f845;
	mul.f32 	%f848, %f847, %f847;
	mov.f32 	%f849, 0f3C4CAF63;
	mov.f32 	%f850, 0f3B18F0FE;
	fma.rn.f32 	%f851, %f850, %f848, %f849;
	mov.f32 	%f852, 0f3DAAAABD;
	fma.rn.f32 	%f853, %f851, %f848, %f852;
	mul.rn.f32 	%f854, %f853, %f848;
	mul.rn.f32 	%f855, %f854, %f847;
	sub.f32 	%f856, %f843, %f847;
	add.f32 	%f857, %f856, %f856;
	neg.f32 	%f858, %f847;
	fma.rn.f32 	%f859, %f858, %f843, %f857;
	mul.rn.f32 	%f860, %f845, %f859;
	add.f32 	%f861, %f855, %f847;
	sub.f32 	%f862, %f847, %f861;
	add.f32 	%f863, %f855, %f862;
	add.f32 	%f864, %f860, %f863;
	add.f32 	%f865, %f861, %f864;
	sub.f32 	%f866, %f861, %f865;
	add.f32 	%f867, %f864, %f866;
	mov.f32 	%f868, 0f3F317200;
	mul.rn.f32 	%f869, %f841, %f868;
	mov.f32 	%f870, 0f35BFBE8E;
	mul.rn.f32 	%f871, %f841, %f870;
	add.f32 	%f872, %f869, %f865;
	sub.f32 	%f873, %f869, %f872;
	add.f32 	%f874, %f865, %f873;
	add.f32 	%f875, %f867, %f874;
	add.f32 	%f876, %f871, %f875;
	add.f32 	%f877, %f872, %f876;
	sub.f32 	%f878, %f872, %f877;
	add.f32 	%f879, %f876, %f878;
	mov.f32 	%f880, 0f3ED55555;
	mul.rn.f32 	%f881, %f880, %f877;
	neg.f32 	%f882, %f881;
	fma.rn.f32 	%f883, %f880, %f877, %f882;
	fma.rn.f32 	%f884, %f880, %f879, %f883;
	mov.f32 	%f885, 0f00000000;
	fma.rn.f32 	%f886, %f885, %f877, %f884;
	add.rn.f32 	%f887, %f881, %f886;
	neg.f32 	%f888, %f887;
	add.rn.f32 	%f889, %f881, %f888;
	add.rn.f32 	%f890, %f889, %f886;
	mov.b32 	%r286, %f887;
	setp.eq.s32 	%p120, %r286, 1118925336;
	add.s32 	%r287, %r286, -1;
	mov.b32 	%f891, %r287;
	add.f32 	%f892, %f890, 0f37000000;
	selp.f32 	%f209, %f892, %f890, %p120;
	selp.f32 	%f893, %f891, %f887, %p120;
	mov.f32 	%f894, 0f3FB8AA3B;
	mul.rn.f32 	%f895, %f893, %f894;
	cvt.rzi.f32.f32 	%f896, %f895;
	abs.f32 	%f897, %f896;
	setp.gt.f32 	%p121, %f897, 0f42FC0000;
	mov.b32 	%r288, %f896;
	and.b32  	%r289, %r288, -2147483648;
	or.b32  	%r290, %r289, 1123811328;
	mov.b32 	%f898, %r290;
	selp.f32 	%f899, %f898, %f896, %p121;
	mov.f32 	%f900, 0fBF317218;
	fma.rn.f32 	%f901, %f899, %f900, %f893;
	mov.f32 	%f902, 0f3102E308;
	fma.rn.f32 	%f903, %f899, %f902, %f901;
	mul.f32 	%f904, %f903, 0f3FB8AA3B;
	add.f32 	%f905, %f899, 0f4B40007F;
	mov.b32 	%r291, %f905;
	shl.b32 	%r292, %r291, 23;
	mov.b32 	%f906, %r292;
	ex2.approx.ftz.f32 	%f907, %f904;
	mul.f32 	%f210, %f907, %f906;
	setp.eq.f32 	%p122, %f210, 0f7F800000;
	mov.f32 	%f1189, 0f7F800000;
	@%p122 bra 	$L__BB0_99;

	fma.rn.f32 	%f1189, %f210, %f209, %f210;

$L__BB0_99:
	setp.lt.f32 	%p123, %f184, 0f00000000;
	and.pred  	%p6, %p123, %p96;
	setp.eq.f32 	%p125, %f184, 0f00000000;
	@%p125 bra 	$L__BB0_103;
	bra.uni 	$L__BB0_100;

$L__BB0_103:
	add.f32 	%f912, %f184, %f184;
	selp.f32 	%f1191, %f912, 0f00000000, %p96;
	bra.uni 	$L__BB0_104;

$L__BB0_100:
	mov.b32 	%r293, %f1189;
	xor.b32  	%r294, %r293, -2147483648;
	mov.b32 	%f908, %r294;
	selp.f32 	%f1191, %f908, %f1189, %p6;
	setp.geu.f32 	%p126, %f184, 0f00000000;
	@%p126 bra 	$L__BB0_104;

	mov.f32 	%f909, 0f3ED55555;
	cvt.rzi.f32.f32 	%f910, %f909;
	setp.eq.f32 	%p127, %f910, 0f3ED55555;
	@%p127 bra 	$L__BB0_104;

	mov.f32 	%f1191, 0f7FFFFFFF;

$L__BB0_104:
	mov.f32 	%f1079, 0f00000000;
	max.f32 	%f1078, %f1079, %f665;
	abs.f32 	%f1077, %f1078;
	add.f32 	%f913, %f1077, 0f3ED55555;
	mov.b32 	%r295, %f913;
	setp.lt.s32 	%p129, %r295, 2139095040;
	@%p129 bra 	$L__BB0_109;

	mov.f32 	%f1082, 0f00000000;
	max.f32 	%f1081, %f1082, %f665;
	abs.f32 	%f1080, %f1081;
	setp.gtu.f32 	%p130, %f1080, 0f7F800000;
	@%p130 bra 	$L__BB0_108;
	bra.uni 	$L__BB0_106;

$L__BB0_108:
	add.f32 	%f1191, %f184, 0f3ED55555;
	bra.uni 	$L__BB0_109;

$L__BB0_106:
	mov.f32 	%f1085, 0f00000000;
	max.f32 	%f1084, %f1085, %f665;
	abs.f32 	%f1083, %f1084;
	setp.neu.f32 	%p131, %f1083, 0f7F800000;
	@%p131 bra 	$L__BB0_109;

	selp.f32 	%f1191, 0fFF800000, 0f7F800000, %p6;

$L__BB0_109:
	mov.f32 	%f1094, 0f00000000;
	max.f32 	%f1093, %f1094, %f662;
	ld.const.u64 	%rd103, [params+144];
	cvta.to.global.u64 	%rd102, %rd103;
	ld.const.u32 	%r346, [params+136];
	mad.lo.s32 	%r345, %r346, %r5, %r4;
	cvt.u64.u32 	%rd101, %r345;
	fma.rn.f32 	%f914, %f1185, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p132, %f1093, 0f3F800000;
	mov.f32 	%f915, 0f3F800000;
	selp.f32 	%f916, 0f3F7FFFFF, %f914, %p132;
	mul.f32 	%f917, %f1093, 0f414EB852;
	setp.lt.f32 	%p133, %f1093, 0f3B4D2E1C;
	selp.f32 	%f918, %f917, %f916, %p133;
	fma.rn.f32 	%f919, %f1188, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p134, %f183, 0f3F800000;
	selp.f32 	%f920, 0f3F7FFFFF, %f919, %p134;
	mul.f32 	%f921, %f183, 0f414EB852;
	setp.lt.f32 	%p135, %f183, 0f3B4D2E1C;
	selp.f32 	%f922, %f921, %f920, %p135;
	fma.rn.f32 	%f923, %f1191, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p136, %f184, 0f3F800000;
	selp.f32 	%f924, 0f3F7FFFFF, %f923, %p136;
	mul.f32 	%f925, %f184, 0f414EB852;
	setp.lt.f32 	%p137, %f184, 0f3B4D2E1C;
	selp.f32 	%f926, %f925, %f924, %p137;
	min.f32 	%f927, %f918, %f915;
	mov.f32 	%f928, 0f00000000;
	max.f32 	%f929, %f928, %f927;
	mul.f32 	%f930, %f929, 0f43800000;
	cvt.rzi.u32.f32 	%r296, %f930;
	min.u32 	%r297, %r296, 255;
	min.f32 	%f931, %f922, %f915;
	max.f32 	%f932, %f928, %f931;
	mul.f32 	%f933, %f932, 0f43800000;
	cvt.rzi.u32.f32 	%r298, %f933;
	min.u32 	%r299, %r298, 255;
	min.f32 	%f934, %f926, %f915;
	max.f32 	%f935, %f928, %f934;
	mul.f32 	%f936, %f935, 0f43800000;
	cvt.rzi.u32.f32 	%r300, %f936;
	min.u32 	%r301, %r300, 255;
	shl.b64 	%rd65, %rd101, 2;
	add.s64 	%rd66, %rd102, %rd65;
	cvt.u16.u32 	%rs15, %r301;
	cvt.u16.u32 	%rs16, %r299;
	cvt.u16.u32 	%rs17, %r297;
	mov.u16 	%rs18, 255;
	st.global.v4.u8 	[%rd66], {%rs17, %rs16, %rs15, %rs18};

$L__BB0_110:
	ld.const.u32 	%r347, [params+104];
	and.b32  	%r302, %r347, 4;
	setp.eq.s32 	%p138, %r302, 0;
	ld.const.u32 	%r359, [params+108];
	@%p138 bra 	$L__BB0_114;

	setp.eq.s32 	%p139, %r359, 0;
	ld.const.u64 	%rd67, [params+224];
	cvta.to.global.u64 	%rd68, %rd67;
	ld.const.u32 	%r303, [params+216];
	mad.lo.s32 	%r304, %r303, %r5, %r4;
	mul.wide.u32 	%rd69, %r304, 8;
	add.s64 	%rd18, %rd68, %rd69;
	@%p139 bra 	$L__BB0_113;

	ld.global.v4.u16 	{%rs26, %rs27, %rs28, %rs29}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f937, %rs26;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f938, %rs27;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f939, %rs28;}

	// end inline asm
	add.f32 	%f940, %f143, %f937;
	add.f32 	%f941, %f144, %f938;
	add.f32 	%f942, %f145, %f939;
	mov.f32 	%f943, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs24, %f942;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs23, %f941;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs22, %f940;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs25, %f943;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs22, %rs23, %rs24, %rs25};
	bra.uni 	$L__BB0_114;

$L__BB0_113:
	mov.f32 	%f947, 0f3F800000;
	mov.u32 	%r359, 0;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f947;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f145;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs31, %f144;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f143;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs30, %rs31, %rs32, %rs33};

$L__BB0_114:
	mul.f32 	%f219, %f128, 0f3F000000;
	mul.f32 	%f220, %f219, %f405;
	mul.f32 	%f221, %f129, 0f3F000000;
	mul.f32 	%f222, %f221, %f406;
	mul.f32 	%f223, %f130, 0f3F000000;
	mul.f32 	%f224, %f223, %f407;
	ld.const.u64 	%rd70, [params+256];
	cvta.to.global.u64 	%rd71, %rd70;
	ld.const.u32 	%r306, [params+248];
	mad.lo.s32 	%r307, %r306, %r5, %r4;
	mul.wide.u32 	%rd72, %r307, 8;
	add.s64 	%rd19, %rd71, %rd72;
	setp.eq.s32 	%p140, %r359, 0;
	@%p140 bra 	$L__BB0_116;

	ld.global.v4.u16 	{%rs41, %rs42, %rs43, %rs44}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f948, %rs41;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f949, %rs42;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f950, %rs43;}

	// end inline asm
	add.f32 	%f951, %f220, %f948;
	add.f32 	%f952, %f222, %f949;
	add.f32 	%f953, %f224, %f950;
	mov.f32 	%f954, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs39, %f953;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f952;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs37, %f951;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f954;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs37, %rs38, %rs39, %rs40};
	bra.uni 	$L__BB0_117;

$L__BB0_116:
	mov.f32 	%f958, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f958;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs47, %f224;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f222;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs45, %f220;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs45, %rs46, %rs47, %rs48};

$L__BB0_117:
	mov.f32 	%f959, 0f34000000;
	max.f32 	%f960, %f219, %f959;
	mul.f32 	%f961, %f131, 0f3F000000;
	div.rn.f32 	%f962, %f961, %f960;
	max.f32 	%f963, %f221, %f959;
	mul.f32 	%f964, %f132, 0f3F000000;
	div.rn.f32 	%f965, %f964, %f963;
	max.f32 	%f966, %f223, %f959;
	mul.f32 	%f967, %f133, 0f3F000000;
	div.rn.f32 	%f968, %f967, %f966;
	fma.rn.f32 	%f225, %f962, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f226, %f965, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f227, %f968, 0f3F000000, 0f3F000000;
	mul.f32 	%f969, %f134, 0f3F000000;
	div.rn.f32 	%f970, %f969, %f960;
	mul.f32 	%f971, %f135, 0f3F000000;
	div.rn.f32 	%f972, %f971, %f963;
	mul.f32 	%f973, %f136, 0f3F000000;
	div.rn.f32 	%f974, %f973, %f966;
	fma.rn.f32 	%f228, %f970, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f229, %f972, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f230, %f974, 0f3F000000, 0f3F000000;
	mul.f32 	%f975, %f137, 0f3F000000;
	div.rn.f32 	%f976, %f975, %f960;
	mul.f32 	%f977, %f138, 0f3F000000;
	div.rn.f32 	%f978, %f977, %f963;
	mul.f32 	%f979, %f139, 0f3F000000;
	div.rn.f32 	%f980, %f979, %f966;
	fma.rn.f32 	%f231, %f976, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f232, %f978, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f233, %f980, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd73, [params+272];
	cvta.to.global.u64 	%rd74, %rd73;
	ld.const.u32 	%r308, [params+264];
	mad.lo.s32 	%r309, %r308, %r5, %r4;
	mul.wide.u32 	%rd75, %r309, 8;
	add.s64 	%rd20, %rd74, %rd75;
	@%p140 bra 	$L__BB0_119;

	ld.global.v4.u16 	{%rs56, %rs57, %rs58, %rs59}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f981, %rs56;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f982, %rs57;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f983, %rs58;}

	// end inline asm
	add.f32 	%f984, %f225, %f981;
	add.f32 	%f985, %f226, %f982;
	add.f32 	%f986, %f227, %f983;
	mov.f32 	%f987, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f986;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f985;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs52, %f984;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f987;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs52, %rs53, %rs54, %rs55};
	bra.uni 	$L__BB0_120;

$L__BB0_119:
	mov.f32 	%f991, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f991;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f227;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f226;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs60, %f225;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs60, %rs61, %rs62, %rs63};

$L__BB0_120:
	ld.const.u64 	%rd76, [params+288];
	cvta.to.global.u64 	%rd77, %rd76;
	ld.const.u32 	%r310, [params+280];
	mad.lo.s32 	%r311, %r310, %r5, %r4;
	mul.wide.u32 	%rd78, %r311, 8;
	add.s64 	%rd21, %rd77, %rd78;
	@%p140 bra 	$L__BB0_122;

	ld.global.v4.u16 	{%rs71, %rs72, %rs73, %rs74}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f992, %rs71;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f993, %rs72;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f994, %rs73;}

	// end inline asm
	add.f32 	%f995, %f228, %f992;
	add.f32 	%f996, %f229, %f993;
	add.f32 	%f997, %f230, %f994;
	mov.f32 	%f998, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f997;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f996;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs67, %f995;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f998;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs67, %rs68, %rs69, %rs70};
	bra.uni 	$L__BB0_123;

$L__BB0_122:
	mov.f32 	%f1002, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f1002;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f230;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f229;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs75, %f228;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs75, %rs76, %rs77, %rs78};

$L__BB0_123:
	ld.const.u64 	%rd79, [params+304];
	cvta.to.global.u64 	%rd80, %rd79;
	ld.const.u32 	%r312, [params+296];
	mad.lo.s32 	%r313, %r312, %r5, %r4;
	mul.wide.u32 	%rd81, %r313, 8;
	add.s64 	%rd22, %rd80, %rd81;
	@%p140 bra 	$L__BB0_125;

	ld.global.v4.u16 	{%rs86, %rs87, %rs88, %rs89}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1003, %rs86;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1004, %rs87;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1005, %rs88;}

	// end inline asm
	add.f32 	%f1006, %f231, %f1003;
	add.f32 	%f1007, %f232, %f1004;
	add.f32 	%f1008, %f233, %f1005;
	mov.f32 	%f1009, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1008;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1007;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs82, %f1006;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1009;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs82, %rs83, %rs84, %rs85};
	bra.uni 	$L__BB0_144;

$L__BB0_125:
	mov.f32 	%f1013, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f1013;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f233;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f232;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs90, %f231;}

	// end inline asm
	st.global.v4.u16 	[%rd22], {%rs90, %rs91, %rs92, %rs93};

$L__BB0_144:
	ret;

}