//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

	// .globl	__raygen__oxMain
.const .align 16 .b8 params[1184];
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.visible .entry __raygen__oxMain()
{
	.local .align 4 .b8 	__local_depot0[28];
	.reg .b64 	%SP;
	.reg .b64 	%SPL;
	.reg .pred 	%p<156>;
	.reg .b16 	%rs<166>;
	.reg .f32 	%f<1167>;
	.reg .b32 	%r<364>;
	.reg .f64 	%fd<5>;
	.reg .b64 	%rd<122>;


	mov.u64 	%SPL, __local_depot0;
	add.u64 	%rd1, %SPL, 0;
	// begin inline asm
	call (%r53), _optix_get_launch_index_x, ();
	// end inline asm
	// begin inline asm
	call (%r54), _optix_get_launch_index_y, ();
	// end inline asm
	ld.const.u32 	%r3, [params+540];
	shl.b32 	%r4, %r3, 1;
	ld.const.u64 	%rd27, [params+400];
	cvta.to.global.u64 	%rd28, %rd27;
	ld.const.u32 	%r59, [params+392];
	mad.lo.s32 	%r60, %r59, %r54, %r53;
	mul.wide.u32 	%rd29, %r60, 4;
	add.s64 	%rd2, %rd28, %rd29;
	ld.global.v2.u8 	{%rs7, %rs165}, [%rd2];
	or.b16  	%rs9, %rs7, %rs165;
	and.b16  	%rs10, %rs9, 255;
	setp.eq.s16 	%p7, %rs10, 0;
	@%p7 bra 	$L__BB0_2;

	ld.global.u8 	%rs164, [%rd2+2];
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	ld.global.u8 	%rs164, [%rd2+2];
	setp.eq.s16 	%p8, %rs164, 0;
	mov.f32 	%f1092, 0f00000000;
	mov.u16 	%rs165, 0;
	mov.f32 	%f1093, %f1092;
	mov.f32 	%f1094, %f1092;
	@%p8 bra 	$L__BB0_4;

$L__BB0_3:
	cvt.rn.f32.u16 	%f228, %rs7;
	div.rn.f32 	%f229, %f228, 0f437F0000;
	fma.rn.f32 	%f230, %f229, 0f40000000, 0fBF800000;
	and.b16  	%rs13, %rs165, 255;
	cvt.rn.f32.u16 	%f231, %rs13;
	div.rn.f32 	%f232, %f231, 0f437F0000;
	fma.rn.f32 	%f233, %f232, 0f40000000, 0fBF800000;
	cvt.rn.f32.u16 	%f234, %rs164;
	div.rn.f32 	%f235, %f234, 0f437F0000;
	fma.rn.f32 	%f236, %f235, 0f40000000, 0fBF800000;
	mul.f32 	%f237, %f233, %f233;
	fma.rn.f32 	%f238, %f230, %f230, %f237;
	fma.rn.f32 	%f239, %f236, %f236, %f238;
	sqrt.rn.f32 	%f240, %f239;
	rcp.rn.f32 	%f241, %f240;
	mul.f32 	%f1094, %f241, %f236;
	mul.f32 	%f1093, %f241, %f233;
	mul.f32 	%f1092, %f230, %f241;

$L__BB0_4:
	ld.const.v2.u32 	{%r61, %r62}, [params];
	add.s32 	%r5, %r61, %r53;
	add.s32 	%r6, %r62, %r54;
	setp.eq.f32 	%p9, %f1092, 0f00000000;
	setp.eq.f32 	%p10, %f1093, 0f00000000;
	and.pred  	%p11, %p9, %p10;
	setp.eq.f32 	%p12, %f1094, 0f00000000;
	and.pred  	%p13, %p12, %p11;
	@%p13 bra 	$L__BB0_128;
	bra.uni 	$L__BB0_5;

$L__BB0_128:
	ld.const.u32 	%r51, [params+104];
	and.b32  	%r316, %r51, 1;
	setp.eq.b32 	%p145, %r316, 1;
	mov.pred 	%p146, 0;
	xor.pred  	%p147, %p145, %p146;
	not.pred 	%p148, %p147;
	@%p148 bra 	$L__BB0_130;

	ld.const.u64 	%rd90, [params+144];
	cvta.to.global.u64 	%rd91, %rd90;
	ld.const.u32 	%r317, [params+136];
	mad.lo.s32 	%r318, %r317, %r6, %r5;
	mul.wide.u32 	%rd92, %r318, 4;
	add.s64 	%rd93, %rd91, %rd92;
	mov.u16 	%rs95, 0;
	st.global.v4.u8 	[%rd93], {%rs95, %rs95, %rs95, %rs95};

$L__BB0_130:
	and.b32  	%r319, %r51, 4;
	setp.eq.s32 	%p149, %r319, 0;
	@%p149 bra 	$L__BB0_132;

	ld.const.u64 	%rd94, [params+224];
	cvta.to.global.u64 	%rd95, %rd94;
	ld.const.u32 	%r320, [params+216];
	mad.lo.s32 	%r321, %r320, %r6, %r5;
	mov.f32 	%f1023, 0f00000000;
	mul.wide.u32 	%rd96, %r321, 8;
	add.s64 	%rd97, %rd95, %rd96;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs98, %f1023;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs97, %f1023;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs96, %f1023;}

	// end inline asm
	mov.u16 	%rs99, 0;
	st.global.v4.u16 	[%rd97], {%rs96, %rs97, %rs98, %rs99};

$L__BB0_132:
	and.b32  	%r322, %r51, 16;
	setp.eq.s32 	%p150, %r322, 0;
	@%p150 bra 	$L__BB0_134;

	ld.const.u64 	%rd98, [params+240];
	cvta.to.global.u64 	%rd99, %rd98;
	ld.const.u32 	%r323, [params+232];
	mad.lo.s32 	%r324, %r323, %r6, %r5;
	mov.f32 	%f1026, 0f00000000;
	mul.wide.u32 	%rd100, %r324, 8;
	add.s64 	%rd101, %rd99, %rd100;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs102, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs101, %f1026;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs100, %f1026;}

	// end inline asm
	mov.u16 	%rs103, 0;
	st.global.v4.u16 	[%rd101], {%rs100, %rs101, %rs102, %rs103};

$L__BB0_134:
	ld.const.u32 	%r52, [params+108];
	setp.eq.s32 	%p151, %r52, 0;
	ld.const.u64 	%rd102, [params+256];
	cvta.to.global.u64 	%rd103, %rd102;
	ld.const.u32 	%r325, [params+248];
	mad.lo.s32 	%r326, %r325, %r6, %r5;
	mul.wide.u32 	%rd104, %r326, 8;
	add.s64 	%rd22, %rd103, %rd104;
	@%p151 bra 	$L__BB0_136;

	ld.global.v4.u16 	{%rs110, %rs111, %rs112, %rs113}, [%rd22];
	// begin inline asm
	{  cvt.f32.f16 %f1027, %rs110;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1028, %rs111;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1029, %rs112;}

	// end inline asm
	add.f32 	%f1030, %f1027, 0f00000000;
	add.f32 	%f1031, %f1028, 0f00000000;
	add.f32 	%f1032, %f1029, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs109, %f1032;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs108, %f1031;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs107, %f1030;}

	// end inline asm
	mov.u16 	%rs114, 0;
	st.global.v4.u16 	[%rd22], {%rs107, %rs108, %rs109, %rs114};
	bra.uni 	$L__BB0_137;

$L__BB0_5:
	ld.const.u64 	%rd30, [params+496];
	cvta.to.global.u64 	%rd31, %rd30;
	ld.const.u32 	%r65, [params+488];
	mad.lo.s32 	%r66, %r65, %r54, %r53;
	mul.wide.u32 	%rd32, %r66, 8;
	add.s64 	%rd33, %rd31, %rd32;
	ld.global.v4.u16 	{%rs19, %rs20, %rs21, %rs22}, [%rd33];
	// begin inline asm
	{  cvt.f32.f16 %f242, %rs19;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f243, %rs20;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f244, %rs21;}

	// end inline asm
	ld.const.u64 	%rd34, [params+432];
	cvta.to.global.u64 	%rd35, %rd34;
	ld.const.u32 	%r67, [params+424];
	mad.lo.s32 	%r68, %r67, %r54, %r53;
	mul.wide.u32 	%rd36, %r68, 12;
	add.s64 	%rd37, %rd35, %rd36;
	ld.global.f32 	%f261, [%rd37];
	mul.f32 	%f262, %f261, 0f3456BF95;
	ld.global.f32 	%f263, [%rd37+4];
	mul.f32 	%f264, %f263, 0f3456BF95;
	ld.global.f32 	%f265, [%rd37+8];
	mul.f32 	%f266, %f265, 0f3456BF95;
	abs.f32 	%f267, %f1092;
	div.rn.f32 	%f268, %f262, %f267;
	abs.f32 	%f269, %f1093;
	div.rn.f32 	%f270, %f264, %f269;
	abs.f32 	%f271, %f1094;
	div.rn.f32 	%f272, %f266, %f271;
	abs.f32 	%f273, %f268;
	abs.f32 	%f274, %f270;
	abs.f32 	%f275, %f272;
	mov.f32 	%f276, 0f38D1B717;
	max.f32 	%f277, %f273, %f276;
	max.f32 	%f278, %f274, %f276;
	max.f32 	%f279, %f275, %f276;
	fma.rn.f32 	%f13, %f1092, %f277, %f261;
	fma.rn.f32 	%f14, %f1093, %f278, %f263;
	fma.rn.f32 	%f15, %f1094, %f279, %f265;
	setp.gt.f32 	%p14, %f267, %f271;
	neg.f32 	%f280, %f1093;
	selp.f32 	%f281, %f280, 0f00000000, %p14;
	mov.f32 	%f1124, 0f00000000;
	neg.f32 	%f282, %f1094;
	selp.f32 	%f283, %f1092, %f282, %p14;
	selp.f32 	%f284, 0f00000000, %f1093, %p14;
	mul.f32 	%f285, %f283, %f283;
	fma.rn.f32 	%f286, %f281, %f281, %f285;
	fma.rn.f32 	%f287, %f284, %f284, %f286;
	sqrt.rn.f32 	%f288, %f287;
	rcp.rn.f32 	%f289, %f288;
	mul.f32 	%f16, %f281, %f289;
	mul.f32 	%f17, %f283, %f289;
	mul.f32 	%f18, %f284, %f289;
	ld.const.u64 	%rd38, [params+128];
	cvta.to.global.u64 	%rd39, %rd38;
	ld.const.u32 	%r69, [params+120];
	mad.lo.s32 	%r70, %r69, %r54, %r53;
	mul.wide.u32 	%rd40, %r70, 4;
	add.s64 	%rd3, %rd39, %rd40;
	setp.lt.s32 	%p15, %r3, 1;
	mov.f32 	%f1123, %f1124;
	mov.f32 	%f1122, %f1124;
	mov.f32 	%f1121, %f1124;
	mov.f32 	%f1120, %f1124;
	mov.f32 	%f1119, %f1124;
	mov.f32 	%f1118, %f1124;
	mov.f32 	%f1117, %f1124;
	mov.f32 	%f1116, %f1124;
	mov.f32 	%f1115, %f1124;
	mov.f32 	%f1114, %f1124;
	mov.f32 	%f1113, %f1124;
	mov.f32 	%f1112, %f1124;
	mov.f32 	%f1111, %f1124;
	mov.f32 	%f1110, %f1124;
	@%p15 bra 	$L__BB0_34;

	cvt.rn.f32.s32 	%f305, %r4;
	rcp.rn.f32 	%f19, %f305;
	ld.global.u32 	%r356, [%rd3];
	mul.f32 	%f20, %f13, 0f3456BF95;
	mul.f32 	%f21, %f14, 0f3456BF95;
	mul.f32 	%f22, %f15, 0f3456BF95;
	ld.const.u64 	%rd4, [params+96];
	mul.f32 	%f306, %f1092, %f17;
	mul.f32 	%f307, %f1093, %f16;
	sub.f32 	%f23, %f307, %f306;
	mul.f32 	%f308, %f1094, %f16;
	mul.f32 	%f309, %f1092, %f18;
	sub.f32 	%f24, %f309, %f308;
	mul.f32 	%f310, %f1093, %f18;
	mul.f32 	%f311, %f1094, %f17;
	sub.f32 	%f25, %f311, %f310;
	mov.u32 	%r71, 0;
	add.s64 	%rd5, %rd1, 24;
	mov.u64 	%rd41, __cudart_i2opi_f;
	abs.f32 	%f376, %f21;
	abs.f32 	%f377, %f20;
	max.f32 	%f378, %f377, %f376;
	abs.f32 	%f379, %f22;
	max.f32 	%f380, %f378, %f379;
	mov.u32 	%r353, %r71;

$L__BB0_7:
	mov.u32 	%r355, %r71;

$L__BB0_8:
	cvt.rn.f32.s32 	%f1069, %r353;
	mad.lo.s32 	%r73, %r356, 1664525, 1013904223;
	and.b32  	%r74, %r73, 16777215;
	cvt.rn.f32.u32 	%f312, %r74;
	fma.rn.f32 	%f313, %f312, 0f33800000, %f1069;
	mul.f32 	%f314, %f19, %f313;
	mad.lo.s32 	%r356, %r73, 1664525, 1013904223;
	and.b32  	%r75, %r356, 16777215;
	cvt.rn.f32.u32 	%f315, %r75;
	cvt.rn.f32.s32 	%f316, %r355;
	fma.rn.f32 	%f317, %f315, 0f33800000, %f316;
	mul.f32 	%f318, %f19, %f317;
	fma.rn.f32 	%f319, %f19, %f313, %f314;
	mov.f32 	%f320, 0f3F800000;
	sub.f32 	%f57, %f320, %f319;
	mul.f32 	%f321, %f57, %f57;
	sub.f32 	%f322, %f320, %f321;
	mov.f32 	%f323, 0f00000000;
	max.f32 	%f324, %f323, %f322;
	sqrt.rn.f32 	%f58, %f324;
	mul.f32 	%f59, %f318, 0f40C90FDB;
	mul.f32 	%f325, %f59, 0f3F22F983;
	cvt.rni.s32.f32 	%r360, %f325;
	cvt.rn.f32.s32 	%f326, %r360;
	mov.f32 	%f327, 0fBFC90FDA;
	fma.rn.f32 	%f328, %f326, %f327, %f59;
	mov.f32 	%f329, 0fB3A22168;
	fma.rn.f32 	%f330, %f326, %f329, %f328;
	mov.f32 	%f331, 0fA7C234C5;
	fma.rn.f32 	%f1128, %f326, %f331, %f330;
	abs.f32 	%f61, %f59;
	setp.ltu.f32 	%p16, %f61, 0f47CE4780;
	mov.f32 	%f1125, %f1128;
	@%p16 bra 	$L__BB0_16;

	setp.eq.f32 	%p17, %f61, 0f7F800000;
	@%p17 bra 	$L__BB0_15;
	bra.uni 	$L__BB0_10;

$L__BB0_15:
	mov.f32 	%f334, 0f00000000;
	mul.rn.f32 	%f1125, %f59, %f334;
	mov.u32 	%r360, 0;
	bra.uni 	$L__BB0_16;

$L__BB0_10:
	mov.b32 	%r14, %f59;
	bfe.u32 	%r77, %r14, 23, 8;
	mov.u64 	%rd119, 0;
	mov.u32 	%r357, 0;
	mov.u64 	%rd117, %rd1;
	mov.u64 	%rd118, %rd41;

$L__BB0_11:
	.pragma "nounroll";
	mov.b32 	%r336, %f59;
	shl.b32 	%r335, %r336, 8;
	or.b32  	%r334, %r335, -2147483648;
	ld.global.nc.u32 	%r79, [%rd118];
	mad.wide.u32 	%rd43, %r79, %r334, %rd119;
	shr.u64 	%rd119, %rd43, 32;
	st.local.u32 	[%rd117], %rd43;
	add.s64 	%rd118, %rd118, 4;
	add.s64 	%rd117, %rd117, 4;
	add.s32 	%r357, %r357, 1;
	setp.ne.s32 	%p18, %r357, 6;
	@%p18 bra 	$L__BB0_11;

	add.s32 	%r341, %r77, -128;
	mov.b32 	%r340, %f59;
	bfe.u32 	%r339, %r340, 23, 8;
	add.s32 	%r338, %r339, -128;
	shr.u32 	%r337, %r338, 5;
	st.local.u32 	[%rd5], %rd119;
	mov.u32 	%r81, 6;
	sub.s32 	%r82, %r81, %r337;
	mul.wide.s32 	%rd44, %r82, 4;
	add.s64 	%rd45, %rd1, %rd44;
	ld.local.u32 	%r358, [%rd45];
	ld.local.u32 	%r359, [%rd45+-4];
	and.b32  	%r23, %r338, 31;
	setp.eq.s32 	%p19, %r23, 0;
	@%p19 bra 	$L__BB0_14;

	mov.b32 	%r348, %f59;
	bfe.u32 	%r347, %r348, 23, 8;
	add.s32 	%r346, %r347, -128;
	shr.u32 	%r345, %r346, 5;
	mov.u32 	%r344, 4;
	sub.s32 	%r343, %r344, %r345;
	mov.u32 	%r83, 32;
	sub.s32 	%r84, %r83, %r23;
	shr.u32 	%r85, %r359, %r84;
	shl.b32 	%r86, %r358, %r23;
	add.s32 	%r358, %r85, %r86;
	mul.wide.s32 	%rd46, %r343, 4;
	add.s64 	%rd47, %rd1, %rd46;
	ld.local.u32 	%r87, [%rd47];
	shr.u32 	%r88, %r87, %r84;
	shl.b32 	%r89, %r359, %r23;
	add.s32 	%r359, %r88, %r89;

$L__BB0_14:
	mov.b32 	%r342, %f59;
	and.b32  	%r90, %r342, -2147483648;
	shr.u32 	%r91, %r359, 30;
	shl.b32 	%r92, %r358, 2;
	or.b32  	%r93, %r91, %r92;
	shr.u32 	%r94, %r93, 31;
	shr.u32 	%r95, %r358, 30;
	add.s32 	%r96, %r94, %r95;
	neg.s32 	%r97, %r96;
	setp.eq.s32 	%p20, %r90, 0;
	selp.b32 	%r360, %r96, %r97, %p20;
	setp.ne.s32 	%p21, %r94, 0;
	xor.b32  	%r98, %r90, -2147483648;
	selp.b32 	%r99, %r98, %r90, %p21;
	selp.b32 	%r100, -1, 0, %p21;
	xor.b32  	%r101, %r93, %r100;
	shl.b32 	%r102, %r359, 2;
	xor.b32  	%r103, %r102, %r100;
	cvt.u64.u32 	%rd48, %r101;
	cvt.u64.u32 	%rd49, %r103;
	bfi.b64 	%rd50, %rd48, %rd49, 32, 32;
	cvt.rn.f64.s64 	%fd1, %rd50;
	mul.f64 	%fd2, %fd1, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f332, %fd2;
	setp.eq.s32 	%p22, %r99, 0;
	neg.f32 	%f333, %f332;
	selp.f32 	%f1125, %f332, %f333, %p22;

$L__BB0_16:
	add.s32 	%r30, %r360, 1;
	and.b32  	%r31, %r30, 1;
	setp.eq.s32 	%p23, %r31, 0;
	selp.f32 	%f65, %f1125, 0f3F800000, %p23;
	mul.rn.f32 	%f66, %f1125, %f1125;
	mov.f32 	%f1126, 0fB94D4153;
	@%p23 bra 	$L__BB0_18;

	mov.f32 	%f336, 0fBAB607ED;
	mov.f32 	%f337, 0f37CBAC00;
	fma.rn.f32 	%f1126, %f337, %f66, %f336;

$L__BB0_18:
	selp.f32 	%f338, 0f3C0885E4, 0f3D2AAABB, %p23;
	fma.rn.f32 	%f339, %f1126, %f66, %f338;
	selp.f32 	%f340, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
	fma.rn.f32 	%f341, %f339, %f66, %f340;
	mov.f32 	%f342, 0f00000000;
	fma.rn.f32 	%f343, %f66, %f65, %f342;
	fma.rn.f32 	%f1127, %f341, %f343, %f65;
	and.b32  	%r105, %r30, 2;
	setp.eq.s32 	%p25, %r105, 0;
	@%p25 bra 	$L__BB0_20;

	mov.f32 	%f345, 0fBF800000;
	fma.rn.f32 	%f1127, %f1127, %f345, %f342;

$L__BB0_20:
	mul.f32 	%f1070, %f59, 0f3F22F983;
	cvt.rni.s32.f32 	%r363, %f1070;
	setp.ltu.f32 	%p155, %f61, 0f47CE4780;
	@%p155 bra 	$L__BB0_28;

	setp.eq.f32 	%p27, %f61, 0f7F800000;
	@%p27 bra 	$L__BB0_27;
	bra.uni 	$L__BB0_22;

$L__BB0_27:
	mov.f32 	%f348, 0f00000000;
	mul.rn.f32 	%f1128, %f59, %f348;
	mov.u32 	%r363, 0;
	bra.uni 	$L__BB0_28;

$L__BB0_22:
	mov.b32 	%r32, %f59;
	bfe.u32 	%r106, %r32, 23, 8;
	add.s32 	%r33, %r106, -128;
	shl.b32 	%r107, %r32, 8;
	or.b32  	%r34, %r107, -2147483648;
	shr.u32 	%r35, %r33, 5;
	mov.u64 	%rd120, 0;
	mov.u64 	%rd121, %rd120;

$L__BB0_23:
	.pragma "nounroll";
	shl.b64 	%rd53, %rd120, 2;
	mov.u64 	%rd54, __cudart_i2opi_f;
	add.s64 	%rd55, %rd54, %rd53;
	ld.global.nc.u32 	%r108, [%rd55];
	mad.wide.u32 	%rd56, %r108, %r34, %rd121;
	shr.u64 	%rd121, %rd56, 32;
	add.s64 	%rd57, %rd1, %rd53;
	st.local.u32 	[%rd57], %rd56;
	cvt.u32.u64 	%r109, %rd120;
	add.s32 	%r110, %r109, 1;
	cvt.s64.s32 	%rd120, %r110;
	setp.ne.s32 	%p28, %r110, 6;
	@%p28 bra 	$L__BB0_23;

	st.local.u32 	[%rd5], %rd121;
	mov.u32 	%r111, 4;
	sub.s32 	%r36, %r111, %r35;
	mov.u32 	%r112, 6;
	sub.s32 	%r113, %r112, %r35;
	mul.wide.s32 	%rd58, %r113, 4;
	add.s64 	%rd59, %rd1, %rd58;
	ld.local.u32 	%r361, [%rd59];
	ld.local.u32 	%r362, [%rd59+-4];
	and.b32  	%r39, %r33, 31;
	setp.eq.s32 	%p29, %r39, 0;
	@%p29 bra 	$L__BB0_26;

	mov.u32 	%r114, 32;
	sub.s32 	%r115, %r114, %r39;
	shr.u32 	%r116, %r362, %r115;
	shl.b32 	%r117, %r361, %r39;
	add.s32 	%r361, %r116, %r117;
	mul.wide.s32 	%rd60, %r36, 4;
	add.s64 	%rd61, %rd1, %rd60;
	ld.local.u32 	%r118, [%rd61];
	shr.u32 	%r119, %r118, %r115;
	shl.b32 	%r120, %r362, %r39;
	add.s32 	%r362, %r119, %r120;

$L__BB0_26:
	and.b32  	%r121, %r32, -2147483648;
	shr.u32 	%r122, %r362, 30;
	shl.b32 	%r123, %r361, 2;
	or.b32  	%r124, %r122, %r123;
	shr.u32 	%r125, %r124, 31;
	shr.u32 	%r126, %r361, 30;
	add.s32 	%r127, %r125, %r126;
	neg.s32 	%r128, %r127;
	setp.eq.s32 	%p30, %r121, 0;
	selp.b32 	%r363, %r127, %r128, %p30;
	setp.ne.s32 	%p31, %r125, 0;
	xor.b32  	%r129, %r121, -2147483648;
	selp.b32 	%r130, %r129, %r121, %p31;
	selp.b32 	%r131, -1, 0, %p31;
	xor.b32  	%r132, %r124, %r131;
	shl.b32 	%r133, %r362, 2;
	xor.b32  	%r134, %r133, %r131;
	cvt.u64.u32 	%rd62, %r132;
	cvt.u64.u32 	%rd63, %r134;
	bfi.b64 	%rd64, %rd62, %rd63, 32, 32;
	cvt.rn.f64.s64 	%fd3, %rd64;
	mul.f64 	%fd4, %fd3, 0d3BF921FB54442D19;
	cvt.rn.f32.f64 	%f346, %fd4;
	setp.eq.s32 	%p32, %r130, 0;
	neg.f32 	%f347, %f346;
	selp.f32 	%f1128, %f346, %f347, %p32;

$L__BB0_28:
	mul.f32 	%f75, %f58, %f1127;
	and.b32  	%r46, %r363, 1;
	setp.eq.s32 	%p33, %r46, 0;
	selp.f32 	%f76, %f1128, 0f3F800000, %p33;
	mul.rn.f32 	%f77, %f1128, %f1128;
	mov.f32 	%f1129, 0fB94D4153;
	@%p33 bra 	$L__BB0_30;

	mov.f32 	%f350, 0fBAB607ED;
	mov.f32 	%f351, 0f37CBAC00;
	fma.rn.f32 	%f1129, %f351, %f77, %f350;

$L__BB0_30:
	selp.f32 	%f352, 0f3C0885E4, 0f3D2AAABB, %p33;
	fma.rn.f32 	%f353, %f1129, %f77, %f352;
	selp.f32 	%f354, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
	fma.rn.f32 	%f355, %f353, %f77, %f354;
	mov.f32 	%f356, 0f00000000;
	fma.rn.f32 	%f357, %f77, %f76, %f356;
	fma.rn.f32 	%f1130, %f355, %f357, %f76;
	and.b32  	%r136, %r363, 2;
	setp.eq.s32 	%p35, %r136, 0;
	@%p35 bra 	$L__BB0_32;

	mov.f32 	%f359, 0fBF800000;
	fma.rn.f32 	%f1130, %f1130, %f359, %f356;

$L__BB0_32:
	mul.f32 	%f369, %f58, %f1130;
	mul.f32 	%f370, %f16, %f369;
	mul.f32 	%f371, %f17, %f369;
	mul.f32 	%f372, %f18, %f369;
	fma.rn.f32 	%f373, %f25, %f75, %f370;
	fma.rn.f32 	%f374, %f24, %f75, %f371;
	fma.rn.f32 	%f375, %f23, %f75, %f372;
	fma.rn.f32 	%f363, %f1092, %f57, %f373;
	fma.rn.f32 	%f364, %f1093, %f57, %f374;
	fma.rn.f32 	%f365, %f1094, %f57, %f375;
	mov.f32 	%f381, 0f38D1B717;
	max.f32 	%f366, %f380, %f381;
	mov.f32 	%f367, 0f6C4ECB8F;
	mov.u32 	%r170, 1;
	mov.u32 	%r173, 2;
	mov.u32 	%r175, 4;
	mov.u32 	%r178, 1065353216;
	mov.u32 	%r179, 2139095039;
	mov.u32 	%r207, 0;
	// begin inline asm
	call(%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168),_optix_trace_typed_32,(%r207,%rd4,%f13,%f14,%f15,%f363,%f364,%f365,%f366,%f367,%f356,%r170,%r207,%r207,%r173,%r207,%r175,%r178,%r178,%r178,%r179,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207);
	// end inline asm
	mov.b32 	%f382, %r137;
	mov.b32 	%f383, %r138;
	mov.b32 	%f384, %r139;
	mov.b32 	%f385, %r140;
	setp.ltu.f32 	%p36, %f385, 0f00000000;
	selp.f32 	%f386, %f384, 0f00000000, %p36;
	selp.f32 	%f387, %f383, 0f00000000, %p36;
	selp.f32 	%f388, %f382, 0f00000000, %p36;
	mul.f32 	%f389, %f1093, %f364;
	fma.rn.f32 	%f390, %f1092, %f363, %f389;
	fma.rn.f32 	%f391, %f1094, %f365, %f390;
	fma.rn.f32 	%f1118, %f363, %f388, %f1118;
	fma.rn.f32 	%f1117, %f363, %f387, %f1117;
	fma.rn.f32 	%f1116, %f363, %f386, %f1116;
	fma.rn.f32 	%f1121, %f364, %f388, %f1121;
	fma.rn.f32 	%f1120, %f364, %f387, %f1120;
	fma.rn.f32 	%f1119, %f364, %f386, %f1119;
	fma.rn.f32 	%f1124, %f365, %f388, %f1124;
	fma.rn.f32 	%f1123, %f365, %f387, %f1123;
	fma.rn.f32 	%f1122, %f365, %f386, %f1122;
	add.f32 	%f1115, %f1115, %f388;
	add.f32 	%f1114, %f1114, %f387;
	add.f32 	%f1113, %f1113, %f386;
	cvt.sat.f32.f32 	%f392, %f391;
	fma.rn.f32 	%f1112, %f392, %f388, %f1112;
	fma.rn.f32 	%f1111, %f392, %f387, %f1111;
	fma.rn.f32 	%f1110, %f392, %f386, %f1110;
	add.s32 	%r355, %r355, 1;
	setp.lt.s32 	%p37, %r355, %r4;
	@%p37 bra 	$L__BB0_8;

	add.s32 	%r353, %r353, 1;
	setp.lt.s32 	%p38, %r353, %r4;
	@%p38 bra 	$L__BB0_7;

$L__BB0_34:
	mov.f32 	%f1146, 0f00000000;
	mul.lo.s32 	%r208, %r4, %r4;
	cvt.rn.f32.s32 	%f396, %r208;
	rcp.rn.f32 	%f397, %f396;
	mul.f32 	%f398, %f397, %f1112;
	mul.f32 	%f399, %f397, %f1111;
	mul.f32 	%f400, %f397, %f1110;
	mul.f32 	%f113, %f397, %f1115;
	mul.f32 	%f114, %f397, %f1114;
	mul.f32 	%f115, %f397, %f1113;
	mul.f32 	%f116, %f397, %f1118;
	mul.f32 	%f117, %f397, %f1117;
	mul.f32 	%f118, %f397, %f1116;
	mul.f32 	%f119, %f397, %f1121;
	mul.f32 	%f120, %f397, %f1120;
	mul.f32 	%f121, %f397, %f1119;
	mul.f32 	%f122, %f397, %f1124;
	mul.f32 	%f123, %f397, %f1123;
	mul.f32 	%f124, %f397, %f1122;
	fma.rn.f32 	%f401, %f397, %f1112, %f398;
	fma.rn.f32 	%f402, %f397, %f1111, %f399;
	fma.rn.f32 	%f403, %f397, %f1110, %f400;
	ld.const.u64 	%rd66, [params+504];
	cvt.rn.f32.u32 	%f404, %r6;
	cvt.rn.f32.u32 	%f405, %r5;
	tex.2d.v4.f32.f32 	{%f406, %f407, %f408, %f409}, [%rd66, {%f405, %f404}];
	mul.f32 	%f125, %f401, %f406;
	mul.f32 	%f126, %f402, %f407;
	mul.f32 	%f127, %f403, %f408;
	add.f32 	%f128, %f242, %f125;
	add.f32 	%f129, %f243, %f126;
	add.f32 	%f130, %f244, %f127;
	abs.f32 	%f410, %f128;
	setp.gtu.f32 	%p39, %f410, 0f7F800000;
	mov.f32 	%f1147, %f1146;
	mov.f32 	%f1148, %f1146;
	@%p39 bra 	$L__BB0_38;

	mov.f32 	%f1146, 0f00000000;
	abs.f32 	%f414, %f129;
	setp.gtu.f32 	%p40, %f414, 0f7F800000;
	@%p40 bra 	$L__BB0_38;

	mov.f32 	%f1146, 0f00000000;
	abs.f32 	%f418, %f130;
	setp.gtu.f32 	%p41, %f418, 0f7F800000;
	mov.f32 	%f1147, %f1146;
	mov.f32 	%f1148, %f1146;
	@%p41 bra 	$L__BB0_38;

	mov.f32 	%f1146, %f128;
	mov.f32 	%f1147, %f129;
	mov.f32 	%f1148, %f130;

$L__BB0_38:
	ld.const.u32 	%r49, [params+104];
	and.b32  	%r209, %r49, 1;
	setp.eq.b32 	%p42, %r209, 1;
	mov.pred 	%p43, 0;
	xor.pred  	%p44, %p42, %p43;
	not.pred 	%p45, %p44;
	@%p45 bra 	$L__BB0_112;

	mov.f32 	%f423, 0f3EE66666;
	abs.f32 	%f141, %f1146;
	setp.lt.f32 	%p46, %f141, 0f00800000;
	mul.f32 	%f425, %f141, 0f4B800000;
	selp.f32 	%f426, %f425, %f141, %p46;
	selp.f32 	%f427, 0fC3170000, 0fC2FE0000, %p46;
	mov.b32 	%r210, %f426;
	and.b32  	%r211, %r210, 8388607;
	or.b32  	%r212, %r211, 1065353216;
	mov.b32 	%f428, %r212;
	shr.u32 	%r213, %r210, 23;
	cvt.rn.f32.u32 	%f429, %r213;
	add.f32 	%f430, %f427, %f429;
	setp.gt.f32 	%p47, %f428, 0f3FB504F3;
	mul.f32 	%f431, %f428, 0f3F000000;
	add.f32 	%f432, %f430, 0f3F800000;
	selp.f32 	%f433, %f432, %f430, %p47;
	selp.f32 	%f434, %f431, %f428, %p47;
	add.f32 	%f435, %f434, 0fBF800000;
	add.f32 	%f436, %f434, 0f3F800000;
	rcp.approx.ftz.f32 	%f437, %f436;
	add.f32 	%f438, %f435, %f435;
	mul.f32 	%f439, %f438, %f437;
	mul.f32 	%f440, %f439, %f439;
	mov.f32 	%f441, 0f3C4CAF63;
	mov.f32 	%f442, 0f3B18F0FE;
	fma.rn.f32 	%f443, %f442, %f440, %f441;
	mov.f32 	%f444, 0f3DAAAABD;
	fma.rn.f32 	%f445, %f443, %f440, %f444;
	mul.rn.f32 	%f446, %f445, %f440;
	mul.rn.f32 	%f447, %f446, %f439;
	sub.f32 	%f448, %f435, %f439;
	add.f32 	%f449, %f448, %f448;
	neg.f32 	%f450, %f439;
	fma.rn.f32 	%f451, %f450, %f435, %f449;
	mul.rn.f32 	%f452, %f437, %f451;
	add.f32 	%f453, %f447, %f439;
	sub.f32 	%f454, %f439, %f453;
	add.f32 	%f455, %f447, %f454;
	add.f32 	%f456, %f452, %f455;
	add.f32 	%f457, %f453, %f456;
	sub.f32 	%f458, %f453, %f457;
	add.f32 	%f459, %f456, %f458;
	mov.f32 	%f460, 0f3F317200;
	mul.rn.f32 	%f461, %f433, %f460;
	mov.f32 	%f462, 0f35BFBE8E;
	mul.rn.f32 	%f463, %f433, %f462;
	add.f32 	%f464, %f461, %f457;
	sub.f32 	%f465, %f461, %f464;
	add.f32 	%f466, %f457, %f465;
	add.f32 	%f467, %f459, %f466;
	add.f32 	%f468, %f463, %f467;
	add.f32 	%f469, %f464, %f468;
	sub.f32 	%f470, %f464, %f469;
	add.f32 	%f471, %f468, %f470;
	mul.rn.f32 	%f472, %f423, %f469;
	neg.f32 	%f473, %f472;
	fma.rn.f32 	%f474, %f423, %f469, %f473;
	fma.rn.f32 	%f475, %f423, %f471, %f474;
	mov.f32 	%f476, 0f00000000;
	fma.rn.f32 	%f477, %f476, %f469, %f475;
	add.rn.f32 	%f478, %f472, %f477;
	neg.f32 	%f479, %f478;
	add.rn.f32 	%f480, %f472, %f479;
	add.rn.f32 	%f481, %f480, %f477;
	mov.b32 	%r214, %f478;
	setp.eq.s32 	%p48, %r214, 1118925336;
	add.s32 	%r215, %r214, -1;
	mov.b32 	%f482, %r215;
	add.f32 	%f483, %f481, 0f37000000;
	selp.f32 	%f142, %f483, %f481, %p48;
	selp.f32 	%f484, %f482, %f478, %p48;
	mov.f32 	%f485, 0f3FB8AA3B;
	mul.rn.f32 	%f486, %f484, %f485;
	cvt.rzi.f32.f32 	%f487, %f486;
	abs.f32 	%f488, %f487;
	setp.gt.f32 	%p49, %f488, 0f42FC0000;
	mov.b32 	%r216, %f487;
	and.b32  	%r217, %r216, -2147483648;
	or.b32  	%r218, %r217, 1123811328;
	mov.b32 	%f489, %r218;
	selp.f32 	%f490, %f489, %f487, %p49;
	mov.f32 	%f491, 0fBF317218;
	fma.rn.f32 	%f492, %f490, %f491, %f484;
	mov.f32 	%f493, 0f3102E308;
	fma.rn.f32 	%f494, %f490, %f493, %f492;
	mul.f32 	%f495, %f494, 0f3FB8AA3B;
	add.f32 	%f496, %f490, 0f4B40007F;
	mov.b32 	%r219, %f496;
	shl.b32 	%r220, %r219, 23;
	mov.b32 	%f497, %r220;
	ex2.approx.ftz.f32 	%f498, %f495;
	mul.f32 	%f143, %f498, %f497;
	setp.eq.f32 	%p50, %f143, 0f7F800000;
	mov.f32 	%f1149, 0f7F800000;
	@%p50 bra 	$L__BB0_41;

	fma.rn.f32 	%f1149, %f143, %f142, %f143;

$L__BB0_41:
	mov.f32 	%f1076, 0f3E666666;
	cvt.rzi.f32.f32 	%f1075, %f1076;
	add.f32 	%f1074, %f1075, %f1075;
	mov.f32 	%f1073, 0f3EE66666;
	sub.f32 	%f1072, %f1073, %f1074;
	abs.f32 	%f1071, %f1072;
	setp.lt.f32 	%p51, %f1146, 0f00000000;
	setp.eq.f32 	%p52, %f1071, 0f3F800000;
	and.pred  	%p1, %p51, %p52;
	setp.eq.f32 	%p53, %f1146, 0f00000000;
	@%p53 bra 	$L__BB0_45;
	bra.uni 	$L__BB0_42;

$L__BB0_45:
	add.f32 	%f503, %f1146, %f1146;
	selp.f32 	%f1151, %f503, 0f00000000, %p52;
	bra.uni 	$L__BB0_46;

$L__BB0_136:
	mov.f32 	%f1035, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs117, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs116, %f1035;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs115, %f1035;}

	// end inline asm
	mov.u16 	%rs118, 0;
	st.global.v4.u16 	[%rd22], {%rs115, %rs116, %rs117, %rs118};

$L__BB0_137:
	ld.const.u64 	%rd105, [params+272];
	cvta.to.global.u64 	%rd106, %rd105;
	ld.const.u32 	%r327, [params+264];
	mad.lo.s32 	%r328, %r327, %r6, %r5;
	mul.wide.u32 	%rd107, %r328, 8;
	add.s64 	%rd23, %rd106, %rd107;
	@%p151 bra 	$L__BB0_139;

	ld.global.v4.u16 	{%rs125, %rs126, %rs127, %rs128}, [%rd23];
	// begin inline asm
	{  cvt.f32.f16 %f1036, %rs125;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1037, %rs126;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1038, %rs127;}

	// end inline asm
	add.f32 	%f1039, %f1036, 0f00000000;
	add.f32 	%f1040, %f1037, 0f00000000;
	add.f32 	%f1041, %f1038, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs124, %f1041;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs123, %f1040;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs122, %f1039;}

	// end inline asm
	mov.u16 	%rs129, 0;
	st.global.v4.u16 	[%rd23], {%rs122, %rs123, %rs124, %rs129};
	bra.uni 	$L__BB0_140;

$L__BB0_139:
	mov.f32 	%f1044, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs132, %f1044;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs131, %f1044;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs130, %f1044;}

	// end inline asm
	mov.u16 	%rs133, 0;
	st.global.v4.u16 	[%rd23], {%rs130, %rs131, %rs132, %rs133};

$L__BB0_140:
	ld.const.u64 	%rd108, [params+288];
	cvta.to.global.u64 	%rd109, %rd108;
	ld.const.u32 	%r329, [params+280];
	mad.lo.s32 	%r330, %r329, %r6, %r5;
	mul.wide.u32 	%rd110, %r330, 8;
	add.s64 	%rd24, %rd109, %rd110;
	@%p151 bra 	$L__BB0_142;

	ld.global.v4.u16 	{%rs140, %rs141, %rs142, %rs143}, [%rd24];
	// begin inline asm
	{  cvt.f32.f16 %f1045, %rs140;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1046, %rs141;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1047, %rs142;}

	// end inline asm
	add.f32 	%f1048, %f1045, 0f00000000;
	add.f32 	%f1049, %f1046, 0f00000000;
	add.f32 	%f1050, %f1047, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs139, %f1050;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs138, %f1049;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs137, %f1048;}

	// end inline asm
	mov.u16 	%rs144, 0;
	st.global.v4.u16 	[%rd24], {%rs137, %rs138, %rs139, %rs144};
	bra.uni 	$L__BB0_143;

$L__BB0_142:
	mov.f32 	%f1053, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs147, %f1053;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs146, %f1053;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs145, %f1053;}

	// end inline asm
	mov.u16 	%rs148, 0;
	st.global.v4.u16 	[%rd24], {%rs145, %rs146, %rs147, %rs148};

$L__BB0_143:
	ld.const.u64 	%rd111, [params+304];
	cvta.to.global.u64 	%rd112, %rd111;
	ld.const.u32 	%r331, [params+296];
	mad.lo.s32 	%r332, %r331, %r6, %r5;
	mul.wide.u32 	%rd113, %r332, 8;
	add.s64 	%rd25, %rd112, %rd113;
	@%p151 bra 	$L__BB0_145;

	ld.global.v4.u16 	{%rs155, %rs156, %rs157, %rs158}, [%rd25];
	// begin inline asm
	{  cvt.f32.f16 %f1054, %rs155;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1055, %rs156;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1056, %rs157;}

	// end inline asm
	add.f32 	%f1057, %f1054, 0f00000000;
	add.f32 	%f1058, %f1055, 0f00000000;
	add.f32 	%f1059, %f1056, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs154, %f1059;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs153, %f1058;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs152, %f1057;}

	// end inline asm
	mov.u16 	%rs159, 0;
	st.global.v4.u16 	[%rd25], {%rs152, %rs153, %rs154, %rs159};
	bra.uni 	$L__BB0_146;

$L__BB0_145:
	mov.f32 	%f1062, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs162, %f1062;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs161, %f1062;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs160, %f1062;}

	// end inline asm
	mov.u16 	%rs163, 0;
	st.global.v4.u16 	[%rd25], {%rs160, %rs161, %rs162, %rs163};
	bra.uni 	$L__BB0_146;

$L__BB0_42:
	mov.b32 	%r221, %f1149;
	xor.b32  	%r222, %r221, -2147483648;
	mov.b32 	%f499, %r222;
	selp.f32 	%f1151, %f499, %f1149, %p1;
	setp.geu.f32 	%p54, %f1146, 0f00000000;
	@%p54 bra 	$L__BB0_46;

	mov.f32 	%f500, 0f3EE66666;
	cvt.rzi.f32.f32 	%f501, %f500;
	setp.eq.f32 	%p55, %f501, 0f3EE66666;
	@%p55 bra 	$L__BB0_46;

	mov.f32 	%f1151, 0f7FFFFFFF;

$L__BB0_46:
	abs.f32 	%f1077, %f1146;
	add.f32 	%f504, %f1077, 0f3EE66666;
	mov.b32 	%r223, %f504;
	setp.lt.s32 	%p57, %r223, 2139095040;
	@%p57 bra 	$L__BB0_51;

	abs.f32 	%f1078, %f1146;
	setp.gtu.f32 	%p58, %f1078, 0f7F800000;
	@%p58 bra 	$L__BB0_50;
	bra.uni 	$L__BB0_48;

$L__BB0_50:
	add.f32 	%f1151, %f1146, 0f3EE66666;
	bra.uni 	$L__BB0_51;

$L__BB0_48:
	abs.f32 	%f1079, %f1146;
	setp.neu.f32 	%p59, %f1079, 0f7F800000;
	@%p59 bra 	$L__BB0_51;

	selp.f32 	%f1151, 0fFF800000, 0f7F800000, %p1;

$L__BB0_51:
	setp.eq.f32 	%p60, %f1146, 0f3F800000;
	selp.f32 	%f152, 0f3F800000, %f1151, %p60;
	abs.f32 	%f153, %f1147;
	setp.lt.f32 	%p61, %f153, 0f00800000;
	mul.f32 	%f506, %f153, 0f4B800000;
	selp.f32 	%f507, %f506, %f153, %p61;
	selp.f32 	%f508, 0fC3170000, 0fC2FE0000, %p61;
	mov.b32 	%r224, %f507;
	and.b32  	%r225, %r224, 8388607;
	or.b32  	%r226, %r225, 1065353216;
	mov.b32 	%f509, %r226;
	shr.u32 	%r227, %r224, 23;
	cvt.rn.f32.u32 	%f510, %r227;
	add.f32 	%f511, %f508, %f510;
	setp.gt.f32 	%p62, %f509, 0f3FB504F3;
	mul.f32 	%f512, %f509, 0f3F000000;
	add.f32 	%f513, %f511, 0f3F800000;
	selp.f32 	%f514, %f513, %f511, %p62;
	selp.f32 	%f515, %f512, %f509, %p62;
	add.f32 	%f516, %f515, 0fBF800000;
	add.f32 	%f517, %f515, 0f3F800000;
	rcp.approx.ftz.f32 	%f518, %f517;
	add.f32 	%f519, %f516, %f516;
	mul.f32 	%f520, %f519, %f518;
	mul.f32 	%f521, %f520, %f520;
	mov.f32 	%f522, 0f3C4CAF63;
	mov.f32 	%f523, 0f3B18F0FE;
	fma.rn.f32 	%f524, %f523, %f521, %f522;
	mov.f32 	%f525, 0f3DAAAABD;
	fma.rn.f32 	%f526, %f524, %f521, %f525;
	mul.rn.f32 	%f527, %f526, %f521;
	mul.rn.f32 	%f528, %f527, %f520;
	sub.f32 	%f529, %f516, %f520;
	add.f32 	%f530, %f529, %f529;
	neg.f32 	%f531, %f520;
	fma.rn.f32 	%f532, %f531, %f516, %f530;
	mul.rn.f32 	%f533, %f518, %f532;
	add.f32 	%f534, %f528, %f520;
	sub.f32 	%f535, %f520, %f534;
	add.f32 	%f536, %f528, %f535;
	add.f32 	%f537, %f533, %f536;
	add.f32 	%f538, %f534, %f537;
	sub.f32 	%f539, %f534, %f538;
	add.f32 	%f540, %f537, %f539;
	mov.f32 	%f541, 0f3F317200;
	mul.rn.f32 	%f542, %f514, %f541;
	mov.f32 	%f543, 0f35BFBE8E;
	mul.rn.f32 	%f544, %f514, %f543;
	add.f32 	%f545, %f542, %f538;
	sub.f32 	%f546, %f542, %f545;
	add.f32 	%f547, %f538, %f546;
	add.f32 	%f548, %f540, %f547;
	add.f32 	%f549, %f544, %f548;
	add.f32 	%f550, %f545, %f549;
	sub.f32 	%f551, %f545, %f550;
	add.f32 	%f552, %f549, %f551;
	mov.f32 	%f553, 0f3EE66666;
	mul.rn.f32 	%f554, %f553, %f550;
	neg.f32 	%f555, %f554;
	fma.rn.f32 	%f556, %f553, %f550, %f555;
	fma.rn.f32 	%f557, %f553, %f552, %f556;
	mov.f32 	%f558, 0f00000000;
	fma.rn.f32 	%f559, %f558, %f550, %f557;
	add.rn.f32 	%f560, %f554, %f559;
	neg.f32 	%f561, %f560;
	add.rn.f32 	%f562, %f554, %f561;
	add.rn.f32 	%f563, %f562, %f559;
	mov.b32 	%r228, %f560;
	setp.eq.s32 	%p63, %r228, 1118925336;
	add.s32 	%r229, %r228, -1;
	mov.b32 	%f564, %r229;
	add.f32 	%f565, %f563, 0f37000000;
	selp.f32 	%f154, %f565, %f563, %p63;
	selp.f32 	%f566, %f564, %f560, %p63;
	mov.f32 	%f567, 0f3FB8AA3B;
	mul.rn.f32 	%f568, %f566, %f567;
	cvt.rzi.f32.f32 	%f569, %f568;
	abs.f32 	%f570, %f569;
	setp.gt.f32 	%p64, %f570, 0f42FC0000;
	mov.b32 	%r230, %f569;
	and.b32  	%r231, %r230, -2147483648;
	or.b32  	%r232, %r231, 1123811328;
	mov.b32 	%f571, %r232;
	selp.f32 	%f572, %f571, %f569, %p64;
	mov.f32 	%f573, 0fBF317218;
	fma.rn.f32 	%f574, %f572, %f573, %f566;
	mov.f32 	%f575, 0f3102E308;
	fma.rn.f32 	%f576, %f572, %f575, %f574;
	mul.f32 	%f577, %f576, 0f3FB8AA3B;
	add.f32 	%f578, %f572, 0f4B40007F;
	mov.b32 	%r233, %f578;
	shl.b32 	%r234, %r233, 23;
	mov.b32 	%f579, %r234;
	ex2.approx.ftz.f32 	%f580, %f577;
	mul.f32 	%f155, %f580, %f579;
	setp.eq.f32 	%p65, %f155, 0f7F800000;
	mov.f32 	%f1152, 0f7F800000;
	@%p65 bra 	$L__BB0_53;

	fma.rn.f32 	%f1152, %f155, %f154, %f155;

$L__BB0_53:
	setp.lt.f32 	%p66, %f1147, 0f00000000;
	and.pred  	%p2, %p66, %p52;
	setp.eq.f32 	%p68, %f1147, 0f00000000;
	@%p68 bra 	$L__BB0_57;
	bra.uni 	$L__BB0_54;

$L__BB0_57:
	add.f32 	%f585, %f1147, %f1147;
	selp.f32 	%f1154, %f585, 0f00000000, %p52;
	bra.uni 	$L__BB0_58;

$L__BB0_54:
	mov.b32 	%r235, %f1152;
	xor.b32  	%r236, %r235, -2147483648;
	mov.b32 	%f581, %r236;
	selp.f32 	%f1154, %f581, %f1152, %p2;
	setp.geu.f32 	%p69, %f1147, 0f00000000;
	@%p69 bra 	$L__BB0_58;

	mov.f32 	%f582, 0f3EE66666;
	cvt.rzi.f32.f32 	%f583, %f582;
	setp.eq.f32 	%p70, %f583, 0f3EE66666;
	@%p70 bra 	$L__BB0_58;

	mov.f32 	%f1154, 0f7FFFFFFF;

$L__BB0_58:
	abs.f32 	%f1080, %f1147;
	add.f32 	%f586, %f1080, 0f3EE66666;
	mov.b32 	%r237, %f586;
	setp.lt.s32 	%p72, %r237, 2139095040;
	@%p72 bra 	$L__BB0_63;

	abs.f32 	%f1081, %f1147;
	setp.gtu.f32 	%p73, %f1081, 0f7F800000;
	@%p73 bra 	$L__BB0_62;
	bra.uni 	$L__BB0_60;

$L__BB0_62:
	add.f32 	%f1154, %f1147, 0f3EE66666;
	bra.uni 	$L__BB0_63;

$L__BB0_60:
	abs.f32 	%f1082, %f1147;
	setp.neu.f32 	%p74, %f1082, 0f7F800000;
	@%p74 bra 	$L__BB0_63;

	selp.f32 	%f1154, 0fFF800000, 0f7F800000, %p2;

$L__BB0_63:
	setp.eq.f32 	%p75, %f1147, 0f3F800000;
	selp.f32 	%f164, 0f3F800000, %f1154, %p75;
	abs.f32 	%f165, %f1148;
	setp.lt.f32 	%p76, %f165, 0f00800000;
	mul.f32 	%f588, %f165, 0f4B800000;
	selp.f32 	%f589, %f588, %f165, %p76;
	selp.f32 	%f590, 0fC3170000, 0fC2FE0000, %p76;
	mov.b32 	%r238, %f589;
	and.b32  	%r239, %r238, 8388607;
	or.b32  	%r240, %r239, 1065353216;
	mov.b32 	%f591, %r240;
	shr.u32 	%r241, %r238, 23;
	cvt.rn.f32.u32 	%f592, %r241;
	add.f32 	%f593, %f590, %f592;
	setp.gt.f32 	%p77, %f591, 0f3FB504F3;
	mul.f32 	%f594, %f591, 0f3F000000;
	add.f32 	%f595, %f593, 0f3F800000;
	selp.f32 	%f596, %f595, %f593, %p77;
	selp.f32 	%f597, %f594, %f591, %p77;
	add.f32 	%f598, %f597, 0fBF800000;
	add.f32 	%f599, %f597, 0f3F800000;
	rcp.approx.ftz.f32 	%f600, %f599;
	add.f32 	%f601, %f598, %f598;
	mul.f32 	%f602, %f601, %f600;
	mul.f32 	%f603, %f602, %f602;
	mov.f32 	%f604, 0f3C4CAF63;
	mov.f32 	%f605, 0f3B18F0FE;
	fma.rn.f32 	%f606, %f605, %f603, %f604;
	mov.f32 	%f607, 0f3DAAAABD;
	fma.rn.f32 	%f608, %f606, %f603, %f607;
	mul.rn.f32 	%f609, %f608, %f603;
	mul.rn.f32 	%f610, %f609, %f602;
	sub.f32 	%f611, %f598, %f602;
	add.f32 	%f612, %f611, %f611;
	neg.f32 	%f613, %f602;
	fma.rn.f32 	%f614, %f613, %f598, %f612;
	mul.rn.f32 	%f615, %f600, %f614;
	add.f32 	%f616, %f610, %f602;
	sub.f32 	%f617, %f602, %f616;
	add.f32 	%f618, %f610, %f617;
	add.f32 	%f619, %f615, %f618;
	add.f32 	%f620, %f616, %f619;
	sub.f32 	%f621, %f616, %f620;
	add.f32 	%f622, %f619, %f621;
	mov.f32 	%f623, 0f3F317200;
	mul.rn.f32 	%f624, %f596, %f623;
	mov.f32 	%f625, 0f35BFBE8E;
	mul.rn.f32 	%f626, %f596, %f625;
	add.f32 	%f627, %f624, %f620;
	sub.f32 	%f628, %f624, %f627;
	add.f32 	%f629, %f620, %f628;
	add.f32 	%f630, %f622, %f629;
	add.f32 	%f631, %f626, %f630;
	add.f32 	%f632, %f627, %f631;
	sub.f32 	%f633, %f627, %f632;
	add.f32 	%f634, %f631, %f633;
	mov.f32 	%f635, 0f3EE66666;
	mul.rn.f32 	%f636, %f635, %f632;
	neg.f32 	%f637, %f636;
	fma.rn.f32 	%f638, %f635, %f632, %f637;
	fma.rn.f32 	%f639, %f635, %f634, %f638;
	mov.f32 	%f640, 0f00000000;
	fma.rn.f32 	%f641, %f640, %f632, %f639;
	add.rn.f32 	%f642, %f636, %f641;
	neg.f32 	%f643, %f642;
	add.rn.f32 	%f644, %f636, %f643;
	add.rn.f32 	%f645, %f644, %f641;
	mov.b32 	%r242, %f642;
	setp.eq.s32 	%p78, %r242, 1118925336;
	add.s32 	%r243, %r242, -1;
	mov.b32 	%f646, %r243;
	add.f32 	%f647, %f645, 0f37000000;
	selp.f32 	%f166, %f647, %f645, %p78;
	selp.f32 	%f648, %f646, %f642, %p78;
	mov.f32 	%f649, 0f3FB8AA3B;
	mul.rn.f32 	%f650, %f648, %f649;
	cvt.rzi.f32.f32 	%f651, %f650;
	abs.f32 	%f652, %f651;
	setp.gt.f32 	%p79, %f652, 0f42FC0000;
	mov.b32 	%r244, %f651;
	and.b32  	%r245, %r244, -2147483648;
	or.b32  	%r246, %r245, 1123811328;
	mov.b32 	%f653, %r246;
	selp.f32 	%f654, %f653, %f651, %p79;
	mov.f32 	%f655, 0fBF317218;
	fma.rn.f32 	%f656, %f654, %f655, %f648;
	mov.f32 	%f657, 0f3102E308;
	fma.rn.f32 	%f658, %f654, %f657, %f656;
	mul.f32 	%f659, %f658, 0f3FB8AA3B;
	add.f32 	%f660, %f654, 0f4B40007F;
	mov.b32 	%r247, %f660;
	shl.b32 	%r248, %r247, 23;
	mov.b32 	%f661, %r248;
	ex2.approx.ftz.f32 	%f662, %f659;
	mul.f32 	%f167, %f662, %f661;
	setp.eq.f32 	%p80, %f167, 0f7F800000;
	mov.f32 	%f1155, 0f7F800000;
	@%p80 bra 	$L__BB0_65;

	fma.rn.f32 	%f1155, %f167, %f166, %f167;

$L__BB0_65:
	setp.lt.f32 	%p81, %f1148, 0f00000000;
	and.pred  	%p3, %p81, %p52;
	setp.eq.f32 	%p83, %f1148, 0f00000000;
	@%p83 bra 	$L__BB0_69;
	bra.uni 	$L__BB0_66;

$L__BB0_69:
	add.f32 	%f667, %f1148, %f1148;
	selp.f32 	%f1157, %f667, 0f00000000, %p52;
	bra.uni 	$L__BB0_70;

$L__BB0_66:
	mov.b32 	%r249, %f1155;
	xor.b32  	%r250, %r249, -2147483648;
	mov.b32 	%f663, %r250;
	selp.f32 	%f1157, %f663, %f1155, %p3;
	setp.geu.f32 	%p84, %f1148, 0f00000000;
	@%p84 bra 	$L__BB0_70;

	mov.f32 	%f664, 0f3EE66666;
	cvt.rzi.f32.f32 	%f665, %f664;
	setp.eq.f32 	%p85, %f665, 0f3EE66666;
	@%p85 bra 	$L__BB0_70;

	mov.f32 	%f1157, 0f7FFFFFFF;

$L__BB0_70:
	abs.f32 	%f1083, %f1148;
	add.f32 	%f668, %f1083, 0f3EE66666;
	mov.b32 	%r251, %f668;
	setp.lt.s32 	%p87, %r251, 2139095040;
	@%p87 bra 	$L__BB0_75;

	abs.f32 	%f1084, %f1148;
	setp.gtu.f32 	%p88, %f1084, 0f7F800000;
	@%p88 bra 	$L__BB0_74;
	bra.uni 	$L__BB0_72;

$L__BB0_74:
	add.f32 	%f1157, %f1148, 0f3EE66666;
	bra.uni 	$L__BB0_75;

$L__BB0_72:
	abs.f32 	%f1085, %f1148;
	setp.neu.f32 	%p89, %f1085, 0f7F800000;
	@%p89 bra 	$L__BB0_75;

	selp.f32 	%f1157, 0fFF800000, 0f7F800000, %p3;

$L__BB0_75:
	setp.eq.f32 	%p90, %f1148, 0f3F800000;
	mov.f32 	%f670, 0f3F800000;
	selp.f32 	%f671, 0f3F800000, %f1157, %p90;
	min.f32 	%f672, %f152, %f670;
	mov.f32 	%f673, 0f00000000;
	max.f32 	%f176, %f673, %f672;
	min.f32 	%f674, %f164, %f670;
	max.f32 	%f177, %f673, %f674;
	min.f32 	%f675, %f671, %f670;
	max.f32 	%f178, %f673, %f675;
	mov.f32 	%f679, 0f3ED55555;
	abs.f32 	%f180, %f176;
	setp.lt.f32 	%p91, %f180, 0f00800000;
	mul.f32 	%f681, %f180, 0f4B800000;
	selp.f32 	%f682, %f681, %f180, %p91;
	selp.f32 	%f683, 0fC3170000, 0fC2FE0000, %p91;
	mov.b32 	%r254, %f682;
	and.b32  	%r255, %r254, 8388607;
	or.b32  	%r256, %r255, 1065353216;
	mov.b32 	%f684, %r256;
	shr.u32 	%r257, %r254, 23;
	cvt.rn.f32.u32 	%f685, %r257;
	add.f32 	%f686, %f683, %f685;
	setp.gt.f32 	%p92, %f684, 0f3FB504F3;
	mul.f32 	%f687, %f684, 0f3F000000;
	add.f32 	%f688, %f686, 0f3F800000;
	selp.f32 	%f689, %f688, %f686, %p92;
	selp.f32 	%f690, %f687, %f684, %p92;
	add.f32 	%f691, %f690, 0fBF800000;
	add.f32 	%f692, %f690, 0f3F800000;
	rcp.approx.ftz.f32 	%f693, %f692;
	add.f32 	%f694, %f691, %f691;
	mul.f32 	%f695, %f694, %f693;
	mul.f32 	%f696, %f695, %f695;
	mov.f32 	%f697, 0f3C4CAF63;
	mov.f32 	%f698, 0f3B18F0FE;
	fma.rn.f32 	%f699, %f698, %f696, %f697;
	mov.f32 	%f700, 0f3DAAAABD;
	fma.rn.f32 	%f701, %f699, %f696, %f700;
	mul.rn.f32 	%f702, %f701, %f696;
	mul.rn.f32 	%f703, %f702, %f695;
	sub.f32 	%f704, %f691, %f695;
	add.f32 	%f705, %f704, %f704;
	neg.f32 	%f706, %f695;
	fma.rn.f32 	%f707, %f706, %f691, %f705;
	mul.rn.f32 	%f708, %f693, %f707;
	add.f32 	%f709, %f703, %f695;
	sub.f32 	%f710, %f695, %f709;
	add.f32 	%f711, %f703, %f710;
	add.f32 	%f712, %f708, %f711;
	add.f32 	%f713, %f709, %f712;
	sub.f32 	%f714, %f709, %f713;
	add.f32 	%f715, %f712, %f714;
	mov.f32 	%f716, 0f3F317200;
	mul.rn.f32 	%f717, %f689, %f716;
	mov.f32 	%f718, 0f35BFBE8E;
	mul.rn.f32 	%f719, %f689, %f718;
	add.f32 	%f720, %f717, %f713;
	sub.f32 	%f721, %f717, %f720;
	add.f32 	%f722, %f713, %f721;
	add.f32 	%f723, %f715, %f722;
	add.f32 	%f724, %f719, %f723;
	add.f32 	%f725, %f720, %f724;
	sub.f32 	%f726, %f720, %f725;
	add.f32 	%f727, %f724, %f726;
	mul.rn.f32 	%f728, %f679, %f725;
	neg.f32 	%f729, %f728;
	fma.rn.f32 	%f730, %f679, %f725, %f729;
	fma.rn.f32 	%f731, %f679, %f727, %f730;
	fma.rn.f32 	%f732, %f673, %f725, %f731;
	add.rn.f32 	%f733, %f728, %f732;
	neg.f32 	%f734, %f733;
	add.rn.f32 	%f735, %f728, %f734;
	add.rn.f32 	%f736, %f735, %f732;
	mov.b32 	%r258, %f733;
	setp.eq.s32 	%p93, %r258, 1118925336;
	add.s32 	%r259, %r258, -1;
	mov.b32 	%f737, %r259;
	add.f32 	%f738, %f736, 0f37000000;
	selp.f32 	%f181, %f738, %f736, %p93;
	selp.f32 	%f739, %f737, %f733, %p93;
	mov.f32 	%f740, 0f3FB8AA3B;
	mul.rn.f32 	%f741, %f739, %f740;
	cvt.rzi.f32.f32 	%f742, %f741;
	abs.f32 	%f743, %f742;
	setp.gt.f32 	%p94, %f743, 0f42FC0000;
	mov.b32 	%r260, %f742;
	and.b32  	%r261, %r260, -2147483648;
	or.b32  	%r262, %r261, 1123811328;
	mov.b32 	%f744, %r262;
	selp.f32 	%f745, %f744, %f742, %p94;
	mov.f32 	%f746, 0fBF317218;
	fma.rn.f32 	%f747, %f745, %f746, %f739;
	mov.f32 	%f748, 0f3102E308;
	fma.rn.f32 	%f749, %f745, %f748, %f747;
	mul.f32 	%f750, %f749, 0f3FB8AA3B;
	add.f32 	%f751, %f745, 0f4B40007F;
	mov.b32 	%r263, %f751;
	shl.b32 	%r264, %r263, 23;
	mov.b32 	%f752, %r264;
	ex2.approx.ftz.f32 	%f753, %f750;
	mul.f32 	%f182, %f753, %f752;
	setp.eq.f32 	%p95, %f182, 0f7F800000;
	mov.f32 	%f1158, 0f7F800000;
	@%p95 bra 	$L__BB0_77;

	fma.rn.f32 	%f1158, %f182, %f181, %f182;

$L__BB0_77:
	mov.f32 	%f1091, 0f3E555555;
	cvt.rzi.f32.f32 	%f1090, %f1091;
	add.f32 	%f1089, %f1090, %f1090;
	mov.f32 	%f1088, 0f3ED55555;
	sub.f32 	%f1087, %f1088, %f1089;
	abs.f32 	%f1086, %f1087;
	setp.lt.f32 	%p96, %f176, 0f00000000;
	setp.eq.f32 	%p97, %f1086, 0f3F800000;
	and.pred  	%p4, %p96, %p97;
	setp.eq.f32 	%p98, %f176, 0f00000000;
	@%p98 bra 	$L__BB0_81;
	bra.uni 	$L__BB0_78;

$L__BB0_81:
	add.f32 	%f758, %f176, %f176;
	selp.f32 	%f1160, %f758, 0f00000000, %p97;
	bra.uni 	$L__BB0_82;

$L__BB0_78:
	mov.b32 	%r265, %f1158;
	xor.b32  	%r266, %r265, -2147483648;
	mov.b32 	%f754, %r266;
	selp.f32 	%f1160, %f754, %f1158, %p4;
	setp.geu.f32 	%p99, %f176, 0f00000000;
	@%p99 bra 	$L__BB0_82;

	mov.f32 	%f755, 0f3ED55555;
	cvt.rzi.f32.f32 	%f756, %f755;
	setp.eq.f32 	%p100, %f756, 0f3ED55555;
	@%p100 bra 	$L__BB0_82;

	mov.f32 	%f1160, 0f7FFFFFFF;

$L__BB0_82:
	add.f32 	%f759, %f180, 0f3ED55555;
	mov.b32 	%r267, %f759;
	setp.lt.s32 	%p102, %r267, 2139095040;
	@%p102 bra 	$L__BB0_87;

	setp.gtu.f32 	%p103, %f180, 0f7F800000;
	@%p103 bra 	$L__BB0_86;
	bra.uni 	$L__BB0_84;

$L__BB0_86:
	add.f32 	%f1160, %f176, 0f3ED55555;
	bra.uni 	$L__BB0_87;

$L__BB0_84:
	setp.neu.f32 	%p104, %f180, 0f7F800000;
	@%p104 bra 	$L__BB0_87;

	selp.f32 	%f1160, 0fFF800000, 0f7F800000, %p4;

$L__BB0_87:
	abs.f32 	%f191, %f177;
	setp.lt.f32 	%p105, %f191, 0f00800000;
	mul.f32 	%f761, %f191, 0f4B800000;
	selp.f32 	%f762, %f761, %f191, %p105;
	selp.f32 	%f763, 0fC3170000, 0fC2FE0000, %p105;
	mov.b32 	%r268, %f762;
	and.b32  	%r269, %r268, 8388607;
	or.b32  	%r270, %r269, 1065353216;
	mov.b32 	%f764, %r270;
	shr.u32 	%r271, %r268, 23;
	cvt.rn.f32.u32 	%f765, %r271;
	add.f32 	%f766, %f763, %f765;
	setp.gt.f32 	%p106, %f764, 0f3FB504F3;
	mul.f32 	%f767, %f764, 0f3F000000;
	add.f32 	%f768, %f766, 0f3F800000;
	selp.f32 	%f769, %f768, %f766, %p106;
	selp.f32 	%f770, %f767, %f764, %p106;
	add.f32 	%f771, %f770, 0fBF800000;
	add.f32 	%f772, %f770, 0f3F800000;
	rcp.approx.ftz.f32 	%f773, %f772;
	add.f32 	%f774, %f771, %f771;
	mul.f32 	%f775, %f774, %f773;
	mul.f32 	%f776, %f775, %f775;
	mov.f32 	%f777, 0f3C4CAF63;
	mov.f32 	%f778, 0f3B18F0FE;
	fma.rn.f32 	%f779, %f778, %f776, %f777;
	mov.f32 	%f780, 0f3DAAAABD;
	fma.rn.f32 	%f781, %f779, %f776, %f780;
	mul.rn.f32 	%f782, %f781, %f776;
	mul.rn.f32 	%f783, %f782, %f775;
	sub.f32 	%f784, %f771, %f775;
	add.f32 	%f785, %f784, %f784;
	neg.f32 	%f786, %f775;
	fma.rn.f32 	%f787, %f786, %f771, %f785;
	mul.rn.f32 	%f788, %f773, %f787;
	add.f32 	%f789, %f783, %f775;
	sub.f32 	%f790, %f775, %f789;
	add.f32 	%f791, %f783, %f790;
	add.f32 	%f792, %f788, %f791;
	add.f32 	%f793, %f789, %f792;
	sub.f32 	%f794, %f789, %f793;
	add.f32 	%f795, %f792, %f794;
	mov.f32 	%f796, 0f3F317200;
	mul.rn.f32 	%f797, %f769, %f796;
	mov.f32 	%f798, 0f35BFBE8E;
	mul.rn.f32 	%f799, %f769, %f798;
	add.f32 	%f800, %f797, %f793;
	sub.f32 	%f801, %f797, %f800;
	add.f32 	%f802, %f793, %f801;
	add.f32 	%f803, %f795, %f802;
	add.f32 	%f804, %f799, %f803;
	add.f32 	%f805, %f800, %f804;
	sub.f32 	%f806, %f800, %f805;
	add.f32 	%f807, %f804, %f806;
	mov.f32 	%f808, 0f3ED55555;
	mul.rn.f32 	%f809, %f808, %f805;
	neg.f32 	%f810, %f809;
	fma.rn.f32 	%f811, %f808, %f805, %f810;
	fma.rn.f32 	%f812, %f808, %f807, %f811;
	mov.f32 	%f813, 0f00000000;
	fma.rn.f32 	%f814, %f813, %f805, %f812;
	add.rn.f32 	%f815, %f809, %f814;
	neg.f32 	%f816, %f815;
	add.rn.f32 	%f817, %f809, %f816;
	add.rn.f32 	%f818, %f817, %f814;
	mov.b32 	%r272, %f815;
	setp.eq.s32 	%p107, %r272, 1118925336;
	add.s32 	%r273, %r272, -1;
	mov.b32 	%f819, %r273;
	add.f32 	%f820, %f818, 0f37000000;
	selp.f32 	%f192, %f820, %f818, %p107;
	selp.f32 	%f821, %f819, %f815, %p107;
	mov.f32 	%f822, 0f3FB8AA3B;
	mul.rn.f32 	%f823, %f821, %f822;
	cvt.rzi.f32.f32 	%f824, %f823;
	abs.f32 	%f825, %f824;
	setp.gt.f32 	%p108, %f825, 0f42FC0000;
	mov.b32 	%r274, %f824;
	and.b32  	%r275, %r274, -2147483648;
	or.b32  	%r276, %r275, 1123811328;
	mov.b32 	%f826, %r276;
	selp.f32 	%f827, %f826, %f824, %p108;
	mov.f32 	%f828, 0fBF317218;
	fma.rn.f32 	%f829, %f827, %f828, %f821;
	mov.f32 	%f830, 0f3102E308;
	fma.rn.f32 	%f831, %f827, %f830, %f829;
	mul.f32 	%f832, %f831, 0f3FB8AA3B;
	add.f32 	%f833, %f827, 0f4B40007F;
	mov.b32 	%r277, %f833;
	shl.b32 	%r278, %r277, 23;
	mov.b32 	%f834, %r278;
	ex2.approx.ftz.f32 	%f835, %f832;
	mul.f32 	%f193, %f835, %f834;
	setp.eq.f32 	%p109, %f193, 0f7F800000;
	mov.f32 	%f1161, 0f7F800000;
	@%p109 bra 	$L__BB0_89;

	fma.rn.f32 	%f1161, %f193, %f192, %f193;

$L__BB0_89:
	setp.lt.f32 	%p110, %f177, 0f00000000;
	and.pred  	%p5, %p110, %p97;
	setp.eq.f32 	%p112, %f177, 0f00000000;
	@%p112 bra 	$L__BB0_93;
	bra.uni 	$L__BB0_90;

$L__BB0_93:
	add.f32 	%f840, %f177, %f177;
	selp.f32 	%f1163, %f840, 0f00000000, %p97;
	bra.uni 	$L__BB0_94;

$L__BB0_90:
	mov.b32 	%r279, %f1161;
	xor.b32  	%r280, %r279, -2147483648;
	mov.b32 	%f836, %r280;
	selp.f32 	%f1163, %f836, %f1161, %p5;
	setp.geu.f32 	%p113, %f177, 0f00000000;
	@%p113 bra 	$L__BB0_94;

	mov.f32 	%f837, 0f3ED55555;
	cvt.rzi.f32.f32 	%f838, %f837;
	setp.eq.f32 	%p114, %f838, 0f3ED55555;
	@%p114 bra 	$L__BB0_94;

	mov.f32 	%f1163, 0f7FFFFFFF;

$L__BB0_94:
	add.f32 	%f841, %f191, 0f3ED55555;
	mov.b32 	%r281, %f841;
	setp.lt.s32 	%p116, %r281, 2139095040;
	@%p116 bra 	$L__BB0_99;

	setp.gtu.f32 	%p117, %f191, 0f7F800000;
	@%p117 bra 	$L__BB0_98;
	bra.uni 	$L__BB0_96;

$L__BB0_98:
	add.f32 	%f1163, %f177, 0f3ED55555;
	bra.uni 	$L__BB0_99;

$L__BB0_96:
	setp.neu.f32 	%p118, %f191, 0f7F800000;
	@%p118 bra 	$L__BB0_99;

	selp.f32 	%f1163, 0fFF800000, 0f7F800000, %p5;

$L__BB0_99:
	abs.f32 	%f202, %f178;
	setp.lt.f32 	%p119, %f202, 0f00800000;
	mul.f32 	%f843, %f202, 0f4B800000;
	selp.f32 	%f844, %f843, %f202, %p119;
	selp.f32 	%f845, 0fC3170000, 0fC2FE0000, %p119;
	mov.b32 	%r282, %f844;
	and.b32  	%r283, %r282, 8388607;
	or.b32  	%r284, %r283, 1065353216;
	mov.b32 	%f846, %r284;
	shr.u32 	%r285, %r282, 23;
	cvt.rn.f32.u32 	%f847, %r285;
	add.f32 	%f848, %f845, %f847;
	setp.gt.f32 	%p120, %f846, 0f3FB504F3;
	mul.f32 	%f849, %f846, 0f3F000000;
	add.f32 	%f850, %f848, 0f3F800000;
	selp.f32 	%f851, %f850, %f848, %p120;
	selp.f32 	%f852, %f849, %f846, %p120;
	add.f32 	%f853, %f852, 0fBF800000;
	add.f32 	%f854, %f852, 0f3F800000;
	rcp.approx.ftz.f32 	%f855, %f854;
	add.f32 	%f856, %f853, %f853;
	mul.f32 	%f857, %f856, %f855;
	mul.f32 	%f858, %f857, %f857;
	mov.f32 	%f859, 0f3C4CAF63;
	mov.f32 	%f860, 0f3B18F0FE;
	fma.rn.f32 	%f861, %f860, %f858, %f859;
	mov.f32 	%f862, 0f3DAAAABD;
	fma.rn.f32 	%f863, %f861, %f858, %f862;
	mul.rn.f32 	%f864, %f863, %f858;
	mul.rn.f32 	%f865, %f864, %f857;
	sub.f32 	%f866, %f853, %f857;
	add.f32 	%f867, %f866, %f866;
	neg.f32 	%f868, %f857;
	fma.rn.f32 	%f869, %f868, %f853, %f867;
	mul.rn.f32 	%f870, %f855, %f869;
	add.f32 	%f871, %f865, %f857;
	sub.f32 	%f872, %f857, %f871;
	add.f32 	%f873, %f865, %f872;
	add.f32 	%f874, %f870, %f873;
	add.f32 	%f875, %f871, %f874;
	sub.f32 	%f876, %f871, %f875;
	add.f32 	%f877, %f874, %f876;
	mov.f32 	%f878, 0f3F317200;
	mul.rn.f32 	%f879, %f851, %f878;
	mov.f32 	%f880, 0f35BFBE8E;
	mul.rn.f32 	%f881, %f851, %f880;
	add.f32 	%f882, %f879, %f875;
	sub.f32 	%f883, %f879, %f882;
	add.f32 	%f884, %f875, %f883;
	add.f32 	%f885, %f877, %f884;
	add.f32 	%f886, %f881, %f885;
	add.f32 	%f887, %f882, %f886;
	sub.f32 	%f888, %f882, %f887;
	add.f32 	%f889, %f886, %f888;
	mov.f32 	%f890, 0f3ED55555;
	mul.rn.f32 	%f891, %f890, %f887;
	neg.f32 	%f892, %f891;
	fma.rn.f32 	%f893, %f890, %f887, %f892;
	fma.rn.f32 	%f894, %f890, %f889, %f893;
	mov.f32 	%f895, 0f00000000;
	fma.rn.f32 	%f896, %f895, %f887, %f894;
	add.rn.f32 	%f897, %f891, %f896;
	neg.f32 	%f898, %f897;
	add.rn.f32 	%f899, %f891, %f898;
	add.rn.f32 	%f900, %f899, %f896;
	mov.b32 	%r286, %f897;
	setp.eq.s32 	%p121, %r286, 1118925336;
	add.s32 	%r287, %r286, -1;
	mov.b32 	%f901, %r287;
	add.f32 	%f902, %f900, 0f37000000;
	selp.f32 	%f203, %f902, %f900, %p121;
	selp.f32 	%f903, %f901, %f897, %p121;
	mov.f32 	%f904, 0f3FB8AA3B;
	mul.rn.f32 	%f905, %f903, %f904;
	cvt.rzi.f32.f32 	%f906, %f905;
	abs.f32 	%f907, %f906;
	setp.gt.f32 	%p122, %f907, 0f42FC0000;
	mov.b32 	%r288, %f906;
	and.b32  	%r289, %r288, -2147483648;
	or.b32  	%r290, %r289, 1123811328;
	mov.b32 	%f908, %r290;
	selp.f32 	%f909, %f908, %f906, %p122;
	mov.f32 	%f910, 0fBF317218;
	fma.rn.f32 	%f911, %f909, %f910, %f903;
	mov.f32 	%f912, 0f3102E308;
	fma.rn.f32 	%f913, %f909, %f912, %f911;
	mul.f32 	%f914, %f913, 0f3FB8AA3B;
	add.f32 	%f915, %f909, 0f4B40007F;
	mov.b32 	%r291, %f915;
	shl.b32 	%r292, %r291, 23;
	mov.b32 	%f916, %r292;
	ex2.approx.ftz.f32 	%f917, %f914;
	mul.f32 	%f204, %f917, %f916;
	setp.eq.f32 	%p123, %f204, 0f7F800000;
	mov.f32 	%f1164, 0f7F800000;
	@%p123 bra 	$L__BB0_101;

	fma.rn.f32 	%f1164, %f204, %f203, %f204;

$L__BB0_101:
	setp.lt.f32 	%p124, %f178, 0f00000000;
	and.pred  	%p6, %p124, %p97;
	setp.eq.f32 	%p126, %f178, 0f00000000;
	@%p126 bra 	$L__BB0_105;
	bra.uni 	$L__BB0_102;

$L__BB0_105:
	add.f32 	%f922, %f178, %f178;
	selp.f32 	%f1166, %f922, 0f00000000, %p97;
	bra.uni 	$L__BB0_106;

$L__BB0_102:
	mov.b32 	%r293, %f1164;
	xor.b32  	%r294, %r293, -2147483648;
	mov.b32 	%f918, %r294;
	selp.f32 	%f1166, %f918, %f1164, %p6;
	setp.geu.f32 	%p127, %f178, 0f00000000;
	@%p127 bra 	$L__BB0_106;

	mov.f32 	%f919, 0f3ED55555;
	cvt.rzi.f32.f32 	%f920, %f919;
	setp.eq.f32 	%p128, %f920, 0f3ED55555;
	@%p128 bra 	$L__BB0_106;

	mov.f32 	%f1166, 0f7FFFFFFF;

$L__BB0_106:
	add.f32 	%f923, %f202, 0f3ED55555;
	mov.b32 	%r295, %f923;
	setp.lt.s32 	%p130, %r295, 2139095040;
	@%p130 bra 	$L__BB0_111;

	setp.gtu.f32 	%p131, %f202, 0f7F800000;
	@%p131 bra 	$L__BB0_110;
	bra.uni 	$L__BB0_108;

$L__BB0_110:
	add.f32 	%f1166, %f178, 0f3ED55555;
	bra.uni 	$L__BB0_111;

$L__BB0_108:
	setp.neu.f32 	%p132, %f202, 0f7F800000;
	@%p132 bra 	$L__BB0_111;

	selp.f32 	%f1166, 0fFF800000, 0f7F800000, %p6;

$L__BB0_111:
	ld.const.u64 	%rd116, [params+144];
	cvta.to.global.u64 	%rd115, %rd116;
	ld.const.u32 	%r352, [params+136];
	mad.lo.s32 	%r351, %r352, %r6, %r5;
	cvt.u64.u32 	%rd114, %r351;
	fma.rn.f32 	%f924, %f1160, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p133, %f176, 0f3F800000;
	mov.f32 	%f925, 0f3F800000;
	selp.f32 	%f926, 0f3F7FFFFF, %f924, %p133;
	mul.f32 	%f927, %f176, 0f414EB852;
	setp.lt.f32 	%p134, %f176, 0f3B4D2E1C;
	selp.f32 	%f928, %f927, %f926, %p134;
	fma.rn.f32 	%f929, %f1163, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p135, %f177, 0f3F800000;
	selp.f32 	%f930, 0f3F7FFFFF, %f929, %p135;
	mul.f32 	%f931, %f177, 0f414EB852;
	setp.lt.f32 	%p136, %f177, 0f3B4D2E1C;
	selp.f32 	%f932, %f931, %f930, %p136;
	fma.rn.f32 	%f933, %f1166, 0f3F870A3D, 0fBD6147AE;
	setp.eq.f32 	%p137, %f178, 0f3F800000;
	selp.f32 	%f934, 0f3F7FFFFF, %f933, %p137;
	mul.f32 	%f935, %f178, 0f414EB852;
	setp.lt.f32 	%p138, %f178, 0f3B4D2E1C;
	selp.f32 	%f936, %f935, %f934, %p138;
	min.f32 	%f937, %f928, %f925;
	mov.f32 	%f938, 0f00000000;
	max.f32 	%f939, %f938, %f937;
	mul.f32 	%f940, %f939, 0f43800000;
	cvt.rzi.u32.f32 	%r296, %f940;
	min.u32 	%r297, %r296, 255;
	min.f32 	%f941, %f932, %f925;
	max.f32 	%f942, %f938, %f941;
	mul.f32 	%f943, %f942, 0f43800000;
	cvt.rzi.u32.f32 	%r298, %f943;
	min.u32 	%r299, %r298, 255;
	min.f32 	%f944, %f936, %f925;
	max.f32 	%f945, %f938, %f944;
	mul.f32 	%f946, %f945, 0f43800000;
	cvt.rzi.u32.f32 	%r300, %f946;
	min.u32 	%r301, %r300, 255;
	shl.b64 	%rd68, %rd114, 2;
	add.s64 	%rd69, %rd115, %rd68;
	cvt.u16.u32 	%rs23, %r301;
	cvt.u16.u32 	%rs24, %r299;
	cvt.u16.u32 	%rs25, %r297;
	mov.u16 	%rs26, 255;
	st.global.v4.u8 	[%rd69], {%rs25, %rs24, %rs23, %rs26};

$L__BB0_112:
	ld.const.u32 	%r349, [params+104];
	and.b32  	%r302, %r349, 4;
	setp.eq.s32 	%p139, %r302, 0;
	@%p139 bra 	$L__BB0_114;

	ld.const.u64 	%rd70, [params+224];
	cvta.to.global.u64 	%rd71, %rd70;
	ld.const.u32 	%r303, [params+216];
	mad.lo.s32 	%r304, %r303, %r6, %r5;
	mov.f32 	%f950, 0f3F800000;
	mul.wide.u32 	%rd72, %r304, 8;
	add.s64 	%rd73, %rd71, %rd72;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f950;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs29, %f1148;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f1147;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs27, %f1146;}

	// end inline asm
	st.global.v4.u16 	[%rd73], {%rs27, %rs28, %rs29, %rs30};

$L__BB0_114:
	ld.const.u32 	%r350, [params+104];
	and.b32  	%r305, %r350, 16;
	setp.eq.s32 	%p140, %r305, 0;
	@%p140 bra 	$L__BB0_116;

	ld.const.u64 	%rd74, [params+240];
	cvta.to.global.u64 	%rd75, %rd74;
	ld.const.u32 	%r306, [params+232];
	mad.lo.s32 	%r307, %r306, %r6, %r5;
	mov.f32 	%f954, 0f3F800000;
	mul.wide.u32 	%rd76, %r307, 8;
	add.s64 	%rd77, %rd75, %rd76;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f954;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs33, %f127;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f126;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs31, %f125;}

	// end inline asm
	st.global.v4.u16 	[%rd77], {%rs31, %rs32, %rs33, %rs34};

$L__BB0_116:
	mul.f32 	%f213, %f113, 0f3F000000;
	mul.f32 	%f214, %f114, 0f3F000000;
	mul.f32 	%f215, %f115, 0f3F000000;
	ld.const.u32 	%r50, [params+108];
	setp.eq.s32 	%p141, %r50, 0;
	ld.const.u64 	%rd78, [params+256];
	cvta.to.global.u64 	%rd79, %rd78;
	ld.const.u32 	%r308, [params+248];
	mad.lo.s32 	%r309, %r308, %r6, %r5;
	mul.wide.u32 	%rd80, %r309, 8;
	add.s64 	%rd18, %rd79, %rd80;
	@%p141 bra 	$L__BB0_118;

	ld.global.v4.u16 	{%rs42, %rs43, %rs44, %rs45}, [%rd18];
	// begin inline asm
	{  cvt.f32.f16 %f955, %rs42;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f956, %rs43;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f957, %rs44;}

	// end inline asm
	add.f32 	%f958, %f213, %f955;
	add.f32 	%f959, %f214, %f956;
	add.f32 	%f960, %f215, %f957;
	mov.f32 	%f961, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs40, %f960;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs39, %f959;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs38, %f958;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs41, %f961;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs38, %rs39, %rs40, %rs41};
	bra.uni 	$L__BB0_119;

$L__BB0_118:
	mov.f32 	%f965, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs49, %f965;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs48, %f215;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs47, %f214;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs46, %f213;}

	// end inline asm
	st.global.v4.u16 	[%rd18], {%rs46, %rs47, %rs48, %rs49};

$L__BB0_119:
	mov.f32 	%f966, 0f34000000;
	max.f32 	%f967, %f213, %f966;
	mul.f32 	%f968, %f116, 0f3F000000;
	div.rn.f32 	%f969, %f968, %f967;
	max.f32 	%f970, %f214, %f966;
	mul.f32 	%f971, %f117, 0f3F000000;
	div.rn.f32 	%f972, %f971, %f970;
	max.f32 	%f973, %f215, %f966;
	mul.f32 	%f974, %f118, 0f3F000000;
	div.rn.f32 	%f975, %f974, %f973;
	fma.rn.f32 	%f216, %f969, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f217, %f972, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f218, %f975, 0f3F000000, 0f3F000000;
	mul.f32 	%f976, %f119, 0f3F000000;
	div.rn.f32 	%f977, %f976, %f967;
	mul.f32 	%f978, %f120, 0f3F000000;
	div.rn.f32 	%f979, %f978, %f970;
	mul.f32 	%f980, %f121, 0f3F000000;
	div.rn.f32 	%f981, %f980, %f973;
	fma.rn.f32 	%f219, %f977, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f220, %f979, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f221, %f981, 0f3F000000, 0f3F000000;
	mul.f32 	%f982, %f122, 0f3F000000;
	div.rn.f32 	%f983, %f982, %f967;
	mul.f32 	%f984, %f123, 0f3F000000;
	div.rn.f32 	%f985, %f984, %f970;
	mul.f32 	%f986, %f124, 0f3F000000;
	div.rn.f32 	%f987, %f986, %f973;
	fma.rn.f32 	%f222, %f983, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f223, %f985, 0f3F000000, 0f3F000000;
	fma.rn.f32 	%f224, %f987, 0f3F000000, 0f3F000000;
	ld.const.u64 	%rd81, [params+272];
	cvta.to.global.u64 	%rd82, %rd81;
	ld.const.u32 	%r310, [params+264];
	mad.lo.s32 	%r311, %r310, %r6, %r5;
	mul.wide.u32 	%rd83, %r311, 8;
	add.s64 	%rd19, %rd82, %rd83;
	@%p141 bra 	$L__BB0_121;

	ld.global.v4.u16 	{%rs57, %rs58, %rs59, %rs60}, [%rd19];
	// begin inline asm
	{  cvt.f32.f16 %f988, %rs57;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f989, %rs58;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f990, %rs59;}

	// end inline asm
	add.f32 	%f991, %f216, %f988;
	add.f32 	%f992, %f217, %f989;
	add.f32 	%f993, %f218, %f990;
	mov.f32 	%f994, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs55, %f993;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs54, %f992;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs53, %f991;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs56, %f994;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs53, %rs54, %rs55, %rs56};
	bra.uni 	$L__BB0_122;

$L__BB0_121:
	mov.f32 	%f998, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs64, %f998;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs63, %f218;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs62, %f217;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs61, %f216;}

	// end inline asm
	st.global.v4.u16 	[%rd19], {%rs61, %rs62, %rs63, %rs64};

$L__BB0_122:
	ld.const.u64 	%rd84, [params+288];
	cvta.to.global.u64 	%rd85, %rd84;
	ld.const.u32 	%r312, [params+280];
	mad.lo.s32 	%r313, %r312, %r6, %r5;
	mul.wide.u32 	%rd86, %r313, 8;
	add.s64 	%rd20, %rd85, %rd86;
	@%p141 bra 	$L__BB0_124;

	ld.global.v4.u16 	{%rs72, %rs73, %rs74, %rs75}, [%rd20];
	// begin inline asm
	{  cvt.f32.f16 %f999, %rs72;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1000, %rs73;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1001, %rs74;}

	// end inline asm
	add.f32 	%f1002, %f219, %f999;
	add.f32 	%f1003, %f220, %f1000;
	add.f32 	%f1004, %f221, %f1001;
	mov.f32 	%f1005, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs70, %f1004;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs69, %f1003;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs68, %f1002;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs71, %f1005;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs68, %rs69, %rs70, %rs71};
	bra.uni 	$L__BB0_125;

$L__BB0_124:
	mov.f32 	%f1009, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs79, %f1009;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs78, %f221;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs77, %f220;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs76, %f219;}

	// end inline asm
	st.global.v4.u16 	[%rd20], {%rs76, %rs77, %rs78, %rs79};

$L__BB0_125:
	ld.const.u64 	%rd87, [params+304];
	cvta.to.global.u64 	%rd88, %rd87;
	ld.const.u32 	%r314, [params+296];
	mad.lo.s32 	%r315, %r314, %r6, %r5;
	mul.wide.u32 	%rd89, %r315, 8;
	add.s64 	%rd21, %rd88, %rd89;
	@%p141 bra 	$L__BB0_127;

	ld.global.v4.u16 	{%rs87, %rs88, %rs89, %rs90}, [%rd21];
	// begin inline asm
	{  cvt.f32.f16 %f1010, %rs87;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1011, %rs88;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f1012, %rs89;}

	// end inline asm
	add.f32 	%f1013, %f222, %f1010;
	add.f32 	%f1014, %f223, %f1011;
	add.f32 	%f1015, %f224, %f1012;
	mov.f32 	%f1016, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs85, %f1015;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs84, %f1014;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs83, %f1013;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs86, %f1016;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs83, %rs84, %rs85, %rs86};
	bra.uni 	$L__BB0_146;

$L__BB0_127:
	mov.f32 	%f1020, 0f3F800000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs94, %f1020;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs93, %f224;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs92, %f223;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs91, %f222;}

	// end inline asm
	st.global.v4.u16 	[%rd21], {%rs91, %rs92, %rs93, %rs94};

$L__BB0_146:
	ret;

}