2675 lines
74 KiB
Plaintext
2675 lines
74 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<193>;
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.reg .b16 %rs<181>;
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.reg .f32 %f<1458>;
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.reg .b32 %r<375>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<115>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r53), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r54), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd29, [params+400];
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cvta.to.global.u64 %rd30, %rd29;
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ld.const.u32 %r59, [params+392];
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mad.lo.s32 %r60, %r59, %r54, %r53;
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mul.wide.u32 %rd31, %r60, 4;
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add.s64 %rd2, %rd30, %rd31;
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ld.global.v2.u8 {%rs16, %rs176}, [%rd2];
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or.b16 %rs18, %rs16, %rs176;
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and.b16 %rs19, %rs18, 255;
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setp.eq.s16 %p9, %rs19, 0;
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@%p9 bra $L__BB0_2;
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ld.global.u8 %rs175, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs175, [%rd2+2];
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setp.eq.s16 %p10, %rs175, 0;
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mov.f32 %f1404, 0f00000000;
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mov.u16 %rs176, 0;
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mov.f32 %f1405, %f1404;
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mov.f32 %f1406, %f1404;
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@%p10 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f220, %rs16;
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div.rn.f32 %f221, %f220, 0f437F0000;
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fma.rn.f32 %f222, %f221, 0f40000000, 0fBF800000;
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and.b16 %rs22, %rs176, 255;
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cvt.rn.f32.u16 %f223, %rs22;
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div.rn.f32 %f224, %f223, 0f437F0000;
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fma.rn.f32 %f225, %f224, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f226, %rs175;
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div.rn.f32 %f227, %f226, 0f437F0000;
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fma.rn.f32 %f228, %f227, 0f40000000, 0fBF800000;
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mul.f32 %f229, %f225, %f225;
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fma.rn.f32 %f230, %f222, %f222, %f229;
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fma.rn.f32 %f231, %f228, %f228, %f230;
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sqrt.rn.f32 %f232, %f231;
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rcp.rn.f32 %f233, %f232;
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mul.f32 %f1406, %f233, %f228;
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mul.f32 %f1405, %f233, %f225;
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mul.f32 %f1404, %f222, %f233;
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$L__BB0_4:
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ld.const.v2.u32 {%r61, %r62}, [params];
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add.s32 %r3, %r61, %r53;
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add.s32 %r4, %r62, %r54;
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setp.eq.f32 %p11, %f1404, 0f00000000;
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setp.eq.f32 %p12, %f1405, 0f00000000;
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and.pred %p13, %p11, %p12;
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setp.eq.f32 %p14, %f1406, 0f00000000;
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and.pred %p15, %p14, %p13;
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@%p15 bra $L__BB0_157;
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bra.uni $L__BB0_5;
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$L__BB0_157:
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ld.const.u32 %r50, [params+104];
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and.b32 %r344, %r50, 1;
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setp.eq.b32 %p183, %r344, 1;
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mov.pred %p184, 0;
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xor.pred %p185, %p183, %p184;
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not.pred %p186, %p185;
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@%p186 bra $L__BB0_159;
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ld.const.u64 %rd86, [params+144];
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cvta.to.global.u64 %rd87, %rd86;
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ld.const.u32 %r345, [params+136];
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mad.lo.s32 %r346, %r345, %r4, %r3;
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mul.wide.u32 %rd88, %r346, 4;
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add.s64 %rd89, %rd87, %rd88;
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mov.u16 %rs112, 0;
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st.global.v4.u8 [%rd89], {%rs112, %rs112, %rs112, %rs112};
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$L__BB0_159:
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and.b32 %r347, %r50, 8;
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setp.eq.s32 %p187, %r347, 0;
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@%p187 bra $L__BB0_161;
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ld.const.u64 %rd90, [params+192];
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cvta.to.global.u64 %rd91, %rd90;
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ld.const.u32 %r348, [params+184];
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mad.lo.s32 %r349, %r348, %r4, %r3;
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mov.f32 %f1298, 0f00000000;
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cvt.rzi.u32.f32 %r350, %f1298;
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mul.wide.u32 %rd92, %r349, 2;
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add.s64 %rd93, %rd91, %rd92;
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mov.u16 %rs113, 0;
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cvt.u16.u32 %rs114, %r350;
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st.global.v2.u8 [%rd93], {%rs114, %rs113};
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$L__BB0_161:
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and.b32 %r351, %r50, 4;
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setp.eq.s32 %p188, %r351, 0;
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ld.const.u32 %r374, [params+108];
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@%p188 bra $L__BB0_165;
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setp.eq.s32 %p189, %r374, 0;
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ld.const.u64 %rd94, [params+224];
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cvta.to.global.u64 %rd95, %rd94;
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ld.const.u32 %r352, [params+216];
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mad.lo.s32 %r353, %r352, %r4, %r3;
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mul.wide.u32 %rd96, %r353, 8;
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add.s64 %rd24, %rd95, %rd96;
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@%p189 bra $L__BB0_164;
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ld.global.v4.u16 {%rs121, %rs122, %rs123, %rs124}, [%rd24];
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// begin inline asm
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{ cvt.f32.f16 %f1299, %rs121;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1300, %rs122;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1301, %rs123;}
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// end inline asm
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add.f32 %f1302, %f1299, 0f00000000;
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add.f32 %f1303, %f1300, 0f00000000;
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add.f32 %f1304, %f1301, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs120, %f1304;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs119, %f1303;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs118, %f1302;}
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// end inline asm
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mov.u16 %rs125, 0;
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st.global.v4.u16 [%rd24], {%rs118, %rs119, %rs120, %rs125};
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bra.uni $L__BB0_165;
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$L__BB0_5:
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ld.const.v4.f32 {%f237, %f238, %f239, %f240}, [params+512];
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neg.f32 %f241, %f238;
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neg.f32 %f242, %f239;
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mul.f32 %f243, %f1404, %f237;
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mul.f32 %f244, %f1405, %f241;
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sub.f32 %f245, %f244, %f243;
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mul.f32 %f246, %f1406, %f239;
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sub.f32 %f13, %f245, %f246;
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ld.const.u64 %rd32, [params+432];
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cvta.to.global.u64 %rd33, %rd32;
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ld.const.u32 %r65, [params+424];
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mad.lo.s32 %r66, %r65, %r54, %r53;
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mul.wide.u32 %rd34, %r66, 12;
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add.s64 %rd35, %rd33, %rd34;
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ld.global.f32 %f247, [%rd35];
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mul.f32 %f248, %f247, 0f3456BF95;
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ld.global.f32 %f249, [%rd35+4];
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mul.f32 %f250, %f249, 0f3456BF95;
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ld.global.f32 %f251, [%rd35+8];
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mul.f32 %f252, %f251, 0f3456BF95;
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abs.f32 %f253, %f1404;
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div.rn.f32 %f254, %f248, %f253;
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abs.f32 %f255, %f1405;
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div.rn.f32 %f256, %f250, %f255;
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abs.f32 %f257, %f1406;
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div.rn.f32 %f258, %f252, %f257;
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abs.f32 %f259, %f254;
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abs.f32 %f260, %f256;
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abs.f32 %f261, %f258;
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mov.f32 %f262, 0f38D1B717;
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max.f32 %f263, %f259, %f262;
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max.f32 %f264, %f260, %f262;
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max.f32 %f265, %f261, %f262;
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fma.rn.f32 %f14, %f1404, %f263, %f247;
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fma.rn.f32 %f15, %f1405, %f264, %f249;
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fma.rn.f32 %f16, %f1406, %f265, %f251;
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abs.f32 %f266, %f237;
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abs.f32 %f267, %f239;
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setp.gt.f32 %p16, %f266, %f267;
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selp.f32 %f268, %f241, 0f00000000, %p16;
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mov.f32 %f1412, 0f00000000;
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selp.f32 %f269, %f237, %f242, %p16;
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selp.f32 %f270, 0f00000000, %f238, %p16;
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mul.f32 %f271, %f269, %f269;
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fma.rn.f32 %f272, %f268, %f268, %f271;
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fma.rn.f32 %f273, %f270, %f270, %f272;
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sqrt.rn.f32 %f274, %f273;
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rcp.rn.f32 %f275, %f274;
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mul.f32 %f17, %f268, %f275;
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mul.f32 %f18, %f269, %f275;
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mul.f32 %f19, %f270, %f275;
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ld.const.u32 %r5, [params+540];
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setp.lt.s32 %p17, %r5, 1;
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mov.f32 %f1411, %f1412;
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mov.f32 %f1410, %f1412;
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@%p17 bra $L__BB0_34;
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ld.const.u64 %rd36, [params+128];
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ld.const.u32 %r68, [params+120];
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cvt.rn.f32.s32 %f279, %r5;
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rcp.rn.f32 %f20, %f279;
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mad.lo.s32 %r69, %r68, %r54, %r53;
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cvta.to.global.u64 %rd37, %rd36;
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mul.wide.u32 %rd38, %r69, 4;
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add.s64 %rd39, %rd37, %rd38;
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ld.global.u32 %r366, [%rd39];
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ld.const.f32 %f21, [params+536];
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ld.const.u8 %rs24, [params+104];
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and.b16 %rs25, %rs24, 32;
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setp.eq.s16 %p18, %rs25, 0;
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mov.u32 %r67, 0;
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selp.f32 %f22, 0f3F800000, 0f41200000, %p18;
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mul.f32 %f23, %f14, 0f3456BF95;
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mul.f32 %f24, %f15, 0f3456BF95;
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mul.f32 %f25, %f16, 0f3456BF95;
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ld.const.u64 %rd3, [params+96];
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mul.f32 %f280, %f237, %f18;
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mul.f32 %f281, %f238, %f17;
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sub.f32 %f26, %f281, %f280;
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mul.f32 %f282, %f239, %f17;
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mul.f32 %f283, %f237, %f19;
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sub.f32 %f27, %f283, %f282;
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mul.f32 %f284, %f238, %f19;
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mul.f32 %f285, %f239, %f18;
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sub.f32 %f28, %f285, %f284;
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add.s64 %rd4, %rd1, 24;
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mov.u64 %rd40, __cudart_i2opi_f;
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abs.f32 %f368, %f24;
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abs.f32 %f369, %f23;
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max.f32 %f370, %f369, %f368;
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abs.f32 %f371, %f25;
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max.f32 %f372, %f370, %f371;
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mov.u32 %r363, %r67;
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$L__BB0_7:
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mov.u32 %r365, %r67;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1350, %r363;
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mad.lo.s32 %r71, %r366, 1664525, 1013904223;
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and.b32 %r72, %r71, 16777215;
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cvt.rn.f32.u32 %f286, %r72;
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fma.rn.f32 %f287, %f286, 0f33800000, %f1350;
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mul.f32 %f288, %f20, %f287;
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mad.lo.s32 %r366, %r71, 1664525, 1013904223;
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and.b32 %r73, %r366, 16777215;
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cvt.rn.f32.u32 %f289, %r73;
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cvt.rn.f32.s32 %f290, %r365;
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fma.rn.f32 %f291, %f289, 0f33800000, %f290;
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mul.f32 %f292, %f20, %f291;
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sqrt.rn.f32 %f36, %f288;
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mul.f32 %f37, %f292, 0f40C90FDB;
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mul.f32 %f293, %f37, 0f3F22F983;
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cvt.rni.s32.f32 %r373, %f293;
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cvt.rn.f32.s32 %f294, %r373;
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mov.f32 %f295, 0fBFC90FDA;
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fma.rn.f32 %f296, %f294, %f295, %f37;
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mov.f32 %f297, 0fB3A22168;
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fma.rn.f32 %f298, %f294, %f297, %f296;
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mov.f32 %f299, 0fA7C234C5;
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fma.rn.f32 %f1416, %f294, %f299, %f298;
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abs.f32 %f39, %f37;
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setp.ltu.f32 %p19, %f39, 0f47CE4780;
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mov.u32 %r370, %r373;
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mov.f32 %f1413, %f1416;
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@%p19 bra $L__BB0_16;
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setp.eq.f32 %p20, %f39, 0f7F800000;
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@%p20 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f302, 0f00000000;
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mul.rn.f32 %f1413, %f37, %f302;
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mov.u32 %r370, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r13, %f37;
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bfe.u32 %r75, %r13, 23, 8;
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add.s32 %r14, %r75, -128;
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shl.b32 %r76, %r13, 8;
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or.b32 %r15, %r76, -2147483648;
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shr.u32 %r16, %r14, 5;
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mov.u64 %rd112, 0;
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mov.u32 %r367, 0;
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mov.u64 %rd110, %rd1;
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mov.u64 %rd111, %rd40;
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$L__BB0_11:
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.pragma "nounroll";
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ld.global.nc.u32 %r77, [%rd111];
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mad.wide.u32 %rd42, %r77, %r15, %rd112;
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shr.u64 %rd112, %rd42, 32;
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st.local.u32 [%rd110], %rd42;
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add.s64 %rd111, %rd111, 4;
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add.s64 %rd110, %rd110, 4;
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add.s32 %r367, %r367, 1;
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setp.ne.s32 %p21, %r367, 6;
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@%p21 bra $L__BB0_11;
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st.local.u32 [%rd4], %rd112;
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mov.u32 %r78, 4;
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sub.s32 %r19, %r78, %r16;
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mov.u32 %r79, 6;
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sub.s32 %r80, %r79, %r16;
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mul.wide.s32 %rd43, %r80, 4;
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add.s64 %rd44, %rd1, %rd43;
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ld.local.u32 %r368, [%rd44];
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ld.local.u32 %r369, [%rd44+-4];
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and.b32 %r22, %r14, 31;
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setp.eq.s32 %p22, %r22, 0;
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@%p22 bra $L__BB0_14;
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mov.u32 %r81, 32;
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sub.s32 %r82, %r81, %r22;
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shr.u32 %r83, %r369, %r82;
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shl.b32 %r84, %r368, %r22;
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add.s32 %r368, %r83, %r84;
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mul.wide.s32 %rd45, %r19, 4;
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add.s64 %rd46, %rd1, %rd45;
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ld.local.u32 %r85, [%rd46];
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shr.u32 %r86, %r85, %r82;
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shl.b32 %r87, %r369, %r22;
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add.s32 %r369, %r86, %r87;
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$L__BB0_14:
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and.b32 %r88, %r13, -2147483648;
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shr.u32 %r89, %r369, 30;
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shl.b32 %r90, %r368, 2;
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or.b32 %r91, %r89, %r90;
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shr.u32 %r92, %r91, 31;
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shr.u32 %r93, %r368, 30;
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add.s32 %r94, %r92, %r93;
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neg.s32 %r95, %r94;
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setp.eq.s32 %p23, %r88, 0;
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selp.b32 %r370, %r94, %r95, %p23;
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setp.ne.s32 %p24, %r92, 0;
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xor.b32 %r96, %r88, -2147483648;
|
|
selp.b32 %r97, %r96, %r88, %p24;
|
|
selp.b32 %r98, -1, 0, %p24;
|
|
xor.b32 %r99, %r91, %r98;
|
|
shl.b32 %r100, %r369, 2;
|
|
xor.b32 %r101, %r100, %r98;
|
|
cvt.u64.u32 %rd47, %r99;
|
|
cvt.u64.u32 %rd48, %r101;
|
|
bfi.b64 %rd49, %rd47, %rd48, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd49;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f300, %fd2;
|
|
setp.eq.s32 %p25, %r97, 0;
|
|
neg.f32 %f301, %f300;
|
|
selp.f32 %f1413, %f300, %f301, %p25;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r29, %r370, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p26, %r30, 0;
|
|
selp.f32 %f43, %f1413, 0f3F800000, %p26;
|
|
mul.rn.f32 %f44, %f1413, %f1413;
|
|
mov.f32 %f1414, 0fB94D4153;
|
|
@%p26 bra $L__BB0_18;
|
|
|
|
mov.f32 %f304, 0fBAB607ED;
|
|
mov.f32 %f305, 0f37CBAC00;
|
|
fma.rn.f32 %f1414, %f305, %f44, %f304;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f306, 0f3C0885E4, 0f3D2AAABB, %p26;
|
|
fma.rn.f32 %f307, %f1414, %f44, %f306;
|
|
selp.f32 %f308, 0fBE2AAAA8, 0fBEFFFFFF, %p26;
|
|
fma.rn.f32 %f309, %f307, %f44, %f308;
|
|
mov.f32 %f310, 0f00000000;
|
|
fma.rn.f32 %f311, %f44, %f43, %f310;
|
|
fma.rn.f32 %f1415, %f309, %f311, %f43;
|
|
and.b32 %r103, %r29, 2;
|
|
setp.eq.s32 %p28, %r103, 0;
|
|
@%p28 bra $L__BB0_20;
|
|
|
|
mov.f32 %f313, 0fBF800000;
|
|
fma.rn.f32 %f1415, %f1415, %f313, %f310;
|
|
|
|
$L__BB0_20:
|
|
@%p19 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p30, %f39, 0f7F800000;
|
|
@%p30 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f316, 0f00000000;
|
|
mul.rn.f32 %f1416, %f37, %f316;
|
|
mov.u32 %r373, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r31, %f37;
|
|
bfe.u32 %r104, %r31, 23, 8;
|
|
add.s32 %r32, %r104, -128;
|
|
shl.b32 %r105, %r31, 8;
|
|
or.b32 %r33, %r105, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd113, 0;
|
|
mov.u64 %rd114, %rd113;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd52, %rd113, 2;
|
|
mov.u64 %rd53, __cudart_i2opi_f;
|
|
add.s64 %rd54, %rd53, %rd52;
|
|
ld.global.nc.u32 %r106, [%rd54];
|
|
mad.wide.u32 %rd55, %r106, %r33, %rd114;
|
|
shr.u64 %rd114, %rd55, 32;
|
|
add.s64 %rd56, %rd1, %rd52;
|
|
st.local.u32 [%rd56], %rd55;
|
|
cvt.u32.u64 %r107, %rd113;
|
|
add.s32 %r108, %r107, 1;
|
|
cvt.s64.s32 %rd113, %r108;
|
|
setp.ne.s32 %p31, %r108, 6;
|
|
@%p31 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd4], %rd114;
|
|
mov.u32 %r109, 4;
|
|
sub.s32 %r35, %r109, %r34;
|
|
mov.u32 %r110, 6;
|
|
sub.s32 %r111, %r110, %r34;
|
|
mul.wide.s32 %rd57, %r111, 4;
|
|
add.s64 %rd58, %rd1, %rd57;
|
|
ld.local.u32 %r371, [%rd58];
|
|
ld.local.u32 %r372, [%rd58+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p32, %r38, 0;
|
|
@%p32 bra $L__BB0_26;
|
|
|
|
mov.u32 %r112, 32;
|
|
sub.s32 %r113, %r112, %r38;
|
|
shr.u32 %r114, %r372, %r113;
|
|
shl.b32 %r115, %r371, %r38;
|
|
add.s32 %r371, %r114, %r115;
|
|
mul.wide.s32 %rd59, %r35, 4;
|
|
add.s64 %rd60, %rd1, %rd59;
|
|
ld.local.u32 %r116, [%rd60];
|
|
shr.u32 %r117, %r116, %r113;
|
|
shl.b32 %r118, %r372, %r38;
|
|
add.s32 %r372, %r117, %r118;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r119, %r31, -2147483648;
|
|
shr.u32 %r120, %r372, 30;
|
|
shl.b32 %r121, %r371, 2;
|
|
or.b32 %r122, %r120, %r121;
|
|
shr.u32 %r123, %r122, 31;
|
|
shr.u32 %r124, %r371, 30;
|
|
add.s32 %r125, %r123, %r124;
|
|
neg.s32 %r126, %r125;
|
|
setp.eq.s32 %p33, %r119, 0;
|
|
selp.b32 %r373, %r125, %r126, %p33;
|
|
setp.ne.s32 %p34, %r123, 0;
|
|
xor.b32 %r127, %r119, -2147483648;
|
|
selp.b32 %r128, %r127, %r119, %p34;
|
|
selp.b32 %r129, -1, 0, %p34;
|
|
xor.b32 %r130, %r122, %r129;
|
|
shl.b32 %r131, %r372, 2;
|
|
xor.b32 %r132, %r131, %r129;
|
|
cvt.u64.u32 %rd61, %r130;
|
|
cvt.u64.u32 %rd62, %r132;
|
|
bfi.b64 %rd63, %rd61, %rd62, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd63;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f314, %fd4;
|
|
setp.eq.s32 %p35, %r128, 0;
|
|
neg.f32 %f315, %f314;
|
|
selp.f32 %f1416, %f314, %f315, %p35;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f53, %f36, %f1415;
|
|
and.b32 %r45, %r373, 1;
|
|
setp.eq.s32 %p36, %r45, 0;
|
|
selp.f32 %f54, %f1416, 0f3F800000, %p36;
|
|
mul.rn.f32 %f55, %f1416, %f1416;
|
|
mov.f32 %f1417, 0fB94D4153;
|
|
@%p36 bra $L__BB0_30;
|
|
|
|
mov.f32 %f318, 0fBAB607ED;
|
|
mov.f32 %f319, 0f37CBAC00;
|
|
fma.rn.f32 %f1417, %f319, %f55, %f318;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f320, 0f3C0885E4, 0f3D2AAABB, %p36;
|
|
fma.rn.f32 %f321, %f1417, %f55, %f320;
|
|
selp.f32 %f322, 0fBE2AAAA8, 0fBEFFFFFF, %p36;
|
|
fma.rn.f32 %f323, %f321, %f55, %f322;
|
|
mov.f32 %f324, 0f00000000;
|
|
fma.rn.f32 %f325, %f55, %f54, %f324;
|
|
fma.rn.f32 %f1418, %f323, %f325, %f54;
|
|
and.b32 %r134, %r373, 2;
|
|
setp.eq.s32 %p38, %r134, 0;
|
|
@%p38 bra $L__BB0_32;
|
|
|
|
mov.f32 %f327, 0fBF800000;
|
|
fma.rn.f32 %f1418, %f1418, %f327, %f324;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f337, %f53, %f53;
|
|
mov.f32 %f338, 0f3F800000;
|
|
sub.f32 %f339, %f338, %f337;
|
|
mul.f32 %f340, %f36, %f1418;
|
|
mul.f32 %f341, %f340, %f340;
|
|
sub.f32 %f342, %f339, %f341;
|
|
max.f32 %f343, %f324, %f342;
|
|
sqrt.rn.f32 %f344, %f343;
|
|
mul.f32 %f345, %f17, %f340;
|
|
mul.f32 %f346, %f18, %f340;
|
|
mul.f32 %f347, %f19, %f340;
|
|
fma.rn.f32 %f348, %f28, %f53, %f345;
|
|
fma.rn.f32 %f349, %f27, %f53, %f346;
|
|
fma.rn.f32 %f350, %f26, %f53, %f347;
|
|
fma.rn.f32 %f351, %f237, %f344, %f348;
|
|
fma.rn.f32 %f352, %f238, %f344, %f349;
|
|
fma.rn.f32 %f353, %f239, %f344, %f350;
|
|
add.f32 %f354, %f237, %f351;
|
|
add.f32 %f355, %f238, %f352;
|
|
add.f32 %f356, %f239, %f353;
|
|
mul.f32 %f357, %f21, %f354;
|
|
mul.f32 %f358, %f21, %f355;
|
|
mul.f32 %f359, %f21, %f356;
|
|
sub.f32 %f360, %f357, %f237;
|
|
sub.f32 %f361, %f358, %f238;
|
|
sub.f32 %f362, %f359, %f239;
|
|
mul.f32 %f363, %f361, %f361;
|
|
fma.rn.f32 %f364, %f360, %f360, %f363;
|
|
fma.rn.f32 %f365, %f362, %f362, %f364;
|
|
sqrt.rn.f32 %f366, %f365;
|
|
rcp.rn.f32 %f367, %f366;
|
|
mul.f32 %f331, %f367, %f360;
|
|
mul.f32 %f332, %f367, %f361;
|
|
mul.f32 %f333, %f367, %f362;
|
|
mov.f32 %f373, 0f38D1B717;
|
|
max.f32 %f374, %f372, %f373;
|
|
mul.f32 %f334, %f22, %f374;
|
|
mov.f32 %f335, 0f6C4ECB8F;
|
|
mov.u32 %r171, 2;
|
|
mov.u32 %r172, 1;
|
|
mov.u32 %r173, 3;
|
|
mov.u32 %r176, 1065353216;
|
|
mov.u32 %r205, 0;
|
|
// begin inline asm
|
|
call(%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166),_optix_trace_typed_32,(%r205,%rd3,%f14,%f15,%f16,%f331,%f332,%f333,%f334,%f335,%f324,%r172,%r205,%r172,%r171,%r172,%r173,%r176,%r176,%r176,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205);
|
|
// end inline asm
|
|
mov.b32 %f375, %r135;
|
|
mov.b32 %f376, %r136;
|
|
mov.b32 %f377, %r137;
|
|
add.f32 %f1412, %f1412, %f375;
|
|
add.f32 %f1411, %f1411, %f376;
|
|
add.f32 %f1410, %f1410, %f377;
|
|
add.s32 %r365, %r365, 1;
|
|
setp.lt.s32 %p39, %r365, %r5;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r363, %r363, 1;
|
|
setp.lt.s32 %p40, %r363, %r5;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
setp.eq.s32 %p41, %r5, 0;
|
|
mov.f32 %f1422, 0f3F800000;
|
|
mov.f32 %f1423, %f1422;
|
|
mov.f32 %f1424, %f1422;
|
|
@%p41 bra $L__BB0_36;
|
|
|
|
mul.lo.s32 %r206, %r5, %r5;
|
|
cvt.rn.f32.s32 %f381, %r206;
|
|
rcp.rn.f32 %f382, %f381;
|
|
mul.f32 %f1422, %f1412, %f382;
|
|
mul.f32 %f1423, %f1411, %f382;
|
|
mul.f32 %f1424, %f1410, %f382;
|
|
|
|
$L__BB0_36:
|
|
ld.const.f32 %f384, [params+524];
|
|
mul.f32 %f73, %f1422, %f384;
|
|
ld.const.v2.f32 {%f385, %f386}, [params+528];
|
|
mul.f32 %f74, %f1423, %f385;
|
|
mul.f32 %f75, %f1424, %f386;
|
|
cvt.sat.f32.f32 %f389, %f13;
|
|
mul.f32 %f76, %f73, %f389;
|
|
mul.f32 %f77, %f74, %f389;
|
|
mul.f32 %f78, %f75, %f389;
|
|
fma.rn.f32 %f390, %f13, 0f3F000000, 0f3F000000;
|
|
cvt.sat.f32.f32 %f391, %f390;
|
|
add.f32 %f79, %f391, %f391;
|
|
mov.f32 %f395, 0f41A00000;
|
|
abs.f32 %f81, %f79;
|
|
setp.lt.f32 %p42, %f81, 0f00800000;
|
|
mul.f32 %f397, %f81, 0f4B800000;
|
|
selp.f32 %f398, %f397, %f81, %p42;
|
|
selp.f32 %f399, 0fC3170000, 0fC2FE0000, %p42;
|
|
mov.b32 %r207, %f398;
|
|
and.b32 %r208, %r207, 8388607;
|
|
or.b32 %r209, %r208, 1065353216;
|
|
mov.b32 %f400, %r209;
|
|
shr.u32 %r210, %r207, 23;
|
|
cvt.rn.f32.u32 %f401, %r210;
|
|
add.f32 %f402, %f399, %f401;
|
|
setp.gt.f32 %p43, %f400, 0f3FB504F3;
|
|
mul.f32 %f403, %f400, 0f3F000000;
|
|
add.f32 %f404, %f402, 0f3F800000;
|
|
selp.f32 %f405, %f404, %f402, %p43;
|
|
selp.f32 %f406, %f403, %f400, %p43;
|
|
add.f32 %f407, %f406, 0fBF800000;
|
|
add.f32 %f408, %f406, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f409, %f408;
|
|
add.f32 %f410, %f407, %f407;
|
|
mul.f32 %f411, %f410, %f409;
|
|
mul.f32 %f412, %f411, %f411;
|
|
mov.f32 %f413, 0f3C4CAF63;
|
|
mov.f32 %f414, 0f3B18F0FE;
|
|
fma.rn.f32 %f415, %f414, %f412, %f413;
|
|
mov.f32 %f416, 0f3DAAAABD;
|
|
fma.rn.f32 %f417, %f415, %f412, %f416;
|
|
mul.rn.f32 %f418, %f417, %f412;
|
|
mul.rn.f32 %f419, %f418, %f411;
|
|
sub.f32 %f420, %f407, %f411;
|
|
add.f32 %f421, %f420, %f420;
|
|
neg.f32 %f422, %f411;
|
|
fma.rn.f32 %f423, %f422, %f407, %f421;
|
|
mul.rn.f32 %f424, %f409, %f423;
|
|
add.f32 %f425, %f419, %f411;
|
|
sub.f32 %f426, %f411, %f425;
|
|
add.f32 %f427, %f419, %f426;
|
|
add.f32 %f428, %f424, %f427;
|
|
add.f32 %f429, %f425, %f428;
|
|
sub.f32 %f430, %f425, %f429;
|
|
add.f32 %f431, %f428, %f430;
|
|
mov.f32 %f432, 0f3F317200;
|
|
mul.rn.f32 %f433, %f405, %f432;
|
|
mov.f32 %f434, 0f35BFBE8E;
|
|
mul.rn.f32 %f435, %f405, %f434;
|
|
add.f32 %f436, %f433, %f429;
|
|
sub.f32 %f437, %f433, %f436;
|
|
add.f32 %f438, %f429, %f437;
|
|
add.f32 %f439, %f431, %f438;
|
|
add.f32 %f440, %f435, %f439;
|
|
add.f32 %f441, %f436, %f440;
|
|
sub.f32 %f442, %f436, %f441;
|
|
add.f32 %f443, %f440, %f442;
|
|
mul.rn.f32 %f444, %f395, %f441;
|
|
neg.f32 %f445, %f444;
|
|
fma.rn.f32 %f446, %f395, %f441, %f445;
|
|
fma.rn.f32 %f447, %f395, %f443, %f446;
|
|
mov.f32 %f448, 0f00000000;
|
|
fma.rn.f32 %f449, %f448, %f441, %f447;
|
|
add.rn.f32 %f450, %f444, %f449;
|
|
neg.f32 %f451, %f450;
|
|
add.rn.f32 %f452, %f444, %f451;
|
|
add.rn.f32 %f453, %f452, %f449;
|
|
mov.b32 %r211, %f450;
|
|
setp.eq.s32 %p44, %r211, 1118925336;
|
|
add.s32 %r212, %r211, -1;
|
|
mov.b32 %f454, %r212;
|
|
add.f32 %f455, %f453, 0f37000000;
|
|
selp.f32 %f82, %f455, %f453, %p44;
|
|
selp.f32 %f456, %f454, %f450, %p44;
|
|
mov.f32 %f457, 0f3FB8AA3B;
|
|
mul.rn.f32 %f458, %f456, %f457;
|
|
cvt.rzi.f32.f32 %f459, %f458;
|
|
abs.f32 %f460, %f459;
|
|
setp.gt.f32 %p45, %f460, 0f42FC0000;
|
|
mov.b32 %r213, %f459;
|
|
and.b32 %r214, %r213, -2147483648;
|
|
or.b32 %r215, %r214, 1123811328;
|
|
mov.b32 %f461, %r215;
|
|
selp.f32 %f462, %f461, %f459, %p45;
|
|
mov.f32 %f463, 0fBF317218;
|
|
fma.rn.f32 %f464, %f462, %f463, %f456;
|
|
mov.f32 %f465, 0f3102E308;
|
|
fma.rn.f32 %f466, %f462, %f465, %f464;
|
|
mul.f32 %f467, %f466, 0f3FB8AA3B;
|
|
add.f32 %f468, %f462, 0f4B40007F;
|
|
mov.b32 %r216, %f468;
|
|
shl.b32 %r217, %r216, 23;
|
|
mov.b32 %f469, %r217;
|
|
ex2.approx.ftz.f32 %f470, %f467;
|
|
mul.f32 %f83, %f470, %f469;
|
|
setp.eq.f32 %p46, %f83, 0f7F800000;
|
|
mov.f32 %f1425, 0f7F800000;
|
|
@%p46 bra $L__BB0_38;
|
|
|
|
fma.rn.f32 %f1425, %f83, %f82, %f83;
|
|
|
|
$L__BB0_38:
|
|
mov.f32 %f1356, 0f41200000;
|
|
cvt.rzi.f32.f32 %f1355, %f1356;
|
|
add.f32 %f1354, %f1355, %f1355;
|
|
mov.f32 %f1353, 0f41A00000;
|
|
sub.f32 %f1352, %f1353, %f1354;
|
|
abs.f32 %f1351, %f1352;
|
|
setp.lt.f32 %p47, %f79, 0f00000000;
|
|
setp.eq.f32 %p48, %f1351, 0f3F800000;
|
|
and.pred %p1, %p47, %p48;
|
|
setp.eq.f32 %p49, %f79, 0f00000000;
|
|
@%p49 bra $L__BB0_42;
|
|
bra.uni $L__BB0_39;
|
|
|
|
$L__BB0_42:
|
|
add.f32 %f475, %f79, %f79;
|
|
selp.f32 %f1427, %f475, 0f00000000, %p48;
|
|
bra.uni $L__BB0_43;
|
|
|
|
$L__BB0_39:
|
|
mov.b32 %r218, %f1425;
|
|
xor.b32 %r219, %r218, -2147483648;
|
|
mov.b32 %f471, %r219;
|
|
selp.f32 %f1427, %f471, %f1425, %p1;
|
|
setp.geu.f32 %p50, %f79, 0f00000000;
|
|
@%p50 bra $L__BB0_43;
|
|
|
|
mov.f32 %f472, 0f41A00000;
|
|
cvt.rzi.f32.f32 %f473, %f472;
|
|
setp.eq.f32 %p51, %f473, 0f41A00000;
|
|
@%p51 bra $L__BB0_43;
|
|
|
|
mov.f32 %f1427, 0f7FFFFFFF;
|
|
|
|
$L__BB0_43:
|
|
abs.f32 %f1357, %f79;
|
|
add.f32 %f476, %f1357, 0f41A00000;
|
|
mov.b32 %r220, %f476;
|
|
setp.lt.s32 %p53, %r220, 2139095040;
|
|
@%p53 bra $L__BB0_48;
|
|
|
|
abs.f32 %f1360, %f79;
|
|
setp.gtu.f32 %p54, %f1360, 0f7F800000;
|
|
@%p54 bra $L__BB0_47;
|
|
bra.uni $L__BB0_45;
|
|
|
|
$L__BB0_47:
|
|
add.f32 %f1427, %f79, 0f41A00000;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_45:
|
|
abs.f32 %f1361, %f79;
|
|
setp.neu.f32 %p55, %f1361, 0f7F800000;
|
|
@%p55 bra $L__BB0_48;
|
|
|
|
selp.f32 %f1427, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_48:
|
|
ld.const.f32 %f1359, [params+524];
|
|
mul.f32 %f1358, %f1422, %f1359;
|
|
setp.eq.f32 %p56, %f79, 0f3F800000;
|
|
selp.f32 %f477, 0f3F800000, %f1427, %p56;
|
|
cvt.sat.f32.f32 %f478, %f477;
|
|
mul.f32 %f92, %f1358, %f478;
|
|
mul.f32 %f93, %f74, %f478;
|
|
mul.f32 %f94, %f75, %f478;
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r221, %r48, 8;
|
|
setp.eq.s32 %p57, %r221, 0;
|
|
@%p57 bra $L__BB0_62;
|
|
|
|
ld.const.u32 %r222, [params+184];
|
|
mad.lo.s32 %r223, %r222, %r4, %r3;
|
|
cvt.u64.u32 %rd16, %r223;
|
|
mov.f32 %f483, 0f3EE8BA2E;
|
|
abs.f32 %f96, %f1422;
|
|
setp.lt.f32 %p58, %f96, 0f00800000;
|
|
mul.f32 %f485, %f96, 0f4B800000;
|
|
selp.f32 %f486, %f485, %f96, %p58;
|
|
selp.f32 %f487, 0fC3170000, 0fC2FE0000, %p58;
|
|
mov.b32 %r224, %f486;
|
|
and.b32 %r225, %r224, 8388607;
|
|
or.b32 %r226, %r225, 1065353216;
|
|
mov.b32 %f488, %r226;
|
|
shr.u32 %r227, %r224, 23;
|
|
cvt.rn.f32.u32 %f489, %r227;
|
|
add.f32 %f490, %f487, %f489;
|
|
setp.gt.f32 %p59, %f488, 0f3FB504F3;
|
|
mul.f32 %f491, %f488, 0f3F000000;
|
|
add.f32 %f492, %f490, 0f3F800000;
|
|
selp.f32 %f493, %f492, %f490, %p59;
|
|
selp.f32 %f494, %f491, %f488, %p59;
|
|
add.f32 %f495, %f494, 0fBF800000;
|
|
add.f32 %f496, %f494, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f497, %f496;
|
|
add.f32 %f498, %f495, %f495;
|
|
mul.f32 %f499, %f498, %f497;
|
|
mul.f32 %f500, %f499, %f499;
|
|
mov.f32 %f501, 0f3C4CAF63;
|
|
mov.f32 %f502, 0f3B18F0FE;
|
|
fma.rn.f32 %f503, %f502, %f500, %f501;
|
|
mov.f32 %f504, 0f3DAAAABD;
|
|
fma.rn.f32 %f505, %f503, %f500, %f504;
|
|
mul.rn.f32 %f506, %f505, %f500;
|
|
mul.rn.f32 %f507, %f506, %f499;
|
|
sub.f32 %f508, %f495, %f499;
|
|
add.f32 %f509, %f508, %f508;
|
|
neg.f32 %f510, %f499;
|
|
fma.rn.f32 %f511, %f510, %f495, %f509;
|
|
mul.rn.f32 %f512, %f497, %f511;
|
|
add.f32 %f513, %f507, %f499;
|
|
sub.f32 %f514, %f499, %f513;
|
|
add.f32 %f515, %f507, %f514;
|
|
add.f32 %f516, %f512, %f515;
|
|
add.f32 %f517, %f513, %f516;
|
|
sub.f32 %f518, %f513, %f517;
|
|
add.f32 %f519, %f516, %f518;
|
|
mov.f32 %f520, 0f3F317200;
|
|
mul.rn.f32 %f521, %f493, %f520;
|
|
mov.f32 %f522, 0f35BFBE8E;
|
|
mul.rn.f32 %f523, %f493, %f522;
|
|
add.f32 %f524, %f521, %f517;
|
|
sub.f32 %f525, %f521, %f524;
|
|
add.f32 %f526, %f517, %f525;
|
|
add.f32 %f527, %f519, %f526;
|
|
add.f32 %f528, %f523, %f527;
|
|
add.f32 %f529, %f524, %f528;
|
|
sub.f32 %f530, %f524, %f529;
|
|
add.f32 %f531, %f528, %f530;
|
|
mul.rn.f32 %f532, %f483, %f529;
|
|
neg.f32 %f533, %f532;
|
|
fma.rn.f32 %f534, %f483, %f529, %f533;
|
|
fma.rn.f32 %f535, %f483, %f531, %f534;
|
|
mov.f32 %f536, 0f00000000;
|
|
fma.rn.f32 %f537, %f536, %f529, %f535;
|
|
add.rn.f32 %f538, %f532, %f537;
|
|
neg.f32 %f539, %f538;
|
|
add.rn.f32 %f540, %f532, %f539;
|
|
add.rn.f32 %f541, %f540, %f537;
|
|
mov.b32 %r228, %f538;
|
|
setp.eq.s32 %p60, %r228, 1118925336;
|
|
add.s32 %r229, %r228, -1;
|
|
mov.b32 %f542, %r229;
|
|
add.f32 %f543, %f541, 0f37000000;
|
|
selp.f32 %f97, %f543, %f541, %p60;
|
|
selp.f32 %f544, %f542, %f538, %p60;
|
|
mov.f32 %f545, 0f3FB8AA3B;
|
|
mul.rn.f32 %f546, %f544, %f545;
|
|
cvt.rzi.f32.f32 %f547, %f546;
|
|
abs.f32 %f548, %f547;
|
|
setp.gt.f32 %p61, %f548, 0f42FC0000;
|
|
mov.b32 %r230, %f547;
|
|
and.b32 %r231, %r230, -2147483648;
|
|
or.b32 %r232, %r231, 1123811328;
|
|
mov.b32 %f549, %r232;
|
|
selp.f32 %f550, %f549, %f547, %p61;
|
|
mov.f32 %f551, 0fBF317218;
|
|
fma.rn.f32 %f552, %f550, %f551, %f544;
|
|
mov.f32 %f553, 0f3102E308;
|
|
fma.rn.f32 %f554, %f550, %f553, %f552;
|
|
mul.f32 %f555, %f554, 0f3FB8AA3B;
|
|
add.f32 %f556, %f550, 0f4B40007F;
|
|
mov.b32 %r233, %f556;
|
|
shl.b32 %r234, %r233, 23;
|
|
mov.b32 %f557, %r234;
|
|
ex2.approx.ftz.f32 %f558, %f555;
|
|
mul.f32 %f98, %f558, %f557;
|
|
setp.eq.f32 %p62, %f98, 0f7F800000;
|
|
mov.f32 %f1428, 0f7F800000;
|
|
@%p62 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1428, %f98, %f97, %f98;
|
|
|
|
$L__BB0_51:
|
|
mov.f32 %f1403, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f1402, %f1403;
|
|
add.f32 %f1401, %f1402, %f1402;
|
|
mov.f32 %f1400, 0f3EE8BA2E;
|
|
sub.f32 %f1399, %f1400, %f1401;
|
|
abs.f32 %f1398, %f1399;
|
|
setp.lt.f32 %p63, %f1422, 0f00000000;
|
|
setp.eq.f32 %p64, %f1398, 0f3F800000;
|
|
and.pred %p2, %p63, %p64;
|
|
setp.eq.f32 %p65, %f1422, 0f00000000;
|
|
@%p65 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f563, %f1422, %f1422;
|
|
selp.f32 %f1430, %f563, 0f00000000, %p64;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_164:
|
|
mov.f32 %f1307, 0f00000000;
|
|
mov.u32 %r374, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1307;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1307;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1307;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs129, 0;
|
|
st.global.v4.u16 [%rd24], {%rs126, %rs127, %rs128, %rs129};
|
|
|
|
$L__BB0_165:
|
|
ld.const.u64 %rd97, [params+256];
|
|
cvta.to.global.u64 %rd98, %rd97;
|
|
ld.const.u32 %r355, [params+248];
|
|
mad.lo.s32 %r356, %r355, %r4, %r3;
|
|
mul.wide.u32 %rd99, %r356, 8;
|
|
add.s64 %rd25, %rd98, %rd99;
|
|
setp.eq.s32 %p190, %r374, 0;
|
|
@%p190 bra $L__BB0_167;
|
|
|
|
ld.global.v4.u16 {%rs136, %rs137, %rs138, %rs139}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1308, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1309, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1310, %rs138;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1311, %f1308, 0f00000000;
|
|
add.f32 %f1312, %f1309, 0f00000000;
|
|
add.f32 %f1313, %f1310, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1313;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1312;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1311;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs140, 0;
|
|
st.global.v4.u16 [%rd25], {%rs133, %rs134, %rs135, %rs140};
|
|
bra.uni $L__BB0_168;
|
|
|
|
$L__BB0_167:
|
|
mov.f32 %f1316, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1316;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs144, 0;
|
|
st.global.v4.u16 [%rd25], {%rs141, %rs142, %rs143, %rs144};
|
|
|
|
$L__BB0_168:
|
|
ld.const.u64 %rd100, [params+272];
|
|
cvta.to.global.u64 %rd101, %rd100;
|
|
ld.const.u32 %r357, [params+264];
|
|
mad.lo.s32 %r358, %r357, %r4, %r3;
|
|
mul.wide.u32 %rd102, %r358, 8;
|
|
add.s64 %rd26, %rd101, %rd102;
|
|
@%p190 bra $L__BB0_170;
|
|
|
|
ld.global.v4.u16 {%rs151, %rs152, %rs153, %rs154}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1317, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1318, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1319, %rs153;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1320, %f1317, 0f00000000;
|
|
add.f32 %f1321, %f1318, 0f00000000;
|
|
add.f32 %f1322, %f1319, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1322;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1321;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1320;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs155, 0;
|
|
st.global.v4.u16 [%rd26], {%rs148, %rs149, %rs150, %rs155};
|
|
bra.uni $L__BB0_171;
|
|
|
|
$L__BB0_170:
|
|
mov.f32 %f1325, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1325;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs159, 0;
|
|
st.global.v4.u16 [%rd26], {%rs156, %rs157, %rs158, %rs159};
|
|
|
|
$L__BB0_171:
|
|
ld.const.u64 %rd103, [params+288];
|
|
cvta.to.global.u64 %rd104, %rd103;
|
|
ld.const.u32 %r359, [params+280];
|
|
mad.lo.s32 %r360, %r359, %r4, %r3;
|
|
mul.wide.u32 %rd105, %r360, 8;
|
|
add.s64 %rd27, %rd104, %rd105;
|
|
@%p190 bra $L__BB0_173;
|
|
|
|
ld.global.v4.u16 {%rs166, %rs167, %rs168, %rs169}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1326, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1327, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1328, %rs168;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1329, %f1326, 0f00000000;
|
|
add.f32 %f1330, %f1327, 0f00000000;
|
|
add.f32 %f1331, %f1328, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1331;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1330;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1329;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs170, 0;
|
|
st.global.v4.u16 [%rd27], {%rs163, %rs164, %rs165, %rs170};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_173:
|
|
mov.f32 %f1334, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1334;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1334;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1334;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs174, 0;
|
|
st.global.v4.u16 [%rd27], {%rs171, %rs172, %rs173, %rs174};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r235, %f1428;
|
|
xor.b32 %r236, %r235, -2147483648;
|
|
mov.b32 %f559, %r236;
|
|
selp.f32 %f1430, %f559, %f1428, %p2;
|
|
setp.geu.f32 %p66, %f1422, 0f00000000;
|
|
@%p66 bra $L__BB0_56;
|
|
|
|
mov.f32 %f560, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f561, %f560;
|
|
setp.eq.f32 %p67, %f561, 0f3EE8BA2E;
|
|
@%p67 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1430, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
abs.f32 %f1362, %f1422;
|
|
add.f32 %f564, %f1362, 0f3EE8BA2E;
|
|
mov.b32 %r237, %f564;
|
|
setp.lt.s32 %p69, %r237, 2139095040;
|
|
@%p69 bra $L__BB0_61;
|
|
|
|
abs.f32 %f1363, %f1422;
|
|
setp.gtu.f32 %p70, %f1363, 0f7F800000;
|
|
@%p70 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1430, %f1422, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1364, %f1422;
|
|
setp.neu.f32 %p71, %f1364, 0f7F800000;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1430, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
ld.const.u64 %rd109, [params+192];
|
|
cvta.to.global.u64 %rd108, %rd109;
|
|
mul.f32 %f565, %f1430, 0f437F0000;
|
|
setp.eq.f32 %p72, %f1422, 0f3F800000;
|
|
selp.f32 %f566, 0f437F0000, %f565, %p72;
|
|
cvt.rzi.u32.f32 %r238, %f566;
|
|
shl.b64 %rd66, %rd16, 1;
|
|
add.s64 %rd67, %rd108, %rd66;
|
|
cvt.u16.u32 %rs26, %r238;
|
|
mov.u16 %rs27, 255;
|
|
st.global.v2.u8 [%rd67], {%rs26, %rs27};
|
|
|
|
$L__BB0_62:
|
|
ld.const.u32 %r362, [params+104];
|
|
and.b32 %r239, %r362, 1;
|
|
setp.eq.b32 %p73, %r239, 1;
|
|
mov.pred %p74, 0;
|
|
xor.pred %p75, %p73, %p74;
|
|
not.pred %p76, %p75;
|
|
@%p76 bra $L__BB0_136;
|
|
|
|
mov.f32 %f571, 0f3EE66666;
|
|
abs.f32 %f108, %f76;
|
|
setp.lt.f32 %p77, %f108, 0f00800000;
|
|
mul.f32 %f573, %f108, 0f4B800000;
|
|
selp.f32 %f574, %f573, %f108, %p77;
|
|
selp.f32 %f575, 0fC3170000, 0fC2FE0000, %p77;
|
|
mov.b32 %r240, %f574;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f576, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f577, %r243;
|
|
add.f32 %f578, %f575, %f577;
|
|
setp.gt.f32 %p78, %f576, 0f3FB504F3;
|
|
mul.f32 %f579, %f576, 0f3F000000;
|
|
add.f32 %f580, %f578, 0f3F800000;
|
|
selp.f32 %f581, %f580, %f578, %p78;
|
|
selp.f32 %f582, %f579, %f576, %p78;
|
|
add.f32 %f583, %f582, 0fBF800000;
|
|
add.f32 %f584, %f582, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f585, %f584;
|
|
add.f32 %f586, %f583, %f583;
|
|
mul.f32 %f587, %f586, %f585;
|
|
mul.f32 %f588, %f587, %f587;
|
|
mov.f32 %f589, 0f3C4CAF63;
|
|
mov.f32 %f590, 0f3B18F0FE;
|
|
fma.rn.f32 %f591, %f590, %f588, %f589;
|
|
mov.f32 %f592, 0f3DAAAABD;
|
|
fma.rn.f32 %f593, %f591, %f588, %f592;
|
|
mul.rn.f32 %f594, %f593, %f588;
|
|
mul.rn.f32 %f595, %f594, %f587;
|
|
sub.f32 %f596, %f583, %f587;
|
|
add.f32 %f597, %f596, %f596;
|
|
neg.f32 %f598, %f587;
|
|
fma.rn.f32 %f599, %f598, %f583, %f597;
|
|
mul.rn.f32 %f600, %f585, %f599;
|
|
add.f32 %f601, %f595, %f587;
|
|
sub.f32 %f602, %f587, %f601;
|
|
add.f32 %f603, %f595, %f602;
|
|
add.f32 %f604, %f600, %f603;
|
|
add.f32 %f605, %f601, %f604;
|
|
sub.f32 %f606, %f601, %f605;
|
|
add.f32 %f607, %f604, %f606;
|
|
mov.f32 %f608, 0f3F317200;
|
|
mul.rn.f32 %f609, %f581, %f608;
|
|
mov.f32 %f610, 0f35BFBE8E;
|
|
mul.rn.f32 %f611, %f581, %f610;
|
|
add.f32 %f612, %f609, %f605;
|
|
sub.f32 %f613, %f609, %f612;
|
|
add.f32 %f614, %f605, %f613;
|
|
add.f32 %f615, %f607, %f614;
|
|
add.f32 %f616, %f611, %f615;
|
|
add.f32 %f617, %f612, %f616;
|
|
sub.f32 %f618, %f612, %f617;
|
|
add.f32 %f619, %f616, %f618;
|
|
mul.rn.f32 %f620, %f571, %f617;
|
|
neg.f32 %f621, %f620;
|
|
fma.rn.f32 %f622, %f571, %f617, %f621;
|
|
fma.rn.f32 %f623, %f571, %f619, %f622;
|
|
mov.f32 %f624, 0f00000000;
|
|
fma.rn.f32 %f625, %f624, %f617, %f623;
|
|
add.rn.f32 %f626, %f620, %f625;
|
|
neg.f32 %f627, %f626;
|
|
add.rn.f32 %f628, %f620, %f627;
|
|
add.rn.f32 %f629, %f628, %f625;
|
|
mov.b32 %r244, %f626;
|
|
setp.eq.s32 %p79, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f630, %r245;
|
|
add.f32 %f631, %f629, 0f37000000;
|
|
selp.f32 %f109, %f631, %f629, %p79;
|
|
selp.f32 %f632, %f630, %f626, %p79;
|
|
mov.f32 %f633, 0f3FB8AA3B;
|
|
mul.rn.f32 %f634, %f632, %f633;
|
|
cvt.rzi.f32.f32 %f635, %f634;
|
|
abs.f32 %f636, %f635;
|
|
setp.gt.f32 %p80, %f636, 0f42FC0000;
|
|
mov.b32 %r246, %f635;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f637, %r248;
|
|
selp.f32 %f638, %f637, %f635, %p80;
|
|
mov.f32 %f639, 0fBF317218;
|
|
fma.rn.f32 %f640, %f638, %f639, %f632;
|
|
mov.f32 %f641, 0f3102E308;
|
|
fma.rn.f32 %f642, %f638, %f641, %f640;
|
|
mul.f32 %f643, %f642, 0f3FB8AA3B;
|
|
add.f32 %f644, %f638, 0f4B40007F;
|
|
mov.b32 %r249, %f644;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f645, %r250;
|
|
ex2.approx.ftz.f32 %f646, %f643;
|
|
mul.f32 %f110, %f646, %f645;
|
|
setp.eq.f32 %p81, %f110, 0f7F800000;
|
|
mov.f32 %f1431, 0f7F800000;
|
|
@%p81 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1431, %f110, %f109, %f110;
|
|
|
|
$L__BB0_65:
|
|
mov.f32 %f1370, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1369, %f1370;
|
|
add.f32 %f1368, %f1369, %f1369;
|
|
mov.f32 %f1367, 0f3EE66666;
|
|
sub.f32 %f1366, %f1367, %f1368;
|
|
abs.f32 %f1365, %f1366;
|
|
setp.lt.f32 %p82, %f76, 0f00000000;
|
|
setp.eq.f32 %p83, %f1365, 0f3F800000;
|
|
and.pred %p3, %p82, %p83;
|
|
setp.eq.f32 %p84, %f76, 0f00000000;
|
|
@%p84 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f651, %f76, %f76;
|
|
selp.f32 %f1433, %f651, 0f00000000, %p83;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r251, %f1431;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f647, %r252;
|
|
selp.f32 %f1433, %f647, %f1431, %p3;
|
|
setp.geu.f32 %p85, %f76, 0f00000000;
|
|
@%p85 bra $L__BB0_70;
|
|
|
|
mov.f32 %f648, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f649, %f648;
|
|
setp.eq.f32 %p86, %f649, 0f3EE66666;
|
|
@%p86 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1433, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1371, %f76;
|
|
add.f32 %f652, %f1371, 0f3EE66666;
|
|
mov.b32 %r253, %f652;
|
|
setp.lt.s32 %p88, %r253, 2139095040;
|
|
@%p88 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1372, %f76;
|
|
setp.gtu.f32 %p89, %f1372, 0f7F800000;
|
|
@%p89 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1433, %f76, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1373, %f76;
|
|
setp.neu.f32 %p90, %f1373, 0f7F800000;
|
|
@%p90 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1433, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p91, %f76, 0f3F800000;
|
|
selp.f32 %f119, 0f3F800000, %f1433, %p91;
|
|
abs.f32 %f120, %f77;
|
|
setp.lt.f32 %p92, %f120, 0f00800000;
|
|
mul.f32 %f654, %f120, 0f4B800000;
|
|
selp.f32 %f655, %f654, %f120, %p92;
|
|
selp.f32 %f656, 0fC3170000, 0fC2FE0000, %p92;
|
|
mov.b32 %r254, %f655;
|
|
and.b32 %r255, %r254, 8388607;
|
|
or.b32 %r256, %r255, 1065353216;
|
|
mov.b32 %f657, %r256;
|
|
shr.u32 %r257, %r254, 23;
|
|
cvt.rn.f32.u32 %f658, %r257;
|
|
add.f32 %f659, %f656, %f658;
|
|
setp.gt.f32 %p93, %f657, 0f3FB504F3;
|
|
mul.f32 %f660, %f657, 0f3F000000;
|
|
add.f32 %f661, %f659, 0f3F800000;
|
|
selp.f32 %f662, %f661, %f659, %p93;
|
|
selp.f32 %f663, %f660, %f657, %p93;
|
|
add.f32 %f664, %f663, 0fBF800000;
|
|
add.f32 %f665, %f663, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f666, %f665;
|
|
add.f32 %f667, %f664, %f664;
|
|
mul.f32 %f668, %f667, %f666;
|
|
mul.f32 %f669, %f668, %f668;
|
|
mov.f32 %f670, 0f3C4CAF63;
|
|
mov.f32 %f671, 0f3B18F0FE;
|
|
fma.rn.f32 %f672, %f671, %f669, %f670;
|
|
mov.f32 %f673, 0f3DAAAABD;
|
|
fma.rn.f32 %f674, %f672, %f669, %f673;
|
|
mul.rn.f32 %f675, %f674, %f669;
|
|
mul.rn.f32 %f676, %f675, %f668;
|
|
sub.f32 %f677, %f664, %f668;
|
|
add.f32 %f678, %f677, %f677;
|
|
neg.f32 %f679, %f668;
|
|
fma.rn.f32 %f680, %f679, %f664, %f678;
|
|
mul.rn.f32 %f681, %f666, %f680;
|
|
add.f32 %f682, %f676, %f668;
|
|
sub.f32 %f683, %f668, %f682;
|
|
add.f32 %f684, %f676, %f683;
|
|
add.f32 %f685, %f681, %f684;
|
|
add.f32 %f686, %f682, %f685;
|
|
sub.f32 %f687, %f682, %f686;
|
|
add.f32 %f688, %f685, %f687;
|
|
mov.f32 %f689, 0f3F317200;
|
|
mul.rn.f32 %f690, %f662, %f689;
|
|
mov.f32 %f691, 0f35BFBE8E;
|
|
mul.rn.f32 %f692, %f662, %f691;
|
|
add.f32 %f693, %f690, %f686;
|
|
sub.f32 %f694, %f690, %f693;
|
|
add.f32 %f695, %f686, %f694;
|
|
add.f32 %f696, %f688, %f695;
|
|
add.f32 %f697, %f692, %f696;
|
|
add.f32 %f698, %f693, %f697;
|
|
sub.f32 %f699, %f693, %f698;
|
|
add.f32 %f700, %f697, %f699;
|
|
mov.f32 %f701, 0f3EE66666;
|
|
mul.rn.f32 %f702, %f701, %f698;
|
|
neg.f32 %f703, %f702;
|
|
fma.rn.f32 %f704, %f701, %f698, %f703;
|
|
fma.rn.f32 %f705, %f701, %f700, %f704;
|
|
mov.f32 %f706, 0f00000000;
|
|
fma.rn.f32 %f707, %f706, %f698, %f705;
|
|
add.rn.f32 %f708, %f702, %f707;
|
|
neg.f32 %f709, %f708;
|
|
add.rn.f32 %f710, %f702, %f709;
|
|
add.rn.f32 %f711, %f710, %f707;
|
|
mov.b32 %r258, %f708;
|
|
setp.eq.s32 %p94, %r258, 1118925336;
|
|
add.s32 %r259, %r258, -1;
|
|
mov.b32 %f712, %r259;
|
|
add.f32 %f713, %f711, 0f37000000;
|
|
selp.f32 %f121, %f713, %f711, %p94;
|
|
selp.f32 %f714, %f712, %f708, %p94;
|
|
mov.f32 %f715, 0f3FB8AA3B;
|
|
mul.rn.f32 %f716, %f714, %f715;
|
|
cvt.rzi.f32.f32 %f717, %f716;
|
|
abs.f32 %f718, %f717;
|
|
setp.gt.f32 %p95, %f718, 0f42FC0000;
|
|
mov.b32 %r260, %f717;
|
|
and.b32 %r261, %r260, -2147483648;
|
|
or.b32 %r262, %r261, 1123811328;
|
|
mov.b32 %f719, %r262;
|
|
selp.f32 %f720, %f719, %f717, %p95;
|
|
mov.f32 %f721, 0fBF317218;
|
|
fma.rn.f32 %f722, %f720, %f721, %f714;
|
|
mov.f32 %f723, 0f3102E308;
|
|
fma.rn.f32 %f724, %f720, %f723, %f722;
|
|
mul.f32 %f725, %f724, 0f3FB8AA3B;
|
|
add.f32 %f726, %f720, 0f4B40007F;
|
|
mov.b32 %r263, %f726;
|
|
shl.b32 %r264, %r263, 23;
|
|
mov.b32 %f727, %r264;
|
|
ex2.approx.ftz.f32 %f728, %f725;
|
|
mul.f32 %f122, %f728, %f727;
|
|
setp.eq.f32 %p96, %f122, 0f7F800000;
|
|
mov.f32 %f1434, 0f7F800000;
|
|
@%p96 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1434, %f122, %f121, %f122;
|
|
|
|
$L__BB0_77:
|
|
setp.lt.f32 %p97, %f77, 0f00000000;
|
|
and.pred %p4, %p97, %p83;
|
|
setp.eq.f32 %p99, %f77, 0f00000000;
|
|
@%p99 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f733, %f77, %f77;
|
|
selp.f32 %f1436, %f733, 0f00000000, %p83;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r265, %f1434;
|
|
xor.b32 %r266, %r265, -2147483648;
|
|
mov.b32 %f729, %r266;
|
|
selp.f32 %f1436, %f729, %f1434, %p4;
|
|
setp.geu.f32 %p100, %f77, 0f00000000;
|
|
@%p100 bra $L__BB0_82;
|
|
|
|
mov.f32 %f730, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f731, %f730;
|
|
setp.eq.f32 %p101, %f731, 0f3EE66666;
|
|
@%p101 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1436, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
abs.f32 %f1374, %f77;
|
|
add.f32 %f734, %f1374, 0f3EE66666;
|
|
mov.b32 %r267, %f734;
|
|
setp.lt.s32 %p103, %r267, 2139095040;
|
|
@%p103 bra $L__BB0_87;
|
|
|
|
abs.f32 %f1375, %f77;
|
|
setp.gtu.f32 %p104, %f1375, 0f7F800000;
|
|
@%p104 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1436, %f77, 0f3EE66666;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
abs.f32 %f1376, %f77;
|
|
setp.neu.f32 %p105, %f1376, 0f7F800000;
|
|
@%p105 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1436, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
setp.eq.f32 %p106, %f77, 0f3F800000;
|
|
selp.f32 %f131, 0f3F800000, %f1436, %p106;
|
|
abs.f32 %f132, %f78;
|
|
setp.lt.f32 %p107, %f132, 0f00800000;
|
|
mul.f32 %f736, %f132, 0f4B800000;
|
|
selp.f32 %f737, %f736, %f132, %p107;
|
|
selp.f32 %f738, 0fC3170000, 0fC2FE0000, %p107;
|
|
mov.b32 %r268, %f737;
|
|
and.b32 %r269, %r268, 8388607;
|
|
or.b32 %r270, %r269, 1065353216;
|
|
mov.b32 %f739, %r270;
|
|
shr.u32 %r271, %r268, 23;
|
|
cvt.rn.f32.u32 %f740, %r271;
|
|
add.f32 %f741, %f738, %f740;
|
|
setp.gt.f32 %p108, %f739, 0f3FB504F3;
|
|
mul.f32 %f742, %f739, 0f3F000000;
|
|
add.f32 %f743, %f741, 0f3F800000;
|
|
selp.f32 %f744, %f743, %f741, %p108;
|
|
selp.f32 %f745, %f742, %f739, %p108;
|
|
add.f32 %f746, %f745, 0fBF800000;
|
|
add.f32 %f747, %f745, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f748, %f747;
|
|
add.f32 %f749, %f746, %f746;
|
|
mul.f32 %f750, %f749, %f748;
|
|
mul.f32 %f751, %f750, %f750;
|
|
mov.f32 %f752, 0f3C4CAF63;
|
|
mov.f32 %f753, 0f3B18F0FE;
|
|
fma.rn.f32 %f754, %f753, %f751, %f752;
|
|
mov.f32 %f755, 0f3DAAAABD;
|
|
fma.rn.f32 %f756, %f754, %f751, %f755;
|
|
mul.rn.f32 %f757, %f756, %f751;
|
|
mul.rn.f32 %f758, %f757, %f750;
|
|
sub.f32 %f759, %f746, %f750;
|
|
add.f32 %f760, %f759, %f759;
|
|
neg.f32 %f761, %f750;
|
|
fma.rn.f32 %f762, %f761, %f746, %f760;
|
|
mul.rn.f32 %f763, %f748, %f762;
|
|
add.f32 %f764, %f758, %f750;
|
|
sub.f32 %f765, %f750, %f764;
|
|
add.f32 %f766, %f758, %f765;
|
|
add.f32 %f767, %f763, %f766;
|
|
add.f32 %f768, %f764, %f767;
|
|
sub.f32 %f769, %f764, %f768;
|
|
add.f32 %f770, %f767, %f769;
|
|
mov.f32 %f771, 0f3F317200;
|
|
mul.rn.f32 %f772, %f744, %f771;
|
|
mov.f32 %f773, 0f35BFBE8E;
|
|
mul.rn.f32 %f774, %f744, %f773;
|
|
add.f32 %f775, %f772, %f768;
|
|
sub.f32 %f776, %f772, %f775;
|
|
add.f32 %f777, %f768, %f776;
|
|
add.f32 %f778, %f770, %f777;
|
|
add.f32 %f779, %f774, %f778;
|
|
add.f32 %f780, %f775, %f779;
|
|
sub.f32 %f781, %f775, %f780;
|
|
add.f32 %f782, %f779, %f781;
|
|
mov.f32 %f783, 0f3EE66666;
|
|
mul.rn.f32 %f784, %f783, %f780;
|
|
neg.f32 %f785, %f784;
|
|
fma.rn.f32 %f786, %f783, %f780, %f785;
|
|
fma.rn.f32 %f787, %f783, %f782, %f786;
|
|
mov.f32 %f788, 0f00000000;
|
|
fma.rn.f32 %f789, %f788, %f780, %f787;
|
|
add.rn.f32 %f790, %f784, %f789;
|
|
neg.f32 %f791, %f790;
|
|
add.rn.f32 %f792, %f784, %f791;
|
|
add.rn.f32 %f793, %f792, %f789;
|
|
mov.b32 %r272, %f790;
|
|
setp.eq.s32 %p109, %r272, 1118925336;
|
|
add.s32 %r273, %r272, -1;
|
|
mov.b32 %f794, %r273;
|
|
add.f32 %f795, %f793, 0f37000000;
|
|
selp.f32 %f133, %f795, %f793, %p109;
|
|
selp.f32 %f796, %f794, %f790, %p109;
|
|
mov.f32 %f797, 0f3FB8AA3B;
|
|
mul.rn.f32 %f798, %f796, %f797;
|
|
cvt.rzi.f32.f32 %f799, %f798;
|
|
abs.f32 %f800, %f799;
|
|
setp.gt.f32 %p110, %f800, 0f42FC0000;
|
|
mov.b32 %r274, %f799;
|
|
and.b32 %r275, %r274, -2147483648;
|
|
or.b32 %r276, %r275, 1123811328;
|
|
mov.b32 %f801, %r276;
|
|
selp.f32 %f802, %f801, %f799, %p110;
|
|
mov.f32 %f803, 0fBF317218;
|
|
fma.rn.f32 %f804, %f802, %f803, %f796;
|
|
mov.f32 %f805, 0f3102E308;
|
|
fma.rn.f32 %f806, %f802, %f805, %f804;
|
|
mul.f32 %f807, %f806, 0f3FB8AA3B;
|
|
add.f32 %f808, %f802, 0f4B40007F;
|
|
mov.b32 %r277, %f808;
|
|
shl.b32 %r278, %r277, 23;
|
|
mov.b32 %f809, %r278;
|
|
ex2.approx.ftz.f32 %f810, %f807;
|
|
mul.f32 %f134, %f810, %f809;
|
|
setp.eq.f32 %p111, %f134, 0f7F800000;
|
|
mov.f32 %f1437, 0f7F800000;
|
|
@%p111 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1437, %f134, %f133, %f134;
|
|
|
|
$L__BB0_89:
|
|
setp.lt.f32 %p112, %f78, 0f00000000;
|
|
and.pred %p5, %p112, %p83;
|
|
setp.eq.f32 %p114, %f78, 0f00000000;
|
|
@%p114 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f815, %f78, %f78;
|
|
selp.f32 %f1439, %f815, 0f00000000, %p83;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.b32 %r279, %f1437;
|
|
xor.b32 %r280, %r279, -2147483648;
|
|
mov.b32 %f811, %r280;
|
|
selp.f32 %f1439, %f811, %f1437, %p5;
|
|
setp.geu.f32 %p115, %f78, 0f00000000;
|
|
@%p115 bra $L__BB0_94;
|
|
|
|
mov.f32 %f812, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f813, %f812;
|
|
setp.eq.f32 %p116, %f813, 0f3EE66666;
|
|
@%p116 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1439, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
abs.f32 %f1377, %f78;
|
|
add.f32 %f816, %f1377, 0f3EE66666;
|
|
mov.b32 %r281, %f816;
|
|
setp.lt.s32 %p118, %r281, 2139095040;
|
|
@%p118 bra $L__BB0_99;
|
|
|
|
abs.f32 %f1378, %f78;
|
|
setp.gtu.f32 %p119, %f1378, 0f7F800000;
|
|
@%p119 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f1439, %f78, 0f3EE66666;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
abs.f32 %f1379, %f78;
|
|
setp.neu.f32 %p120, %f1379, 0f7F800000;
|
|
@%p120 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1439, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
setp.eq.f32 %p121, %f78, 0f3F800000;
|
|
mov.f32 %f818, 0f3F800000;
|
|
selp.f32 %f819, 0f3F800000, %f1439, %p121;
|
|
ld.const.u32 %r282, [params+136];
|
|
mad.lo.s32 %r283, %r282, %r4, %r3;
|
|
cvt.u64.u32 %rd18, %r283;
|
|
min.f32 %f820, %f119, %f818;
|
|
mov.f32 %f821, 0f00000000;
|
|
max.f32 %f143, %f821, %f820;
|
|
min.f32 %f822, %f131, %f818;
|
|
max.f32 %f144, %f821, %f822;
|
|
min.f32 %f823, %f819, %f818;
|
|
max.f32 %f145, %f821, %f823;
|
|
mov.f32 %f827, 0f3ED55555;
|
|
abs.f32 %f147, %f143;
|
|
setp.lt.f32 %p122, %f147, 0f00800000;
|
|
mul.f32 %f829, %f147, 0f4B800000;
|
|
selp.f32 %f830, %f829, %f147, %p122;
|
|
selp.f32 %f831, 0fC3170000, 0fC2FE0000, %p122;
|
|
mov.b32 %r284, %f830;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f832, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f833, %r287;
|
|
add.f32 %f834, %f831, %f833;
|
|
setp.gt.f32 %p123, %f832, 0f3FB504F3;
|
|
mul.f32 %f835, %f832, 0f3F000000;
|
|
add.f32 %f836, %f834, 0f3F800000;
|
|
selp.f32 %f837, %f836, %f834, %p123;
|
|
selp.f32 %f838, %f835, %f832, %p123;
|
|
add.f32 %f839, %f838, 0fBF800000;
|
|
add.f32 %f840, %f838, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f841, %f840;
|
|
add.f32 %f842, %f839, %f839;
|
|
mul.f32 %f843, %f842, %f841;
|
|
mul.f32 %f844, %f843, %f843;
|
|
mov.f32 %f845, 0f3C4CAF63;
|
|
mov.f32 %f846, 0f3B18F0FE;
|
|
fma.rn.f32 %f847, %f846, %f844, %f845;
|
|
mov.f32 %f848, 0f3DAAAABD;
|
|
fma.rn.f32 %f849, %f847, %f844, %f848;
|
|
mul.rn.f32 %f850, %f849, %f844;
|
|
mul.rn.f32 %f851, %f850, %f843;
|
|
sub.f32 %f852, %f839, %f843;
|
|
add.f32 %f853, %f852, %f852;
|
|
neg.f32 %f854, %f843;
|
|
fma.rn.f32 %f855, %f854, %f839, %f853;
|
|
mul.rn.f32 %f856, %f841, %f855;
|
|
add.f32 %f857, %f851, %f843;
|
|
sub.f32 %f858, %f843, %f857;
|
|
add.f32 %f859, %f851, %f858;
|
|
add.f32 %f860, %f856, %f859;
|
|
add.f32 %f861, %f857, %f860;
|
|
sub.f32 %f862, %f857, %f861;
|
|
add.f32 %f863, %f860, %f862;
|
|
mov.f32 %f864, 0f3F317200;
|
|
mul.rn.f32 %f865, %f837, %f864;
|
|
mov.f32 %f866, 0f35BFBE8E;
|
|
mul.rn.f32 %f867, %f837, %f866;
|
|
add.f32 %f868, %f865, %f861;
|
|
sub.f32 %f869, %f865, %f868;
|
|
add.f32 %f870, %f861, %f869;
|
|
add.f32 %f871, %f863, %f870;
|
|
add.f32 %f872, %f867, %f871;
|
|
add.f32 %f873, %f868, %f872;
|
|
sub.f32 %f874, %f868, %f873;
|
|
add.f32 %f875, %f872, %f874;
|
|
mul.rn.f32 %f876, %f827, %f873;
|
|
neg.f32 %f877, %f876;
|
|
fma.rn.f32 %f878, %f827, %f873, %f877;
|
|
fma.rn.f32 %f879, %f827, %f875, %f878;
|
|
fma.rn.f32 %f880, %f821, %f873, %f879;
|
|
add.rn.f32 %f881, %f876, %f880;
|
|
neg.f32 %f882, %f881;
|
|
add.rn.f32 %f883, %f876, %f882;
|
|
add.rn.f32 %f884, %f883, %f880;
|
|
mov.b32 %r288, %f881;
|
|
setp.eq.s32 %p124, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f885, %r289;
|
|
add.f32 %f886, %f884, 0f37000000;
|
|
selp.f32 %f148, %f886, %f884, %p124;
|
|
selp.f32 %f887, %f885, %f881, %p124;
|
|
mov.f32 %f888, 0f3FB8AA3B;
|
|
mul.rn.f32 %f889, %f887, %f888;
|
|
cvt.rzi.f32.f32 %f890, %f889;
|
|
abs.f32 %f891, %f890;
|
|
setp.gt.f32 %p125, %f891, 0f42FC0000;
|
|
mov.b32 %r290, %f890;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f892, %r292;
|
|
selp.f32 %f893, %f892, %f890, %p125;
|
|
mov.f32 %f894, 0fBF317218;
|
|
fma.rn.f32 %f895, %f893, %f894, %f887;
|
|
mov.f32 %f896, 0f3102E308;
|
|
fma.rn.f32 %f897, %f893, %f896, %f895;
|
|
mul.f32 %f898, %f897, 0f3FB8AA3B;
|
|
add.f32 %f899, %f893, 0f4B40007F;
|
|
mov.b32 %r293, %f899;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f900, %r294;
|
|
ex2.approx.ftz.f32 %f901, %f898;
|
|
mul.f32 %f149, %f901, %f900;
|
|
setp.eq.f32 %p126, %f149, 0f7F800000;
|
|
mov.f32 %f1440, 0f7F800000;
|
|
@%p126 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1440, %f149, %f148, %f149;
|
|
|
|
$L__BB0_101:
|
|
mov.f32 %f1340, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1339, %f1340;
|
|
add.f32 %f1338, %f1339, %f1339;
|
|
mov.f32 %f1337, 0f3ED55555;
|
|
sub.f32 %f1336, %f1337, %f1338;
|
|
abs.f32 %f1335, %f1336;
|
|
setp.lt.f32 %p127, %f143, 0f00000000;
|
|
setp.eq.f32 %p128, %f1335, 0f3F800000;
|
|
and.pred %p6, %p127, %p128;
|
|
setp.eq.f32 %p129, %f143, 0f00000000;
|
|
@%p129 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f906, %f143, %f143;
|
|
selp.f32 %f1442, %f906, 0f00000000, %p128;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r295, %f1440;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f902, %r296;
|
|
selp.f32 %f1442, %f902, %f1440, %p6;
|
|
setp.geu.f32 %p130, %f143, 0f00000000;
|
|
@%p130 bra $L__BB0_106;
|
|
|
|
mov.f32 %f903, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f904, %f903;
|
|
setp.eq.f32 %p131, %f904, 0f3ED55555;
|
|
@%p131 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1442, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1343, 0f00000000;
|
|
max.f32 %f1342, %f1343, %f820;
|
|
abs.f32 %f1341, %f1342;
|
|
add.f32 %f907, %f1341, 0f3ED55555;
|
|
mov.b32 %r297, %f907;
|
|
setp.lt.s32 %p133, %r297, 2139095040;
|
|
@%p133 bra $L__BB0_111;
|
|
|
|
mov.f32 %f1346, 0f00000000;
|
|
max.f32 %f1345, %f1346, %f820;
|
|
abs.f32 %f1344, %f1345;
|
|
setp.gtu.f32 %p134, %f1344, 0f7F800000;
|
|
@%p134 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1442, %f143, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
mov.f32 %f1349, 0f00000000;
|
|
max.f32 %f1348, %f1349, %f820;
|
|
abs.f32 %f1347, %f1348;
|
|
setp.neu.f32 %p135, %f1347, 0f7F800000;
|
|
@%p135 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1442, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
abs.f32 %f158, %f144;
|
|
setp.lt.f32 %p136, %f158, 0f00800000;
|
|
mul.f32 %f909, %f158, 0f4B800000;
|
|
selp.f32 %f910, %f909, %f158, %p136;
|
|
selp.f32 %f911, 0fC3170000, 0fC2FE0000, %p136;
|
|
mov.b32 %r298, %f910;
|
|
and.b32 %r299, %r298, 8388607;
|
|
or.b32 %r300, %r299, 1065353216;
|
|
mov.b32 %f912, %r300;
|
|
shr.u32 %r301, %r298, 23;
|
|
cvt.rn.f32.u32 %f913, %r301;
|
|
add.f32 %f914, %f911, %f913;
|
|
setp.gt.f32 %p137, %f912, 0f3FB504F3;
|
|
mul.f32 %f915, %f912, 0f3F000000;
|
|
add.f32 %f916, %f914, 0f3F800000;
|
|
selp.f32 %f917, %f916, %f914, %p137;
|
|
selp.f32 %f918, %f915, %f912, %p137;
|
|
add.f32 %f919, %f918, 0fBF800000;
|
|
add.f32 %f920, %f918, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f921, %f920;
|
|
add.f32 %f922, %f919, %f919;
|
|
mul.f32 %f923, %f922, %f921;
|
|
mul.f32 %f924, %f923, %f923;
|
|
mov.f32 %f925, 0f3C4CAF63;
|
|
mov.f32 %f926, 0f3B18F0FE;
|
|
fma.rn.f32 %f927, %f926, %f924, %f925;
|
|
mov.f32 %f928, 0f3DAAAABD;
|
|
fma.rn.f32 %f929, %f927, %f924, %f928;
|
|
mul.rn.f32 %f930, %f929, %f924;
|
|
mul.rn.f32 %f931, %f930, %f923;
|
|
sub.f32 %f932, %f919, %f923;
|
|
add.f32 %f933, %f932, %f932;
|
|
neg.f32 %f934, %f923;
|
|
fma.rn.f32 %f935, %f934, %f919, %f933;
|
|
mul.rn.f32 %f936, %f921, %f935;
|
|
add.f32 %f937, %f931, %f923;
|
|
sub.f32 %f938, %f923, %f937;
|
|
add.f32 %f939, %f931, %f938;
|
|
add.f32 %f940, %f936, %f939;
|
|
add.f32 %f941, %f937, %f940;
|
|
sub.f32 %f942, %f937, %f941;
|
|
add.f32 %f943, %f940, %f942;
|
|
mov.f32 %f944, 0f3F317200;
|
|
mul.rn.f32 %f945, %f917, %f944;
|
|
mov.f32 %f946, 0f35BFBE8E;
|
|
mul.rn.f32 %f947, %f917, %f946;
|
|
add.f32 %f948, %f945, %f941;
|
|
sub.f32 %f949, %f945, %f948;
|
|
add.f32 %f950, %f941, %f949;
|
|
add.f32 %f951, %f943, %f950;
|
|
add.f32 %f952, %f947, %f951;
|
|
add.f32 %f953, %f948, %f952;
|
|
sub.f32 %f954, %f948, %f953;
|
|
add.f32 %f955, %f952, %f954;
|
|
mov.f32 %f956, 0f3ED55555;
|
|
mul.rn.f32 %f957, %f956, %f953;
|
|
neg.f32 %f958, %f957;
|
|
fma.rn.f32 %f959, %f956, %f953, %f958;
|
|
fma.rn.f32 %f960, %f956, %f955, %f959;
|
|
mov.f32 %f961, 0f00000000;
|
|
fma.rn.f32 %f962, %f961, %f953, %f960;
|
|
add.rn.f32 %f963, %f957, %f962;
|
|
neg.f32 %f964, %f963;
|
|
add.rn.f32 %f965, %f957, %f964;
|
|
add.rn.f32 %f966, %f965, %f962;
|
|
mov.b32 %r302, %f963;
|
|
setp.eq.s32 %p138, %r302, 1118925336;
|
|
add.s32 %r303, %r302, -1;
|
|
mov.b32 %f967, %r303;
|
|
add.f32 %f968, %f966, 0f37000000;
|
|
selp.f32 %f159, %f968, %f966, %p138;
|
|
selp.f32 %f969, %f967, %f963, %p138;
|
|
mov.f32 %f970, 0f3FB8AA3B;
|
|
mul.rn.f32 %f971, %f969, %f970;
|
|
cvt.rzi.f32.f32 %f972, %f971;
|
|
abs.f32 %f973, %f972;
|
|
setp.gt.f32 %p139, %f973, 0f42FC0000;
|
|
mov.b32 %r304, %f972;
|
|
and.b32 %r305, %r304, -2147483648;
|
|
or.b32 %r306, %r305, 1123811328;
|
|
mov.b32 %f974, %r306;
|
|
selp.f32 %f975, %f974, %f972, %p139;
|
|
mov.f32 %f976, 0fBF317218;
|
|
fma.rn.f32 %f977, %f975, %f976, %f969;
|
|
mov.f32 %f978, 0f3102E308;
|
|
fma.rn.f32 %f979, %f975, %f978, %f977;
|
|
mul.f32 %f980, %f979, 0f3FB8AA3B;
|
|
add.f32 %f981, %f975, 0f4B40007F;
|
|
mov.b32 %r307, %f981;
|
|
shl.b32 %r308, %r307, 23;
|
|
mov.b32 %f982, %r308;
|
|
ex2.approx.ftz.f32 %f983, %f980;
|
|
mul.f32 %f160, %f983, %f982;
|
|
setp.eq.f32 %p140, %f160, 0f7F800000;
|
|
mov.f32 %f1443, 0f7F800000;
|
|
@%p140 bra $L__BB0_113;
|
|
|
|
fma.rn.f32 %f1443, %f160, %f159, %f160;
|
|
|
|
$L__BB0_113:
|
|
setp.lt.f32 %p141, %f144, 0f00000000;
|
|
and.pred %p7, %p141, %p128;
|
|
setp.eq.f32 %p143, %f144, 0f00000000;
|
|
@%p143 bra $L__BB0_117;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f988, %f144, %f144;
|
|
selp.f32 %f1445, %f988, 0f00000000, %p128;
|
|
bra.uni $L__BB0_118;
|
|
|
|
$L__BB0_114:
|
|
mov.b32 %r309, %f1443;
|
|
xor.b32 %r310, %r309, -2147483648;
|
|
mov.b32 %f984, %r310;
|
|
selp.f32 %f1445, %f984, %f1443, %p7;
|
|
setp.geu.f32 %p144, %f144, 0f00000000;
|
|
@%p144 bra $L__BB0_118;
|
|
|
|
mov.f32 %f985, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f986, %f985;
|
|
setp.eq.f32 %p145, %f986, 0f3ED55555;
|
|
@%p145 bra $L__BB0_118;
|
|
|
|
mov.f32 %f1445, 0f7FFFFFFF;
|
|
|
|
$L__BB0_118:
|
|
mov.f32 %f1382, 0f00000000;
|
|
max.f32 %f1381, %f1382, %f822;
|
|
abs.f32 %f1380, %f1381;
|
|
add.f32 %f989, %f1380, 0f3ED55555;
|
|
mov.b32 %r311, %f989;
|
|
setp.lt.s32 %p147, %r311, 2139095040;
|
|
@%p147 bra $L__BB0_123;
|
|
|
|
mov.f32 %f1385, 0f00000000;
|
|
max.f32 %f1384, %f1385, %f822;
|
|
abs.f32 %f1383, %f1384;
|
|
setp.gtu.f32 %p148, %f1383, 0f7F800000;
|
|
@%p148 bra $L__BB0_122;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1445, %f144, 0f3ED55555;
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_120:
|
|
mov.f32 %f1388, 0f00000000;
|
|
max.f32 %f1387, %f1388, %f822;
|
|
abs.f32 %f1386, %f1387;
|
|
setp.neu.f32 %p149, %f1386, 0f7F800000;
|
|
@%p149 bra $L__BB0_123;
|
|
|
|
selp.f32 %f1445, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_123:
|
|
abs.f32 %f169, %f145;
|
|
setp.lt.f32 %p150, %f169, 0f00800000;
|
|
mul.f32 %f991, %f169, 0f4B800000;
|
|
selp.f32 %f992, %f991, %f169, %p150;
|
|
selp.f32 %f993, 0fC3170000, 0fC2FE0000, %p150;
|
|
mov.b32 %r312, %f992;
|
|
and.b32 %r313, %r312, 8388607;
|
|
or.b32 %r314, %r313, 1065353216;
|
|
mov.b32 %f994, %r314;
|
|
shr.u32 %r315, %r312, 23;
|
|
cvt.rn.f32.u32 %f995, %r315;
|
|
add.f32 %f996, %f993, %f995;
|
|
setp.gt.f32 %p151, %f994, 0f3FB504F3;
|
|
mul.f32 %f997, %f994, 0f3F000000;
|
|
add.f32 %f998, %f996, 0f3F800000;
|
|
selp.f32 %f999, %f998, %f996, %p151;
|
|
selp.f32 %f1000, %f997, %f994, %p151;
|
|
add.f32 %f1001, %f1000, 0fBF800000;
|
|
add.f32 %f1002, %f1000, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1003, %f1002;
|
|
add.f32 %f1004, %f1001, %f1001;
|
|
mul.f32 %f1005, %f1004, %f1003;
|
|
mul.f32 %f1006, %f1005, %f1005;
|
|
mov.f32 %f1007, 0f3C4CAF63;
|
|
mov.f32 %f1008, 0f3B18F0FE;
|
|
fma.rn.f32 %f1009, %f1008, %f1006, %f1007;
|
|
mov.f32 %f1010, 0f3DAAAABD;
|
|
fma.rn.f32 %f1011, %f1009, %f1006, %f1010;
|
|
mul.rn.f32 %f1012, %f1011, %f1006;
|
|
mul.rn.f32 %f1013, %f1012, %f1005;
|
|
sub.f32 %f1014, %f1001, %f1005;
|
|
add.f32 %f1015, %f1014, %f1014;
|
|
neg.f32 %f1016, %f1005;
|
|
fma.rn.f32 %f1017, %f1016, %f1001, %f1015;
|
|
mul.rn.f32 %f1018, %f1003, %f1017;
|
|
add.f32 %f1019, %f1013, %f1005;
|
|
sub.f32 %f1020, %f1005, %f1019;
|
|
add.f32 %f1021, %f1013, %f1020;
|
|
add.f32 %f1022, %f1018, %f1021;
|
|
add.f32 %f1023, %f1019, %f1022;
|
|
sub.f32 %f1024, %f1019, %f1023;
|
|
add.f32 %f1025, %f1022, %f1024;
|
|
mov.f32 %f1026, 0f3F317200;
|
|
mul.rn.f32 %f1027, %f999, %f1026;
|
|
mov.f32 %f1028, 0f35BFBE8E;
|
|
mul.rn.f32 %f1029, %f999, %f1028;
|
|
add.f32 %f1030, %f1027, %f1023;
|
|
sub.f32 %f1031, %f1027, %f1030;
|
|
add.f32 %f1032, %f1023, %f1031;
|
|
add.f32 %f1033, %f1025, %f1032;
|
|
add.f32 %f1034, %f1029, %f1033;
|
|
add.f32 %f1035, %f1030, %f1034;
|
|
sub.f32 %f1036, %f1030, %f1035;
|
|
add.f32 %f1037, %f1034, %f1036;
|
|
mov.f32 %f1038, 0f3ED55555;
|
|
mul.rn.f32 %f1039, %f1038, %f1035;
|
|
neg.f32 %f1040, %f1039;
|
|
fma.rn.f32 %f1041, %f1038, %f1035, %f1040;
|
|
fma.rn.f32 %f1042, %f1038, %f1037, %f1041;
|
|
mov.f32 %f1043, 0f00000000;
|
|
fma.rn.f32 %f1044, %f1043, %f1035, %f1042;
|
|
add.rn.f32 %f1045, %f1039, %f1044;
|
|
neg.f32 %f1046, %f1045;
|
|
add.rn.f32 %f1047, %f1039, %f1046;
|
|
add.rn.f32 %f1048, %f1047, %f1044;
|
|
mov.b32 %r316, %f1045;
|
|
setp.eq.s32 %p152, %r316, 1118925336;
|
|
add.s32 %r317, %r316, -1;
|
|
mov.b32 %f1049, %r317;
|
|
add.f32 %f1050, %f1048, 0f37000000;
|
|
selp.f32 %f170, %f1050, %f1048, %p152;
|
|
selp.f32 %f1051, %f1049, %f1045, %p152;
|
|
mov.f32 %f1052, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1053, %f1051, %f1052;
|
|
cvt.rzi.f32.f32 %f1054, %f1053;
|
|
abs.f32 %f1055, %f1054;
|
|
setp.gt.f32 %p153, %f1055, 0f42FC0000;
|
|
mov.b32 %r318, %f1054;
|
|
and.b32 %r319, %r318, -2147483648;
|
|
or.b32 %r320, %r319, 1123811328;
|
|
mov.b32 %f1056, %r320;
|
|
selp.f32 %f1057, %f1056, %f1054, %p153;
|
|
mov.f32 %f1058, 0fBF317218;
|
|
fma.rn.f32 %f1059, %f1057, %f1058, %f1051;
|
|
mov.f32 %f1060, 0f3102E308;
|
|
fma.rn.f32 %f1061, %f1057, %f1060, %f1059;
|
|
mul.f32 %f1062, %f1061, 0f3FB8AA3B;
|
|
add.f32 %f1063, %f1057, 0f4B40007F;
|
|
mov.b32 %r321, %f1063;
|
|
shl.b32 %r322, %r321, 23;
|
|
mov.b32 %f1064, %r322;
|
|
ex2.approx.ftz.f32 %f1065, %f1062;
|
|
mul.f32 %f171, %f1065, %f1064;
|
|
setp.eq.f32 %p154, %f171, 0f7F800000;
|
|
mov.f32 %f1446, 0f7F800000;
|
|
@%p154 bra $L__BB0_125;
|
|
|
|
fma.rn.f32 %f1446, %f171, %f170, %f171;
|
|
|
|
$L__BB0_125:
|
|
setp.lt.f32 %p155, %f145, 0f00000000;
|
|
and.pred %p8, %p155, %p128;
|
|
setp.eq.f32 %p157, %f145, 0f00000000;
|
|
@%p157 bra $L__BB0_129;
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_129:
|
|
add.f32 %f1070, %f145, %f145;
|
|
selp.f32 %f1448, %f1070, 0f00000000, %p128;
|
|
bra.uni $L__BB0_130;
|
|
|
|
$L__BB0_126:
|
|
mov.b32 %r323, %f1446;
|
|
xor.b32 %r324, %r323, -2147483648;
|
|
mov.b32 %f1066, %r324;
|
|
selp.f32 %f1448, %f1066, %f1446, %p8;
|
|
setp.geu.f32 %p158, %f145, 0f00000000;
|
|
@%p158 bra $L__BB0_130;
|
|
|
|
mov.f32 %f1067, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1068, %f1067;
|
|
setp.eq.f32 %p159, %f1068, 0f3ED55555;
|
|
@%p159 bra $L__BB0_130;
|
|
|
|
mov.f32 %f1448, 0f7FFFFFFF;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f1391, 0f00000000;
|
|
max.f32 %f1390, %f1391, %f823;
|
|
abs.f32 %f1389, %f1390;
|
|
add.f32 %f1071, %f1389, 0f3ED55555;
|
|
mov.b32 %r325, %f1071;
|
|
setp.lt.s32 %p161, %r325, 2139095040;
|
|
@%p161 bra $L__BB0_135;
|
|
|
|
mov.f32 %f1394, 0f00000000;
|
|
max.f32 %f1393, %f1394, %f823;
|
|
abs.f32 %f1392, %f1393;
|
|
setp.gtu.f32 %p162, %f1392, 0f7F800000;
|
|
@%p162 bra $L__BB0_134;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_134:
|
|
add.f32 %f1448, %f145, 0f3ED55555;
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_132:
|
|
mov.f32 %f1397, 0f00000000;
|
|
max.f32 %f1396, %f1397, %f823;
|
|
abs.f32 %f1395, %f1396;
|
|
setp.neu.f32 %p163, %f1395, 0f7F800000;
|
|
@%p163 bra $L__BB0_135;
|
|
|
|
selp.f32 %f1448, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_135:
|
|
ld.const.u64 %rd107, [params+144];
|
|
cvta.to.global.u64 %rd106, %rd107;
|
|
fma.rn.f32 %f1072, %f1442, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p164, %f143, 0f3F800000;
|
|
mov.f32 %f1073, 0f3F800000;
|
|
selp.f32 %f1074, 0f3F7FFFFF, %f1072, %p164;
|
|
mul.f32 %f1075, %f143, 0f414EB852;
|
|
setp.lt.f32 %p165, %f143, 0f3B4D2E1C;
|
|
selp.f32 %f1076, %f1075, %f1074, %p165;
|
|
fma.rn.f32 %f1077, %f1445, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p166, %f144, 0f3F800000;
|
|
selp.f32 %f1078, 0f3F7FFFFF, %f1077, %p166;
|
|
mul.f32 %f1079, %f144, 0f414EB852;
|
|
setp.lt.f32 %p167, %f144, 0f3B4D2E1C;
|
|
selp.f32 %f1080, %f1079, %f1078, %p167;
|
|
fma.rn.f32 %f1081, %f1448, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p168, %f145, 0f3F800000;
|
|
selp.f32 %f1082, 0f3F7FFFFF, %f1081, %p168;
|
|
mul.f32 %f1083, %f145, 0f414EB852;
|
|
setp.lt.f32 %p169, %f145, 0f3B4D2E1C;
|
|
selp.f32 %f1084, %f1083, %f1082, %p169;
|
|
min.f32 %f1085, %f1076, %f1073;
|
|
mov.f32 %f1086, 0f00000000;
|
|
max.f32 %f1087, %f1086, %f1085;
|
|
mul.f32 %f1088, %f1087, 0f43800000;
|
|
cvt.rzi.u32.f32 %r326, %f1088;
|
|
min.u32 %r327, %r326, 255;
|
|
min.f32 %f1089, %f1080, %f1073;
|
|
max.f32 %f1090, %f1086, %f1089;
|
|
mul.f32 %f1091, %f1090, 0f43800000;
|
|
cvt.rzi.u32.f32 %r328, %f1091;
|
|
min.u32 %r329, %r328, 255;
|
|
min.f32 %f1092, %f1084, %f1073;
|
|
max.f32 %f1093, %f1086, %f1092;
|
|
mul.f32 %f1094, %f1093, 0f43800000;
|
|
cvt.rzi.u32.f32 %r330, %f1094;
|
|
min.u32 %r331, %r330, 255;
|
|
shl.b64 %rd69, %rd18, 2;
|
|
add.s64 %rd70, %rd106, %rd69;
|
|
cvt.u16.u32 %rs28, %r331;
|
|
cvt.u16.u32 %rs29, %r329;
|
|
cvt.u16.u32 %rs30, %r327;
|
|
mov.u16 %rs31, 255;
|
|
st.global.v4.u8 [%rd70], {%rs30, %rs29, %rs28, %rs31};
|
|
|
|
$L__BB0_136:
|
|
ld.const.u32 %r361, [params+104];
|
|
and.b32 %r332, %r361, 4;
|
|
setp.eq.s32 %p170, %r332, 0;
|
|
@%p170 bra $L__BB0_140;
|
|
|
|
ld.const.u32 %r333, [params+108];
|
|
setp.eq.s32 %p171, %r333, 0;
|
|
ld.const.u64 %rd71, [params+224];
|
|
cvta.to.global.u64 %rd72, %rd71;
|
|
ld.const.u32 %r334, [params+216];
|
|
mad.lo.s32 %r335, %r334, %r4, %r3;
|
|
mul.wide.u32 %rd73, %r335, 8;
|
|
add.s64 %rd19, %rd72, %rd73;
|
|
@%p171 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs39, %rs40, %rs41, %rs42}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1095, %rs39;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1096, %rs40;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1097, %rs41;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1098, %f76, %f1095;
|
|
add.f32 %f1099, %f77, %f1096;
|
|
add.f32 %f1100, %f78, %f1097;
|
|
mov.f32 %f1101, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1100;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1099;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f1098;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1101;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs35, %rs36, %rs37, %rs38};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1105, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f1105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f78;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f77;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f76;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs43, %rs44, %rs45, %rs46};
|
|
|
|
$L__BB0_140:
|
|
ld.const.u64 %rd74, [params+464];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r336, [params+456];
|
|
mad.lo.s32 %r337, %r336, %r54, %r53;
|
|
mul.wide.u32 %rd76, %r337, 4;
|
|
add.s64 %rd20, %rd75, %rd76;
|
|
ld.global.v2.u8 {%rs47, %rs179}, [%rd20];
|
|
or.b16 %rs49, %rs47, %rs179;
|
|
and.b16 %rs50, %rs49, 255;
|
|
setp.eq.s16 %p172, %rs50, 0;
|
|
@%p172 bra $L__BB0_142;
|
|
|
|
ld.global.u8 %rs177, [%rd20+2];
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
ld.global.u8 %rs177, [%rd20+2];
|
|
setp.eq.s16 %p173, %rs177, 0;
|
|
mov.f32 %f1449, 0f00000000;
|
|
mov.u16 %rs179, 0;
|
|
mov.u16 %rs180, %rs179;
|
|
mov.f32 %f1450, %f1449;
|
|
mov.f32 %f1451, %f1449;
|
|
@%p173 bra $L__BB0_144;
|
|
|
|
$L__BB0_143:
|
|
mov.u16 %rs180, %rs179;
|
|
cvt.rn.f32.u16 %f1109, %rs47;
|
|
div.rn.f32 %f1110, %f1109, 0f437F0000;
|
|
fma.rn.f32 %f1111, %f1110, 0f40000000, 0fBF800000;
|
|
and.b16 %rs55, %rs180, 255;
|
|
cvt.rn.f32.u16 %f1112, %rs55;
|
|
div.rn.f32 %f1113, %f1112, 0f437F0000;
|
|
fma.rn.f32 %f1114, %f1113, 0f40000000, 0fBF800000;
|
|
cvt.rn.f32.u16 %f1115, %rs177;
|
|
div.rn.f32 %f1116, %f1115, 0f437F0000;
|
|
fma.rn.f32 %f1117, %f1116, 0f40000000, 0fBF800000;
|
|
mul.f32 %f1118, %f1114, %f1114;
|
|
fma.rn.f32 %f1119, %f1111, %f1111, %f1118;
|
|
fma.rn.f32 %f1120, %f1117, %f1117, %f1119;
|
|
sqrt.rn.f32 %f1121, %f1120;
|
|
rcp.rn.f32 %f1122, %f1121;
|
|
mul.f32 %f1451, %f1122, %f1117;
|
|
mul.f32 %f1450, %f1122, %f1114;
|
|
mul.f32 %f1449, %f1111, %f1122;
|
|
mov.u16 %rs179, %rs177;
|
|
|
|
$L__BB0_144:
|
|
mul.f32 %f1126, %f1405, %f1451;
|
|
mul.f32 %f1127, %f1406, %f1450;
|
|
sub.f32 %f1128, %f1126, %f1127;
|
|
mul.f32 %f1129, %f1406, %f1449;
|
|
mul.f32 %f1130, %f1404, %f1451;
|
|
sub.f32 %f1131, %f1129, %f1130;
|
|
mul.f32 %f1132, %f1404, %f1450;
|
|
mul.f32 %f1133, %f1405, %f1449;
|
|
sub.f32 %f1134, %f1132, %f1133;
|
|
ld.global.u8 %rs57, [%rd20+3];
|
|
setp.eq.s16 %p174, %rs57, 0;
|
|
selp.f32 %f186, 0fBF800000, 0f3F800000, %p174;
|
|
mul.f32 %f1135, %f1128, %f186;
|
|
mul.f32 %f1136, %f1131, %f186;
|
|
mul.f32 %f1137, %f1134, %f186;
|
|
mul.f32 %f1138, %f1135, 0f00000000;
|
|
mul.f32 %f1139, %f1136, 0f00000000;
|
|
mul.f32 %f1140, %f1137, 0f00000000;
|
|
fma.rn.f32 %f1141, %f1449, 0f3F5105EC, %f1138;
|
|
fma.rn.f32 %f1142, %f1450, 0f3F5105EC, %f1139;
|
|
fma.rn.f32 %f1143, %f1451, 0f3F5105EC, %f1140;
|
|
mul.f32 %f187, %f1404, 0f3F13CD3A;
|
|
add.f32 %f188, %f187, %f1141;
|
|
mul.f32 %f189, %f1405, 0f3F13CD3A;
|
|
add.f32 %f190, %f189, %f1142;
|
|
mul.f32 %f191, %f1406, 0f3F13CD3A;
|
|
add.f32 %f192, %f191, %f1143;
|
|
or.b16 %rs58, %rs47, %rs180;
|
|
or.b16 %rs15, %rs58, %rs179;
|
|
and.b16 %rs59, %rs15, 255;
|
|
setp.eq.s16 %p175, %rs59, 0;
|
|
mov.f32 %f1455, 0f00000000;
|
|
mov.f32 %f1452, %f1455;
|
|
mov.f32 %f1453, %f1455;
|
|
mov.f32 %f1454, %f1455;
|
|
@%p175 bra $L__BB0_146;
|
|
|
|
cvt.rn.f32.u16 %f1144, %rs47;
|
|
div.rn.f32 %f1145, %f1144, 0f437F0000;
|
|
fma.rn.f32 %f1146, %f1145, 0f40000000, 0fBF800000;
|
|
and.b16 %rs61, %rs180, 255;
|
|
cvt.rn.f32.u16 %f1147, %rs61;
|
|
div.rn.f32 %f1148, %f1147, 0f437F0000;
|
|
fma.rn.f32 %f1149, %f1148, 0f40000000, 0fBF800000;
|
|
and.b16 %rs62, %rs179, 255;
|
|
cvt.rn.f32.u16 %f1150, %rs62;
|
|
div.rn.f32 %f1151, %f1150, 0f437F0000;
|
|
fma.rn.f32 %f1152, %f1151, 0f40000000, 0fBF800000;
|
|
mul.f32 %f1153, %f1149, %f1149;
|
|
fma.rn.f32 %f1154, %f1146, %f1146, %f1153;
|
|
fma.rn.f32 %f1155, %f1152, %f1152, %f1154;
|
|
sqrt.rn.f32 %f1156, %f1155;
|
|
rcp.rn.f32 %f1157, %f1156;
|
|
mul.f32 %f1454, %f1157, %f1152;
|
|
mul.f32 %f1453, %f1157, %f1149;
|
|
mul.f32 %f1452, %f1146, %f1157;
|
|
|
|
$L__BB0_146:
|
|
mul.f32 %f1161, %f1405, %f1454;
|
|
mul.f32 %f1162, %f1406, %f1453;
|
|
sub.f32 %f1163, %f1161, %f1162;
|
|
mul.f32 %f1164, %f1406, %f1452;
|
|
mul.f32 %f1165, %f1404, %f1454;
|
|
sub.f32 %f1166, %f1164, %f1165;
|
|
mul.f32 %f1167, %f1404, %f1453;
|
|
mul.f32 %f1168, %f1405, %f1452;
|
|
sub.f32 %f1169, %f1167, %f1168;
|
|
mul.f32 %f1170, %f1163, %f186;
|
|
mul.f32 %f1171, %f1166, %f186;
|
|
mul.f32 %f1172, %f1169, %f186;
|
|
mul.f32 %f1173, %f1452, 0f3ED105EC;
|
|
mul.f32 %f1174, %f1453, 0f3ED105EC;
|
|
mul.f32 %f1175, %f1454, 0f3ED105EC;
|
|
mul.f32 %f1176, %f1170, 0f3F3504F3;
|
|
mul.f32 %f1177, %f1171, 0f3F3504F3;
|
|
mul.f32 %f1178, %f1172, 0f3F3504F3;
|
|
sub.f32 %f1179, %f1176, %f1173;
|
|
sub.f32 %f1180, %f1177, %f1174;
|
|
sub.f32 %f1181, %f1178, %f1175;
|
|
add.f32 %f199, %f187, %f1179;
|
|
add.f32 %f200, %f189, %f1180;
|
|
add.f32 %f201, %f191, %f1181;
|
|
mov.f32 %f1456, %f1455;
|
|
mov.f32 %f1457, %f1455;
|
|
@%p175 bra $L__BB0_148;
|
|
|
|
cvt.rn.f32.u16 %f1182, %rs47;
|
|
div.rn.f32 %f1183, %f1182, 0f437F0000;
|
|
fma.rn.f32 %f1184, %f1183, 0f40000000, 0fBF800000;
|
|
and.b16 %rs65, %rs180, 255;
|
|
cvt.rn.f32.u16 %f1185, %rs65;
|
|
div.rn.f32 %f1186, %f1185, 0f437F0000;
|
|
fma.rn.f32 %f1187, %f1186, 0f40000000, 0fBF800000;
|
|
and.b16 %rs66, %rs179, 255;
|
|
cvt.rn.f32.u16 %f1188, %rs66;
|
|
div.rn.f32 %f1189, %f1188, 0f437F0000;
|
|
fma.rn.f32 %f1190, %f1189, 0f40000000, 0fBF800000;
|
|
mul.f32 %f1191, %f1187, %f1187;
|
|
fma.rn.f32 %f1192, %f1184, %f1184, %f1191;
|
|
fma.rn.f32 %f1193, %f1190, %f1190, %f1192;
|
|
sqrt.rn.f32 %f1194, %f1193;
|
|
rcp.rn.f32 %f1195, %f1194;
|
|
mul.f32 %f1457, %f1195, %f1190;
|
|
mul.f32 %f1456, %f1195, %f1187;
|
|
mul.f32 %f1455, %f1184, %f1195;
|
|
|
|
$L__BB0_148:
|
|
mul.f32 %f1196, %f1405, %f1457;
|
|
mul.f32 %f1197, %f1406, %f1456;
|
|
sub.f32 %f1198, %f1196, %f1197;
|
|
mul.f32 %f1199, %f1406, %f1455;
|
|
mul.f32 %f1200, %f1404, %f1457;
|
|
sub.f32 %f1201, %f1199, %f1200;
|
|
mul.f32 %f1202, %f1404, %f1456;
|
|
mul.f32 %f1203, %f1405, %f1455;
|
|
sub.f32 %f1204, %f1202, %f1203;
|
|
mul.f32 %f1205, %f1198, %f186;
|
|
mul.f32 %f1206, %f1201, %f186;
|
|
mul.f32 %f1207, %f1204, %f186;
|
|
mul.f32 %f1208, %f1455, 0f3ED105EC;
|
|
mul.f32 %f1209, %f1456, 0f3ED105EC;
|
|
mul.f32 %f1210, %f1457, 0f3ED105EC;
|
|
mul.f32 %f1211, %f1205, 0fBF3504F3;
|
|
mul.f32 %f1212, %f1206, 0fBF3504F3;
|
|
mul.f32 %f1213, %f1207, 0fBF3504F3;
|
|
sub.f32 %f1214, %f1211, %f1208;
|
|
sub.f32 %f1215, %f1212, %f1209;
|
|
sub.f32 %f1216, %f1213, %f1210;
|
|
add.f32 %f1217, %f187, %f1214;
|
|
add.f32 %f1218, %f189, %f1215;
|
|
add.f32 %f1219, %f191, %f1216;
|
|
mul.f32 %f1220, %f190, %f238;
|
|
neg.f32 %f1221, %f1220;
|
|
mul.f32 %f1222, %f188, %f237;
|
|
sub.f32 %f1223, %f1221, %f1222;
|
|
mul.f32 %f1224, %f192, %f239;
|
|
sub.f32 %f1225, %f1223, %f1224;
|
|
cvt.sat.f32.f32 %f1226, %f1225;
|
|
mul.f32 %f1227, %f92, %f1226;
|
|
mul.f32 %f1228, %f93, %f1226;
|
|
mul.f32 %f1229, %f94, %f1226;
|
|
mul.f32 %f1230, %f200, %f238;
|
|
neg.f32 %f1231, %f1230;
|
|
mul.f32 %f1232, %f199, %f237;
|
|
sub.f32 %f1233, %f1231, %f1232;
|
|
mul.f32 %f1234, %f201, %f239;
|
|
sub.f32 %f1235, %f1233, %f1234;
|
|
cvt.sat.f32.f32 %f1236, %f1235;
|
|
mul.f32 %f1237, %f92, %f1236;
|
|
mul.f32 %f1238, %f93, %f1236;
|
|
mul.f32 %f1239, %f94, %f1236;
|
|
mul.f32 %f1240, %f1217, %f237;
|
|
mul.f32 %f1241, %f1218, %f238;
|
|
neg.f32 %f1242, %f1241;
|
|
sub.f32 %f1243, %f1242, %f1240;
|
|
mul.f32 %f1244, %f1219, %f239;
|
|
sub.f32 %f1245, %f1243, %f1244;
|
|
cvt.sat.f32.f32 %f1246, %f1245;
|
|
mul.f32 %f1247, %f92, %f1246;
|
|
mul.f32 %f1248, %f93, %f1246;
|
|
mul.f32 %f1249, %f94, %f1246;
|
|
add.f32 %f1250, %f1227, %f1237;
|
|
add.f32 %f1251, %f1228, %f1238;
|
|
add.f32 %f1252, %f1229, %f1239;
|
|
add.f32 %f1253, %f1250, %f1247;
|
|
add.f32 %f1254, %f1251, %f1248;
|
|
add.f32 %f1255, %f1252, %f1249;
|
|
mul.f32 %f1256, %f1253, 0f3F13CD3A;
|
|
mul.f32 %f1257, %f1254, 0f3F13CD3A;
|
|
mul.f32 %f1258, %f1255, 0f3F13CD3A;
|
|
div.rn.f32 %f1259, %f76, %f1256;
|
|
div.rn.f32 %f1260, %f77, %f1257;
|
|
div.rn.f32 %f1261, %f78, %f1258;
|
|
setp.eq.f32 %p177, %f76, 0f00000000;
|
|
selp.f32 %f1262, 0f00000000, %f1259, %p177;
|
|
setp.eq.f32 %p178, %f77, 0f00000000;
|
|
selp.f32 %f1263, 0f00000000, %f1260, %p178;
|
|
setp.eq.f32 %p179, %f78, 0f00000000;
|
|
selp.f32 %f1264, 0f00000000, %f1261, %p179;
|
|
mul.f32 %f208, %f1227, %f1262;
|
|
mul.f32 %f209, %f1228, %f1263;
|
|
mul.f32 %f210, %f1229, %f1264;
|
|
mul.f32 %f211, %f1237, %f1262;
|
|
mul.f32 %f212, %f1238, %f1263;
|
|
mul.f32 %f213, %f1239, %f1264;
|
|
mul.f32 %f214, %f1247, %f1262;
|
|
mul.f32 %f215, %f1248, %f1263;
|
|
mul.f32 %f216, %f1249, %f1264;
|
|
ld.const.u32 %r49, [params+108];
|
|
setp.eq.s32 %p180, %r49, 0;
|
|
ld.const.u64 %rd77, [params+256];
|
|
cvta.to.global.u64 %rd78, %rd77;
|
|
ld.const.u32 %r338, [params+248];
|
|
mad.lo.s32 %r339, %r338, %r4, %r3;
|
|
mul.wide.u32 %rd79, %r339, 8;
|
|
add.s64 %rd21, %rd78, %rd79;
|
|
@%p180 bra $L__BB0_150;
|
|
|
|
ld.global.v4.u16 {%rs74, %rs75, %rs76, %rs77}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1265, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1266, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1267, %rs76;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1268, %f208, %f1265;
|
|
add.f32 %f1269, %f209, %f1266;
|
|
add.f32 %f1270, %f210, %f1267;
|
|
mov.f32 %f1271, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1270;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1269;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1268;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1271;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs70, %rs71, %rs72, %rs73};
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_150:
|
|
mov.f32 %f1275, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1275;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f210;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f209;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f208;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs78, %rs79, %rs80, %rs81};
|
|
|
|
$L__BB0_151:
|
|
ld.const.u64 %rd80, [params+272];
|
|
cvta.to.global.u64 %rd81, %rd80;
|
|
ld.const.u32 %r340, [params+264];
|
|
mad.lo.s32 %r341, %r340, %r4, %r3;
|
|
mul.wide.u32 %rd82, %r341, 8;
|
|
add.s64 %rd22, %rd81, %rd82;
|
|
@%p180 bra $L__BB0_153;
|
|
|
|
ld.global.v4.u16 {%rs89, %rs90, %rs91, %rs92}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1276, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1277, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1278, %rs91;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1279, %f211, %f1276;
|
|
add.f32 %f1280, %f212, %f1277;
|
|
add.f32 %f1281, %f213, %f1278;
|
|
mov.f32 %f1282, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1281;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1280;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1279;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1282;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs85, %rs86, %rs87, %rs88};
|
|
bra.uni $L__BB0_154;
|
|
|
|
$L__BB0_153:
|
|
mov.f32 %f1286, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1286;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f213;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f211;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs93, %rs94, %rs95, %rs96};
|
|
|
|
$L__BB0_154:
|
|
ld.const.u64 %rd83, [params+288];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r342, [params+280];
|
|
mad.lo.s32 %r343, %r342, %r4, %r3;
|
|
mul.wide.u32 %rd85, %r343, 8;
|
|
add.s64 %rd23, %rd84, %rd85;
|
|
@%p180 bra $L__BB0_156;
|
|
|
|
ld.global.v4.u16 {%rs104, %rs105, %rs106, %rs107}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1287, %rs104;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1288, %rs105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1289, %rs106;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1290, %f214, %f1287;
|
|
add.f32 %f1291, %f215, %f1288;
|
|
add.f32 %f1292, %f216, %f1289;
|
|
mov.f32 %f1293, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1292;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs101, %f1291;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1290;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs103, %f1293;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs100, %rs101, %rs102, %rs103};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_156:
|
|
mov.f32 %f1297, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f1297;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f216;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs109, %f215;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f214;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs108, %rs109, %rs110, %rs111};
|
|
|
|
$L__BB0_174:
|
|
ret;
|
|
|
|
}
|
|
|