231 lines
6.2 KiB
Plaintext
231 lines
6.2 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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.const .align 16 .b8 params[1184];
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.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
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.param .b32 __direct_callable__oxMain_param_0,
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.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
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)
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{
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.reg .pred %p<6>;
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.reg .b16 %rs<57>;
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.reg .f32 %f<114>;
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.reg .b32 %r<41>;
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.reg .b64 %rd<49>;
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ld.param.u32 %r6, [__direct_callable__oxMain_param_0];
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ld.param.f32 %f29, [__direct_callable__oxMain_param_1+4];
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ld.param.f32 %f28, [__direct_callable__oxMain_param_1];
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// begin inline asm
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call (%r7), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r8), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd4, [params+72];
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cvta.to.global.u64 %rd5, %rd4;
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mul.wide.s32 %rd6, %r6, 4;
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add.s64 %rd7, %rd5, %rd6;
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ld.global.u32 %r3, [%rd7];
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setp.eq.s32 %p1, %r3, 0;
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@%p1 bra $L__BB0_2;
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ld.const.u64 %rd8, [params+480];
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cvta.to.global.u64 %rd9, %rd8;
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ld.const.u32 %r10, [params+472];
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mad.lo.s32 %r11, %r10, %r8, %r7;
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cvt.u64.u32 %rd10, %r11;
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add.s64 %rd11, %rd9, %rd10;
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ld.global.u8 %r12, [%rd11];
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mov.u32 %r13, 1;
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shl.b32 %r14, %r13, %r12;
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and.b32 %r15, %r14, %r3;
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setp.eq.s32 %p2, %r15, 0;
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mov.f32 %f110, 0f00000000;
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mov.f32 %f111, %f110;
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mov.f32 %f112, %f110;
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mov.f32 %f113, %f110;
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@%p2 bra $L__BB0_8;
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$L__BB0_2:
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ld.const.u64 %rd12, [params+24];
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cvta.to.global.u64 %rd13, %rd12;
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mul.wide.u32 %rd14, %r6, 12;
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add.s64 %rd15, %rd13, %rd14;
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ld.global.s32 %rd1, [%rd15];
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ld.global.s32 %rd2, [%rd15+4];
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ld.global.s32 %rd3, [%rd15+8];
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ld.const.u32 %r4, [params+32];
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setp.gt.u32 %p3, %r4, %r6;
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@%p3 bra $L__BB0_6;
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bra.uni $L__BB0_3;
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$L__BB0_6:
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mov.f32 %f113, 0f3F800000;
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sub.f32 %f82, %f113, %f28;
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sub.f32 %f108, %f82, %f29;
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bra.uni $L__BB0_7;
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$L__BB0_3:
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sub.s32 %r16, %r6, %r4;
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ld.const.u64 %rd16, [params+48];
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cvta.to.global.u64 %rd17, %rd16;
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mul.wide.u32 %rd18, %r16, 4;
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add.s64 %rd19, %rd17, %rd18;
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ld.const.u64 %rd20, [params+40];
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cvta.to.global.u64 %rd21, %rd20;
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shl.b64 %rd22, %rd1, 3;
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add.s64 %rd23, %rd21, %rd22;
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ld.global.v2.f32 {%f38, %f39}, [%rd23];
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shl.b64 %rd24, %rd2, 3;
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add.s64 %rd25, %rd21, %rd24;
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ld.global.v2.f32 {%f42, %f43}, [%rd25];
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shl.b64 %rd26, %rd3, 3;
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add.s64 %rd27, %rd21, %rd26;
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ld.global.v2.f32 {%f46, %f47}, [%rd27];
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mov.f32 %f50, 0f3F800000;
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sub.f32 %f51, %f50, %f28;
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sub.f32 %f108, %f51, %f29;
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mul.f32 %f52, %f28, %f42;
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mul.f32 %f53, %f28, %f43;
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fma.rn.f32 %f54, %f108, %f38, %f52;
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fma.rn.f32 %f55, %f108, %f39, %f53;
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fma.rn.f32 %f4, %f29, %f46, %f54;
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fma.rn.f32 %f5, %f29, %f47, %f55;
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ld.global.u32 %r5, [%rd19];
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and.b32 %r17, %r5, -16384;
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setp.eq.s32 %p4, %r17, 16384;
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@%p4 bra $L__BB0_5;
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bra.uni $L__BB0_4;
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$L__BB0_5:
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add.s32 %r29, %r5, -16384;
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ld.const.u64 %rd36, [params+64];
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cvta.to.global.u64 %rd37, %rd36;
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mul.wide.u32 %rd38, %r29, 8;
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add.s64 %rd39, %rd37, %rd38;
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ld.global.u64 %rd40, [%rd39];
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tex.2d.v4.f32.f32 {%f66, %f67, %f68, %f69}, [%rd40, {%f4, %f5}];
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cvt.sat.f32.f32 %f70, %f66;
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mul.f32 %f71, %f70, 0f437F0000;
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cvt.rzi.s32.f32 %r30, %f71;
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cvt.sat.f32.f32 %f72, %f67;
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mul.f32 %f73, %f72, 0f437F0000;
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cvt.rzi.s32.f32 %r31, %f73;
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cvt.sat.f32.f32 %f74, %f68;
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mul.f32 %f75, %f74, 0f437F0000;
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cvt.rzi.s32.f32 %r32, %f75;
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shl.b32 %r33, %r31, 8;
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or.b32 %r34, %r33, %r30;
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shl.b32 %r35, %r32, 16;
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or.b32 %r36, %r34, %r35;
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not.b32 %r37, %r36;
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cvt.rn.f32.s32 %f113, %r37;
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bra.uni $L__BB0_8;
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$L__BB0_4:
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abs.f32 %f56, %f4;
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cvt.rmi.f32.f32 %f57, %f56;
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sub.f32 %f58, %f56, %f57;
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abs.f32 %f59, %f5;
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cvt.rmi.f32.f32 %f60, %f59;
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sub.f32 %f61, %f59, %f60;
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ld.const.u64 %rd28, [params+56];
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cvta.to.global.u64 %rd29, %rd28;
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shl.b32 %r18, %r5, 4;
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cvt.u64.u32 %rd30, %r18;
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and.b64 %rd31, %rd30, 1048560;
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add.s64 %rd32, %rd29, %rd31;
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ld.global.v2.u32 {%r19, %r20}, [%rd32];
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cvt.rn.f32.u32 %f62, %r19;
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mul.f32 %f63, %f58, %f62;
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cvt.rzi.u32.f32 %r23, %f63;
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cvt.rn.f32.u32 %f64, %r20;
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mul.f32 %f65, %f61, %f64;
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cvt.rzi.u32.f32 %r24, %f65;
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mad.lo.s32 %r25, %r19, %r24, %r23;
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cvt.u64.u32 %rd33, %r25;
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ld.global.u64 %rd34, [%rd32+8];
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add.s64 %rd35, %rd34, %rd33;
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ld.u8 %r26, [%rd35];
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shr.u32 %r27, %r5, 16;
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and.b32 %r28, %r27, %r26;
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setp.eq.s32 %p5, %r28, 0;
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selp.f32 %f113, 0f00000000, 0f3F800000, %p5;
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$L__BB0_7:
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cvt.u32.u64 %r38, %rd1;
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cvt.u32.u64 %r39, %rd2;
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cvt.u32.u64 %r40, %rd3;
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ld.const.u64 %rd41, [params+16];
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cvta.to.global.u64 %rd42, %rd41;
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mul.wide.s32 %rd43, %r38, 24;
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add.s64 %rd44, %rd42, %rd43;
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mul.wide.s32 %rd45, %r39, 24;
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add.s64 %rd46, %rd42, %rd45;
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mul.wide.s32 %rd47, %r40, 24;
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add.s64 %rd48, %rd42, %rd47;
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ld.global.f32 %f83, [%rd44+12];
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ld.global.f32 %f84, [%rd44+16];
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ld.global.f32 %f85, [%rd44+20];
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ld.global.f32 %f86, [%rd46+12];
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mul.f32 %f87, %f28, %f86;
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ld.global.f32 %f88, [%rd46+16];
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mul.f32 %f89, %f28, %f88;
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ld.global.f32 %f90, [%rd46+20];
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mul.f32 %f91, %f28, %f90;
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fma.rn.f32 %f92, %f108, %f83, %f87;
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fma.rn.f32 %f93, %f108, %f84, %f89;
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fma.rn.f32 %f94, %f108, %f85, %f91;
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ld.global.f32 %f95, [%rd48+12];
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ld.global.f32 %f96, [%rd48+16];
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ld.global.f32 %f97, [%rd48+20];
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fma.rn.f32 %f98, %f29, %f95, %f92;
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fma.rn.f32 %f99, %f29, %f96, %f93;
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fma.rn.f32 %f100, %f29, %f97, %f94;
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mul.f32 %f101, %f99, %f99;
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fma.rn.f32 %f102, %f98, %f98, %f101;
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fma.rn.f32 %f103, %f100, %f100, %f102;
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sqrt.rn.f32 %f104, %f103;
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rcp.rn.f32 %f105, %f104;
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mul.f32 %f112, %f100, %f105;
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mul.f32 %f111, %f99, %f105;
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mul.f32 %f110, %f98, %f105;
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$L__BB0_8:
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st.param.f32 [func_retval0+0], %f110;
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st.param.f32 [func_retval0+4], %f111;
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st.param.f32 [func_retval0+8], %f112;
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st.param.v4.b8 [func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
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st.param.f32 [func_retval0+16], %f25;
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st.param.f32 [func_retval0+20], %f26;
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st.param.f32 [func_retval0+24], %f113;
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st.param.v4.b8 [func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
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ret;
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}
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// .globl oxMain
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.visible .entry oxMain()
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{
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.reg .b64 %rd<2>;
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mov.u64 %rd1, __direct_callable__oxMain;
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// begin inline asm
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// end inline asm
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ret;
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}
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