2081 lines
57 KiB
Plaintext
2081 lines
57 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<178>;
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.reg .b16 %rs<84>;
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.reg .f32 %f<1078>;
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.reg .b32 %r<374>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<113>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r52), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r53), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd24, [params+400];
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cvta.to.global.u64 %rd25, %rd24;
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ld.const.u32 %r58, [params+392];
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mad.lo.s32 %r59, %r58, %r53, %r52;
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mul.wide.u32 %rd26, %r59, 4;
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add.s64 %rd2, %rd25, %rd26;
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ld.global.v2.u8 {%rs7, %rs83}, [%rd2];
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or.b16 %rs9, %rs7, %rs83;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p8, %rs10, 0;
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@%p8 bra $L__BB0_2;
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ld.global.u8 %rs82, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs82, [%rd2+2];
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setp.eq.s16 %p9, %rs82, 0;
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mov.f32 %f1044, 0f00000000;
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mov.u16 %rs83, 0;
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mov.f32 %f1045, %f1044;
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mov.f32 %f1046, %f1044;
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@%p9 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f154, %rs7;
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div.rn.f32 %f155, %f154, 0f437F0000;
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fma.rn.f32 %f156, %f155, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs83, 255;
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cvt.rn.f32.u16 %f157, %rs13;
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div.rn.f32 %f158, %f157, 0f437F0000;
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fma.rn.f32 %f159, %f158, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f160, %rs82;
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div.rn.f32 %f161, %f160, 0f437F0000;
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fma.rn.f32 %f162, %f161, 0f40000000, 0fBF800000;
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mul.f32 %f163, %f159, %f159;
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fma.rn.f32 %f164, %f156, %f156, %f163;
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fma.rn.f32 %f165, %f162, %f162, %f164;
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sqrt.rn.f32 %f166, %f165;
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rcp.rn.f32 %f167, %f166;
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mul.f32 %f1046, %f167, %f162;
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mul.f32 %f1045, %f167, %f159;
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mul.f32 %f1044, %f156, %f167;
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$L__BB0_4:
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ld.const.v2.u32 {%r60, %r61}, [params];
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add.s32 %r3, %r60, %r52;
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add.s32 %r4, %r61, %r53;
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setp.eq.f32 %p10, %f1044, 0f00000000;
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setp.eq.f32 %p11, %f1045, 0f00000000;
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and.pred %p12, %p10, %p11;
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setp.eq.f32 %p13, %f1046, 0f00000000;
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and.pred %p14, %p13, %p12;
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@%p14 bra $L__BB0_142;
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bra.uni $L__BB0_5;
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$L__BB0_142:
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ld.const.u32 %r51, [params+104];
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and.b32 %r342, %r51, 1;
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setp.eq.b32 %p170, %r342, 1;
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mov.pred %p171, 0;
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xor.pred %p172, %p170, %p171;
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not.pred %p173, %p172;
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@%p173 bra $L__BB0_144;
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ld.const.u64 %rd87, [params+144];
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cvta.to.global.u64 %rd88, %rd87;
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ld.const.u32 %r343, [params+136];
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mad.lo.s32 %r344, %r343, %r4, %r3;
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mul.wide.u32 %rd89, %r344, 4;
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add.s64 %rd90, %rd88, %rd89;
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mov.u16 %rs63, 0;
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st.global.v4.u8 [%rd90], {%rs63, %rs63, %rs63, %rs63};
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$L__BB0_144:
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and.b32 %r345, %r51, 8;
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setp.eq.s32 %p174, %r345, 0;
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@%p174 bra $L__BB0_146;
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ld.const.u64 %rd91, [params+192];
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cvta.to.global.u64 %rd92, %rd91;
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ld.const.u32 %r346, [params+184];
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mad.lo.s32 %r347, %r346, %r4, %r3;
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mov.f32 %f967, 0f00000000;
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cvt.rzi.u32.f32 %r348, %f967;
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mul.wide.u32 %rd93, %r347, 2;
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add.s64 %rd94, %rd92, %rd93;
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mov.u16 %rs64, 0;
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cvt.u16.u32 %rs65, %r348;
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st.global.v2.u8 [%rd94], {%rs65, %rs64};
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$L__BB0_146:
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and.b32 %r349, %r51, 4;
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setp.eq.s32 %p175, %r349, 0;
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@%p175 bra $L__BB0_150;
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ld.const.u32 %r350, [params+108];
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setp.eq.s32 %p176, %r350, 0;
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ld.const.u64 %rd95, [params+224];
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cvta.to.global.u64 %rd96, %rd95;
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ld.const.u32 %r351, [params+216];
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mad.lo.s32 %r352, %r351, %r4, %r3;
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mul.wide.u32 %rd97, %r352, 8;
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add.s64 %rd22, %rd96, %rd97;
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@%p176 bra $L__BB0_149;
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ld.global.v4.u16 {%rs72, %rs73, %rs74, %rs75}, [%rd22];
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// begin inline asm
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{ cvt.f32.f16 %f968, %rs72;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f969, %rs73;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f970, %rs74;}
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// end inline asm
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add.f32 %f971, %f968, 0f00000000;
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add.f32 %f972, %f969, 0f00000000;
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add.f32 %f973, %f970, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs71, %f973;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs70, %f972;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs69, %f971;}
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// end inline asm
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mov.u16 %rs76, 0;
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st.global.v4.u16 [%rd22], {%rs69, %rs70, %rs71, %rs76};
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bra.uni $L__BB0_150;
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$L__BB0_5:
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ld.const.v4.f32 {%f168, %f169, %f170, %f171}, [params+512];
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neg.f32 %f13, %f169;
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neg.f32 %f14, %f170;
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mul.f32 %f172, %f1044, %f168;
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mul.f32 %f173, %f1045, %f13;
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sub.f32 %f174, %f173, %f172;
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mul.f32 %f175, %f1046, %f170;
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sub.f32 %f15, %f174, %f175;
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setp.gtu.f32 %p15, %f15, 0f00000000;
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ld.const.u32 %r5, [params+544];
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setp.ne.s32 %p16, %r5, 0;
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or.pred %p17, %p16, %p15;
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@%p17 bra $L__BB0_7;
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ld.const.u32 %r6, [params+104];
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and.b32 %r64, %r6, 32;
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setp.eq.s32 %p18, %r64, 0;
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@%p18 bra $L__BB0_132;
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bra.uni $L__BB0_7;
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$L__BB0_132:
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and.b32 %r328, %r6, 1;
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setp.eq.b32 %p162, %r328, 1;
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mov.pred %p163, 0;
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xor.pred %p164, %p162, %p163;
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not.pred %p165, %p164;
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@%p165 bra $L__BB0_134;
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ld.const.u64 %rd72, [params+144];
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cvta.to.global.u64 %rd73, %rd72;
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ld.const.u32 %r329, [params+136];
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mad.lo.s32 %r330, %r329, %r4, %r3;
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mul.wide.u32 %rd74, %r330, 4;
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add.s64 %rd75, %rd73, %rd74;
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mov.u16 %rs42, 0;
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mov.u16 %rs43, 255;
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st.global.v4.u8 [%rd75], {%rs42, %rs42, %rs42, %rs43};
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$L__BB0_134:
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and.b32 %r331, %r6, 8;
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setp.eq.s32 %p166, %r331, 0;
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@%p166 bra $L__BB0_136;
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ld.const.u64 %rd76, [params+192];
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cvta.to.global.u64 %rd77, %rd76;
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ld.const.u32 %r332, [params+184];
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mad.lo.s32 %r333, %r332, %r4, %r3;
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mov.f32 %f955, 0f00000000;
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cvt.rzi.u32.f32 %r334, %f955;
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mul.wide.u32 %rd78, %r333, 2;
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add.s64 %rd79, %rd77, %rd78;
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cvt.u16.u32 %rs44, %r334;
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mov.u16 %rs45, 255;
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st.global.v2.u8 [%rd79], {%rs44, %rs45};
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$L__BB0_136:
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and.b32 %r335, %r6, 4;
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setp.eq.s32 %p167, %r335, 0;
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@%p167 bra $L__BB0_140;
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ld.const.u32 %r336, [params+108];
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setp.eq.s32 %p168, %r336, 0;
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ld.const.u64 %rd80, [params+224];
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cvta.to.global.u64 %rd81, %rd80;
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ld.const.u32 %r337, [params+216];
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mad.lo.s32 %r338, %r337, %r4, %r3;
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mul.wide.u32 %rd82, %r338, 8;
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add.s64 %rd21, %rd81, %rd82;
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@%p168 bra $L__BB0_139;
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ld.global.v4.u16 {%rs53, %rs54, %rs55, %rs56}, [%rd21];
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// begin inline asm
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{ cvt.f32.f16 %f956, %rs53;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f957, %rs54;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f958, %rs55;}
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// end inline asm
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add.f32 %f959, %f956, 0f00000000;
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add.f32 %f960, %f957, 0f00000000;
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add.f32 %f961, %f958, 0f00000000;
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mov.f32 %f962, 0f3F800000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs52, %f962;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs51, %f961;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs50, %f960;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs49, %f959;}
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// end inline asm
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st.global.v4.u16 [%rd21], {%rs49, %rs50, %rs51, %rs52};
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bra.uni $L__BB0_140;
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$L__BB0_7:
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ld.const.u64 %rd27, [params+432];
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cvta.to.global.u64 %rd28, %rd27;
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ld.const.u32 %r65, [params+424];
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mad.lo.s32 %r66, %r65, %r53, %r52;
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mul.wide.u32 %rd29, %r66, 12;
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add.s64 %rd30, %rd28, %rd29;
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ld.global.f32 %f177, [%rd30];
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mul.f32 %f178, %f177, 0f3456BF95;
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ld.global.f32 %f179, [%rd30+4];
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mul.f32 %f180, %f179, 0f3456BF95;
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ld.global.f32 %f181, [%rd30+8];
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mul.f32 %f182, %f181, 0f3456BF95;
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abs.f32 %f183, %f1044;
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div.rn.f32 %f184, %f178, %f183;
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abs.f32 %f185, %f1045;
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div.rn.f32 %f186, %f180, %f185;
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abs.f32 %f187, %f1046;
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div.rn.f32 %f188, %f182, %f187;
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abs.f32 %f189, %f184;
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abs.f32 %f190, %f186;
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abs.f32 %f191, %f188;
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mov.f32 %f192, 0f38D1B717;
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max.f32 %f193, %f189, %f192;
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max.f32 %f194, %f190, %f192;
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max.f32 %f195, %f191, %f192;
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fma.rn.f32 %f16, %f1044, %f193, %f177;
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fma.rn.f32 %f17, %f1045, %f194, %f179;
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fma.rn.f32 %f18, %f1046, %f195, %f181;
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abs.f32 %f196, %f170;
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abs.f32 %f197, %f168;
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setp.gt.f32 %p19, %f197, %f196;
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selp.f32 %f198, %f13, 0f00000000, %p19;
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mov.f32 %f1048, 0f00000000;
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selp.f32 %f199, %f168, %f14, %p19;
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selp.f32 %f200, 0f00000000, %f169, %p19;
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mul.f32 %f201, %f199, %f199;
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fma.rn.f32 %f202, %f198, %f198, %f201;
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fma.rn.f32 %f203, %f200, %f200, %f202;
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sqrt.rn.f32 %f204, %f203;
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rcp.rn.f32 %f205, %f204;
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mul.f32 %f19, %f198, %f205;
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mul.f32 %f20, %f199, %f205;
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mul.f32 %f21, %f200, %f205;
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ld.const.u64 %rd31, [params+128];
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cvta.to.global.u64 %rd32, %rd31;
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ld.const.u32 %r67, [params+120];
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mad.lo.s32 %r68, %r67, %r53, %r52;
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mul.wide.u32 %rd33, %r68, 4;
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add.s64 %rd3, %rd32, %rd33;
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ld.const.u32 %r7, [params+540];
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setp.lt.s32 %p20, %r7, 1;
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@%p20 bra $L__BB0_36;
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cvt.rn.f32.s32 %f207, %r7;
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rcp.rn.f32 %f22, %f207;
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ld.global.u32 %r366, [%rd3];
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ld.const.f32 %f23, [params+536];
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ld.const.u8 %rs15, [params+104];
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and.b16 %rs16, %rs15, 32;
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setp.eq.s16 %p21, %rs16, 0;
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mov.u32 %r69, 0;
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selp.f32 %f24, 0f3F800000, 0f41200000, %p21;
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mul.f32 %f25, %f16, 0f3456BF95;
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mul.f32 %f26, %f17, 0f3456BF95;
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mul.f32 %f27, %f18, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f208, %f168, %f20;
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mul.f32 %f209, %f169, %f19;
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sub.f32 %f28, %f209, %f208;
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mul.f32 %f210, %f170, %f19;
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mul.f32 %f211, %f168, %f21;
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sub.f32 %f29, %f211, %f210;
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mul.f32 %f212, %f169, %f21;
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mul.f32 %f213, %f170, %f20;
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sub.f32 %f30, %f213, %f212;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd34, __cudart_i2opi_f;
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abs.f32 %f296, %f26;
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abs.f32 %f297, %f25;
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max.f32 %f298, %f297, %f296;
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abs.f32 %f299, %f27;
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max.f32 %f300, %f298, %f299;
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mov.u32 %r363, %r69;
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$L__BB0_9:
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cvt.rn.f32.s32 %f32, %r363;
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mov.u32 %r365, %r69;
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$L__BB0_10:
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mad.lo.s32 %r71, %r366, 1664525, 1013904223;
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and.b32 %r72, %r71, 16777215;
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cvt.rn.f32.u32 %f214, %r72;
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fma.rn.f32 %f215, %f214, 0f33800000, %f32;
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mul.f32 %f216, %f22, %f215;
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mad.lo.s32 %r366, %r71, 1664525, 1013904223;
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and.b32 %r73, %r366, 16777215;
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cvt.rn.f32.u32 %f217, %r73;
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cvt.rn.f32.s32 %f218, %r365;
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fma.rn.f32 %f219, %f217, 0f33800000, %f218;
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mul.f32 %f220, %f22, %f219;
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sqrt.rn.f32 %f34, %f216;
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mul.f32 %f35, %f220, 0f40C90FDB;
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mul.f32 %f221, %f35, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r373, %f221;
|
|
cvt.rn.f32.s32 %f222, %r373;
|
|
mov.f32 %f223, 0fBFC90FDA;
|
|
fma.rn.f32 %f224, %f222, %f223, %f35;
|
|
mov.f32 %f225, 0fB3A22168;
|
|
fma.rn.f32 %f226, %f222, %f225, %f224;
|
|
mov.f32 %f227, 0fA7C234C5;
|
|
fma.rn.f32 %f1052, %f222, %f227, %f226;
|
|
abs.f32 %f37, %f35;
|
|
setp.ltu.f32 %p22, %f37, 0f47CE4780;
|
|
mov.u32 %r370, %r373;
|
|
mov.f32 %f1049, %f1052;
|
|
@%p22 bra $L__BB0_18;
|
|
|
|
setp.eq.f32 %p23, %f37, 0f7F800000;
|
|
@%p23 bra $L__BB0_17;
|
|
bra.uni $L__BB0_12;
|
|
|
|
$L__BB0_17:
|
|
mov.f32 %f230, 0f00000000;
|
|
mul.rn.f32 %f1049, %f35, %f230;
|
|
mov.u32 %r370, 0;
|
|
bra.uni $L__BB0_18;
|
|
|
|
$L__BB0_12:
|
|
mov.b32 %r15, %f35;
|
|
bfe.u32 %r75, %r15, 23, 8;
|
|
add.s32 %r16, %r75, -128;
|
|
shl.b32 %r76, %r15, 8;
|
|
or.b32 %r17, %r76, -2147483648;
|
|
shr.u32 %r18, %r16, 5;
|
|
mov.u64 %rd110, 0;
|
|
mov.u32 %r367, 0;
|
|
mov.u64 %rd108, %rd1;
|
|
mov.u64 %rd109, %rd34;
|
|
|
|
$L__BB0_13:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r77, [%rd109];
|
|
mad.wide.u32 %rd36, %r77, %r17, %rd110;
|
|
shr.u64 %rd110, %rd36, 32;
|
|
st.local.u32 [%rd108], %rd36;
|
|
add.s64 %rd109, %rd109, 4;
|
|
add.s64 %rd108, %rd108, 4;
|
|
add.s32 %r367, %r367, 1;
|
|
setp.ne.s32 %p24, %r367, 6;
|
|
@%p24 bra $L__BB0_13;
|
|
|
|
st.local.u32 [%rd5], %rd110;
|
|
mov.u32 %r78, 4;
|
|
sub.s32 %r21, %r78, %r18;
|
|
mov.u32 %r79, 6;
|
|
sub.s32 %r80, %r79, %r18;
|
|
mul.wide.s32 %rd37, %r80, 4;
|
|
add.s64 %rd38, %rd1, %rd37;
|
|
ld.local.u32 %r368, [%rd38];
|
|
ld.local.u32 %r369, [%rd38+-4];
|
|
and.b32 %r24, %r16, 31;
|
|
setp.eq.s32 %p25, %r24, 0;
|
|
@%p25 bra $L__BB0_16;
|
|
|
|
mov.u32 %r81, 32;
|
|
sub.s32 %r82, %r81, %r24;
|
|
shr.u32 %r83, %r369, %r82;
|
|
shl.b32 %r84, %r368, %r24;
|
|
add.s32 %r368, %r83, %r84;
|
|
mul.wide.s32 %rd39, %r21, 4;
|
|
add.s64 %rd40, %rd1, %rd39;
|
|
ld.local.u32 %r85, [%rd40];
|
|
shr.u32 %r86, %r85, %r82;
|
|
shl.b32 %r87, %r369, %r24;
|
|
add.s32 %r369, %r86, %r87;
|
|
|
|
$L__BB0_16:
|
|
and.b32 %r88, %r15, -2147483648;
|
|
shr.u32 %r89, %r369, 30;
|
|
shl.b32 %r90, %r368, 2;
|
|
or.b32 %r91, %r89, %r90;
|
|
shr.u32 %r92, %r91, 31;
|
|
shr.u32 %r93, %r368, 30;
|
|
add.s32 %r94, %r92, %r93;
|
|
neg.s32 %r95, %r94;
|
|
setp.eq.s32 %p26, %r88, 0;
|
|
selp.b32 %r370, %r94, %r95, %p26;
|
|
setp.ne.s32 %p27, %r92, 0;
|
|
xor.b32 %r96, %r88, -2147483648;
|
|
selp.b32 %r97, %r96, %r88, %p27;
|
|
selp.b32 %r98, -1, 0, %p27;
|
|
xor.b32 %r99, %r91, %r98;
|
|
shl.b32 %r100, %r369, 2;
|
|
xor.b32 %r101, %r100, %r98;
|
|
cvt.u64.u32 %rd41, %r99;
|
|
cvt.u64.u32 %rd42, %r101;
|
|
bfi.b64 %rd43, %rd41, %rd42, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd43;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f228, %fd2;
|
|
setp.eq.s32 %p28, %r97, 0;
|
|
neg.f32 %f229, %f228;
|
|
selp.f32 %f1049, %f228, %f229, %p28;
|
|
|
|
$L__BB0_18:
|
|
add.s32 %r31, %r370, 1;
|
|
and.b32 %r32, %r31, 1;
|
|
setp.eq.s32 %p29, %r32, 0;
|
|
selp.f32 %f41, %f1049, 0f3F800000, %p29;
|
|
mul.rn.f32 %f42, %f1049, %f1049;
|
|
mov.f32 %f1050, 0fB94D4153;
|
|
@%p29 bra $L__BB0_20;
|
|
|
|
mov.f32 %f232, 0fBAB607ED;
|
|
mov.f32 %f233, 0f37CBAC00;
|
|
fma.rn.f32 %f1050, %f233, %f42, %f232;
|
|
|
|
$L__BB0_20:
|
|
selp.f32 %f234, 0f3C0885E4, 0f3D2AAABB, %p29;
|
|
fma.rn.f32 %f235, %f1050, %f42, %f234;
|
|
selp.f32 %f236, 0fBE2AAAA8, 0fBEFFFFFF, %p29;
|
|
fma.rn.f32 %f237, %f235, %f42, %f236;
|
|
mov.f32 %f238, 0f00000000;
|
|
fma.rn.f32 %f239, %f42, %f41, %f238;
|
|
fma.rn.f32 %f1051, %f237, %f239, %f41;
|
|
and.b32 %r103, %r31, 2;
|
|
setp.eq.s32 %p31, %r103, 0;
|
|
@%p31 bra $L__BB0_22;
|
|
|
|
mov.f32 %f241, 0fBF800000;
|
|
fma.rn.f32 %f1051, %f1051, %f241, %f238;
|
|
|
|
$L__BB0_22:
|
|
@%p22 bra $L__BB0_30;
|
|
|
|
setp.eq.f32 %p33, %f37, 0f7F800000;
|
|
@%p33 bra $L__BB0_29;
|
|
bra.uni $L__BB0_24;
|
|
|
|
$L__BB0_29:
|
|
mov.f32 %f244, 0f00000000;
|
|
mul.rn.f32 %f1052, %f35, %f244;
|
|
mov.u32 %r373, 0;
|
|
bra.uni $L__BB0_30;
|
|
|
|
$L__BB0_24:
|
|
mov.b32 %r33, %f35;
|
|
bfe.u32 %r104, %r33, 23, 8;
|
|
add.s32 %r34, %r104, -128;
|
|
shl.b32 %r105, %r33, 8;
|
|
or.b32 %r35, %r105, -2147483648;
|
|
shr.u32 %r36, %r34, 5;
|
|
mov.u64 %rd111, 0;
|
|
mov.u64 %rd112, %rd111;
|
|
|
|
$L__BB0_25:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd46, %rd111, 2;
|
|
mov.u64 %rd47, __cudart_i2opi_f;
|
|
add.s64 %rd48, %rd47, %rd46;
|
|
ld.global.nc.u32 %r106, [%rd48];
|
|
mad.wide.u32 %rd49, %r106, %r35, %rd112;
|
|
shr.u64 %rd112, %rd49, 32;
|
|
add.s64 %rd50, %rd1, %rd46;
|
|
st.local.u32 [%rd50], %rd49;
|
|
cvt.u32.u64 %r107, %rd111;
|
|
add.s32 %r108, %r107, 1;
|
|
cvt.s64.s32 %rd111, %r108;
|
|
setp.ne.s32 %p34, %r108, 6;
|
|
@%p34 bra $L__BB0_25;
|
|
|
|
st.local.u32 [%rd5], %rd112;
|
|
mov.u32 %r109, 4;
|
|
sub.s32 %r37, %r109, %r36;
|
|
mov.u32 %r110, 6;
|
|
sub.s32 %r111, %r110, %r36;
|
|
mul.wide.s32 %rd51, %r111, 4;
|
|
add.s64 %rd52, %rd1, %rd51;
|
|
ld.local.u32 %r371, [%rd52];
|
|
ld.local.u32 %r372, [%rd52+-4];
|
|
and.b32 %r40, %r34, 31;
|
|
setp.eq.s32 %p35, %r40, 0;
|
|
@%p35 bra $L__BB0_28;
|
|
|
|
mov.u32 %r112, 32;
|
|
sub.s32 %r113, %r112, %r40;
|
|
shr.u32 %r114, %r372, %r113;
|
|
shl.b32 %r115, %r371, %r40;
|
|
add.s32 %r371, %r114, %r115;
|
|
mul.wide.s32 %rd53, %r37, 4;
|
|
add.s64 %rd54, %rd1, %rd53;
|
|
ld.local.u32 %r116, [%rd54];
|
|
shr.u32 %r117, %r116, %r113;
|
|
shl.b32 %r118, %r372, %r40;
|
|
add.s32 %r372, %r117, %r118;
|
|
|
|
$L__BB0_28:
|
|
and.b32 %r119, %r33, -2147483648;
|
|
shr.u32 %r120, %r372, 30;
|
|
shl.b32 %r121, %r371, 2;
|
|
or.b32 %r122, %r120, %r121;
|
|
shr.u32 %r123, %r122, 31;
|
|
shr.u32 %r124, %r371, 30;
|
|
add.s32 %r125, %r123, %r124;
|
|
neg.s32 %r126, %r125;
|
|
setp.eq.s32 %p36, %r119, 0;
|
|
selp.b32 %r373, %r125, %r126, %p36;
|
|
setp.ne.s32 %p37, %r123, 0;
|
|
xor.b32 %r127, %r119, -2147483648;
|
|
selp.b32 %r128, %r127, %r119, %p37;
|
|
selp.b32 %r129, -1, 0, %p37;
|
|
xor.b32 %r130, %r122, %r129;
|
|
shl.b32 %r131, %r372, 2;
|
|
xor.b32 %r132, %r131, %r129;
|
|
cvt.u64.u32 %rd55, %r130;
|
|
cvt.u64.u32 %rd56, %r132;
|
|
bfi.b64 %rd57, %rd55, %rd56, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd57;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f242, %fd4;
|
|
setp.eq.s32 %p38, %r128, 0;
|
|
neg.f32 %f243, %f242;
|
|
selp.f32 %f1052, %f242, %f243, %p38;
|
|
|
|
$L__BB0_30:
|
|
mul.f32 %f51, %f34, %f1051;
|
|
and.b32 %r47, %r373, 1;
|
|
setp.eq.s32 %p39, %r47, 0;
|
|
selp.f32 %f52, %f1052, 0f3F800000, %p39;
|
|
mul.rn.f32 %f53, %f1052, %f1052;
|
|
mov.f32 %f1053, 0fB94D4153;
|
|
@%p39 bra $L__BB0_32;
|
|
|
|
mov.f32 %f246, 0fBAB607ED;
|
|
mov.f32 %f247, 0f37CBAC00;
|
|
fma.rn.f32 %f1053, %f247, %f53, %f246;
|
|
|
|
$L__BB0_32:
|
|
selp.f32 %f248, 0f3C0885E4, 0f3D2AAABB, %p39;
|
|
fma.rn.f32 %f249, %f1053, %f53, %f248;
|
|
selp.f32 %f250, 0fBE2AAAA8, 0fBEFFFFFF, %p39;
|
|
fma.rn.f32 %f251, %f249, %f53, %f250;
|
|
mov.f32 %f252, 0f00000000;
|
|
fma.rn.f32 %f253, %f53, %f52, %f252;
|
|
fma.rn.f32 %f1054, %f251, %f253, %f52;
|
|
and.b32 %r134, %r373, 2;
|
|
setp.eq.s32 %p41, %r134, 0;
|
|
@%p41 bra $L__BB0_34;
|
|
|
|
mov.f32 %f255, 0fBF800000;
|
|
fma.rn.f32 %f1054, %f1054, %f255, %f252;
|
|
|
|
$L__BB0_34:
|
|
mul.f32 %f265, %f51, %f51;
|
|
mov.f32 %f266, 0f3F800000;
|
|
sub.f32 %f267, %f266, %f265;
|
|
mul.f32 %f268, %f34, %f1054;
|
|
mul.f32 %f269, %f268, %f268;
|
|
sub.f32 %f270, %f267, %f269;
|
|
max.f32 %f271, %f252, %f270;
|
|
sqrt.rn.f32 %f272, %f271;
|
|
mul.f32 %f273, %f19, %f268;
|
|
mul.f32 %f274, %f20, %f268;
|
|
mul.f32 %f275, %f21, %f268;
|
|
fma.rn.f32 %f276, %f30, %f51, %f273;
|
|
fma.rn.f32 %f277, %f29, %f51, %f274;
|
|
fma.rn.f32 %f278, %f28, %f51, %f275;
|
|
fma.rn.f32 %f279, %f168, %f272, %f276;
|
|
fma.rn.f32 %f280, %f169, %f272, %f277;
|
|
fma.rn.f32 %f281, %f170, %f272, %f278;
|
|
add.f32 %f282, %f168, %f279;
|
|
add.f32 %f283, %f169, %f280;
|
|
add.f32 %f284, %f170, %f281;
|
|
mul.f32 %f285, %f23, %f282;
|
|
mul.f32 %f286, %f23, %f283;
|
|
mul.f32 %f287, %f23, %f284;
|
|
sub.f32 %f288, %f285, %f168;
|
|
sub.f32 %f289, %f286, %f169;
|
|
sub.f32 %f290, %f287, %f170;
|
|
mul.f32 %f291, %f289, %f289;
|
|
fma.rn.f32 %f292, %f288, %f288, %f291;
|
|
fma.rn.f32 %f293, %f290, %f290, %f292;
|
|
sqrt.rn.f32 %f294, %f293;
|
|
rcp.rn.f32 %f295, %f294;
|
|
mul.f32 %f259, %f295, %f288;
|
|
mul.f32 %f260, %f295, %f289;
|
|
mul.f32 %f261, %f295, %f290;
|
|
mov.f32 %f301, 0f38D1B717;
|
|
max.f32 %f302, %f300, %f301;
|
|
mul.f32 %f262, %f24, %f302;
|
|
mov.f32 %f263, 0f6C4ECB8F;
|
|
mov.u32 %r171, 2;
|
|
mov.u32 %r173, 1;
|
|
mov.u32 %r174, 1065353216;
|
|
mov.u32 %r205, 0;
|
|
// begin inline asm
|
|
call(%r135,%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166),_optix_trace_typed_32,(%r205,%rd4,%f16,%f17,%f18,%f259,%f260,%f261,%f262,%f263,%f252,%r173,%r205,%r173,%r171,%r173,%r173,%r174,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205,%r205);
|
|
// end inline asm
|
|
mov.b32 %f303, %r135;
|
|
add.f32 %f1048, %f1048, %f303;
|
|
add.s32 %r365, %r365, 1;
|
|
setp.lt.s32 %p42, %r365, %r7;
|
|
@%p42 bra $L__BB0_10;
|
|
|
|
add.s32 %r363, %r363, 1;
|
|
setp.lt.s32 %p43, %r363, %r7;
|
|
@%p43 bra $L__BB0_9;
|
|
|
|
$L__BB0_36:
|
|
setp.eq.s32 %p44, %r7, 0;
|
|
mov.f32 %f1056, 0f3F800000;
|
|
@%p44 bra $L__BB0_38;
|
|
|
|
mul.lo.s32 %r206, %r7, %r7;
|
|
cvt.rn.f32.s32 %f305, %r206;
|
|
div.rn.f32 %f1056, %f1048, %f305;
|
|
|
|
$L__BB0_38:
|
|
ld.const.f32 %f306, [params+524];
|
|
mul.f32 %f307, %f1056, %f306;
|
|
ld.const.v2.f32 {%f308, %f309}, [params+528];
|
|
mul.f32 %f312, %f1056, %f308;
|
|
mul.f32 %f313, %f1056, %f309;
|
|
cvt.sat.f32.f32 %f314, %f15;
|
|
mul.f32 %f315, %f307, %f314;
|
|
mul.f32 %f316, %f312, %f314;
|
|
mul.f32 %f317, %f313, %f314;
|
|
setp.eq.s32 %p45, %r5, 0;
|
|
selp.f32 %f63, %f315, %f307, %p45;
|
|
selp.f32 %f64, %f316, %f312, %p45;
|
|
selp.f32 %f65, %f317, %f313, %p45;
|
|
ld.const.u32 %r50, [params+104];
|
|
and.b32 %r207, %r50, 8;
|
|
setp.eq.s32 %p46, %r207, 0;
|
|
@%p46 bra $L__BB0_52;
|
|
|
|
mov.f32 %f322, 0f3EE8BA2E;
|
|
abs.f32 %f67, %f1056;
|
|
setp.lt.f32 %p47, %f67, 0f00800000;
|
|
mul.f32 %f324, %f67, 0f4B800000;
|
|
selp.f32 %f325, %f324, %f67, %p47;
|
|
selp.f32 %f326, 0fC3170000, 0fC2FE0000, %p47;
|
|
mov.b32 %r210, %f325;
|
|
and.b32 %r211, %r210, 8388607;
|
|
or.b32 %r212, %r211, 1065353216;
|
|
mov.b32 %f327, %r212;
|
|
shr.u32 %r213, %r210, 23;
|
|
cvt.rn.f32.u32 %f328, %r213;
|
|
add.f32 %f329, %f326, %f328;
|
|
setp.gt.f32 %p48, %f327, 0f3FB504F3;
|
|
mul.f32 %f330, %f327, 0f3F000000;
|
|
add.f32 %f331, %f329, 0f3F800000;
|
|
selp.f32 %f332, %f331, %f329, %p48;
|
|
selp.f32 %f333, %f330, %f327, %p48;
|
|
add.f32 %f334, %f333, 0fBF800000;
|
|
add.f32 %f335, %f333, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f336, %f335;
|
|
add.f32 %f337, %f334, %f334;
|
|
mul.f32 %f338, %f337, %f336;
|
|
mul.f32 %f339, %f338, %f338;
|
|
mov.f32 %f340, 0f3C4CAF63;
|
|
mov.f32 %f341, 0f3B18F0FE;
|
|
fma.rn.f32 %f342, %f341, %f339, %f340;
|
|
mov.f32 %f343, 0f3DAAAABD;
|
|
fma.rn.f32 %f344, %f342, %f339, %f343;
|
|
mul.rn.f32 %f345, %f344, %f339;
|
|
mul.rn.f32 %f346, %f345, %f338;
|
|
sub.f32 %f347, %f334, %f338;
|
|
add.f32 %f348, %f347, %f347;
|
|
neg.f32 %f349, %f338;
|
|
fma.rn.f32 %f350, %f349, %f334, %f348;
|
|
mul.rn.f32 %f351, %f336, %f350;
|
|
add.f32 %f352, %f346, %f338;
|
|
sub.f32 %f353, %f338, %f352;
|
|
add.f32 %f354, %f346, %f353;
|
|
add.f32 %f355, %f351, %f354;
|
|
add.f32 %f356, %f352, %f355;
|
|
sub.f32 %f357, %f352, %f356;
|
|
add.f32 %f358, %f355, %f357;
|
|
mov.f32 %f359, 0f3F317200;
|
|
mul.rn.f32 %f360, %f332, %f359;
|
|
mov.f32 %f361, 0f35BFBE8E;
|
|
mul.rn.f32 %f362, %f332, %f361;
|
|
add.f32 %f363, %f360, %f356;
|
|
sub.f32 %f364, %f360, %f363;
|
|
add.f32 %f365, %f356, %f364;
|
|
add.f32 %f366, %f358, %f365;
|
|
add.f32 %f367, %f362, %f366;
|
|
add.f32 %f368, %f363, %f367;
|
|
sub.f32 %f369, %f363, %f368;
|
|
add.f32 %f370, %f367, %f369;
|
|
mul.rn.f32 %f371, %f322, %f368;
|
|
neg.f32 %f372, %f371;
|
|
fma.rn.f32 %f373, %f322, %f368, %f372;
|
|
fma.rn.f32 %f374, %f322, %f370, %f373;
|
|
mov.f32 %f375, 0f00000000;
|
|
fma.rn.f32 %f376, %f375, %f368, %f374;
|
|
add.rn.f32 %f377, %f371, %f376;
|
|
neg.f32 %f378, %f377;
|
|
add.rn.f32 %f379, %f371, %f378;
|
|
add.rn.f32 %f380, %f379, %f376;
|
|
mov.b32 %r214, %f377;
|
|
setp.eq.s32 %p49, %r214, 1118925336;
|
|
add.s32 %r215, %r214, -1;
|
|
mov.b32 %f381, %r215;
|
|
add.f32 %f382, %f380, 0f37000000;
|
|
selp.f32 %f68, %f382, %f380, %p49;
|
|
selp.f32 %f383, %f381, %f377, %p49;
|
|
mov.f32 %f384, 0f3FB8AA3B;
|
|
mul.rn.f32 %f385, %f383, %f384;
|
|
cvt.rzi.f32.f32 %f386, %f385;
|
|
abs.f32 %f387, %f386;
|
|
setp.gt.f32 %p50, %f387, 0f42FC0000;
|
|
mov.b32 %r216, %f386;
|
|
and.b32 %r217, %r216, -2147483648;
|
|
or.b32 %r218, %r217, 1123811328;
|
|
mov.b32 %f388, %r218;
|
|
selp.f32 %f389, %f388, %f386, %p50;
|
|
mov.f32 %f390, 0fBF317218;
|
|
fma.rn.f32 %f391, %f389, %f390, %f383;
|
|
mov.f32 %f392, 0f3102E308;
|
|
fma.rn.f32 %f393, %f389, %f392, %f391;
|
|
mul.f32 %f394, %f393, 0f3FB8AA3B;
|
|
add.f32 %f395, %f389, 0f4B40007F;
|
|
mov.b32 %r219, %f395;
|
|
shl.b32 %r220, %r219, 23;
|
|
mov.b32 %f396, %r220;
|
|
ex2.approx.ftz.f32 %f397, %f394;
|
|
mul.f32 %f69, %f397, %f396;
|
|
setp.eq.f32 %p51, %f69, 0f7F800000;
|
|
mov.f32 %f1057, 0f7F800000;
|
|
@%p51 bra $L__BB0_41;
|
|
|
|
fma.rn.f32 %f1057, %f69, %f68, %f69;
|
|
|
|
$L__BB0_41:
|
|
mov.f32 %f988, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f987, %f988;
|
|
add.f32 %f986, %f987, %f987;
|
|
mov.f32 %f985, 0f3EE8BA2E;
|
|
sub.f32 %f984, %f985, %f986;
|
|
abs.f32 %f983, %f984;
|
|
setp.lt.f32 %p52, %f1056, 0f00000000;
|
|
setp.eq.f32 %p53, %f983, 0f3F800000;
|
|
and.pred %p1, %p52, %p53;
|
|
setp.eq.f32 %p54, %f1056, 0f00000000;
|
|
@%p54 bra $L__BB0_45;
|
|
bra.uni $L__BB0_42;
|
|
|
|
$L__BB0_45:
|
|
add.f32 %f402, %f1056, %f1056;
|
|
selp.f32 %f1059, %f402, 0f00000000, %p53;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_149:
|
|
mov.f32 %f976, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f976;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f976;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f976;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs80, 0;
|
|
st.global.v4.u16 [%rd22], {%rs77, %rs78, %rs79, %rs80};
|
|
|
|
$L__BB0_150:
|
|
and.b32 %r353, %r51, 64;
|
|
setp.eq.s32 %p177, %r353, 0;
|
|
@%p177 bra $L__BB0_152;
|
|
|
|
ld.const.u64 %rd98, [params+208];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r354, [params+200];
|
|
mad.lo.s32 %r355, %r354, %r4, %r3;
|
|
mul.wide.u32 %rd100, %r355, 4;
|
|
add.s64 %rd101, %rd99, %rd100;
|
|
mov.u16 %rs81, 0;
|
|
st.global.v4.u8 [%rd101], {%rs81, %rs81, %rs81, %rs81};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_42:
|
|
mov.b32 %r221, %f1057;
|
|
xor.b32 %r222, %r221, -2147483648;
|
|
mov.b32 %f398, %r222;
|
|
selp.f32 %f1059, %f398, %f1057, %p1;
|
|
setp.geu.f32 %p55, %f1056, 0f00000000;
|
|
@%p55 bra $L__BB0_46;
|
|
|
|
mov.f32 %f399, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f400, %f399;
|
|
setp.eq.f32 %p56, %f400, 0f3EE8BA2E;
|
|
@%p56 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1059, 0f7FFFFFFF;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f989, %f1056;
|
|
add.f32 %f403, %f989, 0f3EE8BA2E;
|
|
mov.b32 %r223, %f403;
|
|
setp.lt.s32 %p58, %r223, 2139095040;
|
|
@%p58 bra $L__BB0_51;
|
|
|
|
abs.f32 %f990, %f1056;
|
|
setp.gtu.f32 %p59, %f990, 0f7F800000;
|
|
@%p59 bra $L__BB0_50;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_50:
|
|
add.f32 %f1059, %f1056, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_48:
|
|
abs.f32 %f991, %f1056;
|
|
setp.neu.f32 %p60, %f991, 0f7F800000;
|
|
@%p60 bra $L__BB0_51;
|
|
|
|
selp.f32 %f1059, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_51:
|
|
ld.const.u32 %r362, [params+184];
|
|
mad.lo.s32 %r361, %r362, %r4, %r3;
|
|
cvt.u64.u32 %rd107, %r361;
|
|
ld.const.u64 %rd106, [params+192];
|
|
cvta.to.global.u64 %rd105, %rd106;
|
|
mul.f32 %f404, %f1059, 0f437F0000;
|
|
setp.eq.f32 %p61, %f1056, 0f3F800000;
|
|
selp.f32 %f405, 0f437F0000, %f404, %p61;
|
|
cvt.rzi.u32.f32 %r224, %f405;
|
|
shl.b64 %rd60, %rd107, 1;
|
|
add.s64 %rd61, %rd105, %rd60;
|
|
cvt.u16.u32 %rs17, %r224;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v2.u8 [%rd61], {%rs17, %rs18};
|
|
|
|
$L__BB0_52:
|
|
ld.const.u32 %r360, [params+104];
|
|
and.b32 %r225, %r360, 1;
|
|
setp.eq.b32 %p62, %r225, 1;
|
|
mov.pred %p63, 0;
|
|
xor.pred %p64, %p62, %p63;
|
|
not.pred %p65, %p64;
|
|
@%p65 bra $L__BB0_126;
|
|
|
|
mov.f32 %f410, 0f3EE66666;
|
|
abs.f32 %f79, %f63;
|
|
setp.lt.f32 %p66, %f79, 0f00800000;
|
|
mul.f32 %f412, %f79, 0f4B800000;
|
|
selp.f32 %f413, %f412, %f79, %p66;
|
|
selp.f32 %f414, 0fC3170000, 0fC2FE0000, %p66;
|
|
mov.b32 %r226, %f413;
|
|
and.b32 %r227, %r226, 8388607;
|
|
or.b32 %r228, %r227, 1065353216;
|
|
mov.b32 %f415, %r228;
|
|
shr.u32 %r229, %r226, 23;
|
|
cvt.rn.f32.u32 %f416, %r229;
|
|
add.f32 %f417, %f414, %f416;
|
|
setp.gt.f32 %p67, %f415, 0f3FB504F3;
|
|
mul.f32 %f418, %f415, 0f3F000000;
|
|
add.f32 %f419, %f417, 0f3F800000;
|
|
selp.f32 %f420, %f419, %f417, %p67;
|
|
selp.f32 %f421, %f418, %f415, %p67;
|
|
add.f32 %f422, %f421, 0fBF800000;
|
|
add.f32 %f423, %f421, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f424, %f423;
|
|
add.f32 %f425, %f422, %f422;
|
|
mul.f32 %f426, %f425, %f424;
|
|
mul.f32 %f427, %f426, %f426;
|
|
mov.f32 %f428, 0f3C4CAF63;
|
|
mov.f32 %f429, 0f3B18F0FE;
|
|
fma.rn.f32 %f430, %f429, %f427, %f428;
|
|
mov.f32 %f431, 0f3DAAAABD;
|
|
fma.rn.f32 %f432, %f430, %f427, %f431;
|
|
mul.rn.f32 %f433, %f432, %f427;
|
|
mul.rn.f32 %f434, %f433, %f426;
|
|
sub.f32 %f435, %f422, %f426;
|
|
add.f32 %f436, %f435, %f435;
|
|
neg.f32 %f437, %f426;
|
|
fma.rn.f32 %f438, %f437, %f422, %f436;
|
|
mul.rn.f32 %f439, %f424, %f438;
|
|
add.f32 %f440, %f434, %f426;
|
|
sub.f32 %f441, %f426, %f440;
|
|
add.f32 %f442, %f434, %f441;
|
|
add.f32 %f443, %f439, %f442;
|
|
add.f32 %f444, %f440, %f443;
|
|
sub.f32 %f445, %f440, %f444;
|
|
add.f32 %f446, %f443, %f445;
|
|
mov.f32 %f447, 0f3F317200;
|
|
mul.rn.f32 %f448, %f420, %f447;
|
|
mov.f32 %f449, 0f35BFBE8E;
|
|
mul.rn.f32 %f450, %f420, %f449;
|
|
add.f32 %f451, %f448, %f444;
|
|
sub.f32 %f452, %f448, %f451;
|
|
add.f32 %f453, %f444, %f452;
|
|
add.f32 %f454, %f446, %f453;
|
|
add.f32 %f455, %f450, %f454;
|
|
add.f32 %f456, %f451, %f455;
|
|
sub.f32 %f457, %f451, %f456;
|
|
add.f32 %f458, %f455, %f457;
|
|
mul.rn.f32 %f459, %f410, %f456;
|
|
neg.f32 %f460, %f459;
|
|
fma.rn.f32 %f461, %f410, %f456, %f460;
|
|
fma.rn.f32 %f462, %f410, %f458, %f461;
|
|
mov.f32 %f463, 0f00000000;
|
|
fma.rn.f32 %f464, %f463, %f456, %f462;
|
|
add.rn.f32 %f465, %f459, %f464;
|
|
neg.f32 %f466, %f465;
|
|
add.rn.f32 %f467, %f459, %f466;
|
|
add.rn.f32 %f468, %f467, %f464;
|
|
mov.b32 %r230, %f465;
|
|
setp.eq.s32 %p68, %r230, 1118925336;
|
|
add.s32 %r231, %r230, -1;
|
|
mov.b32 %f469, %r231;
|
|
add.f32 %f470, %f468, 0f37000000;
|
|
selp.f32 %f80, %f470, %f468, %p68;
|
|
selp.f32 %f471, %f469, %f465, %p68;
|
|
mov.f32 %f472, 0f3FB8AA3B;
|
|
mul.rn.f32 %f473, %f471, %f472;
|
|
cvt.rzi.f32.f32 %f474, %f473;
|
|
abs.f32 %f475, %f474;
|
|
setp.gt.f32 %p69, %f475, 0f42FC0000;
|
|
mov.b32 %r232, %f474;
|
|
and.b32 %r233, %r232, -2147483648;
|
|
or.b32 %r234, %r233, 1123811328;
|
|
mov.b32 %f476, %r234;
|
|
selp.f32 %f477, %f476, %f474, %p69;
|
|
mov.f32 %f478, 0fBF317218;
|
|
fma.rn.f32 %f479, %f477, %f478, %f471;
|
|
mov.f32 %f480, 0f3102E308;
|
|
fma.rn.f32 %f481, %f477, %f480, %f479;
|
|
mul.f32 %f482, %f481, 0f3FB8AA3B;
|
|
add.f32 %f483, %f477, 0f4B40007F;
|
|
mov.b32 %r235, %f483;
|
|
shl.b32 %r236, %r235, 23;
|
|
mov.b32 %f484, %r236;
|
|
ex2.approx.ftz.f32 %f485, %f482;
|
|
mul.f32 %f81, %f485, %f484;
|
|
setp.eq.f32 %p70, %f81, 0f7F800000;
|
|
mov.f32 %f1060, 0f7F800000;
|
|
@%p70 bra $L__BB0_55;
|
|
|
|
fma.rn.f32 %f1060, %f81, %f80, %f81;
|
|
|
|
$L__BB0_55:
|
|
mov.f32 %f997, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f996, %f997;
|
|
add.f32 %f995, %f996, %f996;
|
|
mov.f32 %f994, 0f3EE66666;
|
|
sub.f32 %f993, %f994, %f995;
|
|
abs.f32 %f992, %f993;
|
|
setp.lt.f32 %p71, %f63, 0f00000000;
|
|
setp.eq.f32 %p72, %f992, 0f3F800000;
|
|
and.pred %p2, %p71, %p72;
|
|
setp.eq.f32 %p73, %f63, 0f00000000;
|
|
@%p73 bra $L__BB0_59;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_59:
|
|
add.f32 %f490, %f63, %f63;
|
|
selp.f32 %f1062, %f490, 0f00000000, %p72;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_56:
|
|
mov.b32 %r237, %f1060;
|
|
xor.b32 %r238, %r237, -2147483648;
|
|
mov.b32 %f486, %r238;
|
|
selp.f32 %f1062, %f486, %f1060, %p2;
|
|
setp.geu.f32 %p74, %f63, 0f00000000;
|
|
@%p74 bra $L__BB0_60;
|
|
|
|
mov.f32 %f487, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f488, %f487;
|
|
setp.eq.f32 %p75, %f488, 0f3EE66666;
|
|
@%p75 bra $L__BB0_60;
|
|
|
|
mov.f32 %f1062, 0f7FFFFFFF;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f998, %f63;
|
|
add.f32 %f491, %f998, 0f3EE66666;
|
|
mov.b32 %r239, %f491;
|
|
setp.lt.s32 %p77, %r239, 2139095040;
|
|
@%p77 bra $L__BB0_65;
|
|
|
|
abs.f32 %f999, %f63;
|
|
setp.gtu.f32 %p78, %f999, 0f7F800000;
|
|
@%p78 bra $L__BB0_64;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_64:
|
|
add.f32 %f1062, %f63, 0f3EE66666;
|
|
bra.uni $L__BB0_65;
|
|
|
|
$L__BB0_62:
|
|
abs.f32 %f1000, %f63;
|
|
setp.neu.f32 %p79, %f1000, 0f7F800000;
|
|
@%p79 bra $L__BB0_65;
|
|
|
|
selp.f32 %f1062, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_65:
|
|
setp.eq.f32 %p80, %f63, 0f3F800000;
|
|
selp.f32 %f90, 0f3F800000, %f1062, %p80;
|
|
abs.f32 %f91, %f64;
|
|
setp.lt.f32 %p81, %f91, 0f00800000;
|
|
mul.f32 %f493, %f91, 0f4B800000;
|
|
selp.f32 %f494, %f493, %f91, %p81;
|
|
selp.f32 %f495, 0fC3170000, 0fC2FE0000, %p81;
|
|
mov.b32 %r240, %f494;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f496, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f497, %r243;
|
|
add.f32 %f498, %f495, %f497;
|
|
setp.gt.f32 %p82, %f496, 0f3FB504F3;
|
|
mul.f32 %f499, %f496, 0f3F000000;
|
|
add.f32 %f500, %f498, 0f3F800000;
|
|
selp.f32 %f501, %f500, %f498, %p82;
|
|
selp.f32 %f502, %f499, %f496, %p82;
|
|
add.f32 %f503, %f502, 0fBF800000;
|
|
add.f32 %f504, %f502, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f505, %f504;
|
|
add.f32 %f506, %f503, %f503;
|
|
mul.f32 %f507, %f506, %f505;
|
|
mul.f32 %f508, %f507, %f507;
|
|
mov.f32 %f509, 0f3C4CAF63;
|
|
mov.f32 %f510, 0f3B18F0FE;
|
|
fma.rn.f32 %f511, %f510, %f508, %f509;
|
|
mov.f32 %f512, 0f3DAAAABD;
|
|
fma.rn.f32 %f513, %f511, %f508, %f512;
|
|
mul.rn.f32 %f514, %f513, %f508;
|
|
mul.rn.f32 %f515, %f514, %f507;
|
|
sub.f32 %f516, %f503, %f507;
|
|
add.f32 %f517, %f516, %f516;
|
|
neg.f32 %f518, %f507;
|
|
fma.rn.f32 %f519, %f518, %f503, %f517;
|
|
mul.rn.f32 %f520, %f505, %f519;
|
|
add.f32 %f521, %f515, %f507;
|
|
sub.f32 %f522, %f507, %f521;
|
|
add.f32 %f523, %f515, %f522;
|
|
add.f32 %f524, %f520, %f523;
|
|
add.f32 %f525, %f521, %f524;
|
|
sub.f32 %f526, %f521, %f525;
|
|
add.f32 %f527, %f524, %f526;
|
|
mov.f32 %f528, 0f3F317200;
|
|
mul.rn.f32 %f529, %f501, %f528;
|
|
mov.f32 %f530, 0f35BFBE8E;
|
|
mul.rn.f32 %f531, %f501, %f530;
|
|
add.f32 %f532, %f529, %f525;
|
|
sub.f32 %f533, %f529, %f532;
|
|
add.f32 %f534, %f525, %f533;
|
|
add.f32 %f535, %f527, %f534;
|
|
add.f32 %f536, %f531, %f535;
|
|
add.f32 %f537, %f532, %f536;
|
|
sub.f32 %f538, %f532, %f537;
|
|
add.f32 %f539, %f536, %f538;
|
|
mov.f32 %f540, 0f3EE66666;
|
|
mul.rn.f32 %f541, %f540, %f537;
|
|
neg.f32 %f542, %f541;
|
|
fma.rn.f32 %f543, %f540, %f537, %f542;
|
|
fma.rn.f32 %f544, %f540, %f539, %f543;
|
|
mov.f32 %f545, 0f00000000;
|
|
fma.rn.f32 %f546, %f545, %f537, %f544;
|
|
add.rn.f32 %f547, %f541, %f546;
|
|
neg.f32 %f548, %f547;
|
|
add.rn.f32 %f549, %f541, %f548;
|
|
add.rn.f32 %f550, %f549, %f546;
|
|
mov.b32 %r244, %f547;
|
|
setp.eq.s32 %p83, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f551, %r245;
|
|
add.f32 %f552, %f550, 0f37000000;
|
|
selp.f32 %f92, %f552, %f550, %p83;
|
|
selp.f32 %f553, %f551, %f547, %p83;
|
|
mov.f32 %f554, 0f3FB8AA3B;
|
|
mul.rn.f32 %f555, %f553, %f554;
|
|
cvt.rzi.f32.f32 %f556, %f555;
|
|
abs.f32 %f557, %f556;
|
|
setp.gt.f32 %p84, %f557, 0f42FC0000;
|
|
mov.b32 %r246, %f556;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f558, %r248;
|
|
selp.f32 %f559, %f558, %f556, %p84;
|
|
mov.f32 %f560, 0fBF317218;
|
|
fma.rn.f32 %f561, %f559, %f560, %f553;
|
|
mov.f32 %f562, 0f3102E308;
|
|
fma.rn.f32 %f563, %f559, %f562, %f561;
|
|
mul.f32 %f564, %f563, 0f3FB8AA3B;
|
|
add.f32 %f565, %f559, 0f4B40007F;
|
|
mov.b32 %r249, %f565;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f566, %r250;
|
|
ex2.approx.ftz.f32 %f567, %f564;
|
|
mul.f32 %f93, %f567, %f566;
|
|
setp.eq.f32 %p85, %f93, 0f7F800000;
|
|
mov.f32 %f1063, 0f7F800000;
|
|
@%p85 bra $L__BB0_67;
|
|
|
|
fma.rn.f32 %f1063, %f93, %f92, %f93;
|
|
|
|
$L__BB0_67:
|
|
setp.lt.f32 %p86, %f64, 0f00000000;
|
|
and.pred %p3, %p86, %p72;
|
|
setp.eq.f32 %p88, %f64, 0f00000000;
|
|
@%p88 bra $L__BB0_71;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_71:
|
|
add.f32 %f572, %f64, %f64;
|
|
selp.f32 %f1065, %f572, 0f00000000, %p72;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_68:
|
|
mov.b32 %r251, %f1063;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f568, %r252;
|
|
selp.f32 %f1065, %f568, %f1063, %p3;
|
|
setp.geu.f32 %p89, %f64, 0f00000000;
|
|
@%p89 bra $L__BB0_72;
|
|
|
|
mov.f32 %f569, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f570, %f569;
|
|
setp.eq.f32 %p90, %f570, 0f3EE66666;
|
|
@%p90 bra $L__BB0_72;
|
|
|
|
mov.f32 %f1065, 0f7FFFFFFF;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1001, %f64;
|
|
add.f32 %f573, %f1001, 0f3EE66666;
|
|
mov.b32 %r253, %f573;
|
|
setp.lt.s32 %p92, %r253, 2139095040;
|
|
@%p92 bra $L__BB0_77;
|
|
|
|
abs.f32 %f1002, %f64;
|
|
setp.gtu.f32 %p93, %f1002, 0f7F800000;
|
|
@%p93 bra $L__BB0_76;
|
|
bra.uni $L__BB0_74;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f1065, %f64, 0f3EE66666;
|
|
bra.uni $L__BB0_77;
|
|
|
|
$L__BB0_74:
|
|
abs.f32 %f1003, %f64;
|
|
setp.neu.f32 %p94, %f1003, 0f7F800000;
|
|
@%p94 bra $L__BB0_77;
|
|
|
|
selp.f32 %f1065, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_77:
|
|
setp.eq.f32 %p95, %f64, 0f3F800000;
|
|
selp.f32 %f102, 0f3F800000, %f1065, %p95;
|
|
abs.f32 %f103, %f65;
|
|
setp.lt.f32 %p96, %f103, 0f00800000;
|
|
mul.f32 %f575, %f103, 0f4B800000;
|
|
selp.f32 %f576, %f575, %f103, %p96;
|
|
selp.f32 %f577, 0fC3170000, 0fC2FE0000, %p96;
|
|
mov.b32 %r254, %f576;
|
|
and.b32 %r255, %r254, 8388607;
|
|
or.b32 %r256, %r255, 1065353216;
|
|
mov.b32 %f578, %r256;
|
|
shr.u32 %r257, %r254, 23;
|
|
cvt.rn.f32.u32 %f579, %r257;
|
|
add.f32 %f580, %f577, %f579;
|
|
setp.gt.f32 %p97, %f578, 0f3FB504F3;
|
|
mul.f32 %f581, %f578, 0f3F000000;
|
|
add.f32 %f582, %f580, 0f3F800000;
|
|
selp.f32 %f583, %f582, %f580, %p97;
|
|
selp.f32 %f584, %f581, %f578, %p97;
|
|
add.f32 %f585, %f584, 0fBF800000;
|
|
add.f32 %f586, %f584, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f587, %f586;
|
|
add.f32 %f588, %f585, %f585;
|
|
mul.f32 %f589, %f588, %f587;
|
|
mul.f32 %f590, %f589, %f589;
|
|
mov.f32 %f591, 0f3C4CAF63;
|
|
mov.f32 %f592, 0f3B18F0FE;
|
|
fma.rn.f32 %f593, %f592, %f590, %f591;
|
|
mov.f32 %f594, 0f3DAAAABD;
|
|
fma.rn.f32 %f595, %f593, %f590, %f594;
|
|
mul.rn.f32 %f596, %f595, %f590;
|
|
mul.rn.f32 %f597, %f596, %f589;
|
|
sub.f32 %f598, %f585, %f589;
|
|
add.f32 %f599, %f598, %f598;
|
|
neg.f32 %f600, %f589;
|
|
fma.rn.f32 %f601, %f600, %f585, %f599;
|
|
mul.rn.f32 %f602, %f587, %f601;
|
|
add.f32 %f603, %f597, %f589;
|
|
sub.f32 %f604, %f589, %f603;
|
|
add.f32 %f605, %f597, %f604;
|
|
add.f32 %f606, %f602, %f605;
|
|
add.f32 %f607, %f603, %f606;
|
|
sub.f32 %f608, %f603, %f607;
|
|
add.f32 %f609, %f606, %f608;
|
|
mov.f32 %f610, 0f3F317200;
|
|
mul.rn.f32 %f611, %f583, %f610;
|
|
mov.f32 %f612, 0f35BFBE8E;
|
|
mul.rn.f32 %f613, %f583, %f612;
|
|
add.f32 %f614, %f611, %f607;
|
|
sub.f32 %f615, %f611, %f614;
|
|
add.f32 %f616, %f607, %f615;
|
|
add.f32 %f617, %f609, %f616;
|
|
add.f32 %f618, %f613, %f617;
|
|
add.f32 %f619, %f614, %f618;
|
|
sub.f32 %f620, %f614, %f619;
|
|
add.f32 %f621, %f618, %f620;
|
|
mov.f32 %f622, 0f3EE66666;
|
|
mul.rn.f32 %f623, %f622, %f619;
|
|
neg.f32 %f624, %f623;
|
|
fma.rn.f32 %f625, %f622, %f619, %f624;
|
|
fma.rn.f32 %f626, %f622, %f621, %f625;
|
|
mov.f32 %f627, 0f00000000;
|
|
fma.rn.f32 %f628, %f627, %f619, %f626;
|
|
add.rn.f32 %f629, %f623, %f628;
|
|
neg.f32 %f630, %f629;
|
|
add.rn.f32 %f631, %f623, %f630;
|
|
add.rn.f32 %f632, %f631, %f628;
|
|
mov.b32 %r258, %f629;
|
|
setp.eq.s32 %p98, %r258, 1118925336;
|
|
add.s32 %r259, %r258, -1;
|
|
mov.b32 %f633, %r259;
|
|
add.f32 %f634, %f632, 0f37000000;
|
|
selp.f32 %f104, %f634, %f632, %p98;
|
|
selp.f32 %f635, %f633, %f629, %p98;
|
|
mov.f32 %f636, 0f3FB8AA3B;
|
|
mul.rn.f32 %f637, %f635, %f636;
|
|
cvt.rzi.f32.f32 %f638, %f637;
|
|
abs.f32 %f639, %f638;
|
|
setp.gt.f32 %p99, %f639, 0f42FC0000;
|
|
mov.b32 %r260, %f638;
|
|
and.b32 %r261, %r260, -2147483648;
|
|
or.b32 %r262, %r261, 1123811328;
|
|
mov.b32 %f640, %r262;
|
|
selp.f32 %f641, %f640, %f638, %p99;
|
|
mov.f32 %f642, 0fBF317218;
|
|
fma.rn.f32 %f643, %f641, %f642, %f635;
|
|
mov.f32 %f644, 0f3102E308;
|
|
fma.rn.f32 %f645, %f641, %f644, %f643;
|
|
mul.f32 %f646, %f645, 0f3FB8AA3B;
|
|
add.f32 %f647, %f641, 0f4B40007F;
|
|
mov.b32 %r263, %f647;
|
|
shl.b32 %r264, %r263, 23;
|
|
mov.b32 %f648, %r264;
|
|
ex2.approx.ftz.f32 %f649, %f646;
|
|
mul.f32 %f105, %f649, %f648;
|
|
setp.eq.f32 %p100, %f105, 0f7F800000;
|
|
mov.f32 %f1066, 0f7F800000;
|
|
@%p100 bra $L__BB0_79;
|
|
|
|
fma.rn.f32 %f1066, %f105, %f104, %f105;
|
|
|
|
$L__BB0_79:
|
|
setp.lt.f32 %p101, %f65, 0f00000000;
|
|
and.pred %p4, %p101, %p72;
|
|
setp.eq.f32 %p103, %f65, 0f00000000;
|
|
@%p103 bra $L__BB0_83;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_83:
|
|
add.f32 %f654, %f65, %f65;
|
|
selp.f32 %f1068, %f654, 0f00000000, %p72;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_80:
|
|
mov.b32 %r265, %f1066;
|
|
xor.b32 %r266, %r265, -2147483648;
|
|
mov.b32 %f650, %r266;
|
|
selp.f32 %f1068, %f650, %f1066, %p4;
|
|
setp.geu.f32 %p104, %f65, 0f00000000;
|
|
@%p104 bra $L__BB0_84;
|
|
|
|
mov.f32 %f651, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f652, %f651;
|
|
setp.eq.f32 %p105, %f652, 0f3EE66666;
|
|
@%p105 bra $L__BB0_84;
|
|
|
|
mov.f32 %f1068, 0f7FFFFFFF;
|
|
|
|
$L__BB0_84:
|
|
abs.f32 %f1004, %f65;
|
|
add.f32 %f655, %f1004, 0f3EE66666;
|
|
mov.b32 %r267, %f655;
|
|
setp.lt.s32 %p107, %r267, 2139095040;
|
|
@%p107 bra $L__BB0_89;
|
|
|
|
abs.f32 %f1005, %f65;
|
|
setp.gtu.f32 %p108, %f1005, 0f7F800000;
|
|
@%p108 bra $L__BB0_88;
|
|
bra.uni $L__BB0_86;
|
|
|
|
$L__BB0_88:
|
|
add.f32 %f1068, %f65, 0f3EE66666;
|
|
bra.uni $L__BB0_89;
|
|
|
|
$L__BB0_86:
|
|
abs.f32 %f1006, %f65;
|
|
setp.neu.f32 %p109, %f1006, 0f7F800000;
|
|
@%p109 bra $L__BB0_89;
|
|
|
|
selp.f32 %f1068, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_89:
|
|
setp.eq.f32 %p110, %f65, 0f3F800000;
|
|
mov.f32 %f657, 0f3F800000;
|
|
selp.f32 %f658, 0f3F800000, %f1068, %p110;
|
|
min.f32 %f659, %f90, %f657;
|
|
mov.f32 %f660, 0f00000000;
|
|
max.f32 %f114, %f660, %f659;
|
|
min.f32 %f661, %f102, %f657;
|
|
max.f32 %f115, %f660, %f661;
|
|
min.f32 %f662, %f658, %f657;
|
|
max.f32 %f116, %f660, %f662;
|
|
mov.f32 %f666, 0f3ED55555;
|
|
abs.f32 %f118, %f114;
|
|
setp.lt.f32 %p111, %f118, 0f00800000;
|
|
mul.f32 %f668, %f118, 0f4B800000;
|
|
selp.f32 %f669, %f668, %f118, %p111;
|
|
selp.f32 %f670, 0fC3170000, 0fC2FE0000, %p111;
|
|
mov.b32 %r270, %f669;
|
|
and.b32 %r271, %r270, 8388607;
|
|
or.b32 %r272, %r271, 1065353216;
|
|
mov.b32 %f671, %r272;
|
|
shr.u32 %r273, %r270, 23;
|
|
cvt.rn.f32.u32 %f672, %r273;
|
|
add.f32 %f673, %f670, %f672;
|
|
setp.gt.f32 %p112, %f671, 0f3FB504F3;
|
|
mul.f32 %f674, %f671, 0f3F000000;
|
|
add.f32 %f675, %f673, 0f3F800000;
|
|
selp.f32 %f676, %f675, %f673, %p112;
|
|
selp.f32 %f677, %f674, %f671, %p112;
|
|
add.f32 %f678, %f677, 0fBF800000;
|
|
add.f32 %f679, %f677, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f680, %f679;
|
|
add.f32 %f681, %f678, %f678;
|
|
mul.f32 %f682, %f681, %f680;
|
|
mul.f32 %f683, %f682, %f682;
|
|
mov.f32 %f684, 0f3C4CAF63;
|
|
mov.f32 %f685, 0f3B18F0FE;
|
|
fma.rn.f32 %f686, %f685, %f683, %f684;
|
|
mov.f32 %f687, 0f3DAAAABD;
|
|
fma.rn.f32 %f688, %f686, %f683, %f687;
|
|
mul.rn.f32 %f689, %f688, %f683;
|
|
mul.rn.f32 %f690, %f689, %f682;
|
|
sub.f32 %f691, %f678, %f682;
|
|
add.f32 %f692, %f691, %f691;
|
|
neg.f32 %f693, %f682;
|
|
fma.rn.f32 %f694, %f693, %f678, %f692;
|
|
mul.rn.f32 %f695, %f680, %f694;
|
|
add.f32 %f696, %f690, %f682;
|
|
sub.f32 %f697, %f682, %f696;
|
|
add.f32 %f698, %f690, %f697;
|
|
add.f32 %f699, %f695, %f698;
|
|
add.f32 %f700, %f696, %f699;
|
|
sub.f32 %f701, %f696, %f700;
|
|
add.f32 %f702, %f699, %f701;
|
|
mov.f32 %f703, 0f3F317200;
|
|
mul.rn.f32 %f704, %f676, %f703;
|
|
mov.f32 %f705, 0f35BFBE8E;
|
|
mul.rn.f32 %f706, %f676, %f705;
|
|
add.f32 %f707, %f704, %f700;
|
|
sub.f32 %f708, %f704, %f707;
|
|
add.f32 %f709, %f700, %f708;
|
|
add.f32 %f710, %f702, %f709;
|
|
add.f32 %f711, %f706, %f710;
|
|
add.f32 %f712, %f707, %f711;
|
|
sub.f32 %f713, %f707, %f712;
|
|
add.f32 %f714, %f711, %f713;
|
|
mul.rn.f32 %f715, %f666, %f712;
|
|
neg.f32 %f716, %f715;
|
|
fma.rn.f32 %f717, %f666, %f712, %f716;
|
|
fma.rn.f32 %f718, %f666, %f714, %f717;
|
|
fma.rn.f32 %f719, %f660, %f712, %f718;
|
|
add.rn.f32 %f720, %f715, %f719;
|
|
neg.f32 %f721, %f720;
|
|
add.rn.f32 %f722, %f715, %f721;
|
|
add.rn.f32 %f723, %f722, %f719;
|
|
mov.b32 %r274, %f720;
|
|
setp.eq.s32 %p113, %r274, 1118925336;
|
|
add.s32 %r275, %r274, -1;
|
|
mov.b32 %f724, %r275;
|
|
add.f32 %f725, %f723, 0f37000000;
|
|
selp.f32 %f119, %f725, %f723, %p113;
|
|
selp.f32 %f726, %f724, %f720, %p113;
|
|
mov.f32 %f727, 0f3FB8AA3B;
|
|
mul.rn.f32 %f728, %f726, %f727;
|
|
cvt.rzi.f32.f32 %f729, %f728;
|
|
abs.f32 %f730, %f729;
|
|
setp.gt.f32 %p114, %f730, 0f42FC0000;
|
|
mov.b32 %r276, %f729;
|
|
and.b32 %r277, %r276, -2147483648;
|
|
or.b32 %r278, %r277, 1123811328;
|
|
mov.b32 %f731, %r278;
|
|
selp.f32 %f732, %f731, %f729, %p114;
|
|
mov.f32 %f733, 0fBF317218;
|
|
fma.rn.f32 %f734, %f732, %f733, %f726;
|
|
mov.f32 %f735, 0f3102E308;
|
|
fma.rn.f32 %f736, %f732, %f735, %f734;
|
|
mul.f32 %f737, %f736, 0f3FB8AA3B;
|
|
add.f32 %f738, %f732, 0f4B40007F;
|
|
mov.b32 %r279, %f738;
|
|
shl.b32 %r280, %r279, 23;
|
|
mov.b32 %f739, %r280;
|
|
ex2.approx.ftz.f32 %f740, %f737;
|
|
mul.f32 %f120, %f740, %f739;
|
|
setp.eq.f32 %p115, %f120, 0f7F800000;
|
|
mov.f32 %f1069, 0f7F800000;
|
|
@%p115 bra $L__BB0_91;
|
|
|
|
fma.rn.f32 %f1069, %f120, %f119, %f120;
|
|
|
|
$L__BB0_91:
|
|
mov.f32 %f1026, 0f00000000;
|
|
max.f32 %f1025, %f1026, %f659;
|
|
mov.f32 %f982, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f981, %f982;
|
|
add.f32 %f980, %f981, %f981;
|
|
mov.f32 %f979, 0f3ED55555;
|
|
sub.f32 %f978, %f979, %f980;
|
|
abs.f32 %f977, %f978;
|
|
setp.lt.f32 %p116, %f1025, 0f00000000;
|
|
setp.eq.f32 %p117, %f977, 0f3F800000;
|
|
and.pred %p5, %p116, %p117;
|
|
setp.eq.f32 %p118, %f1025, 0f00000000;
|
|
@%p118 bra $L__BB0_95;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_95:
|
|
mov.f32 %f1043, 0f00000000;
|
|
max.f32 %f1042, %f1043, %f659;
|
|
add.f32 %f745, %f1042, %f1042;
|
|
selp.f32 %f1071, %f745, 0f00000000, %p117;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f1028, 0f00000000;
|
|
max.f32 %f1027, %f1028, %f659;
|
|
mov.b32 %r281, %f1069;
|
|
xor.b32 %r282, %r281, -2147483648;
|
|
mov.b32 %f741, %r282;
|
|
selp.f32 %f1071, %f741, %f1069, %p5;
|
|
setp.geu.f32 %p119, %f1027, 0f00000000;
|
|
@%p119 bra $L__BB0_96;
|
|
|
|
mov.f32 %f742, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f743, %f742;
|
|
setp.eq.f32 %p120, %f743, 0f3ED55555;
|
|
@%p120 bra $L__BB0_96;
|
|
|
|
mov.f32 %f1071, 0f7FFFFFFF;
|
|
|
|
$L__BB0_96:
|
|
mov.f32 %f1031, 0f00000000;
|
|
max.f32 %f1030, %f1031, %f659;
|
|
abs.f32 %f1029, %f1030;
|
|
add.f32 %f746, %f1029, 0f3ED55555;
|
|
mov.b32 %r283, %f746;
|
|
setp.lt.s32 %p122, %r283, 2139095040;
|
|
@%p122 bra $L__BB0_101;
|
|
|
|
mov.f32 %f1036, 0f00000000;
|
|
max.f32 %f1035, %f1036, %f659;
|
|
abs.f32 %f1034, %f1035;
|
|
setp.gtu.f32 %p123, %f1034, 0f7F800000;
|
|
@%p123 bra $L__BB0_100;
|
|
bra.uni $L__BB0_98;
|
|
|
|
$L__BB0_100:
|
|
mov.f32 %f1041, 0f00000000;
|
|
max.f32 %f1040, %f1041, %f659;
|
|
add.f32 %f1071, %f1040, 0f3ED55555;
|
|
bra.uni $L__BB0_101;
|
|
|
|
$L__BB0_98:
|
|
mov.f32 %f1039, 0f00000000;
|
|
max.f32 %f1038, %f1039, %f659;
|
|
abs.f32 %f1037, %f1038;
|
|
setp.neu.f32 %p124, %f1037, 0f7F800000;
|
|
@%p124 bra $L__BB0_101;
|
|
|
|
selp.f32 %f1071, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_101:
|
|
abs.f32 %f129, %f115;
|
|
setp.lt.f32 %p125, %f129, 0f00800000;
|
|
mul.f32 %f748, %f129, 0f4B800000;
|
|
selp.f32 %f749, %f748, %f129, %p125;
|
|
selp.f32 %f750, 0fC3170000, 0fC2FE0000, %p125;
|
|
mov.b32 %r284, %f749;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f751, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f752, %r287;
|
|
add.f32 %f753, %f750, %f752;
|
|
setp.gt.f32 %p126, %f751, 0f3FB504F3;
|
|
mul.f32 %f754, %f751, 0f3F000000;
|
|
add.f32 %f755, %f753, 0f3F800000;
|
|
selp.f32 %f756, %f755, %f753, %p126;
|
|
selp.f32 %f757, %f754, %f751, %p126;
|
|
add.f32 %f758, %f757, 0fBF800000;
|
|
add.f32 %f759, %f757, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f760, %f759;
|
|
add.f32 %f761, %f758, %f758;
|
|
mul.f32 %f762, %f761, %f760;
|
|
mul.f32 %f763, %f762, %f762;
|
|
mov.f32 %f764, 0f3C4CAF63;
|
|
mov.f32 %f765, 0f3B18F0FE;
|
|
fma.rn.f32 %f766, %f765, %f763, %f764;
|
|
mov.f32 %f767, 0f3DAAAABD;
|
|
fma.rn.f32 %f768, %f766, %f763, %f767;
|
|
mul.rn.f32 %f769, %f768, %f763;
|
|
mul.rn.f32 %f770, %f769, %f762;
|
|
sub.f32 %f771, %f758, %f762;
|
|
add.f32 %f772, %f771, %f771;
|
|
neg.f32 %f773, %f762;
|
|
fma.rn.f32 %f774, %f773, %f758, %f772;
|
|
mul.rn.f32 %f775, %f760, %f774;
|
|
add.f32 %f776, %f770, %f762;
|
|
sub.f32 %f777, %f762, %f776;
|
|
add.f32 %f778, %f770, %f777;
|
|
add.f32 %f779, %f775, %f778;
|
|
add.f32 %f780, %f776, %f779;
|
|
sub.f32 %f781, %f776, %f780;
|
|
add.f32 %f782, %f779, %f781;
|
|
mov.f32 %f783, 0f3F317200;
|
|
mul.rn.f32 %f784, %f756, %f783;
|
|
mov.f32 %f785, 0f35BFBE8E;
|
|
mul.rn.f32 %f786, %f756, %f785;
|
|
add.f32 %f787, %f784, %f780;
|
|
sub.f32 %f788, %f784, %f787;
|
|
add.f32 %f789, %f780, %f788;
|
|
add.f32 %f790, %f782, %f789;
|
|
add.f32 %f791, %f786, %f790;
|
|
add.f32 %f792, %f787, %f791;
|
|
sub.f32 %f793, %f787, %f792;
|
|
add.f32 %f794, %f791, %f793;
|
|
mov.f32 %f795, 0f3ED55555;
|
|
mul.rn.f32 %f796, %f795, %f792;
|
|
neg.f32 %f797, %f796;
|
|
fma.rn.f32 %f798, %f795, %f792, %f797;
|
|
fma.rn.f32 %f799, %f795, %f794, %f798;
|
|
mov.f32 %f800, 0f00000000;
|
|
fma.rn.f32 %f801, %f800, %f792, %f799;
|
|
add.rn.f32 %f802, %f796, %f801;
|
|
neg.f32 %f803, %f802;
|
|
add.rn.f32 %f804, %f796, %f803;
|
|
add.rn.f32 %f805, %f804, %f801;
|
|
mov.b32 %r288, %f802;
|
|
setp.eq.s32 %p127, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f806, %r289;
|
|
add.f32 %f807, %f805, 0f37000000;
|
|
selp.f32 %f130, %f807, %f805, %p127;
|
|
selp.f32 %f808, %f806, %f802, %p127;
|
|
mov.f32 %f809, 0f3FB8AA3B;
|
|
mul.rn.f32 %f810, %f808, %f809;
|
|
cvt.rzi.f32.f32 %f811, %f810;
|
|
abs.f32 %f812, %f811;
|
|
setp.gt.f32 %p128, %f812, 0f42FC0000;
|
|
mov.b32 %r290, %f811;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f813, %r292;
|
|
selp.f32 %f814, %f813, %f811, %p128;
|
|
mov.f32 %f815, 0fBF317218;
|
|
fma.rn.f32 %f816, %f814, %f815, %f808;
|
|
mov.f32 %f817, 0f3102E308;
|
|
fma.rn.f32 %f818, %f814, %f817, %f816;
|
|
mul.f32 %f819, %f818, 0f3FB8AA3B;
|
|
add.f32 %f820, %f814, 0f4B40007F;
|
|
mov.b32 %r293, %f820;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f821, %r294;
|
|
ex2.approx.ftz.f32 %f822, %f819;
|
|
mul.f32 %f131, %f822, %f821;
|
|
setp.eq.f32 %p129, %f131, 0f7F800000;
|
|
mov.f32 %f1072, 0f7F800000;
|
|
@%p129 bra $L__BB0_103;
|
|
|
|
fma.rn.f32 %f1072, %f131, %f130, %f131;
|
|
|
|
$L__BB0_103:
|
|
setp.lt.f32 %p130, %f115, 0f00000000;
|
|
and.pred %p6, %p130, %p117;
|
|
setp.eq.f32 %p132, %f115, 0f00000000;
|
|
@%p132 bra $L__BB0_107;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_107:
|
|
add.f32 %f827, %f115, %f115;
|
|
selp.f32 %f1074, %f827, 0f00000000, %p117;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_104:
|
|
mov.b32 %r295, %f1072;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f823, %r296;
|
|
selp.f32 %f1074, %f823, %f1072, %p6;
|
|
setp.geu.f32 %p133, %f115, 0f00000000;
|
|
@%p133 bra $L__BB0_108;
|
|
|
|
mov.f32 %f824, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f825, %f824;
|
|
setp.eq.f32 %p134, %f825, 0f3ED55555;
|
|
@%p134 bra $L__BB0_108;
|
|
|
|
mov.f32 %f1074, 0f7FFFFFFF;
|
|
|
|
$L__BB0_108:
|
|
mov.f32 %f1009, 0f00000000;
|
|
max.f32 %f1008, %f1009, %f661;
|
|
abs.f32 %f1007, %f1008;
|
|
add.f32 %f828, %f1007, 0f3ED55555;
|
|
mov.b32 %r297, %f828;
|
|
setp.lt.s32 %p136, %r297, 2139095040;
|
|
@%p136 bra $L__BB0_113;
|
|
|
|
mov.f32 %f1012, 0f00000000;
|
|
max.f32 %f1011, %f1012, %f661;
|
|
abs.f32 %f1010, %f1011;
|
|
setp.gtu.f32 %p137, %f1010, 0f7F800000;
|
|
@%p137 bra $L__BB0_112;
|
|
bra.uni $L__BB0_110;
|
|
|
|
$L__BB0_112:
|
|
add.f32 %f1074, %f115, 0f3ED55555;
|
|
bra.uni $L__BB0_113;
|
|
|
|
$L__BB0_110:
|
|
mov.f32 %f1015, 0f00000000;
|
|
max.f32 %f1014, %f1015, %f661;
|
|
abs.f32 %f1013, %f1014;
|
|
setp.neu.f32 %p138, %f1013, 0f7F800000;
|
|
@%p138 bra $L__BB0_113;
|
|
|
|
selp.f32 %f1074, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_113:
|
|
abs.f32 %f140, %f116;
|
|
setp.lt.f32 %p139, %f140, 0f00800000;
|
|
mul.f32 %f830, %f140, 0f4B800000;
|
|
selp.f32 %f831, %f830, %f140, %p139;
|
|
selp.f32 %f832, 0fC3170000, 0fC2FE0000, %p139;
|
|
mov.b32 %r298, %f831;
|
|
and.b32 %r299, %r298, 8388607;
|
|
or.b32 %r300, %r299, 1065353216;
|
|
mov.b32 %f833, %r300;
|
|
shr.u32 %r301, %r298, 23;
|
|
cvt.rn.f32.u32 %f834, %r301;
|
|
add.f32 %f835, %f832, %f834;
|
|
setp.gt.f32 %p140, %f833, 0f3FB504F3;
|
|
mul.f32 %f836, %f833, 0f3F000000;
|
|
add.f32 %f837, %f835, 0f3F800000;
|
|
selp.f32 %f838, %f837, %f835, %p140;
|
|
selp.f32 %f839, %f836, %f833, %p140;
|
|
add.f32 %f840, %f839, 0fBF800000;
|
|
add.f32 %f841, %f839, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f842, %f841;
|
|
add.f32 %f843, %f840, %f840;
|
|
mul.f32 %f844, %f843, %f842;
|
|
mul.f32 %f845, %f844, %f844;
|
|
mov.f32 %f846, 0f3C4CAF63;
|
|
mov.f32 %f847, 0f3B18F0FE;
|
|
fma.rn.f32 %f848, %f847, %f845, %f846;
|
|
mov.f32 %f849, 0f3DAAAABD;
|
|
fma.rn.f32 %f850, %f848, %f845, %f849;
|
|
mul.rn.f32 %f851, %f850, %f845;
|
|
mul.rn.f32 %f852, %f851, %f844;
|
|
sub.f32 %f853, %f840, %f844;
|
|
add.f32 %f854, %f853, %f853;
|
|
neg.f32 %f855, %f844;
|
|
fma.rn.f32 %f856, %f855, %f840, %f854;
|
|
mul.rn.f32 %f857, %f842, %f856;
|
|
add.f32 %f858, %f852, %f844;
|
|
sub.f32 %f859, %f844, %f858;
|
|
add.f32 %f860, %f852, %f859;
|
|
add.f32 %f861, %f857, %f860;
|
|
add.f32 %f862, %f858, %f861;
|
|
sub.f32 %f863, %f858, %f862;
|
|
add.f32 %f864, %f861, %f863;
|
|
mov.f32 %f865, 0f3F317200;
|
|
mul.rn.f32 %f866, %f838, %f865;
|
|
mov.f32 %f867, 0f35BFBE8E;
|
|
mul.rn.f32 %f868, %f838, %f867;
|
|
add.f32 %f869, %f866, %f862;
|
|
sub.f32 %f870, %f866, %f869;
|
|
add.f32 %f871, %f862, %f870;
|
|
add.f32 %f872, %f864, %f871;
|
|
add.f32 %f873, %f868, %f872;
|
|
add.f32 %f874, %f869, %f873;
|
|
sub.f32 %f875, %f869, %f874;
|
|
add.f32 %f876, %f873, %f875;
|
|
mov.f32 %f877, 0f3ED55555;
|
|
mul.rn.f32 %f878, %f877, %f874;
|
|
neg.f32 %f879, %f878;
|
|
fma.rn.f32 %f880, %f877, %f874, %f879;
|
|
fma.rn.f32 %f881, %f877, %f876, %f880;
|
|
mov.f32 %f882, 0f00000000;
|
|
fma.rn.f32 %f883, %f882, %f874, %f881;
|
|
add.rn.f32 %f884, %f878, %f883;
|
|
neg.f32 %f885, %f884;
|
|
add.rn.f32 %f886, %f878, %f885;
|
|
add.rn.f32 %f887, %f886, %f883;
|
|
mov.b32 %r302, %f884;
|
|
setp.eq.s32 %p141, %r302, 1118925336;
|
|
add.s32 %r303, %r302, -1;
|
|
mov.b32 %f888, %r303;
|
|
add.f32 %f889, %f887, 0f37000000;
|
|
selp.f32 %f141, %f889, %f887, %p141;
|
|
selp.f32 %f890, %f888, %f884, %p141;
|
|
mov.f32 %f891, 0f3FB8AA3B;
|
|
mul.rn.f32 %f892, %f890, %f891;
|
|
cvt.rzi.f32.f32 %f893, %f892;
|
|
abs.f32 %f894, %f893;
|
|
setp.gt.f32 %p142, %f894, 0f42FC0000;
|
|
mov.b32 %r304, %f893;
|
|
and.b32 %r305, %r304, -2147483648;
|
|
or.b32 %r306, %r305, 1123811328;
|
|
mov.b32 %f895, %r306;
|
|
selp.f32 %f896, %f895, %f893, %p142;
|
|
mov.f32 %f897, 0fBF317218;
|
|
fma.rn.f32 %f898, %f896, %f897, %f890;
|
|
mov.f32 %f899, 0f3102E308;
|
|
fma.rn.f32 %f900, %f896, %f899, %f898;
|
|
mul.f32 %f901, %f900, 0f3FB8AA3B;
|
|
add.f32 %f902, %f896, 0f4B40007F;
|
|
mov.b32 %r307, %f902;
|
|
shl.b32 %r308, %r307, 23;
|
|
mov.b32 %f903, %r308;
|
|
ex2.approx.ftz.f32 %f904, %f901;
|
|
mul.f32 %f142, %f904, %f903;
|
|
setp.eq.f32 %p143, %f142, 0f7F800000;
|
|
mov.f32 %f1075, 0f7F800000;
|
|
@%p143 bra $L__BB0_115;
|
|
|
|
fma.rn.f32 %f1075, %f142, %f141, %f142;
|
|
|
|
$L__BB0_115:
|
|
setp.lt.f32 %p144, %f116, 0f00000000;
|
|
and.pred %p7, %p144, %p117;
|
|
setp.eq.f32 %p146, %f116, 0f00000000;
|
|
@%p146 bra $L__BB0_119;
|
|
bra.uni $L__BB0_116;
|
|
|
|
$L__BB0_119:
|
|
add.f32 %f909, %f116, %f116;
|
|
selp.f32 %f1077, %f909, 0f00000000, %p117;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_116:
|
|
mov.b32 %r309, %f1075;
|
|
xor.b32 %r310, %r309, -2147483648;
|
|
mov.b32 %f905, %r310;
|
|
selp.f32 %f1077, %f905, %f1075, %p7;
|
|
setp.geu.f32 %p147, %f116, 0f00000000;
|
|
@%p147 bra $L__BB0_120;
|
|
|
|
mov.f32 %f906, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f907, %f906;
|
|
setp.eq.f32 %p148, %f907, 0f3ED55555;
|
|
@%p148 bra $L__BB0_120;
|
|
|
|
mov.f32 %f1077, 0f7FFFFFFF;
|
|
|
|
$L__BB0_120:
|
|
mov.f32 %f1018, 0f00000000;
|
|
max.f32 %f1017, %f1018, %f662;
|
|
abs.f32 %f1016, %f1017;
|
|
add.f32 %f910, %f1016, 0f3ED55555;
|
|
mov.b32 %r311, %f910;
|
|
setp.lt.s32 %p150, %r311, 2139095040;
|
|
@%p150 bra $L__BB0_125;
|
|
|
|
mov.f32 %f1021, 0f00000000;
|
|
max.f32 %f1020, %f1021, %f662;
|
|
abs.f32 %f1019, %f1020;
|
|
setp.gtu.f32 %p151, %f1019, 0f7F800000;
|
|
@%p151 bra $L__BB0_124;
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1077, %f116, 0f3ED55555;
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f1024, 0f00000000;
|
|
max.f32 %f1023, %f1024, %f662;
|
|
abs.f32 %f1022, %f1023;
|
|
setp.neu.f32 %p152, %f1022, 0f7F800000;
|
|
@%p152 bra $L__BB0_125;
|
|
|
|
selp.f32 %f1077, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f1033, 0f00000000;
|
|
max.f32 %f1032, %f1033, %f659;
|
|
ld.const.u64 %rd104, [params+144];
|
|
cvta.to.global.u64 %rd103, %rd104;
|
|
ld.const.u32 %r357, [params+136];
|
|
mad.lo.s32 %r356, %r357, %r4, %r3;
|
|
cvt.u64.u32 %rd102, %r356;
|
|
fma.rn.f32 %f911, %f1071, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p153, %f1032, 0f3F800000;
|
|
mov.f32 %f912, 0f3F800000;
|
|
selp.f32 %f913, 0f3F7FFFFF, %f911, %p153;
|
|
mul.f32 %f914, %f1032, 0f414EB852;
|
|
setp.lt.f32 %p154, %f1032, 0f3B4D2E1C;
|
|
selp.f32 %f915, %f914, %f913, %p154;
|
|
fma.rn.f32 %f916, %f1074, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p155, %f115, 0f3F800000;
|
|
selp.f32 %f917, 0f3F7FFFFF, %f916, %p155;
|
|
mul.f32 %f918, %f115, 0f414EB852;
|
|
setp.lt.f32 %p156, %f115, 0f3B4D2E1C;
|
|
selp.f32 %f919, %f918, %f917, %p156;
|
|
fma.rn.f32 %f920, %f1077, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p157, %f116, 0f3F800000;
|
|
selp.f32 %f921, 0f3F7FFFFF, %f920, %p157;
|
|
mul.f32 %f922, %f116, 0f414EB852;
|
|
setp.lt.f32 %p158, %f116, 0f3B4D2E1C;
|
|
selp.f32 %f923, %f922, %f921, %p158;
|
|
min.f32 %f924, %f915, %f912;
|
|
mov.f32 %f925, 0f00000000;
|
|
max.f32 %f926, %f925, %f924;
|
|
mul.f32 %f927, %f926, 0f43800000;
|
|
cvt.rzi.u32.f32 %r312, %f927;
|
|
min.u32 %r313, %r312, 255;
|
|
min.f32 %f928, %f919, %f912;
|
|
max.f32 %f929, %f925, %f928;
|
|
mul.f32 %f930, %f929, 0f43800000;
|
|
cvt.rzi.u32.f32 %r314, %f930;
|
|
min.u32 %r315, %r314, 255;
|
|
min.f32 %f931, %f923, %f912;
|
|
max.f32 %f932, %f925, %f931;
|
|
mul.f32 %f933, %f932, 0f43800000;
|
|
cvt.rzi.u32.f32 %r316, %f933;
|
|
min.u32 %r317, %r316, 255;
|
|
shl.b64 %rd63, %rd102, 2;
|
|
add.s64 %rd64, %rd103, %rd63;
|
|
cvt.u16.u32 %rs19, %r317;
|
|
cvt.u16.u32 %rs20, %r315;
|
|
cvt.u16.u32 %rs21, %r313;
|
|
mov.u16 %rs22, 255;
|
|
st.global.v4.u8 [%rd64], {%rs21, %rs20, %rs19, %rs22};
|
|
|
|
$L__BB0_126:
|
|
ld.const.u32 %r358, [params+104];
|
|
and.b32 %r318, %r358, 4;
|
|
setp.eq.s32 %p159, %r318, 0;
|
|
@%p159 bra $L__BB0_130;
|
|
|
|
ld.const.u32 %r319, [params+108];
|
|
setp.eq.s32 %p160, %r319, 0;
|
|
ld.const.u64 %rd65, [params+224];
|
|
cvta.to.global.u64 %rd66, %rd65;
|
|
ld.const.u32 %r320, [params+216];
|
|
mad.lo.s32 %r321, %r320, %r4, %r3;
|
|
mul.wide.u32 %rd67, %r321, 8;
|
|
add.s64 %rd20, %rd66, %rd67;
|
|
@%p160 bra $L__BB0_129;
|
|
|
|
ld.global.v4.u16 {%rs30, %rs31, %rs32, %rs33}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f934, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f935, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f936, %rs32;}
|
|
|
|
// end inline asm
|
|
add.f32 %f937, %f63, %f934;
|
|
add.f32 %f938, %f64, %f935;
|
|
add.f32 %f939, %f65, %f936;
|
|
mov.f32 %f940, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f939;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f938;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f937;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f940;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs26, %rs27, %rs28, %rs29};
|
|
bra.uni $L__BB0_130;
|
|
|
|
$L__BB0_129:
|
|
mov.f32 %f944, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f944;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f65;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f64;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f63;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs34, %rs35, %rs36, %rs37};
|
|
|
|
$L__BB0_130:
|
|
ld.const.u32 %r359, [params+104];
|
|
and.b32 %r322, %r359, 64;
|
|
setp.eq.s32 %p161, %r322, 0;
|
|
@%p161 bra $L__BB0_152;
|
|
|
|
ld.const.u64 %rd68, [params+208];
|
|
cvta.to.global.u64 %rd69, %rd68;
|
|
ld.const.u32 %r323, [params+200];
|
|
mad.lo.s32 %r324, %r323, %r4, %r3;
|
|
mul.f32 %f945, %f168, 0f3F000000;
|
|
mov.f32 %f946, 0f3F000000;
|
|
sub.f32 %f947, %f946, %f945;
|
|
mul.f32 %f948, %f947, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r325, %f948;
|
|
mul.f32 %f949, %f169, 0f3F000000;
|
|
sub.f32 %f950, %f946, %f949;
|
|
mul.f32 %f951, %f950, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r326, %f951;
|
|
mul.f32 %f952, %f170, 0f3F000000;
|
|
sub.f32 %f953, %f946, %f952;
|
|
mul.f32 %f954, %f953, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r327, %f954;
|
|
mul.wide.u32 %rd70, %r324, 4;
|
|
add.s64 %rd71, %rd69, %rd70;
|
|
cvt.u16.u32 %rs38, %r327;
|
|
cvt.u16.u32 %rs39, %r326;
|
|
cvt.u16.u32 %rs40, %r325;
|
|
mov.u16 %rs41, 255;
|
|
st.global.v4.u8 [%rd71], {%rs40, %rs39, %rs38, %rs41};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f965, 0f00000000;
|
|
mov.f32 %f966, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f966;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f965;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f965;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f965;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs57, %rs58, %rs59, %rs60};
|
|
|
|
$L__BB0_140:
|
|
and.b32 %r339, %r6, 64;
|
|
setp.eq.s32 %p169, %r339, 0;
|
|
@%p169 bra $L__BB0_152;
|
|
|
|
ld.const.u64 %rd83, [params+208];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r340, [params+200];
|
|
mad.lo.s32 %r341, %r340, %r4, %r3;
|
|
mul.wide.u32 %rd85, %r341, 4;
|
|
add.s64 %rd86, %rd84, %rd85;
|
|
mov.u16 %rs61, 0;
|
|
mov.u16 %rs62, 255;
|
|
st.global.v4.u8 [%rd86], {%rs61, %rs61, %rs61, %rs62};
|
|
|
|
$L__BB0_152:
|
|
ret;
|
|
|
|
}
|
|
|