2712 lines
76 KiB
Plaintext
2712 lines
76 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<205>;
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.reg .b16 %rs<180>;
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.reg .f32 %f<1488>;
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.reg .b32 %r<468>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<123>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r62), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r63), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+616];
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abs.s32 %r4, %r3;
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ld.const.u32 %r5, [params+540];
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ld.const.u64 %rd33, [params+400];
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cvta.to.global.u64 %rd34, %rd33;
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ld.const.u32 %r68, [params+392];
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mad.lo.s32 %r69, %r68, %r63, %r62;
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mul.wide.u32 %rd35, %r69, 4;
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add.s64 %rd2, %rd34, %rd35;
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ld.global.v2.u8 {%rs16, %rs175}, [%rd2];
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or.b16 %rs18, %rs16, %rs175;
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and.b16 %rs19, %rs18, 255;
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setp.eq.s16 %p10, %rs19, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs174, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs174, [%rd2+2];
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setp.eq.s16 %p11, %rs174, 0;
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mov.f32 %f1406, 0f00000000;
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mov.u16 %rs175, 0;
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mov.f32 %f1407, %f1406;
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mov.f32 %f1408, %f1406;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f275, %rs16;
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div.rn.f32 %f276, %f275, 0f437F0000;
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fma.rn.f32 %f277, %f276, 0f40000000, 0fBF800000;
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and.b16 %rs22, %rs175, 255;
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cvt.rn.f32.u16 %f278, %rs22;
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div.rn.f32 %f279, %f278, 0f437F0000;
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fma.rn.f32 %f280, %f279, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f281, %rs174;
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div.rn.f32 %f282, %f281, 0f437F0000;
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fma.rn.f32 %f283, %f282, 0f40000000, 0fBF800000;
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mul.f32 %f284, %f280, %f280;
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fma.rn.f32 %f285, %f277, %f277, %f284;
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fma.rn.f32 %f286, %f283, %f283, %f285;
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sqrt.rn.f32 %f287, %f286;
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rcp.rn.f32 %f288, %f287;
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mul.f32 %f1408, %f288, %f283;
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mul.f32 %f1407, %f288, %f280;
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mul.f32 %f1406, %f277, %f288;
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$L__BB0_4:
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ld.const.v2.u32 {%r70, %r71}, [params];
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add.s32 %r6, %r70, %r62;
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add.s32 %r7, %r71, %r63;
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setp.eq.f32 %p12, %f1406, 0f00000000;
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setp.eq.f32 %p13, %f1407, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1408, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_165;
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bra.uni $L__BB0_5;
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$L__BB0_165:
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ld.const.u32 %r59, [params+104];
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and.b32 %r432, %r59, 1;
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setp.eq.b32 %p194, %r432, 1;
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mov.pred %p195, 0;
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xor.pred %p196, %p194, %p195;
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not.pred %p197, %p196;
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@%p197 bra $L__BB0_167;
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ld.const.u64 %rd96, [params+144];
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cvta.to.global.u64 %rd97, %rd96;
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ld.const.u32 %r433, [params+136];
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mad.lo.s32 %r434, %r433, %r7, %r6;
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mul.wide.u32 %rd98, %r434, 4;
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add.s64 %rd99, %rd97, %rd98;
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mov.u16 %rs111, 0;
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st.global.v4.u8 [%rd99], {%rs111, %rs111, %rs111, %rs111};
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$L__BB0_167:
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and.b32 %r435, %r59, 8;
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setp.eq.s32 %p198, %r435, 0;
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@%p198 bra $L__BB0_169;
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ld.const.u64 %rd100, [params+192];
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cvta.to.global.u64 %rd101, %rd100;
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ld.const.u32 %r436, [params+184];
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mad.lo.s32 %r437, %r436, %r7, %r6;
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mov.f32 %f1361, 0f00000000;
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cvt.rzi.u32.f32 %r438, %f1361;
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mul.wide.u32 %rd102, %r437, 2;
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add.s64 %rd103, %rd101, %rd102;
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mov.u16 %rs112, 0;
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cvt.u16.u32 %rs113, %r438;
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st.global.v2.u8 [%rd103], {%rs113, %rs112};
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$L__BB0_169:
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and.b32 %r439, %r59, 4;
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setp.eq.s32 %p199, %r439, 0;
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ld.const.u32 %r467, [params+108];
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@%p199 bra $L__BB0_173;
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setp.eq.s32 %p200, %r467, 0;
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ld.const.u64 %rd104, [params+224];
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cvta.to.global.u64 %rd105, %rd104;
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ld.const.u32 %r440, [params+216];
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mad.lo.s32 %r441, %r440, %r7, %r6;
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mul.wide.u32 %rd106, %r441, 8;
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add.s64 %rd28, %rd105, %rd106;
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@%p200 bra $L__BB0_172;
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ld.global.v4.u16 {%rs120, %rs121, %rs122, %rs123}, [%rd28];
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// begin inline asm
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{ cvt.f32.f16 %f1362, %rs120;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1363, %rs121;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1364, %rs122;}
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// end inline asm
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add.f32 %f1365, %f1362, 0f00000000;
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add.f32 %f1366, %f1363, 0f00000000;
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add.f32 %f1367, %f1364, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs119, %f1367;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs118, %f1366;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs117, %f1365;}
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// end inline asm
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mov.u16 %rs124, 0;
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st.global.v4.u16 [%rd28], {%rs117, %rs118, %rs119, %rs124};
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bra.uni $L__BB0_173;
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$L__BB0_5:
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ld.const.u64 %rd36, [params+432];
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cvta.to.global.u64 %rd37, %rd36;
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ld.const.u32 %r74, [params+424];
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mad.lo.s32 %r75, %r74, %r63, %r62;
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mul.wide.u32 %rd38, %r75, 12;
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add.s64 %rd39, %rd37, %rd38;
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ld.global.f32 %f10, [%rd39];
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mul.f32 %f289, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd39+4];
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mul.f32 %f290, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd39+8];
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mul.f32 %f291, %f12, 0f3456BF95;
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abs.f32 %f13, %f1406;
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div.rn.f32 %f292, %f289, %f13;
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abs.f32 %f293, %f1407;
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div.rn.f32 %f294, %f290, %f293;
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abs.f32 %f14, %f1408;
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div.rn.f32 %f295, %f291, %f14;
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abs.f32 %f296, %f292;
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abs.f32 %f297, %f294;
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abs.f32 %f298, %f295;
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mov.f32 %f299, 0f38D1B717;
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max.f32 %f300, %f296, %f299;
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max.f32 %f301, %f297, %f299;
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max.f32 %f302, %f298, %f299;
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fma.rn.f32 %f15, %f1406, %f300, %f10;
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fma.rn.f32 %f16, %f1407, %f301, %f11;
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fma.rn.f32 %f17, %f1408, %f302, %f12;
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ld.const.u64 %rd40, [params+464];
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cvta.to.global.u64 %rd41, %rd40;
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ld.const.u32 %r76, [params+456];
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mad.lo.s32 %r77, %r76, %r63, %r62;
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mul.wide.u32 %rd42, %r77, 4;
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add.s64 %rd3, %rd41, %rd42;
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ld.global.v2.u8 {%rs24, %rs178}, [%rd3];
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or.b16 %rs26, %rs24, %rs178;
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and.b16 %rs27, %rs26, 255;
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setp.eq.s16 %p17, %rs27, 0;
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@%p17 bra $L__BB0_7;
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ld.global.u8 %rs176, [%rd3+2];
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bra.uni $L__BB0_8;
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$L__BB0_7:
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ld.global.u8 %rs176, [%rd3+2];
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setp.eq.s16 %p18, %rs176, 0;
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mov.f32 %f1409, 0f00000000;
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mov.u16 %rs178, 0;
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mov.u16 %rs179, %rs178;
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mov.f32 %f1410, %f1409;
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mov.f32 %f1411, %f1409;
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@%p18 bra $L__BB0_9;
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$L__BB0_8:
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mov.u16 %rs179, %rs178;
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cvt.rn.f32.u16 %f306, %rs24;
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div.rn.f32 %f307, %f306, 0f437F0000;
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fma.rn.f32 %f308, %f307, 0f40000000, 0fBF800000;
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and.b16 %rs32, %rs179, 255;
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cvt.rn.f32.u16 %f309, %rs32;
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div.rn.f32 %f310, %f309, 0f437F0000;
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fma.rn.f32 %f311, %f310, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f312, %rs176;
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div.rn.f32 %f313, %f312, 0f437F0000;
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fma.rn.f32 %f314, %f313, 0f40000000, 0fBF800000;
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mul.f32 %f315, %f311, %f311;
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fma.rn.f32 %f316, %f308, %f308, %f315;
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fma.rn.f32 %f317, %f314, %f314, %f316;
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sqrt.rn.f32 %f318, %f317;
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rcp.rn.f32 %f319, %f318;
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mul.f32 %f1411, %f319, %f314;
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mul.f32 %f1410, %f319, %f311;
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mul.f32 %f1409, %f308, %f319;
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mov.u16 %rs178, %rs176;
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$L__BB0_9:
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mul.f32 %f323, %f1407, %f1411;
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mul.f32 %f324, %f1408, %f1410;
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sub.f32 %f325, %f323, %f324;
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mul.f32 %f326, %f1408, %f1409;
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mul.f32 %f327, %f1406, %f1411;
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sub.f32 %f328, %f326, %f327;
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mul.f32 %f329, %f1406, %f1410;
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mul.f32 %f330, %f1407, %f1409;
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sub.f32 %f331, %f329, %f330;
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ld.global.u8 %rs34, [%rd3+3];
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setp.eq.s16 %p19, %rs34, 0;
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selp.f32 %f24, 0fBF800000, 0f3F800000, %p19;
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mul.f32 %f332, %f325, %f24;
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mul.f32 %f333, %f328, %f24;
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mul.f32 %f334, %f331, %f24;
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mul.f32 %f335, %f332, 0f00000000;
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mul.f32 %f336, %f333, 0f00000000;
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mul.f32 %f337, %f334, 0f00000000;
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fma.rn.f32 %f338, %f1409, 0f3F5105EC, %f335;
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fma.rn.f32 %f339, %f1410, 0f3F5105EC, %f336;
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fma.rn.f32 %f340, %f1411, 0f3F5105EC, %f337;
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mul.f32 %f25, %f1406, 0f3F13CD3A;
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add.f32 %f26, %f25, %f338;
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mul.f32 %f27, %f1407, 0f3F13CD3A;
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add.f32 %f28, %f27, %f339;
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mul.f32 %f29, %f1408, 0f3F13CD3A;
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add.f32 %f30, %f29, %f340;
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or.b16 %rs35, %rs24, %rs179;
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or.b16 %rs15, %rs35, %rs178;
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and.b16 %rs36, %rs15, 255;
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setp.eq.s16 %p20, %rs36, 0;
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mov.f32 %f1415, 0f00000000;
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mov.f32 %f1412, %f1415;
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mov.f32 %f1413, %f1415;
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mov.f32 %f1414, %f1415;
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@%p20 bra $L__BB0_11;
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cvt.rn.f32.u16 %f341, %rs24;
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div.rn.f32 %f342, %f341, 0f437F0000;
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fma.rn.f32 %f343, %f342, 0f40000000, 0fBF800000;
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and.b16 %rs38, %rs179, 255;
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cvt.rn.f32.u16 %f344, %rs38;
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div.rn.f32 %f345, %f344, 0f437F0000;
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fma.rn.f32 %f346, %f345, 0f40000000, 0fBF800000;
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and.b16 %rs39, %rs178, 255;
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cvt.rn.f32.u16 %f347, %rs39;
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div.rn.f32 %f348, %f347, 0f437F0000;
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fma.rn.f32 %f349, %f348, 0f40000000, 0fBF800000;
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mul.f32 %f350, %f346, %f346;
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fma.rn.f32 %f351, %f343, %f343, %f350;
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fma.rn.f32 %f352, %f349, %f349, %f351;
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sqrt.rn.f32 %f353, %f352;
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rcp.rn.f32 %f354, %f353;
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mul.f32 %f1414, %f354, %f349;
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mul.f32 %f1413, %f354, %f346;
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mul.f32 %f1412, %f343, %f354;
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$L__BB0_11:
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mul.f32 %f358, %f1407, %f1414;
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mul.f32 %f359, %f1408, %f1413;
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sub.f32 %f360, %f358, %f359;
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mul.f32 %f361, %f1408, %f1412;
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mul.f32 %f362, %f1406, %f1414;
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sub.f32 %f363, %f361, %f362;
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mul.f32 %f364, %f1406, %f1413;
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mul.f32 %f365, %f1407, %f1412;
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sub.f32 %f366, %f364, %f365;
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mul.f32 %f367, %f360, %f24;
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mul.f32 %f368, %f363, %f24;
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mul.f32 %f369, %f366, %f24;
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mul.f32 %f370, %f1412, 0f3ED105EC;
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mul.f32 %f371, %f1413, 0f3ED105EC;
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mul.f32 %f372, %f1414, 0f3ED105EC;
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mul.f32 %f373, %f367, 0f3F3504F3;
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mul.f32 %f374, %f368, 0f3F3504F3;
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mul.f32 %f375, %f369, 0f3F3504F3;
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sub.f32 %f376, %f373, %f370;
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sub.f32 %f377, %f374, %f371;
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sub.f32 %f378, %f375, %f372;
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add.f32 %f37, %f25, %f376;
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add.f32 %f38, %f27, %f377;
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add.f32 %f39, %f29, %f378;
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mov.f32 %f1416, %f1415;
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mov.f32 %f1417, %f1415;
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@%p20 bra $L__BB0_13;
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cvt.rn.f32.u16 %f379, %rs24;
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div.rn.f32 %f380, %f379, 0f437F0000;
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fma.rn.f32 %f381, %f380, 0f40000000, 0fBF800000;
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and.b16 %rs42, %rs179, 255;
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cvt.rn.f32.u16 %f382, %rs42;
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div.rn.f32 %f383, %f382, 0f437F0000;
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fma.rn.f32 %f384, %f383, 0f40000000, 0fBF800000;
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and.b16 %rs43, %rs178, 255;
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cvt.rn.f32.u16 %f385, %rs43;
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div.rn.f32 %f386, %f385, 0f437F0000;
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fma.rn.f32 %f387, %f386, 0f40000000, 0fBF800000;
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mul.f32 %f388, %f384, %f384;
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fma.rn.f32 %f389, %f381, %f381, %f388;
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fma.rn.f32 %f390, %f387, %f387, %f389;
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sqrt.rn.f32 %f391, %f390;
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rcp.rn.f32 %f392, %f391;
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mul.f32 %f1417, %f392, %f387;
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mul.f32 %f1416, %f392, %f384;
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mul.f32 %f1415, %f381, %f392;
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$L__BB0_13:
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mul.f32 %f398, %f1407, %f1417;
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mul.f32 %f399, %f1408, %f1416;
|
|
sub.f32 %f400, %f398, %f399;
|
|
mul.f32 %f401, %f1408, %f1415;
|
|
mul.f32 %f402, %f1406, %f1417;
|
|
sub.f32 %f403, %f401, %f402;
|
|
mul.f32 %f404, %f1406, %f1416;
|
|
mul.f32 %f405, %f1407, %f1415;
|
|
sub.f32 %f406, %f404, %f405;
|
|
mul.f32 %f407, %f400, %f24;
|
|
mul.f32 %f408, %f403, %f24;
|
|
mul.f32 %f409, %f406, %f24;
|
|
mul.f32 %f410, %f1415, 0f3ED105EC;
|
|
mul.f32 %f411, %f1416, 0f3ED105EC;
|
|
mul.f32 %f412, %f1417, 0f3ED105EC;
|
|
mul.f32 %f413, %f407, 0fBF3504F3;
|
|
mul.f32 %f414, %f408, 0fBF3504F3;
|
|
mul.f32 %f415, %f409, 0fBF3504F3;
|
|
sub.f32 %f416, %f413, %f410;
|
|
sub.f32 %f417, %f414, %f411;
|
|
sub.f32 %f418, %f415, %f412;
|
|
add.f32 %f46, %f25, %f416;
|
|
add.f32 %f47, %f27, %f417;
|
|
add.f32 %f48, %f29, %f418;
|
|
ld.const.u64 %rd43, [params+128];
|
|
cvta.to.global.u64 %rd44, %rd43;
|
|
ld.const.u32 %r79, [params+120];
|
|
mad.lo.s32 %r80, %r79, %r63, %r62;
|
|
mul.wide.u32 %rd45, %r80, 4;
|
|
add.s64 %rd46, %rd44, %rd45;
|
|
ld.global.u32 %r458, [%rd46];
|
|
setp.lt.s32 %p23, %r4, 1;
|
|
mov.pred %p22, 0;
|
|
mov.f32 %f1426, 0f00000000;
|
|
mov.u32 %r454, 0;
|
|
mov.f32 %f1427, %f1426;
|
|
mov.f32 %f1428, %f1426;
|
|
mov.f32 %f1429, %f1426;
|
|
mov.f32 %f1430, %f1426;
|
|
mov.pred %p204, %p22;
|
|
@%p23 bra $L__BB0_33;
|
|
|
|
ld.const.f32 %f49, [params+620];
|
|
ld.const.u64 %rd47, [params+624];
|
|
cvta.to.global.u64 %rd4, %rd47;
|
|
ld.const.u64 %rd48, [params+640];
|
|
cvta.to.global.u64 %rd49, %rd48;
|
|
ld.const.u32 %r83, [params+632];
|
|
and.b32 %r84, %r63, 255;
|
|
and.b32 %r85, %r62, 255;
|
|
mad.lo.s32 %r86, %r83, %r84, %r85;
|
|
mul.wide.u32 %rd50, %r86, 3;
|
|
add.s64 %rd5, %rd49, %rd50;
|
|
ld.const.f32 %f50, [params+660];
|
|
mul.f32 %f51, %f15, 0f3456BF95;
|
|
mul.f32 %f52, %f16, 0f3456BF95;
|
|
mul.f32 %f53, %f17, 0f3456BF95;
|
|
ld.const.u64 %rd6, [params+96];
|
|
abs.f32 %f551, %f52;
|
|
abs.f32 %f552, %f51;
|
|
max.f32 %f553, %f552, %f551;
|
|
abs.f32 %f554, %f53;
|
|
max.f32 %f555, %f553, %f554;
|
|
mov.u32 %r451, %r454;
|
|
|
|
$L__BB0_15:
|
|
shl.b32 %r87, %r451, 1;
|
|
mul.wide.s32 %rd51, %r87, 12;
|
|
add.s64 %rd7, %rd4, %rd51;
|
|
ld.global.f32 %f424, [%rd7];
|
|
sub.f32 %f425, %f424, %f10;
|
|
ld.global.f32 %f426, [%rd7+4];
|
|
sub.f32 %f427, %f426, %f11;
|
|
ld.global.f32 %f428, [%rd7+8];
|
|
sub.f32 %f429, %f428, %f12;
|
|
mul.f32 %f430, %f427, %f427;
|
|
fma.rn.f32 %f431, %f425, %f425, %f430;
|
|
fma.rn.f32 %f432, %f429, %f429, %f431;
|
|
sqrt.rn.f32 %f59, %f432;
|
|
rcp.rn.f32 %f433, %f59;
|
|
mul.f32 %f60, %f425, %f433;
|
|
mul.f32 %f61, %f427, %f433;
|
|
mul.f32 %f62, %f429, %f433;
|
|
mul.f32 %f434, %f1407, %f61;
|
|
fma.rn.f32 %f435, %f1406, %f60, %f434;
|
|
fma.rn.f32 %f63, %f1408, %f62, %f435;
|
|
setp.leu.f32 %p24, %f63, 0f00000000;
|
|
@%p24 bra $L__BB0_32;
|
|
|
|
setp.ne.s32 %p26, %r5, 0;
|
|
mul.f32 %f436, %f59, %f59;
|
|
div.rn.f32 %f64, %f49, %f436;
|
|
ld.global.u8 %rs44, [%rd5];
|
|
cvt.rn.f32.u16 %f437, %rs44;
|
|
div.rn.f32 %f438, %f437, 0fC37F0000;
|
|
fma.rn.f32 %f439, %f438, 0f3F333333, 0f3F800000;
|
|
setp.gt.f32 %p27, %f64, %f439;
|
|
and.pred %p28, %p26, %p27;
|
|
mov.pred %p204, -1;
|
|
@%p28 bra $L__BB0_33;
|
|
|
|
mul.f32 %f65, %f59, %f50;
|
|
mov.f32 %f444, 0f40800000;
|
|
abs.f32 %f67, %f65;
|
|
setp.lt.f32 %p29, %f67, 0f00800000;
|
|
mul.f32 %f446, %f67, 0f4B800000;
|
|
selp.f32 %f447, %f446, %f67, %p29;
|
|
selp.f32 %f448, 0fC3170000, 0fC2FE0000, %p29;
|
|
mov.b32 %r88, %f447;
|
|
and.b32 %r89, %r88, 8388607;
|
|
or.b32 %r90, %r89, 1065353216;
|
|
mov.b32 %f449, %r90;
|
|
shr.u32 %r91, %r88, 23;
|
|
cvt.rn.f32.u32 %f450, %r91;
|
|
add.f32 %f451, %f448, %f450;
|
|
setp.gt.f32 %p30, %f449, 0f3FB504F3;
|
|
mul.f32 %f452, %f449, 0f3F000000;
|
|
add.f32 %f453, %f451, 0f3F800000;
|
|
selp.f32 %f454, %f453, %f451, %p30;
|
|
selp.f32 %f455, %f452, %f449, %p30;
|
|
add.f32 %f456, %f455, 0fBF800000;
|
|
add.f32 %f457, %f455, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f458, %f457;
|
|
add.f32 %f459, %f456, %f456;
|
|
mul.f32 %f460, %f459, %f458;
|
|
mul.f32 %f461, %f460, %f460;
|
|
mov.f32 %f462, 0f3C4CAF63;
|
|
mov.f32 %f463, 0f3B18F0FE;
|
|
fma.rn.f32 %f464, %f463, %f461, %f462;
|
|
mov.f32 %f465, 0f3DAAAABD;
|
|
fma.rn.f32 %f466, %f464, %f461, %f465;
|
|
mul.rn.f32 %f467, %f466, %f461;
|
|
mul.rn.f32 %f468, %f467, %f460;
|
|
sub.f32 %f469, %f456, %f460;
|
|
add.f32 %f470, %f469, %f469;
|
|
neg.f32 %f471, %f460;
|
|
fma.rn.f32 %f472, %f471, %f456, %f470;
|
|
mul.rn.f32 %f473, %f458, %f472;
|
|
add.f32 %f474, %f468, %f460;
|
|
sub.f32 %f475, %f460, %f474;
|
|
add.f32 %f476, %f468, %f475;
|
|
add.f32 %f477, %f473, %f476;
|
|
add.f32 %f478, %f474, %f477;
|
|
sub.f32 %f479, %f474, %f478;
|
|
add.f32 %f480, %f477, %f479;
|
|
mov.f32 %f481, 0f3F317200;
|
|
mul.rn.f32 %f482, %f454, %f481;
|
|
mov.f32 %f483, 0f35BFBE8E;
|
|
mul.rn.f32 %f484, %f454, %f483;
|
|
add.f32 %f485, %f482, %f478;
|
|
sub.f32 %f486, %f482, %f485;
|
|
add.f32 %f487, %f478, %f486;
|
|
add.f32 %f488, %f480, %f487;
|
|
add.f32 %f489, %f484, %f488;
|
|
add.f32 %f490, %f485, %f489;
|
|
sub.f32 %f491, %f485, %f490;
|
|
add.f32 %f492, %f489, %f491;
|
|
mul.rn.f32 %f493, %f444, %f490;
|
|
neg.f32 %f494, %f493;
|
|
fma.rn.f32 %f495, %f444, %f490, %f494;
|
|
fma.rn.f32 %f496, %f444, %f492, %f495;
|
|
mov.f32 %f497, 0f00000000;
|
|
fma.rn.f32 %f498, %f497, %f490, %f496;
|
|
add.rn.f32 %f499, %f493, %f498;
|
|
neg.f32 %f500, %f499;
|
|
add.rn.f32 %f501, %f493, %f500;
|
|
add.rn.f32 %f502, %f501, %f498;
|
|
mov.b32 %r92, %f499;
|
|
setp.eq.s32 %p31, %r92, 1118925336;
|
|
add.s32 %r93, %r92, -1;
|
|
mov.b32 %f503, %r93;
|
|
add.f32 %f504, %f502, 0f37000000;
|
|
selp.f32 %f68, %f504, %f502, %p31;
|
|
selp.f32 %f505, %f503, %f499, %p31;
|
|
mov.f32 %f506, 0f3FB8AA3B;
|
|
mul.rn.f32 %f507, %f505, %f506;
|
|
cvt.rzi.f32.f32 %f508, %f507;
|
|
abs.f32 %f509, %f508;
|
|
setp.gt.f32 %p32, %f509, 0f42FC0000;
|
|
mov.b32 %r94, %f508;
|
|
and.b32 %r95, %r94, -2147483648;
|
|
or.b32 %r96, %r95, 1123811328;
|
|
mov.b32 %f510, %r96;
|
|
selp.f32 %f511, %f510, %f508, %p32;
|
|
mov.f32 %f512, 0fBF317218;
|
|
fma.rn.f32 %f513, %f511, %f512, %f505;
|
|
mov.f32 %f514, 0f3102E308;
|
|
fma.rn.f32 %f515, %f511, %f514, %f513;
|
|
mul.f32 %f516, %f515, 0f3FB8AA3B;
|
|
add.f32 %f517, %f511, 0f4B40007F;
|
|
mov.b32 %r97, %f517;
|
|
shl.b32 %r98, %r97, 23;
|
|
mov.b32 %f518, %r98;
|
|
ex2.approx.ftz.f32 %f519, %f516;
|
|
mul.f32 %f69, %f519, %f518;
|
|
setp.eq.f32 %p33, %f69, 0f7F800000;
|
|
mov.f32 %f1423, 0f7F800000;
|
|
@%p33 bra $L__BB0_19;
|
|
|
|
fma.rn.f32 %f1423, %f69, %f68, %f69;
|
|
|
|
$L__BB0_19:
|
|
mov.f32 %f1403, 0f40000000;
|
|
cvt.rzi.f32.f32 %f1402, %f1403;
|
|
add.f32 %f1401, %f1402, %f1402;
|
|
mov.f32 %f1400, 0f40800000;
|
|
sub.f32 %f1399, %f1400, %f1401;
|
|
abs.f32 %f1398, %f1399;
|
|
setp.lt.f32 %p34, %f65, 0f00000000;
|
|
setp.eq.f32 %p35, %f1398, 0f3F800000;
|
|
and.pred %p1, %p34, %p35;
|
|
setp.eq.f32 %p36, %f65, 0f00000000;
|
|
@%p36 bra $L__BB0_23;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_23:
|
|
add.f32 %f524, %f65, %f65;
|
|
selp.f32 %f1425, %f524, 0f00000000, %p35;
|
|
bra.uni $L__BB0_24;
|
|
|
|
$L__BB0_20:
|
|
mov.b32 %r99, %f1423;
|
|
xor.b32 %r100, %r99, -2147483648;
|
|
mov.b32 %f520, %r100;
|
|
selp.f32 %f1425, %f520, %f1423, %p1;
|
|
setp.geu.f32 %p37, %f65, 0f00000000;
|
|
@%p37 bra $L__BB0_24;
|
|
|
|
mov.f32 %f521, 0f40800000;
|
|
cvt.rzi.f32.f32 %f522, %f521;
|
|
setp.eq.f32 %p38, %f522, 0f40800000;
|
|
@%p38 bra $L__BB0_24;
|
|
|
|
mov.f32 %f1425, 0f7FFFFFFF;
|
|
|
|
$L__BB0_24:
|
|
add.f32 %f525, %f67, 0f40800000;
|
|
mov.b32 %r101, %f525;
|
|
setp.lt.s32 %p40, %r101, 2139095040;
|
|
@%p40 bra $L__BB0_29;
|
|
|
|
setp.gtu.f32 %p41, %f67, 0f7F800000;
|
|
@%p41 bra $L__BB0_28;
|
|
bra.uni $L__BB0_26;
|
|
|
|
$L__BB0_28:
|
|
add.f32 %f1425, %f65, 0f40800000;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_26:
|
|
setp.neu.f32 %p42, %f67, 0f7F800000;
|
|
@%p42 bra $L__BB0_29;
|
|
|
|
selp.f32 %f1425, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_29:
|
|
shl.b32 %r449, %r451, 1;
|
|
mul.wide.s32 %rd117, %r449, 12;
|
|
add.s64 %rd116, %rd4, %rd117;
|
|
mov.f32 %f526, 0f3F800000;
|
|
sub.f32 %f527, %f526, %f1425;
|
|
setp.eq.f32 %p43, %f65, 0f3F800000;
|
|
selp.f32 %f528, 0f00000000, %f527, %p43;
|
|
cvt.sat.f32.f32 %f529, %f528;
|
|
mul.f32 %f530, %f64, %f529;
|
|
ld.global.f32 %f531, [%rd116+12];
|
|
mul.f32 %f532, %f60, %f531;
|
|
ld.global.f32 %f533, [%rd116+16];
|
|
mul.f32 %f534, %f61, %f533;
|
|
neg.f32 %f535, %f534;
|
|
sub.f32 %f536, %f535, %f532;
|
|
ld.global.f32 %f537, [%rd116+20];
|
|
mul.f32 %f538, %f62, %f537;
|
|
sub.f32 %f539, %f536, %f538;
|
|
cvt.sat.f32.f32 %f540, %f539;
|
|
mul.f32 %f78, %f530, %f540;
|
|
setp.leu.f32 %p44, %f78, 0f3727C5AC;
|
|
@%p44 bra $L__BB0_31;
|
|
|
|
cvt.sat.f32.f32 %f550, %f63;
|
|
mov.f32 %f556, 0f38D1B717;
|
|
max.f32 %f547, %f555, %f556;
|
|
sub.f32 %f548, %f59, %f547;
|
|
mov.f32 %f549, 0f00000000;
|
|
mov.u32 %r138, 2;
|
|
mov.u32 %r140, 1;
|
|
mov.u32 %r141, 1065353216;
|
|
mov.u32 %r172, 0;
|
|
// begin inline asm
|
|
call(%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128,%r129,%r130,%r131,%r132,%r133),_optix_trace_typed_32,(%r172,%rd6,%f15,%f16,%f17,%f60,%f61,%f62,%f547,%f548,%f549,%r140,%r172,%r140,%r138,%r140,%r140,%r141,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172,%r172);
|
|
// end inline asm
|
|
mov.b32 %f557, %r102;
|
|
mul.f32 %f558, %f78, 0f3EA2F983;
|
|
mul.f32 %f559, %f558, %f557;
|
|
fma.rn.f32 %f1430, %f550, %f559, %f1430;
|
|
mul.f32 %f560, %f28, %f61;
|
|
fma.rn.f32 %f561, %f26, %f60, %f560;
|
|
fma.rn.f32 %f562, %f30, %f62, %f561;
|
|
cvt.sat.f32.f32 %f563, %f562;
|
|
fma.rn.f32 %f1429, %f563, %f559, %f1429;
|
|
mul.f32 %f564, %f38, %f61;
|
|
fma.rn.f32 %f565, %f37, %f60, %f564;
|
|
fma.rn.f32 %f566, %f39, %f62, %f565;
|
|
cvt.sat.f32.f32 %f567, %f566;
|
|
fma.rn.f32 %f1428, %f567, %f559, %f1428;
|
|
mul.f32 %f568, %f47, %f61;
|
|
fma.rn.f32 %f569, %f46, %f60, %f568;
|
|
fma.rn.f32 %f570, %f48, %f62, %f569;
|
|
cvt.sat.f32.f32 %f571, %f570;
|
|
fma.rn.f32 %f1427, %f571, %f559, %f1427;
|
|
add.f32 %f1426, %f1426, %f557;
|
|
|
|
$L__BB0_31:
|
|
add.s32 %r454, %r454, 1;
|
|
|
|
$L__BB0_32:
|
|
add.s32 %r451, %r451, 1;
|
|
setp.lt.s32 %p46, %r451, %r4;
|
|
mov.pred %p204, %p22;
|
|
@%p46 bra $L__BB0_15;
|
|
|
|
$L__BB0_33:
|
|
cvt.rn.f32.s32 %f572, %r454;
|
|
mov.f32 %f573, 0f3F800000;
|
|
max.f32 %f574, %f572, %f573;
|
|
div.rn.f32 %f1466, %f1430, %f574;
|
|
div.rn.f32 %f1462, %f1426, %f574;
|
|
div.rn.f32 %f1465, %f1429, %f574;
|
|
div.rn.f32 %f1464, %f1428, %f574;
|
|
div.rn.f32 %f1463, %f1427, %f574;
|
|
not.pred %p47, %p204;
|
|
@%p47 bra $L__BB0_64;
|
|
|
|
abs.f32 %f1405, %f1408;
|
|
abs.f32 %f1404, %f1406;
|
|
setp.gt.f32 %p48, %f1404, %f1405;
|
|
selp.f32 %f580, 0f00000000, %f1407, %p48;
|
|
mov.f32 %f1450, 0f00000000;
|
|
neg.f32 %f581, %f1408;
|
|
selp.f32 %f582, %f1406, %f581, %p48;
|
|
neg.f32 %f583, %f1407;
|
|
selp.f32 %f584, %f583, 0f00000000, %p48;
|
|
mul.f32 %f585, %f582, %f582;
|
|
fma.rn.f32 %f586, %f584, %f584, %f585;
|
|
fma.rn.f32 %f587, %f580, %f580, %f586;
|
|
sqrt.rn.f32 %f588, %f587;
|
|
rcp.rn.f32 %f589, %f588;
|
|
mul.f32 %f104, %f584, %f589;
|
|
mul.f32 %f105, %f582, %f589;
|
|
mul.f32 %f106, %f580, %f589;
|
|
setp.lt.s32 %p49, %r5, 1;
|
|
mov.f32 %f1449, %f1450;
|
|
mov.f32 %f1448, %f1450;
|
|
mov.f32 %f1447, %f1450;
|
|
mov.f32 %f1446, %f1450;
|
|
@%p49 bra $L__BB0_63;
|
|
|
|
cvt.rn.f32.s32 %f595, %r5;
|
|
rcp.rn.f32 %f107, %f595;
|
|
mul.f32 %f108, %f15, 0f3456BF95;
|
|
mul.f32 %f109, %f16, 0f3456BF95;
|
|
mul.f32 %f110, %f17, 0f3456BF95;
|
|
ld.const.u64 %rd8, [params+96];
|
|
mul.f32 %f596, %f1406, %f105;
|
|
mul.f32 %f597, %f1407, %f104;
|
|
sub.f32 %f111, %f597, %f596;
|
|
mul.f32 %f598, %f1408, %f104;
|
|
mul.f32 %f599, %f1406, %f106;
|
|
sub.f32 %f112, %f599, %f598;
|
|
mul.f32 %f600, %f1407, %f106;
|
|
mul.f32 %f601, %f1408, %f105;
|
|
sub.f32 %f113, %f601, %f600;
|
|
mov.u32 %r173, 0;
|
|
add.s64 %rd9, %rd1, 24;
|
|
mov.u64 %rd53, __cudart_i2opi_f;
|
|
abs.f32 %f664, %f109;
|
|
abs.f32 %f665, %f108;
|
|
max.f32 %f666, %f665, %f664;
|
|
abs.f32 %f667, %f110;
|
|
max.f32 %f668, %f666, %f667;
|
|
mov.u32 %r455, %r173;
|
|
|
|
$L__BB0_36:
|
|
cvt.rn.f32.s32 %f119, %r455;
|
|
mov.u32 %r457, %r173;
|
|
|
|
$L__BB0_37:
|
|
mad.lo.s32 %r175, %r458, 1664525, 1013904223;
|
|
and.b32 %r176, %r175, 16777215;
|
|
cvt.rn.f32.u32 %f602, %r176;
|
|
fma.rn.f32 %f603, %f602, 0f33800000, %f119;
|
|
mul.f32 %f125, %f107, %f603;
|
|
mad.lo.s32 %r458, %r175, 1664525, 1013904223;
|
|
and.b32 %r177, %r458, 16777215;
|
|
cvt.rn.f32.u32 %f604, %r177;
|
|
cvt.rn.f32.s32 %f605, %r457;
|
|
fma.rn.f32 %f606, %f604, 0f33800000, %f605;
|
|
mul.f32 %f607, %f107, %f606;
|
|
mul.f32 %f608, %f125, %f125;
|
|
mov.f32 %f609, 0f3F800000;
|
|
sub.f32 %f610, %f609, %f608;
|
|
mov.f32 %f611, 0f00000000;
|
|
max.f32 %f612, %f611, %f610;
|
|
sqrt.rn.f32 %f126, %f612;
|
|
mul.f32 %f127, %f607, 0f40C90FDB;
|
|
mul.f32 %f613, %f127, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r465, %f613;
|
|
cvt.rn.f32.s32 %f614, %r465;
|
|
mov.f32 %f615, 0fBFC90FDA;
|
|
fma.rn.f32 %f616, %f614, %f615, %f127;
|
|
mov.f32 %f617, 0fB3A22168;
|
|
fma.rn.f32 %f618, %f614, %f617, %f616;
|
|
mov.f32 %f619, 0fA7C234C5;
|
|
fma.rn.f32 %f1454, %f614, %f619, %f618;
|
|
abs.f32 %f129, %f127;
|
|
setp.ltu.f32 %p50, %f129, 0f47CE4780;
|
|
mov.u32 %r462, %r465;
|
|
mov.f32 %f1451, %f1454;
|
|
@%p50 bra $L__BB0_45;
|
|
|
|
setp.eq.f32 %p51, %f129, 0f7F800000;
|
|
@%p51 bra $L__BB0_44;
|
|
bra.uni $L__BB0_39;
|
|
|
|
$L__BB0_44:
|
|
mov.f32 %f622, 0f00000000;
|
|
mul.rn.f32 %f1451, %f127, %f622;
|
|
mov.u32 %r462, 0;
|
|
bra.uni $L__BB0_45;
|
|
|
|
$L__BB0_39:
|
|
mov.b32 %r21, %f127;
|
|
bfe.u32 %r179, %r21, 23, 8;
|
|
add.s32 %r22, %r179, -128;
|
|
shl.b32 %r180, %r21, 8;
|
|
or.b32 %r23, %r180, -2147483648;
|
|
shr.u32 %r24, %r22, 5;
|
|
mov.u64 %rd120, 0;
|
|
mov.u32 %r459, 0;
|
|
mov.u64 %rd118, %rd1;
|
|
mov.u64 %rd119, %rd53;
|
|
|
|
$L__BB0_40:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r181, [%rd119];
|
|
mad.wide.u32 %rd55, %r181, %r23, %rd120;
|
|
shr.u64 %rd120, %rd55, 32;
|
|
st.local.u32 [%rd118], %rd55;
|
|
add.s64 %rd119, %rd119, 4;
|
|
add.s64 %rd118, %rd118, 4;
|
|
add.s32 %r459, %r459, 1;
|
|
setp.ne.s32 %p52, %r459, 6;
|
|
@%p52 bra $L__BB0_40;
|
|
|
|
st.local.u32 [%rd9], %rd120;
|
|
mov.u32 %r182, 4;
|
|
sub.s32 %r27, %r182, %r24;
|
|
mov.u32 %r183, 6;
|
|
sub.s32 %r184, %r183, %r24;
|
|
mul.wide.s32 %rd56, %r184, 4;
|
|
add.s64 %rd57, %rd1, %rd56;
|
|
ld.local.u32 %r460, [%rd57];
|
|
ld.local.u32 %r461, [%rd57+-4];
|
|
and.b32 %r30, %r22, 31;
|
|
setp.eq.s32 %p53, %r30, 0;
|
|
@%p53 bra $L__BB0_43;
|
|
|
|
mov.u32 %r185, 32;
|
|
sub.s32 %r186, %r185, %r30;
|
|
shr.u32 %r187, %r461, %r186;
|
|
shl.b32 %r188, %r460, %r30;
|
|
add.s32 %r460, %r187, %r188;
|
|
mul.wide.s32 %rd58, %r27, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r189, [%rd59];
|
|
shr.u32 %r190, %r189, %r186;
|
|
shl.b32 %r191, %r461, %r30;
|
|
add.s32 %r461, %r190, %r191;
|
|
|
|
$L__BB0_43:
|
|
and.b32 %r192, %r21, -2147483648;
|
|
shr.u32 %r193, %r461, 30;
|
|
shl.b32 %r194, %r460, 2;
|
|
or.b32 %r195, %r193, %r194;
|
|
shr.u32 %r196, %r195, 31;
|
|
shr.u32 %r197, %r460, 30;
|
|
add.s32 %r198, %r196, %r197;
|
|
neg.s32 %r199, %r198;
|
|
setp.eq.s32 %p54, %r192, 0;
|
|
selp.b32 %r462, %r198, %r199, %p54;
|
|
setp.ne.s32 %p55, %r196, 0;
|
|
xor.b32 %r200, %r192, -2147483648;
|
|
selp.b32 %r201, %r200, %r192, %p55;
|
|
selp.b32 %r202, -1, 0, %p55;
|
|
xor.b32 %r203, %r195, %r202;
|
|
shl.b32 %r204, %r461, 2;
|
|
xor.b32 %r205, %r204, %r202;
|
|
cvt.u64.u32 %rd60, %r203;
|
|
cvt.u64.u32 %rd61, %r205;
|
|
bfi.b64 %rd62, %rd60, %rd61, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd62;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f620, %fd2;
|
|
setp.eq.s32 %p56, %r201, 0;
|
|
neg.f32 %f621, %f620;
|
|
selp.f32 %f1451, %f620, %f621, %p56;
|
|
|
|
$L__BB0_45:
|
|
add.s32 %r37, %r462, 1;
|
|
and.b32 %r38, %r37, 1;
|
|
setp.eq.s32 %p57, %r38, 0;
|
|
selp.f32 %f133, %f1451, 0f3F800000, %p57;
|
|
mul.rn.f32 %f134, %f1451, %f1451;
|
|
mov.f32 %f1452, 0fB94D4153;
|
|
@%p57 bra $L__BB0_47;
|
|
|
|
mov.f32 %f624, 0fBAB607ED;
|
|
mov.f32 %f625, 0f37CBAC00;
|
|
fma.rn.f32 %f1452, %f625, %f134, %f624;
|
|
|
|
$L__BB0_47:
|
|
selp.f32 %f626, 0f3C0885E4, 0f3D2AAABB, %p57;
|
|
fma.rn.f32 %f627, %f1452, %f134, %f626;
|
|
selp.f32 %f628, 0fBE2AAAA8, 0fBEFFFFFF, %p57;
|
|
fma.rn.f32 %f629, %f627, %f134, %f628;
|
|
mov.f32 %f630, 0f00000000;
|
|
fma.rn.f32 %f631, %f134, %f133, %f630;
|
|
fma.rn.f32 %f1453, %f629, %f631, %f133;
|
|
and.b32 %r207, %r37, 2;
|
|
setp.eq.s32 %p59, %r207, 0;
|
|
@%p59 bra $L__BB0_49;
|
|
|
|
mov.f32 %f633, 0fBF800000;
|
|
fma.rn.f32 %f1453, %f1453, %f633, %f630;
|
|
|
|
$L__BB0_49:
|
|
@%p50 bra $L__BB0_57;
|
|
|
|
setp.eq.f32 %p61, %f129, 0f7F800000;
|
|
@%p61 bra $L__BB0_56;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_56:
|
|
mov.f32 %f636, 0f00000000;
|
|
mul.rn.f32 %f1454, %f127, %f636;
|
|
mov.u32 %r465, 0;
|
|
bra.uni $L__BB0_57;
|
|
|
|
$L__BB0_51:
|
|
mov.b32 %r39, %f127;
|
|
bfe.u32 %r208, %r39, 23, 8;
|
|
add.s32 %r40, %r208, -128;
|
|
shl.b32 %r209, %r39, 8;
|
|
or.b32 %r41, %r209, -2147483648;
|
|
shr.u32 %r42, %r40, 5;
|
|
mov.u64 %rd121, 0;
|
|
mov.u64 %rd122, %rd121;
|
|
|
|
$L__BB0_52:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd65, %rd121, 2;
|
|
mov.u64 %rd66, __cudart_i2opi_f;
|
|
add.s64 %rd67, %rd66, %rd65;
|
|
ld.global.nc.u32 %r210, [%rd67];
|
|
mad.wide.u32 %rd68, %r210, %r41, %rd122;
|
|
shr.u64 %rd122, %rd68, 32;
|
|
add.s64 %rd69, %rd1, %rd65;
|
|
st.local.u32 [%rd69], %rd68;
|
|
cvt.u32.u64 %r211, %rd121;
|
|
add.s32 %r212, %r211, 1;
|
|
cvt.s64.s32 %rd121, %r212;
|
|
setp.ne.s32 %p62, %r212, 6;
|
|
@%p62 bra $L__BB0_52;
|
|
|
|
st.local.u32 [%rd9], %rd122;
|
|
mov.u32 %r213, 4;
|
|
sub.s32 %r43, %r213, %r42;
|
|
mov.u32 %r214, 6;
|
|
sub.s32 %r215, %r214, %r42;
|
|
mul.wide.s32 %rd70, %r215, 4;
|
|
add.s64 %rd71, %rd1, %rd70;
|
|
ld.local.u32 %r463, [%rd71];
|
|
ld.local.u32 %r464, [%rd71+-4];
|
|
and.b32 %r46, %r40, 31;
|
|
setp.eq.s32 %p63, %r46, 0;
|
|
@%p63 bra $L__BB0_55;
|
|
|
|
mov.u32 %r216, 32;
|
|
sub.s32 %r217, %r216, %r46;
|
|
shr.u32 %r218, %r464, %r217;
|
|
shl.b32 %r219, %r463, %r46;
|
|
add.s32 %r463, %r218, %r219;
|
|
mul.wide.s32 %rd72, %r43, 4;
|
|
add.s64 %rd73, %rd1, %rd72;
|
|
ld.local.u32 %r220, [%rd73];
|
|
shr.u32 %r221, %r220, %r217;
|
|
shl.b32 %r222, %r464, %r46;
|
|
add.s32 %r464, %r221, %r222;
|
|
|
|
$L__BB0_55:
|
|
and.b32 %r223, %r39, -2147483648;
|
|
shr.u32 %r224, %r464, 30;
|
|
shl.b32 %r225, %r463, 2;
|
|
or.b32 %r226, %r224, %r225;
|
|
shr.u32 %r227, %r226, 31;
|
|
shr.u32 %r228, %r463, 30;
|
|
add.s32 %r229, %r227, %r228;
|
|
neg.s32 %r230, %r229;
|
|
setp.eq.s32 %p64, %r223, 0;
|
|
selp.b32 %r465, %r229, %r230, %p64;
|
|
setp.ne.s32 %p65, %r227, 0;
|
|
xor.b32 %r231, %r223, -2147483648;
|
|
selp.b32 %r232, %r231, %r223, %p65;
|
|
selp.b32 %r233, -1, 0, %p65;
|
|
xor.b32 %r234, %r226, %r233;
|
|
shl.b32 %r235, %r464, 2;
|
|
xor.b32 %r236, %r235, %r233;
|
|
cvt.u64.u32 %rd74, %r234;
|
|
cvt.u64.u32 %rd75, %r236;
|
|
bfi.b64 %rd76, %rd74, %rd75, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd76;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f634, %fd4;
|
|
setp.eq.s32 %p66, %r232, 0;
|
|
neg.f32 %f635, %f634;
|
|
selp.f32 %f1454, %f634, %f635, %p66;
|
|
|
|
$L__BB0_57:
|
|
mul.f32 %f143, %f126, %f1453;
|
|
and.b32 %r53, %r465, 1;
|
|
setp.eq.s32 %p67, %r53, 0;
|
|
selp.f32 %f144, %f1454, 0f3F800000, %p67;
|
|
mul.rn.f32 %f145, %f1454, %f1454;
|
|
mov.f32 %f1455, 0fB94D4153;
|
|
@%p67 bra $L__BB0_59;
|
|
|
|
mov.f32 %f638, 0fBAB607ED;
|
|
mov.f32 %f639, 0f37CBAC00;
|
|
fma.rn.f32 %f1455, %f639, %f145, %f638;
|
|
|
|
$L__BB0_59:
|
|
selp.f32 %f640, 0f3C0885E4, 0f3D2AAABB, %p67;
|
|
fma.rn.f32 %f641, %f1455, %f145, %f640;
|
|
selp.f32 %f642, 0fBE2AAAA8, 0fBEFFFFFF, %p67;
|
|
fma.rn.f32 %f643, %f641, %f145, %f642;
|
|
mov.f32 %f644, 0f00000000;
|
|
fma.rn.f32 %f645, %f145, %f144, %f644;
|
|
fma.rn.f32 %f1456, %f643, %f645, %f144;
|
|
and.b32 %r238, %r465, 2;
|
|
setp.eq.s32 %p69, %r238, 0;
|
|
@%p69 bra $L__BB0_61;
|
|
|
|
mov.f32 %f647, 0fBF800000;
|
|
fma.rn.f32 %f1456, %f1456, %f647, %f644;
|
|
|
|
$L__BB0_61:
|
|
mul.f32 %f657, %f126, %f1456;
|
|
mul.f32 %f658, %f104, %f657;
|
|
mul.f32 %f659, %f105, %f657;
|
|
mul.f32 %f660, %f106, %f657;
|
|
fma.rn.f32 %f661, %f113, %f143, %f658;
|
|
fma.rn.f32 %f662, %f112, %f143, %f659;
|
|
fma.rn.f32 %f663, %f111, %f143, %f660;
|
|
fma.rn.f32 %f651, %f1406, %f125, %f661;
|
|
fma.rn.f32 %f652, %f1407, %f125, %f662;
|
|
fma.rn.f32 %f653, %f1408, %f125, %f663;
|
|
mov.f32 %f669, 0f38D1B717;
|
|
max.f32 %f654, %f668, %f669;
|
|
mov.f32 %f655, 0f6C4ECB8F;
|
|
mov.u32 %r275, 2;
|
|
mov.u32 %r277, 1;
|
|
mov.u32 %r309, 0;
|
|
// begin inline asm
|
|
call(%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268,%r269,%r270),_optix_trace_typed_32,(%r309,%rd8,%f15,%f16,%f17,%f651,%f652,%f653,%f654,%f655,%f644,%r277,%r309,%r309,%r275,%r309,%r277,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309,%r309);
|
|
// end inline asm
|
|
mov.b32 %f670, %r239;
|
|
setp.lt.f32 %p70, %f670, 0f00000000;
|
|
selp.f32 %f671, 0f00000000, %f670, %p70;
|
|
setp.geu.f32 %p71, %f670, 0f00000000;
|
|
selp.f32 %f672, 0f3F800000, 0f00000000, %p71;
|
|
add.f32 %f1450, %f1450, %f672;
|
|
mul.f32 %f673, %f28, %f652;
|
|
fma.rn.f32 %f674, %f26, %f651, %f673;
|
|
fma.rn.f32 %f675, %f30, %f653, %f674;
|
|
cvt.sat.f32.f32 %f676, %f675;
|
|
fma.rn.f32 %f1447, %f676, %f671, %f1447;
|
|
mul.f32 %f677, %f38, %f652;
|
|
fma.rn.f32 %f678, %f37, %f651, %f677;
|
|
fma.rn.f32 %f679, %f39, %f653, %f678;
|
|
cvt.sat.f32.f32 %f680, %f679;
|
|
fma.rn.f32 %f1448, %f680, %f671, %f1448;
|
|
mul.f32 %f681, %f47, %f652;
|
|
fma.rn.f32 %f682, %f46, %f651, %f681;
|
|
fma.rn.f32 %f683, %f48, %f653, %f682;
|
|
cvt.sat.f32.f32 %f684, %f683;
|
|
fma.rn.f32 %f1449, %f684, %f671, %f1449;
|
|
mul.f32 %f685, %f1407, %f652;
|
|
fma.rn.f32 %f686, %f1406, %f651, %f685;
|
|
fma.rn.f32 %f687, %f1408, %f653, %f686;
|
|
cvt.sat.f32.f32 %f688, %f687;
|
|
fma.rn.f32 %f1446, %f671, %f688, %f1446;
|
|
add.s32 %r457, %r457, 1;
|
|
setp.lt.s32 %p72, %r457, %r5;
|
|
@%p72 bra $L__BB0_37;
|
|
|
|
add.s32 %r455, %r455, 1;
|
|
setp.lt.s32 %p73, %r455, %r5;
|
|
@%p73 bra $L__BB0_36;
|
|
|
|
$L__BB0_63:
|
|
mul.lo.s32 %r310, %r5, %r5;
|
|
cvt.rn.f32.s32 %f689, %r310;
|
|
div.rn.f32 %f690, %f1446, %f689;
|
|
div.rn.f32 %f1462, %f1450, %f689;
|
|
div.rn.f32 %f1465, %f1447, %f689;
|
|
div.rn.f32 %f1464, %f1448, %f689;
|
|
div.rn.f32 %f1463, %f1449, %f689;
|
|
add.f32 %f1466, %f690, %f690;
|
|
|
|
$L__BB0_64:
|
|
ld.const.u32 %r450, [params+616];
|
|
setp.lt.s32 %p74, %r450, 0;
|
|
selp.f32 %f171, %f1466, %f1462, %p74;
|
|
ld.const.u32 %r56, [params+104];
|
|
and.b32 %r311, %r56, 8;
|
|
setp.eq.s32 %p75, %r311, 0;
|
|
@%p75 bra $L__BB0_78;
|
|
|
|
ld.const.u64 %rd78, [params+192];
|
|
cvta.to.global.u64 %rd20, %rd78;
|
|
ld.const.u32 %r312, [params+184];
|
|
mad.lo.s32 %r313, %r312, %r7, %r6;
|
|
cvt.u64.u32 %rd21, %r313;
|
|
mov.f32 %f692, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f693, %f692;
|
|
add.f32 %f694, %f693, %f693;
|
|
mov.f32 %f695, 0f3EE8BA2E;
|
|
sub.f32 %f696, %f695, %f694;
|
|
abs.f32 %f172, %f696;
|
|
abs.f32 %f173, %f171;
|
|
setp.lt.f32 %p76, %f173, 0f00800000;
|
|
mul.f32 %f697, %f173, 0f4B800000;
|
|
selp.f32 %f698, %f697, %f173, %p76;
|
|
selp.f32 %f699, 0fC3170000, 0fC2FE0000, %p76;
|
|
mov.b32 %r314, %f698;
|
|
and.b32 %r315, %r314, 8388607;
|
|
or.b32 %r316, %r315, 1065353216;
|
|
mov.b32 %f700, %r316;
|
|
shr.u32 %r317, %r314, 23;
|
|
cvt.rn.f32.u32 %f701, %r317;
|
|
add.f32 %f702, %f699, %f701;
|
|
setp.gt.f32 %p77, %f700, 0f3FB504F3;
|
|
mul.f32 %f703, %f700, 0f3F000000;
|
|
add.f32 %f704, %f702, 0f3F800000;
|
|
selp.f32 %f705, %f704, %f702, %p77;
|
|
selp.f32 %f706, %f703, %f700, %p77;
|
|
add.f32 %f707, %f706, 0fBF800000;
|
|
add.f32 %f708, %f706, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f709, %f708;
|
|
add.f32 %f710, %f707, %f707;
|
|
mul.f32 %f711, %f710, %f709;
|
|
mul.f32 %f712, %f711, %f711;
|
|
mov.f32 %f713, 0f3C4CAF63;
|
|
mov.f32 %f714, 0f3B18F0FE;
|
|
fma.rn.f32 %f715, %f714, %f712, %f713;
|
|
mov.f32 %f716, 0f3DAAAABD;
|
|
fma.rn.f32 %f717, %f715, %f712, %f716;
|
|
mul.rn.f32 %f718, %f717, %f712;
|
|
mul.rn.f32 %f719, %f718, %f711;
|
|
sub.f32 %f720, %f707, %f711;
|
|
add.f32 %f721, %f720, %f720;
|
|
neg.f32 %f722, %f711;
|
|
fma.rn.f32 %f723, %f722, %f707, %f721;
|
|
mul.rn.f32 %f724, %f709, %f723;
|
|
add.f32 %f725, %f719, %f711;
|
|
sub.f32 %f726, %f711, %f725;
|
|
add.f32 %f727, %f719, %f726;
|
|
add.f32 %f728, %f724, %f727;
|
|
add.f32 %f729, %f725, %f728;
|
|
sub.f32 %f730, %f725, %f729;
|
|
add.f32 %f731, %f728, %f730;
|
|
mov.f32 %f732, 0f3F317200;
|
|
mul.rn.f32 %f733, %f705, %f732;
|
|
mov.f32 %f734, 0f35BFBE8E;
|
|
mul.rn.f32 %f735, %f705, %f734;
|
|
add.f32 %f736, %f733, %f729;
|
|
sub.f32 %f737, %f733, %f736;
|
|
add.f32 %f738, %f729, %f737;
|
|
add.f32 %f739, %f731, %f738;
|
|
add.f32 %f740, %f735, %f739;
|
|
add.f32 %f741, %f736, %f740;
|
|
sub.f32 %f742, %f736, %f741;
|
|
add.f32 %f743, %f740, %f742;
|
|
mul.rn.f32 %f744, %f695, %f741;
|
|
neg.f32 %f745, %f744;
|
|
fma.rn.f32 %f746, %f695, %f741, %f745;
|
|
fma.rn.f32 %f747, %f695, %f743, %f746;
|
|
mov.f32 %f748, 0f00000000;
|
|
fma.rn.f32 %f749, %f748, %f741, %f747;
|
|
add.rn.f32 %f750, %f744, %f749;
|
|
neg.f32 %f751, %f750;
|
|
add.rn.f32 %f752, %f744, %f751;
|
|
add.rn.f32 %f753, %f752, %f749;
|
|
mov.b32 %r318, %f750;
|
|
setp.eq.s32 %p78, %r318, 1118925336;
|
|
add.s32 %r319, %r318, -1;
|
|
mov.b32 %f754, %r319;
|
|
add.f32 %f755, %f753, 0f37000000;
|
|
selp.f32 %f174, %f755, %f753, %p78;
|
|
selp.f32 %f756, %f754, %f750, %p78;
|
|
mov.f32 %f757, 0f3FB8AA3B;
|
|
mul.rn.f32 %f758, %f756, %f757;
|
|
cvt.rzi.f32.f32 %f759, %f758;
|
|
abs.f32 %f760, %f759;
|
|
setp.gt.f32 %p79, %f760, 0f42FC0000;
|
|
mov.b32 %r320, %f759;
|
|
and.b32 %r321, %r320, -2147483648;
|
|
or.b32 %r322, %r321, 1123811328;
|
|
mov.b32 %f761, %r322;
|
|
selp.f32 %f762, %f761, %f759, %p79;
|
|
mov.f32 %f763, 0fBF317218;
|
|
fma.rn.f32 %f764, %f762, %f763, %f756;
|
|
mov.f32 %f765, 0f3102E308;
|
|
fma.rn.f32 %f766, %f762, %f765, %f764;
|
|
mul.f32 %f767, %f766, 0f3FB8AA3B;
|
|
add.f32 %f768, %f762, 0f4B40007F;
|
|
mov.b32 %r323, %f768;
|
|
shl.b32 %r324, %r323, 23;
|
|
mov.b32 %f769, %r324;
|
|
ex2.approx.ftz.f32 %f770, %f767;
|
|
mul.f32 %f175, %f770, %f769;
|
|
setp.eq.f32 %p80, %f175, 0f7F800000;
|
|
mov.f32 %f1467, 0f7F800000;
|
|
@%p80 bra $L__BB0_67;
|
|
|
|
fma.rn.f32 %f1467, %f175, %f174, %f175;
|
|
|
|
$L__BB0_67:
|
|
setp.lt.f32 %p81, %f171, 0f00000000;
|
|
setp.eq.f32 %p82, %f172, 0f3F800000;
|
|
and.pred %p3, %p81, %p82;
|
|
setp.eq.f32 %p83, %f171, 0f00000000;
|
|
@%p83 bra $L__BB0_71;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_71:
|
|
add.f32 %f775, %f171, %f171;
|
|
selp.f32 %f1469, %f775, 0f00000000, %p82;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_172:
|
|
mov.f32 %f1370, 0f00000000;
|
|
mov.u32 %r467, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1370;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1370;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs125, %f1370;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs128, 0;
|
|
st.global.v4.u16 [%rd28], {%rs125, %rs126, %rs127, %rs128};
|
|
|
|
$L__BB0_173:
|
|
ld.const.u64 %rd107, [params+256];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r443, [params+248];
|
|
mad.lo.s32 %r444, %r443, %r7, %r6;
|
|
mul.wide.u32 %rd109, %r444, 8;
|
|
add.s64 %rd29, %rd108, %rd109;
|
|
setp.eq.s32 %p201, %r467, 0;
|
|
@%p201 bra $L__BB0_175;
|
|
|
|
ld.global.v4.u16 {%rs135, %rs136, %rs137, %rs138}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1371, %rs135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1372, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1373, %rs137;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1374, %f1371, 0f00000000;
|
|
add.f32 %f1375, %f1372, 0f00000000;
|
|
add.f32 %f1376, %f1373, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1376;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1375;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1374;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs139, 0;
|
|
st.global.v4.u16 [%rd29], {%rs132, %rs133, %rs134, %rs139};
|
|
bra.uni $L__BB0_176;
|
|
|
|
$L__BB0_175:
|
|
mov.f32 %f1379, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1379;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1379;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs140, %f1379;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs143, 0;
|
|
st.global.v4.u16 [%rd29], {%rs140, %rs141, %rs142, %rs143};
|
|
|
|
$L__BB0_176:
|
|
ld.const.u64 %rd110, [params+272];
|
|
cvta.to.global.u64 %rd111, %rd110;
|
|
ld.const.u32 %r445, [params+264];
|
|
mad.lo.s32 %r446, %r445, %r7, %r6;
|
|
mul.wide.u32 %rd112, %r446, 8;
|
|
add.s64 %rd30, %rd111, %rd112;
|
|
@%p201 bra $L__BB0_178;
|
|
|
|
ld.global.v4.u16 {%rs150, %rs151, %rs152, %rs153}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1380, %rs150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1381, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1382, %rs152;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1383, %f1380, 0f00000000;
|
|
add.f32 %f1384, %f1381, 0f00000000;
|
|
add.f32 %f1385, %f1382, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1385;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1384;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1383;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs154, 0;
|
|
st.global.v4.u16 [%rd30], {%rs147, %rs148, %rs149, %rs154};
|
|
bra.uni $L__BB0_179;
|
|
|
|
$L__BB0_178:
|
|
mov.f32 %f1388, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1388;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1388;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs155, %f1388;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs158, 0;
|
|
st.global.v4.u16 [%rd30], {%rs155, %rs156, %rs157, %rs158};
|
|
|
|
$L__BB0_179:
|
|
ld.const.u64 %rd113, [params+288];
|
|
cvta.to.global.u64 %rd114, %rd113;
|
|
ld.const.u32 %r447, [params+280];
|
|
mad.lo.s32 %r448, %r447, %r7, %r6;
|
|
mul.wide.u32 %rd115, %r448, 8;
|
|
add.s64 %rd31, %rd114, %rd115;
|
|
@%p201 bra $L__BB0_181;
|
|
|
|
ld.global.v4.u16 {%rs165, %rs166, %rs167, %rs168}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1389, %rs165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1390, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1391, %rs167;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1392, %f1389, 0f00000000;
|
|
add.f32 %f1393, %f1390, 0f00000000;
|
|
add.f32 %f1394, %f1391, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1394;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1393;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1392;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs169, 0;
|
|
st.global.v4.u16 [%rd31], {%rs162, %rs163, %rs164, %rs169};
|
|
bra.uni $L__BB0_182;
|
|
|
|
$L__BB0_181:
|
|
mov.f32 %f1397, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1397;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1397;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs170, %f1397;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs173, 0;
|
|
st.global.v4.u16 [%rd31], {%rs170, %rs171, %rs172, %rs173};
|
|
bra.uni $L__BB0_182;
|
|
|
|
$L__BB0_68:
|
|
mov.b32 %r325, %f1467;
|
|
xor.b32 %r326, %r325, -2147483648;
|
|
mov.b32 %f771, %r326;
|
|
selp.f32 %f1469, %f771, %f1467, %p3;
|
|
setp.geu.f32 %p84, %f171, 0f00000000;
|
|
@%p84 bra $L__BB0_72;
|
|
|
|
mov.f32 %f772, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f773, %f772;
|
|
setp.eq.f32 %p85, %f773, 0f3EE8BA2E;
|
|
@%p85 bra $L__BB0_72;
|
|
|
|
mov.f32 %f1469, 0f7FFFFFFF;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f776, %f173, 0f3EE8BA2E;
|
|
mov.b32 %r327, %f776;
|
|
setp.lt.s32 %p87, %r327, 2139095040;
|
|
@%p87 bra $L__BB0_77;
|
|
|
|
setp.gtu.f32 %p88, %f173, 0f7F800000;
|
|
@%p88 bra $L__BB0_76;
|
|
bra.uni $L__BB0_74;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f1469, %f171, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_77;
|
|
|
|
$L__BB0_74:
|
|
setp.neu.f32 %p89, %f173, 0f7F800000;
|
|
@%p89 bra $L__BB0_77;
|
|
|
|
selp.f32 %f1469, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_77:
|
|
mul.f32 %f777, %f1469, 0f437F0000;
|
|
setp.eq.f32 %p90, %f171, 0f3F800000;
|
|
selp.f32 %f778, 0f437F0000, %f777, %p90;
|
|
cvt.rzi.u32.f32 %r328, %f778;
|
|
shl.b64 %rd79, %rd21, 1;
|
|
add.s64 %rd80, %rd20, %rd79;
|
|
cvt.u16.u32 %rs45, %r328;
|
|
mov.u16 %rs46, 255;
|
|
st.global.v2.u8 [%rd80], {%rs45, %rs46};
|
|
|
|
$L__BB0_78:
|
|
ld.const.v2.f32 {%f779, %f780}, [params+648];
|
|
mul.f32 %f186, %f1466, %f779;
|
|
mul.f32 %f187, %f1466, %f780;
|
|
ld.const.f32 %f188, [params+656];
|
|
mul.f32 %f189, %f1466, %f188;
|
|
and.b32 %r329, %r56, 1;
|
|
setp.eq.b32 %p91, %r329, 1;
|
|
mov.pred %p92, 0;
|
|
xor.pred %p93, %p91, %p92;
|
|
not.pred %p94, %p93;
|
|
@%p94 bra $L__BB0_152;
|
|
|
|
mov.f32 %f782, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f783, %f782;
|
|
add.f32 %f784, %f783, %f783;
|
|
mov.f32 %f785, 0f3EE66666;
|
|
sub.f32 %f786, %f785, %f784;
|
|
abs.f32 %f190, %f786;
|
|
abs.f32 %f191, %f186;
|
|
setp.lt.f32 %p95, %f191, 0f00800000;
|
|
mul.f32 %f787, %f191, 0f4B800000;
|
|
selp.f32 %f788, %f787, %f191, %p95;
|
|
selp.f32 %f789, 0fC3170000, 0fC2FE0000, %p95;
|
|
mov.b32 %r330, %f788;
|
|
and.b32 %r331, %r330, 8388607;
|
|
or.b32 %r332, %r331, 1065353216;
|
|
mov.b32 %f790, %r332;
|
|
shr.u32 %r333, %r330, 23;
|
|
cvt.rn.f32.u32 %f791, %r333;
|
|
add.f32 %f792, %f789, %f791;
|
|
setp.gt.f32 %p96, %f790, 0f3FB504F3;
|
|
mul.f32 %f793, %f790, 0f3F000000;
|
|
add.f32 %f794, %f792, 0f3F800000;
|
|
selp.f32 %f795, %f794, %f792, %p96;
|
|
selp.f32 %f796, %f793, %f790, %p96;
|
|
add.f32 %f797, %f796, 0fBF800000;
|
|
add.f32 %f798, %f796, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f799, %f798;
|
|
add.f32 %f800, %f797, %f797;
|
|
mul.f32 %f801, %f800, %f799;
|
|
mul.f32 %f802, %f801, %f801;
|
|
mov.f32 %f803, 0f3C4CAF63;
|
|
mov.f32 %f804, 0f3B18F0FE;
|
|
fma.rn.f32 %f805, %f804, %f802, %f803;
|
|
mov.f32 %f806, 0f3DAAAABD;
|
|
fma.rn.f32 %f807, %f805, %f802, %f806;
|
|
mul.rn.f32 %f808, %f807, %f802;
|
|
mul.rn.f32 %f809, %f808, %f801;
|
|
sub.f32 %f810, %f797, %f801;
|
|
add.f32 %f811, %f810, %f810;
|
|
neg.f32 %f812, %f801;
|
|
fma.rn.f32 %f813, %f812, %f797, %f811;
|
|
mul.rn.f32 %f814, %f799, %f813;
|
|
add.f32 %f815, %f809, %f801;
|
|
sub.f32 %f816, %f801, %f815;
|
|
add.f32 %f817, %f809, %f816;
|
|
add.f32 %f818, %f814, %f817;
|
|
add.f32 %f819, %f815, %f818;
|
|
sub.f32 %f820, %f815, %f819;
|
|
add.f32 %f821, %f818, %f820;
|
|
mov.f32 %f822, 0f3F317200;
|
|
mul.rn.f32 %f823, %f795, %f822;
|
|
mov.f32 %f824, 0f35BFBE8E;
|
|
mul.rn.f32 %f825, %f795, %f824;
|
|
add.f32 %f826, %f823, %f819;
|
|
sub.f32 %f827, %f823, %f826;
|
|
add.f32 %f828, %f819, %f827;
|
|
add.f32 %f829, %f821, %f828;
|
|
add.f32 %f830, %f825, %f829;
|
|
add.f32 %f831, %f826, %f830;
|
|
sub.f32 %f832, %f826, %f831;
|
|
add.f32 %f833, %f830, %f832;
|
|
mul.rn.f32 %f834, %f785, %f831;
|
|
neg.f32 %f835, %f834;
|
|
fma.rn.f32 %f836, %f785, %f831, %f835;
|
|
fma.rn.f32 %f837, %f785, %f833, %f836;
|
|
mov.f32 %f838, 0f00000000;
|
|
fma.rn.f32 %f839, %f838, %f831, %f837;
|
|
add.rn.f32 %f840, %f834, %f839;
|
|
neg.f32 %f841, %f840;
|
|
add.rn.f32 %f842, %f834, %f841;
|
|
add.rn.f32 %f843, %f842, %f839;
|
|
mov.b32 %r334, %f840;
|
|
setp.eq.s32 %p97, %r334, 1118925336;
|
|
add.s32 %r335, %r334, -1;
|
|
mov.b32 %f844, %r335;
|
|
add.f32 %f845, %f843, 0f37000000;
|
|
selp.f32 %f192, %f845, %f843, %p97;
|
|
selp.f32 %f846, %f844, %f840, %p97;
|
|
mov.f32 %f847, 0f3FB8AA3B;
|
|
mul.rn.f32 %f848, %f846, %f847;
|
|
cvt.rzi.f32.f32 %f849, %f848;
|
|
abs.f32 %f850, %f849;
|
|
setp.gt.f32 %p98, %f850, 0f42FC0000;
|
|
mov.b32 %r336, %f849;
|
|
and.b32 %r337, %r336, -2147483648;
|
|
or.b32 %r338, %r337, 1123811328;
|
|
mov.b32 %f851, %r338;
|
|
selp.f32 %f852, %f851, %f849, %p98;
|
|
mov.f32 %f853, 0fBF317218;
|
|
fma.rn.f32 %f854, %f852, %f853, %f846;
|
|
mov.f32 %f855, 0f3102E308;
|
|
fma.rn.f32 %f856, %f852, %f855, %f854;
|
|
mul.f32 %f857, %f856, 0f3FB8AA3B;
|
|
add.f32 %f858, %f852, 0f4B40007F;
|
|
mov.b32 %r339, %f858;
|
|
shl.b32 %r340, %r339, 23;
|
|
mov.b32 %f859, %r340;
|
|
ex2.approx.ftz.f32 %f860, %f857;
|
|
mul.f32 %f193, %f860, %f859;
|
|
setp.eq.f32 %p99, %f193, 0f7F800000;
|
|
mov.f32 %f1470, 0f7F800000;
|
|
@%p99 bra $L__BB0_81;
|
|
|
|
fma.rn.f32 %f1470, %f193, %f192, %f193;
|
|
|
|
$L__BB0_81:
|
|
setp.lt.f32 %p100, %f186, 0f00000000;
|
|
setp.eq.f32 %p101, %f190, 0f3F800000;
|
|
and.pred %p4, %p100, %p101;
|
|
setp.eq.f32 %p102, %f186, 0f00000000;
|
|
@%p102 bra $L__BB0_85;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_85:
|
|
add.f32 %f865, %f186, %f186;
|
|
selp.f32 %f1472, %f865, 0f00000000, %p101;
|
|
bra.uni $L__BB0_86;
|
|
|
|
$L__BB0_82:
|
|
mov.b32 %r341, %f1470;
|
|
xor.b32 %r342, %r341, -2147483648;
|
|
mov.b32 %f861, %r342;
|
|
selp.f32 %f1472, %f861, %f1470, %p4;
|
|
setp.geu.f32 %p103, %f186, 0f00000000;
|
|
@%p103 bra $L__BB0_86;
|
|
|
|
mov.f32 %f862, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f863, %f862;
|
|
setp.eq.f32 %p104, %f863, 0f3EE66666;
|
|
@%p104 bra $L__BB0_86;
|
|
|
|
mov.f32 %f1472, 0f7FFFFFFF;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f866, %f191, 0f3EE66666;
|
|
mov.b32 %r343, %f866;
|
|
setp.lt.s32 %p106, %r343, 2139095040;
|
|
@%p106 bra $L__BB0_91;
|
|
|
|
setp.gtu.f32 %p107, %f191, 0f7F800000;
|
|
@%p107 bra $L__BB0_90;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_90:
|
|
add.f32 %f1472, %f186, 0f3EE66666;
|
|
bra.uni $L__BB0_91;
|
|
|
|
$L__BB0_88:
|
|
setp.neu.f32 %p108, %f191, 0f7F800000;
|
|
@%p108 bra $L__BB0_91;
|
|
|
|
selp.f32 %f1472, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_91:
|
|
setp.eq.f32 %p109, %f186, 0f3F800000;
|
|
selp.f32 %f202, 0f3F800000, %f1472, %p109;
|
|
abs.f32 %f203, %f187;
|
|
setp.lt.f32 %p110, %f203, 0f00800000;
|
|
mul.f32 %f868, %f203, 0f4B800000;
|
|
selp.f32 %f869, %f868, %f203, %p110;
|
|
selp.f32 %f870, 0fC3170000, 0fC2FE0000, %p110;
|
|
mov.b32 %r344, %f869;
|
|
and.b32 %r345, %r344, 8388607;
|
|
or.b32 %r346, %r345, 1065353216;
|
|
mov.b32 %f871, %r346;
|
|
shr.u32 %r347, %r344, 23;
|
|
cvt.rn.f32.u32 %f872, %r347;
|
|
add.f32 %f873, %f870, %f872;
|
|
setp.gt.f32 %p111, %f871, 0f3FB504F3;
|
|
mul.f32 %f874, %f871, 0f3F000000;
|
|
add.f32 %f875, %f873, 0f3F800000;
|
|
selp.f32 %f876, %f875, %f873, %p111;
|
|
selp.f32 %f877, %f874, %f871, %p111;
|
|
add.f32 %f878, %f877, 0fBF800000;
|
|
add.f32 %f879, %f877, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f880, %f879;
|
|
add.f32 %f881, %f878, %f878;
|
|
mul.f32 %f882, %f881, %f880;
|
|
mul.f32 %f883, %f882, %f882;
|
|
mov.f32 %f884, 0f3C4CAF63;
|
|
mov.f32 %f885, 0f3B18F0FE;
|
|
fma.rn.f32 %f886, %f885, %f883, %f884;
|
|
mov.f32 %f887, 0f3DAAAABD;
|
|
fma.rn.f32 %f888, %f886, %f883, %f887;
|
|
mul.rn.f32 %f889, %f888, %f883;
|
|
mul.rn.f32 %f890, %f889, %f882;
|
|
sub.f32 %f891, %f878, %f882;
|
|
add.f32 %f892, %f891, %f891;
|
|
neg.f32 %f893, %f882;
|
|
fma.rn.f32 %f894, %f893, %f878, %f892;
|
|
mul.rn.f32 %f895, %f880, %f894;
|
|
add.f32 %f896, %f890, %f882;
|
|
sub.f32 %f897, %f882, %f896;
|
|
add.f32 %f898, %f890, %f897;
|
|
add.f32 %f899, %f895, %f898;
|
|
add.f32 %f900, %f896, %f899;
|
|
sub.f32 %f901, %f896, %f900;
|
|
add.f32 %f902, %f899, %f901;
|
|
mov.f32 %f903, 0f3F317200;
|
|
mul.rn.f32 %f904, %f876, %f903;
|
|
mov.f32 %f905, 0f35BFBE8E;
|
|
mul.rn.f32 %f906, %f876, %f905;
|
|
add.f32 %f907, %f904, %f900;
|
|
sub.f32 %f908, %f904, %f907;
|
|
add.f32 %f909, %f900, %f908;
|
|
add.f32 %f910, %f902, %f909;
|
|
add.f32 %f911, %f906, %f910;
|
|
add.f32 %f912, %f907, %f911;
|
|
sub.f32 %f913, %f907, %f912;
|
|
add.f32 %f914, %f911, %f913;
|
|
mov.f32 %f915, 0f3EE66666;
|
|
mul.rn.f32 %f916, %f915, %f912;
|
|
neg.f32 %f917, %f916;
|
|
fma.rn.f32 %f918, %f915, %f912, %f917;
|
|
fma.rn.f32 %f919, %f915, %f914, %f918;
|
|
mov.f32 %f920, 0f00000000;
|
|
fma.rn.f32 %f921, %f920, %f912, %f919;
|
|
add.rn.f32 %f922, %f916, %f921;
|
|
neg.f32 %f923, %f922;
|
|
add.rn.f32 %f924, %f916, %f923;
|
|
add.rn.f32 %f925, %f924, %f921;
|
|
mov.b32 %r348, %f922;
|
|
setp.eq.s32 %p112, %r348, 1118925336;
|
|
add.s32 %r349, %r348, -1;
|
|
mov.b32 %f926, %r349;
|
|
add.f32 %f927, %f925, 0f37000000;
|
|
selp.f32 %f204, %f927, %f925, %p112;
|
|
selp.f32 %f928, %f926, %f922, %p112;
|
|
mov.f32 %f929, 0f3FB8AA3B;
|
|
mul.rn.f32 %f930, %f928, %f929;
|
|
cvt.rzi.f32.f32 %f931, %f930;
|
|
abs.f32 %f932, %f931;
|
|
setp.gt.f32 %p113, %f932, 0f42FC0000;
|
|
mov.b32 %r350, %f931;
|
|
and.b32 %r351, %r350, -2147483648;
|
|
or.b32 %r352, %r351, 1123811328;
|
|
mov.b32 %f933, %r352;
|
|
selp.f32 %f934, %f933, %f931, %p113;
|
|
mov.f32 %f935, 0fBF317218;
|
|
fma.rn.f32 %f936, %f934, %f935, %f928;
|
|
mov.f32 %f937, 0f3102E308;
|
|
fma.rn.f32 %f938, %f934, %f937, %f936;
|
|
mul.f32 %f939, %f938, 0f3FB8AA3B;
|
|
add.f32 %f940, %f934, 0f4B40007F;
|
|
mov.b32 %r353, %f940;
|
|
shl.b32 %r354, %r353, 23;
|
|
mov.b32 %f941, %r354;
|
|
ex2.approx.ftz.f32 %f942, %f939;
|
|
mul.f32 %f205, %f942, %f941;
|
|
setp.eq.f32 %p114, %f205, 0f7F800000;
|
|
mov.f32 %f1473, 0f7F800000;
|
|
@%p114 bra $L__BB0_93;
|
|
|
|
fma.rn.f32 %f1473, %f205, %f204, %f205;
|
|
|
|
$L__BB0_93:
|
|
setp.lt.f32 %p115, %f187, 0f00000000;
|
|
and.pred %p5, %p115, %p101;
|
|
setp.eq.f32 %p117, %f187, 0f00000000;
|
|
@%p117 bra $L__BB0_97;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_97:
|
|
add.f32 %f947, %f187, %f187;
|
|
selp.f32 %f1475, %f947, 0f00000000, %p101;
|
|
bra.uni $L__BB0_98;
|
|
|
|
$L__BB0_94:
|
|
mov.b32 %r355, %f1473;
|
|
xor.b32 %r356, %r355, -2147483648;
|
|
mov.b32 %f943, %r356;
|
|
selp.f32 %f1475, %f943, %f1473, %p5;
|
|
setp.geu.f32 %p118, %f187, 0f00000000;
|
|
@%p118 bra $L__BB0_98;
|
|
|
|
mov.f32 %f944, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f945, %f944;
|
|
setp.eq.f32 %p119, %f945, 0f3EE66666;
|
|
@%p119 bra $L__BB0_98;
|
|
|
|
mov.f32 %f1475, 0f7FFFFFFF;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f948, %f203, 0f3EE66666;
|
|
mov.b32 %r357, %f948;
|
|
setp.lt.s32 %p121, %r357, 2139095040;
|
|
@%p121 bra $L__BB0_103;
|
|
|
|
setp.gtu.f32 %p122, %f203, 0f7F800000;
|
|
@%p122 bra $L__BB0_102;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_102:
|
|
add.f32 %f1475, %f187, 0f3EE66666;
|
|
bra.uni $L__BB0_103;
|
|
|
|
$L__BB0_100:
|
|
setp.neu.f32 %p123, %f203, 0f7F800000;
|
|
@%p123 bra $L__BB0_103;
|
|
|
|
selp.f32 %f1475, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_103:
|
|
setp.eq.f32 %p124, %f187, 0f3F800000;
|
|
selp.f32 %f214, 0f3F800000, %f1475, %p124;
|
|
abs.f32 %f215, %f189;
|
|
setp.lt.f32 %p125, %f215, 0f00800000;
|
|
mul.f32 %f950, %f215, 0f4B800000;
|
|
selp.f32 %f951, %f950, %f215, %p125;
|
|
selp.f32 %f952, 0fC3170000, 0fC2FE0000, %p125;
|
|
mov.b32 %r358, %f951;
|
|
and.b32 %r359, %r358, 8388607;
|
|
or.b32 %r360, %r359, 1065353216;
|
|
mov.b32 %f953, %r360;
|
|
shr.u32 %r361, %r358, 23;
|
|
cvt.rn.f32.u32 %f954, %r361;
|
|
add.f32 %f955, %f952, %f954;
|
|
setp.gt.f32 %p126, %f953, 0f3FB504F3;
|
|
mul.f32 %f956, %f953, 0f3F000000;
|
|
add.f32 %f957, %f955, 0f3F800000;
|
|
selp.f32 %f958, %f957, %f955, %p126;
|
|
selp.f32 %f959, %f956, %f953, %p126;
|
|
add.f32 %f960, %f959, 0fBF800000;
|
|
add.f32 %f961, %f959, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f962, %f961;
|
|
add.f32 %f963, %f960, %f960;
|
|
mul.f32 %f964, %f963, %f962;
|
|
mul.f32 %f965, %f964, %f964;
|
|
mov.f32 %f966, 0f3C4CAF63;
|
|
mov.f32 %f967, 0f3B18F0FE;
|
|
fma.rn.f32 %f968, %f967, %f965, %f966;
|
|
mov.f32 %f969, 0f3DAAAABD;
|
|
fma.rn.f32 %f970, %f968, %f965, %f969;
|
|
mul.rn.f32 %f971, %f970, %f965;
|
|
mul.rn.f32 %f972, %f971, %f964;
|
|
sub.f32 %f973, %f960, %f964;
|
|
add.f32 %f974, %f973, %f973;
|
|
neg.f32 %f975, %f964;
|
|
fma.rn.f32 %f976, %f975, %f960, %f974;
|
|
mul.rn.f32 %f977, %f962, %f976;
|
|
add.f32 %f978, %f972, %f964;
|
|
sub.f32 %f979, %f964, %f978;
|
|
add.f32 %f980, %f972, %f979;
|
|
add.f32 %f981, %f977, %f980;
|
|
add.f32 %f982, %f978, %f981;
|
|
sub.f32 %f983, %f978, %f982;
|
|
add.f32 %f984, %f981, %f983;
|
|
mov.f32 %f985, 0f3F317200;
|
|
mul.rn.f32 %f986, %f958, %f985;
|
|
mov.f32 %f987, 0f35BFBE8E;
|
|
mul.rn.f32 %f988, %f958, %f987;
|
|
add.f32 %f989, %f986, %f982;
|
|
sub.f32 %f990, %f986, %f989;
|
|
add.f32 %f991, %f982, %f990;
|
|
add.f32 %f992, %f984, %f991;
|
|
add.f32 %f993, %f988, %f992;
|
|
add.f32 %f994, %f989, %f993;
|
|
sub.f32 %f995, %f989, %f994;
|
|
add.f32 %f996, %f993, %f995;
|
|
mov.f32 %f997, 0f3EE66666;
|
|
mul.rn.f32 %f998, %f997, %f994;
|
|
neg.f32 %f999, %f998;
|
|
fma.rn.f32 %f1000, %f997, %f994, %f999;
|
|
fma.rn.f32 %f1001, %f997, %f996, %f1000;
|
|
mov.f32 %f1002, 0f00000000;
|
|
fma.rn.f32 %f1003, %f1002, %f994, %f1001;
|
|
add.rn.f32 %f1004, %f998, %f1003;
|
|
neg.f32 %f1005, %f1004;
|
|
add.rn.f32 %f1006, %f998, %f1005;
|
|
add.rn.f32 %f1007, %f1006, %f1003;
|
|
mov.b32 %r362, %f1004;
|
|
setp.eq.s32 %p127, %r362, 1118925336;
|
|
add.s32 %r363, %r362, -1;
|
|
mov.b32 %f1008, %r363;
|
|
add.f32 %f1009, %f1007, 0f37000000;
|
|
selp.f32 %f216, %f1009, %f1007, %p127;
|
|
selp.f32 %f1010, %f1008, %f1004, %p127;
|
|
mov.f32 %f1011, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1012, %f1010, %f1011;
|
|
cvt.rzi.f32.f32 %f1013, %f1012;
|
|
abs.f32 %f1014, %f1013;
|
|
setp.gt.f32 %p128, %f1014, 0f42FC0000;
|
|
mov.b32 %r364, %f1013;
|
|
and.b32 %r365, %r364, -2147483648;
|
|
or.b32 %r366, %r365, 1123811328;
|
|
mov.b32 %f1015, %r366;
|
|
selp.f32 %f1016, %f1015, %f1013, %p128;
|
|
mov.f32 %f1017, 0fBF317218;
|
|
fma.rn.f32 %f1018, %f1016, %f1017, %f1010;
|
|
mov.f32 %f1019, 0f3102E308;
|
|
fma.rn.f32 %f1020, %f1016, %f1019, %f1018;
|
|
mul.f32 %f1021, %f1020, 0f3FB8AA3B;
|
|
add.f32 %f1022, %f1016, 0f4B40007F;
|
|
mov.b32 %r367, %f1022;
|
|
shl.b32 %r368, %r367, 23;
|
|
mov.b32 %f1023, %r368;
|
|
ex2.approx.ftz.f32 %f1024, %f1021;
|
|
mul.f32 %f217, %f1024, %f1023;
|
|
setp.eq.f32 %p129, %f217, 0f7F800000;
|
|
mov.f32 %f1476, 0f7F800000;
|
|
@%p129 bra $L__BB0_105;
|
|
|
|
fma.rn.f32 %f1476, %f217, %f216, %f217;
|
|
|
|
$L__BB0_105:
|
|
setp.lt.f32 %p130, %f189, 0f00000000;
|
|
and.pred %p6, %p130, %p101;
|
|
setp.eq.f32 %p132, %f189, 0f00000000;
|
|
@%p132 bra $L__BB0_109;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_109:
|
|
add.f32 %f1029, %f189, %f189;
|
|
selp.f32 %f1478, %f1029, 0f00000000, %p101;
|
|
bra.uni $L__BB0_110;
|
|
|
|
$L__BB0_106:
|
|
mov.b32 %r369, %f1476;
|
|
xor.b32 %r370, %r369, -2147483648;
|
|
mov.b32 %f1025, %r370;
|
|
selp.f32 %f1478, %f1025, %f1476, %p6;
|
|
setp.geu.f32 %p133, %f189, 0f00000000;
|
|
@%p133 bra $L__BB0_110;
|
|
|
|
mov.f32 %f1026, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1027, %f1026;
|
|
setp.eq.f32 %p134, %f1027, 0f3EE66666;
|
|
@%p134 bra $L__BB0_110;
|
|
|
|
mov.f32 %f1478, 0f7FFFFFFF;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1030, %f215, 0f3EE66666;
|
|
mov.b32 %r371, %f1030;
|
|
setp.lt.s32 %p136, %r371, 2139095040;
|
|
@%p136 bra $L__BB0_115;
|
|
|
|
setp.gtu.f32 %p137, %f215, 0f7F800000;
|
|
@%p137 bra $L__BB0_114;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_114:
|
|
add.f32 %f1478, %f189, 0f3EE66666;
|
|
bra.uni $L__BB0_115;
|
|
|
|
$L__BB0_112:
|
|
setp.neu.f32 %p138, %f215, 0f7F800000;
|
|
@%p138 bra $L__BB0_115;
|
|
|
|
selp.f32 %f1478, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_115:
|
|
setp.eq.f32 %p139, %f189, 0f3F800000;
|
|
mov.f32 %f1032, 0f3F800000;
|
|
selp.f32 %f1033, 0f3F800000, %f1478, %p139;
|
|
ld.const.u64 %rd81, [params+144];
|
|
cvta.to.global.u64 %rd22, %rd81;
|
|
ld.const.u32 %r372, [params+136];
|
|
mad.lo.s32 %r373, %r372, %r7, %r6;
|
|
cvt.u64.u32 %rd23, %r373;
|
|
min.f32 %f1034, %f202, %f1032;
|
|
mov.f32 %f1035, 0f00000000;
|
|
max.f32 %f226, %f1035, %f1034;
|
|
min.f32 %f1036, %f214, %f1032;
|
|
max.f32 %f227, %f1035, %f1036;
|
|
min.f32 %f1037, %f1033, %f1032;
|
|
max.f32 %f228, %f1035, %f1037;
|
|
mov.f32 %f1038, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1039, %f1038;
|
|
add.f32 %f1040, %f1039, %f1039;
|
|
mov.f32 %f1041, 0f3ED55555;
|
|
sub.f32 %f1042, %f1041, %f1040;
|
|
abs.f32 %f229, %f1042;
|
|
abs.f32 %f230, %f226;
|
|
setp.lt.f32 %p140, %f230, 0f00800000;
|
|
mul.f32 %f1043, %f230, 0f4B800000;
|
|
selp.f32 %f1044, %f1043, %f230, %p140;
|
|
selp.f32 %f1045, 0fC3170000, 0fC2FE0000, %p140;
|
|
mov.b32 %r374, %f1044;
|
|
and.b32 %r375, %r374, 8388607;
|
|
or.b32 %r376, %r375, 1065353216;
|
|
mov.b32 %f1046, %r376;
|
|
shr.u32 %r377, %r374, 23;
|
|
cvt.rn.f32.u32 %f1047, %r377;
|
|
add.f32 %f1048, %f1045, %f1047;
|
|
setp.gt.f32 %p141, %f1046, 0f3FB504F3;
|
|
mul.f32 %f1049, %f1046, 0f3F000000;
|
|
add.f32 %f1050, %f1048, 0f3F800000;
|
|
selp.f32 %f1051, %f1050, %f1048, %p141;
|
|
selp.f32 %f1052, %f1049, %f1046, %p141;
|
|
add.f32 %f1053, %f1052, 0fBF800000;
|
|
add.f32 %f1054, %f1052, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1055, %f1054;
|
|
add.f32 %f1056, %f1053, %f1053;
|
|
mul.f32 %f1057, %f1056, %f1055;
|
|
mul.f32 %f1058, %f1057, %f1057;
|
|
mov.f32 %f1059, 0f3C4CAF63;
|
|
mov.f32 %f1060, 0f3B18F0FE;
|
|
fma.rn.f32 %f1061, %f1060, %f1058, %f1059;
|
|
mov.f32 %f1062, 0f3DAAAABD;
|
|
fma.rn.f32 %f1063, %f1061, %f1058, %f1062;
|
|
mul.rn.f32 %f1064, %f1063, %f1058;
|
|
mul.rn.f32 %f1065, %f1064, %f1057;
|
|
sub.f32 %f1066, %f1053, %f1057;
|
|
add.f32 %f1067, %f1066, %f1066;
|
|
neg.f32 %f1068, %f1057;
|
|
fma.rn.f32 %f1069, %f1068, %f1053, %f1067;
|
|
mul.rn.f32 %f1070, %f1055, %f1069;
|
|
add.f32 %f1071, %f1065, %f1057;
|
|
sub.f32 %f1072, %f1057, %f1071;
|
|
add.f32 %f1073, %f1065, %f1072;
|
|
add.f32 %f1074, %f1070, %f1073;
|
|
add.f32 %f1075, %f1071, %f1074;
|
|
sub.f32 %f1076, %f1071, %f1075;
|
|
add.f32 %f1077, %f1074, %f1076;
|
|
mov.f32 %f1078, 0f3F317200;
|
|
mul.rn.f32 %f1079, %f1051, %f1078;
|
|
mov.f32 %f1080, 0f35BFBE8E;
|
|
mul.rn.f32 %f1081, %f1051, %f1080;
|
|
add.f32 %f1082, %f1079, %f1075;
|
|
sub.f32 %f1083, %f1079, %f1082;
|
|
add.f32 %f1084, %f1075, %f1083;
|
|
add.f32 %f1085, %f1077, %f1084;
|
|
add.f32 %f1086, %f1081, %f1085;
|
|
add.f32 %f1087, %f1082, %f1086;
|
|
sub.f32 %f1088, %f1082, %f1087;
|
|
add.f32 %f1089, %f1086, %f1088;
|
|
mul.rn.f32 %f1090, %f1041, %f1087;
|
|
neg.f32 %f1091, %f1090;
|
|
fma.rn.f32 %f1092, %f1041, %f1087, %f1091;
|
|
fma.rn.f32 %f1093, %f1041, %f1089, %f1092;
|
|
fma.rn.f32 %f1094, %f1035, %f1087, %f1093;
|
|
add.rn.f32 %f1095, %f1090, %f1094;
|
|
neg.f32 %f1096, %f1095;
|
|
add.rn.f32 %f1097, %f1090, %f1096;
|
|
add.rn.f32 %f1098, %f1097, %f1094;
|
|
mov.b32 %r378, %f1095;
|
|
setp.eq.s32 %p142, %r378, 1118925336;
|
|
add.s32 %r379, %r378, -1;
|
|
mov.b32 %f1099, %r379;
|
|
add.f32 %f1100, %f1098, 0f37000000;
|
|
selp.f32 %f231, %f1100, %f1098, %p142;
|
|
selp.f32 %f1101, %f1099, %f1095, %p142;
|
|
mov.f32 %f1102, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1103, %f1101, %f1102;
|
|
cvt.rzi.f32.f32 %f1104, %f1103;
|
|
abs.f32 %f1105, %f1104;
|
|
setp.gt.f32 %p143, %f1105, 0f42FC0000;
|
|
mov.b32 %r380, %f1104;
|
|
and.b32 %r381, %r380, -2147483648;
|
|
or.b32 %r382, %r381, 1123811328;
|
|
mov.b32 %f1106, %r382;
|
|
selp.f32 %f1107, %f1106, %f1104, %p143;
|
|
mov.f32 %f1108, 0fBF317218;
|
|
fma.rn.f32 %f1109, %f1107, %f1108, %f1101;
|
|
mov.f32 %f1110, 0f3102E308;
|
|
fma.rn.f32 %f1111, %f1107, %f1110, %f1109;
|
|
mul.f32 %f1112, %f1111, 0f3FB8AA3B;
|
|
add.f32 %f1113, %f1107, 0f4B40007F;
|
|
mov.b32 %r383, %f1113;
|
|
shl.b32 %r384, %r383, 23;
|
|
mov.b32 %f1114, %r384;
|
|
ex2.approx.ftz.f32 %f1115, %f1112;
|
|
mul.f32 %f232, %f1115, %f1114;
|
|
setp.eq.f32 %p144, %f232, 0f7F800000;
|
|
mov.f32 %f1479, 0f7F800000;
|
|
@%p144 bra $L__BB0_117;
|
|
|
|
fma.rn.f32 %f1479, %f232, %f231, %f232;
|
|
|
|
$L__BB0_117:
|
|
setp.lt.f32 %p145, %f226, 0f00000000;
|
|
setp.eq.f32 %p146, %f229, 0f3F800000;
|
|
and.pred %p7, %p145, %p146;
|
|
setp.eq.f32 %p147, %f226, 0f00000000;
|
|
@%p147 bra $L__BB0_121;
|
|
bra.uni $L__BB0_118;
|
|
|
|
$L__BB0_121:
|
|
add.f32 %f1120, %f226, %f226;
|
|
selp.f32 %f1481, %f1120, 0f00000000, %p146;
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_118:
|
|
mov.b32 %r385, %f1479;
|
|
xor.b32 %r386, %r385, -2147483648;
|
|
mov.b32 %f1116, %r386;
|
|
selp.f32 %f1481, %f1116, %f1479, %p7;
|
|
setp.geu.f32 %p148, %f226, 0f00000000;
|
|
@%p148 bra $L__BB0_122;
|
|
|
|
mov.f32 %f1117, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1118, %f1117;
|
|
setp.eq.f32 %p149, %f1118, 0f3ED55555;
|
|
@%p149 bra $L__BB0_122;
|
|
|
|
mov.f32 %f1481, 0f7FFFFFFF;
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1121, %f230, 0f3ED55555;
|
|
mov.b32 %r387, %f1121;
|
|
setp.lt.s32 %p151, %r387, 2139095040;
|
|
@%p151 bra $L__BB0_127;
|
|
|
|
setp.gtu.f32 %p152, %f230, 0f7F800000;
|
|
@%p152 bra $L__BB0_126;
|
|
bra.uni $L__BB0_124;
|
|
|
|
$L__BB0_126:
|
|
add.f32 %f1481, %f226, 0f3ED55555;
|
|
bra.uni $L__BB0_127;
|
|
|
|
$L__BB0_124:
|
|
setp.neu.f32 %p153, %f230, 0f7F800000;
|
|
@%p153 bra $L__BB0_127;
|
|
|
|
selp.f32 %f1481, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_127:
|
|
abs.f32 %f241, %f227;
|
|
setp.lt.f32 %p154, %f241, 0f00800000;
|
|
mul.f32 %f1123, %f241, 0f4B800000;
|
|
selp.f32 %f1124, %f1123, %f241, %p154;
|
|
selp.f32 %f1125, 0fC3170000, 0fC2FE0000, %p154;
|
|
mov.b32 %r388, %f1124;
|
|
and.b32 %r389, %r388, 8388607;
|
|
or.b32 %r390, %r389, 1065353216;
|
|
mov.b32 %f1126, %r390;
|
|
shr.u32 %r391, %r388, 23;
|
|
cvt.rn.f32.u32 %f1127, %r391;
|
|
add.f32 %f1128, %f1125, %f1127;
|
|
setp.gt.f32 %p155, %f1126, 0f3FB504F3;
|
|
mul.f32 %f1129, %f1126, 0f3F000000;
|
|
add.f32 %f1130, %f1128, 0f3F800000;
|
|
selp.f32 %f1131, %f1130, %f1128, %p155;
|
|
selp.f32 %f1132, %f1129, %f1126, %p155;
|
|
add.f32 %f1133, %f1132, 0fBF800000;
|
|
add.f32 %f1134, %f1132, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1135, %f1134;
|
|
add.f32 %f1136, %f1133, %f1133;
|
|
mul.f32 %f1137, %f1136, %f1135;
|
|
mul.f32 %f1138, %f1137, %f1137;
|
|
mov.f32 %f1139, 0f3C4CAF63;
|
|
mov.f32 %f1140, 0f3B18F0FE;
|
|
fma.rn.f32 %f1141, %f1140, %f1138, %f1139;
|
|
mov.f32 %f1142, 0f3DAAAABD;
|
|
fma.rn.f32 %f1143, %f1141, %f1138, %f1142;
|
|
mul.rn.f32 %f1144, %f1143, %f1138;
|
|
mul.rn.f32 %f1145, %f1144, %f1137;
|
|
sub.f32 %f1146, %f1133, %f1137;
|
|
add.f32 %f1147, %f1146, %f1146;
|
|
neg.f32 %f1148, %f1137;
|
|
fma.rn.f32 %f1149, %f1148, %f1133, %f1147;
|
|
mul.rn.f32 %f1150, %f1135, %f1149;
|
|
add.f32 %f1151, %f1145, %f1137;
|
|
sub.f32 %f1152, %f1137, %f1151;
|
|
add.f32 %f1153, %f1145, %f1152;
|
|
add.f32 %f1154, %f1150, %f1153;
|
|
add.f32 %f1155, %f1151, %f1154;
|
|
sub.f32 %f1156, %f1151, %f1155;
|
|
add.f32 %f1157, %f1154, %f1156;
|
|
mov.f32 %f1158, 0f3F317200;
|
|
mul.rn.f32 %f1159, %f1131, %f1158;
|
|
mov.f32 %f1160, 0f35BFBE8E;
|
|
mul.rn.f32 %f1161, %f1131, %f1160;
|
|
add.f32 %f1162, %f1159, %f1155;
|
|
sub.f32 %f1163, %f1159, %f1162;
|
|
add.f32 %f1164, %f1155, %f1163;
|
|
add.f32 %f1165, %f1157, %f1164;
|
|
add.f32 %f1166, %f1161, %f1165;
|
|
add.f32 %f1167, %f1162, %f1166;
|
|
sub.f32 %f1168, %f1162, %f1167;
|
|
add.f32 %f1169, %f1166, %f1168;
|
|
mov.f32 %f1170, 0f3ED55555;
|
|
mul.rn.f32 %f1171, %f1170, %f1167;
|
|
neg.f32 %f1172, %f1171;
|
|
fma.rn.f32 %f1173, %f1170, %f1167, %f1172;
|
|
fma.rn.f32 %f1174, %f1170, %f1169, %f1173;
|
|
mov.f32 %f1175, 0f00000000;
|
|
fma.rn.f32 %f1176, %f1175, %f1167, %f1174;
|
|
add.rn.f32 %f1177, %f1171, %f1176;
|
|
neg.f32 %f1178, %f1177;
|
|
add.rn.f32 %f1179, %f1171, %f1178;
|
|
add.rn.f32 %f1180, %f1179, %f1176;
|
|
mov.b32 %r392, %f1177;
|
|
setp.eq.s32 %p156, %r392, 1118925336;
|
|
add.s32 %r393, %r392, -1;
|
|
mov.b32 %f1181, %r393;
|
|
add.f32 %f1182, %f1180, 0f37000000;
|
|
selp.f32 %f242, %f1182, %f1180, %p156;
|
|
selp.f32 %f1183, %f1181, %f1177, %p156;
|
|
mov.f32 %f1184, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1185, %f1183, %f1184;
|
|
cvt.rzi.f32.f32 %f1186, %f1185;
|
|
abs.f32 %f1187, %f1186;
|
|
setp.gt.f32 %p157, %f1187, 0f42FC0000;
|
|
mov.b32 %r394, %f1186;
|
|
and.b32 %r395, %r394, -2147483648;
|
|
or.b32 %r396, %r395, 1123811328;
|
|
mov.b32 %f1188, %r396;
|
|
selp.f32 %f1189, %f1188, %f1186, %p157;
|
|
mov.f32 %f1190, 0fBF317218;
|
|
fma.rn.f32 %f1191, %f1189, %f1190, %f1183;
|
|
mov.f32 %f1192, 0f3102E308;
|
|
fma.rn.f32 %f1193, %f1189, %f1192, %f1191;
|
|
mul.f32 %f1194, %f1193, 0f3FB8AA3B;
|
|
add.f32 %f1195, %f1189, 0f4B40007F;
|
|
mov.b32 %r397, %f1195;
|
|
shl.b32 %r398, %r397, 23;
|
|
mov.b32 %f1196, %r398;
|
|
ex2.approx.ftz.f32 %f1197, %f1194;
|
|
mul.f32 %f243, %f1197, %f1196;
|
|
setp.eq.f32 %p158, %f243, 0f7F800000;
|
|
mov.f32 %f1482, 0f7F800000;
|
|
@%p158 bra $L__BB0_129;
|
|
|
|
fma.rn.f32 %f1482, %f243, %f242, %f243;
|
|
|
|
$L__BB0_129:
|
|
setp.lt.f32 %p159, %f227, 0f00000000;
|
|
and.pred %p8, %p159, %p146;
|
|
setp.eq.f32 %p161, %f227, 0f00000000;
|
|
@%p161 bra $L__BB0_133;
|
|
bra.uni $L__BB0_130;
|
|
|
|
$L__BB0_133:
|
|
add.f32 %f1202, %f227, %f227;
|
|
selp.f32 %f1484, %f1202, 0f00000000, %p146;
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_130:
|
|
mov.b32 %r399, %f1482;
|
|
xor.b32 %r400, %r399, -2147483648;
|
|
mov.b32 %f1198, %r400;
|
|
selp.f32 %f1484, %f1198, %f1482, %p8;
|
|
setp.geu.f32 %p162, %f227, 0f00000000;
|
|
@%p162 bra $L__BB0_134;
|
|
|
|
mov.f32 %f1199, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1200, %f1199;
|
|
setp.eq.f32 %p163, %f1200, 0f3ED55555;
|
|
@%p163 bra $L__BB0_134;
|
|
|
|
mov.f32 %f1484, 0f7FFFFFFF;
|
|
|
|
$L__BB0_134:
|
|
add.f32 %f1203, %f241, 0f3ED55555;
|
|
mov.b32 %r401, %f1203;
|
|
setp.lt.s32 %p165, %r401, 2139095040;
|
|
@%p165 bra $L__BB0_139;
|
|
|
|
setp.gtu.f32 %p166, %f241, 0f7F800000;
|
|
@%p166 bra $L__BB0_138;
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_138:
|
|
add.f32 %f1484, %f227, 0f3ED55555;
|
|
bra.uni $L__BB0_139;
|
|
|
|
$L__BB0_136:
|
|
setp.neu.f32 %p167, %f241, 0f7F800000;
|
|
@%p167 bra $L__BB0_139;
|
|
|
|
selp.f32 %f1484, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_139:
|
|
abs.f32 %f252, %f228;
|
|
setp.lt.f32 %p168, %f252, 0f00800000;
|
|
mul.f32 %f1205, %f252, 0f4B800000;
|
|
selp.f32 %f1206, %f1205, %f252, %p168;
|
|
selp.f32 %f1207, 0fC3170000, 0fC2FE0000, %p168;
|
|
mov.b32 %r402, %f1206;
|
|
and.b32 %r403, %r402, 8388607;
|
|
or.b32 %r404, %r403, 1065353216;
|
|
mov.b32 %f1208, %r404;
|
|
shr.u32 %r405, %r402, 23;
|
|
cvt.rn.f32.u32 %f1209, %r405;
|
|
add.f32 %f1210, %f1207, %f1209;
|
|
setp.gt.f32 %p169, %f1208, 0f3FB504F3;
|
|
mul.f32 %f1211, %f1208, 0f3F000000;
|
|
add.f32 %f1212, %f1210, 0f3F800000;
|
|
selp.f32 %f1213, %f1212, %f1210, %p169;
|
|
selp.f32 %f1214, %f1211, %f1208, %p169;
|
|
add.f32 %f1215, %f1214, 0fBF800000;
|
|
add.f32 %f1216, %f1214, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1217, %f1216;
|
|
add.f32 %f1218, %f1215, %f1215;
|
|
mul.f32 %f1219, %f1218, %f1217;
|
|
mul.f32 %f1220, %f1219, %f1219;
|
|
mov.f32 %f1221, 0f3C4CAF63;
|
|
mov.f32 %f1222, 0f3B18F0FE;
|
|
fma.rn.f32 %f1223, %f1222, %f1220, %f1221;
|
|
mov.f32 %f1224, 0f3DAAAABD;
|
|
fma.rn.f32 %f1225, %f1223, %f1220, %f1224;
|
|
mul.rn.f32 %f1226, %f1225, %f1220;
|
|
mul.rn.f32 %f1227, %f1226, %f1219;
|
|
sub.f32 %f1228, %f1215, %f1219;
|
|
add.f32 %f1229, %f1228, %f1228;
|
|
neg.f32 %f1230, %f1219;
|
|
fma.rn.f32 %f1231, %f1230, %f1215, %f1229;
|
|
mul.rn.f32 %f1232, %f1217, %f1231;
|
|
add.f32 %f1233, %f1227, %f1219;
|
|
sub.f32 %f1234, %f1219, %f1233;
|
|
add.f32 %f1235, %f1227, %f1234;
|
|
add.f32 %f1236, %f1232, %f1235;
|
|
add.f32 %f1237, %f1233, %f1236;
|
|
sub.f32 %f1238, %f1233, %f1237;
|
|
add.f32 %f1239, %f1236, %f1238;
|
|
mov.f32 %f1240, 0f3F317200;
|
|
mul.rn.f32 %f1241, %f1213, %f1240;
|
|
mov.f32 %f1242, 0f35BFBE8E;
|
|
mul.rn.f32 %f1243, %f1213, %f1242;
|
|
add.f32 %f1244, %f1241, %f1237;
|
|
sub.f32 %f1245, %f1241, %f1244;
|
|
add.f32 %f1246, %f1237, %f1245;
|
|
add.f32 %f1247, %f1239, %f1246;
|
|
add.f32 %f1248, %f1243, %f1247;
|
|
add.f32 %f1249, %f1244, %f1248;
|
|
sub.f32 %f1250, %f1244, %f1249;
|
|
add.f32 %f1251, %f1248, %f1250;
|
|
mov.f32 %f1252, 0f3ED55555;
|
|
mul.rn.f32 %f1253, %f1252, %f1249;
|
|
neg.f32 %f1254, %f1253;
|
|
fma.rn.f32 %f1255, %f1252, %f1249, %f1254;
|
|
fma.rn.f32 %f1256, %f1252, %f1251, %f1255;
|
|
mov.f32 %f1257, 0f00000000;
|
|
fma.rn.f32 %f1258, %f1257, %f1249, %f1256;
|
|
add.rn.f32 %f1259, %f1253, %f1258;
|
|
neg.f32 %f1260, %f1259;
|
|
add.rn.f32 %f1261, %f1253, %f1260;
|
|
add.rn.f32 %f1262, %f1261, %f1258;
|
|
mov.b32 %r406, %f1259;
|
|
setp.eq.s32 %p170, %r406, 1118925336;
|
|
add.s32 %r407, %r406, -1;
|
|
mov.b32 %f1263, %r407;
|
|
add.f32 %f1264, %f1262, 0f37000000;
|
|
selp.f32 %f253, %f1264, %f1262, %p170;
|
|
selp.f32 %f1265, %f1263, %f1259, %p170;
|
|
mov.f32 %f1266, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1267, %f1265, %f1266;
|
|
cvt.rzi.f32.f32 %f1268, %f1267;
|
|
abs.f32 %f1269, %f1268;
|
|
setp.gt.f32 %p171, %f1269, 0f42FC0000;
|
|
mov.b32 %r408, %f1268;
|
|
and.b32 %r409, %r408, -2147483648;
|
|
or.b32 %r410, %r409, 1123811328;
|
|
mov.b32 %f1270, %r410;
|
|
selp.f32 %f1271, %f1270, %f1268, %p171;
|
|
mov.f32 %f1272, 0fBF317218;
|
|
fma.rn.f32 %f1273, %f1271, %f1272, %f1265;
|
|
mov.f32 %f1274, 0f3102E308;
|
|
fma.rn.f32 %f1275, %f1271, %f1274, %f1273;
|
|
mul.f32 %f1276, %f1275, 0f3FB8AA3B;
|
|
add.f32 %f1277, %f1271, 0f4B40007F;
|
|
mov.b32 %r411, %f1277;
|
|
shl.b32 %r412, %r411, 23;
|
|
mov.b32 %f1278, %r412;
|
|
ex2.approx.ftz.f32 %f1279, %f1276;
|
|
mul.f32 %f254, %f1279, %f1278;
|
|
setp.eq.f32 %p172, %f254, 0f7F800000;
|
|
mov.f32 %f1485, 0f7F800000;
|
|
@%p172 bra $L__BB0_141;
|
|
|
|
fma.rn.f32 %f1485, %f254, %f253, %f254;
|
|
|
|
$L__BB0_141:
|
|
setp.lt.f32 %p173, %f228, 0f00000000;
|
|
and.pred %p9, %p173, %p146;
|
|
setp.eq.f32 %p175, %f228, 0f00000000;
|
|
@%p175 bra $L__BB0_145;
|
|
bra.uni $L__BB0_142;
|
|
|
|
$L__BB0_145:
|
|
add.f32 %f1284, %f228, %f228;
|
|
selp.f32 %f1487, %f1284, 0f00000000, %p146;
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_142:
|
|
mov.b32 %r413, %f1485;
|
|
xor.b32 %r414, %r413, -2147483648;
|
|
mov.b32 %f1280, %r414;
|
|
selp.f32 %f1487, %f1280, %f1485, %p9;
|
|
setp.geu.f32 %p176, %f228, 0f00000000;
|
|
@%p176 bra $L__BB0_146;
|
|
|
|
mov.f32 %f1281, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1282, %f1281;
|
|
setp.eq.f32 %p177, %f1282, 0f3ED55555;
|
|
@%p177 bra $L__BB0_146;
|
|
|
|
mov.f32 %f1487, 0f7FFFFFFF;
|
|
|
|
$L__BB0_146:
|
|
add.f32 %f1285, %f252, 0f3ED55555;
|
|
mov.b32 %r415, %f1285;
|
|
setp.lt.s32 %p179, %r415, 2139095040;
|
|
@%p179 bra $L__BB0_151;
|
|
|
|
setp.gtu.f32 %p180, %f252, 0f7F800000;
|
|
@%p180 bra $L__BB0_150;
|
|
bra.uni $L__BB0_148;
|
|
|
|
$L__BB0_150:
|
|
add.f32 %f1487, %f228, 0f3ED55555;
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_148:
|
|
setp.neu.f32 %p181, %f252, 0f7F800000;
|
|
@%p181 bra $L__BB0_151;
|
|
|
|
selp.f32 %f1487, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_151:
|
|
fma.rn.f32 %f1286, %f1481, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p182, %f226, 0f3F800000;
|
|
mov.f32 %f1287, 0f3F800000;
|
|
selp.f32 %f1288, 0f3F7FFFFF, %f1286, %p182;
|
|
mul.f32 %f1289, %f226, 0f414EB852;
|
|
setp.lt.f32 %p183, %f226, 0f3B4D2E1C;
|
|
selp.f32 %f1290, %f1289, %f1288, %p183;
|
|
fma.rn.f32 %f1291, %f1484, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p184, %f227, 0f3F800000;
|
|
selp.f32 %f1292, 0f3F7FFFFF, %f1291, %p184;
|
|
mul.f32 %f1293, %f227, 0f414EB852;
|
|
setp.lt.f32 %p185, %f227, 0f3B4D2E1C;
|
|
selp.f32 %f1294, %f1293, %f1292, %p185;
|
|
fma.rn.f32 %f1295, %f1487, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p186, %f228, 0f3F800000;
|
|
selp.f32 %f1296, 0f3F7FFFFF, %f1295, %p186;
|
|
mul.f32 %f1297, %f228, 0f414EB852;
|
|
setp.lt.f32 %p187, %f228, 0f3B4D2E1C;
|
|
selp.f32 %f1298, %f1297, %f1296, %p187;
|
|
min.f32 %f1299, %f1290, %f1287;
|
|
mov.f32 %f1300, 0f00000000;
|
|
max.f32 %f1301, %f1300, %f1299;
|
|
mul.f32 %f1302, %f1301, 0f43800000;
|
|
cvt.rzi.u32.f32 %r416, %f1302;
|
|
min.u32 %r417, %r416, 255;
|
|
min.f32 %f1303, %f1294, %f1287;
|
|
max.f32 %f1304, %f1300, %f1303;
|
|
mul.f32 %f1305, %f1304, 0f43800000;
|
|
cvt.rzi.u32.f32 %r418, %f1305;
|
|
min.u32 %r419, %r418, 255;
|
|
min.f32 %f1306, %f1298, %f1287;
|
|
max.f32 %f1307, %f1300, %f1306;
|
|
mul.f32 %f1308, %f1307, 0f43800000;
|
|
cvt.rzi.u32.f32 %r420, %f1308;
|
|
min.u32 %r421, %r420, 255;
|
|
shl.b64 %rd82, %rd23, 2;
|
|
add.s64 %rd83, %rd22, %rd82;
|
|
cvt.u16.u32 %rs47, %r421;
|
|
cvt.u16.u32 %rs48, %r419;
|
|
cvt.u16.u32 %rs49, %r417;
|
|
mov.u16 %rs50, 255;
|
|
st.global.v4.u8 [%rd83], {%rs49, %rs48, %rs47, %rs50};
|
|
|
|
$L__BB0_152:
|
|
and.b32 %r422, %r56, 4;
|
|
setp.eq.s32 %p188, %r422, 0;
|
|
ld.const.u32 %r466, [params+108];
|
|
@%p188 bra $L__BB0_156;
|
|
|
|
setp.eq.s32 %p189, %r466, 0;
|
|
ld.const.u64 %rd84, [params+224];
|
|
cvta.to.global.u64 %rd85, %rd84;
|
|
ld.const.u32 %r423, [params+216];
|
|
mad.lo.s32 %r424, %r423, %r7, %r6;
|
|
mul.wide.u32 %rd86, %r424, 8;
|
|
add.s64 %rd24, %rd85, %rd86;
|
|
@%p189 bra $L__BB0_155;
|
|
|
|
ld.global.v4.u16 {%rs58, %rs59, %rs60, %rs61}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1309, %rs58;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1310, %rs59;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1311, %rs60;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1312, %f186, %f1309;
|
|
add.f32 %f1313, %f187, %f1310;
|
|
add.f32 %f1314, %f189, %f1311;
|
|
mov.f32 %f1315, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1314;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1313;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f1312;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1315;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs54, %rs55, %rs56, %rs57};
|
|
bra.uni $L__BB0_156;
|
|
|
|
$L__BB0_155:
|
|
mov.f32 %f1319, 0f3F800000;
|
|
mov.u32 %r466, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f1319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f189;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f187;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f186;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs62, %rs63, %rs64, %rs65};
|
|
|
|
$L__BB0_156:
|
|
add.f32 %f1320, %f1464, %f1465;
|
|
add.f32 %f1321, %f1463, %f1320;
|
|
mul.f32 %f1322, %f1321, 0f3F13CD3A;
|
|
div.rn.f32 %f1323, %f1466, %f1322;
|
|
setp.eq.f32 %p190, %f1466, 0f00000000;
|
|
selp.f32 %f1324, 0f00000000, %f1323, %p190;
|
|
mul.f32 %f1325, %f1465, %f1324;
|
|
mul.f32 %f1326, %f1464, %f1324;
|
|
mul.f32 %f1327, %f1463, %f1324;
|
|
mul.f32 %f263, %f1325, %f779;
|
|
mul.f32 %f264, %f1325, %f780;
|
|
mul.f32 %f265, %f1325, %f188;
|
|
mul.f32 %f266, %f1326, %f779;
|
|
mul.f32 %f267, %f1326, %f780;
|
|
mul.f32 %f268, %f1326, %f188;
|
|
mul.f32 %f269, %f1327, %f779;
|
|
mul.f32 %f270, %f1327, %f780;
|
|
mul.f32 %f271, %f1327, %f188;
|
|
ld.const.u64 %rd87, [params+256];
|
|
cvta.to.global.u64 %rd88, %rd87;
|
|
ld.const.u32 %r426, [params+248];
|
|
mad.lo.s32 %r427, %r426, %r7, %r6;
|
|
mul.wide.u32 %rd89, %r427, 8;
|
|
add.s64 %rd25, %rd88, %rd89;
|
|
setp.eq.s32 %p191, %r466, 0;
|
|
@%p191 bra $L__BB0_158;
|
|
|
|
ld.global.v4.u16 {%rs73, %rs74, %rs75, %rs76}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1328, %rs73;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1329, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1330, %rs75;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1331, %f263, %f1328;
|
|
add.f32 %f1332, %f264, %f1329;
|
|
add.f32 %f1333, %f265, %f1330;
|
|
mov.f32 %f1334, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1333;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1332;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1331;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1334;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs69, %rs70, %rs71, %rs72};
|
|
bra.uni $L__BB0_159;
|
|
|
|
$L__BB0_158:
|
|
mov.f32 %f1338, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f1338;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f265;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f264;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f263;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs77, %rs78, %rs79, %rs80};
|
|
|
|
$L__BB0_159:
|
|
ld.const.u64 %rd90, [params+272];
|
|
cvta.to.global.u64 %rd91, %rd90;
|
|
ld.const.u32 %r428, [params+264];
|
|
mad.lo.s32 %r429, %r428, %r7, %r6;
|
|
mul.wide.u32 %rd92, %r429, 8;
|
|
add.s64 %rd26, %rd91, %rd92;
|
|
@%p191 bra $L__BB0_161;
|
|
|
|
ld.global.v4.u16 {%rs88, %rs89, %rs90, %rs91}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1339, %rs88;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1340, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1341, %rs90;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1342, %f266, %f1339;
|
|
add.f32 %f1343, %f267, %f1340;
|
|
add.f32 %f1344, %f268, %f1341;
|
|
mov.f32 %f1345, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1344;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1343;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1342;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1345;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs84, %rs85, %rs86, %rs87};
|
|
bra.uni $L__BB0_162;
|
|
|
|
$L__BB0_161:
|
|
mov.f32 %f1349, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f1349;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f268;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f267;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f266;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs92, %rs93, %rs94, %rs95};
|
|
|
|
$L__BB0_162:
|
|
ld.const.u64 %rd93, [params+288];
|
|
cvta.to.global.u64 %rd94, %rd93;
|
|
ld.const.u32 %r430, [params+280];
|
|
mad.lo.s32 %r431, %r430, %r7, %r6;
|
|
mul.wide.u32 %rd95, %r431, 8;
|
|
add.s64 %rd27, %rd94, %rd95;
|
|
@%p191 bra $L__BB0_164;
|
|
|
|
ld.global.v4.u16 {%rs103, %rs104, %rs105, %rs106}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1350, %rs103;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1351, %rs104;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1352, %rs105;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1353, %f269, %f1350;
|
|
add.f32 %f1354, %f270, %f1351;
|
|
add.f32 %f1355, %f271, %f1352;
|
|
mov.f32 %f1356, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs101, %f1355;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1354;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1353;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1356;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs99, %rs100, %rs101, %rs102};
|
|
bra.uni $L__BB0_182;
|
|
|
|
$L__BB0_164:
|
|
mov.f32 %f1360, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f1360;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs109, %f271;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f270;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f269;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs107, %rs108, %rs109, %rs110};
|
|
|
|
$L__BB0_182:
|
|
ret;
|
|
|
|
}
|
|
|