253 lines
6.8 KiB
Plaintext
253 lines
6.8 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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.const .align 16 .b8 params[1184];
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.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
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.param .b32 __direct_callable__oxMain_param_0,
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.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
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)
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{
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.reg .pred %p<7>;
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.reg .b16 %rs<57>;
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.reg .f32 %f<140>;
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.reg .b32 %r<41>;
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.reg .b64 %rd<51>;
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ld.param.u32 %r6, [__direct_callable__oxMain_param_0];
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ld.param.f32 %f41, [__direct_callable__oxMain_param_1+4];
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ld.param.f32 %f40, [__direct_callable__oxMain_param_1];
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// begin inline asm
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call (%r7), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r8), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd6, [params+72];
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cvta.to.global.u64 %rd7, %rd6;
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mul.wide.s32 %rd8, %r6, 4;
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add.s64 %rd9, %rd7, %rd8;
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ld.global.u32 %r3, [%rd9];
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setp.eq.s32 %p1, %r3, 0;
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@%p1 bra $L__BB0_2;
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ld.const.u64 %rd10, [params+480];
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cvta.to.global.u64 %rd11, %rd10;
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ld.const.u32 %r10, [params+472];
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mad.lo.s32 %r11, %r10, %r8, %r7;
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cvt.u64.u32 %rd12, %r11;
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add.s64 %rd13, %rd11, %rd12;
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ld.global.u8 %r12, [%rd13];
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mov.u32 %r13, 1;
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shl.b32 %r14, %r13, %r12;
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and.b32 %r15, %r14, %r3;
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setp.eq.s32 %p2, %r15, 0;
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mov.f32 %f134, 0f00000000;
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mov.f32 %f135, %f134;
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mov.f32 %f136, %f134;
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mov.f32 %f137, %f134;
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mov.f32 %f138, %f134;
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mov.f32 %f139, %f134;
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@%p2 bra $L__BB0_11;
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$L__BB0_2:
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ld.const.u64 %rd14, [params+24];
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cvta.to.global.u64 %rd15, %rd14;
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mul.wide.u32 %rd16, %r6, 12;
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add.s64 %rd17, %rd15, %rd16;
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ld.global.s32 %rd1, [%rd17];
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ld.global.s32 %rd2, [%rd17+4];
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ld.global.s32 %rd3, [%rd17+8];
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ld.const.u32 %r4, [params+32];
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setp.gt.u32 %p3, %r4, %r6;
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@%p3 bra $L__BB0_6;
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bra.uni $L__BB0_3;
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$L__BB0_6:
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mov.f32 %f139, 0f3F800000;
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sub.f32 %f92, %f139, %f40;
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sub.f32 %f130, %f92, %f41;
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bra.uni $L__BB0_7;
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$L__BB0_3:
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sub.s32 %r16, %r6, %r4;
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ld.const.u64 %rd18, [params+48];
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cvta.to.global.u64 %rd19, %rd18;
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mul.wide.u32 %rd20, %r16, 4;
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add.s64 %rd21, %rd19, %rd20;
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ld.const.u64 %rd22, [params+40];
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cvta.to.global.u64 %rd23, %rd22;
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shl.b64 %rd24, %rd1, 3;
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add.s64 %rd25, %rd23, %rd24;
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ld.global.v2.f32 {%f48, %f49}, [%rd25];
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shl.b64 %rd26, %rd2, 3;
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add.s64 %rd27, %rd23, %rd26;
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ld.global.v2.f32 {%f52, %f53}, [%rd27];
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shl.b64 %rd28, %rd3, 3;
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add.s64 %rd29, %rd23, %rd28;
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ld.global.v2.f32 {%f56, %f57}, [%rd29];
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mov.f32 %f60, 0f3F800000;
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sub.f32 %f61, %f60, %f40;
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sub.f32 %f130, %f61, %f41;
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mul.f32 %f62, %f40, %f52;
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mul.f32 %f63, %f40, %f53;
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fma.rn.f32 %f64, %f130, %f48, %f62;
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fma.rn.f32 %f65, %f130, %f49, %f63;
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fma.rn.f32 %f4, %f41, %f56, %f64;
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fma.rn.f32 %f5, %f41, %f57, %f65;
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ld.global.u32 %r5, [%rd21];
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and.b32 %r17, %r5, -16384;
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setp.eq.s32 %p4, %r17, 16384;
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@%p4 bra $L__BB0_5;
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bra.uni $L__BB0_4;
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$L__BB0_5:
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add.s32 %r29, %r5, -16384;
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ld.const.u64 %rd38, [params+64];
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cvta.to.global.u64 %rd39, %rd38;
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mul.wide.u32 %rd40, %r29, 8;
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add.s64 %rd41, %rd39, %rd40;
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ld.global.u64 %rd42, [%rd41];
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tex.2d.v4.f32.f32 {%f76, %f77, %f78, %f79}, [%rd42, {%f4, %f5}];
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cvt.sat.f32.f32 %f80, %f76;
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mul.f32 %f81, %f80, 0f437F0000;
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cvt.rzi.s32.f32 %r30, %f81;
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cvt.sat.f32.f32 %f82, %f77;
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mul.f32 %f83, %f82, 0f437F0000;
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cvt.rzi.s32.f32 %r31, %f83;
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cvt.sat.f32.f32 %f84, %f78;
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mul.f32 %f85, %f84, 0f437F0000;
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cvt.rzi.s32.f32 %r32, %f85;
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shl.b32 %r33, %r31, 8;
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or.b32 %r34, %r33, %r30;
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shl.b32 %r35, %r32, 16;
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or.b32 %r36, %r34, %r35;
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not.b32 %r37, %r36;
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cvt.rn.f32.s32 %f139, %r37;
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bra.uni $L__BB0_11;
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$L__BB0_4:
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abs.f32 %f66, %f4;
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cvt.rmi.f32.f32 %f67, %f66;
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sub.f32 %f68, %f66, %f67;
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abs.f32 %f69, %f5;
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cvt.rmi.f32.f32 %f70, %f69;
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sub.f32 %f71, %f69, %f70;
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ld.const.u64 %rd30, [params+56];
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cvta.to.global.u64 %rd31, %rd30;
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shl.b32 %r18, %r5, 4;
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cvt.u64.u32 %rd32, %r18;
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and.b64 %rd33, %rd32, 1048560;
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add.s64 %rd34, %rd31, %rd33;
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ld.global.v2.u32 {%r19, %r20}, [%rd34];
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cvt.rn.f32.u32 %f72, %r19;
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mul.f32 %f73, %f68, %f72;
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cvt.rzi.u32.f32 %r23, %f73;
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cvt.rn.f32.u32 %f74, %r20;
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mul.f32 %f75, %f71, %f74;
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cvt.rzi.u32.f32 %r24, %f75;
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mad.lo.s32 %r25, %r19, %r24, %r23;
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cvt.u64.u32 %rd35, %r25;
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ld.global.u64 %rd36, [%rd34+8];
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add.s64 %rd37, %rd36, %rd35;
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ld.u8 %r26, [%rd37];
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shr.u32 %r27, %r5, 16;
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and.b32 %r28, %r27, %r26;
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setp.eq.s32 %p5, %r28, 0;
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selp.f32 %f139, 0f00000000, 0f3F800000, %p5;
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$L__BB0_7:
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cvt.u32.u64 %r38, %rd1;
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cvt.u32.u64 %r39, %rd2;
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cvt.u32.u64 %r40, %rd3;
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ld.const.u64 %rd43, [params+16];
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cvta.to.global.u64 %rd44, %rd43;
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mul.wide.s32 %rd45, %r38, 32;
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add.s64 %rd46, %rd44, %rd45;
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mul.wide.s32 %rd47, %r39, 32;
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add.s64 %rd48, %rd44, %rd47;
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add.s64 %rd4, %rd48, 12;
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mul.wide.s32 %rd49, %r40, 32;
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add.s64 %rd50, %rd44, %rd49;
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add.s64 %rd5, %rd50, 12;
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ld.global.f32 %f93, [%rd46+12];
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ld.global.f32 %f94, [%rd46+16];
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ld.global.f32 %f95, [%rd46+20];
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ld.global.f32 %f96, [%rd48+12];
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mul.f32 %f97, %f40, %f96;
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ld.global.f32 %f98, [%rd48+16];
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mul.f32 %f99, %f40, %f98;
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ld.global.f32 %f100, [%rd48+20];
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mul.f32 %f101, %f40, %f100;
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fma.rn.f32 %f102, %f130, %f93, %f97;
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fma.rn.f32 %f103, %f130, %f94, %f99;
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fma.rn.f32 %f104, %f130, %f95, %f101;
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ld.global.f32 %f105, [%rd50+12];
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ld.global.f32 %f106, [%rd50+16];
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ld.global.f32 %f107, [%rd50+20];
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fma.rn.f32 %f108, %f41, %f105, %f102;
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fma.rn.f32 %f109, %f41, %f106, %f103;
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fma.rn.f32 %f110, %f41, %f107, %f104;
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mul.f32 %f111, %f109, %f109;
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fma.rn.f32 %f112, %f108, %f108, %f111;
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fma.rn.f32 %f113, %f110, %f110, %f112;
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sqrt.rn.f32 %f114, %f113;
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rcp.rn.f32 %f115, %f114;
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mul.f32 %f134, %f108, %f115;
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mul.f32 %f135, %f109, %f115;
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mul.f32 %f136, %f110, %f115;
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ld.global.v2.f32 {%f137, %f117}, [%rd46+24];
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setp.lt.f32 %p6, %f117, 0f00000000;
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@%p6 bra $L__BB0_9;
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bra.uni $L__BB0_8;
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$L__BB0_9:
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add.f32 %f138, %f117, 0f3F800000;
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bra.uni $L__BB0_11;
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$L__BB0_8:
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ld.global.v2.f32 {%f118, %f119}, [%rd4+12];
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ld.global.v2.f32 {%f120, %f121}, [%rd5+12];
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mul.f32 %f123, %f40, %f118;
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mul.f32 %f125, %f40, %f119;
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fma.rn.f32 %f126, %f130, %f137, %f123;
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fma.rn.f32 %f127, %f130, %f117, %f125;
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fma.rn.f32 %f137, %f41, %f120, %f126;
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fma.rn.f32 %f138, %f41, %f121, %f127;
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$L__BB0_11:
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st.param.f32 [func_retval0+0], %f134;
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st.param.f32 [func_retval0+4], %f135;
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st.param.f32 [func_retval0+8], %f136;
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st.param.v4.b8 [func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
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st.param.f32 [func_retval0+16], %f137;
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st.param.f32 [func_retval0+20], %f138;
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st.param.f32 [func_retval0+24], %f139;
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st.param.v4.b8 [func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
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ret;
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}
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// .globl oxMain
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.visible .entry oxMain()
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{
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.reg .b64 %rd<2>;
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mov.u64 %rd1, __direct_callable__oxMain;
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// begin inline asm
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// end inline asm
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ret;
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}
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