2196 lines
58 KiB
Plaintext
2196 lines
58 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<154>;
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.reg .b16 %rs<172>;
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.reg .f32 %f<1054>;
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.reg .b32 %r<346>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<109>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r56), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r57), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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shl.b32 %r4, %r3, 1;
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ld.const.u64 %rd29, [params+400];
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cvta.to.global.u64 %rd30, %rd29;
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ld.const.u32 %r62, [params+392];
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mad.lo.s32 %r63, %r62, %r57, %r56;
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mul.wide.u32 %rd31, %r63, 4;
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add.s64 %rd2, %rd30, %rd31;
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ld.global.v2.u8 {%rs7, %rs171}, [%rd2];
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or.b16 %rs9, %rs7, %rs171;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs170, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs170, [%rd2+2];
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setp.eq.s16 %p8, %rs170, 0;
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mov.f32 %f1007, 0f00000000;
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mov.u16 %rs171, 0;
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mov.f32 %f1008, %f1007;
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mov.f32 %f1009, %f1007;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f171, %rs7;
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div.rn.f32 %f172, %f171, 0f437F0000;
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fma.rn.f32 %f173, %f172, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs171, 255;
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cvt.rn.f32.u16 %f174, %rs13;
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div.rn.f32 %f175, %f174, 0f437F0000;
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fma.rn.f32 %f176, %f175, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f177, %rs170;
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div.rn.f32 %f178, %f177, 0f437F0000;
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fma.rn.f32 %f179, %f178, 0f40000000, 0fBF800000;
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mul.f32 %f180, %f176, %f176;
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fma.rn.f32 %f181, %f173, %f173, %f180;
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fma.rn.f32 %f182, %f179, %f179, %f181;
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sqrt.rn.f32 %f183, %f182;
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rcp.rn.f32 %f184, %f183;
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mul.f32 %f1009, %f184, %f179;
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mul.f32 %f1008, %f184, %f176;
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mul.f32 %f1007, %f173, %f184;
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$L__BB0_4:
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ld.const.v2.u32 {%r64, %r65}, [params];
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add.s32 %r5, %r64, %r56;
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add.s32 %r6, %r65, %r57;
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setp.eq.f32 %p9, %f1007, 0f00000000;
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setp.eq.f32 %p10, %f1008, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1009, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_126;
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bra.uni $L__BB0_5;
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$L__BB0_126:
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ld.const.u32 %r53, [params+104];
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and.b32 %r315, %r53, 1;
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setp.eq.b32 %p144, %r315, 1;
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mov.pred %p145, 0;
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xor.pred %p146, %p144, %p145;
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not.pred %p147, %p146;
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@%p147 bra $L__BB0_128;
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ld.const.u64 %rd82, [params+144];
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cvta.to.global.u64 %rd83, %rd82;
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ld.const.u32 %r316, [params+136];
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mad.lo.s32 %r317, %r316, %r6, %r5;
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mul.wide.u32 %rd84, %r317, 4;
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add.s64 %rd85, %rd83, %rd84;
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mov.u16 %rs94, 0;
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st.global.v4.u8 [%rd85], {%rs94, %rs94, %rs94, %rs94};
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$L__BB0_128:
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and.b32 %r318, %r53, 4;
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setp.eq.s32 %p148, %r318, 0;
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ld.const.u32 %r345, [params+108];
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@%p148 bra $L__BB0_132;
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setp.eq.s32 %p149, %r345, 0;
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ld.const.u64 %rd86, [params+224];
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cvta.to.global.u64 %rd87, %rd86;
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ld.const.u32 %r319, [params+216];
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mad.lo.s32 %r320, %r319, %r6, %r5;
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mul.wide.u32 %rd88, %r320, 8;
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add.s64 %rd23, %rd87, %rd88;
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@%p149 bra $L__BB0_131;
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ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd23];
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// begin inline asm
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{ cvt.f32.f16 %f904, %rs101;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f905, %rs102;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f906, %rs103;}
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// end inline asm
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add.f32 %f907, %f904, 0f00000000;
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add.f32 %f908, %f905, 0f00000000;
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add.f32 %f909, %f906, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs100, %f909;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs99, %f908;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs98, %f907;}
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// end inline asm
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mov.u16 %rs105, 0;
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st.global.v4.u16 [%rd23], {%rs98, %rs99, %rs100, %rs105};
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bra.uni $L__BB0_132;
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$L__BB0_5:
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ld.const.u64 %rd32, [params+432];
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cvta.to.global.u64 %rd33, %rd32;
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ld.const.u32 %r68, [params+424];
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mad.lo.s32 %r69, %r68, %r57, %r56;
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mul.wide.u32 %rd34, %r69, 12;
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add.s64 %rd35, %rd33, %rd34;
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ld.global.f32 %f190, [%rd35];
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mul.f32 %f191, %f190, 0f3456BF95;
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ld.global.f32 %f192, [%rd35+4];
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mul.f32 %f193, %f192, 0f3456BF95;
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ld.global.f32 %f194, [%rd35+8];
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mul.f32 %f195, %f194, 0f3456BF95;
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abs.f32 %f196, %f1007;
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div.rn.f32 %f197, %f191, %f196;
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abs.f32 %f198, %f1008;
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div.rn.f32 %f199, %f193, %f198;
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abs.f32 %f200, %f1009;
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div.rn.f32 %f201, %f195, %f200;
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abs.f32 %f202, %f197;
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abs.f32 %f203, %f199;
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abs.f32 %f204, %f201;
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mov.f32 %f205, 0f38D1B717;
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max.f32 %f206, %f202, %f205;
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max.f32 %f207, %f203, %f205;
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max.f32 %f208, %f204, %f205;
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fma.rn.f32 %f10, %f1007, %f206, %f190;
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fma.rn.f32 %f11, %f1008, %f207, %f192;
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fma.rn.f32 %f12, %f1009, %f208, %f194;
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setp.gt.f32 %p14, %f196, %f200;
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neg.f32 %f209, %f1008;
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selp.f32 %f210, %f209, 0f00000000, %p14;
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mov.f32 %f1026, 0f00000000;
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neg.f32 %f211, %f1009;
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selp.f32 %f212, %f1007, %f211, %p14;
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selp.f32 %f213, 0f00000000, %f1008, %p14;
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mul.f32 %f214, %f212, %f212;
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fma.rn.f32 %f215, %f210, %f210, %f214;
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fma.rn.f32 %f216, %f213, %f213, %f215;
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sqrt.rn.f32 %f217, %f216;
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rcp.rn.f32 %f218, %f217;
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mul.f32 %f13, %f210, %f218;
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mul.f32 %f14, %f212, %f218;
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mul.f32 %f15, %f213, %f218;
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ld.const.u64 %rd36, [params+128];
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cvta.to.global.u64 %rd37, %rd36;
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ld.const.u32 %r70, [params+120];
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mad.lo.s32 %r71, %r70, %r57, %r56;
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mul.wide.u32 %rd38, %r71, 4;
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add.s64 %rd3, %rd37, %rd38;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1027, %f1026;
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mov.f32 %f1028, %f1026;
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mov.f32 %f1029, %f1026;
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mov.f32 %f1030, %f1026;
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@%p15 bra $L__BB0_36;
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ld.const.u32 %r7, [params+588];
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cvt.rn.f32.s32 %f224, %r4;
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rcp.rn.f32 %f16, %f224;
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ld.global.u32 %r336, [%rd3];
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mul.f32 %f17, %f10, 0f3456BF95;
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mul.f32 %f18, %f11, 0f3456BF95;
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mul.f32 %f19, %f12, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f225, %f1007, %f14;
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mul.f32 %f226, %f1008, %f13;
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sub.f32 %f20, %f226, %f225;
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mul.f32 %f227, %f1009, %f13;
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mul.f32 %f228, %f1007, %f15;
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sub.f32 %f21, %f228, %f227;
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mul.f32 %f229, %f1008, %f15;
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mul.f32 %f230, %f1009, %f14;
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sub.f32 %f22, %f230, %f229;
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mov.u32 %r72, 0;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd39, __cudart_i2opi_f;
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abs.f32 %f295, %f17;
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abs.f32 %f296, %f18;
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max.f32 %f297, %f295, %f296;
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abs.f32 %f298, %f19;
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max.f32 %f299, %f297, %f298;
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mov.u32 %r333, %r72;
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$L__BB0_7:
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mov.u32 %r335, %r72;
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$L__BB0_8:
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cvt.rn.f32.s32 %f978, %r333;
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mad.lo.s32 %r74, %r336, 1664525, 1013904223;
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and.b32 %r75, %r74, 16777215;
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cvt.rn.f32.u32 %f231, %r75;
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fma.rn.f32 %f232, %f231, 0f33800000, %f978;
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mul.f32 %f233, %f16, %f232;
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mad.lo.s32 %r336, %r74, 1664525, 1013904223;
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and.b32 %r76, %r336, 16777215;
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cvt.rn.f32.u32 %f234, %r76;
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cvt.rn.f32.s32 %f235, %r335;
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fma.rn.f32 %f236, %f234, 0f33800000, %f235;
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mul.f32 %f237, %f16, %f236;
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fma.rn.f32 %f238, %f16, %f232, %f233;
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mov.f32 %f239, 0f3F800000;
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sub.f32 %f34, %f239, %f238;
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mul.f32 %f240, %f34, %f34;
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sub.f32 %f241, %f239, %f240;
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mov.f32 %f242, 0f00000000;
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max.f32 %f243, %f242, %f241;
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sqrt.rn.f32 %f35, %f243;
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mul.f32 %f36, %f237, 0f40C90FDB;
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mul.f32 %f244, %f36, 0f3F22F983;
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cvt.rni.s32.f32 %r343, %f244;
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cvt.rn.f32.s32 %f245, %r343;
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mov.f32 %f246, 0fBFC90FDA;
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fma.rn.f32 %f247, %f245, %f246, %f36;
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mov.f32 %f248, 0fB3A22168;
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fma.rn.f32 %f249, %f245, %f248, %f247;
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mov.f32 %f250, 0fA7C234C5;
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fma.rn.f32 %f1023, %f245, %f250, %f249;
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abs.f32 %f38, %f36;
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setp.ltu.f32 %p16, %f38, 0f47CE4780;
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mov.u32 %r340, %r343;
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mov.f32 %f1020, %f1023;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f38, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f253, 0f00000000;
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mul.rn.f32 %f1020, %f36, %f253;
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mov.u32 %r340, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r15, %f36;
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bfe.u32 %r78, %r15, 23, 8;
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add.s32 %r16, %r78, -128;
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shl.b32 %r79, %r15, 8;
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or.b32 %r17, %r79, -2147483648;
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shr.u32 %r18, %r16, 5;
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mov.u64 %rd106, 0;
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mov.u32 %r337, 0;
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mov.u64 %rd104, %rd1;
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mov.u64 %rd105, %rd39;
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$L__BB0_11:
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.pragma "nounroll";
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ld.global.nc.u32 %r80, [%rd105];
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mad.wide.u32 %rd41, %r80, %r17, %rd106;
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shr.u64 %rd106, %rd41, 32;
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st.local.u32 [%rd104], %rd41;
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add.s64 %rd105, %rd105, 4;
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add.s64 %rd104, %rd104, 4;
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add.s32 %r337, %r337, 1;
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setp.ne.s32 %p18, %r337, 6;
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@%p18 bra $L__BB0_11;
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st.local.u32 [%rd5], %rd106;
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mov.u32 %r81, 4;
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sub.s32 %r21, %r81, %r18;
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mov.u32 %r82, 6;
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sub.s32 %r83, %r82, %r18;
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mul.wide.s32 %rd42, %r83, 4;
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add.s64 %rd43, %rd1, %rd42;
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ld.local.u32 %r338, [%rd43];
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ld.local.u32 %r339, [%rd43+-4];
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and.b32 %r24, %r16, 31;
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setp.eq.s32 %p19, %r24, 0;
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@%p19 bra $L__BB0_14;
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mov.u32 %r84, 32;
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sub.s32 %r85, %r84, %r24;
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shr.u32 %r86, %r339, %r85;
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shl.b32 %r87, %r338, %r24;
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add.s32 %r338, %r86, %r87;
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mul.wide.s32 %rd44, %r21, 4;
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add.s64 %rd45, %rd1, %rd44;
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ld.local.u32 %r88, [%rd45];
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shr.u32 %r89, %r88, %r85;
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shl.b32 %r90, %r339, %r24;
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add.s32 %r339, %r89, %r90;
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$L__BB0_14:
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and.b32 %r91, %r15, -2147483648;
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shr.u32 %r92, %r339, 30;
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shl.b32 %r93, %r338, 2;
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or.b32 %r94, %r92, %r93;
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shr.u32 %r95, %r94, 31;
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shr.u32 %r96, %r338, 30;
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add.s32 %r97, %r95, %r96;
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neg.s32 %r98, %r97;
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setp.eq.s32 %p20, %r91, 0;
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selp.b32 %r340, %r97, %r98, %p20;
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setp.ne.s32 %p21, %r95, 0;
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xor.b32 %r99, %r91, -2147483648;
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selp.b32 %r100, %r99, %r91, %p21;
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selp.b32 %r101, -1, 0, %p21;
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xor.b32 %r102, %r94, %r101;
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shl.b32 %r103, %r339, 2;
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xor.b32 %r104, %r103, %r101;
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cvt.u64.u32 %rd46, %r102;
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cvt.u64.u32 %rd47, %r104;
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bfi.b64 %rd48, %rd46, %rd47, 32, 32;
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cvt.rn.f64.s64 %fd1, %rd48;
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mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
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cvt.rn.f32.f64 %f251, %fd2;
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setp.eq.s32 %p22, %r100, 0;
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neg.f32 %f252, %f251;
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selp.f32 %f1020, %f251, %f252, %p22;
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$L__BB0_16:
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add.s32 %r31, %r340, 1;
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and.b32 %r32, %r31, 1;
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setp.eq.s32 %p23, %r32, 0;
|
|
selp.f32 %f42, %f1020, 0f3F800000, %p23;
|
|
mul.rn.f32 %f43, %f1020, %f1020;
|
|
mov.f32 %f1021, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f255, 0fBAB607ED;
|
|
mov.f32 %f256, 0f37CBAC00;
|
|
fma.rn.f32 %f1021, %f256, %f43, %f255;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f257, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f258, %f1021, %f43, %f257;
|
|
selp.f32 %f259, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f260, %f258, %f43, %f259;
|
|
mov.f32 %f261, 0f00000000;
|
|
fma.rn.f32 %f262, %f43, %f42, %f261;
|
|
fma.rn.f32 %f1022, %f260, %f262, %f42;
|
|
and.b32 %r106, %r31, 2;
|
|
setp.eq.s32 %p25, %r106, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f264, 0fBF800000;
|
|
fma.rn.f32 %f1022, %f1022, %f264, %f261;
|
|
|
|
$L__BB0_20:
|
|
@%p16 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f38, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f267, 0f00000000;
|
|
mul.rn.f32 %f1023, %f36, %f267;
|
|
mov.u32 %r343, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r33, %f36;
|
|
bfe.u32 %r107, %r33, 23, 8;
|
|
add.s32 %r34, %r107, -128;
|
|
shl.b32 %r108, %r33, 8;
|
|
or.b32 %r35, %r108, -2147483648;
|
|
shr.u32 %r36, %r34, 5;
|
|
mov.u64 %rd107, 0;
|
|
mov.u64 %rd108, %rd107;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd51, %rd107, 2;
|
|
mov.u64 %rd52, __cudart_i2opi_f;
|
|
add.s64 %rd53, %rd52, %rd51;
|
|
ld.global.nc.u32 %r109, [%rd53];
|
|
mad.wide.u32 %rd54, %r109, %r35, %rd108;
|
|
shr.u64 %rd108, %rd54, 32;
|
|
add.s64 %rd55, %rd1, %rd51;
|
|
st.local.u32 [%rd55], %rd54;
|
|
cvt.u32.u64 %r110, %rd107;
|
|
add.s32 %r111, %r110, 1;
|
|
cvt.s64.s32 %rd107, %r111;
|
|
setp.ne.s32 %p28, %r111, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd108;
|
|
mov.u32 %r112, 4;
|
|
sub.s32 %r37, %r112, %r36;
|
|
mov.u32 %r113, 6;
|
|
sub.s32 %r114, %r113, %r36;
|
|
mul.wide.s32 %rd56, %r114, 4;
|
|
add.s64 %rd57, %rd1, %rd56;
|
|
ld.local.u32 %r341, [%rd57];
|
|
ld.local.u32 %r342, [%rd57+-4];
|
|
and.b32 %r40, %r34, 31;
|
|
setp.eq.s32 %p29, %r40, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r115, 32;
|
|
sub.s32 %r116, %r115, %r40;
|
|
shr.u32 %r117, %r342, %r116;
|
|
shl.b32 %r118, %r341, %r40;
|
|
add.s32 %r341, %r117, %r118;
|
|
mul.wide.s32 %rd58, %r37, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r119, [%rd59];
|
|
shr.u32 %r120, %r119, %r116;
|
|
shl.b32 %r121, %r342, %r40;
|
|
add.s32 %r342, %r120, %r121;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r122, %r33, -2147483648;
|
|
shr.u32 %r123, %r342, 30;
|
|
shl.b32 %r124, %r341, 2;
|
|
or.b32 %r125, %r123, %r124;
|
|
shr.u32 %r126, %r125, 31;
|
|
shr.u32 %r127, %r341, 30;
|
|
add.s32 %r128, %r126, %r127;
|
|
neg.s32 %r129, %r128;
|
|
setp.eq.s32 %p30, %r122, 0;
|
|
selp.b32 %r343, %r128, %r129, %p30;
|
|
setp.ne.s32 %p31, %r126, 0;
|
|
xor.b32 %r130, %r122, -2147483648;
|
|
selp.b32 %r131, %r130, %r122, %p31;
|
|
selp.b32 %r132, -1, 0, %p31;
|
|
xor.b32 %r133, %r125, %r132;
|
|
shl.b32 %r134, %r342, 2;
|
|
xor.b32 %r135, %r134, %r132;
|
|
cvt.u64.u32 %rd60, %r133;
|
|
cvt.u64.u32 %rd61, %r135;
|
|
bfi.b64 %rd62, %rd60, %rd61, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd62;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f265, %fd4;
|
|
setp.eq.s32 %p32, %r131, 0;
|
|
neg.f32 %f266, %f265;
|
|
selp.f32 %f1023, %f265, %f266, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f52, %f35, %f1022;
|
|
and.b32 %r47, %r343, 1;
|
|
setp.eq.s32 %p33, %r47, 0;
|
|
selp.f32 %f53, %f1023, 0f3F800000, %p33;
|
|
mul.rn.f32 %f54, %f1023, %f1023;
|
|
mov.f32 %f1024, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f269, 0fBAB607ED;
|
|
mov.f32 %f270, 0f37CBAC00;
|
|
fma.rn.f32 %f1024, %f270, %f54, %f269;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f271, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f272, %f1024, %f54, %f271;
|
|
selp.f32 %f273, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f274, %f272, %f54, %f273;
|
|
mov.f32 %f275, 0f00000000;
|
|
fma.rn.f32 %f276, %f54, %f53, %f275;
|
|
fma.rn.f32 %f1025, %f274, %f276, %f53;
|
|
and.b32 %r137, %r343, 2;
|
|
setp.eq.s32 %p35, %r137, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f278, 0fBF800000;
|
|
fma.rn.f32 %f1025, %f1025, %f278, %f275;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f279, %f35, %f1025;
|
|
mul.f32 %f280, %f13, %f279;
|
|
mul.f32 %f281, %f14, %f279;
|
|
mul.f32 %f282, %f15, %f279;
|
|
fma.rn.f32 %f283, %f22, %f52, %f280;
|
|
fma.rn.f32 %f284, %f21, %f52, %f281;
|
|
fma.rn.f32 %f285, %f20, %f52, %f282;
|
|
fma.rn.f32 %f60, %f1007, %f34, %f283;
|
|
fma.rn.f32 %f61, %f1008, %f34, %f284;
|
|
fma.rn.f32 %f62, %f1009, %f34, %f285;
|
|
setp.leu.f32 %p36, %f61, 0f00000000;
|
|
setp.ne.s32 %p37, %r7, 0;
|
|
and.pred %p38, %p37, %p36;
|
|
@%p38 bra $L__BB0_34;
|
|
|
|
mov.f32 %f300, 0f38D1B717;
|
|
max.f32 %f292, %f299, %f300;
|
|
mov.f32 %f293, 0f6C4ECB8F;
|
|
mov.f32 %f294, 0f00000000;
|
|
mov.u32 %r174, 2;
|
|
mov.u32 %r176, 1;
|
|
mov.u32 %r177, 1065353216;
|
|
mov.u32 %r208, 0;
|
|
// begin inline asm
|
|
call(%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169),_optix_trace_typed_32,(%r208,%rd4,%f10,%f11,%f12,%f60,%f61,%f62,%f292,%f293,%f294,%r176,%r208,%r176,%r174,%r176,%r176,%r177,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208);
|
|
// end inline asm
|
|
mov.b32 %f301, %r138;
|
|
mul.f32 %f302, %f1008, %f61;
|
|
fma.rn.f32 %f303, %f1007, %f60, %f302;
|
|
fma.rn.f32 %f304, %f1009, %f62, %f303;
|
|
fma.rn.f32 %f1028, %f60, %f301, %f1028;
|
|
fma.rn.f32 %f1029, %f61, %f301, %f1029;
|
|
fma.rn.f32 %f1030, %f62, %f301, %f1030;
|
|
add.f32 %f1026, %f1026, %f301;
|
|
cvt.sat.f32.f32 %f305, %f304;
|
|
fma.rn.f32 %f1027, %f305, %f301, %f1027;
|
|
|
|
$L__BB0_34:
|
|
add.s32 %r335, %r335, 1;
|
|
setp.lt.s32 %p39, %r335, %r4;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r333, %r333, 1;
|
|
setp.lt.s32 %p40, %r333, %r4;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_36:
|
|
mul.lo.s32 %r209, %r4, %r4;
|
|
cvt.rn.f32.s32 %f306, %r209;
|
|
div.rn.f32 %f307, %f1027, %f306;
|
|
div.rn.f32 %f78, %f1026, %f306;
|
|
div.rn.f32 %f79, %f1028, %f306;
|
|
div.rn.f32 %f80, %f1029, %f306;
|
|
div.rn.f32 %f81, %f1030, %f306;
|
|
add.f32 %f308, %f307, %f307;
|
|
ld.const.v4.f32 {%f309, %f310, %f311, %f312}, [params+576];
|
|
mul.f32 %f85, %f308, %f309;
|
|
mul.f32 %f86, %f308, %f310;
|
|
mul.f32 %f87, %f308, %f311;
|
|
ld.const.u32 %r50, [params+104];
|
|
and.b32 %r210, %r50, 1;
|
|
setp.eq.b32 %p41, %r210, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_110;
|
|
|
|
mov.f32 %f317, 0f3EE66666;
|
|
abs.f32 %f89, %f85;
|
|
setp.lt.f32 %p45, %f89, 0f00800000;
|
|
mul.f32 %f319, %f89, 0f4B800000;
|
|
selp.f32 %f320, %f319, %f89, %p45;
|
|
selp.f32 %f321, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r211, %f320;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f322, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f323, %r214;
|
|
add.f32 %f324, %f321, %f323;
|
|
setp.gt.f32 %p46, %f322, 0f3FB504F3;
|
|
mul.f32 %f325, %f322, 0f3F000000;
|
|
add.f32 %f326, %f324, 0f3F800000;
|
|
selp.f32 %f327, %f326, %f324, %p46;
|
|
selp.f32 %f328, %f325, %f322, %p46;
|
|
add.f32 %f329, %f328, 0fBF800000;
|
|
add.f32 %f330, %f328, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f331, %f330;
|
|
add.f32 %f332, %f329, %f329;
|
|
mul.f32 %f333, %f332, %f331;
|
|
mul.f32 %f334, %f333, %f333;
|
|
mov.f32 %f335, 0f3C4CAF63;
|
|
mov.f32 %f336, 0f3B18F0FE;
|
|
fma.rn.f32 %f337, %f336, %f334, %f335;
|
|
mov.f32 %f338, 0f3DAAAABD;
|
|
fma.rn.f32 %f339, %f337, %f334, %f338;
|
|
mul.rn.f32 %f340, %f339, %f334;
|
|
mul.rn.f32 %f341, %f340, %f333;
|
|
sub.f32 %f342, %f329, %f333;
|
|
add.f32 %f343, %f342, %f342;
|
|
neg.f32 %f344, %f333;
|
|
fma.rn.f32 %f345, %f344, %f329, %f343;
|
|
mul.rn.f32 %f346, %f331, %f345;
|
|
add.f32 %f347, %f341, %f333;
|
|
sub.f32 %f348, %f333, %f347;
|
|
add.f32 %f349, %f341, %f348;
|
|
add.f32 %f350, %f346, %f349;
|
|
add.f32 %f351, %f347, %f350;
|
|
sub.f32 %f352, %f347, %f351;
|
|
add.f32 %f353, %f350, %f352;
|
|
mov.f32 %f354, 0f3F317200;
|
|
mul.rn.f32 %f355, %f327, %f354;
|
|
mov.f32 %f356, 0f35BFBE8E;
|
|
mul.rn.f32 %f357, %f327, %f356;
|
|
add.f32 %f358, %f355, %f351;
|
|
sub.f32 %f359, %f355, %f358;
|
|
add.f32 %f360, %f351, %f359;
|
|
add.f32 %f361, %f353, %f360;
|
|
add.f32 %f362, %f357, %f361;
|
|
add.f32 %f363, %f358, %f362;
|
|
sub.f32 %f364, %f358, %f363;
|
|
add.f32 %f365, %f362, %f364;
|
|
mul.rn.f32 %f366, %f317, %f363;
|
|
neg.f32 %f367, %f366;
|
|
fma.rn.f32 %f368, %f317, %f363, %f367;
|
|
fma.rn.f32 %f369, %f317, %f365, %f368;
|
|
mov.f32 %f370, 0f00000000;
|
|
fma.rn.f32 %f371, %f370, %f363, %f369;
|
|
add.rn.f32 %f372, %f366, %f371;
|
|
neg.f32 %f373, %f372;
|
|
add.rn.f32 %f374, %f366, %f373;
|
|
add.rn.f32 %f375, %f374, %f371;
|
|
mov.b32 %r215, %f372;
|
|
setp.eq.s32 %p47, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f376, %r216;
|
|
add.f32 %f377, %f375, 0f37000000;
|
|
selp.f32 %f90, %f377, %f375, %p47;
|
|
selp.f32 %f378, %f376, %f372, %p47;
|
|
mov.f32 %f379, 0f3FB8AA3B;
|
|
mul.rn.f32 %f380, %f378, %f379;
|
|
cvt.rzi.f32.f32 %f381, %f380;
|
|
abs.f32 %f382, %f381;
|
|
setp.gt.f32 %p48, %f382, 0f42FC0000;
|
|
mov.b32 %r217, %f381;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f383, %r219;
|
|
selp.f32 %f384, %f383, %f381, %p48;
|
|
mov.f32 %f385, 0fBF317218;
|
|
fma.rn.f32 %f386, %f384, %f385, %f378;
|
|
mov.f32 %f387, 0f3102E308;
|
|
fma.rn.f32 %f388, %f384, %f387, %f386;
|
|
mul.f32 %f389, %f388, 0f3FB8AA3B;
|
|
add.f32 %f390, %f384, 0f4B40007F;
|
|
mov.b32 %r220, %f390;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f391, %r221;
|
|
ex2.approx.ftz.f32 %f392, %f389;
|
|
mul.f32 %f91, %f392, %f391;
|
|
setp.eq.f32 %p49, %f91, 0f7F800000;
|
|
mov.f32 %f1036, 0f7F800000;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1036, %f91, %f90, %f91;
|
|
|
|
$L__BB0_39:
|
|
mov.f32 %f984, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f983, %f984;
|
|
add.f32 %f982, %f983, %f983;
|
|
mov.f32 %f981, 0f3EE66666;
|
|
sub.f32 %f980, %f981, %f982;
|
|
abs.f32 %f979, %f980;
|
|
setp.lt.f32 %p50, %f85, 0f00000000;
|
|
setp.eq.f32 %p51, %f979, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f85, 0f00000000;
|
|
@%p52 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f397, %f85, %f85;
|
|
selp.f32 %f1038, %f397, 0f00000000, %p51;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_131:
|
|
mov.f32 %f912, 0f00000000;
|
|
mov.u32 %r345, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f912;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f912;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f912;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs109, 0;
|
|
st.global.v4.u16 [%rd23], {%rs106, %rs107, %rs108, %rs109};
|
|
|
|
$L__BB0_132:
|
|
ld.const.u64 %rd89, [params+256];
|
|
cvta.to.global.u64 %rd90, %rd89;
|
|
ld.const.u32 %r322, [params+248];
|
|
mad.lo.s32 %r323, %r322, %r6, %r5;
|
|
mul.wide.u32 %rd91, %r323, 8;
|
|
add.s64 %rd24, %rd90, %rd91;
|
|
setp.eq.s32 %p150, %r345, 0;
|
|
@%p150 bra $L__BB0_134;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f913, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f914, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f915, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f916, %f913, 0f00000000;
|
|
add.f32 %f917, %f914, 0f00000000;
|
|
add.f32 %f918, %f915, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f918;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f917;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f916;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs120, 0;
|
|
st.global.v4.u16 [%rd24], {%rs113, %rs114, %rs115, %rs120};
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_134:
|
|
mov.f32 %f921, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f921;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f921;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f921;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs124, 0;
|
|
st.global.v4.u16 [%rd24], {%rs121, %rs122, %rs123, %rs124};
|
|
|
|
$L__BB0_135:
|
|
ld.const.u64 %rd92, [params+272];
|
|
cvta.to.global.u64 %rd93, %rd92;
|
|
ld.const.u32 %r324, [params+264];
|
|
mad.lo.s32 %r325, %r324, %r6, %r5;
|
|
mul.wide.u32 %rd94, %r325, 8;
|
|
add.s64 %rd25, %rd93, %rd94;
|
|
@%p150 bra $L__BB0_137;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f922, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f923, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f924, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f925, %f922, 0f00000000;
|
|
add.f32 %f926, %f923, 0f00000000;
|
|
add.f32 %f927, %f924, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f927;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f926;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f925;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs135, 0;
|
|
st.global.v4.u16 [%rd25], {%rs128, %rs129, %rs130, %rs135};
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_137:
|
|
mov.f32 %f930, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f930;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f930;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f930;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs139, 0;
|
|
st.global.v4.u16 [%rd25], {%rs136, %rs137, %rs138, %rs139};
|
|
|
|
$L__BB0_138:
|
|
ld.const.u64 %rd95, [params+288];
|
|
cvta.to.global.u64 %rd96, %rd95;
|
|
ld.const.u32 %r326, [params+280];
|
|
mad.lo.s32 %r327, %r326, %r6, %r5;
|
|
mul.wide.u32 %rd97, %r327, 8;
|
|
add.s64 %rd26, %rd96, %rd97;
|
|
@%p150 bra $L__BB0_140;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f931, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f932, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f933, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f934, %f931, 0f00000000;
|
|
add.f32 %f935, %f932, 0f00000000;
|
|
add.f32 %f936, %f933, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f936;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f935;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f934;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs150, 0;
|
|
st.global.v4.u16 [%rd26], {%rs143, %rs144, %rs145, %rs150};
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_140:
|
|
mov.f32 %f939, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f939;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f939;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f939;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs154, 0;
|
|
st.global.v4.u16 [%rd26], {%rs151, %rs152, %rs153, %rs154};
|
|
|
|
$L__BB0_141:
|
|
ld.const.u64 %rd98, [params+304];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r328, [params+296];
|
|
mad.lo.s32 %r329, %r328, %r6, %r5;
|
|
mul.wide.u32 %rd100, %r329, 8;
|
|
add.s64 %rd27, %rd99, %rd100;
|
|
@%p150 bra $L__BB0_143;
|
|
|
|
ld.global.v4.u16 {%rs161, %rs162, %rs163, %rs164}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f940, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f941, %rs162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f942, %rs163;}
|
|
|
|
// end inline asm
|
|
add.f32 %f943, %f940, 0f00000000;
|
|
add.f32 %f944, %f941, 0f00000000;
|
|
add.f32 %f945, %f942, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f945;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f944;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f943;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs165, 0;
|
|
st.global.v4.u16 [%rd27], {%rs158, %rs159, %rs160, %rs165};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_143:
|
|
mov.f32 %f948, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f948;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f948;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f948;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs169, 0;
|
|
st.global.v4.u16 [%rd27], {%rs166, %rs167, %rs168, %rs169};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r222, %f1036;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f393, %r223;
|
|
selp.f32 %f1038, %f393, %f1036, %p1;
|
|
setp.geu.f32 %p53, %f85, 0f00000000;
|
|
@%p53 bra $L__BB0_44;
|
|
|
|
mov.f32 %f394, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f395, %f394;
|
|
setp.eq.f32 %p54, %f395, 0f3EE66666;
|
|
@%p54 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1038, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
add.f32 %f398, %f89, 0f3EE66666;
|
|
mov.b32 %r224, %f398;
|
|
setp.lt.s32 %p56, %r224, 2139095040;
|
|
@%p56 bra $L__BB0_49;
|
|
|
|
setp.gtu.f32 %p57, %f89, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1038, %f85, 0f3EE66666;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
setp.neu.f32 %p58, %f89, 0f7F800000;
|
|
@%p58 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1038, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
setp.eq.f32 %p59, %f85, 0f3F800000;
|
|
selp.f32 %f100, 0f3F800000, %f1038, %p59;
|
|
abs.f32 %f101, %f86;
|
|
setp.lt.f32 %p60, %f101, 0f00800000;
|
|
mul.f32 %f400, %f101, 0f4B800000;
|
|
selp.f32 %f401, %f400, %f101, %p60;
|
|
selp.f32 %f402, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r225, %f401;
|
|
and.b32 %r226, %r225, 8388607;
|
|
or.b32 %r227, %r226, 1065353216;
|
|
mov.b32 %f403, %r227;
|
|
shr.u32 %r228, %r225, 23;
|
|
cvt.rn.f32.u32 %f404, %r228;
|
|
add.f32 %f405, %f402, %f404;
|
|
setp.gt.f32 %p61, %f403, 0f3FB504F3;
|
|
mul.f32 %f406, %f403, 0f3F000000;
|
|
add.f32 %f407, %f405, 0f3F800000;
|
|
selp.f32 %f408, %f407, %f405, %p61;
|
|
selp.f32 %f409, %f406, %f403, %p61;
|
|
add.f32 %f410, %f409, 0fBF800000;
|
|
add.f32 %f411, %f409, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f412, %f411;
|
|
add.f32 %f413, %f410, %f410;
|
|
mul.f32 %f414, %f413, %f412;
|
|
mul.f32 %f415, %f414, %f414;
|
|
mov.f32 %f416, 0f3C4CAF63;
|
|
mov.f32 %f417, 0f3B18F0FE;
|
|
fma.rn.f32 %f418, %f417, %f415, %f416;
|
|
mov.f32 %f419, 0f3DAAAABD;
|
|
fma.rn.f32 %f420, %f418, %f415, %f419;
|
|
mul.rn.f32 %f421, %f420, %f415;
|
|
mul.rn.f32 %f422, %f421, %f414;
|
|
sub.f32 %f423, %f410, %f414;
|
|
add.f32 %f424, %f423, %f423;
|
|
neg.f32 %f425, %f414;
|
|
fma.rn.f32 %f426, %f425, %f410, %f424;
|
|
mul.rn.f32 %f427, %f412, %f426;
|
|
add.f32 %f428, %f422, %f414;
|
|
sub.f32 %f429, %f414, %f428;
|
|
add.f32 %f430, %f422, %f429;
|
|
add.f32 %f431, %f427, %f430;
|
|
add.f32 %f432, %f428, %f431;
|
|
sub.f32 %f433, %f428, %f432;
|
|
add.f32 %f434, %f431, %f433;
|
|
mov.f32 %f435, 0f3F317200;
|
|
mul.rn.f32 %f436, %f408, %f435;
|
|
mov.f32 %f437, 0f35BFBE8E;
|
|
mul.rn.f32 %f438, %f408, %f437;
|
|
add.f32 %f439, %f436, %f432;
|
|
sub.f32 %f440, %f436, %f439;
|
|
add.f32 %f441, %f432, %f440;
|
|
add.f32 %f442, %f434, %f441;
|
|
add.f32 %f443, %f438, %f442;
|
|
add.f32 %f444, %f439, %f443;
|
|
sub.f32 %f445, %f439, %f444;
|
|
add.f32 %f446, %f443, %f445;
|
|
mov.f32 %f447, 0f3EE66666;
|
|
mul.rn.f32 %f448, %f447, %f444;
|
|
neg.f32 %f449, %f448;
|
|
fma.rn.f32 %f450, %f447, %f444, %f449;
|
|
fma.rn.f32 %f451, %f447, %f446, %f450;
|
|
mov.f32 %f452, 0f00000000;
|
|
fma.rn.f32 %f453, %f452, %f444, %f451;
|
|
add.rn.f32 %f454, %f448, %f453;
|
|
neg.f32 %f455, %f454;
|
|
add.rn.f32 %f456, %f448, %f455;
|
|
add.rn.f32 %f457, %f456, %f453;
|
|
mov.b32 %r229, %f454;
|
|
setp.eq.s32 %p62, %r229, 1118925336;
|
|
add.s32 %r230, %r229, -1;
|
|
mov.b32 %f458, %r230;
|
|
add.f32 %f459, %f457, 0f37000000;
|
|
selp.f32 %f102, %f459, %f457, %p62;
|
|
selp.f32 %f460, %f458, %f454, %p62;
|
|
mov.f32 %f461, 0f3FB8AA3B;
|
|
mul.rn.f32 %f462, %f460, %f461;
|
|
cvt.rzi.f32.f32 %f463, %f462;
|
|
abs.f32 %f464, %f463;
|
|
setp.gt.f32 %p63, %f464, 0f42FC0000;
|
|
mov.b32 %r231, %f463;
|
|
and.b32 %r232, %r231, -2147483648;
|
|
or.b32 %r233, %r232, 1123811328;
|
|
mov.b32 %f465, %r233;
|
|
selp.f32 %f466, %f465, %f463, %p63;
|
|
mov.f32 %f467, 0fBF317218;
|
|
fma.rn.f32 %f468, %f466, %f467, %f460;
|
|
mov.f32 %f469, 0f3102E308;
|
|
fma.rn.f32 %f470, %f466, %f469, %f468;
|
|
mul.f32 %f471, %f470, 0f3FB8AA3B;
|
|
add.f32 %f472, %f466, 0f4B40007F;
|
|
mov.b32 %r234, %f472;
|
|
shl.b32 %r235, %r234, 23;
|
|
mov.b32 %f473, %r235;
|
|
ex2.approx.ftz.f32 %f474, %f471;
|
|
mul.f32 %f103, %f474, %f473;
|
|
setp.eq.f32 %p64, %f103, 0f7F800000;
|
|
mov.f32 %f1039, 0f7F800000;
|
|
@%p64 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1039, %f103, %f102, %f103;
|
|
|
|
$L__BB0_51:
|
|
setp.lt.f32 %p65, %f86, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f86, 0f00000000;
|
|
@%p67 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f479, %f86, %f86;
|
|
selp.f32 %f1041, %f479, 0f00000000, %p51;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r236, %f1039;
|
|
xor.b32 %r237, %r236, -2147483648;
|
|
mov.b32 %f475, %r237;
|
|
selp.f32 %f1041, %f475, %f1039, %p2;
|
|
setp.geu.f32 %p68, %f86, 0f00000000;
|
|
@%p68 bra $L__BB0_56;
|
|
|
|
mov.f32 %f476, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f477, %f476;
|
|
setp.eq.f32 %p69, %f477, 0f3EE66666;
|
|
@%p69 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1041, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f480, %f101, 0f3EE66666;
|
|
mov.b32 %r238, %f480;
|
|
setp.lt.s32 %p71, %r238, 2139095040;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
setp.gtu.f32 %p72, %f101, 0f7F800000;
|
|
@%p72 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1041, %f86, 0f3EE66666;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
setp.neu.f32 %p73, %f101, 0f7F800000;
|
|
@%p73 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1041, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
setp.eq.f32 %p74, %f86, 0f3F800000;
|
|
selp.f32 %f112, 0f3F800000, %f1041, %p74;
|
|
abs.f32 %f113, %f87;
|
|
setp.lt.f32 %p75, %f113, 0f00800000;
|
|
mul.f32 %f482, %f113, 0f4B800000;
|
|
selp.f32 %f483, %f482, %f113, %p75;
|
|
selp.f32 %f484, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r239, %f483;
|
|
and.b32 %r240, %r239, 8388607;
|
|
or.b32 %r241, %r240, 1065353216;
|
|
mov.b32 %f485, %r241;
|
|
shr.u32 %r242, %r239, 23;
|
|
cvt.rn.f32.u32 %f486, %r242;
|
|
add.f32 %f487, %f484, %f486;
|
|
setp.gt.f32 %p76, %f485, 0f3FB504F3;
|
|
mul.f32 %f488, %f485, 0f3F000000;
|
|
add.f32 %f489, %f487, 0f3F800000;
|
|
selp.f32 %f490, %f489, %f487, %p76;
|
|
selp.f32 %f491, %f488, %f485, %p76;
|
|
add.f32 %f492, %f491, 0fBF800000;
|
|
add.f32 %f493, %f491, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f494, %f493;
|
|
add.f32 %f495, %f492, %f492;
|
|
mul.f32 %f496, %f495, %f494;
|
|
mul.f32 %f497, %f496, %f496;
|
|
mov.f32 %f498, 0f3C4CAF63;
|
|
mov.f32 %f499, 0f3B18F0FE;
|
|
fma.rn.f32 %f500, %f499, %f497, %f498;
|
|
mov.f32 %f501, 0f3DAAAABD;
|
|
fma.rn.f32 %f502, %f500, %f497, %f501;
|
|
mul.rn.f32 %f503, %f502, %f497;
|
|
mul.rn.f32 %f504, %f503, %f496;
|
|
sub.f32 %f505, %f492, %f496;
|
|
add.f32 %f506, %f505, %f505;
|
|
neg.f32 %f507, %f496;
|
|
fma.rn.f32 %f508, %f507, %f492, %f506;
|
|
mul.rn.f32 %f509, %f494, %f508;
|
|
add.f32 %f510, %f504, %f496;
|
|
sub.f32 %f511, %f496, %f510;
|
|
add.f32 %f512, %f504, %f511;
|
|
add.f32 %f513, %f509, %f512;
|
|
add.f32 %f514, %f510, %f513;
|
|
sub.f32 %f515, %f510, %f514;
|
|
add.f32 %f516, %f513, %f515;
|
|
mov.f32 %f517, 0f3F317200;
|
|
mul.rn.f32 %f518, %f490, %f517;
|
|
mov.f32 %f519, 0f35BFBE8E;
|
|
mul.rn.f32 %f520, %f490, %f519;
|
|
add.f32 %f521, %f518, %f514;
|
|
sub.f32 %f522, %f518, %f521;
|
|
add.f32 %f523, %f514, %f522;
|
|
add.f32 %f524, %f516, %f523;
|
|
add.f32 %f525, %f520, %f524;
|
|
add.f32 %f526, %f521, %f525;
|
|
sub.f32 %f527, %f521, %f526;
|
|
add.f32 %f528, %f525, %f527;
|
|
mov.f32 %f529, 0f3EE66666;
|
|
mul.rn.f32 %f530, %f529, %f526;
|
|
neg.f32 %f531, %f530;
|
|
fma.rn.f32 %f532, %f529, %f526, %f531;
|
|
fma.rn.f32 %f533, %f529, %f528, %f532;
|
|
mov.f32 %f534, 0f00000000;
|
|
fma.rn.f32 %f535, %f534, %f526, %f533;
|
|
add.rn.f32 %f536, %f530, %f535;
|
|
neg.f32 %f537, %f536;
|
|
add.rn.f32 %f538, %f530, %f537;
|
|
add.rn.f32 %f539, %f538, %f535;
|
|
mov.b32 %r243, %f536;
|
|
setp.eq.s32 %p77, %r243, 1118925336;
|
|
add.s32 %r244, %r243, -1;
|
|
mov.b32 %f540, %r244;
|
|
add.f32 %f541, %f539, 0f37000000;
|
|
selp.f32 %f114, %f541, %f539, %p77;
|
|
selp.f32 %f542, %f540, %f536, %p77;
|
|
mov.f32 %f543, 0f3FB8AA3B;
|
|
mul.rn.f32 %f544, %f542, %f543;
|
|
cvt.rzi.f32.f32 %f545, %f544;
|
|
abs.f32 %f546, %f545;
|
|
setp.gt.f32 %p78, %f546, 0f42FC0000;
|
|
mov.b32 %r245, %f545;
|
|
and.b32 %r246, %r245, -2147483648;
|
|
or.b32 %r247, %r246, 1123811328;
|
|
mov.b32 %f547, %r247;
|
|
selp.f32 %f548, %f547, %f545, %p78;
|
|
mov.f32 %f549, 0fBF317218;
|
|
fma.rn.f32 %f550, %f548, %f549, %f542;
|
|
mov.f32 %f551, 0f3102E308;
|
|
fma.rn.f32 %f552, %f548, %f551, %f550;
|
|
mul.f32 %f553, %f552, 0f3FB8AA3B;
|
|
add.f32 %f554, %f548, 0f4B40007F;
|
|
mov.b32 %r248, %f554;
|
|
shl.b32 %r249, %r248, 23;
|
|
mov.b32 %f555, %r249;
|
|
ex2.approx.ftz.f32 %f556, %f553;
|
|
mul.f32 %f115, %f556, %f555;
|
|
setp.eq.f32 %p79, %f115, 0f7F800000;
|
|
mov.f32 %f1042, 0f7F800000;
|
|
@%p79 bra $L__BB0_63;
|
|
|
|
fma.rn.f32 %f1042, %f115, %f114, %f115;
|
|
|
|
$L__BB0_63:
|
|
setp.lt.f32 %p80, %f87, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f87, 0f00000000;
|
|
@%p82 bra $L__BB0_67;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f561, %f87, %f87;
|
|
selp.f32 %f1044, %f561, 0f00000000, %p51;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_64:
|
|
mov.b32 %r250, %f1042;
|
|
xor.b32 %r251, %r250, -2147483648;
|
|
mov.b32 %f557, %r251;
|
|
selp.f32 %f1044, %f557, %f1042, %p3;
|
|
setp.geu.f32 %p83, %f87, 0f00000000;
|
|
@%p83 bra $L__BB0_68;
|
|
|
|
mov.f32 %f558, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f559, %f558;
|
|
setp.eq.f32 %p84, %f559, 0f3EE66666;
|
|
@%p84 bra $L__BB0_68;
|
|
|
|
mov.f32 %f1044, 0f7FFFFFFF;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f562, %f113, 0f3EE66666;
|
|
mov.b32 %r252, %f562;
|
|
setp.lt.s32 %p86, %r252, 2139095040;
|
|
@%p86 bra $L__BB0_73;
|
|
|
|
setp.gtu.f32 %p87, %f113, 0f7F800000;
|
|
@%p87 bra $L__BB0_72;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f1044, %f87, 0f3EE66666;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_70:
|
|
setp.neu.f32 %p88, %f113, 0f7F800000;
|
|
@%p88 bra $L__BB0_73;
|
|
|
|
selp.f32 %f1044, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_73:
|
|
setp.eq.f32 %p89, %f87, 0f3F800000;
|
|
mov.f32 %f564, 0f3F800000;
|
|
selp.f32 %f565, 0f3F800000, %f1044, %p89;
|
|
min.f32 %f566, %f100, %f564;
|
|
mov.f32 %f567, 0f00000000;
|
|
max.f32 %f124, %f567, %f566;
|
|
min.f32 %f568, %f112, %f564;
|
|
max.f32 %f125, %f567, %f568;
|
|
min.f32 %f569, %f565, %f564;
|
|
max.f32 %f126, %f567, %f569;
|
|
mov.f32 %f573, 0f3ED55555;
|
|
abs.f32 %f128, %f124;
|
|
setp.lt.f32 %p90, %f128, 0f00800000;
|
|
mul.f32 %f575, %f128, 0f4B800000;
|
|
selp.f32 %f576, %f575, %f128, %p90;
|
|
selp.f32 %f577, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r255, %f576;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f578, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f579, %r258;
|
|
add.f32 %f580, %f577, %f579;
|
|
setp.gt.f32 %p91, %f578, 0f3FB504F3;
|
|
mul.f32 %f581, %f578, 0f3F000000;
|
|
add.f32 %f582, %f580, 0f3F800000;
|
|
selp.f32 %f583, %f582, %f580, %p91;
|
|
selp.f32 %f584, %f581, %f578, %p91;
|
|
add.f32 %f585, %f584, 0fBF800000;
|
|
add.f32 %f586, %f584, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f587, %f586;
|
|
add.f32 %f588, %f585, %f585;
|
|
mul.f32 %f589, %f588, %f587;
|
|
mul.f32 %f590, %f589, %f589;
|
|
mov.f32 %f591, 0f3C4CAF63;
|
|
mov.f32 %f592, 0f3B18F0FE;
|
|
fma.rn.f32 %f593, %f592, %f590, %f591;
|
|
mov.f32 %f594, 0f3DAAAABD;
|
|
fma.rn.f32 %f595, %f593, %f590, %f594;
|
|
mul.rn.f32 %f596, %f595, %f590;
|
|
mul.rn.f32 %f597, %f596, %f589;
|
|
sub.f32 %f598, %f585, %f589;
|
|
add.f32 %f599, %f598, %f598;
|
|
neg.f32 %f600, %f589;
|
|
fma.rn.f32 %f601, %f600, %f585, %f599;
|
|
mul.rn.f32 %f602, %f587, %f601;
|
|
add.f32 %f603, %f597, %f589;
|
|
sub.f32 %f604, %f589, %f603;
|
|
add.f32 %f605, %f597, %f604;
|
|
add.f32 %f606, %f602, %f605;
|
|
add.f32 %f607, %f603, %f606;
|
|
sub.f32 %f608, %f603, %f607;
|
|
add.f32 %f609, %f606, %f608;
|
|
mov.f32 %f610, 0f3F317200;
|
|
mul.rn.f32 %f611, %f583, %f610;
|
|
mov.f32 %f612, 0f35BFBE8E;
|
|
mul.rn.f32 %f613, %f583, %f612;
|
|
add.f32 %f614, %f611, %f607;
|
|
sub.f32 %f615, %f611, %f614;
|
|
add.f32 %f616, %f607, %f615;
|
|
add.f32 %f617, %f609, %f616;
|
|
add.f32 %f618, %f613, %f617;
|
|
add.f32 %f619, %f614, %f618;
|
|
sub.f32 %f620, %f614, %f619;
|
|
add.f32 %f621, %f618, %f620;
|
|
mul.rn.f32 %f622, %f573, %f619;
|
|
neg.f32 %f623, %f622;
|
|
fma.rn.f32 %f624, %f573, %f619, %f623;
|
|
fma.rn.f32 %f625, %f573, %f621, %f624;
|
|
fma.rn.f32 %f626, %f567, %f619, %f625;
|
|
add.rn.f32 %f627, %f622, %f626;
|
|
neg.f32 %f628, %f627;
|
|
add.rn.f32 %f629, %f622, %f628;
|
|
add.rn.f32 %f630, %f629, %f626;
|
|
mov.b32 %r259, %f627;
|
|
setp.eq.s32 %p92, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f631, %r260;
|
|
add.f32 %f632, %f630, 0f37000000;
|
|
selp.f32 %f129, %f632, %f630, %p92;
|
|
selp.f32 %f633, %f631, %f627, %p92;
|
|
mov.f32 %f634, 0f3FB8AA3B;
|
|
mul.rn.f32 %f635, %f633, %f634;
|
|
cvt.rzi.f32.f32 %f636, %f635;
|
|
abs.f32 %f637, %f636;
|
|
setp.gt.f32 %p93, %f637, 0f42FC0000;
|
|
mov.b32 %r261, %f636;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f638, %r263;
|
|
selp.f32 %f639, %f638, %f636, %p93;
|
|
mov.f32 %f640, 0fBF317218;
|
|
fma.rn.f32 %f641, %f639, %f640, %f633;
|
|
mov.f32 %f642, 0f3102E308;
|
|
fma.rn.f32 %f643, %f639, %f642, %f641;
|
|
mul.f32 %f644, %f643, 0f3FB8AA3B;
|
|
add.f32 %f645, %f639, 0f4B40007F;
|
|
mov.b32 %r264, %f645;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f646, %r265;
|
|
ex2.approx.ftz.f32 %f647, %f644;
|
|
mul.f32 %f130, %f647, %f646;
|
|
setp.eq.f32 %p94, %f130, 0f7F800000;
|
|
mov.f32 %f1045, 0f7F800000;
|
|
@%p94 bra $L__BB0_75;
|
|
|
|
fma.rn.f32 %f1045, %f130, %f129, %f130;
|
|
|
|
$L__BB0_75:
|
|
mov.f32 %f956, 0f00000000;
|
|
max.f32 %f955, %f956, %f566;
|
|
mov.f32 %f954, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f953, %f954;
|
|
add.f32 %f952, %f953, %f953;
|
|
mov.f32 %f951, 0f3ED55555;
|
|
sub.f32 %f950, %f951, %f952;
|
|
abs.f32 %f949, %f950;
|
|
setp.lt.f32 %p95, %f955, 0f00000000;
|
|
setp.eq.f32 %p96, %f949, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f955, 0f00000000;
|
|
@%p97 bra $L__BB0_79;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_79:
|
|
mov.f32 %f977, 0f00000000;
|
|
max.f32 %f976, %f977, %f566;
|
|
add.f32 %f652, %f976, %f976;
|
|
selp.f32 %f1047, %f652, 0f00000000, %p96;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_76:
|
|
mov.f32 %f958, 0f00000000;
|
|
max.f32 %f957, %f958, %f566;
|
|
mov.b32 %r266, %f1045;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f648, %r267;
|
|
selp.f32 %f1047, %f648, %f1045, %p4;
|
|
setp.geu.f32 %p98, %f957, 0f00000000;
|
|
@%p98 bra $L__BB0_80;
|
|
|
|
mov.f32 %f649, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f650, %f649;
|
|
setp.eq.f32 %p99, %f650, 0f3ED55555;
|
|
@%p99 bra $L__BB0_80;
|
|
|
|
mov.f32 %f1047, 0f7FFFFFFF;
|
|
|
|
$L__BB0_80:
|
|
mov.f32 %f961, 0f00000000;
|
|
max.f32 %f960, %f961, %f566;
|
|
abs.f32 %f959, %f960;
|
|
add.f32 %f653, %f959, 0f3ED55555;
|
|
mov.b32 %r268, %f653;
|
|
setp.lt.s32 %p101, %r268, 2139095040;
|
|
@%p101 bra $L__BB0_85;
|
|
|
|
mov.f32 %f970, 0f00000000;
|
|
max.f32 %f969, %f970, %f566;
|
|
abs.f32 %f968, %f969;
|
|
setp.gtu.f32 %p102, %f968, 0f7F800000;
|
|
@%p102 bra $L__BB0_84;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_84:
|
|
mov.f32 %f975, 0f00000000;
|
|
max.f32 %f974, %f975, %f566;
|
|
add.f32 %f1047, %f974, 0f3ED55555;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_82:
|
|
mov.f32 %f973, 0f00000000;
|
|
max.f32 %f972, %f973, %f566;
|
|
abs.f32 %f971, %f972;
|
|
setp.neu.f32 %p103, %f971, 0f7F800000;
|
|
@%p103 bra $L__BB0_85;
|
|
|
|
selp.f32 %f1047, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_85:
|
|
abs.f32 %f139, %f125;
|
|
setp.lt.f32 %p104, %f139, 0f00800000;
|
|
mul.f32 %f655, %f139, 0f4B800000;
|
|
selp.f32 %f656, %f655, %f139, %p104;
|
|
selp.f32 %f657, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r269, %f656;
|
|
and.b32 %r270, %r269, 8388607;
|
|
or.b32 %r271, %r270, 1065353216;
|
|
mov.b32 %f658, %r271;
|
|
shr.u32 %r272, %r269, 23;
|
|
cvt.rn.f32.u32 %f659, %r272;
|
|
add.f32 %f660, %f657, %f659;
|
|
setp.gt.f32 %p105, %f658, 0f3FB504F3;
|
|
mul.f32 %f661, %f658, 0f3F000000;
|
|
add.f32 %f662, %f660, 0f3F800000;
|
|
selp.f32 %f663, %f662, %f660, %p105;
|
|
selp.f32 %f664, %f661, %f658, %p105;
|
|
add.f32 %f665, %f664, 0fBF800000;
|
|
add.f32 %f666, %f664, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f667, %f666;
|
|
add.f32 %f668, %f665, %f665;
|
|
mul.f32 %f669, %f668, %f667;
|
|
mul.f32 %f670, %f669, %f669;
|
|
mov.f32 %f671, 0f3C4CAF63;
|
|
mov.f32 %f672, 0f3B18F0FE;
|
|
fma.rn.f32 %f673, %f672, %f670, %f671;
|
|
mov.f32 %f674, 0f3DAAAABD;
|
|
fma.rn.f32 %f675, %f673, %f670, %f674;
|
|
mul.rn.f32 %f676, %f675, %f670;
|
|
mul.rn.f32 %f677, %f676, %f669;
|
|
sub.f32 %f678, %f665, %f669;
|
|
add.f32 %f679, %f678, %f678;
|
|
neg.f32 %f680, %f669;
|
|
fma.rn.f32 %f681, %f680, %f665, %f679;
|
|
mul.rn.f32 %f682, %f667, %f681;
|
|
add.f32 %f683, %f677, %f669;
|
|
sub.f32 %f684, %f669, %f683;
|
|
add.f32 %f685, %f677, %f684;
|
|
add.f32 %f686, %f682, %f685;
|
|
add.f32 %f687, %f683, %f686;
|
|
sub.f32 %f688, %f683, %f687;
|
|
add.f32 %f689, %f686, %f688;
|
|
mov.f32 %f690, 0f3F317200;
|
|
mul.rn.f32 %f691, %f663, %f690;
|
|
mov.f32 %f692, 0f35BFBE8E;
|
|
mul.rn.f32 %f693, %f663, %f692;
|
|
add.f32 %f694, %f691, %f687;
|
|
sub.f32 %f695, %f691, %f694;
|
|
add.f32 %f696, %f687, %f695;
|
|
add.f32 %f697, %f689, %f696;
|
|
add.f32 %f698, %f693, %f697;
|
|
add.f32 %f699, %f694, %f698;
|
|
sub.f32 %f700, %f694, %f699;
|
|
add.f32 %f701, %f698, %f700;
|
|
mov.f32 %f702, 0f3ED55555;
|
|
mul.rn.f32 %f703, %f702, %f699;
|
|
neg.f32 %f704, %f703;
|
|
fma.rn.f32 %f705, %f702, %f699, %f704;
|
|
fma.rn.f32 %f706, %f702, %f701, %f705;
|
|
mov.f32 %f707, 0f00000000;
|
|
fma.rn.f32 %f708, %f707, %f699, %f706;
|
|
add.rn.f32 %f709, %f703, %f708;
|
|
neg.f32 %f710, %f709;
|
|
add.rn.f32 %f711, %f703, %f710;
|
|
add.rn.f32 %f712, %f711, %f708;
|
|
mov.b32 %r273, %f709;
|
|
setp.eq.s32 %p106, %r273, 1118925336;
|
|
add.s32 %r274, %r273, -1;
|
|
mov.b32 %f713, %r274;
|
|
add.f32 %f714, %f712, 0f37000000;
|
|
selp.f32 %f140, %f714, %f712, %p106;
|
|
selp.f32 %f715, %f713, %f709, %p106;
|
|
mov.f32 %f716, 0f3FB8AA3B;
|
|
mul.rn.f32 %f717, %f715, %f716;
|
|
cvt.rzi.f32.f32 %f718, %f717;
|
|
abs.f32 %f719, %f718;
|
|
setp.gt.f32 %p107, %f719, 0f42FC0000;
|
|
mov.b32 %r275, %f718;
|
|
and.b32 %r276, %r275, -2147483648;
|
|
or.b32 %r277, %r276, 1123811328;
|
|
mov.b32 %f720, %r277;
|
|
selp.f32 %f721, %f720, %f718, %p107;
|
|
mov.f32 %f722, 0fBF317218;
|
|
fma.rn.f32 %f723, %f721, %f722, %f715;
|
|
mov.f32 %f724, 0f3102E308;
|
|
fma.rn.f32 %f725, %f721, %f724, %f723;
|
|
mul.f32 %f726, %f725, 0f3FB8AA3B;
|
|
add.f32 %f727, %f721, 0f4B40007F;
|
|
mov.b32 %r278, %f727;
|
|
shl.b32 %r279, %r278, 23;
|
|
mov.b32 %f728, %r279;
|
|
ex2.approx.ftz.f32 %f729, %f726;
|
|
mul.f32 %f141, %f729, %f728;
|
|
setp.eq.f32 %p108, %f141, 0f7F800000;
|
|
mov.f32 %f1048, 0f7F800000;
|
|
@%p108 bra $L__BB0_87;
|
|
|
|
fma.rn.f32 %f1048, %f141, %f140, %f141;
|
|
|
|
$L__BB0_87:
|
|
setp.lt.f32 %p109, %f125, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f125, 0f00000000;
|
|
@%p111 bra $L__BB0_91;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f734, %f125, %f125;
|
|
selp.f32 %f1050, %f734, 0f00000000, %p96;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_88:
|
|
mov.b32 %r280, %f1048;
|
|
xor.b32 %r281, %r280, -2147483648;
|
|
mov.b32 %f730, %r281;
|
|
selp.f32 %f1050, %f730, %f1048, %p5;
|
|
setp.geu.f32 %p112, %f125, 0f00000000;
|
|
@%p112 bra $L__BB0_92;
|
|
|
|
mov.f32 %f731, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f732, %f731;
|
|
setp.eq.f32 %p113, %f732, 0f3ED55555;
|
|
@%p113 bra $L__BB0_92;
|
|
|
|
mov.f32 %f1050, 0f7FFFFFFF;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f991, 0f00000000;
|
|
max.f32 %f990, %f991, %f568;
|
|
abs.f32 %f989, %f990;
|
|
add.f32 %f735, %f989, 0f3ED55555;
|
|
mov.b32 %r282, %f735;
|
|
setp.lt.s32 %p115, %r282, 2139095040;
|
|
@%p115 bra $L__BB0_97;
|
|
|
|
mov.f32 %f994, 0f00000000;
|
|
max.f32 %f993, %f994, %f568;
|
|
abs.f32 %f992, %f993;
|
|
setp.gtu.f32 %p116, %f992, 0f7F800000;
|
|
@%p116 bra $L__BB0_96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_96:
|
|
add.f32 %f1050, %f125, 0f3ED55555;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_94:
|
|
mov.f32 %f997, 0f00000000;
|
|
max.f32 %f996, %f997, %f568;
|
|
abs.f32 %f995, %f996;
|
|
setp.neu.f32 %p117, %f995, 0f7F800000;
|
|
@%p117 bra $L__BB0_97;
|
|
|
|
selp.f32 %f1050, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_97:
|
|
abs.f32 %f150, %f126;
|
|
setp.lt.f32 %p118, %f150, 0f00800000;
|
|
mul.f32 %f737, %f150, 0f4B800000;
|
|
selp.f32 %f738, %f737, %f150, %p118;
|
|
selp.f32 %f739, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r283, %f738;
|
|
and.b32 %r284, %r283, 8388607;
|
|
or.b32 %r285, %r284, 1065353216;
|
|
mov.b32 %f740, %r285;
|
|
shr.u32 %r286, %r283, 23;
|
|
cvt.rn.f32.u32 %f741, %r286;
|
|
add.f32 %f742, %f739, %f741;
|
|
setp.gt.f32 %p119, %f740, 0f3FB504F3;
|
|
mul.f32 %f743, %f740, 0f3F000000;
|
|
add.f32 %f744, %f742, 0f3F800000;
|
|
selp.f32 %f745, %f744, %f742, %p119;
|
|
selp.f32 %f746, %f743, %f740, %p119;
|
|
add.f32 %f747, %f746, 0fBF800000;
|
|
add.f32 %f748, %f746, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f749, %f748;
|
|
add.f32 %f750, %f747, %f747;
|
|
mul.f32 %f751, %f750, %f749;
|
|
mul.f32 %f752, %f751, %f751;
|
|
mov.f32 %f753, 0f3C4CAF63;
|
|
mov.f32 %f754, 0f3B18F0FE;
|
|
fma.rn.f32 %f755, %f754, %f752, %f753;
|
|
mov.f32 %f756, 0f3DAAAABD;
|
|
fma.rn.f32 %f757, %f755, %f752, %f756;
|
|
mul.rn.f32 %f758, %f757, %f752;
|
|
mul.rn.f32 %f759, %f758, %f751;
|
|
sub.f32 %f760, %f747, %f751;
|
|
add.f32 %f761, %f760, %f760;
|
|
neg.f32 %f762, %f751;
|
|
fma.rn.f32 %f763, %f762, %f747, %f761;
|
|
mul.rn.f32 %f764, %f749, %f763;
|
|
add.f32 %f765, %f759, %f751;
|
|
sub.f32 %f766, %f751, %f765;
|
|
add.f32 %f767, %f759, %f766;
|
|
add.f32 %f768, %f764, %f767;
|
|
add.f32 %f769, %f765, %f768;
|
|
sub.f32 %f770, %f765, %f769;
|
|
add.f32 %f771, %f768, %f770;
|
|
mov.f32 %f772, 0f3F317200;
|
|
mul.rn.f32 %f773, %f745, %f772;
|
|
mov.f32 %f774, 0f35BFBE8E;
|
|
mul.rn.f32 %f775, %f745, %f774;
|
|
add.f32 %f776, %f773, %f769;
|
|
sub.f32 %f777, %f773, %f776;
|
|
add.f32 %f778, %f769, %f777;
|
|
add.f32 %f779, %f771, %f778;
|
|
add.f32 %f780, %f775, %f779;
|
|
add.f32 %f781, %f776, %f780;
|
|
sub.f32 %f782, %f776, %f781;
|
|
add.f32 %f783, %f780, %f782;
|
|
mov.f32 %f784, 0f3ED55555;
|
|
mul.rn.f32 %f785, %f784, %f781;
|
|
neg.f32 %f786, %f785;
|
|
fma.rn.f32 %f787, %f784, %f781, %f786;
|
|
fma.rn.f32 %f788, %f784, %f783, %f787;
|
|
mov.f32 %f789, 0f00000000;
|
|
fma.rn.f32 %f790, %f789, %f781, %f788;
|
|
add.rn.f32 %f791, %f785, %f790;
|
|
neg.f32 %f792, %f791;
|
|
add.rn.f32 %f793, %f785, %f792;
|
|
add.rn.f32 %f794, %f793, %f790;
|
|
mov.b32 %r287, %f791;
|
|
setp.eq.s32 %p120, %r287, 1118925336;
|
|
add.s32 %r288, %r287, -1;
|
|
mov.b32 %f795, %r288;
|
|
add.f32 %f796, %f794, 0f37000000;
|
|
selp.f32 %f151, %f796, %f794, %p120;
|
|
selp.f32 %f797, %f795, %f791, %p120;
|
|
mov.f32 %f798, 0f3FB8AA3B;
|
|
mul.rn.f32 %f799, %f797, %f798;
|
|
cvt.rzi.f32.f32 %f800, %f799;
|
|
abs.f32 %f801, %f800;
|
|
setp.gt.f32 %p121, %f801, 0f42FC0000;
|
|
mov.b32 %r289, %f800;
|
|
and.b32 %r290, %r289, -2147483648;
|
|
or.b32 %r291, %r290, 1123811328;
|
|
mov.b32 %f802, %r291;
|
|
selp.f32 %f803, %f802, %f800, %p121;
|
|
mov.f32 %f804, 0fBF317218;
|
|
fma.rn.f32 %f805, %f803, %f804, %f797;
|
|
mov.f32 %f806, 0f3102E308;
|
|
fma.rn.f32 %f807, %f803, %f806, %f805;
|
|
mul.f32 %f808, %f807, 0f3FB8AA3B;
|
|
add.f32 %f809, %f803, 0f4B40007F;
|
|
mov.b32 %r292, %f809;
|
|
shl.b32 %r293, %r292, 23;
|
|
mov.b32 %f810, %r293;
|
|
ex2.approx.ftz.f32 %f811, %f808;
|
|
mul.f32 %f152, %f811, %f810;
|
|
setp.eq.f32 %p122, %f152, 0f7F800000;
|
|
mov.f32 %f1051, 0f7F800000;
|
|
@%p122 bra $L__BB0_99;
|
|
|
|
fma.rn.f32 %f1051, %f152, %f151, %f152;
|
|
|
|
$L__BB0_99:
|
|
setp.lt.f32 %p123, %f126, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f126, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f816, %f126, %f126;
|
|
selp.f32 %f1053, %f816, 0f00000000, %p96;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_100:
|
|
mov.b32 %r294, %f1051;
|
|
xor.b32 %r295, %r294, -2147483648;
|
|
mov.b32 %f812, %r295;
|
|
selp.f32 %f1053, %f812, %f1051, %p6;
|
|
setp.geu.f32 %p126, %f126, 0f00000000;
|
|
@%p126 bra $L__BB0_104;
|
|
|
|
mov.f32 %f813, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f814, %f813;
|
|
setp.eq.f32 %p127, %f814, 0f3ED55555;
|
|
@%p127 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1053, 0f7FFFFFFF;
|
|
|
|
$L__BB0_104:
|
|
mov.f32 %f1000, 0f00000000;
|
|
max.f32 %f999, %f1000, %f569;
|
|
abs.f32 %f998, %f999;
|
|
add.f32 %f817, %f998, 0f3ED55555;
|
|
mov.b32 %r296, %f817;
|
|
setp.lt.s32 %p129, %r296, 2139095040;
|
|
@%p129 bra $L__BB0_109;
|
|
|
|
mov.f32 %f1003, 0f00000000;
|
|
max.f32 %f1002, %f1003, %f569;
|
|
abs.f32 %f1001, %f1002;
|
|
setp.gtu.f32 %p130, %f1001, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_108:
|
|
add.f32 %f1053, %f126, 0f3ED55555;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1006, 0f00000000;
|
|
max.f32 %f1005, %f1006, %f569;
|
|
abs.f32 %f1004, %f1005;
|
|
setp.neu.f32 %p131, %f1004, 0f7F800000;
|
|
@%p131 bra $L__BB0_109;
|
|
|
|
selp.f32 %f1053, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_109:
|
|
mov.f32 %f963, 0f00000000;
|
|
max.f32 %f962, %f963, %f566;
|
|
ld.const.u64 %rd103, [params+144];
|
|
cvta.to.global.u64 %rd102, %rd103;
|
|
ld.const.u32 %r331, [params+136];
|
|
mad.lo.s32 %r330, %r331, %r6, %r5;
|
|
cvt.u64.u32 %rd101, %r330;
|
|
fma.rn.f32 %f818, %f1047, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f962, 0f3F800000;
|
|
mov.f32 %f819, 0f3F800000;
|
|
selp.f32 %f820, 0f3F7FFFFF, %f818, %p132;
|
|
mul.f32 %f821, %f962, 0f414EB852;
|
|
setp.lt.f32 %p133, %f962, 0f3B4D2E1C;
|
|
selp.f32 %f822, %f821, %f820, %p133;
|
|
fma.rn.f32 %f823, %f1050, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f125, 0f3F800000;
|
|
selp.f32 %f824, 0f3F7FFFFF, %f823, %p134;
|
|
mul.f32 %f825, %f125, 0f414EB852;
|
|
setp.lt.f32 %p135, %f125, 0f3B4D2E1C;
|
|
selp.f32 %f826, %f825, %f824, %p135;
|
|
fma.rn.f32 %f827, %f1053, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f126, 0f3F800000;
|
|
selp.f32 %f828, 0f3F7FFFFF, %f827, %p136;
|
|
mul.f32 %f829, %f126, 0f414EB852;
|
|
setp.lt.f32 %p137, %f126, 0f3B4D2E1C;
|
|
selp.f32 %f830, %f829, %f828, %p137;
|
|
min.f32 %f831, %f822, %f819;
|
|
mov.f32 %f832, 0f00000000;
|
|
max.f32 %f833, %f832, %f831;
|
|
mul.f32 %f834, %f833, 0f43800000;
|
|
cvt.rzi.u32.f32 %r297, %f834;
|
|
min.u32 %r298, %r297, 255;
|
|
min.f32 %f835, %f826, %f819;
|
|
max.f32 %f836, %f832, %f835;
|
|
mul.f32 %f837, %f836, 0f43800000;
|
|
cvt.rzi.u32.f32 %r299, %f837;
|
|
min.u32 %r300, %r299, 255;
|
|
min.f32 %f838, %f830, %f819;
|
|
max.f32 %f839, %f832, %f838;
|
|
mul.f32 %f840, %f839, 0f43800000;
|
|
cvt.rzi.u32.f32 %r301, %f840;
|
|
min.u32 %r302, %r301, 255;
|
|
shl.b64 %rd65, %rd101, 2;
|
|
add.s64 %rd66, %rd102, %rd65;
|
|
cvt.u16.u32 %rs15, %r302;
|
|
cvt.u16.u32 %rs16, %r300;
|
|
cvt.u16.u32 %rs17, %r298;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd66], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_110:
|
|
ld.const.u32 %r332, [params+104];
|
|
and.b32 %r303, %r332, 4;
|
|
setp.eq.s32 %p138, %r303, 0;
|
|
ld.const.u32 %r344, [params+108];
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
setp.eq.s32 %p139, %r344, 0;
|
|
ld.const.u64 %rd67, [params+224];
|
|
cvta.to.global.u64 %rd68, %rd67;
|
|
ld.const.u32 %r304, [params+216];
|
|
mad.lo.s32 %r305, %r304, %r6, %r5;
|
|
mul.wide.u32 %rd69, %r305, 8;
|
|
add.s64 %rd18, %rd68, %rd69;
|
|
@%p139 bra $L__BB0_113;
|
|
|
|
add.f32 %f986, %f307, %f307;
|
|
mul.f32 %f985, %f986, %f309;
|
|
add.f32 %f965, %f307, %f307;
|
|
mul.f32 %f964, %f965, %f310;
|
|
ld.global.v4.u16 {%rs26, %rs27, %rs28, %rs29}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f841, %rs26;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f842, %rs27;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f843, %rs28;}
|
|
|
|
// end inline asm
|
|
add.f32 %f844, %f985, %f841;
|
|
add.f32 %f845, %f964, %f842;
|
|
add.f32 %f846, %f87, %f843;
|
|
mov.f32 %f847, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs24, %f846;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs23, %f845;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs22, %f844;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f847;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs22, %rs23, %rs24, %rs25};
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_113:
|
|
add.f32 %f988, %f307, %f307;
|
|
mul.f32 %f987, %f988, %f309;
|
|
add.f32 %f967, %f307, %f307;
|
|
mul.f32 %f966, %f967, %f310;
|
|
mov.f32 %f851, 0f3F800000;
|
|
mov.u32 %r344, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f851;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f966;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f987;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs30, %rs31, %rs32, %rs33};
|
|
|
|
$L__BB0_114:
|
|
mul.f32 %f161, %f78, 0f3F000000;
|
|
mul.f32 %f162, %f161, %f309;
|
|
mul.f32 %f163, %f161, %f310;
|
|
mul.f32 %f164, %f161, %f311;
|
|
ld.const.u64 %rd70, [params+256];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r307, [params+248];
|
|
mad.lo.s32 %r308, %r307, %r6, %r5;
|
|
mul.wide.u32 %rd72, %r308, 8;
|
|
add.s64 %rd19, %rd71, %rd72;
|
|
setp.eq.s32 %p140, %r344, 0;
|
|
@%p140 bra $L__BB0_116;
|
|
|
|
ld.global.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f852, %rs41;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f853, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f854, %rs43;}
|
|
|
|
// end inline asm
|
|
add.f32 %f855, %f162, %f852;
|
|
add.f32 %f856, %f163, %f853;
|
|
add.f32 %f857, %f164, %f854;
|
|
mov.f32 %f858, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f857;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f856;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f855;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f858;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs37, %rs38, %rs39, %rs40};
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_116:
|
|
mov.f32 %f862, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f862;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f162;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs45, %rs46, %rs47, %rs48};
|
|
|
|
$L__BB0_117:
|
|
mov.f32 %f863, 0f34000000;
|
|
max.f32 %f864, %f161, %f863;
|
|
mul.f32 %f865, %f79, 0f3F000000;
|
|
div.rn.f32 %f866, %f865, %f864;
|
|
fma.rn.f32 %f165, %f866, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f867, %f80, 0f3F000000;
|
|
div.rn.f32 %f868, %f867, %f864;
|
|
fma.rn.f32 %f166, %f868, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f869, %f81, 0f3F000000;
|
|
div.rn.f32 %f870, %f869, %f864;
|
|
fma.rn.f32 %f167, %f870, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd73, [params+272];
|
|
cvta.to.global.u64 %rd74, %rd73;
|
|
ld.const.u32 %r309, [params+264];
|
|
mad.lo.s32 %r310, %r309, %r6, %r5;
|
|
mul.wide.u32 %rd75, %r310, 8;
|
|
add.s64 %rd20, %rd74, %rd75;
|
|
@%p140 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs56, %rs57, %rs58, %rs59}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f871, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f872, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f873, %rs58;}
|
|
|
|
// end inline asm
|
|
add.f32 %f874, %f165, %f871;
|
|
add.f32 %f875, %f165, %f872;
|
|
add.f32 %f876, %f165, %f873;
|
|
mov.f32 %f877, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f876;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f875;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f874;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f877;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs52, %rs53, %rs54, %rs55};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f881, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f881;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f165;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_120:
|
|
ld.const.u64 %rd76, [params+288];
|
|
cvta.to.global.u64 %rd77, %rd76;
|
|
ld.const.u32 %r311, [params+280];
|
|
mad.lo.s32 %r312, %r311, %r6, %r5;
|
|
mul.wide.u32 %rd78, %r312, 8;
|
|
add.s64 %rd21, %rd77, %rd78;
|
|
@%p140 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f882, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f883, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f884, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f885, %f166, %f882;
|
|
add.f32 %f886, %f166, %f883;
|
|
add.f32 %f887, %f166, %f884;
|
|
mov.f32 %f888, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f887;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f886;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f885;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f888;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f892, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f892;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f166;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd79, [params+304];
|
|
cvta.to.global.u64 %rd80, %rd79;
|
|
ld.const.u32 %r313, [params+296];
|
|
mad.lo.s32 %r314, %r313, %r6, %r5;
|
|
mul.wide.u32 %rd81, %r314, 8;
|
|
add.s64 %rd22, %rd80, %rd81;
|
|
@%p140 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f893, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f894, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f895, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f896, %f167, %f893;
|
|
add.f32 %f897, %f167, %f894;
|
|
add.f32 %f898, %f167, %f895;
|
|
mov.f32 %f899, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f898;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f897;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f896;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f899;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f903, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f903;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f167;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs90, %rs91, %rs92, %rs93};
|
|
|
|
$L__BB0_144:
|
|
ret;
|
|
|
|
}
|
|
|