199 lines
5.3 KiB
Plaintext
199 lines
5.3 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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.const .align 16 .b8 params[1184];
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.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
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.param .b32 __direct_callable__oxMain_param_0,
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.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
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)
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{
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.reg .pred %p<4>;
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.reg .b16 %rs<41>;
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.reg .f32 %f<104>;
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.reg .b32 %r<29>;
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.reg .b64 %rd<41>;
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ld.param.u32 %r3, [__direct_callable__oxMain_param_0];
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ld.param.f32 %f1, [__direct_callable__oxMain_param_1];
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ld.param.f32 %f2, [__direct_callable__oxMain_param_1+4];
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ld.const.u64 %rd4, [params+24];
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cvta.to.global.u64 %rd5, %rd4;
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mul.wide.u32 %rd6, %r3, 12;
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add.s64 %rd7, %rd5, %rd6;
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ld.global.s32 %rd1, [%rd7];
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ld.global.s32 %rd2, [%rd7+4];
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ld.global.s32 %rd3, [%rd7+8];
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ld.const.u32 %r1, [params+32];
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setp.gt.u32 %p1, %r1, %r3;
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@%p1 bra $L__BB0_4;
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bra.uni $L__BB0_1;
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$L__BB0_4:
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mov.f32 %f103, 0f3F800000;
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sub.f32 %f72, %f103, %f1;
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sub.f32 %f98, %f72, %f2;
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bra.uni $L__BB0_5;
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$L__BB0_1:
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sub.s32 %r4, %r3, %r1;
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ld.const.u64 %rd8, [params+48];
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cvta.to.global.u64 %rd9, %rd8;
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mul.wide.u32 %rd10, %r4, 4;
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add.s64 %rd11, %rd9, %rd10;
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ld.const.u64 %rd12, [params+40];
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cvta.to.global.u64 %rd13, %rd12;
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shl.b64 %rd14, %rd1, 3;
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add.s64 %rd15, %rd13, %rd14;
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ld.global.v2.f32 {%f28, %f29}, [%rd15];
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shl.b64 %rd16, %rd2, 3;
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add.s64 %rd17, %rd13, %rd16;
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ld.global.v2.f32 {%f32, %f33}, [%rd17];
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shl.b64 %rd18, %rd3, 3;
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add.s64 %rd19, %rd13, %rd18;
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ld.global.v2.f32 {%f36, %f37}, [%rd19];
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mov.f32 %f40, 0f3F800000;
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sub.f32 %f41, %f40, %f1;
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sub.f32 %f98, %f41, %f2;
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mul.f32 %f42, %f1, %f32;
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mul.f32 %f43, %f1, %f33;
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fma.rn.f32 %f44, %f98, %f28, %f42;
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fma.rn.f32 %f45, %f98, %f29, %f43;
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fma.rn.f32 %f4, %f2, %f36, %f44;
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fma.rn.f32 %f5, %f2, %f37, %f45;
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ld.global.u32 %r2, [%rd11];
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and.b32 %r5, %r2, -16384;
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setp.eq.s32 %p2, %r5, 16384;
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@%p2 bra $L__BB0_3;
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bra.uni $L__BB0_2;
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$L__BB0_3:
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add.s32 %r17, %r2, -16384;
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ld.const.u64 %rd28, [params+64];
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cvta.to.global.u64 %rd29, %rd28;
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mul.wide.u32 %rd30, %r17, 8;
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add.s64 %rd31, %rd29, %rd30;
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ld.global.u64 %rd32, [%rd31];
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tex.2d.v4.f32.f32 {%f56, %f57, %f58, %f59}, [%rd32, {%f4, %f5}];
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cvt.sat.f32.f32 %f60, %f56;
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mul.f32 %f61, %f60, 0f437F0000;
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cvt.rzi.s32.f32 %r18, %f61;
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cvt.sat.f32.f32 %f62, %f57;
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mul.f32 %f63, %f62, 0f437F0000;
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cvt.rzi.s32.f32 %r19, %f63;
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cvt.sat.f32.f32 %f64, %f58;
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mul.f32 %f65, %f64, 0f437F0000;
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cvt.rzi.s32.f32 %r20, %f65;
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shl.b32 %r21, %r19, 8;
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or.b32 %r22, %r21, %r18;
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shl.b32 %r23, %r20, 16;
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or.b32 %r24, %r22, %r23;
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not.b32 %r25, %r24;
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cvt.rn.f32.s32 %f103, %r25;
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bra.uni $L__BB0_6;
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$L__BB0_2:
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abs.f32 %f46, %f4;
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cvt.rmi.f32.f32 %f47, %f46;
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sub.f32 %f48, %f46, %f47;
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abs.f32 %f49, %f5;
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cvt.rmi.f32.f32 %f50, %f49;
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sub.f32 %f51, %f49, %f50;
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ld.const.u64 %rd20, [params+56];
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cvta.to.global.u64 %rd21, %rd20;
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shl.b32 %r6, %r2, 4;
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cvt.u64.u32 %rd22, %r6;
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and.b64 %rd23, %rd22, 1048560;
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add.s64 %rd24, %rd21, %rd23;
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ld.global.v2.u32 {%r7, %r8}, [%rd24];
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cvt.rn.f32.u32 %f52, %r7;
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mul.f32 %f53, %f48, %f52;
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cvt.rzi.u32.f32 %r11, %f53;
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cvt.rn.f32.u32 %f54, %r8;
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mul.f32 %f55, %f51, %f54;
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cvt.rzi.u32.f32 %r12, %f55;
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mad.lo.s32 %r13, %r7, %r12, %r11;
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cvt.u64.u32 %rd25, %r13;
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ld.global.u64 %rd26, [%rd24+8];
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add.s64 %rd27, %rd26, %rd25;
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ld.u8 %r14, [%rd27];
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shr.u32 %r15, %r2, 16;
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and.b32 %r16, %r15, %r14;
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setp.eq.s32 %p3, %r16, 0;
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selp.f32 %f103, 0f00000000, 0f3F800000, %p3;
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$L__BB0_5:
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cvt.u32.u64 %r26, %rd1;
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cvt.u32.u64 %r27, %rd2;
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cvt.u32.u64 %r28, %rd3;
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ld.const.u64 %rd33, [params+16];
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cvta.to.global.u64 %rd34, %rd33;
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mul.wide.s32 %rd35, %r26, 24;
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add.s64 %rd36, %rd34, %rd35;
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mul.wide.s32 %rd37, %r27, 24;
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add.s64 %rd38, %rd34, %rd37;
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mul.wide.s32 %rd39, %r28, 24;
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add.s64 %rd40, %rd34, %rd39;
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ld.global.f32 %f73, [%rd36+12];
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ld.global.f32 %f74, [%rd36+16];
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ld.global.f32 %f75, [%rd36+20];
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ld.global.f32 %f76, [%rd38+12];
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mul.f32 %f77, %f1, %f76;
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ld.global.f32 %f78, [%rd38+16];
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mul.f32 %f79, %f1, %f78;
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ld.global.f32 %f80, [%rd38+20];
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mul.f32 %f81, %f1, %f80;
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fma.rn.f32 %f82, %f98, %f73, %f77;
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fma.rn.f32 %f83, %f98, %f74, %f79;
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fma.rn.f32 %f84, %f98, %f75, %f81;
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ld.global.f32 %f85, [%rd40+12];
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ld.global.f32 %f86, [%rd40+16];
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ld.global.f32 %f87, [%rd40+20];
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fma.rn.f32 %f88, %f2, %f85, %f82;
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fma.rn.f32 %f89, %f2, %f86, %f83;
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fma.rn.f32 %f90, %f2, %f87, %f84;
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mul.f32 %f91, %f89, %f89;
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fma.rn.f32 %f92, %f88, %f88, %f91;
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fma.rn.f32 %f93, %f90, %f90, %f92;
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sqrt.rn.f32 %f94, %f93;
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rcp.rn.f32 %f95, %f94;
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mul.f32 %f102, %f90, %f95;
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mul.f32 %f101, %f89, %f95;
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mul.f32 %f100, %f88, %f95;
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$L__BB0_6:
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st.param.f32 [func_retval0+0], %f100;
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st.param.f32 [func_retval0+4], %f101;
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st.param.f32 [func_retval0+8], %f102;
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st.param.v4.b8 [func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
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st.param.f32 [func_retval0+16], %f25;
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st.param.f32 [func_retval0+20], %f26;
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st.param.f32 [func_retval0+24], %f103;
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st.param.v4.b8 [func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
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ret;
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}
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// .globl oxMain
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.visible .entry oxMain()
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{
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.reg .b64 %rd<2>;
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mov.u64 %rd1, __direct_callable__oxMain;
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// begin inline asm
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// end inline asm
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ret;
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}
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