2256 lines
60 KiB
Plaintext
2256 lines
60 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<155>;
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.reg .b16 %rs<172>;
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.reg .f32 %f<1189>;
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.reg .b32 %r<362>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<109>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r56), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r57), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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shl.b32 %r4, %r3, 1;
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ld.const.u64 %rd29, [params+400];
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cvta.to.global.u64 %rd30, %rd29;
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ld.const.u32 %r62, [params+392];
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mad.lo.s32 %r63, %r62, %r57, %r56;
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mul.wide.u32 %rd31, %r63, 4;
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add.s64 %rd2, %rd30, %rd31;
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ld.global.v2.u8 {%rs7, %rs171}, [%rd2];
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or.b16 %rs9, %rs7, %rs171;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs170, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs170, [%rd2+2];
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setp.eq.s16 %p8, %rs170, 0;
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mov.f32 %f1102, 0f00000000;
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mov.u16 %rs171, 0;
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mov.f32 %f1103, %f1102;
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mov.f32 %f1104, %f1102;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f237, %rs7;
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div.rn.f32 %f238, %f237, 0f437F0000;
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fma.rn.f32 %f239, %f238, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs171, 255;
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cvt.rn.f32.u16 %f240, %rs13;
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div.rn.f32 %f241, %f240, 0f437F0000;
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fma.rn.f32 %f242, %f241, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f243, %rs170;
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div.rn.f32 %f244, %f243, 0f437F0000;
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fma.rn.f32 %f245, %f244, 0f40000000, 0fBF800000;
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mul.f32 %f246, %f242, %f242;
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fma.rn.f32 %f247, %f239, %f239, %f246;
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fma.rn.f32 %f248, %f245, %f245, %f247;
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sqrt.rn.f32 %f249, %f248;
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rcp.rn.f32 %f250, %f249;
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mul.f32 %f1104, %f250, %f245;
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mul.f32 %f1103, %f250, %f242;
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mul.f32 %f1102, %f239, %f250;
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$L__BB0_4:
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ld.const.v2.u32 {%r64, %r65}, [params];
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add.s32 %r5, %r64, %r56;
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add.s32 %r6, %r65, %r57;
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setp.eq.f32 %p9, %f1102, 0f00000000;
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setp.eq.f32 %p10, %f1103, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1104, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_126;
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bra.uni $L__BB0_5;
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$L__BB0_126:
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ld.const.u32 %r53, [params+104];
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and.b32 %r315, %r53, 1;
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setp.eq.b32 %p144, %r315, 1;
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mov.pred %p145, 0;
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xor.pred %p146, %p144, %p145;
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not.pred %p147, %p146;
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@%p147 bra $L__BB0_128;
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ld.const.u64 %rd82, [params+144];
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cvta.to.global.u64 %rd83, %rd82;
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ld.const.u32 %r316, [params+136];
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mad.lo.s32 %r317, %r316, %r6, %r5;
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mul.wide.u32 %rd84, %r317, 4;
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add.s64 %rd85, %rd83, %rd84;
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mov.u16 %rs94, 0;
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st.global.v4.u8 [%rd85], {%rs94, %rs94, %rs94, %rs94};
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$L__BB0_128:
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and.b32 %r318, %r53, 4;
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setp.eq.s32 %p148, %r318, 0;
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ld.const.u32 %r361, [params+108];
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@%p148 bra $L__BB0_132;
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setp.eq.s32 %p149, %r361, 0;
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ld.const.u64 %rd86, [params+224];
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cvta.to.global.u64 %rd87, %rd86;
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ld.const.u32 %r319, [params+216];
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mad.lo.s32 %r320, %r319, %r6, %r5;
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mul.wide.u32 %rd88, %r320, 8;
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add.s64 %rd23, %rd87, %rd88;
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@%p149 bra $L__BB0_131;
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ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd23];
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// begin inline asm
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{ cvt.f32.f16 %f1011, %rs101;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1012, %rs102;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1013, %rs103;}
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// end inline asm
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add.f32 %f1014, %f1011, 0f00000000;
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add.f32 %f1015, %f1012, 0f00000000;
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add.f32 %f1016, %f1013, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs100, %f1016;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs99, %f1015;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs98, %f1014;}
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// end inline asm
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mov.u16 %rs105, 0;
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st.global.v4.u16 [%rd23], {%rs98, %rs99, %rs100, %rs105};
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bra.uni $L__BB0_132;
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$L__BB0_5:
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ld.const.u64 %rd32, [params+432];
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cvta.to.global.u64 %rd33, %rd32;
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ld.const.u32 %r68, [params+424];
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mad.lo.s32 %r69, %r68, %r57, %r56;
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mul.wide.u32 %rd34, %r69, 12;
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add.s64 %rd35, %rd33, %rd34;
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ld.global.f32 %f266, [%rd35];
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mul.f32 %f267, %f266, 0f3456BF95;
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ld.global.f32 %f268, [%rd35+4];
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mul.f32 %f269, %f268, 0f3456BF95;
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ld.global.f32 %f270, [%rd35+8];
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mul.f32 %f271, %f270, 0f3456BF95;
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abs.f32 %f272, %f1102;
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div.rn.f32 %f273, %f267, %f272;
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abs.f32 %f274, %f1103;
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div.rn.f32 %f275, %f269, %f274;
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abs.f32 %f276, %f1104;
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div.rn.f32 %f277, %f271, %f276;
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abs.f32 %f278, %f273;
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abs.f32 %f279, %f275;
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abs.f32 %f280, %f277;
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mov.f32 %f281, 0f38D1B717;
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max.f32 %f282, %f278, %f281;
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max.f32 %f283, %f279, %f281;
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max.f32 %f284, %f280, %f281;
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fma.rn.f32 %f10, %f1102, %f282, %f266;
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fma.rn.f32 %f11, %f1103, %f283, %f268;
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fma.rn.f32 %f12, %f1104, %f284, %f270;
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setp.gt.f32 %p14, %f272, %f276;
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neg.f32 %f285, %f1103;
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selp.f32 %f286, %f285, 0f00000000, %p14;
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mov.f32 %f1141, 0f00000000;
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neg.f32 %f287, %f1104;
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selp.f32 %f288, %f1102, %f287, %p14;
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selp.f32 %f289, 0f00000000, %f1103, %p14;
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mul.f32 %f290, %f288, %f288;
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fma.rn.f32 %f291, %f286, %f286, %f290;
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fma.rn.f32 %f292, %f289, %f289, %f291;
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sqrt.rn.f32 %f293, %f292;
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rcp.rn.f32 %f294, %f293;
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mul.f32 %f13, %f286, %f294;
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mul.f32 %f14, %f288, %f294;
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mul.f32 %f15, %f289, %f294;
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ld.const.u64 %rd36, [params+128];
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cvta.to.global.u64 %rd37, %rd36;
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ld.const.u32 %r70, [params+120];
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mad.lo.s32 %r71, %r70, %r57, %r56;
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mul.wide.u32 %rd38, %r71, 4;
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add.s64 %rd3, %rd37, %rd38;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1142, %f1141;
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mov.f32 %f1143, %f1141;
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mov.f32 %f1144, %f1141;
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mov.f32 %f1145, %f1141;
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mov.f32 %f1146, %f1141;
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mov.f32 %f1147, %f1141;
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mov.f32 %f1148, %f1141;
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mov.f32 %f1149, %f1141;
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mov.f32 %f1150, %f1141;
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mov.f32 %f1151, %f1141;
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mov.f32 %f1152, %f1141;
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mov.f32 %f1153, %f1141;
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mov.f32 %f1154, %f1141;
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mov.f32 %f1155, %f1141;
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@%p15 bra $L__BB0_36;
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ld.const.u32 %r7, [params+588];
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cvt.rn.f32.s32 %f310, %r4;
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rcp.rn.f32 %f16, %f310;
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ld.global.u32 %r352, [%rd3];
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mul.f32 %f17, %f10, 0f3456BF95;
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mul.f32 %f18, %f11, 0f3456BF95;
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mul.f32 %f19, %f12, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f311, %f1102, %f14;
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mul.f32 %f312, %f1103, %f13;
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sub.f32 %f20, %f312, %f311;
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mul.f32 %f313, %f1104, %f13;
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mul.f32 %f314, %f1102, %f15;
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sub.f32 %f21, %f314, %f313;
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mul.f32 %f315, %f1103, %f15;
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mul.f32 %f316, %f1104, %f14;
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sub.f32 %f22, %f316, %f315;
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mov.u32 %r72, 0;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd39, __cudart_i2opi_f;
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abs.f32 %f381, %f17;
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abs.f32 %f382, %f18;
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max.f32 %f383, %f381, %f382;
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abs.f32 %f384, %f19;
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max.f32 %f385, %f383, %f384;
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mov.u32 %r349, %r72;
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$L__BB0_7:
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mov.u32 %r351, %r72;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1057, %r349;
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mad.lo.s32 %r74, %r352, 1664525, 1013904223;
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and.b32 %r75, %r74, 16777215;
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cvt.rn.f32.u32 %f317, %r75;
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fma.rn.f32 %f318, %f317, 0f33800000, %f1057;
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mul.f32 %f319, %f16, %f318;
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mad.lo.s32 %r352, %r74, 1664525, 1013904223;
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and.b32 %r76, %r352, 16777215;
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cvt.rn.f32.u32 %f320, %r76;
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cvt.rn.f32.s32 %f321, %r351;
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fma.rn.f32 %f322, %f320, 0f33800000, %f321;
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mul.f32 %f323, %f16, %f322;
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fma.rn.f32 %f324, %f16, %f318, %f319;
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mov.f32 %f325, 0f3F800000;
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sub.f32 %f54, %f325, %f324;
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mul.f32 %f326, %f54, %f54;
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sub.f32 %f327, %f325, %f326;
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mov.f32 %f328, 0f00000000;
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max.f32 %f329, %f328, %f327;
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sqrt.rn.f32 %f55, %f329;
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mul.f32 %f56, %f323, 0f40C90FDB;
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mul.f32 %f330, %f56, 0f3F22F983;
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cvt.rni.s32.f32 %r356, %f330;
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cvt.rn.f32.s32 %f331, %r356;
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mov.f32 %f332, 0fBFC90FDA;
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fma.rn.f32 %f333, %f331, %f332, %f56;
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mov.f32 %f334, 0fB3A22168;
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fma.rn.f32 %f335, %f331, %f334, %f333;
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mov.f32 %f336, 0fA7C234C5;
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fma.rn.f32 %f1138, %f331, %f336, %f335;
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abs.f32 %f58, %f56;
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setp.ltu.f32 %p16, %f58, 0f47CE4780;
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mov.f32 %f1135, %f1138;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f58, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f339, 0f00000000;
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mul.rn.f32 %f1135, %f56, %f339;
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mov.u32 %r356, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r15, %f56;
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bfe.u32 %r78, %r15, 23, 8;
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mov.u64 %rd106, 0;
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mov.u32 %r353, 0;
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mov.u64 %rd104, %rd1;
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mov.u64 %rd105, %rd39;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r332, %f56;
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shl.b32 %r331, %r332, 8;
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or.b32 %r330, %r331, -2147483648;
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ld.global.nc.u32 %r80, [%rd105];
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mad.wide.u32 %rd41, %r80, %r330, %rd106;
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shr.u64 %rd106, %rd41, 32;
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st.local.u32 [%rd104], %rd41;
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add.s64 %rd105, %rd105, 4;
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add.s64 %rd104, %rd104, 4;
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add.s32 %r353, %r353, 1;
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setp.ne.s32 %p18, %r353, 6;
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@%p18 bra $L__BB0_11;
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add.s32 %r337, %r78, -128;
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mov.b32 %r336, %f56;
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bfe.u32 %r335, %r336, 23, 8;
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add.s32 %r334, %r335, -128;
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shr.u32 %r333, %r334, 5;
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st.local.u32 [%rd5], %rd106;
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mov.u32 %r82, 6;
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sub.s32 %r83, %r82, %r333;
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mul.wide.s32 %rd42, %r83, 4;
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add.s64 %rd43, %rd1, %rd42;
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ld.local.u32 %r354, [%rd43];
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ld.local.u32 %r355, [%rd43+-4];
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and.b32 %r24, %r334, 31;
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setp.eq.s32 %p19, %r24, 0;
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@%p19 bra $L__BB0_14;
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mov.b32 %r345, %f56;
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bfe.u32 %r344, %r345, 23, 8;
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add.s32 %r343, %r344, -128;
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shr.u32 %r342, %r343, 5;
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mov.u32 %r341, 4;
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sub.s32 %r340, %r341, %r342;
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mov.u32 %r84, 32;
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sub.s32 %r85, %r84, %r24;
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shr.u32 %r86, %r355, %r85;
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shl.b32 %r87, %r354, %r24;
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add.s32 %r354, %r86, %r87;
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mul.wide.s32 %rd44, %r340, 4;
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add.s64 %rd45, %rd1, %rd44;
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ld.local.u32 %r88, [%rd45];
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shr.u32 %r89, %r88, %r85;
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shl.b32 %r90, %r355, %r24;
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add.s32 %r355, %r89, %r90;
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$L__BB0_14:
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mov.b32 %r338, %f56;
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and.b32 %r91, %r338, -2147483648;
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shr.u32 %r92, %r355, 30;
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shl.b32 %r93, %r354, 2;
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or.b32 %r94, %r92, %r93;
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shr.u32 %r95, %r94, 31;
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shr.u32 %r96, %r354, 30;
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add.s32 %r97, %r95, %r96;
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neg.s32 %r98, %r97;
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setp.eq.s32 %p20, %r91, 0;
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selp.b32 %r356, %r97, %r98, %p20;
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setp.ne.s32 %p21, %r95, 0;
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xor.b32 %r99, %r91, -2147483648;
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selp.b32 %r100, %r99, %r91, %p21;
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selp.b32 %r101, -1, 0, %p21;
|
|
xor.b32 %r102, %r94, %r101;
|
|
shl.b32 %r103, %r355, 2;
|
|
xor.b32 %r104, %r103, %r101;
|
|
cvt.u64.u32 %rd46, %r102;
|
|
cvt.u64.u32 %rd47, %r104;
|
|
bfi.b64 %rd48, %rd46, %rd47, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd48;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f337, %fd2;
|
|
setp.eq.s32 %p22, %r100, 0;
|
|
neg.f32 %f338, %f337;
|
|
selp.f32 %f1135, %f337, %f338, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r31, %r356, 1;
|
|
and.b32 %r32, %r31, 1;
|
|
setp.eq.s32 %p23, %r32, 0;
|
|
selp.f32 %f62, %f1135, 0f3F800000, %p23;
|
|
mul.rn.f32 %f63, %f1135, %f1135;
|
|
mov.f32 %f1136, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f341, 0fBAB607ED;
|
|
mov.f32 %f342, 0f37CBAC00;
|
|
fma.rn.f32 %f1136, %f342, %f63, %f341;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f343, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f344, %f1136, %f63, %f343;
|
|
selp.f32 %f345, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f346, %f344, %f63, %f345;
|
|
mov.f32 %f347, 0f00000000;
|
|
fma.rn.f32 %f348, %f63, %f62, %f347;
|
|
fma.rn.f32 %f1137, %f346, %f348, %f62;
|
|
and.b32 %r106, %r31, 2;
|
|
setp.eq.s32 %p25, %r106, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f350, 0fBF800000;
|
|
fma.rn.f32 %f1137, %f1137, %f350, %f347;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1056, %f56, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r359, %f1056;
|
|
setp.ltu.f32 %p154, %f58, 0f47CE4780;
|
|
@%p154 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f58, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f353, 0f00000000;
|
|
mul.rn.f32 %f1138, %f56, %f353;
|
|
mov.u32 %r359, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r33, %f56;
|
|
bfe.u32 %r107, %r33, 23, 8;
|
|
add.s32 %r34, %r107, -128;
|
|
shl.b32 %r108, %r33, 8;
|
|
or.b32 %r35, %r108, -2147483648;
|
|
shr.u32 %r36, %r34, 5;
|
|
mov.u64 %rd107, 0;
|
|
mov.u64 %rd108, %rd107;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd51, %rd107, 2;
|
|
mov.u64 %rd52, __cudart_i2opi_f;
|
|
add.s64 %rd53, %rd52, %rd51;
|
|
ld.global.nc.u32 %r109, [%rd53];
|
|
mad.wide.u32 %rd54, %r109, %r35, %rd108;
|
|
shr.u64 %rd108, %rd54, 32;
|
|
add.s64 %rd55, %rd1, %rd51;
|
|
st.local.u32 [%rd55], %rd54;
|
|
cvt.u32.u64 %r110, %rd107;
|
|
add.s32 %r111, %r110, 1;
|
|
cvt.s64.s32 %rd107, %r111;
|
|
setp.ne.s32 %p28, %r111, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd108;
|
|
mov.u32 %r112, 4;
|
|
sub.s32 %r37, %r112, %r36;
|
|
mov.u32 %r113, 6;
|
|
sub.s32 %r114, %r113, %r36;
|
|
mul.wide.s32 %rd56, %r114, 4;
|
|
add.s64 %rd57, %rd1, %rd56;
|
|
ld.local.u32 %r357, [%rd57];
|
|
ld.local.u32 %r358, [%rd57+-4];
|
|
and.b32 %r40, %r34, 31;
|
|
setp.eq.s32 %p29, %r40, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r115, 32;
|
|
sub.s32 %r116, %r115, %r40;
|
|
shr.u32 %r117, %r358, %r116;
|
|
shl.b32 %r118, %r357, %r40;
|
|
add.s32 %r357, %r117, %r118;
|
|
mul.wide.s32 %rd58, %r37, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r119, [%rd59];
|
|
shr.u32 %r120, %r119, %r116;
|
|
shl.b32 %r121, %r358, %r40;
|
|
add.s32 %r358, %r120, %r121;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r122, %r33, -2147483648;
|
|
shr.u32 %r123, %r358, 30;
|
|
shl.b32 %r124, %r357, 2;
|
|
or.b32 %r125, %r123, %r124;
|
|
shr.u32 %r126, %r125, 31;
|
|
shr.u32 %r127, %r357, 30;
|
|
add.s32 %r128, %r126, %r127;
|
|
neg.s32 %r129, %r128;
|
|
setp.eq.s32 %p30, %r122, 0;
|
|
selp.b32 %r359, %r128, %r129, %p30;
|
|
setp.ne.s32 %p31, %r126, 0;
|
|
xor.b32 %r130, %r122, -2147483648;
|
|
selp.b32 %r131, %r130, %r122, %p31;
|
|
selp.b32 %r132, -1, 0, %p31;
|
|
xor.b32 %r133, %r125, %r132;
|
|
shl.b32 %r134, %r358, 2;
|
|
xor.b32 %r135, %r134, %r132;
|
|
cvt.u64.u32 %rd60, %r133;
|
|
cvt.u64.u32 %rd61, %r135;
|
|
bfi.b64 %rd62, %rd60, %rd61, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd62;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f351, %fd4;
|
|
setp.eq.s32 %p32, %r131, 0;
|
|
neg.f32 %f352, %f351;
|
|
selp.f32 %f1138, %f351, %f352, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f72, %f55, %f1137;
|
|
and.b32 %r47, %r359, 1;
|
|
setp.eq.s32 %p33, %r47, 0;
|
|
mul.rn.f32 %f74, %f1138, %f1138;
|
|
mov.f32 %f1139, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f355, 0fBAB607ED;
|
|
mov.f32 %f356, 0f37CBAC00;
|
|
fma.rn.f32 %f1139, %f356, %f74, %f355;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1058, %f1138, 0f3F800000, %p33;
|
|
selp.f32 %f357, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f358, %f1139, %f74, %f357;
|
|
selp.f32 %f359, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f360, %f358, %f74, %f359;
|
|
mov.f32 %f361, 0f00000000;
|
|
fma.rn.f32 %f362, %f74, %f1058, %f361;
|
|
fma.rn.f32 %f1140, %f360, %f362, %f1058;
|
|
and.b32 %r137, %r359, 2;
|
|
setp.eq.s32 %p35, %r137, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f364, 0fBF800000;
|
|
fma.rn.f32 %f1140, %f1140, %f364, %f361;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f365, %f55, %f1140;
|
|
mul.f32 %f366, %f13, %f365;
|
|
mul.f32 %f367, %f14, %f365;
|
|
mul.f32 %f368, %f15, %f365;
|
|
fma.rn.f32 %f369, %f22, %f72, %f366;
|
|
fma.rn.f32 %f370, %f21, %f72, %f367;
|
|
fma.rn.f32 %f371, %f20, %f72, %f368;
|
|
fma.rn.f32 %f80, %f1102, %f54, %f369;
|
|
fma.rn.f32 %f81, %f1103, %f54, %f370;
|
|
fma.rn.f32 %f82, %f1104, %f54, %f371;
|
|
setp.leu.f32 %p36, %f81, 0f00000000;
|
|
setp.ne.s32 %p37, %r7, 0;
|
|
and.pred %p38, %p37, %p36;
|
|
@%p38 bra $L__BB0_34;
|
|
|
|
mov.f32 %f386, 0f38D1B717;
|
|
max.f32 %f378, %f385, %f386;
|
|
mov.f32 %f379, 0f6C4ECB8F;
|
|
mov.f32 %f380, 0f00000000;
|
|
mov.u32 %r174, 2;
|
|
mov.u32 %r175, 1;
|
|
mov.u32 %r176, 3;
|
|
mov.u32 %r179, 1065353216;
|
|
mov.u32 %r208, 0;
|
|
// begin inline asm
|
|
call(%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169),_optix_trace_typed_32,(%r208,%rd4,%f10,%f11,%f12,%f80,%f81,%f82,%f378,%f379,%f380,%r175,%r208,%r175,%r174,%r175,%r176,%r179,%r179,%r179,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208);
|
|
// end inline asm
|
|
mov.b32 %f387, %r138;
|
|
mov.b32 %f388, %r139;
|
|
mov.b32 %f389, %r140;
|
|
mul.f32 %f390, %f1103, %f81;
|
|
fma.rn.f32 %f391, %f1102, %f80, %f390;
|
|
fma.rn.f32 %f392, %f1104, %f82, %f391;
|
|
fma.rn.f32 %f1147, %f80, %f387, %f1147;
|
|
fma.rn.f32 %f1148, %f80, %f388, %f1148;
|
|
fma.rn.f32 %f1149, %f80, %f389, %f1149;
|
|
fma.rn.f32 %f1144, %f81, %f387, %f1144;
|
|
fma.rn.f32 %f1145, %f81, %f388, %f1145;
|
|
fma.rn.f32 %f1146, %f81, %f389, %f1146;
|
|
fma.rn.f32 %f1141, %f82, %f387, %f1141;
|
|
fma.rn.f32 %f1142, %f82, %f388, %f1142;
|
|
fma.rn.f32 %f1143, %f82, %f389, %f1143;
|
|
add.f32 %f1150, %f1150, %f387;
|
|
add.f32 %f1151, %f1151, %f388;
|
|
add.f32 %f1152, %f1152, %f389;
|
|
cvt.sat.f32.f32 %f393, %f392;
|
|
fma.rn.f32 %f1153, %f393, %f387, %f1153;
|
|
fma.rn.f32 %f1154, %f393, %f388, %f1154;
|
|
fma.rn.f32 %f1155, %f393, %f389, %f1155;
|
|
|
|
$L__BB0_34:
|
|
add.s32 %r351, %r351, 1;
|
|
setp.lt.s32 %p39, %r351, %r4;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r349, %r349, 1;
|
|
setp.lt.s32 %p40, %r349, %r4;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_36:
|
|
mul.lo.s32 %r209, %r4, %r4;
|
|
cvt.rn.f32.s32 %f394, %r209;
|
|
rcp.rn.f32 %f395, %f394;
|
|
mul.f32 %f396, %f395, %f1153;
|
|
mul.f32 %f397, %f395, %f1154;
|
|
mul.f32 %f398, %f395, %f1155;
|
|
mul.f32 %f128, %f395, %f1150;
|
|
mul.f32 %f129, %f395, %f1151;
|
|
mul.f32 %f130, %f395, %f1152;
|
|
mul.f32 %f131, %f395, %f1147;
|
|
mul.f32 %f132, %f395, %f1148;
|
|
mul.f32 %f133, %f395, %f1149;
|
|
mul.f32 %f134, %f395, %f1144;
|
|
mul.f32 %f135, %f395, %f1145;
|
|
mul.f32 %f136, %f395, %f1146;
|
|
mul.f32 %f137, %f395, %f1141;
|
|
mul.f32 %f138, %f395, %f1142;
|
|
mul.f32 %f139, %f395, %f1143;
|
|
fma.rn.f32 %f399, %f395, %f1153, %f396;
|
|
fma.rn.f32 %f400, %f395, %f1154, %f397;
|
|
fma.rn.f32 %f401, %f395, %f1155, %f398;
|
|
ld.const.v4.f32 {%f402, %f403, %f404, %f405}, [params+576];
|
|
mul.f32 %f143, %f399, %f402;
|
|
mul.f32 %f144, %f400, %f403;
|
|
mul.f32 %f145, %f401, %f404;
|
|
ld.const.u32 %r50, [params+104];
|
|
and.b32 %r210, %r50, 1;
|
|
setp.eq.b32 %p41, %r210, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_110;
|
|
|
|
mov.f32 %f407, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f408, %f407;
|
|
add.f32 %f409, %f408, %f408;
|
|
mov.f32 %f410, 0f3EE66666;
|
|
sub.f32 %f411, %f410, %f409;
|
|
abs.f32 %f146, %f411;
|
|
abs.f32 %f147, %f143;
|
|
setp.lt.f32 %p45, %f147, 0f00800000;
|
|
mul.f32 %f412, %f147, 0f4B800000;
|
|
selp.f32 %f413, %f412, %f147, %p45;
|
|
selp.f32 %f414, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r211, %f413;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f415, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f416, %r214;
|
|
add.f32 %f417, %f414, %f416;
|
|
setp.gt.f32 %p46, %f415, 0f3FB504F3;
|
|
mul.f32 %f418, %f415, 0f3F000000;
|
|
add.f32 %f419, %f417, 0f3F800000;
|
|
selp.f32 %f420, %f419, %f417, %p46;
|
|
selp.f32 %f421, %f418, %f415, %p46;
|
|
add.f32 %f422, %f421, 0fBF800000;
|
|
add.f32 %f423, %f421, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f424, %f423;
|
|
add.f32 %f425, %f422, %f422;
|
|
mul.f32 %f426, %f425, %f424;
|
|
mul.f32 %f427, %f426, %f426;
|
|
mov.f32 %f428, 0f3C4CAF63;
|
|
mov.f32 %f429, 0f3B18F0FE;
|
|
fma.rn.f32 %f430, %f429, %f427, %f428;
|
|
mov.f32 %f431, 0f3DAAAABD;
|
|
fma.rn.f32 %f432, %f430, %f427, %f431;
|
|
mul.rn.f32 %f433, %f432, %f427;
|
|
mul.rn.f32 %f434, %f433, %f426;
|
|
sub.f32 %f435, %f422, %f426;
|
|
add.f32 %f436, %f435, %f435;
|
|
neg.f32 %f437, %f426;
|
|
fma.rn.f32 %f438, %f437, %f422, %f436;
|
|
mul.rn.f32 %f439, %f424, %f438;
|
|
add.f32 %f440, %f434, %f426;
|
|
sub.f32 %f441, %f426, %f440;
|
|
add.f32 %f442, %f434, %f441;
|
|
add.f32 %f443, %f439, %f442;
|
|
add.f32 %f444, %f440, %f443;
|
|
sub.f32 %f445, %f440, %f444;
|
|
add.f32 %f446, %f443, %f445;
|
|
mov.f32 %f447, 0f3F317200;
|
|
mul.rn.f32 %f448, %f420, %f447;
|
|
mov.f32 %f449, 0f35BFBE8E;
|
|
mul.rn.f32 %f450, %f420, %f449;
|
|
add.f32 %f451, %f448, %f444;
|
|
sub.f32 %f452, %f448, %f451;
|
|
add.f32 %f453, %f444, %f452;
|
|
add.f32 %f454, %f446, %f453;
|
|
add.f32 %f455, %f450, %f454;
|
|
add.f32 %f456, %f451, %f455;
|
|
sub.f32 %f457, %f451, %f456;
|
|
add.f32 %f458, %f455, %f457;
|
|
mul.rn.f32 %f459, %f410, %f456;
|
|
neg.f32 %f460, %f459;
|
|
fma.rn.f32 %f461, %f410, %f456, %f460;
|
|
fma.rn.f32 %f462, %f410, %f458, %f461;
|
|
mov.f32 %f463, 0f00000000;
|
|
fma.rn.f32 %f464, %f463, %f456, %f462;
|
|
add.rn.f32 %f465, %f459, %f464;
|
|
neg.f32 %f466, %f465;
|
|
add.rn.f32 %f467, %f459, %f466;
|
|
add.rn.f32 %f468, %f467, %f464;
|
|
mov.b32 %r215, %f465;
|
|
setp.eq.s32 %p47, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f469, %r216;
|
|
add.f32 %f470, %f468, 0f37000000;
|
|
selp.f32 %f148, %f470, %f468, %p47;
|
|
selp.f32 %f471, %f469, %f465, %p47;
|
|
mov.f32 %f472, 0f3FB8AA3B;
|
|
mul.rn.f32 %f473, %f471, %f472;
|
|
cvt.rzi.f32.f32 %f474, %f473;
|
|
abs.f32 %f475, %f474;
|
|
setp.gt.f32 %p48, %f475, 0f42FC0000;
|
|
mov.b32 %r217, %f474;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f476, %r219;
|
|
selp.f32 %f477, %f476, %f474, %p48;
|
|
mov.f32 %f478, 0fBF317218;
|
|
fma.rn.f32 %f479, %f477, %f478, %f471;
|
|
mov.f32 %f480, 0f3102E308;
|
|
fma.rn.f32 %f481, %f477, %f480, %f479;
|
|
mul.f32 %f482, %f481, 0f3FB8AA3B;
|
|
add.f32 %f483, %f477, 0f4B40007F;
|
|
mov.b32 %r220, %f483;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f484, %r221;
|
|
ex2.approx.ftz.f32 %f485, %f482;
|
|
mul.f32 %f149, %f485, %f484;
|
|
setp.eq.f32 %p49, %f149, 0f7F800000;
|
|
mov.f32 %f1171, 0f7F800000;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1171, %f149, %f148, %f149;
|
|
|
|
$L__BB0_39:
|
|
setp.lt.f32 %p50, %f143, 0f00000000;
|
|
setp.eq.f32 %p51, %f146, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f143, 0f00000000;
|
|
@%p52 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f490, %f143, %f143;
|
|
selp.f32 %f1173, %f490, 0f00000000, %p51;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_131:
|
|
mov.f32 %f1019, 0f00000000;
|
|
mov.u32 %r361, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f1019;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f1019;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f1019;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs109, 0;
|
|
st.global.v4.u16 [%rd23], {%rs106, %rs107, %rs108, %rs109};
|
|
|
|
$L__BB0_132:
|
|
ld.const.u64 %rd89, [params+256];
|
|
cvta.to.global.u64 %rd90, %rd89;
|
|
ld.const.u32 %r322, [params+248];
|
|
mad.lo.s32 %r323, %r322, %r6, %r5;
|
|
mul.wide.u32 %rd91, %r323, 8;
|
|
add.s64 %rd24, %rd90, %rd91;
|
|
setp.eq.s32 %p150, %r361, 0;
|
|
@%p150 bra $L__BB0_134;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1020, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1021, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1022, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1023, %f1020, 0f00000000;
|
|
add.f32 %f1024, %f1021, 0f00000000;
|
|
add.f32 %f1025, %f1022, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1025;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1024;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1023;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs120, 0;
|
|
st.global.v4.u16 [%rd24], {%rs113, %rs114, %rs115, %rs120};
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_134:
|
|
mov.f32 %f1028, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1028;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1028;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1028;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs124, 0;
|
|
st.global.v4.u16 [%rd24], {%rs121, %rs122, %rs123, %rs124};
|
|
|
|
$L__BB0_135:
|
|
ld.const.u64 %rd92, [params+272];
|
|
cvta.to.global.u64 %rd93, %rd92;
|
|
ld.const.u32 %r324, [params+264];
|
|
mad.lo.s32 %r325, %r324, %r6, %r5;
|
|
mul.wide.u32 %rd94, %r325, 8;
|
|
add.s64 %rd25, %rd93, %rd94;
|
|
@%p150 bra $L__BB0_137;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1029, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1030, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1031, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1032, %f1029, 0f00000000;
|
|
add.f32 %f1033, %f1030, 0f00000000;
|
|
add.f32 %f1034, %f1031, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1034;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1033;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1032;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs135, 0;
|
|
st.global.v4.u16 [%rd25], {%rs128, %rs129, %rs130, %rs135};
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_137:
|
|
mov.f32 %f1037, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1037;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs139, 0;
|
|
st.global.v4.u16 [%rd25], {%rs136, %rs137, %rs138, %rs139};
|
|
|
|
$L__BB0_138:
|
|
ld.const.u64 %rd95, [params+288];
|
|
cvta.to.global.u64 %rd96, %rd95;
|
|
ld.const.u32 %r326, [params+280];
|
|
mad.lo.s32 %r327, %r326, %r6, %r5;
|
|
mul.wide.u32 %rd97, %r327, 8;
|
|
add.s64 %rd26, %rd96, %rd97;
|
|
@%p150 bra $L__BB0_140;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1038, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1039, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1040, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1041, %f1038, 0f00000000;
|
|
add.f32 %f1042, %f1039, 0f00000000;
|
|
add.f32 %f1043, %f1040, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1043;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1042;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1041;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs150, 0;
|
|
st.global.v4.u16 [%rd26], {%rs143, %rs144, %rs145, %rs150};
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_140:
|
|
mov.f32 %f1046, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1046;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1046;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1046;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs154, 0;
|
|
st.global.v4.u16 [%rd26], {%rs151, %rs152, %rs153, %rs154};
|
|
|
|
$L__BB0_141:
|
|
ld.const.u64 %rd98, [params+304];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r328, [params+296];
|
|
mad.lo.s32 %r329, %r328, %r6, %r5;
|
|
mul.wide.u32 %rd100, %r329, 8;
|
|
add.s64 %rd27, %rd99, %rd100;
|
|
@%p150 bra $L__BB0_143;
|
|
|
|
ld.global.v4.u16 {%rs161, %rs162, %rs163, %rs164}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1047, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1048, %rs162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1049, %rs163;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1050, %f1047, 0f00000000;
|
|
add.f32 %f1051, %f1048, 0f00000000;
|
|
add.f32 %f1052, %f1049, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1051;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1050;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs165, 0;
|
|
st.global.v4.u16 [%rd27], {%rs158, %rs159, %rs160, %rs165};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_143:
|
|
mov.f32 %f1055, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f1055;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1055;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1055;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs169, 0;
|
|
st.global.v4.u16 [%rd27], {%rs166, %rs167, %rs168, %rs169};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r222, %f1171;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f486, %r223;
|
|
selp.f32 %f1173, %f486, %f1171, %p1;
|
|
setp.geu.f32 %p53, %f143, 0f00000000;
|
|
@%p53 bra $L__BB0_44;
|
|
|
|
mov.f32 %f487, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f488, %f487;
|
|
setp.eq.f32 %p54, %f488, 0f3EE66666;
|
|
@%p54 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1173, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
add.f32 %f491, %f147, 0f3EE66666;
|
|
mov.b32 %r224, %f491;
|
|
setp.lt.s32 %p56, %r224, 2139095040;
|
|
@%p56 bra $L__BB0_49;
|
|
|
|
setp.gtu.f32 %p57, %f147, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1173, %f143, 0f3EE66666;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
setp.neu.f32 %p58, %f147, 0f7F800000;
|
|
@%p58 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1173, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
setp.eq.f32 %p59, %f143, 0f3F800000;
|
|
selp.f32 %f158, 0f3F800000, %f1173, %p59;
|
|
abs.f32 %f159, %f144;
|
|
setp.lt.f32 %p60, %f159, 0f00800000;
|
|
mul.f32 %f493, %f159, 0f4B800000;
|
|
selp.f32 %f494, %f493, %f159, %p60;
|
|
selp.f32 %f495, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r225, %f494;
|
|
and.b32 %r226, %r225, 8388607;
|
|
or.b32 %r227, %r226, 1065353216;
|
|
mov.b32 %f496, %r227;
|
|
shr.u32 %r228, %r225, 23;
|
|
cvt.rn.f32.u32 %f497, %r228;
|
|
add.f32 %f498, %f495, %f497;
|
|
setp.gt.f32 %p61, %f496, 0f3FB504F3;
|
|
mul.f32 %f499, %f496, 0f3F000000;
|
|
add.f32 %f500, %f498, 0f3F800000;
|
|
selp.f32 %f501, %f500, %f498, %p61;
|
|
selp.f32 %f502, %f499, %f496, %p61;
|
|
add.f32 %f503, %f502, 0fBF800000;
|
|
add.f32 %f504, %f502, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f505, %f504;
|
|
add.f32 %f506, %f503, %f503;
|
|
mul.f32 %f507, %f506, %f505;
|
|
mul.f32 %f508, %f507, %f507;
|
|
mov.f32 %f509, 0f3C4CAF63;
|
|
mov.f32 %f510, 0f3B18F0FE;
|
|
fma.rn.f32 %f511, %f510, %f508, %f509;
|
|
mov.f32 %f512, 0f3DAAAABD;
|
|
fma.rn.f32 %f513, %f511, %f508, %f512;
|
|
mul.rn.f32 %f514, %f513, %f508;
|
|
mul.rn.f32 %f515, %f514, %f507;
|
|
sub.f32 %f516, %f503, %f507;
|
|
add.f32 %f517, %f516, %f516;
|
|
neg.f32 %f518, %f507;
|
|
fma.rn.f32 %f519, %f518, %f503, %f517;
|
|
mul.rn.f32 %f520, %f505, %f519;
|
|
add.f32 %f521, %f515, %f507;
|
|
sub.f32 %f522, %f507, %f521;
|
|
add.f32 %f523, %f515, %f522;
|
|
add.f32 %f524, %f520, %f523;
|
|
add.f32 %f525, %f521, %f524;
|
|
sub.f32 %f526, %f521, %f525;
|
|
add.f32 %f527, %f524, %f526;
|
|
mov.f32 %f528, 0f3F317200;
|
|
mul.rn.f32 %f529, %f501, %f528;
|
|
mov.f32 %f530, 0f35BFBE8E;
|
|
mul.rn.f32 %f531, %f501, %f530;
|
|
add.f32 %f532, %f529, %f525;
|
|
sub.f32 %f533, %f529, %f532;
|
|
add.f32 %f534, %f525, %f533;
|
|
add.f32 %f535, %f527, %f534;
|
|
add.f32 %f536, %f531, %f535;
|
|
add.f32 %f537, %f532, %f536;
|
|
sub.f32 %f538, %f532, %f537;
|
|
add.f32 %f539, %f536, %f538;
|
|
mov.f32 %f540, 0f3EE66666;
|
|
mul.rn.f32 %f541, %f540, %f537;
|
|
neg.f32 %f542, %f541;
|
|
fma.rn.f32 %f543, %f540, %f537, %f542;
|
|
fma.rn.f32 %f544, %f540, %f539, %f543;
|
|
mov.f32 %f545, 0f00000000;
|
|
fma.rn.f32 %f546, %f545, %f537, %f544;
|
|
add.rn.f32 %f547, %f541, %f546;
|
|
neg.f32 %f548, %f547;
|
|
add.rn.f32 %f549, %f541, %f548;
|
|
add.rn.f32 %f550, %f549, %f546;
|
|
mov.b32 %r229, %f547;
|
|
setp.eq.s32 %p62, %r229, 1118925336;
|
|
add.s32 %r230, %r229, -1;
|
|
mov.b32 %f551, %r230;
|
|
add.f32 %f552, %f550, 0f37000000;
|
|
selp.f32 %f160, %f552, %f550, %p62;
|
|
selp.f32 %f553, %f551, %f547, %p62;
|
|
mov.f32 %f554, 0f3FB8AA3B;
|
|
mul.rn.f32 %f555, %f553, %f554;
|
|
cvt.rzi.f32.f32 %f556, %f555;
|
|
abs.f32 %f557, %f556;
|
|
setp.gt.f32 %p63, %f557, 0f42FC0000;
|
|
mov.b32 %r231, %f556;
|
|
and.b32 %r232, %r231, -2147483648;
|
|
or.b32 %r233, %r232, 1123811328;
|
|
mov.b32 %f558, %r233;
|
|
selp.f32 %f559, %f558, %f556, %p63;
|
|
mov.f32 %f560, 0fBF317218;
|
|
fma.rn.f32 %f561, %f559, %f560, %f553;
|
|
mov.f32 %f562, 0f3102E308;
|
|
fma.rn.f32 %f563, %f559, %f562, %f561;
|
|
mul.f32 %f564, %f563, 0f3FB8AA3B;
|
|
add.f32 %f565, %f559, 0f4B40007F;
|
|
mov.b32 %r234, %f565;
|
|
shl.b32 %r235, %r234, 23;
|
|
mov.b32 %f566, %r235;
|
|
ex2.approx.ftz.f32 %f567, %f564;
|
|
mul.f32 %f161, %f567, %f566;
|
|
setp.eq.f32 %p64, %f161, 0f7F800000;
|
|
mov.f32 %f1174, 0f7F800000;
|
|
@%p64 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1174, %f161, %f160, %f161;
|
|
|
|
$L__BB0_51:
|
|
setp.lt.f32 %p65, %f144, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f144, 0f00000000;
|
|
@%p67 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f572, %f144, %f144;
|
|
selp.f32 %f1176, %f572, 0f00000000, %p51;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r236, %f1174;
|
|
xor.b32 %r237, %r236, -2147483648;
|
|
mov.b32 %f568, %r237;
|
|
selp.f32 %f1176, %f568, %f1174, %p2;
|
|
setp.geu.f32 %p68, %f144, 0f00000000;
|
|
@%p68 bra $L__BB0_56;
|
|
|
|
mov.f32 %f569, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f570, %f569;
|
|
setp.eq.f32 %p69, %f570, 0f3EE66666;
|
|
@%p69 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1176, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f573, %f159, 0f3EE66666;
|
|
mov.b32 %r238, %f573;
|
|
setp.lt.s32 %p71, %r238, 2139095040;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
setp.gtu.f32 %p72, %f159, 0f7F800000;
|
|
@%p72 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1176, %f144, 0f3EE66666;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
setp.neu.f32 %p73, %f159, 0f7F800000;
|
|
@%p73 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1176, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
setp.eq.f32 %p74, %f144, 0f3F800000;
|
|
selp.f32 %f170, 0f3F800000, %f1176, %p74;
|
|
abs.f32 %f171, %f145;
|
|
setp.lt.f32 %p75, %f171, 0f00800000;
|
|
mul.f32 %f575, %f171, 0f4B800000;
|
|
selp.f32 %f576, %f575, %f171, %p75;
|
|
selp.f32 %f577, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r239, %f576;
|
|
and.b32 %r240, %r239, 8388607;
|
|
or.b32 %r241, %r240, 1065353216;
|
|
mov.b32 %f578, %r241;
|
|
shr.u32 %r242, %r239, 23;
|
|
cvt.rn.f32.u32 %f579, %r242;
|
|
add.f32 %f580, %f577, %f579;
|
|
setp.gt.f32 %p76, %f578, 0f3FB504F3;
|
|
mul.f32 %f581, %f578, 0f3F000000;
|
|
add.f32 %f582, %f580, 0f3F800000;
|
|
selp.f32 %f583, %f582, %f580, %p76;
|
|
selp.f32 %f584, %f581, %f578, %p76;
|
|
add.f32 %f585, %f584, 0fBF800000;
|
|
add.f32 %f586, %f584, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f587, %f586;
|
|
add.f32 %f588, %f585, %f585;
|
|
mul.f32 %f589, %f588, %f587;
|
|
mul.f32 %f590, %f589, %f589;
|
|
mov.f32 %f591, 0f3C4CAF63;
|
|
mov.f32 %f592, 0f3B18F0FE;
|
|
fma.rn.f32 %f593, %f592, %f590, %f591;
|
|
mov.f32 %f594, 0f3DAAAABD;
|
|
fma.rn.f32 %f595, %f593, %f590, %f594;
|
|
mul.rn.f32 %f596, %f595, %f590;
|
|
mul.rn.f32 %f597, %f596, %f589;
|
|
sub.f32 %f598, %f585, %f589;
|
|
add.f32 %f599, %f598, %f598;
|
|
neg.f32 %f600, %f589;
|
|
fma.rn.f32 %f601, %f600, %f585, %f599;
|
|
mul.rn.f32 %f602, %f587, %f601;
|
|
add.f32 %f603, %f597, %f589;
|
|
sub.f32 %f604, %f589, %f603;
|
|
add.f32 %f605, %f597, %f604;
|
|
add.f32 %f606, %f602, %f605;
|
|
add.f32 %f607, %f603, %f606;
|
|
sub.f32 %f608, %f603, %f607;
|
|
add.f32 %f609, %f606, %f608;
|
|
mov.f32 %f610, 0f3F317200;
|
|
mul.rn.f32 %f611, %f583, %f610;
|
|
mov.f32 %f612, 0f35BFBE8E;
|
|
mul.rn.f32 %f613, %f583, %f612;
|
|
add.f32 %f614, %f611, %f607;
|
|
sub.f32 %f615, %f611, %f614;
|
|
add.f32 %f616, %f607, %f615;
|
|
add.f32 %f617, %f609, %f616;
|
|
add.f32 %f618, %f613, %f617;
|
|
add.f32 %f619, %f614, %f618;
|
|
sub.f32 %f620, %f614, %f619;
|
|
add.f32 %f621, %f618, %f620;
|
|
mov.f32 %f622, 0f3EE66666;
|
|
mul.rn.f32 %f623, %f622, %f619;
|
|
neg.f32 %f624, %f623;
|
|
fma.rn.f32 %f625, %f622, %f619, %f624;
|
|
fma.rn.f32 %f626, %f622, %f621, %f625;
|
|
mov.f32 %f627, 0f00000000;
|
|
fma.rn.f32 %f628, %f627, %f619, %f626;
|
|
add.rn.f32 %f629, %f623, %f628;
|
|
neg.f32 %f630, %f629;
|
|
add.rn.f32 %f631, %f623, %f630;
|
|
add.rn.f32 %f632, %f631, %f628;
|
|
mov.b32 %r243, %f629;
|
|
setp.eq.s32 %p77, %r243, 1118925336;
|
|
add.s32 %r244, %r243, -1;
|
|
mov.b32 %f633, %r244;
|
|
add.f32 %f634, %f632, 0f37000000;
|
|
selp.f32 %f172, %f634, %f632, %p77;
|
|
selp.f32 %f635, %f633, %f629, %p77;
|
|
mov.f32 %f636, 0f3FB8AA3B;
|
|
mul.rn.f32 %f637, %f635, %f636;
|
|
cvt.rzi.f32.f32 %f638, %f637;
|
|
abs.f32 %f639, %f638;
|
|
setp.gt.f32 %p78, %f639, 0f42FC0000;
|
|
mov.b32 %r245, %f638;
|
|
and.b32 %r246, %r245, -2147483648;
|
|
or.b32 %r247, %r246, 1123811328;
|
|
mov.b32 %f640, %r247;
|
|
selp.f32 %f641, %f640, %f638, %p78;
|
|
mov.f32 %f642, 0fBF317218;
|
|
fma.rn.f32 %f643, %f641, %f642, %f635;
|
|
mov.f32 %f644, 0f3102E308;
|
|
fma.rn.f32 %f645, %f641, %f644, %f643;
|
|
mul.f32 %f646, %f645, 0f3FB8AA3B;
|
|
add.f32 %f647, %f641, 0f4B40007F;
|
|
mov.b32 %r248, %f647;
|
|
shl.b32 %r249, %r248, 23;
|
|
mov.b32 %f648, %r249;
|
|
ex2.approx.ftz.f32 %f649, %f646;
|
|
mul.f32 %f173, %f649, %f648;
|
|
setp.eq.f32 %p79, %f173, 0f7F800000;
|
|
mov.f32 %f1177, 0f7F800000;
|
|
@%p79 bra $L__BB0_63;
|
|
|
|
fma.rn.f32 %f1177, %f173, %f172, %f173;
|
|
|
|
$L__BB0_63:
|
|
setp.lt.f32 %p80, %f145, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f145, 0f00000000;
|
|
@%p82 bra $L__BB0_67;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f654, %f145, %f145;
|
|
selp.f32 %f1179, %f654, 0f00000000, %p51;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_64:
|
|
mov.b32 %r250, %f1177;
|
|
xor.b32 %r251, %r250, -2147483648;
|
|
mov.b32 %f650, %r251;
|
|
selp.f32 %f1179, %f650, %f1177, %p3;
|
|
setp.geu.f32 %p83, %f145, 0f00000000;
|
|
@%p83 bra $L__BB0_68;
|
|
|
|
mov.f32 %f651, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f652, %f651;
|
|
setp.eq.f32 %p84, %f652, 0f3EE66666;
|
|
@%p84 bra $L__BB0_68;
|
|
|
|
mov.f32 %f1179, 0f7FFFFFFF;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f655, %f171, 0f3EE66666;
|
|
mov.b32 %r252, %f655;
|
|
setp.lt.s32 %p86, %r252, 2139095040;
|
|
@%p86 bra $L__BB0_73;
|
|
|
|
setp.gtu.f32 %p87, %f171, 0f7F800000;
|
|
@%p87 bra $L__BB0_72;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f1179, %f145, 0f3EE66666;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_70:
|
|
setp.neu.f32 %p88, %f171, 0f7F800000;
|
|
@%p88 bra $L__BB0_73;
|
|
|
|
selp.f32 %f1179, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_73:
|
|
setp.eq.f32 %p89, %f145, 0f3F800000;
|
|
mov.f32 %f657, 0f3F800000;
|
|
selp.f32 %f658, 0f3F800000, %f1179, %p89;
|
|
min.f32 %f659, %f158, %f657;
|
|
mov.f32 %f660, 0f00000000;
|
|
max.f32 %f182, %f660, %f659;
|
|
min.f32 %f661, %f170, %f657;
|
|
max.f32 %f183, %f660, %f661;
|
|
min.f32 %f662, %f658, %f657;
|
|
max.f32 %f184, %f660, %f662;
|
|
mov.f32 %f666, 0f3ED55555;
|
|
abs.f32 %f186, %f182;
|
|
setp.lt.f32 %p90, %f186, 0f00800000;
|
|
mul.f32 %f668, %f186, 0f4B800000;
|
|
selp.f32 %f669, %f668, %f186, %p90;
|
|
selp.f32 %f670, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r255, %f669;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f671, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f672, %r258;
|
|
add.f32 %f673, %f670, %f672;
|
|
setp.gt.f32 %p91, %f671, 0f3FB504F3;
|
|
mul.f32 %f674, %f671, 0f3F000000;
|
|
add.f32 %f675, %f673, 0f3F800000;
|
|
selp.f32 %f676, %f675, %f673, %p91;
|
|
selp.f32 %f677, %f674, %f671, %p91;
|
|
add.f32 %f678, %f677, 0fBF800000;
|
|
add.f32 %f679, %f677, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f680, %f679;
|
|
add.f32 %f681, %f678, %f678;
|
|
mul.f32 %f682, %f681, %f680;
|
|
mul.f32 %f683, %f682, %f682;
|
|
mov.f32 %f684, 0f3C4CAF63;
|
|
mov.f32 %f685, 0f3B18F0FE;
|
|
fma.rn.f32 %f686, %f685, %f683, %f684;
|
|
mov.f32 %f687, 0f3DAAAABD;
|
|
fma.rn.f32 %f688, %f686, %f683, %f687;
|
|
mul.rn.f32 %f689, %f688, %f683;
|
|
mul.rn.f32 %f690, %f689, %f682;
|
|
sub.f32 %f691, %f678, %f682;
|
|
add.f32 %f692, %f691, %f691;
|
|
neg.f32 %f693, %f682;
|
|
fma.rn.f32 %f694, %f693, %f678, %f692;
|
|
mul.rn.f32 %f695, %f680, %f694;
|
|
add.f32 %f696, %f690, %f682;
|
|
sub.f32 %f697, %f682, %f696;
|
|
add.f32 %f698, %f690, %f697;
|
|
add.f32 %f699, %f695, %f698;
|
|
add.f32 %f700, %f696, %f699;
|
|
sub.f32 %f701, %f696, %f700;
|
|
add.f32 %f702, %f699, %f701;
|
|
mov.f32 %f703, 0f3F317200;
|
|
mul.rn.f32 %f704, %f676, %f703;
|
|
mov.f32 %f705, 0f35BFBE8E;
|
|
mul.rn.f32 %f706, %f676, %f705;
|
|
add.f32 %f707, %f704, %f700;
|
|
sub.f32 %f708, %f704, %f707;
|
|
add.f32 %f709, %f700, %f708;
|
|
add.f32 %f710, %f702, %f709;
|
|
add.f32 %f711, %f706, %f710;
|
|
add.f32 %f712, %f707, %f711;
|
|
sub.f32 %f713, %f707, %f712;
|
|
add.f32 %f714, %f711, %f713;
|
|
mul.rn.f32 %f715, %f666, %f712;
|
|
neg.f32 %f716, %f715;
|
|
fma.rn.f32 %f717, %f666, %f712, %f716;
|
|
fma.rn.f32 %f718, %f666, %f714, %f717;
|
|
fma.rn.f32 %f719, %f660, %f712, %f718;
|
|
add.rn.f32 %f720, %f715, %f719;
|
|
neg.f32 %f721, %f720;
|
|
add.rn.f32 %f722, %f715, %f721;
|
|
add.rn.f32 %f723, %f722, %f719;
|
|
mov.b32 %r259, %f720;
|
|
setp.eq.s32 %p92, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f724, %r260;
|
|
add.f32 %f725, %f723, 0f37000000;
|
|
selp.f32 %f187, %f725, %f723, %p92;
|
|
selp.f32 %f726, %f724, %f720, %p92;
|
|
mov.f32 %f727, 0f3FB8AA3B;
|
|
mul.rn.f32 %f728, %f726, %f727;
|
|
cvt.rzi.f32.f32 %f729, %f728;
|
|
abs.f32 %f730, %f729;
|
|
setp.gt.f32 %p93, %f730, 0f42FC0000;
|
|
mov.b32 %r261, %f729;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f731, %r263;
|
|
selp.f32 %f732, %f731, %f729, %p93;
|
|
mov.f32 %f733, 0fBF317218;
|
|
fma.rn.f32 %f734, %f732, %f733, %f726;
|
|
mov.f32 %f735, 0f3102E308;
|
|
fma.rn.f32 %f736, %f732, %f735, %f734;
|
|
mul.f32 %f737, %f736, 0f3FB8AA3B;
|
|
add.f32 %f738, %f732, 0f4B40007F;
|
|
mov.b32 %r264, %f738;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f739, %r265;
|
|
ex2.approx.ftz.f32 %f740, %f737;
|
|
mul.f32 %f188, %f740, %f739;
|
|
setp.eq.f32 %p94, %f188, 0f7F800000;
|
|
mov.f32 %f1180, 0f7F800000;
|
|
@%p94 bra $L__BB0_75;
|
|
|
|
fma.rn.f32 %f1180, %f188, %f187, %f188;
|
|
|
|
$L__BB0_75:
|
|
mov.f32 %f1084, 0f00000000;
|
|
max.f32 %f1083, %f1084, %f659;
|
|
mov.f32 %f1064, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1063, %f1064;
|
|
add.f32 %f1062, %f1063, %f1063;
|
|
mov.f32 %f1061, 0f3ED55555;
|
|
sub.f32 %f1060, %f1061, %f1062;
|
|
abs.f32 %f1059, %f1060;
|
|
setp.lt.f32 %p95, %f1083, 0f00000000;
|
|
setp.eq.f32 %p96, %f1059, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f1083, 0f00000000;
|
|
@%p97 bra $L__BB0_79;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_79:
|
|
mov.f32 %f1101, 0f00000000;
|
|
max.f32 %f1100, %f1101, %f659;
|
|
add.f32 %f745, %f1100, %f1100;
|
|
selp.f32 %f1182, %f745, 0f00000000, %p96;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_76:
|
|
mov.f32 %f1086, 0f00000000;
|
|
max.f32 %f1085, %f1086, %f659;
|
|
mov.b32 %r266, %f1180;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f741, %r267;
|
|
selp.f32 %f1182, %f741, %f1180, %p4;
|
|
setp.geu.f32 %p98, %f1085, 0f00000000;
|
|
@%p98 bra $L__BB0_80;
|
|
|
|
mov.f32 %f742, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f743, %f742;
|
|
setp.eq.f32 %p99, %f743, 0f3ED55555;
|
|
@%p99 bra $L__BB0_80;
|
|
|
|
mov.f32 %f1182, 0f7FFFFFFF;
|
|
|
|
$L__BB0_80:
|
|
mov.f32 %f1089, 0f00000000;
|
|
max.f32 %f1088, %f1089, %f659;
|
|
abs.f32 %f1087, %f1088;
|
|
add.f32 %f746, %f1087, 0f3ED55555;
|
|
mov.b32 %r268, %f746;
|
|
setp.lt.s32 %p101, %r268, 2139095040;
|
|
@%p101 bra $L__BB0_85;
|
|
|
|
mov.f32 %f1094, 0f00000000;
|
|
max.f32 %f1093, %f1094, %f659;
|
|
abs.f32 %f1092, %f1093;
|
|
setp.gtu.f32 %p102, %f1092, 0f7F800000;
|
|
@%p102 bra $L__BB0_84;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_84:
|
|
mov.f32 %f1099, 0f00000000;
|
|
max.f32 %f1098, %f1099, %f659;
|
|
add.f32 %f1182, %f1098, 0f3ED55555;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_82:
|
|
mov.f32 %f1097, 0f00000000;
|
|
max.f32 %f1096, %f1097, %f659;
|
|
abs.f32 %f1095, %f1096;
|
|
setp.neu.f32 %p103, %f1095, 0f7F800000;
|
|
@%p103 bra $L__BB0_85;
|
|
|
|
selp.f32 %f1182, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_85:
|
|
abs.f32 %f197, %f183;
|
|
setp.lt.f32 %p104, %f197, 0f00800000;
|
|
mul.f32 %f748, %f197, 0f4B800000;
|
|
selp.f32 %f749, %f748, %f197, %p104;
|
|
selp.f32 %f750, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r269, %f749;
|
|
and.b32 %r270, %r269, 8388607;
|
|
or.b32 %r271, %r270, 1065353216;
|
|
mov.b32 %f751, %r271;
|
|
shr.u32 %r272, %r269, 23;
|
|
cvt.rn.f32.u32 %f752, %r272;
|
|
add.f32 %f753, %f750, %f752;
|
|
setp.gt.f32 %p105, %f751, 0f3FB504F3;
|
|
mul.f32 %f754, %f751, 0f3F000000;
|
|
add.f32 %f755, %f753, 0f3F800000;
|
|
selp.f32 %f756, %f755, %f753, %p105;
|
|
selp.f32 %f757, %f754, %f751, %p105;
|
|
add.f32 %f758, %f757, 0fBF800000;
|
|
add.f32 %f759, %f757, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f760, %f759;
|
|
add.f32 %f761, %f758, %f758;
|
|
mul.f32 %f762, %f761, %f760;
|
|
mul.f32 %f763, %f762, %f762;
|
|
mov.f32 %f764, 0f3C4CAF63;
|
|
mov.f32 %f765, 0f3B18F0FE;
|
|
fma.rn.f32 %f766, %f765, %f763, %f764;
|
|
mov.f32 %f767, 0f3DAAAABD;
|
|
fma.rn.f32 %f768, %f766, %f763, %f767;
|
|
mul.rn.f32 %f769, %f768, %f763;
|
|
mul.rn.f32 %f770, %f769, %f762;
|
|
sub.f32 %f771, %f758, %f762;
|
|
add.f32 %f772, %f771, %f771;
|
|
neg.f32 %f773, %f762;
|
|
fma.rn.f32 %f774, %f773, %f758, %f772;
|
|
mul.rn.f32 %f775, %f760, %f774;
|
|
add.f32 %f776, %f770, %f762;
|
|
sub.f32 %f777, %f762, %f776;
|
|
add.f32 %f778, %f770, %f777;
|
|
add.f32 %f779, %f775, %f778;
|
|
add.f32 %f780, %f776, %f779;
|
|
sub.f32 %f781, %f776, %f780;
|
|
add.f32 %f782, %f779, %f781;
|
|
mov.f32 %f783, 0f3F317200;
|
|
mul.rn.f32 %f784, %f756, %f783;
|
|
mov.f32 %f785, 0f35BFBE8E;
|
|
mul.rn.f32 %f786, %f756, %f785;
|
|
add.f32 %f787, %f784, %f780;
|
|
sub.f32 %f788, %f784, %f787;
|
|
add.f32 %f789, %f780, %f788;
|
|
add.f32 %f790, %f782, %f789;
|
|
add.f32 %f791, %f786, %f790;
|
|
add.f32 %f792, %f787, %f791;
|
|
sub.f32 %f793, %f787, %f792;
|
|
add.f32 %f794, %f791, %f793;
|
|
mov.f32 %f795, 0f3ED55555;
|
|
mul.rn.f32 %f796, %f795, %f792;
|
|
neg.f32 %f797, %f796;
|
|
fma.rn.f32 %f798, %f795, %f792, %f797;
|
|
fma.rn.f32 %f799, %f795, %f794, %f798;
|
|
mov.f32 %f800, 0f00000000;
|
|
fma.rn.f32 %f801, %f800, %f792, %f799;
|
|
add.rn.f32 %f802, %f796, %f801;
|
|
neg.f32 %f803, %f802;
|
|
add.rn.f32 %f804, %f796, %f803;
|
|
add.rn.f32 %f805, %f804, %f801;
|
|
mov.b32 %r273, %f802;
|
|
setp.eq.s32 %p106, %r273, 1118925336;
|
|
add.s32 %r274, %r273, -1;
|
|
mov.b32 %f806, %r274;
|
|
add.f32 %f807, %f805, 0f37000000;
|
|
selp.f32 %f198, %f807, %f805, %p106;
|
|
selp.f32 %f808, %f806, %f802, %p106;
|
|
mov.f32 %f809, 0f3FB8AA3B;
|
|
mul.rn.f32 %f810, %f808, %f809;
|
|
cvt.rzi.f32.f32 %f811, %f810;
|
|
abs.f32 %f812, %f811;
|
|
setp.gt.f32 %p107, %f812, 0f42FC0000;
|
|
mov.b32 %r275, %f811;
|
|
and.b32 %r276, %r275, -2147483648;
|
|
or.b32 %r277, %r276, 1123811328;
|
|
mov.b32 %f813, %r277;
|
|
selp.f32 %f814, %f813, %f811, %p107;
|
|
mov.f32 %f815, 0fBF317218;
|
|
fma.rn.f32 %f816, %f814, %f815, %f808;
|
|
mov.f32 %f817, 0f3102E308;
|
|
fma.rn.f32 %f818, %f814, %f817, %f816;
|
|
mul.f32 %f819, %f818, 0f3FB8AA3B;
|
|
add.f32 %f820, %f814, 0f4B40007F;
|
|
mov.b32 %r278, %f820;
|
|
shl.b32 %r279, %r278, 23;
|
|
mov.b32 %f821, %r279;
|
|
ex2.approx.ftz.f32 %f822, %f819;
|
|
mul.f32 %f199, %f822, %f821;
|
|
setp.eq.f32 %p108, %f199, 0f7F800000;
|
|
mov.f32 %f1183, 0f7F800000;
|
|
@%p108 bra $L__BB0_87;
|
|
|
|
fma.rn.f32 %f1183, %f199, %f198, %f199;
|
|
|
|
$L__BB0_87:
|
|
setp.lt.f32 %p109, %f183, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f183, 0f00000000;
|
|
@%p111 bra $L__BB0_91;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f827, %f183, %f183;
|
|
selp.f32 %f1185, %f827, 0f00000000, %p96;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_88:
|
|
mov.b32 %r280, %f1183;
|
|
xor.b32 %r281, %r280, -2147483648;
|
|
mov.b32 %f823, %r281;
|
|
selp.f32 %f1185, %f823, %f1183, %p5;
|
|
setp.geu.f32 %p112, %f183, 0f00000000;
|
|
@%p112 bra $L__BB0_92;
|
|
|
|
mov.f32 %f824, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f825, %f824;
|
|
setp.eq.f32 %p113, %f825, 0f3ED55555;
|
|
@%p113 bra $L__BB0_92;
|
|
|
|
mov.f32 %f1185, 0f7FFFFFFF;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f1067, 0f00000000;
|
|
max.f32 %f1066, %f1067, %f661;
|
|
abs.f32 %f1065, %f1066;
|
|
add.f32 %f828, %f1065, 0f3ED55555;
|
|
mov.b32 %r282, %f828;
|
|
setp.lt.s32 %p115, %r282, 2139095040;
|
|
@%p115 bra $L__BB0_97;
|
|
|
|
mov.f32 %f1070, 0f00000000;
|
|
max.f32 %f1069, %f1070, %f661;
|
|
abs.f32 %f1068, %f1069;
|
|
setp.gtu.f32 %p116, %f1068, 0f7F800000;
|
|
@%p116 bra $L__BB0_96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_96:
|
|
add.f32 %f1185, %f183, 0f3ED55555;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_94:
|
|
mov.f32 %f1073, 0f00000000;
|
|
max.f32 %f1072, %f1073, %f661;
|
|
abs.f32 %f1071, %f1072;
|
|
setp.neu.f32 %p117, %f1071, 0f7F800000;
|
|
@%p117 bra $L__BB0_97;
|
|
|
|
selp.f32 %f1185, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_97:
|
|
abs.f32 %f208, %f184;
|
|
setp.lt.f32 %p118, %f208, 0f00800000;
|
|
mul.f32 %f830, %f208, 0f4B800000;
|
|
selp.f32 %f831, %f830, %f208, %p118;
|
|
selp.f32 %f832, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r283, %f831;
|
|
and.b32 %r284, %r283, 8388607;
|
|
or.b32 %r285, %r284, 1065353216;
|
|
mov.b32 %f833, %r285;
|
|
shr.u32 %r286, %r283, 23;
|
|
cvt.rn.f32.u32 %f834, %r286;
|
|
add.f32 %f835, %f832, %f834;
|
|
setp.gt.f32 %p119, %f833, 0f3FB504F3;
|
|
mul.f32 %f836, %f833, 0f3F000000;
|
|
add.f32 %f837, %f835, 0f3F800000;
|
|
selp.f32 %f838, %f837, %f835, %p119;
|
|
selp.f32 %f839, %f836, %f833, %p119;
|
|
add.f32 %f840, %f839, 0fBF800000;
|
|
add.f32 %f841, %f839, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f842, %f841;
|
|
add.f32 %f843, %f840, %f840;
|
|
mul.f32 %f844, %f843, %f842;
|
|
mul.f32 %f845, %f844, %f844;
|
|
mov.f32 %f846, 0f3C4CAF63;
|
|
mov.f32 %f847, 0f3B18F0FE;
|
|
fma.rn.f32 %f848, %f847, %f845, %f846;
|
|
mov.f32 %f849, 0f3DAAAABD;
|
|
fma.rn.f32 %f850, %f848, %f845, %f849;
|
|
mul.rn.f32 %f851, %f850, %f845;
|
|
mul.rn.f32 %f852, %f851, %f844;
|
|
sub.f32 %f853, %f840, %f844;
|
|
add.f32 %f854, %f853, %f853;
|
|
neg.f32 %f855, %f844;
|
|
fma.rn.f32 %f856, %f855, %f840, %f854;
|
|
mul.rn.f32 %f857, %f842, %f856;
|
|
add.f32 %f858, %f852, %f844;
|
|
sub.f32 %f859, %f844, %f858;
|
|
add.f32 %f860, %f852, %f859;
|
|
add.f32 %f861, %f857, %f860;
|
|
add.f32 %f862, %f858, %f861;
|
|
sub.f32 %f863, %f858, %f862;
|
|
add.f32 %f864, %f861, %f863;
|
|
mov.f32 %f865, 0f3F317200;
|
|
mul.rn.f32 %f866, %f838, %f865;
|
|
mov.f32 %f867, 0f35BFBE8E;
|
|
mul.rn.f32 %f868, %f838, %f867;
|
|
add.f32 %f869, %f866, %f862;
|
|
sub.f32 %f870, %f866, %f869;
|
|
add.f32 %f871, %f862, %f870;
|
|
add.f32 %f872, %f864, %f871;
|
|
add.f32 %f873, %f868, %f872;
|
|
add.f32 %f874, %f869, %f873;
|
|
sub.f32 %f875, %f869, %f874;
|
|
add.f32 %f876, %f873, %f875;
|
|
mov.f32 %f877, 0f3ED55555;
|
|
mul.rn.f32 %f878, %f877, %f874;
|
|
neg.f32 %f879, %f878;
|
|
fma.rn.f32 %f880, %f877, %f874, %f879;
|
|
fma.rn.f32 %f881, %f877, %f876, %f880;
|
|
mov.f32 %f882, 0f00000000;
|
|
fma.rn.f32 %f883, %f882, %f874, %f881;
|
|
add.rn.f32 %f884, %f878, %f883;
|
|
neg.f32 %f885, %f884;
|
|
add.rn.f32 %f886, %f878, %f885;
|
|
add.rn.f32 %f887, %f886, %f883;
|
|
mov.b32 %r287, %f884;
|
|
setp.eq.s32 %p120, %r287, 1118925336;
|
|
add.s32 %r288, %r287, -1;
|
|
mov.b32 %f888, %r288;
|
|
add.f32 %f889, %f887, 0f37000000;
|
|
selp.f32 %f209, %f889, %f887, %p120;
|
|
selp.f32 %f890, %f888, %f884, %p120;
|
|
mov.f32 %f891, 0f3FB8AA3B;
|
|
mul.rn.f32 %f892, %f890, %f891;
|
|
cvt.rzi.f32.f32 %f893, %f892;
|
|
abs.f32 %f894, %f893;
|
|
setp.gt.f32 %p121, %f894, 0f42FC0000;
|
|
mov.b32 %r289, %f893;
|
|
and.b32 %r290, %r289, -2147483648;
|
|
or.b32 %r291, %r290, 1123811328;
|
|
mov.b32 %f895, %r291;
|
|
selp.f32 %f896, %f895, %f893, %p121;
|
|
mov.f32 %f897, 0fBF317218;
|
|
fma.rn.f32 %f898, %f896, %f897, %f890;
|
|
mov.f32 %f899, 0f3102E308;
|
|
fma.rn.f32 %f900, %f896, %f899, %f898;
|
|
mul.f32 %f901, %f900, 0f3FB8AA3B;
|
|
add.f32 %f902, %f896, 0f4B40007F;
|
|
mov.b32 %r292, %f902;
|
|
shl.b32 %r293, %r292, 23;
|
|
mov.b32 %f903, %r293;
|
|
ex2.approx.ftz.f32 %f904, %f901;
|
|
mul.f32 %f210, %f904, %f903;
|
|
setp.eq.f32 %p122, %f210, 0f7F800000;
|
|
mov.f32 %f1186, 0f7F800000;
|
|
@%p122 bra $L__BB0_99;
|
|
|
|
fma.rn.f32 %f1186, %f210, %f209, %f210;
|
|
|
|
$L__BB0_99:
|
|
setp.lt.f32 %p123, %f184, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f184, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f909, %f184, %f184;
|
|
selp.f32 %f1188, %f909, 0f00000000, %p96;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_100:
|
|
mov.b32 %r294, %f1186;
|
|
xor.b32 %r295, %r294, -2147483648;
|
|
mov.b32 %f905, %r295;
|
|
selp.f32 %f1188, %f905, %f1186, %p6;
|
|
setp.geu.f32 %p126, %f184, 0f00000000;
|
|
@%p126 bra $L__BB0_104;
|
|
|
|
mov.f32 %f906, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f907, %f906;
|
|
setp.eq.f32 %p127, %f907, 0f3ED55555;
|
|
@%p127 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1188, 0f7FFFFFFF;
|
|
|
|
$L__BB0_104:
|
|
mov.f32 %f1076, 0f00000000;
|
|
max.f32 %f1075, %f1076, %f662;
|
|
abs.f32 %f1074, %f1075;
|
|
add.f32 %f910, %f1074, 0f3ED55555;
|
|
mov.b32 %r296, %f910;
|
|
setp.lt.s32 %p129, %r296, 2139095040;
|
|
@%p129 bra $L__BB0_109;
|
|
|
|
mov.f32 %f1079, 0f00000000;
|
|
max.f32 %f1078, %f1079, %f662;
|
|
abs.f32 %f1077, %f1078;
|
|
setp.gtu.f32 %p130, %f1077, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_108:
|
|
add.f32 %f1188, %f184, 0f3ED55555;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1082, 0f00000000;
|
|
max.f32 %f1081, %f1082, %f662;
|
|
abs.f32 %f1080, %f1081;
|
|
setp.neu.f32 %p131, %f1080, 0f7F800000;
|
|
@%p131 bra $L__BB0_109;
|
|
|
|
selp.f32 %f1188, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_109:
|
|
mov.f32 %f1091, 0f00000000;
|
|
max.f32 %f1090, %f1091, %f659;
|
|
ld.const.u64 %rd103, [params+144];
|
|
cvta.to.global.u64 %rd102, %rd103;
|
|
ld.const.u32 %r347, [params+136];
|
|
mad.lo.s32 %r346, %r347, %r6, %r5;
|
|
cvt.u64.u32 %rd101, %r346;
|
|
fma.rn.f32 %f911, %f1182, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f1090, 0f3F800000;
|
|
mov.f32 %f912, 0f3F800000;
|
|
selp.f32 %f913, 0f3F7FFFFF, %f911, %p132;
|
|
mul.f32 %f914, %f1090, 0f414EB852;
|
|
setp.lt.f32 %p133, %f1090, 0f3B4D2E1C;
|
|
selp.f32 %f915, %f914, %f913, %p133;
|
|
fma.rn.f32 %f916, %f1185, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f183, 0f3F800000;
|
|
selp.f32 %f917, 0f3F7FFFFF, %f916, %p134;
|
|
mul.f32 %f918, %f183, 0f414EB852;
|
|
setp.lt.f32 %p135, %f183, 0f3B4D2E1C;
|
|
selp.f32 %f919, %f918, %f917, %p135;
|
|
fma.rn.f32 %f920, %f1188, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f184, 0f3F800000;
|
|
selp.f32 %f921, 0f3F7FFFFF, %f920, %p136;
|
|
mul.f32 %f922, %f184, 0f414EB852;
|
|
setp.lt.f32 %p137, %f184, 0f3B4D2E1C;
|
|
selp.f32 %f923, %f922, %f921, %p137;
|
|
min.f32 %f924, %f915, %f912;
|
|
mov.f32 %f925, 0f00000000;
|
|
max.f32 %f926, %f925, %f924;
|
|
mul.f32 %f927, %f926, 0f43800000;
|
|
cvt.rzi.u32.f32 %r297, %f927;
|
|
min.u32 %r298, %r297, 255;
|
|
min.f32 %f928, %f919, %f912;
|
|
max.f32 %f929, %f925, %f928;
|
|
mul.f32 %f930, %f929, 0f43800000;
|
|
cvt.rzi.u32.f32 %r299, %f930;
|
|
min.u32 %r300, %r299, 255;
|
|
min.f32 %f931, %f923, %f912;
|
|
max.f32 %f932, %f925, %f931;
|
|
mul.f32 %f933, %f932, 0f43800000;
|
|
cvt.rzi.u32.f32 %r301, %f933;
|
|
min.u32 %r302, %r301, 255;
|
|
shl.b64 %rd65, %rd101, 2;
|
|
add.s64 %rd66, %rd102, %rd65;
|
|
cvt.u16.u32 %rs15, %r302;
|
|
cvt.u16.u32 %rs16, %r300;
|
|
cvt.u16.u32 %rs17, %r298;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd66], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_110:
|
|
ld.const.u32 %r348, [params+104];
|
|
and.b32 %r303, %r348, 4;
|
|
setp.eq.s32 %p138, %r303, 0;
|
|
ld.const.u32 %r360, [params+108];
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
setp.eq.s32 %p139, %r360, 0;
|
|
ld.const.u64 %rd67, [params+224];
|
|
cvta.to.global.u64 %rd68, %rd67;
|
|
ld.const.u32 %r304, [params+216];
|
|
mad.lo.s32 %r305, %r304, %r6, %r5;
|
|
mul.wide.u32 %rd69, %r305, 8;
|
|
add.s64 %rd18, %rd68, %rd69;
|
|
@%p139 bra $L__BB0_113;
|
|
|
|
ld.global.v4.u16 {%rs26, %rs27, %rs28, %rs29}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f934, %rs26;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f935, %rs27;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f936, %rs28;}
|
|
|
|
// end inline asm
|
|
add.f32 %f937, %f143, %f934;
|
|
add.f32 %f938, %f144, %f935;
|
|
add.f32 %f939, %f145, %f936;
|
|
mov.f32 %f940, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs24, %f939;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs23, %f938;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs22, %f937;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f940;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs22, %rs23, %rs24, %rs25};
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_113:
|
|
mov.f32 %f944, 0f3F800000;
|
|
mov.u32 %r360, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f944;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f143;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs30, %rs31, %rs32, %rs33};
|
|
|
|
$L__BB0_114:
|
|
mul.f32 %f219, %f128, 0f3F000000;
|
|
mul.f32 %f220, %f219, %f402;
|
|
mul.f32 %f221, %f129, 0f3F000000;
|
|
mul.f32 %f222, %f221, %f403;
|
|
mul.f32 %f223, %f130, 0f3F000000;
|
|
mul.f32 %f224, %f223, %f404;
|
|
ld.const.u64 %rd70, [params+256];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r307, [params+248];
|
|
mad.lo.s32 %r308, %r307, %r6, %r5;
|
|
mul.wide.u32 %rd72, %r308, 8;
|
|
add.s64 %rd19, %rd71, %rd72;
|
|
setp.eq.s32 %p140, %r360, 0;
|
|
@%p140 bra $L__BB0_116;
|
|
|
|
ld.global.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f945, %rs41;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f946, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f947, %rs43;}
|
|
|
|
// end inline asm
|
|
add.f32 %f948, %f220, %f945;
|
|
add.f32 %f949, %f222, %f946;
|
|
add.f32 %f950, %f224, %f947;
|
|
mov.f32 %f951, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f950;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f949;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f948;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f951;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs37, %rs38, %rs39, %rs40};
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_116:
|
|
mov.f32 %f955, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f955;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f224;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f222;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f220;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs45, %rs46, %rs47, %rs48};
|
|
|
|
$L__BB0_117:
|
|
mov.f32 %f956, 0f34000000;
|
|
max.f32 %f957, %f219, %f956;
|
|
mul.f32 %f958, %f131, 0f3F000000;
|
|
div.rn.f32 %f959, %f958, %f957;
|
|
max.f32 %f960, %f221, %f956;
|
|
mul.f32 %f961, %f132, 0f3F000000;
|
|
div.rn.f32 %f962, %f961, %f960;
|
|
max.f32 %f963, %f223, %f956;
|
|
mul.f32 %f964, %f133, 0f3F000000;
|
|
div.rn.f32 %f965, %f964, %f963;
|
|
fma.rn.f32 %f225, %f959, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f226, %f962, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f227, %f965, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f966, %f134, 0f3F000000;
|
|
div.rn.f32 %f967, %f966, %f957;
|
|
mul.f32 %f968, %f135, 0f3F000000;
|
|
div.rn.f32 %f969, %f968, %f960;
|
|
mul.f32 %f970, %f136, 0f3F000000;
|
|
div.rn.f32 %f971, %f970, %f963;
|
|
fma.rn.f32 %f228, %f967, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f229, %f969, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f230, %f971, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f972, %f137, 0f3F000000;
|
|
div.rn.f32 %f973, %f972, %f957;
|
|
mul.f32 %f974, %f138, 0f3F000000;
|
|
div.rn.f32 %f975, %f974, %f960;
|
|
mul.f32 %f976, %f139, 0f3F000000;
|
|
div.rn.f32 %f977, %f976, %f963;
|
|
fma.rn.f32 %f231, %f973, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f232, %f975, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f233, %f977, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd73, [params+272];
|
|
cvta.to.global.u64 %rd74, %rd73;
|
|
ld.const.u32 %r309, [params+264];
|
|
mad.lo.s32 %r310, %r309, %r6, %r5;
|
|
mul.wide.u32 %rd75, %r310, 8;
|
|
add.s64 %rd20, %rd74, %rd75;
|
|
@%p140 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs56, %rs57, %rs58, %rs59}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f978, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f979, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f980, %rs58;}
|
|
|
|
// end inline asm
|
|
add.f32 %f981, %f225, %f978;
|
|
add.f32 %f982, %f226, %f979;
|
|
add.f32 %f983, %f227, %f980;
|
|
mov.f32 %f984, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f983;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f982;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f981;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f984;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs52, %rs53, %rs54, %rs55};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f988, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f988;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f227;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f226;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f225;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_120:
|
|
ld.const.u64 %rd76, [params+288];
|
|
cvta.to.global.u64 %rd77, %rd76;
|
|
ld.const.u32 %r311, [params+280];
|
|
mad.lo.s32 %r312, %r311, %r6, %r5;
|
|
mul.wide.u32 %rd78, %r312, 8;
|
|
add.s64 %rd21, %rd77, %rd78;
|
|
@%p140 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f989, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f990, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f991, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f992, %f228, %f989;
|
|
add.f32 %f993, %f229, %f990;
|
|
add.f32 %f994, %f230, %f991;
|
|
mov.f32 %f995, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f994;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f993;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f992;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f995;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f999, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f999;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f230;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f229;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f228;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd79, [params+304];
|
|
cvta.to.global.u64 %rd80, %rd79;
|
|
ld.const.u32 %r313, [params+296];
|
|
mad.lo.s32 %r314, %r313, %r6, %r5;
|
|
mul.wide.u32 %rd81, %r314, 8;
|
|
add.s64 %rd22, %rd80, %rd81;
|
|
@%p140 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1000, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1001, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1002, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1003, %f231, %f1000;
|
|
add.f32 %f1004, %f232, %f1001;
|
|
add.f32 %f1005, %f233, %f1002;
|
|
mov.f32 %f1006, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1005;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1004;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1003;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1006;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f1010, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f232;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f231;}
|
|
|
|
// end inline asm
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st.global.v4.u16 [%rd22], {%rs90, %rs91, %rs92, %rs93};
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$L__BB0_144:
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|
ret;
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}
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