2388 lines
64 KiB
Plaintext
2388 lines
64 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<171>;
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.reg .b16 %rs<178>;
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.reg .f32 %f<1129>;
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.reg .b32 %r<369>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<121>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r54), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r55), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd31, [params+400];
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cvta.to.global.u64 %rd32, %rd31;
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ld.const.u32 %r60, [params+392];
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mad.lo.s32 %r61, %r60, %r55, %r54;
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mul.wide.u32 %rd33, %r61, 4;
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add.s64 %rd2, %rd32, %rd33;
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ld.global.v2.u8 {%rs7, %rs177}, [%rd2];
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or.b16 %rs9, %rs7, %rs177;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p8, %rs10, 0;
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@%p8 bra $L__BB0_2;
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ld.global.u8 %rs176, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs176, [%rd2+2];
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setp.eq.s16 %p9, %rs176, 0;
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mov.f32 %f1095, 0f00000000;
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mov.u16 %rs177, 0;
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mov.f32 %f1096, %f1095;
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mov.f32 %f1097, %f1095;
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@%p9 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f158, %rs7;
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div.rn.f32 %f159, %f158, 0f437F0000;
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fma.rn.f32 %f160, %f159, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs177, 255;
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cvt.rn.f32.u16 %f161, %rs13;
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div.rn.f32 %f162, %f161, 0f437F0000;
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fma.rn.f32 %f163, %f162, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f164, %rs176;
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div.rn.f32 %f165, %f164, 0f437F0000;
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fma.rn.f32 %f166, %f165, 0f40000000, 0fBF800000;
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mul.f32 %f167, %f163, %f163;
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fma.rn.f32 %f168, %f160, %f160, %f167;
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fma.rn.f32 %f169, %f166, %f166, %f168;
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sqrt.rn.f32 %f170, %f169;
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rcp.rn.f32 %f171, %f170;
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mul.f32 %f1097, %f171, %f166;
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mul.f32 %f1096, %f171, %f163;
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mul.f32 %f1095, %f160, %f171;
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$L__BB0_4:
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ld.const.v2.u32 {%r62, %r63}, [params];
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add.s32 %r3, %r62, %r54;
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add.s32 %r4, %r63, %r55;
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setp.eq.f32 %p10, %f1095, 0f00000000;
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setp.eq.f32 %p11, %f1096, 0f00000000;
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and.pred %p12, %p10, %p11;
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setp.eq.f32 %p13, %f1097, 0f00000000;
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and.pred %p14, %p13, %p12;
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@%p14 bra $L__BB0_140;
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bra.uni $L__BB0_5;
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$L__BB0_140:
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ld.const.u32 %r51, [params+104];
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and.b32 %r331, %r51, 1;
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setp.eq.b32 %p160, %r331, 1;
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mov.pred %p161, 0;
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xor.pred %p162, %p160, %p161;
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not.pred %p163, %p162;
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@%p163 bra $L__BB0_142;
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ld.const.u64 %rd87, [params+144];
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cvta.to.global.u64 %rd88, %rd87;
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ld.const.u32 %r332, [params+136];
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mad.lo.s32 %r333, %r332, %r4, %r3;
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mul.wide.u32 %rd89, %r333, 4;
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add.s64 %rd90, %rd88, %rd89;
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mov.u16 %rs98, 0;
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st.global.v4.u8 [%rd90], {%rs98, %rs98, %rs98, %rs98};
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$L__BB0_142:
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and.b32 %r334, %r51, 8;
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setp.eq.s32 %p164, %r334, 0;
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@%p164 bra $L__BB0_144;
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ld.const.u64 %rd91, [params+192];
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cvta.to.global.u64 %rd92, %rd91;
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ld.const.u32 %r335, [params+184];
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mad.lo.s32 %r336, %r335, %r4, %r3;
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mov.f32 %f1001, 0f00000000;
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cvt.rzi.u32.f32 %r337, %f1001;
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mul.wide.u32 %rd93, %r336, 2;
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add.s64 %rd94, %rd92, %rd93;
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mov.u16 %rs99, 0;
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cvt.u16.u32 %rs100, %r337;
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st.global.v2.u8 [%rd94], {%rs100, %rs99};
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$L__BB0_144:
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and.b32 %r338, %r51, 4;
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setp.eq.s32 %p165, %r338, 0;
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ld.const.u32 %r368, [params+108];
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@%p165 bra $L__BB0_148;
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setp.eq.s32 %p166, %r368, 0;
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ld.const.u64 %rd95, [params+224];
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cvta.to.global.u64 %rd96, %rd95;
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ld.const.u32 %r339, [params+216];
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mad.lo.s32 %r340, %r339, %r4, %r3;
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mul.wide.u32 %rd97, %r340, 8;
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add.s64 %rd25, %rd96, %rd97;
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@%p166 bra $L__BB0_147;
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ld.global.v4.u16 {%rs107, %rs108, %rs109, %rs110}, [%rd25];
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// begin inline asm
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{ cvt.f32.f16 %f1002, %rs107;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1003, %rs108;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1004, %rs109;}
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// end inline asm
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add.f32 %f1005, %f1002, 0f00000000;
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add.f32 %f1006, %f1003, 0f00000000;
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add.f32 %f1007, %f1004, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs106, %f1007;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs105, %f1006;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs104, %f1005;}
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// end inline asm
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mov.u16 %rs111, 0;
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st.global.v4.u16 [%rd25], {%rs104, %rs105, %rs106, %rs111};
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bra.uni $L__BB0_148;
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$L__BB0_5:
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ld.const.v4.f32 {%f173, %f174, %f175, %f176}, [params+512];
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neg.f32 %f177, %f174;
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neg.f32 %f178, %f175;
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mul.f32 %f179, %f1095, %f173;
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mul.f32 %f180, %f1096, %f177;
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sub.f32 %f181, %f180, %f179;
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mul.f32 %f182, %f1097, %f175;
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sub.f32 %f13, %f181, %f182;
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ld.const.u64 %rd34, [params+432];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r66, [params+424];
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mad.lo.s32 %r67, %r66, %r55, %r54;
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mul.wide.u32 %rd36, %r67, 12;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.f32 %f183, [%rd37];
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mul.f32 %f184, %f183, 0f3456BF95;
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ld.global.f32 %f185, [%rd37+4];
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mul.f32 %f186, %f185, 0f3456BF95;
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ld.global.f32 %f187, [%rd37+8];
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mul.f32 %f188, %f187, 0f3456BF95;
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abs.f32 %f189, %f1095;
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div.rn.f32 %f190, %f184, %f189;
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abs.f32 %f191, %f1096;
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div.rn.f32 %f192, %f186, %f191;
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abs.f32 %f193, %f1097;
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div.rn.f32 %f194, %f188, %f193;
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abs.f32 %f195, %f190;
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abs.f32 %f196, %f192;
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abs.f32 %f197, %f194;
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mov.f32 %f198, 0f38D1B717;
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max.f32 %f199, %f195, %f198;
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max.f32 %f200, %f196, %f198;
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max.f32 %f201, %f197, %f198;
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fma.rn.f32 %f14, %f1095, %f199, %f183;
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fma.rn.f32 %f15, %f1096, %f200, %f185;
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fma.rn.f32 %f16, %f1097, %f201, %f187;
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abs.f32 %f202, %f173;
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abs.f32 %f203, %f175;
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setp.gt.f32 %p15, %f202, %f203;
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selp.f32 %f204, %f177, 0f00000000, %p15;
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mov.f32 %f1099, 0f00000000;
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selp.f32 %f205, %f173, %f178, %p15;
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selp.f32 %f206, 0f00000000, %f174, %p15;
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mul.f32 %f207, %f205, %f205;
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fma.rn.f32 %f208, %f204, %f204, %f207;
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fma.rn.f32 %f209, %f206, %f206, %f208;
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sqrt.rn.f32 %f210, %f209;
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rcp.rn.f32 %f211, %f210;
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mul.f32 %f17, %f204, %f211;
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mul.f32 %f18, %f205, %f211;
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mul.f32 %f19, %f206, %f211;
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ld.const.u64 %rd38, [params+128];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r68, [params+120];
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mad.lo.s32 %r69, %r68, %r55, %r54;
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mul.wide.u32 %rd40, %r69, 4;
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add.s64 %rd3, %rd39, %rd40;
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ld.const.u32 %r5, [params+540];
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setp.lt.s32 %p16, %r5, 1;
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@%p16 bra $L__BB0_34;
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cvt.rn.f32.s32 %f213, %r5;
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rcp.rn.f32 %f20, %f213;
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ld.global.u32 %r359, [%rd3];
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ld.const.f32 %f21, [params+536];
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ld.const.u8 %rs15, [params+104];
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and.b16 %rs16, %rs15, 32;
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setp.eq.s16 %p17, %rs16, 0;
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mov.u32 %r70, 0;
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selp.f32 %f22, 0f3F800000, 0f41200000, %p17;
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mul.f32 %f23, %f14, 0f3456BF95;
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mul.f32 %f24, %f15, 0f3456BF95;
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mul.f32 %f25, %f16, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f214, %f173, %f18;
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mul.f32 %f215, %f174, %f17;
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sub.f32 %f26, %f215, %f214;
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mul.f32 %f216, %f175, %f17;
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mul.f32 %f217, %f173, %f19;
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sub.f32 %f27, %f217, %f216;
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mul.f32 %f218, %f174, %f19;
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mul.f32 %f219, %f175, %f18;
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sub.f32 %f28, %f219, %f218;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd41, __cudart_i2opi_f;
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abs.f32 %f302, %f24;
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abs.f32 %f303, %f23;
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max.f32 %f304, %f303, %f302;
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abs.f32 %f305, %f25;
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max.f32 %f306, %f304, %f305;
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mov.u32 %r356, %r70;
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$L__BB0_7:
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cvt.rn.f32.s32 %f30, %r356;
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mov.u32 %r358, %r70;
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$L__BB0_8:
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mad.lo.s32 %r72, %r359, 1664525, 1013904223;
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and.b32 %r73, %r72, 16777215;
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cvt.rn.f32.u32 %f220, %r73;
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fma.rn.f32 %f221, %f220, 0f33800000, %f30;
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mul.f32 %f222, %f20, %f221;
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mad.lo.s32 %r359, %r72, 1664525, 1013904223;
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and.b32 %r74, %r359, 16777215;
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cvt.rn.f32.u32 %f223, %r74;
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cvt.rn.f32.s32 %f224, %r358;
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fma.rn.f32 %f225, %f223, 0f33800000, %f224;
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mul.f32 %f226, %f20, %f225;
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sqrt.rn.f32 %f32, %f222;
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mul.f32 %f33, %f226, 0f40C90FDB;
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mul.f32 %f227, %f33, 0f3F22F983;
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cvt.rni.s32.f32 %r366, %f227;
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cvt.rn.f32.s32 %f228, %r366;
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mov.f32 %f229, 0fBFC90FDA;
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fma.rn.f32 %f230, %f228, %f229, %f33;
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mov.f32 %f231, 0fB3A22168;
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fma.rn.f32 %f232, %f228, %f231, %f230;
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mov.f32 %f233, 0fA7C234C5;
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fma.rn.f32 %f1103, %f228, %f233, %f232;
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abs.f32 %f35, %f33;
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setp.ltu.f32 %p18, %f35, 0f47CE4780;
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mov.u32 %r363, %r366;
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mov.f32 %f1100, %f1103;
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@%p18 bra $L__BB0_16;
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setp.eq.f32 %p19, %f35, 0f7F800000;
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@%p19 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f236, 0f00000000;
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mul.rn.f32 %f1100, %f33, %f236;
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mov.u32 %r363, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r13, %f33;
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bfe.u32 %r76, %r13, 23, 8;
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add.s32 %r14, %r76, -128;
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shl.b32 %r77, %r13, 8;
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or.b32 %r15, %r77, -2147483648;
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shr.u32 %r16, %r14, 5;
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mov.u64 %rd118, 0;
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mov.u32 %r360, 0;
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mov.u64 %rd116, %rd1;
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mov.u64 %rd117, %rd41;
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$L__BB0_11:
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.pragma "nounroll";
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ld.global.nc.u32 %r78, [%rd117];
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mad.wide.u32 %rd43, %r78, %r15, %rd118;
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shr.u64 %rd118, %rd43, 32;
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st.local.u32 [%rd116], %rd43;
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add.s64 %rd117, %rd117, 4;
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add.s64 %rd116, %rd116, 4;
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add.s32 %r360, %r360, 1;
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setp.ne.s32 %p20, %r360, 6;
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@%p20 bra $L__BB0_11;
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st.local.u32 [%rd5], %rd118;
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mov.u32 %r79, 4;
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sub.s32 %r19, %r79, %r16;
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mov.u32 %r80, 6;
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sub.s32 %r81, %r80, %r16;
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mul.wide.s32 %rd44, %r81, 4;
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add.s64 %rd45, %rd1, %rd44;
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ld.local.u32 %r361, [%rd45];
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ld.local.u32 %r362, [%rd45+-4];
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and.b32 %r22, %r14, 31;
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setp.eq.s32 %p21, %r22, 0;
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@%p21 bra $L__BB0_14;
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mov.u32 %r82, 32;
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sub.s32 %r83, %r82, %r22;
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shr.u32 %r84, %r362, %r83;
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shl.b32 %r85, %r361, %r22;
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add.s32 %r361, %r84, %r85;
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mul.wide.s32 %rd46, %r19, 4;
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add.s64 %rd47, %rd1, %rd46;
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ld.local.u32 %r86, [%rd47];
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shr.u32 %r87, %r86, %r83;
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shl.b32 %r88, %r362, %r22;
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add.s32 %r362, %r87, %r88;
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$L__BB0_14:
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and.b32 %r89, %r13, -2147483648;
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shr.u32 %r90, %r362, 30;
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shl.b32 %r91, %r361, 2;
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or.b32 %r92, %r90, %r91;
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shr.u32 %r93, %r92, 31;
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shr.u32 %r94, %r361, 30;
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add.s32 %r95, %r93, %r94;
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neg.s32 %r96, %r95;
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setp.eq.s32 %p22, %r89, 0;
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selp.b32 %r363, %r95, %r96, %p22;
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setp.ne.s32 %p23, %r93, 0;
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xor.b32 %r97, %r89, -2147483648;
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selp.b32 %r98, %r97, %r89, %p23;
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selp.b32 %r99, -1, 0, %p23;
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xor.b32 %r100, %r92, %r99;
|
|
shl.b32 %r101, %r362, 2;
|
|
xor.b32 %r102, %r101, %r99;
|
|
cvt.u64.u32 %rd48, %r100;
|
|
cvt.u64.u32 %rd49, %r102;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f234, %fd2;
|
|
setp.eq.s32 %p24, %r98, 0;
|
|
neg.f32 %f235, %f234;
|
|
selp.f32 %f1100, %f234, %f235, %p24;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r29, %r363, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p25, %r30, 0;
|
|
selp.f32 %f39, %f1100, 0f3F800000, %p25;
|
|
mul.rn.f32 %f40, %f1100, %f1100;
|
|
mov.f32 %f1101, 0fB94D4153;
|
|
@%p25 bra $L__BB0_18;
|
|
|
|
mov.f32 %f238, 0fBAB607ED;
|
|
mov.f32 %f239, 0f37CBAC00;
|
|
fma.rn.f32 %f1101, %f239, %f40, %f238;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f240, 0f3C0885E4, 0f3D2AAABB, %p25;
|
|
fma.rn.f32 %f241, %f1101, %f40, %f240;
|
|
selp.f32 %f242, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
|
|
fma.rn.f32 %f243, %f241, %f40, %f242;
|
|
mov.f32 %f244, 0f00000000;
|
|
fma.rn.f32 %f245, %f40, %f39, %f244;
|
|
fma.rn.f32 %f1102, %f243, %f245, %f39;
|
|
and.b32 %r104, %r29, 2;
|
|
setp.eq.s32 %p27, %r104, 0;
|
|
@%p27 bra $L__BB0_20;
|
|
|
|
mov.f32 %f247, 0fBF800000;
|
|
fma.rn.f32 %f1102, %f1102, %f247, %f244;
|
|
|
|
$L__BB0_20:
|
|
@%p18 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p29, %f35, 0f7F800000;
|
|
@%p29 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f250, 0f00000000;
|
|
mul.rn.f32 %f1103, %f33, %f250;
|
|
mov.u32 %r366, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r31, %f33;
|
|
bfe.u32 %r105, %r31, 23, 8;
|
|
add.s32 %r32, %r105, -128;
|
|
shl.b32 %r106, %r31, 8;
|
|
or.b32 %r33, %r106, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd119, 0;
|
|
mov.u64 %rd120, %rd119;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd119, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r107, [%rd55];
|
|
mad.wide.u32 %rd56, %r107, %r33, %rd120;
|
|
shr.u64 %rd120, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r108, %rd119;
|
|
add.s32 %r109, %r108, 1;
|
|
cvt.s64.s32 %rd119, %r109;
|
|
setp.ne.s32 %p30, %r109, 6;
|
|
@%p30 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd120;
|
|
mov.u32 %r110, 4;
|
|
sub.s32 %r35, %r110, %r34;
|
|
mov.u32 %r111, 6;
|
|
sub.s32 %r112, %r111, %r34;
|
|
mul.wide.s32 %rd58, %r112, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r364, [%rd59];
|
|
ld.local.u32 %r365, [%rd59+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p31, %r38, 0;
|
|
@%p31 bra $L__BB0_26;
|
|
|
|
mov.u32 %r113, 32;
|
|
sub.s32 %r114, %r113, %r38;
|
|
shr.u32 %r115, %r365, %r114;
|
|
shl.b32 %r116, %r364, %r38;
|
|
add.s32 %r364, %r115, %r116;
|
|
mul.wide.s32 %rd60, %r35, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r117, [%rd61];
|
|
shr.u32 %r118, %r117, %r114;
|
|
shl.b32 %r119, %r365, %r38;
|
|
add.s32 %r365, %r118, %r119;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r120, %r31, -2147483648;
|
|
shr.u32 %r121, %r365, 30;
|
|
shl.b32 %r122, %r364, 2;
|
|
or.b32 %r123, %r121, %r122;
|
|
shr.u32 %r124, %r123, 31;
|
|
shr.u32 %r125, %r364, 30;
|
|
add.s32 %r126, %r124, %r125;
|
|
neg.s32 %r127, %r126;
|
|
setp.eq.s32 %p32, %r120, 0;
|
|
selp.b32 %r366, %r126, %r127, %p32;
|
|
setp.ne.s32 %p33, %r124, 0;
|
|
xor.b32 %r128, %r120, -2147483648;
|
|
selp.b32 %r129, %r128, %r120, %p33;
|
|
selp.b32 %r130, -1, 0, %p33;
|
|
xor.b32 %r131, %r123, %r130;
|
|
shl.b32 %r132, %r365, 2;
|
|
xor.b32 %r133, %r132, %r130;
|
|
cvt.u64.u32 %rd62, %r131;
|
|
cvt.u64.u32 %rd63, %r133;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f248, %fd4;
|
|
setp.eq.s32 %p34, %r129, 0;
|
|
neg.f32 %f249, %f248;
|
|
selp.f32 %f1103, %f248, %f249, %p34;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f49, %f32, %f1102;
|
|
and.b32 %r45, %r366, 1;
|
|
setp.eq.s32 %p35, %r45, 0;
|
|
selp.f32 %f50, %f1103, 0f3F800000, %p35;
|
|
mul.rn.f32 %f51, %f1103, %f1103;
|
|
mov.f32 %f1104, 0fB94D4153;
|
|
@%p35 bra $L__BB0_30;
|
|
|
|
mov.f32 %f252, 0fBAB607ED;
|
|
mov.f32 %f253, 0f37CBAC00;
|
|
fma.rn.f32 %f1104, %f253, %f51, %f252;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f254, 0f3C0885E4, 0f3D2AAABB, %p35;
|
|
fma.rn.f32 %f255, %f1104, %f51, %f254;
|
|
selp.f32 %f256, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
|
|
fma.rn.f32 %f257, %f255, %f51, %f256;
|
|
mov.f32 %f258, 0f00000000;
|
|
fma.rn.f32 %f259, %f51, %f50, %f258;
|
|
fma.rn.f32 %f1105, %f257, %f259, %f50;
|
|
and.b32 %r135, %r366, 2;
|
|
setp.eq.s32 %p37, %r135, 0;
|
|
@%p37 bra $L__BB0_32;
|
|
|
|
mov.f32 %f261, 0fBF800000;
|
|
fma.rn.f32 %f1105, %f1105, %f261, %f258;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f271, %f49, %f49;
|
|
mov.f32 %f272, 0f3F800000;
|
|
sub.f32 %f273, %f272, %f271;
|
|
mul.f32 %f274, %f32, %f1105;
|
|
mul.f32 %f275, %f274, %f274;
|
|
sub.f32 %f276, %f273, %f275;
|
|
max.f32 %f277, %f258, %f276;
|
|
sqrt.rn.f32 %f278, %f277;
|
|
mul.f32 %f279, %f17, %f274;
|
|
mul.f32 %f280, %f18, %f274;
|
|
mul.f32 %f281, %f19, %f274;
|
|
fma.rn.f32 %f282, %f28, %f49, %f279;
|
|
fma.rn.f32 %f283, %f27, %f49, %f280;
|
|
fma.rn.f32 %f284, %f26, %f49, %f281;
|
|
fma.rn.f32 %f285, %f173, %f278, %f282;
|
|
fma.rn.f32 %f286, %f174, %f278, %f283;
|
|
fma.rn.f32 %f287, %f175, %f278, %f284;
|
|
add.f32 %f288, %f173, %f285;
|
|
add.f32 %f289, %f174, %f286;
|
|
add.f32 %f290, %f175, %f287;
|
|
mul.f32 %f291, %f21, %f288;
|
|
mul.f32 %f292, %f21, %f289;
|
|
mul.f32 %f293, %f21, %f290;
|
|
sub.f32 %f294, %f291, %f173;
|
|
sub.f32 %f295, %f292, %f174;
|
|
sub.f32 %f296, %f293, %f175;
|
|
mul.f32 %f297, %f295, %f295;
|
|
fma.rn.f32 %f298, %f294, %f294, %f297;
|
|
fma.rn.f32 %f299, %f296, %f296, %f298;
|
|
sqrt.rn.f32 %f300, %f299;
|
|
rcp.rn.f32 %f301, %f300;
|
|
mul.f32 %f265, %f301, %f294;
|
|
mul.f32 %f266, %f301, %f295;
|
|
mul.f32 %f267, %f301, %f296;
|
|
mov.f32 %f307, 0f38D1B717;
|
|
max.f32 %f308, %f306, %f307;
|
|
mul.f32 %f268, %f22, %f308;
|
|
mov.f32 %f269, 0f6C4ECB8F;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r174, 1;
|
|
mov.u32 %r175, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f14,%f15,%f16,%f265,%f266,%f267,%f268,%f269,%f258,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f309, %r136;
|
|
add.f32 %f1099, %f1099, %f309;
|
|
add.s32 %r358, %r358, 1;
|
|
setp.lt.s32 %p38, %r358, %r5;
|
|
@%p38 bra $L__BB0_8;
|
|
|
|
add.s32 %r356, %r356, 1;
|
|
setp.lt.s32 %p39, %r356, %r5;
|
|
@%p39 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
setp.eq.s32 %p40, %r5, 0;
|
|
mov.f32 %f1107, 0f3F800000;
|
|
@%p40 bra $L__BB0_36;
|
|
|
|
mul.lo.s32 %r207, %r5, %r5;
|
|
cvt.rn.f32.s32 %f311, %r207;
|
|
div.rn.f32 %f1107, %f1099, %f311;
|
|
|
|
$L__BB0_36:
|
|
ld.const.f32 %f312, [params+524];
|
|
mul.f32 %f313, %f1107, %f312;
|
|
ld.const.v2.f32 {%f314, %f315}, [params+528];
|
|
mul.f32 %f318, %f1107, %f314;
|
|
mul.f32 %f319, %f1107, %f315;
|
|
cvt.sat.f32.f32 %f320, %f13;
|
|
mul.f32 %f61, %f313, %f320;
|
|
mul.f32 %f62, %f318, %f320;
|
|
mul.f32 %f63, %f319, %f320;
|
|
mul.f32 %f321, %f13, 0f40800000;
|
|
cvt.sat.f32.f32 %f322, %f321;
|
|
mul.f32 %f323, %f313, %f322;
|
|
mul.f32 %f324, %f318, %f322;
|
|
mul.f32 %f325, %f319, %f322;
|
|
mul.f32 %f64, %f323, 0f3E800000;
|
|
mul.f32 %f65, %f324, 0f3E800000;
|
|
mul.f32 %f66, %f325, 0f3E800000;
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r208, %r48, 8;
|
|
setp.eq.s32 %p41, %r208, 0;
|
|
@%p41 bra $L__BB0_50;
|
|
|
|
mov.f32 %f330, 0f3EE8BA2E;
|
|
abs.f32 %f68, %f1107;
|
|
setp.lt.f32 %p42, %f68, 0f00800000;
|
|
mul.f32 %f332, %f68, 0f4B800000;
|
|
selp.f32 %f333, %f332, %f68, %p42;
|
|
selp.f32 %f334, 0fC3170000, 0fC2FE0000, %p42;
|
|
mov.b32 %r211, %f333;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f335, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f336, %r214;
|
|
add.f32 %f337, %f334, %f336;
|
|
setp.gt.f32 %p43, %f335, 0f3FB504F3;
|
|
mul.f32 %f338, %f335, 0f3F000000;
|
|
add.f32 %f339, %f337, 0f3F800000;
|
|
selp.f32 %f340, %f339, %f337, %p43;
|
|
selp.f32 %f341, %f338, %f335, %p43;
|
|
add.f32 %f342, %f341, 0fBF800000;
|
|
add.f32 %f343, %f341, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f344, %f343;
|
|
add.f32 %f345, %f342, %f342;
|
|
mul.f32 %f346, %f345, %f344;
|
|
mul.f32 %f347, %f346, %f346;
|
|
mov.f32 %f348, 0f3C4CAF63;
|
|
mov.f32 %f349, 0f3B18F0FE;
|
|
fma.rn.f32 %f350, %f349, %f347, %f348;
|
|
mov.f32 %f351, 0f3DAAAABD;
|
|
fma.rn.f32 %f352, %f350, %f347, %f351;
|
|
mul.rn.f32 %f353, %f352, %f347;
|
|
mul.rn.f32 %f354, %f353, %f346;
|
|
sub.f32 %f355, %f342, %f346;
|
|
add.f32 %f356, %f355, %f355;
|
|
neg.f32 %f357, %f346;
|
|
fma.rn.f32 %f358, %f357, %f342, %f356;
|
|
mul.rn.f32 %f359, %f344, %f358;
|
|
add.f32 %f360, %f354, %f346;
|
|
sub.f32 %f361, %f346, %f360;
|
|
add.f32 %f362, %f354, %f361;
|
|
add.f32 %f363, %f359, %f362;
|
|
add.f32 %f364, %f360, %f363;
|
|
sub.f32 %f365, %f360, %f364;
|
|
add.f32 %f366, %f363, %f365;
|
|
mov.f32 %f367, 0f3F317200;
|
|
mul.rn.f32 %f368, %f340, %f367;
|
|
mov.f32 %f369, 0f35BFBE8E;
|
|
mul.rn.f32 %f370, %f340, %f369;
|
|
add.f32 %f371, %f368, %f364;
|
|
sub.f32 %f372, %f368, %f371;
|
|
add.f32 %f373, %f364, %f372;
|
|
add.f32 %f374, %f366, %f373;
|
|
add.f32 %f375, %f370, %f374;
|
|
add.f32 %f376, %f371, %f375;
|
|
sub.f32 %f377, %f371, %f376;
|
|
add.f32 %f378, %f375, %f377;
|
|
mul.rn.f32 %f379, %f330, %f376;
|
|
neg.f32 %f380, %f379;
|
|
fma.rn.f32 %f381, %f330, %f376, %f380;
|
|
fma.rn.f32 %f382, %f330, %f378, %f381;
|
|
mov.f32 %f383, 0f00000000;
|
|
fma.rn.f32 %f384, %f383, %f376, %f382;
|
|
add.rn.f32 %f385, %f379, %f384;
|
|
neg.f32 %f386, %f385;
|
|
add.rn.f32 %f387, %f379, %f386;
|
|
add.rn.f32 %f388, %f387, %f384;
|
|
mov.b32 %r215, %f385;
|
|
setp.eq.s32 %p44, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f389, %r216;
|
|
add.f32 %f390, %f388, 0f37000000;
|
|
selp.f32 %f69, %f390, %f388, %p44;
|
|
selp.f32 %f391, %f389, %f385, %p44;
|
|
mov.f32 %f392, 0f3FB8AA3B;
|
|
mul.rn.f32 %f393, %f391, %f392;
|
|
cvt.rzi.f32.f32 %f394, %f393;
|
|
abs.f32 %f395, %f394;
|
|
setp.gt.f32 %p45, %f395, 0f42FC0000;
|
|
mov.b32 %r217, %f394;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f396, %r219;
|
|
selp.f32 %f397, %f396, %f394, %p45;
|
|
mov.f32 %f398, 0fBF317218;
|
|
fma.rn.f32 %f399, %f397, %f398, %f391;
|
|
mov.f32 %f400, 0f3102E308;
|
|
fma.rn.f32 %f401, %f397, %f400, %f399;
|
|
mul.f32 %f402, %f401, 0f3FB8AA3B;
|
|
add.f32 %f403, %f397, 0f4B40007F;
|
|
mov.b32 %r220, %f403;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f404, %r221;
|
|
ex2.approx.ftz.f32 %f405, %f402;
|
|
mul.f32 %f70, %f405, %f404;
|
|
setp.eq.f32 %p46, %f70, 0f7F800000;
|
|
mov.f32 %f1108, 0f7F800000;
|
|
@%p46 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1108, %f70, %f69, %f70;
|
|
|
|
$L__BB0_39:
|
|
mov.f32 %f1058, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f1057, %f1058;
|
|
add.f32 %f1056, %f1057, %f1057;
|
|
mov.f32 %f1055, 0f3EE8BA2E;
|
|
sub.f32 %f1054, %f1055, %f1056;
|
|
abs.f32 %f1053, %f1054;
|
|
setp.lt.f32 %p47, %f1107, 0f00000000;
|
|
setp.eq.f32 %p48, %f1053, 0f3F800000;
|
|
and.pred %p1, %p47, %p48;
|
|
setp.eq.f32 %p49, %f1107, 0f00000000;
|
|
@%p49 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f410, %f1107, %f1107;
|
|
selp.f32 %f1110, %f410, 0f00000000, %p48;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_147:
|
|
mov.f32 %f1010, 0f00000000;
|
|
mov.u32 %r368, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1010;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs115, 0;
|
|
st.global.v4.u16 [%rd25], {%rs112, %rs113, %rs114, %rs115};
|
|
|
|
$L__BB0_148:
|
|
ld.const.u64 %rd98, [params+256];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r342, [params+248];
|
|
mad.lo.s32 %r343, %r342, %r4, %r3;
|
|
mul.wide.u32 %rd100, %r343, 8;
|
|
add.s64 %rd26, %rd99, %rd100;
|
|
setp.eq.s32 %p167, %r368, 0;
|
|
@%p167 bra $L__BB0_150;
|
|
|
|
ld.global.v4.u16 {%rs122, %rs123, %rs124, %rs125}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1011, %rs122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1012, %rs123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1013, %rs124;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1014, %f1011, 0f00000000;
|
|
add.f32 %f1015, %f1012, 0f00000000;
|
|
add.f32 %f1016, %f1013, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1016;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1015;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1014;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs126, 0;
|
|
st.global.v4.u16 [%rd26], {%rs119, %rs120, %rs121, %rs126};
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_150:
|
|
mov.f32 %f1019, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1019;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1019;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1019;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs130, 0;
|
|
st.global.v4.u16 [%rd26], {%rs127, %rs128, %rs129, %rs130};
|
|
|
|
$L__BB0_151:
|
|
ld.const.u64 %rd101, [params+272];
|
|
cvta.to.global.u64 %rd102, %rd101;
|
|
ld.const.u32 %r344, [params+264];
|
|
mad.lo.s32 %r345, %r344, %r4, %r3;
|
|
mul.wide.u32 %rd103, %r345, 8;
|
|
add.s64 %rd27, %rd102, %rd103;
|
|
@%p167 bra $L__BB0_153;
|
|
|
|
ld.global.v4.u16 {%rs137, %rs138, %rs139, %rs140}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1020, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1021, %rs138;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1022, %rs139;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1023, %f1020, 0f00000000;
|
|
add.f32 %f1024, %f1021, 0f00000000;
|
|
add.f32 %f1025, %f1022, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1025;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1024;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1023;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs141, 0;
|
|
st.global.v4.u16 [%rd27], {%rs134, %rs135, %rs136, %rs141};
|
|
bra.uni $L__BB0_154;
|
|
|
|
$L__BB0_153:
|
|
mov.f32 %f1028, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1028;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1028;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1028;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs145, 0;
|
|
st.global.v4.u16 [%rd27], {%rs142, %rs143, %rs144, %rs145};
|
|
|
|
$L__BB0_154:
|
|
ld.const.u64 %rd104, [params+288];
|
|
cvta.to.global.u64 %rd105, %rd104;
|
|
ld.const.u32 %r346, [params+280];
|
|
mad.lo.s32 %r347, %r346, %r4, %r3;
|
|
mul.wide.u32 %rd106, %r347, 8;
|
|
add.s64 %rd28, %rd105, %rd106;
|
|
@%p167 bra $L__BB0_156;
|
|
|
|
ld.global.v4.u16 {%rs152, %rs153, %rs154, %rs155}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1029, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1030, %rs153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1031, %rs154;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1032, %f1029, 0f00000000;
|
|
add.f32 %f1033, %f1030, 0f00000000;
|
|
add.f32 %f1034, %f1031, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1034;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1033;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1032;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs156, 0;
|
|
st.global.v4.u16 [%rd28], {%rs149, %rs150, %rs151, %rs156};
|
|
bra.uni $L__BB0_157;
|
|
|
|
$L__BB0_156:
|
|
mov.f32 %f1037, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1037;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs160, 0;
|
|
st.global.v4.u16 [%rd28], {%rs157, %rs158, %rs159, %rs160};
|
|
|
|
$L__BB0_157:
|
|
ld.const.u64 %rd107, [params+304];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r348, [params+296];
|
|
mad.lo.s32 %r349, %r348, %r4, %r3;
|
|
mul.wide.u32 %rd109, %r349, 8;
|
|
add.s64 %rd29, %rd108, %rd109;
|
|
@%p167 bra $L__BB0_159;
|
|
|
|
ld.global.v4.u16 {%rs167, %rs168, %rs169, %rs170}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1038, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1039, %rs168;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1040, %rs169;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1041, %f1038, 0f00000000;
|
|
add.f32 %f1042, %f1039, 0f00000000;
|
|
add.f32 %f1043, %f1040, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1043;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1042;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1041;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs171, 0;
|
|
st.global.v4.u16 [%rd29], {%rs164, %rs165, %rs166, %rs171};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_159:
|
|
mov.f32 %f1046, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs174, %f1046;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1046;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1046;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs175, 0;
|
|
st.global.v4.u16 [%rd29], {%rs172, %rs173, %rs174, %rs175};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r222, %f1108;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f406, %r223;
|
|
selp.f32 %f1110, %f406, %f1108, %p1;
|
|
setp.geu.f32 %p50, %f1107, 0f00000000;
|
|
@%p50 bra $L__BB0_44;
|
|
|
|
mov.f32 %f407, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f408, %f407;
|
|
setp.eq.f32 %p51, %f408, 0f3EE8BA2E;
|
|
@%p51 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1110, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
abs.f32 %f1059, %f1107;
|
|
add.f32 %f411, %f1059, 0f3EE8BA2E;
|
|
mov.b32 %r224, %f411;
|
|
setp.lt.s32 %p53, %r224, 2139095040;
|
|
@%p53 bra $L__BB0_49;
|
|
|
|
abs.f32 %f1060, %f1107;
|
|
setp.gtu.f32 %p54, %f1060, 0f7F800000;
|
|
@%p54 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1110, %f1107, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f1061, %f1107;
|
|
setp.neu.f32 %p55, %f1061, 0f7F800000;
|
|
@%p55 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1110, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
ld.const.u64 %rd115, [params+192];
|
|
cvta.to.global.u64 %rd114, %rd115;
|
|
ld.const.u32 %r354, [params+184];
|
|
mad.lo.s32 %r353, %r354, %r4, %r3;
|
|
cvt.u64.u32 %rd113, %r353;
|
|
mul.f32 %f412, %f1110, 0f437F0000;
|
|
setp.eq.f32 %p56, %f1107, 0f3F800000;
|
|
selp.f32 %f413, 0f437F0000, %f412, %p56;
|
|
cvt.rzi.u32.f32 %r225, %f413;
|
|
shl.b64 %rd67, %rd113, 1;
|
|
add.s64 %rd68, %rd114, %rd67;
|
|
cvt.u16.u32 %rs17, %r225;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v2.u8 [%rd68], {%rs17, %rs18};
|
|
|
|
$L__BB0_50:
|
|
ld.const.u32 %r355, [params+104];
|
|
and.b32 %r226, %r355, 1;
|
|
setp.eq.b32 %p57, %r226, 1;
|
|
mov.pred %p58, 0;
|
|
xor.pred %p59, %p57, %p58;
|
|
not.pred %p60, %p59;
|
|
@%p60 bra $L__BB0_124;
|
|
|
|
mov.f32 %f418, 0f3EE66666;
|
|
abs.f32 %f80, %f61;
|
|
setp.lt.f32 %p61, %f80, 0f00800000;
|
|
mul.f32 %f420, %f80, 0f4B800000;
|
|
selp.f32 %f421, %f420, %f80, %p61;
|
|
selp.f32 %f422, 0fC3170000, 0fC2FE0000, %p61;
|
|
mov.b32 %r227, %f421;
|
|
and.b32 %r228, %r227, 8388607;
|
|
or.b32 %r229, %r228, 1065353216;
|
|
mov.b32 %f423, %r229;
|
|
shr.u32 %r230, %r227, 23;
|
|
cvt.rn.f32.u32 %f424, %r230;
|
|
add.f32 %f425, %f422, %f424;
|
|
setp.gt.f32 %p62, %f423, 0f3FB504F3;
|
|
mul.f32 %f426, %f423, 0f3F000000;
|
|
add.f32 %f427, %f425, 0f3F800000;
|
|
selp.f32 %f428, %f427, %f425, %p62;
|
|
selp.f32 %f429, %f426, %f423, %p62;
|
|
add.f32 %f430, %f429, 0fBF800000;
|
|
add.f32 %f431, %f429, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f432, %f431;
|
|
add.f32 %f433, %f430, %f430;
|
|
mul.f32 %f434, %f433, %f432;
|
|
mul.f32 %f435, %f434, %f434;
|
|
mov.f32 %f436, 0f3C4CAF63;
|
|
mov.f32 %f437, 0f3B18F0FE;
|
|
fma.rn.f32 %f438, %f437, %f435, %f436;
|
|
mov.f32 %f439, 0f3DAAAABD;
|
|
fma.rn.f32 %f440, %f438, %f435, %f439;
|
|
mul.rn.f32 %f441, %f440, %f435;
|
|
mul.rn.f32 %f442, %f441, %f434;
|
|
sub.f32 %f443, %f430, %f434;
|
|
add.f32 %f444, %f443, %f443;
|
|
neg.f32 %f445, %f434;
|
|
fma.rn.f32 %f446, %f445, %f430, %f444;
|
|
mul.rn.f32 %f447, %f432, %f446;
|
|
add.f32 %f448, %f442, %f434;
|
|
sub.f32 %f449, %f434, %f448;
|
|
add.f32 %f450, %f442, %f449;
|
|
add.f32 %f451, %f447, %f450;
|
|
add.f32 %f452, %f448, %f451;
|
|
sub.f32 %f453, %f448, %f452;
|
|
add.f32 %f454, %f451, %f453;
|
|
mov.f32 %f455, 0f3F317200;
|
|
mul.rn.f32 %f456, %f428, %f455;
|
|
mov.f32 %f457, 0f35BFBE8E;
|
|
mul.rn.f32 %f458, %f428, %f457;
|
|
add.f32 %f459, %f456, %f452;
|
|
sub.f32 %f460, %f456, %f459;
|
|
add.f32 %f461, %f452, %f460;
|
|
add.f32 %f462, %f454, %f461;
|
|
add.f32 %f463, %f458, %f462;
|
|
add.f32 %f464, %f459, %f463;
|
|
sub.f32 %f465, %f459, %f464;
|
|
add.f32 %f466, %f463, %f465;
|
|
mul.rn.f32 %f467, %f418, %f464;
|
|
neg.f32 %f468, %f467;
|
|
fma.rn.f32 %f469, %f418, %f464, %f468;
|
|
fma.rn.f32 %f470, %f418, %f466, %f469;
|
|
mov.f32 %f471, 0f00000000;
|
|
fma.rn.f32 %f472, %f471, %f464, %f470;
|
|
add.rn.f32 %f473, %f467, %f472;
|
|
neg.f32 %f474, %f473;
|
|
add.rn.f32 %f475, %f467, %f474;
|
|
add.rn.f32 %f476, %f475, %f472;
|
|
mov.b32 %r231, %f473;
|
|
setp.eq.s32 %p63, %r231, 1118925336;
|
|
add.s32 %r232, %r231, -1;
|
|
mov.b32 %f477, %r232;
|
|
add.f32 %f478, %f476, 0f37000000;
|
|
selp.f32 %f81, %f478, %f476, %p63;
|
|
selp.f32 %f479, %f477, %f473, %p63;
|
|
mov.f32 %f480, 0f3FB8AA3B;
|
|
mul.rn.f32 %f481, %f479, %f480;
|
|
cvt.rzi.f32.f32 %f482, %f481;
|
|
abs.f32 %f483, %f482;
|
|
setp.gt.f32 %p64, %f483, 0f42FC0000;
|
|
mov.b32 %r233, %f482;
|
|
and.b32 %r234, %r233, -2147483648;
|
|
or.b32 %r235, %r234, 1123811328;
|
|
mov.b32 %f484, %r235;
|
|
selp.f32 %f485, %f484, %f482, %p64;
|
|
mov.f32 %f486, 0fBF317218;
|
|
fma.rn.f32 %f487, %f485, %f486, %f479;
|
|
mov.f32 %f488, 0f3102E308;
|
|
fma.rn.f32 %f489, %f485, %f488, %f487;
|
|
mul.f32 %f490, %f489, 0f3FB8AA3B;
|
|
add.f32 %f491, %f485, 0f4B40007F;
|
|
mov.b32 %r236, %f491;
|
|
shl.b32 %r237, %r236, 23;
|
|
mov.b32 %f492, %r237;
|
|
ex2.approx.ftz.f32 %f493, %f490;
|
|
mul.f32 %f82, %f493, %f492;
|
|
setp.eq.f32 %p65, %f82, 0f7F800000;
|
|
mov.f32 %f1111, 0f7F800000;
|
|
@%p65 bra $L__BB0_53;
|
|
|
|
fma.rn.f32 %f1111, %f82, %f81, %f82;
|
|
|
|
$L__BB0_53:
|
|
mov.f32 %f1067, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1066, %f1067;
|
|
add.f32 %f1065, %f1066, %f1066;
|
|
mov.f32 %f1064, 0f3EE66666;
|
|
sub.f32 %f1063, %f1064, %f1065;
|
|
abs.f32 %f1062, %f1063;
|
|
setp.lt.f32 %p66, %f61, 0f00000000;
|
|
setp.eq.f32 %p67, %f1062, 0f3F800000;
|
|
and.pred %p2, %p66, %p67;
|
|
setp.eq.f32 %p68, %f61, 0f00000000;
|
|
@%p68 bra $L__BB0_57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f498, %f61, %f61;
|
|
selp.f32 %f1113, %f498, 0f00000000, %p67;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_54:
|
|
mov.b32 %r238, %f1111;
|
|
xor.b32 %r239, %r238, -2147483648;
|
|
mov.b32 %f494, %r239;
|
|
selp.f32 %f1113, %f494, %f1111, %p2;
|
|
setp.geu.f32 %p69, %f61, 0f00000000;
|
|
@%p69 bra $L__BB0_58;
|
|
|
|
mov.f32 %f495, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f496, %f495;
|
|
setp.eq.f32 %p70, %f496, 0f3EE66666;
|
|
@%p70 bra $L__BB0_58;
|
|
|
|
mov.f32 %f1113, 0f7FFFFFFF;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1068, %f61;
|
|
add.f32 %f499, %f1068, 0f3EE66666;
|
|
mov.b32 %r240, %f499;
|
|
setp.lt.s32 %p72, %r240, 2139095040;
|
|
@%p72 bra $L__BB0_63;
|
|
|
|
abs.f32 %f1069, %f61;
|
|
setp.gtu.f32 %p73, %f1069, 0f7F800000;
|
|
@%p73 bra $L__BB0_62;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1113, %f61, 0f3EE66666;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f1070, %f61;
|
|
setp.neu.f32 %p74, %f1070, 0f7F800000;
|
|
@%p74 bra $L__BB0_63;
|
|
|
|
selp.f32 %f1113, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_63:
|
|
setp.eq.f32 %p75, %f61, 0f3F800000;
|
|
selp.f32 %f91, 0f3F800000, %f1113, %p75;
|
|
abs.f32 %f92, %f62;
|
|
setp.lt.f32 %p76, %f92, 0f00800000;
|
|
mul.f32 %f501, %f92, 0f4B800000;
|
|
selp.f32 %f502, %f501, %f92, %p76;
|
|
selp.f32 %f503, 0fC3170000, 0fC2FE0000, %p76;
|
|
mov.b32 %r241, %f502;
|
|
and.b32 %r242, %r241, 8388607;
|
|
or.b32 %r243, %r242, 1065353216;
|
|
mov.b32 %f504, %r243;
|
|
shr.u32 %r244, %r241, 23;
|
|
cvt.rn.f32.u32 %f505, %r244;
|
|
add.f32 %f506, %f503, %f505;
|
|
setp.gt.f32 %p77, %f504, 0f3FB504F3;
|
|
mul.f32 %f507, %f504, 0f3F000000;
|
|
add.f32 %f508, %f506, 0f3F800000;
|
|
selp.f32 %f509, %f508, %f506, %p77;
|
|
selp.f32 %f510, %f507, %f504, %p77;
|
|
add.f32 %f511, %f510, 0fBF800000;
|
|
add.f32 %f512, %f510, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f513, %f512;
|
|
add.f32 %f514, %f511, %f511;
|
|
mul.f32 %f515, %f514, %f513;
|
|
mul.f32 %f516, %f515, %f515;
|
|
mov.f32 %f517, 0f3C4CAF63;
|
|
mov.f32 %f518, 0f3B18F0FE;
|
|
fma.rn.f32 %f519, %f518, %f516, %f517;
|
|
mov.f32 %f520, 0f3DAAAABD;
|
|
fma.rn.f32 %f521, %f519, %f516, %f520;
|
|
mul.rn.f32 %f522, %f521, %f516;
|
|
mul.rn.f32 %f523, %f522, %f515;
|
|
sub.f32 %f524, %f511, %f515;
|
|
add.f32 %f525, %f524, %f524;
|
|
neg.f32 %f526, %f515;
|
|
fma.rn.f32 %f527, %f526, %f511, %f525;
|
|
mul.rn.f32 %f528, %f513, %f527;
|
|
add.f32 %f529, %f523, %f515;
|
|
sub.f32 %f530, %f515, %f529;
|
|
add.f32 %f531, %f523, %f530;
|
|
add.f32 %f532, %f528, %f531;
|
|
add.f32 %f533, %f529, %f532;
|
|
sub.f32 %f534, %f529, %f533;
|
|
add.f32 %f535, %f532, %f534;
|
|
mov.f32 %f536, 0f3F317200;
|
|
mul.rn.f32 %f537, %f509, %f536;
|
|
mov.f32 %f538, 0f35BFBE8E;
|
|
mul.rn.f32 %f539, %f509, %f538;
|
|
add.f32 %f540, %f537, %f533;
|
|
sub.f32 %f541, %f537, %f540;
|
|
add.f32 %f542, %f533, %f541;
|
|
add.f32 %f543, %f535, %f542;
|
|
add.f32 %f544, %f539, %f543;
|
|
add.f32 %f545, %f540, %f544;
|
|
sub.f32 %f546, %f540, %f545;
|
|
add.f32 %f547, %f544, %f546;
|
|
mov.f32 %f548, 0f3EE66666;
|
|
mul.rn.f32 %f549, %f548, %f545;
|
|
neg.f32 %f550, %f549;
|
|
fma.rn.f32 %f551, %f548, %f545, %f550;
|
|
fma.rn.f32 %f552, %f548, %f547, %f551;
|
|
mov.f32 %f553, 0f00000000;
|
|
fma.rn.f32 %f554, %f553, %f545, %f552;
|
|
add.rn.f32 %f555, %f549, %f554;
|
|
neg.f32 %f556, %f555;
|
|
add.rn.f32 %f557, %f549, %f556;
|
|
add.rn.f32 %f558, %f557, %f554;
|
|
mov.b32 %r245, %f555;
|
|
setp.eq.s32 %p78, %r245, 1118925336;
|
|
add.s32 %r246, %r245, -1;
|
|
mov.b32 %f559, %r246;
|
|
add.f32 %f560, %f558, 0f37000000;
|
|
selp.f32 %f93, %f560, %f558, %p78;
|
|
selp.f32 %f561, %f559, %f555, %p78;
|
|
mov.f32 %f562, 0f3FB8AA3B;
|
|
mul.rn.f32 %f563, %f561, %f562;
|
|
cvt.rzi.f32.f32 %f564, %f563;
|
|
abs.f32 %f565, %f564;
|
|
setp.gt.f32 %p79, %f565, 0f42FC0000;
|
|
mov.b32 %r247, %f564;
|
|
and.b32 %r248, %r247, -2147483648;
|
|
or.b32 %r249, %r248, 1123811328;
|
|
mov.b32 %f566, %r249;
|
|
selp.f32 %f567, %f566, %f564, %p79;
|
|
mov.f32 %f568, 0fBF317218;
|
|
fma.rn.f32 %f569, %f567, %f568, %f561;
|
|
mov.f32 %f570, 0f3102E308;
|
|
fma.rn.f32 %f571, %f567, %f570, %f569;
|
|
mul.f32 %f572, %f571, 0f3FB8AA3B;
|
|
add.f32 %f573, %f567, 0f4B40007F;
|
|
mov.b32 %r250, %f573;
|
|
shl.b32 %r251, %r250, 23;
|
|
mov.b32 %f574, %r251;
|
|
ex2.approx.ftz.f32 %f575, %f572;
|
|
mul.f32 %f94, %f575, %f574;
|
|
setp.eq.f32 %p80, %f94, 0f7F800000;
|
|
mov.f32 %f1114, 0f7F800000;
|
|
@%p80 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1114, %f94, %f93, %f94;
|
|
|
|
$L__BB0_65:
|
|
setp.lt.f32 %p81, %f62, 0f00000000;
|
|
and.pred %p3, %p81, %p67;
|
|
setp.eq.f32 %p83, %f62, 0f00000000;
|
|
@%p83 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f580, %f62, %f62;
|
|
selp.f32 %f1116, %f580, 0f00000000, %p67;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r252, %f1114;
|
|
xor.b32 %r253, %r252, -2147483648;
|
|
mov.b32 %f576, %r253;
|
|
selp.f32 %f1116, %f576, %f1114, %p3;
|
|
setp.geu.f32 %p84, %f62, 0f00000000;
|
|
@%p84 bra $L__BB0_70;
|
|
|
|
mov.f32 %f577, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f578, %f577;
|
|
setp.eq.f32 %p85, %f578, 0f3EE66666;
|
|
@%p85 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1116, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1071, %f62;
|
|
add.f32 %f581, %f1071, 0f3EE66666;
|
|
mov.b32 %r254, %f581;
|
|
setp.lt.s32 %p87, %r254, 2139095040;
|
|
@%p87 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1072, %f62;
|
|
setp.gtu.f32 %p88, %f1072, 0f7F800000;
|
|
@%p88 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1116, %f62, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1073, %f62;
|
|
setp.neu.f32 %p89, %f1073, 0f7F800000;
|
|
@%p89 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1116, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p90, %f62, 0f3F800000;
|
|
selp.f32 %f103, 0f3F800000, %f1116, %p90;
|
|
abs.f32 %f104, %f63;
|
|
setp.lt.f32 %p91, %f104, 0f00800000;
|
|
mul.f32 %f583, %f104, 0f4B800000;
|
|
selp.f32 %f584, %f583, %f104, %p91;
|
|
selp.f32 %f585, 0fC3170000, 0fC2FE0000, %p91;
|
|
mov.b32 %r255, %f584;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f586, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f587, %r258;
|
|
add.f32 %f588, %f585, %f587;
|
|
setp.gt.f32 %p92, %f586, 0f3FB504F3;
|
|
mul.f32 %f589, %f586, 0f3F000000;
|
|
add.f32 %f590, %f588, 0f3F800000;
|
|
selp.f32 %f591, %f590, %f588, %p92;
|
|
selp.f32 %f592, %f589, %f586, %p92;
|
|
add.f32 %f593, %f592, 0fBF800000;
|
|
add.f32 %f594, %f592, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f595, %f594;
|
|
add.f32 %f596, %f593, %f593;
|
|
mul.f32 %f597, %f596, %f595;
|
|
mul.f32 %f598, %f597, %f597;
|
|
mov.f32 %f599, 0f3C4CAF63;
|
|
mov.f32 %f600, 0f3B18F0FE;
|
|
fma.rn.f32 %f601, %f600, %f598, %f599;
|
|
mov.f32 %f602, 0f3DAAAABD;
|
|
fma.rn.f32 %f603, %f601, %f598, %f602;
|
|
mul.rn.f32 %f604, %f603, %f598;
|
|
mul.rn.f32 %f605, %f604, %f597;
|
|
sub.f32 %f606, %f593, %f597;
|
|
add.f32 %f607, %f606, %f606;
|
|
neg.f32 %f608, %f597;
|
|
fma.rn.f32 %f609, %f608, %f593, %f607;
|
|
mul.rn.f32 %f610, %f595, %f609;
|
|
add.f32 %f611, %f605, %f597;
|
|
sub.f32 %f612, %f597, %f611;
|
|
add.f32 %f613, %f605, %f612;
|
|
add.f32 %f614, %f610, %f613;
|
|
add.f32 %f615, %f611, %f614;
|
|
sub.f32 %f616, %f611, %f615;
|
|
add.f32 %f617, %f614, %f616;
|
|
mov.f32 %f618, 0f3F317200;
|
|
mul.rn.f32 %f619, %f591, %f618;
|
|
mov.f32 %f620, 0f35BFBE8E;
|
|
mul.rn.f32 %f621, %f591, %f620;
|
|
add.f32 %f622, %f619, %f615;
|
|
sub.f32 %f623, %f619, %f622;
|
|
add.f32 %f624, %f615, %f623;
|
|
add.f32 %f625, %f617, %f624;
|
|
add.f32 %f626, %f621, %f625;
|
|
add.f32 %f627, %f622, %f626;
|
|
sub.f32 %f628, %f622, %f627;
|
|
add.f32 %f629, %f626, %f628;
|
|
mov.f32 %f630, 0f3EE66666;
|
|
mul.rn.f32 %f631, %f630, %f627;
|
|
neg.f32 %f632, %f631;
|
|
fma.rn.f32 %f633, %f630, %f627, %f632;
|
|
fma.rn.f32 %f634, %f630, %f629, %f633;
|
|
mov.f32 %f635, 0f00000000;
|
|
fma.rn.f32 %f636, %f635, %f627, %f634;
|
|
add.rn.f32 %f637, %f631, %f636;
|
|
neg.f32 %f638, %f637;
|
|
add.rn.f32 %f639, %f631, %f638;
|
|
add.rn.f32 %f640, %f639, %f636;
|
|
mov.b32 %r259, %f637;
|
|
setp.eq.s32 %p93, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f641, %r260;
|
|
add.f32 %f642, %f640, 0f37000000;
|
|
selp.f32 %f105, %f642, %f640, %p93;
|
|
selp.f32 %f643, %f641, %f637, %p93;
|
|
mov.f32 %f644, 0f3FB8AA3B;
|
|
mul.rn.f32 %f645, %f643, %f644;
|
|
cvt.rzi.f32.f32 %f646, %f645;
|
|
abs.f32 %f647, %f646;
|
|
setp.gt.f32 %p94, %f647, 0f42FC0000;
|
|
mov.b32 %r261, %f646;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f648, %r263;
|
|
selp.f32 %f649, %f648, %f646, %p94;
|
|
mov.f32 %f650, 0fBF317218;
|
|
fma.rn.f32 %f651, %f649, %f650, %f643;
|
|
mov.f32 %f652, 0f3102E308;
|
|
fma.rn.f32 %f653, %f649, %f652, %f651;
|
|
mul.f32 %f654, %f653, 0f3FB8AA3B;
|
|
add.f32 %f655, %f649, 0f4B40007F;
|
|
mov.b32 %r264, %f655;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f656, %r265;
|
|
ex2.approx.ftz.f32 %f657, %f654;
|
|
mul.f32 %f106, %f657, %f656;
|
|
setp.eq.f32 %p95, %f106, 0f7F800000;
|
|
mov.f32 %f1117, 0f7F800000;
|
|
@%p95 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1117, %f106, %f105, %f106;
|
|
|
|
$L__BB0_77:
|
|
setp.lt.f32 %p96, %f63, 0f00000000;
|
|
and.pred %p4, %p96, %p67;
|
|
setp.eq.f32 %p98, %f63, 0f00000000;
|
|
@%p98 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f662, %f63, %f63;
|
|
selp.f32 %f1119, %f662, 0f00000000, %p67;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r266, %f1117;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f658, %r267;
|
|
selp.f32 %f1119, %f658, %f1117, %p4;
|
|
setp.geu.f32 %p99, %f63, 0f00000000;
|
|
@%p99 bra $L__BB0_82;
|
|
|
|
mov.f32 %f659, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f660, %f659;
|
|
setp.eq.f32 %p100, %f660, 0f3EE66666;
|
|
@%p100 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1119, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
abs.f32 %f1074, %f63;
|
|
add.f32 %f663, %f1074, 0f3EE66666;
|
|
mov.b32 %r268, %f663;
|
|
setp.lt.s32 %p102, %r268, 2139095040;
|
|
@%p102 bra $L__BB0_87;
|
|
|
|
abs.f32 %f1075, %f63;
|
|
setp.gtu.f32 %p103, %f1075, 0f7F800000;
|
|
@%p103 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1119, %f63, 0f3EE66666;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
abs.f32 %f1076, %f63;
|
|
setp.neu.f32 %p104, %f1076, 0f7F800000;
|
|
@%p104 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1119, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
setp.eq.f32 %p105, %f63, 0f3F800000;
|
|
mov.f32 %f665, 0f3F800000;
|
|
selp.f32 %f666, 0f3F800000, %f1119, %p105;
|
|
min.f32 %f667, %f91, %f665;
|
|
mov.f32 %f668, 0f00000000;
|
|
max.f32 %f115, %f668, %f667;
|
|
min.f32 %f669, %f103, %f665;
|
|
max.f32 %f116, %f668, %f669;
|
|
min.f32 %f670, %f666, %f665;
|
|
max.f32 %f117, %f668, %f670;
|
|
mov.f32 %f674, 0f3ED55555;
|
|
abs.f32 %f119, %f115;
|
|
setp.lt.f32 %p106, %f119, 0f00800000;
|
|
mul.f32 %f676, %f119, 0f4B800000;
|
|
selp.f32 %f677, %f676, %f119, %p106;
|
|
selp.f32 %f678, 0fC3170000, 0fC2FE0000, %p106;
|
|
mov.b32 %r271, %f677;
|
|
and.b32 %r272, %r271, 8388607;
|
|
or.b32 %r273, %r272, 1065353216;
|
|
mov.b32 %f679, %r273;
|
|
shr.u32 %r274, %r271, 23;
|
|
cvt.rn.f32.u32 %f680, %r274;
|
|
add.f32 %f681, %f678, %f680;
|
|
setp.gt.f32 %p107, %f679, 0f3FB504F3;
|
|
mul.f32 %f682, %f679, 0f3F000000;
|
|
add.f32 %f683, %f681, 0f3F800000;
|
|
selp.f32 %f684, %f683, %f681, %p107;
|
|
selp.f32 %f685, %f682, %f679, %p107;
|
|
add.f32 %f686, %f685, 0fBF800000;
|
|
add.f32 %f687, %f685, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f688, %f687;
|
|
add.f32 %f689, %f686, %f686;
|
|
mul.f32 %f690, %f689, %f688;
|
|
mul.f32 %f691, %f690, %f690;
|
|
mov.f32 %f692, 0f3C4CAF63;
|
|
mov.f32 %f693, 0f3B18F0FE;
|
|
fma.rn.f32 %f694, %f693, %f691, %f692;
|
|
mov.f32 %f695, 0f3DAAAABD;
|
|
fma.rn.f32 %f696, %f694, %f691, %f695;
|
|
mul.rn.f32 %f697, %f696, %f691;
|
|
mul.rn.f32 %f698, %f697, %f690;
|
|
sub.f32 %f699, %f686, %f690;
|
|
add.f32 %f700, %f699, %f699;
|
|
neg.f32 %f701, %f690;
|
|
fma.rn.f32 %f702, %f701, %f686, %f700;
|
|
mul.rn.f32 %f703, %f688, %f702;
|
|
add.f32 %f704, %f698, %f690;
|
|
sub.f32 %f705, %f690, %f704;
|
|
add.f32 %f706, %f698, %f705;
|
|
add.f32 %f707, %f703, %f706;
|
|
add.f32 %f708, %f704, %f707;
|
|
sub.f32 %f709, %f704, %f708;
|
|
add.f32 %f710, %f707, %f709;
|
|
mov.f32 %f711, 0f3F317200;
|
|
mul.rn.f32 %f712, %f684, %f711;
|
|
mov.f32 %f713, 0f35BFBE8E;
|
|
mul.rn.f32 %f714, %f684, %f713;
|
|
add.f32 %f715, %f712, %f708;
|
|
sub.f32 %f716, %f712, %f715;
|
|
add.f32 %f717, %f708, %f716;
|
|
add.f32 %f718, %f710, %f717;
|
|
add.f32 %f719, %f714, %f718;
|
|
add.f32 %f720, %f715, %f719;
|
|
sub.f32 %f721, %f715, %f720;
|
|
add.f32 %f722, %f719, %f721;
|
|
mul.rn.f32 %f723, %f674, %f720;
|
|
neg.f32 %f724, %f723;
|
|
fma.rn.f32 %f725, %f674, %f720, %f724;
|
|
fma.rn.f32 %f726, %f674, %f722, %f725;
|
|
fma.rn.f32 %f727, %f668, %f720, %f726;
|
|
add.rn.f32 %f728, %f723, %f727;
|
|
neg.f32 %f729, %f728;
|
|
add.rn.f32 %f730, %f723, %f729;
|
|
add.rn.f32 %f731, %f730, %f727;
|
|
mov.b32 %r275, %f728;
|
|
setp.eq.s32 %p108, %r275, 1118925336;
|
|
add.s32 %r276, %r275, -1;
|
|
mov.b32 %f732, %r276;
|
|
add.f32 %f733, %f731, 0f37000000;
|
|
selp.f32 %f120, %f733, %f731, %p108;
|
|
selp.f32 %f734, %f732, %f728, %p108;
|
|
mov.f32 %f735, 0f3FB8AA3B;
|
|
mul.rn.f32 %f736, %f734, %f735;
|
|
cvt.rzi.f32.f32 %f737, %f736;
|
|
abs.f32 %f738, %f737;
|
|
setp.gt.f32 %p109, %f738, 0f42FC0000;
|
|
mov.b32 %r277, %f737;
|
|
and.b32 %r278, %r277, -2147483648;
|
|
or.b32 %r279, %r278, 1123811328;
|
|
mov.b32 %f739, %r279;
|
|
selp.f32 %f740, %f739, %f737, %p109;
|
|
mov.f32 %f741, 0fBF317218;
|
|
fma.rn.f32 %f742, %f740, %f741, %f734;
|
|
mov.f32 %f743, 0f3102E308;
|
|
fma.rn.f32 %f744, %f740, %f743, %f742;
|
|
mul.f32 %f745, %f744, 0f3FB8AA3B;
|
|
add.f32 %f746, %f740, 0f4B40007F;
|
|
mov.b32 %r280, %f746;
|
|
shl.b32 %r281, %r280, 23;
|
|
mov.b32 %f747, %r281;
|
|
ex2.approx.ftz.f32 %f748, %f745;
|
|
mul.f32 %f121, %f748, %f747;
|
|
setp.eq.f32 %p110, %f121, 0f7F800000;
|
|
mov.f32 %f1120, 0f7F800000;
|
|
@%p110 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1120, %f121, %f120, %f121;
|
|
|
|
$L__BB0_89:
|
|
mov.f32 %f1052, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1051, %f1052;
|
|
add.f32 %f1050, %f1051, %f1051;
|
|
mov.f32 %f1049, 0f3ED55555;
|
|
sub.f32 %f1048, %f1049, %f1050;
|
|
abs.f32 %f1047, %f1048;
|
|
setp.lt.f32 %p111, %f115, 0f00000000;
|
|
setp.eq.f32 %p112, %f1047, 0f3F800000;
|
|
and.pred %p5, %p111, %p112;
|
|
setp.eq.f32 %p113, %f115, 0f00000000;
|
|
@%p113 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f753, %f115, %f115;
|
|
selp.f32 %f1122, %f753, 0f00000000, %p112;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.b32 %r282, %f1120;
|
|
xor.b32 %r283, %r282, -2147483648;
|
|
mov.b32 %f749, %r283;
|
|
selp.f32 %f1122, %f749, %f1120, %p5;
|
|
setp.geu.f32 %p114, %f115, 0f00000000;
|
|
@%p114 bra $L__BB0_94;
|
|
|
|
mov.f32 %f750, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f751, %f750;
|
|
setp.eq.f32 %p115, %f751, 0f3ED55555;
|
|
@%p115 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1122, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f754, %f119, 0f3ED55555;
|
|
mov.b32 %r284, %f754;
|
|
setp.lt.s32 %p117, %r284, 2139095040;
|
|
@%p117 bra $L__BB0_99;
|
|
|
|
setp.gtu.f32 %p118, %f119, 0f7F800000;
|
|
@%p118 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f1122, %f115, 0f3ED55555;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
setp.neu.f32 %p119, %f119, 0f7F800000;
|
|
@%p119 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1122, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
abs.f32 %f130, %f116;
|
|
setp.lt.f32 %p120, %f130, 0f00800000;
|
|
mul.f32 %f756, %f130, 0f4B800000;
|
|
selp.f32 %f757, %f756, %f130, %p120;
|
|
selp.f32 %f758, 0fC3170000, 0fC2FE0000, %p120;
|
|
mov.b32 %r285, %f757;
|
|
and.b32 %r286, %r285, 8388607;
|
|
or.b32 %r287, %r286, 1065353216;
|
|
mov.b32 %f759, %r287;
|
|
shr.u32 %r288, %r285, 23;
|
|
cvt.rn.f32.u32 %f760, %r288;
|
|
add.f32 %f761, %f758, %f760;
|
|
setp.gt.f32 %p121, %f759, 0f3FB504F3;
|
|
mul.f32 %f762, %f759, 0f3F000000;
|
|
add.f32 %f763, %f761, 0f3F800000;
|
|
selp.f32 %f764, %f763, %f761, %p121;
|
|
selp.f32 %f765, %f762, %f759, %p121;
|
|
add.f32 %f766, %f765, 0fBF800000;
|
|
add.f32 %f767, %f765, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f768, %f767;
|
|
add.f32 %f769, %f766, %f766;
|
|
mul.f32 %f770, %f769, %f768;
|
|
mul.f32 %f771, %f770, %f770;
|
|
mov.f32 %f772, 0f3C4CAF63;
|
|
mov.f32 %f773, 0f3B18F0FE;
|
|
fma.rn.f32 %f774, %f773, %f771, %f772;
|
|
mov.f32 %f775, 0f3DAAAABD;
|
|
fma.rn.f32 %f776, %f774, %f771, %f775;
|
|
mul.rn.f32 %f777, %f776, %f771;
|
|
mul.rn.f32 %f778, %f777, %f770;
|
|
sub.f32 %f779, %f766, %f770;
|
|
add.f32 %f780, %f779, %f779;
|
|
neg.f32 %f781, %f770;
|
|
fma.rn.f32 %f782, %f781, %f766, %f780;
|
|
mul.rn.f32 %f783, %f768, %f782;
|
|
add.f32 %f784, %f778, %f770;
|
|
sub.f32 %f785, %f770, %f784;
|
|
add.f32 %f786, %f778, %f785;
|
|
add.f32 %f787, %f783, %f786;
|
|
add.f32 %f788, %f784, %f787;
|
|
sub.f32 %f789, %f784, %f788;
|
|
add.f32 %f790, %f787, %f789;
|
|
mov.f32 %f791, 0f3F317200;
|
|
mul.rn.f32 %f792, %f764, %f791;
|
|
mov.f32 %f793, 0f35BFBE8E;
|
|
mul.rn.f32 %f794, %f764, %f793;
|
|
add.f32 %f795, %f792, %f788;
|
|
sub.f32 %f796, %f792, %f795;
|
|
add.f32 %f797, %f788, %f796;
|
|
add.f32 %f798, %f790, %f797;
|
|
add.f32 %f799, %f794, %f798;
|
|
add.f32 %f800, %f795, %f799;
|
|
sub.f32 %f801, %f795, %f800;
|
|
add.f32 %f802, %f799, %f801;
|
|
mov.f32 %f803, 0f3ED55555;
|
|
mul.rn.f32 %f804, %f803, %f800;
|
|
neg.f32 %f805, %f804;
|
|
fma.rn.f32 %f806, %f803, %f800, %f805;
|
|
fma.rn.f32 %f807, %f803, %f802, %f806;
|
|
mov.f32 %f808, 0f00000000;
|
|
fma.rn.f32 %f809, %f808, %f800, %f807;
|
|
add.rn.f32 %f810, %f804, %f809;
|
|
neg.f32 %f811, %f810;
|
|
add.rn.f32 %f812, %f804, %f811;
|
|
add.rn.f32 %f813, %f812, %f809;
|
|
mov.b32 %r289, %f810;
|
|
setp.eq.s32 %p122, %r289, 1118925336;
|
|
add.s32 %r290, %r289, -1;
|
|
mov.b32 %f814, %r290;
|
|
add.f32 %f815, %f813, 0f37000000;
|
|
selp.f32 %f131, %f815, %f813, %p122;
|
|
selp.f32 %f816, %f814, %f810, %p122;
|
|
mov.f32 %f817, 0f3FB8AA3B;
|
|
mul.rn.f32 %f818, %f816, %f817;
|
|
cvt.rzi.f32.f32 %f819, %f818;
|
|
abs.f32 %f820, %f819;
|
|
setp.gt.f32 %p123, %f820, 0f42FC0000;
|
|
mov.b32 %r291, %f819;
|
|
and.b32 %r292, %r291, -2147483648;
|
|
or.b32 %r293, %r292, 1123811328;
|
|
mov.b32 %f821, %r293;
|
|
selp.f32 %f822, %f821, %f819, %p123;
|
|
mov.f32 %f823, 0fBF317218;
|
|
fma.rn.f32 %f824, %f822, %f823, %f816;
|
|
mov.f32 %f825, 0f3102E308;
|
|
fma.rn.f32 %f826, %f822, %f825, %f824;
|
|
mul.f32 %f827, %f826, 0f3FB8AA3B;
|
|
add.f32 %f828, %f822, 0f4B40007F;
|
|
mov.b32 %r294, %f828;
|
|
shl.b32 %r295, %r294, 23;
|
|
mov.b32 %f829, %r295;
|
|
ex2.approx.ftz.f32 %f830, %f827;
|
|
mul.f32 %f132, %f830, %f829;
|
|
setp.eq.f32 %p124, %f132, 0f7F800000;
|
|
mov.f32 %f1123, 0f7F800000;
|
|
@%p124 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1123, %f132, %f131, %f132;
|
|
|
|
$L__BB0_101:
|
|
setp.lt.f32 %p125, %f116, 0f00000000;
|
|
and.pred %p6, %p125, %p112;
|
|
setp.eq.f32 %p127, %f116, 0f00000000;
|
|
@%p127 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f835, %f116, %f116;
|
|
selp.f32 %f1125, %f835, 0f00000000, %p112;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r296, %f1123;
|
|
xor.b32 %r297, %r296, -2147483648;
|
|
mov.b32 %f831, %r297;
|
|
selp.f32 %f1125, %f831, %f1123, %p6;
|
|
setp.geu.f32 %p128, %f116, 0f00000000;
|
|
@%p128 bra $L__BB0_106;
|
|
|
|
mov.f32 %f832, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f833, %f832;
|
|
setp.eq.f32 %p129, %f833, 0f3ED55555;
|
|
@%p129 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1125, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1079, 0f00000000;
|
|
max.f32 %f1078, %f1079, %f669;
|
|
abs.f32 %f1077, %f1078;
|
|
add.f32 %f836, %f1077, 0f3ED55555;
|
|
mov.b32 %r298, %f836;
|
|
setp.lt.s32 %p131, %r298, 2139095040;
|
|
@%p131 bra $L__BB0_111;
|
|
|
|
mov.f32 %f1082, 0f00000000;
|
|
max.f32 %f1081, %f1082, %f669;
|
|
abs.f32 %f1080, %f1081;
|
|
setp.gtu.f32 %p132, %f1080, 0f7F800000;
|
|
@%p132 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1125, %f116, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
mov.f32 %f1085, 0f00000000;
|
|
max.f32 %f1084, %f1085, %f669;
|
|
abs.f32 %f1083, %f1084;
|
|
setp.neu.f32 %p133, %f1083, 0f7F800000;
|
|
@%p133 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1125, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
abs.f32 %f141, %f117;
|
|
setp.lt.f32 %p134, %f141, 0f00800000;
|
|
mul.f32 %f838, %f141, 0f4B800000;
|
|
selp.f32 %f839, %f838, %f141, %p134;
|
|
selp.f32 %f840, 0fC3170000, 0fC2FE0000, %p134;
|
|
mov.b32 %r299, %f839;
|
|
and.b32 %r300, %r299, 8388607;
|
|
or.b32 %r301, %r300, 1065353216;
|
|
mov.b32 %f841, %r301;
|
|
shr.u32 %r302, %r299, 23;
|
|
cvt.rn.f32.u32 %f842, %r302;
|
|
add.f32 %f843, %f840, %f842;
|
|
setp.gt.f32 %p135, %f841, 0f3FB504F3;
|
|
mul.f32 %f844, %f841, 0f3F000000;
|
|
add.f32 %f845, %f843, 0f3F800000;
|
|
selp.f32 %f846, %f845, %f843, %p135;
|
|
selp.f32 %f847, %f844, %f841, %p135;
|
|
add.f32 %f848, %f847, 0fBF800000;
|
|
add.f32 %f849, %f847, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f850, %f849;
|
|
add.f32 %f851, %f848, %f848;
|
|
mul.f32 %f852, %f851, %f850;
|
|
mul.f32 %f853, %f852, %f852;
|
|
mov.f32 %f854, 0f3C4CAF63;
|
|
mov.f32 %f855, 0f3B18F0FE;
|
|
fma.rn.f32 %f856, %f855, %f853, %f854;
|
|
mov.f32 %f857, 0f3DAAAABD;
|
|
fma.rn.f32 %f858, %f856, %f853, %f857;
|
|
mul.rn.f32 %f859, %f858, %f853;
|
|
mul.rn.f32 %f860, %f859, %f852;
|
|
sub.f32 %f861, %f848, %f852;
|
|
add.f32 %f862, %f861, %f861;
|
|
neg.f32 %f863, %f852;
|
|
fma.rn.f32 %f864, %f863, %f848, %f862;
|
|
mul.rn.f32 %f865, %f850, %f864;
|
|
add.f32 %f866, %f860, %f852;
|
|
sub.f32 %f867, %f852, %f866;
|
|
add.f32 %f868, %f860, %f867;
|
|
add.f32 %f869, %f865, %f868;
|
|
add.f32 %f870, %f866, %f869;
|
|
sub.f32 %f871, %f866, %f870;
|
|
add.f32 %f872, %f869, %f871;
|
|
mov.f32 %f873, 0f3F317200;
|
|
mul.rn.f32 %f874, %f846, %f873;
|
|
mov.f32 %f875, 0f35BFBE8E;
|
|
mul.rn.f32 %f876, %f846, %f875;
|
|
add.f32 %f877, %f874, %f870;
|
|
sub.f32 %f878, %f874, %f877;
|
|
add.f32 %f879, %f870, %f878;
|
|
add.f32 %f880, %f872, %f879;
|
|
add.f32 %f881, %f876, %f880;
|
|
add.f32 %f882, %f877, %f881;
|
|
sub.f32 %f883, %f877, %f882;
|
|
add.f32 %f884, %f881, %f883;
|
|
mov.f32 %f885, 0f3ED55555;
|
|
mul.rn.f32 %f886, %f885, %f882;
|
|
neg.f32 %f887, %f886;
|
|
fma.rn.f32 %f888, %f885, %f882, %f887;
|
|
fma.rn.f32 %f889, %f885, %f884, %f888;
|
|
mov.f32 %f890, 0f00000000;
|
|
fma.rn.f32 %f891, %f890, %f882, %f889;
|
|
add.rn.f32 %f892, %f886, %f891;
|
|
neg.f32 %f893, %f892;
|
|
add.rn.f32 %f894, %f886, %f893;
|
|
add.rn.f32 %f895, %f894, %f891;
|
|
mov.b32 %r303, %f892;
|
|
setp.eq.s32 %p136, %r303, 1118925336;
|
|
add.s32 %r304, %r303, -1;
|
|
mov.b32 %f896, %r304;
|
|
add.f32 %f897, %f895, 0f37000000;
|
|
selp.f32 %f142, %f897, %f895, %p136;
|
|
selp.f32 %f898, %f896, %f892, %p136;
|
|
mov.f32 %f899, 0f3FB8AA3B;
|
|
mul.rn.f32 %f900, %f898, %f899;
|
|
cvt.rzi.f32.f32 %f901, %f900;
|
|
abs.f32 %f902, %f901;
|
|
setp.gt.f32 %p137, %f902, 0f42FC0000;
|
|
mov.b32 %r305, %f901;
|
|
and.b32 %r306, %r305, -2147483648;
|
|
or.b32 %r307, %r306, 1123811328;
|
|
mov.b32 %f903, %r307;
|
|
selp.f32 %f904, %f903, %f901, %p137;
|
|
mov.f32 %f905, 0fBF317218;
|
|
fma.rn.f32 %f906, %f904, %f905, %f898;
|
|
mov.f32 %f907, 0f3102E308;
|
|
fma.rn.f32 %f908, %f904, %f907, %f906;
|
|
mul.f32 %f909, %f908, 0f3FB8AA3B;
|
|
add.f32 %f910, %f904, 0f4B40007F;
|
|
mov.b32 %r308, %f910;
|
|
shl.b32 %r309, %r308, 23;
|
|
mov.b32 %f911, %r309;
|
|
ex2.approx.ftz.f32 %f912, %f909;
|
|
mul.f32 %f143, %f912, %f911;
|
|
setp.eq.f32 %p138, %f143, 0f7F800000;
|
|
mov.f32 %f1126, 0f7F800000;
|
|
@%p138 bra $L__BB0_113;
|
|
|
|
fma.rn.f32 %f1126, %f143, %f142, %f143;
|
|
|
|
$L__BB0_113:
|
|
setp.lt.f32 %p139, %f117, 0f00000000;
|
|
and.pred %p7, %p139, %p112;
|
|
setp.eq.f32 %p141, %f117, 0f00000000;
|
|
@%p141 bra $L__BB0_117;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f917, %f117, %f117;
|
|
selp.f32 %f1128, %f917, 0f00000000, %p112;
|
|
bra.uni $L__BB0_118;
|
|
|
|
$L__BB0_114:
|
|
mov.b32 %r310, %f1126;
|
|
xor.b32 %r311, %r310, -2147483648;
|
|
mov.b32 %f913, %r311;
|
|
selp.f32 %f1128, %f913, %f1126, %p7;
|
|
setp.geu.f32 %p142, %f117, 0f00000000;
|
|
@%p142 bra $L__BB0_118;
|
|
|
|
mov.f32 %f914, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f915, %f914;
|
|
setp.eq.f32 %p143, %f915, 0f3ED55555;
|
|
@%p143 bra $L__BB0_118;
|
|
|
|
mov.f32 %f1128, 0f7FFFFFFF;
|
|
|
|
$L__BB0_118:
|
|
mov.f32 %f1088, 0f00000000;
|
|
max.f32 %f1087, %f1088, %f670;
|
|
abs.f32 %f1086, %f1087;
|
|
add.f32 %f918, %f1086, 0f3ED55555;
|
|
mov.b32 %r312, %f918;
|
|
setp.lt.s32 %p145, %r312, 2139095040;
|
|
@%p145 bra $L__BB0_123;
|
|
|
|
mov.f32 %f1091, 0f00000000;
|
|
max.f32 %f1090, %f1091, %f670;
|
|
abs.f32 %f1089, %f1090;
|
|
setp.gtu.f32 %p146, %f1089, 0f7F800000;
|
|
@%p146 bra $L__BB0_122;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1128, %f117, 0f3ED55555;
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_120:
|
|
mov.f32 %f1094, 0f00000000;
|
|
max.f32 %f1093, %f1094, %f670;
|
|
abs.f32 %f1092, %f1093;
|
|
setp.neu.f32 %p147, %f1092, 0f7F800000;
|
|
@%p147 bra $L__BB0_123;
|
|
|
|
selp.f32 %f1128, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd112, [params+144];
|
|
cvta.to.global.u64 %rd111, %rd112;
|
|
ld.const.u32 %r351, [params+136];
|
|
mad.lo.s32 %r350, %r351, %r4, %r3;
|
|
cvt.u64.u32 %rd110, %r350;
|
|
fma.rn.f32 %f919, %f1122, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p148, %f115, 0f3F800000;
|
|
mov.f32 %f920, 0f3F800000;
|
|
selp.f32 %f921, 0f3F7FFFFF, %f919, %p148;
|
|
mul.f32 %f922, %f115, 0f414EB852;
|
|
setp.lt.f32 %p149, %f115, 0f3B4D2E1C;
|
|
selp.f32 %f923, %f922, %f921, %p149;
|
|
fma.rn.f32 %f924, %f1125, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p150, %f116, 0f3F800000;
|
|
selp.f32 %f925, 0f3F7FFFFF, %f924, %p150;
|
|
mul.f32 %f926, %f116, 0f414EB852;
|
|
setp.lt.f32 %p151, %f116, 0f3B4D2E1C;
|
|
selp.f32 %f927, %f926, %f925, %p151;
|
|
fma.rn.f32 %f928, %f1128, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p152, %f117, 0f3F800000;
|
|
selp.f32 %f929, 0f3F7FFFFF, %f928, %p152;
|
|
mul.f32 %f930, %f117, 0f414EB852;
|
|
setp.lt.f32 %p153, %f117, 0f3B4D2E1C;
|
|
selp.f32 %f931, %f930, %f929, %p153;
|
|
min.f32 %f932, %f923, %f920;
|
|
mov.f32 %f933, 0f00000000;
|
|
max.f32 %f934, %f933, %f932;
|
|
mul.f32 %f935, %f934, 0f43800000;
|
|
cvt.rzi.u32.f32 %r313, %f935;
|
|
min.u32 %r314, %r313, 255;
|
|
min.f32 %f936, %f927, %f920;
|
|
max.f32 %f937, %f933, %f936;
|
|
mul.f32 %f938, %f937, 0f43800000;
|
|
cvt.rzi.u32.f32 %r315, %f938;
|
|
min.u32 %r316, %r315, 255;
|
|
min.f32 %f939, %f931, %f920;
|
|
max.f32 %f940, %f933, %f939;
|
|
mul.f32 %f941, %f940, 0f43800000;
|
|
cvt.rzi.u32.f32 %r317, %f941;
|
|
min.u32 %r318, %r317, 255;
|
|
shl.b64 %rd70, %rd110, 2;
|
|
add.s64 %rd71, %rd111, %rd70;
|
|
cvt.u16.u32 %rs19, %r318;
|
|
cvt.u16.u32 %rs20, %r316;
|
|
cvt.u16.u32 %rs21, %r314;
|
|
mov.u16 %rs22, 255;
|
|
st.global.v4.u8 [%rd71], {%rs21, %rs20, %rs19, %rs22};
|
|
|
|
$L__BB0_124:
|
|
ld.const.u32 %r352, [params+104];
|
|
and.b32 %r319, %r352, 4;
|
|
setp.eq.s32 %p154, %r319, 0;
|
|
ld.const.u32 %r367, [params+108];
|
|
@%p154 bra $L__BB0_128;
|
|
|
|
setp.eq.s32 %p155, %r367, 0;
|
|
ld.const.u64 %rd72, [params+224];
|
|
cvta.to.global.u64 %rd73, %rd72;
|
|
ld.const.u32 %r320, [params+216];
|
|
mad.lo.s32 %r321, %r320, %r4, %r3;
|
|
mul.wide.u32 %rd74, %r321, 8;
|
|
add.s64 %rd20, %rd73, %rd74;
|
|
@%p155 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs30, %rs31, %rs32, %rs33}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f942, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f943, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f944, %rs32;}
|
|
|
|
// end inline asm
|
|
add.f32 %f945, %f61, %f942;
|
|
add.f32 %f946, %f62, %f943;
|
|
add.f32 %f947, %f63, %f944;
|
|
mov.f32 %f948, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f947;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f946;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f945;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f948;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs26, %rs27, %rs28, %rs29};
|
|
bra.uni $L__BB0_128;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f952, 0f3F800000;
|
|
mov.u32 %r367, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f952;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f63;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f62;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f61;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs34, %rs35, %rs36, %rs37};
|
|
|
|
$L__BB0_128:
|
|
ld.const.u64 %rd75, [params+256];
|
|
cvta.to.global.u64 %rd76, %rd75;
|
|
ld.const.u32 %r323, [params+248];
|
|
mad.lo.s32 %r324, %r323, %r4, %r3;
|
|
mul.wide.u32 %rd77, %r324, 8;
|
|
add.s64 %rd21, %rd76, %rd77;
|
|
setp.eq.s32 %p156, %r367, 0;
|
|
@%p156 bra $L__BB0_130;
|
|
|
|
ld.global.v4.u16 {%rs45, %rs46, %rs47, %rs48}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f953, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f954, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f955, %rs47;}
|
|
|
|
// end inline asm
|
|
add.f32 %f956, %f64, %f953;
|
|
add.f32 %f957, %f65, %f954;
|
|
add.f32 %f958, %f66, %f955;
|
|
mov.f32 %f959, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f958;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f957;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f956;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f959;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs41, %rs42, %rs43, %rs44};
|
|
bra.uni $L__BB0_131;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f963, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f963;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f66;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f65;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f64;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs49, %rs50, %rs51, %rs52};
|
|
|
|
$L__BB0_131:
|
|
mul.f32 %f964, %f173, 0f3F000000;
|
|
mov.f32 %f965, 0f3F000000;
|
|
sub.f32 %f152, %f965, %f964;
|
|
mul.f32 %f966, %f174, 0f3F000000;
|
|
sub.f32 %f153, %f965, %f966;
|
|
mul.f32 %f967, %f175, 0f3F000000;
|
|
sub.f32 %f154, %f965, %f967;
|
|
ld.const.u64 %rd78, [params+272];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r325, [params+264];
|
|
mad.lo.s32 %r326, %r325, %r4, %r3;
|
|
mul.wide.u32 %rd80, %r326, 8;
|
|
add.s64 %rd22, %rd79, %rd80;
|
|
@%p156 bra $L__BB0_133;
|
|
|
|
ld.global.v4.u16 {%rs60, %rs61, %rs62, %rs63}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f968, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f969, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f970, %rs62;}
|
|
|
|
// end inline asm
|
|
add.f32 %f971, %f152, %f968;
|
|
add.f32 %f972, %f152, %f969;
|
|
add.f32 %f973, %f152, %f970;
|
|
mov.f32 %f974, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f973;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f972;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f971;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f974;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs56, %rs57, %rs58, %rs59};
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_133:
|
|
mov.f32 %f978, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f978;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f152;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs64, %rs65, %rs66, %rs67};
|
|
|
|
$L__BB0_134:
|
|
ld.const.u64 %rd81, [params+288];
|
|
cvta.to.global.u64 %rd82, %rd81;
|
|
ld.const.u32 %r327, [params+280];
|
|
mad.lo.s32 %r328, %r327, %r4, %r3;
|
|
mul.wide.u32 %rd83, %r328, 8;
|
|
add.s64 %rd23, %rd82, %rd83;
|
|
@%p156 bra $L__BB0_136;
|
|
|
|
ld.global.v4.u16 {%rs75, %rs76, %rs77, %rs78}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f979, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f980, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f981, %rs77;}
|
|
|
|
// end inline asm
|
|
add.f32 %f982, %f153, %f979;
|
|
add.f32 %f983, %f153, %f980;
|
|
add.f32 %f984, %f153, %f981;
|
|
mov.f32 %f985, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f984;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f983;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f982;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f985;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs71, %rs72, %rs73, %rs74};
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f989, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f989;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f153;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs79, %rs80, %rs81, %rs82};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd84, [params+304];
|
|
cvta.to.global.u64 %rd85, %rd84;
|
|
ld.const.u32 %r329, [params+296];
|
|
mad.lo.s32 %r330, %r329, %r4, %r3;
|
|
mul.wide.u32 %rd86, %r330, 8;
|
|
add.s64 %rd24, %rd85, %rd86;
|
|
@%p156 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs90, %rs91, %rs92, %rs93}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f990, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f991, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f992, %rs92;}
|
|
|
|
// end inline asm
|
|
add.f32 %f993, %f154, %f990;
|
|
add.f32 %f994, %f154, %f991;
|
|
add.f32 %f995, %f154, %f992;
|
|
mov.f32 %f996, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f995;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f994;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f993;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f996;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs86, %rs87, %rs88, %rs89};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1000, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1000;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f154;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs94, %rs95, %rs96, %rs97};
|
|
|
|
$L__BB0_160:
|
|
ret;
|
|
|
|
}
|
|
|