2157 lines
58 KiB
Plaintext
2157 lines
58 KiB
Plaintext
//
|
|
// Generated by NVIDIA NVVM Compiler
|
|
//
|
|
// Compiler Build ID: CL-31968024
|
|
// Cuda compilation tools, release 12.0, V12.0.76
|
|
// Based on NVVM 7.0.1
|
|
//
|
|
|
|
.version 8.0
|
|
.target sm_52
|
|
.address_size 64
|
|
|
|
// .globl __raygen__oxMain
|
|
.const .align 16 .b8 params[1184];
|
|
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
|
|
|
|
.visible .entry __raygen__oxMain()
|
|
{
|
|
.local .align 4 .b8 __local_depot0[28];
|
|
.reg .b64 %SP;
|
|
.reg .b64 %SPL;
|
|
.reg .pred %p<152>;
|
|
.reg .b16 %rs<157>;
|
|
.reg .f32 %f<1072>;
|
|
.reg .b32 %r<442>;
|
|
.reg .f64 %fd<5>;
|
|
.reg .b64 %rd<113>;
|
|
|
|
|
|
mov.u64 %SPL, __local_depot0;
|
|
add.u64 %rd1, %SPL, 0;
|
|
// begin inline asm
|
|
call (%r84), _optix_get_launch_index_x, ();
|
|
// end inline asm
|
|
// begin inline asm
|
|
call (%r85), _optix_get_launch_index_y, ();
|
|
// end inline asm
|
|
ld.const.u64 %rd26, [params+400];
|
|
cvta.to.global.u64 %rd27, %rd26;
|
|
ld.const.u32 %r90, [params+392];
|
|
mad.lo.s32 %r91, %r90, %r85, %r84;
|
|
mul.wide.u32 %rd28, %r91, 4;
|
|
add.s64 %rd2, %rd27, %rd28;
|
|
ld.global.v2.u8 {%rs7, %rs156}, [%rd2];
|
|
or.b16 %rs9, %rs7, %rs156;
|
|
and.b16 %rs10, %rs9, 255;
|
|
setp.eq.s16 %p7, %rs10, 0;
|
|
@%p7 bra $L__BB0_2;
|
|
|
|
ld.global.u8 %rs155, [%rd2+2];
|
|
bra.uni $L__BB0_3;
|
|
|
|
$L__BB0_2:
|
|
ld.global.u8 %rs155, [%rd2+2];
|
|
setp.eq.s16 %p8, %rs155, 0;
|
|
mov.f32 %f1013, 0f00000000;
|
|
mov.u16 %rs156, 0;
|
|
mov.f32 %f1014, %f1013;
|
|
mov.f32 %f1015, %f1013;
|
|
@%p8 bra $L__BB0_4;
|
|
|
|
$L__BB0_3:
|
|
cvt.rn.f32.u16 %f195, %rs7;
|
|
div.rn.f32 %f196, %f195, 0f437F0000;
|
|
fma.rn.f32 %f197, %f196, 0f40000000, 0fBF800000;
|
|
and.b16 %rs13, %rs156, 255;
|
|
cvt.rn.f32.u16 %f198, %rs13;
|
|
div.rn.f32 %f199, %f198, 0f437F0000;
|
|
fma.rn.f32 %f200, %f199, 0f40000000, 0fBF800000;
|
|
cvt.rn.f32.u16 %f201, %rs155;
|
|
div.rn.f32 %f202, %f201, 0f437F0000;
|
|
fma.rn.f32 %f203, %f202, 0f40000000, 0fBF800000;
|
|
mul.f32 %f204, %f200, %f200;
|
|
fma.rn.f32 %f205, %f197, %f197, %f204;
|
|
fma.rn.f32 %f206, %f203, %f203, %f205;
|
|
sqrt.rn.f32 %f207, %f206;
|
|
rcp.rn.f32 %f208, %f207;
|
|
mul.f32 %f1015, %f208, %f203;
|
|
mul.f32 %f1014, %f208, %f200;
|
|
mul.f32 %f1013, %f197, %f208;
|
|
|
|
$L__BB0_4:
|
|
ld.const.v2.u32 {%r92, %r93}, [params];
|
|
add.s32 %r3, %r92, %r84;
|
|
add.s32 %r4, %r93, %r85;
|
|
setp.eq.f32 %p9, %f1013, 0f00000000;
|
|
setp.eq.f32 %p10, %f1014, 0f00000000;
|
|
and.pred %p11, %p9, %p10;
|
|
setp.eq.f32 %p12, %f1015, 0f00000000;
|
|
and.pred %p13, %p12, %p11;
|
|
@%p13 bra $L__BB0_129;
|
|
bra.uni $L__BB0_5;
|
|
|
|
$L__BB0_129:
|
|
ld.const.u32 %r82, [params+104];
|
|
and.b32 %r416, %r82, 1;
|
|
setp.eq.b32 %p143, %r416, 1;
|
|
mov.pred %p144, 0;
|
|
xor.pred %p145, %p143, %p144;
|
|
not.pred %p146, %p145;
|
|
@%p146 bra $L__BB0_131;
|
|
|
|
ld.const.u64 %rd86, [params+144];
|
|
cvta.to.global.u64 %rd87, %rd86;
|
|
ld.const.u32 %r417, [params+136];
|
|
mad.lo.s32 %r418, %r417, %r4, %r3;
|
|
mul.wide.u32 %rd88, %r418, 4;
|
|
add.s64 %rd89, %rd87, %rd88;
|
|
mov.u16 %rs90, 0;
|
|
st.global.v4.u8 [%rd89], {%rs90, %rs90, %rs90, %rs90};
|
|
|
|
$L__BB0_131:
|
|
and.b32 %r419, %r82, 4;
|
|
setp.eq.s32 %p147, %r419, 0;
|
|
@%p147 bra $L__BB0_133;
|
|
|
|
ld.const.u64 %rd90, [params+224];
|
|
cvta.to.global.u64 %rd91, %rd90;
|
|
ld.const.u32 %r420, [params+216];
|
|
mad.lo.s32 %r421, %r420, %r4, %r3;
|
|
mov.f32 %f954, 0f00000000;
|
|
mul.wide.u32 %rd92, %r421, 8;
|
|
add.s64 %rd93, %rd91, %rd92;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f954;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f954;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f954;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs94, 0;
|
|
st.global.v4.u16 [%rd93], {%rs91, %rs92, %rs93, %rs94};
|
|
|
|
$L__BB0_133:
|
|
ld.const.u32 %r83, [params+108];
|
|
setp.eq.s32 %p148, %r83, 0;
|
|
ld.const.u64 %rd94, [params+256];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r422, [params+248];
|
|
mad.lo.s32 %r423, %r422, %r4, %r3;
|
|
mul.wide.u32 %rd96, %r423, 8;
|
|
add.s64 %rd21, %rd95, %rd96;
|
|
@%p148 bra $L__BB0_135;
|
|
|
|
ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f955, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f956, %rs102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f957, %rs103;}
|
|
|
|
// end inline asm
|
|
add.f32 %f958, %f955, 0f00000000;
|
|
add.f32 %f959, %f956, 0f00000000;
|
|
add.f32 %f960, %f957, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f960;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f959;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f958;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs105, 0;
|
|
st.global.v4.u16 [%rd21], {%rs98, %rs99, %rs100, %rs105};
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_5:
|
|
ld.const.u64 %rd30, [params+432];
|
|
cvta.to.global.u64 %rd31, %rd30;
|
|
ld.const.u32 %r167, [params+424];
|
|
mad.lo.s32 %r168, %r167, %r85, %r84;
|
|
mul.wide.u32 %rd32, %r168, 12;
|
|
add.s64 %rd33, %rd31, %rd32;
|
|
ld.global.f32 %f218, [%rd33];
|
|
mul.f32 %f219, %f218, 0f3456BF95;
|
|
ld.global.f32 %f220, [%rd33+4];
|
|
mul.f32 %f221, %f220, 0f3456BF95;
|
|
ld.global.f32 %f222, [%rd33+8];
|
|
mul.f32 %f223, %f222, 0f3456BF95;
|
|
abs.f32 %f224, %f1013;
|
|
div.rn.f32 %f225, %f219, %f224;
|
|
abs.f32 %f226, %f1014;
|
|
div.rn.f32 %f227, %f221, %f226;
|
|
abs.f32 %f228, %f1015;
|
|
div.rn.f32 %f229, %f223, %f228;
|
|
abs.f32 %f230, %f225;
|
|
abs.f32 %f231, %f227;
|
|
abs.f32 %f232, %f229;
|
|
mov.f32 %f233, 0f38D1B717;
|
|
max.f32 %f234, %f230, %f233;
|
|
max.f32 %f235, %f231, %f233;
|
|
max.f32 %f236, %f232, %f233;
|
|
fma.rn.f32 %f1018, %f1013, %f234, %f218;
|
|
fma.rn.f32 %f1019, %f1014, %f235, %f220;
|
|
fma.rn.f32 %f1020, %f1015, %f236, %f222;
|
|
ld.const.u64 %rd3, [params+96];
|
|
neg.f32 %f214, %f1015;
|
|
neg.f32 %f213, %f1014;
|
|
neg.f32 %f212, %f1013;
|
|
mov.f32 %f216, 0f6C4ECB8F;
|
|
mov.f32 %f217, 0f00000000;
|
|
mov.u32 %r129, 1;
|
|
mov.u32 %r132, 2;
|
|
mov.u32 %r134, 3;
|
|
mov.u32 %r166, 0;
|
|
// begin inline asm
|
|
call(%r96,%r97,%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127),_optix_trace_typed_32,(%r166,%rd3,%f1018,%f1019,%f1020,%f212,%f213,%f214,%f217,%f216,%f217,%r129,%r166,%r166,%r132,%r166,%r134,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166,%r166);
|
|
// end inline asm
|
|
mov.b32 %f16, %r96;
|
|
setp.lt.f32 %p14, %f16, 0f00000000;
|
|
@%p14 bra $L__BB0_7;
|
|
bra.uni $L__BB0_6;
|
|
|
|
$L__BB0_7:
|
|
fma.rn.f32 %f237, %f1013, %f16, %f1018;
|
|
fma.rn.f32 %f238, %f1014, %f16, %f1019;
|
|
fma.rn.f32 %f239, %f1015, %f16, %f1020;
|
|
mul.f32 %f240, %f237, 0f3456BF95;
|
|
mul.f32 %f241, %f238, 0f3456BF95;
|
|
mul.f32 %f242, %f239, 0f3456BF95;
|
|
abs.f32 %f1017, %f212;
|
|
div.rn.f32 %f243, %f240, %f1017;
|
|
abs.f32 %f244, %f213;
|
|
div.rn.f32 %f245, %f241, %f244;
|
|
abs.f32 %f1016, %f214;
|
|
div.rn.f32 %f246, %f242, %f1016;
|
|
abs.f32 %f247, %f243;
|
|
abs.f32 %f248, %f245;
|
|
abs.f32 %f249, %f246;
|
|
max.f32 %f251, %f247, %f233;
|
|
max.f32 %f252, %f248, %f233;
|
|
max.f32 %f253, %f249, %f233;
|
|
fma.rn.f32 %f1018, %f251, %f212, %f237;
|
|
fma.rn.f32 %f1019, %f252, %f213, %f238;
|
|
fma.rn.f32 %f1020, %f253, %f214, %f239;
|
|
bra.uni $L__BB0_8;
|
|
|
|
$L__BB0_6:
|
|
abs.f32 %f1017, %f212;
|
|
abs.f32 %f1016, %f214;
|
|
|
|
$L__BB0_8:
|
|
setp.gt.f32 %p15, %f1017, %f1016;
|
|
selp.f32 %f260, %f1014, 0f00000000, %p15;
|
|
mov.f32 %f1039, 0f00000000;
|
|
selp.f32 %f261, %f212, %f1015, %p15;
|
|
selp.f32 %f262, 0f00000000, %f213, %p15;
|
|
mul.f32 %f263, %f261, %f261;
|
|
fma.rn.f32 %f264, %f260, %f260, %f263;
|
|
fma.rn.f32 %f265, %f262, %f262, %f264;
|
|
sqrt.rn.f32 %f266, %f265;
|
|
rcp.rn.f32 %f267, %f266;
|
|
mul.f32 %f29, %f260, %f267;
|
|
mul.f32 %f30, %f261, %f267;
|
|
mul.f32 %f31, %f262, %f267;
|
|
ld.const.u32 %r5, [params+540];
|
|
setp.lt.s32 %p16, %r5, 1;
|
|
mov.f32 %f1040, %f1039;
|
|
mov.f32 %f1041, %f1039;
|
|
mov.f32 %f1042, %f1039;
|
|
mov.f32 %f1043, %f1039;
|
|
mov.f32 %f1044, %f1039;
|
|
@%p16 bra $L__BB0_39;
|
|
|
|
ld.const.u64 %rd34, [params+128];
|
|
ld.const.u32 %r170, [params+120];
|
|
cvt.rn.f32.s32 %f274, %r5;
|
|
rcp.rn.f32 %f32, %f274;
|
|
mad.lo.s32 %r171, %r170, %r85, %r84;
|
|
cvta.to.global.u64 %rd35, %rd34;
|
|
mul.wide.u32 %rd36, %r171, 4;
|
|
add.s64 %rd37, %rd35, %rd36;
|
|
ld.global.u32 %r434, [%rd37];
|
|
mul.f32 %f33, %f1018, 0f3456BF95;
|
|
mul.f32 %f34, %f1019, 0f3456BF95;
|
|
mul.f32 %f35, %f1020, 0f3456BF95;
|
|
mul.f32 %f275, %f30, %f212;
|
|
mul.f32 %f276, %f29, %f213;
|
|
sub.f32 %f36, %f276, %f275;
|
|
mul.f32 %f277, %f29, %f214;
|
|
mul.f32 %f278, %f31, %f212;
|
|
sub.f32 %f37, %f278, %f277;
|
|
mul.f32 %f279, %f31, %f213;
|
|
mul.f32 %f280, %f30, %f214;
|
|
sub.f32 %f38, %f280, %f279;
|
|
mov.u32 %r169, 0;
|
|
add.s64 %rd4, %rd1, 24;
|
|
mov.u64 %rd38, __cudart_i2opi_f;
|
|
abs.f32 %f343, %f34;
|
|
abs.f32 %f344, %f33;
|
|
max.f32 %f345, %f344, %f343;
|
|
abs.f32 %f346, %f35;
|
|
max.f32 %f347, %f345, %f346;
|
|
mov.u32 %r431, %r169;
|
|
|
|
$L__BB0_10:
|
|
mov.u32 %r433, %r169;
|
|
|
|
$L__BB0_11:
|
|
cvt.rn.f32.s32 %f991, %r431;
|
|
mad.lo.s32 %r173, %r434, 1664525, 1013904223;
|
|
and.b32 %r174, %r173, 16777215;
|
|
cvt.rn.f32.u32 %f281, %r174;
|
|
fma.rn.f32 %f282, %f281, 0f33800000, %f991;
|
|
mul.f32 %f52, %f32, %f282;
|
|
mad.lo.s32 %r434, %r173, 1664525, 1013904223;
|
|
and.b32 %r175, %r434, 16777215;
|
|
cvt.rn.f32.u32 %f283, %r175;
|
|
cvt.rn.f32.s32 %f284, %r433;
|
|
fma.rn.f32 %f285, %f283, 0f33800000, %f284;
|
|
mul.f32 %f286, %f32, %f285;
|
|
mul.f32 %f287, %f52, %f52;
|
|
mov.f32 %f288, 0f3F800000;
|
|
sub.f32 %f289, %f288, %f287;
|
|
mov.f32 %f290, 0f00000000;
|
|
max.f32 %f291, %f290, %f289;
|
|
sqrt.rn.f32 %f53, %f291;
|
|
mul.f32 %f54, %f286, 0f40C90FDB;
|
|
mul.f32 %f292, %f54, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r441, %f292;
|
|
cvt.rn.f32.s32 %f293, %r441;
|
|
mov.f32 %f294, 0fBFC90FDA;
|
|
fma.rn.f32 %f295, %f293, %f294, %f54;
|
|
mov.f32 %f296, 0fB3A22168;
|
|
fma.rn.f32 %f297, %f293, %f296, %f295;
|
|
mov.f32 %f298, 0fA7C234C5;
|
|
fma.rn.f32 %f1036, %f293, %f298, %f297;
|
|
abs.f32 %f56, %f54;
|
|
setp.ltu.f32 %p17, %f56, 0f47CE4780;
|
|
mov.u32 %r438, %r441;
|
|
mov.f32 %f1033, %f1036;
|
|
@%p17 bra $L__BB0_19;
|
|
|
|
setp.eq.f32 %p18, %f56, 0f7F800000;
|
|
@%p18 bra $L__BB0_18;
|
|
bra.uni $L__BB0_13;
|
|
|
|
$L__BB0_18:
|
|
mov.f32 %f301, 0f00000000;
|
|
mul.rn.f32 %f1033, %f54, %f301;
|
|
mov.u32 %r438, 0;
|
|
bra.uni $L__BB0_19;
|
|
|
|
$L__BB0_13:
|
|
mov.b32 %r13, %f54;
|
|
bfe.u32 %r177, %r13, 23, 8;
|
|
add.s32 %r14, %r177, -128;
|
|
shl.b32 %r178, %r13, 8;
|
|
or.b32 %r15, %r178, -2147483648;
|
|
shr.u32 %r16, %r14, 5;
|
|
mov.u64 %rd110, 0;
|
|
mov.u32 %r435, 0;
|
|
mov.u64 %rd108, %rd1;
|
|
mov.u64 %rd109, %rd38;
|
|
|
|
$L__BB0_14:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r179, [%rd109];
|
|
mad.wide.u32 %rd40, %r179, %r15, %rd110;
|
|
shr.u64 %rd110, %rd40, 32;
|
|
st.local.u32 [%rd108], %rd40;
|
|
add.s64 %rd109, %rd109, 4;
|
|
add.s64 %rd108, %rd108, 4;
|
|
add.s32 %r435, %r435, 1;
|
|
setp.ne.s32 %p19, %r435, 6;
|
|
@%p19 bra $L__BB0_14;
|
|
|
|
st.local.u32 [%rd4], %rd110;
|
|
mov.u32 %r180, 4;
|
|
sub.s32 %r19, %r180, %r16;
|
|
mov.u32 %r181, 6;
|
|
sub.s32 %r182, %r181, %r16;
|
|
mul.wide.s32 %rd41, %r182, 4;
|
|
add.s64 %rd42, %rd1, %rd41;
|
|
ld.local.u32 %r436, [%rd42];
|
|
ld.local.u32 %r437, [%rd42+-4];
|
|
and.b32 %r22, %r14, 31;
|
|
setp.eq.s32 %p20, %r22, 0;
|
|
@%p20 bra $L__BB0_17;
|
|
|
|
mov.u32 %r183, 32;
|
|
sub.s32 %r184, %r183, %r22;
|
|
shr.u32 %r185, %r437, %r184;
|
|
shl.b32 %r186, %r436, %r22;
|
|
add.s32 %r436, %r185, %r186;
|
|
mul.wide.s32 %rd43, %r19, 4;
|
|
add.s64 %rd44, %rd1, %rd43;
|
|
ld.local.u32 %r187, [%rd44];
|
|
shr.u32 %r188, %r187, %r184;
|
|
shl.b32 %r189, %r437, %r22;
|
|
add.s32 %r437, %r188, %r189;
|
|
|
|
$L__BB0_17:
|
|
and.b32 %r190, %r13, -2147483648;
|
|
shr.u32 %r191, %r437, 30;
|
|
shl.b32 %r192, %r436, 2;
|
|
or.b32 %r193, %r191, %r192;
|
|
shr.u32 %r194, %r193, 31;
|
|
shr.u32 %r195, %r436, 30;
|
|
add.s32 %r196, %r194, %r195;
|
|
neg.s32 %r197, %r196;
|
|
setp.eq.s32 %p21, %r190, 0;
|
|
selp.b32 %r438, %r196, %r197, %p21;
|
|
setp.ne.s32 %p22, %r194, 0;
|
|
xor.b32 %r198, %r190, -2147483648;
|
|
selp.b32 %r199, %r198, %r190, %p22;
|
|
selp.b32 %r200, -1, 0, %p22;
|
|
xor.b32 %r201, %r193, %r200;
|
|
shl.b32 %r202, %r437, 2;
|
|
xor.b32 %r203, %r202, %r200;
|
|
cvt.u64.u32 %rd45, %r201;
|
|
cvt.u64.u32 %rd46, %r203;
|
|
bfi.b64 %rd47, %rd45, %rd46, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd47;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f299, %fd2;
|
|
setp.eq.s32 %p23, %r199, 0;
|
|
neg.f32 %f300, %f299;
|
|
selp.f32 %f1033, %f299, %f300, %p23;
|
|
|
|
$L__BB0_19:
|
|
add.s32 %r29, %r438, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p24, %r30, 0;
|
|
selp.f32 %f60, %f1033, 0f3F800000, %p24;
|
|
mul.rn.f32 %f61, %f1033, %f1033;
|
|
mov.f32 %f1034, 0fB94D4153;
|
|
@%p24 bra $L__BB0_21;
|
|
|
|
mov.f32 %f303, 0fBAB607ED;
|
|
mov.f32 %f304, 0f37CBAC00;
|
|
fma.rn.f32 %f1034, %f304, %f61, %f303;
|
|
|
|
$L__BB0_21:
|
|
selp.f32 %f305, 0f3C0885E4, 0f3D2AAABB, %p24;
|
|
fma.rn.f32 %f306, %f1034, %f61, %f305;
|
|
selp.f32 %f307, 0fBE2AAAA8, 0fBEFFFFFF, %p24;
|
|
fma.rn.f32 %f308, %f306, %f61, %f307;
|
|
mov.f32 %f309, 0f00000000;
|
|
fma.rn.f32 %f310, %f61, %f60, %f309;
|
|
fma.rn.f32 %f1035, %f308, %f310, %f60;
|
|
and.b32 %r205, %r29, 2;
|
|
setp.eq.s32 %p26, %r205, 0;
|
|
@%p26 bra $L__BB0_23;
|
|
|
|
mov.f32 %f312, 0fBF800000;
|
|
fma.rn.f32 %f1035, %f1035, %f312, %f309;
|
|
|
|
$L__BB0_23:
|
|
@%p17 bra $L__BB0_31;
|
|
|
|
setp.eq.f32 %p28, %f56, 0f7F800000;
|
|
@%p28 bra $L__BB0_30;
|
|
bra.uni $L__BB0_25;
|
|
|
|
$L__BB0_30:
|
|
mov.f32 %f315, 0f00000000;
|
|
mul.rn.f32 %f1036, %f54, %f315;
|
|
mov.u32 %r441, 0;
|
|
bra.uni $L__BB0_31;
|
|
|
|
$L__BB0_25:
|
|
mov.b32 %r31, %f54;
|
|
bfe.u32 %r206, %r31, 23, 8;
|
|
add.s32 %r32, %r206, -128;
|
|
shl.b32 %r207, %r31, 8;
|
|
or.b32 %r33, %r207, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd111, 0;
|
|
mov.u64 %rd112, %rd111;
|
|
|
|
$L__BB0_26:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd50, %rd111, 2;
|
|
mov.u64 %rd51, __cudart_i2opi_f;
|
|
add.s64 %rd52, %rd51, %rd50;
|
|
ld.global.nc.u32 %r208, [%rd52];
|
|
mad.wide.u32 %rd53, %r208, %r33, %rd112;
|
|
shr.u64 %rd112, %rd53, 32;
|
|
add.s64 %rd54, %rd1, %rd50;
|
|
st.local.u32 [%rd54], %rd53;
|
|
cvt.u32.u64 %r209, %rd111;
|
|
add.s32 %r210, %r209, 1;
|
|
cvt.s64.s32 %rd111, %r210;
|
|
setp.ne.s32 %p29, %r210, 6;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
st.local.u32 [%rd4], %rd112;
|
|
mov.u32 %r211, 4;
|
|
sub.s32 %r35, %r211, %r34;
|
|
mov.u32 %r212, 6;
|
|
sub.s32 %r213, %r212, %r34;
|
|
mul.wide.s32 %rd55, %r213, 4;
|
|
add.s64 %rd56, %rd1, %rd55;
|
|
ld.local.u32 %r439, [%rd56];
|
|
ld.local.u32 %r440, [%rd56+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p30, %r38, 0;
|
|
@%p30 bra $L__BB0_29;
|
|
|
|
mov.u32 %r214, 32;
|
|
sub.s32 %r215, %r214, %r38;
|
|
shr.u32 %r216, %r440, %r215;
|
|
shl.b32 %r217, %r439, %r38;
|
|
add.s32 %r439, %r216, %r217;
|
|
mul.wide.s32 %rd57, %r35, 4;
|
|
add.s64 %rd58, %rd1, %rd57;
|
|
ld.local.u32 %r218, [%rd58];
|
|
shr.u32 %r219, %r218, %r215;
|
|
shl.b32 %r220, %r440, %r38;
|
|
add.s32 %r440, %r219, %r220;
|
|
|
|
$L__BB0_29:
|
|
and.b32 %r221, %r31, -2147483648;
|
|
shr.u32 %r222, %r440, 30;
|
|
shl.b32 %r223, %r439, 2;
|
|
or.b32 %r224, %r222, %r223;
|
|
shr.u32 %r225, %r224, 31;
|
|
shr.u32 %r226, %r439, 30;
|
|
add.s32 %r227, %r225, %r226;
|
|
neg.s32 %r228, %r227;
|
|
setp.eq.s32 %p31, %r221, 0;
|
|
selp.b32 %r441, %r227, %r228, %p31;
|
|
setp.ne.s32 %p32, %r225, 0;
|
|
xor.b32 %r229, %r221, -2147483648;
|
|
selp.b32 %r230, %r229, %r221, %p32;
|
|
selp.b32 %r231, -1, 0, %p32;
|
|
xor.b32 %r232, %r224, %r231;
|
|
shl.b32 %r233, %r440, 2;
|
|
xor.b32 %r234, %r233, %r231;
|
|
cvt.u64.u32 %rd59, %r232;
|
|
cvt.u64.u32 %rd60, %r234;
|
|
bfi.b64 %rd61, %rd59, %rd60, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd61;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f313, %fd4;
|
|
setp.eq.s32 %p33, %r230, 0;
|
|
neg.f32 %f314, %f313;
|
|
selp.f32 %f1036, %f313, %f314, %p33;
|
|
|
|
$L__BB0_31:
|
|
mul.f32 %f70, %f53, %f1035;
|
|
and.b32 %r45, %r441, 1;
|
|
setp.eq.s32 %p34, %r45, 0;
|
|
selp.f32 %f71, %f1036, 0f3F800000, %p34;
|
|
mul.rn.f32 %f72, %f1036, %f1036;
|
|
mov.f32 %f1037, 0fB94D4153;
|
|
@%p34 bra $L__BB0_33;
|
|
|
|
mov.f32 %f317, 0fBAB607ED;
|
|
mov.f32 %f318, 0f37CBAC00;
|
|
fma.rn.f32 %f1037, %f318, %f72, %f317;
|
|
|
|
$L__BB0_33:
|
|
selp.f32 %f319, 0f3C0885E4, 0f3D2AAABB, %p34;
|
|
fma.rn.f32 %f320, %f1037, %f72, %f319;
|
|
selp.f32 %f321, 0fBE2AAAA8, 0fBEFFFFFF, %p34;
|
|
fma.rn.f32 %f322, %f320, %f72, %f321;
|
|
mov.f32 %f323, 0f00000000;
|
|
fma.rn.f32 %f324, %f72, %f71, %f323;
|
|
fma.rn.f32 %f1038, %f322, %f324, %f71;
|
|
and.b32 %r236, %r441, 2;
|
|
setp.eq.s32 %p36, %r236, 0;
|
|
@%p36 bra $L__BB0_35;
|
|
|
|
mov.f32 %f326, 0fBF800000;
|
|
fma.rn.f32 %f1038, %f1038, %f326, %f323;
|
|
|
|
$L__BB0_35:
|
|
mul.f32 %f336, %f53, %f1038;
|
|
mul.f32 %f337, %f29, %f336;
|
|
mul.f32 %f338, %f30, %f336;
|
|
mul.f32 %f339, %f31, %f336;
|
|
fma.rn.f32 %f340, %f38, %f70, %f337;
|
|
fma.rn.f32 %f341, %f37, %f70, %f338;
|
|
fma.rn.f32 %f342, %f36, %f70, %f339;
|
|
fma.rn.f32 %f78, %f52, %f212, %f340;
|
|
fma.rn.f32 %f79, %f52, %f213, %f341;
|
|
fma.rn.f32 %f80, %f52, %f214, %f342;
|
|
mov.f32 %f348, 0f38D1B717;
|
|
max.f32 %f333, %f347, %f348;
|
|
mov.f32 %f334, 0f6C4ECB8F;
|
|
mov.u32 %r270, 1;
|
|
mov.u32 %r273, 2;
|
|
mov.u32 %r275, 3;
|
|
mov.u32 %r278, -1082130432;
|
|
mov.u32 %r307, 0;
|
|
// begin inline asm
|
|
call(%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268),_optix_trace_typed_32,(%r307,%rd3,%f1018,%f1019,%f1020,%f78,%f79,%f80,%f333,%f334,%f323,%r270,%r307,%r307,%r273,%r307,%r275,%r278,%r278,%r278,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307);
|
|
// end inline asm
|
|
mov.b32 %f81, %r237;
|
|
setp.lt.f32 %p37, %f81, 0f00000000;
|
|
@%p37 bra $L__BB0_37;
|
|
|
|
mov.b32 %f349, %r238;
|
|
mov.b32 %f350, %r239;
|
|
mul.f32 %f351, %f79, %f213;
|
|
fma.rn.f32 %f352, %f78, %f212, %f351;
|
|
fma.rn.f32 %f353, %f80, %f214, %f352;
|
|
mul.f32 %f354, %f353, 0f40800000;
|
|
cvt.sat.f32.f32 %f355, %f354;
|
|
fma.rn.f32 %f1042, %f355, %f81, %f1042;
|
|
fma.rn.f32 %f1043, %f355, %f349, %f1043;
|
|
fma.rn.f32 %f1044, %f355, %f350, %f1044;
|
|
cvt.sat.f32.f32 %f356, %f353;
|
|
fma.rn.f32 %f1041, %f356, %f81, %f1041;
|
|
fma.rn.f32 %f1040, %f356, %f349, %f1040;
|
|
fma.rn.f32 %f1039, %f356, %f350, %f1039;
|
|
|
|
$L__BB0_37:
|
|
add.s32 %r433, %r433, 1;
|
|
setp.lt.s32 %p38, %r433, %r5;
|
|
@%p38 bra $L__BB0_11;
|
|
|
|
add.s32 %r431, %r431, 1;
|
|
setp.lt.s32 %p39, %r431, %r5;
|
|
@%p39 bra $L__BB0_10;
|
|
|
|
$L__BB0_39:
|
|
mul.lo.s32 %r308, %r5, %r5;
|
|
cvt.rn.f32.s32 %f357, %r308;
|
|
rcp.rn.f32 %f100, %f357;
|
|
mul.f32 %f358, %f1041, %f100;
|
|
mul.f32 %f359, %f1040, %f100;
|
|
mul.f32 %f360, %f1039, %f100;
|
|
fma.rn.f32 %f101, %f1041, %f100, %f358;
|
|
fma.rn.f32 %f102, %f1040, %f100, %f359;
|
|
fma.rn.f32 %f103, %f1039, %f100, %f360;
|
|
ld.const.u32 %r80, [params+104];
|
|
and.b32 %r309, %r80, 1;
|
|
setp.eq.b32 %p40, %r309, 1;
|
|
mov.pred %p41, 0;
|
|
xor.pred %p42, %p40, %p41;
|
|
not.pred %p43, %p42;
|
|
@%p43 bra $L__BB0_113;
|
|
|
|
mov.f32 %f365, 0f3EE66666;
|
|
abs.f32 %f105, %f101;
|
|
setp.lt.f32 %p44, %f105, 0f00800000;
|
|
mul.f32 %f367, %f105, 0f4B800000;
|
|
selp.f32 %f368, %f367, %f105, %p44;
|
|
selp.f32 %f369, 0fC3170000, 0fC2FE0000, %p44;
|
|
mov.b32 %r310, %f368;
|
|
and.b32 %r311, %r310, 8388607;
|
|
or.b32 %r312, %r311, 1065353216;
|
|
mov.b32 %f370, %r312;
|
|
shr.u32 %r313, %r310, 23;
|
|
cvt.rn.f32.u32 %f371, %r313;
|
|
add.f32 %f372, %f369, %f371;
|
|
setp.gt.f32 %p45, %f370, 0f3FB504F3;
|
|
mul.f32 %f373, %f370, 0f3F000000;
|
|
add.f32 %f374, %f372, 0f3F800000;
|
|
selp.f32 %f375, %f374, %f372, %p45;
|
|
selp.f32 %f376, %f373, %f370, %p45;
|
|
add.f32 %f377, %f376, 0fBF800000;
|
|
add.f32 %f378, %f376, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f379, %f378;
|
|
add.f32 %f380, %f377, %f377;
|
|
mul.f32 %f381, %f380, %f379;
|
|
mul.f32 %f382, %f381, %f381;
|
|
mov.f32 %f383, 0f3C4CAF63;
|
|
mov.f32 %f384, 0f3B18F0FE;
|
|
fma.rn.f32 %f385, %f384, %f382, %f383;
|
|
mov.f32 %f386, 0f3DAAAABD;
|
|
fma.rn.f32 %f387, %f385, %f382, %f386;
|
|
mul.rn.f32 %f388, %f387, %f382;
|
|
mul.rn.f32 %f389, %f388, %f381;
|
|
sub.f32 %f390, %f377, %f381;
|
|
add.f32 %f391, %f390, %f390;
|
|
neg.f32 %f392, %f381;
|
|
fma.rn.f32 %f393, %f392, %f377, %f391;
|
|
mul.rn.f32 %f394, %f379, %f393;
|
|
add.f32 %f395, %f389, %f381;
|
|
sub.f32 %f396, %f381, %f395;
|
|
add.f32 %f397, %f389, %f396;
|
|
add.f32 %f398, %f394, %f397;
|
|
add.f32 %f399, %f395, %f398;
|
|
sub.f32 %f400, %f395, %f399;
|
|
add.f32 %f401, %f398, %f400;
|
|
mov.f32 %f402, 0f3F317200;
|
|
mul.rn.f32 %f403, %f375, %f402;
|
|
mov.f32 %f404, 0f35BFBE8E;
|
|
mul.rn.f32 %f405, %f375, %f404;
|
|
add.f32 %f406, %f403, %f399;
|
|
sub.f32 %f407, %f403, %f406;
|
|
add.f32 %f408, %f399, %f407;
|
|
add.f32 %f409, %f401, %f408;
|
|
add.f32 %f410, %f405, %f409;
|
|
add.f32 %f411, %f406, %f410;
|
|
sub.f32 %f412, %f406, %f411;
|
|
add.f32 %f413, %f410, %f412;
|
|
mul.rn.f32 %f414, %f365, %f411;
|
|
neg.f32 %f415, %f414;
|
|
fma.rn.f32 %f416, %f365, %f411, %f415;
|
|
fma.rn.f32 %f417, %f365, %f413, %f416;
|
|
mov.f32 %f418, 0f00000000;
|
|
fma.rn.f32 %f419, %f418, %f411, %f417;
|
|
add.rn.f32 %f420, %f414, %f419;
|
|
neg.f32 %f421, %f420;
|
|
add.rn.f32 %f422, %f414, %f421;
|
|
add.rn.f32 %f423, %f422, %f419;
|
|
mov.b32 %r314, %f420;
|
|
setp.eq.s32 %p46, %r314, 1118925336;
|
|
add.s32 %r315, %r314, -1;
|
|
mov.b32 %f424, %r315;
|
|
add.f32 %f425, %f423, 0f37000000;
|
|
selp.f32 %f106, %f425, %f423, %p46;
|
|
selp.f32 %f426, %f424, %f420, %p46;
|
|
mov.f32 %f427, 0f3FB8AA3B;
|
|
mul.rn.f32 %f428, %f426, %f427;
|
|
cvt.rzi.f32.f32 %f429, %f428;
|
|
abs.f32 %f430, %f429;
|
|
setp.gt.f32 %p47, %f430, 0f42FC0000;
|
|
mov.b32 %r316, %f429;
|
|
and.b32 %r317, %r316, -2147483648;
|
|
or.b32 %r318, %r317, 1123811328;
|
|
mov.b32 %f431, %r318;
|
|
selp.f32 %f432, %f431, %f429, %p47;
|
|
mov.f32 %f433, 0fBF317218;
|
|
fma.rn.f32 %f434, %f432, %f433, %f426;
|
|
mov.f32 %f435, 0f3102E308;
|
|
fma.rn.f32 %f436, %f432, %f435, %f434;
|
|
mul.f32 %f437, %f436, 0f3FB8AA3B;
|
|
add.f32 %f438, %f432, 0f4B40007F;
|
|
mov.b32 %r319, %f438;
|
|
shl.b32 %r320, %r319, 23;
|
|
mov.b32 %f439, %r320;
|
|
ex2.approx.ftz.f32 %f440, %f437;
|
|
mul.f32 %f107, %f440, %f439;
|
|
setp.eq.f32 %p48, %f107, 0f7F800000;
|
|
mov.f32 %f1051, 0f7F800000;
|
|
@%p48 bra $L__BB0_42;
|
|
|
|
fma.rn.f32 %f1051, %f107, %f106, %f107;
|
|
|
|
$L__BB0_42:
|
|
mov.f32 %f997, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f996, %f997;
|
|
add.f32 %f995, %f996, %f996;
|
|
mov.f32 %f994, 0f3EE66666;
|
|
sub.f32 %f993, %f994, %f995;
|
|
abs.f32 %f992, %f993;
|
|
setp.lt.f32 %p49, %f101, 0f00000000;
|
|
setp.eq.f32 %p50, %f992, 0f3F800000;
|
|
and.pred %p1, %p49, %p50;
|
|
setp.eq.f32 %p51, %f101, 0f00000000;
|
|
@%p51 bra $L__BB0_46;
|
|
bra.uni $L__BB0_43;
|
|
|
|
$L__BB0_46:
|
|
add.f32 %f445, %f101, %f101;
|
|
selp.f32 %f1053, %f445, 0f00000000, %p50;
|
|
bra.uni $L__BB0_47;
|
|
|
|
$L__BB0_135:
|
|
mov.f32 %f963, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f963;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f963;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f963;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs109, 0;
|
|
st.global.v4.u16 [%rd21], {%rs106, %rs107, %rs108, %rs109};
|
|
|
|
$L__BB0_136:
|
|
ld.const.u64 %rd97, [params+272];
|
|
cvta.to.global.u64 %rd98, %rd97;
|
|
ld.const.u32 %r424, [params+264];
|
|
mad.lo.s32 %r425, %r424, %r4, %r3;
|
|
mul.wide.u32 %rd99, %r425, 8;
|
|
add.s64 %rd22, %rd98, %rd99;
|
|
@%p148 bra $L__BB0_138;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f964, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f965, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f966, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f967, %f964, 0f00000000;
|
|
add.f32 %f968, %f965, 0f00000000;
|
|
add.f32 %f969, %f966, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f969;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f968;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f967;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs120, 0;
|
|
st.global.v4.u16 [%rd22], {%rs113, %rs114, %rs115, %rs120};
|
|
bra.uni $L__BB0_139;
|
|
|
|
$L__BB0_138:
|
|
mov.f32 %f972, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f972;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f972;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f972;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs124, 0;
|
|
st.global.v4.u16 [%rd22], {%rs121, %rs122, %rs123, %rs124};
|
|
|
|
$L__BB0_139:
|
|
ld.const.u64 %rd100, [params+288];
|
|
cvta.to.global.u64 %rd101, %rd100;
|
|
ld.const.u32 %r426, [params+280];
|
|
mad.lo.s32 %r427, %r426, %r4, %r3;
|
|
mul.wide.u32 %rd102, %r427, 8;
|
|
add.s64 %rd23, %rd101, %rd102;
|
|
@%p148 bra $L__BB0_141;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f973, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f974, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f975, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f976, %f973, 0f00000000;
|
|
add.f32 %f977, %f974, 0f00000000;
|
|
add.f32 %f978, %f975, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f978;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f977;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f976;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs135, 0;
|
|
st.global.v4.u16 [%rd23], {%rs128, %rs129, %rs130, %rs135};
|
|
bra.uni $L__BB0_142;
|
|
|
|
$L__BB0_141:
|
|
mov.f32 %f981, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f981;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f981;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f981;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs139, 0;
|
|
st.global.v4.u16 [%rd23], {%rs136, %rs137, %rs138, %rs139};
|
|
|
|
$L__BB0_142:
|
|
ld.const.u64 %rd103, [params+304];
|
|
cvta.to.global.u64 %rd104, %rd103;
|
|
ld.const.u32 %r428, [params+296];
|
|
mad.lo.s32 %r429, %r428, %r4, %r3;
|
|
mul.wide.u32 %rd105, %r429, 8;
|
|
add.s64 %rd24, %rd104, %rd105;
|
|
@%p148 bra $L__BB0_144;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f982, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f983, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f984, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f985, %f982, 0f00000000;
|
|
add.f32 %f986, %f983, 0f00000000;
|
|
add.f32 %f987, %f984, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f987;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f986;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f985;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs150, 0;
|
|
st.global.v4.u16 [%rd24], {%rs143, %rs144, %rs145, %rs150};
|
|
bra.uni $L__BB0_145;
|
|
|
|
$L__BB0_144:
|
|
mov.f32 %f990, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f990;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f990;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f990;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs154, 0;
|
|
st.global.v4.u16 [%rd24], {%rs151, %rs152, %rs153, %rs154};
|
|
bra.uni $L__BB0_145;
|
|
|
|
$L__BB0_43:
|
|
mov.b32 %r321, %f1051;
|
|
xor.b32 %r322, %r321, -2147483648;
|
|
mov.b32 %f441, %r322;
|
|
selp.f32 %f1053, %f441, %f1051, %p1;
|
|
setp.geu.f32 %p52, %f101, 0f00000000;
|
|
@%p52 bra $L__BB0_47;
|
|
|
|
mov.f32 %f442, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f443, %f442;
|
|
setp.eq.f32 %p53, %f443, 0f3EE66666;
|
|
@%p53 bra $L__BB0_47;
|
|
|
|
mov.f32 %f1053, 0f7FFFFFFF;
|
|
|
|
$L__BB0_47:
|
|
abs.f32 %f998, %f101;
|
|
add.f32 %f446, %f998, 0f3EE66666;
|
|
mov.b32 %r323, %f446;
|
|
setp.lt.s32 %p55, %r323, 2139095040;
|
|
@%p55 bra $L__BB0_52;
|
|
|
|
abs.f32 %f999, %f101;
|
|
setp.gtu.f32 %p56, %f999, 0f7F800000;
|
|
@%p56 bra $L__BB0_51;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_51:
|
|
add.f32 %f1053, %f101, 0f3EE66666;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_49:
|
|
abs.f32 %f1000, %f101;
|
|
setp.neu.f32 %p57, %f1000, 0f7F800000;
|
|
@%p57 bra $L__BB0_52;
|
|
|
|
selp.f32 %f1053, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_52:
|
|
setp.eq.f32 %p58, %f101, 0f3F800000;
|
|
selp.f32 %f116, 0f3F800000, %f1053, %p58;
|
|
abs.f32 %f117, %f102;
|
|
setp.lt.f32 %p59, %f117, 0f00800000;
|
|
mul.f32 %f448, %f117, 0f4B800000;
|
|
selp.f32 %f449, %f448, %f117, %p59;
|
|
selp.f32 %f450, 0fC3170000, 0fC2FE0000, %p59;
|
|
mov.b32 %r324, %f449;
|
|
and.b32 %r325, %r324, 8388607;
|
|
or.b32 %r326, %r325, 1065353216;
|
|
mov.b32 %f451, %r326;
|
|
shr.u32 %r327, %r324, 23;
|
|
cvt.rn.f32.u32 %f452, %r327;
|
|
add.f32 %f453, %f450, %f452;
|
|
setp.gt.f32 %p60, %f451, 0f3FB504F3;
|
|
mul.f32 %f454, %f451, 0f3F000000;
|
|
add.f32 %f455, %f453, 0f3F800000;
|
|
selp.f32 %f456, %f455, %f453, %p60;
|
|
selp.f32 %f457, %f454, %f451, %p60;
|
|
add.f32 %f458, %f457, 0fBF800000;
|
|
add.f32 %f459, %f457, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f460, %f459;
|
|
add.f32 %f461, %f458, %f458;
|
|
mul.f32 %f462, %f461, %f460;
|
|
mul.f32 %f463, %f462, %f462;
|
|
mov.f32 %f464, 0f3C4CAF63;
|
|
mov.f32 %f465, 0f3B18F0FE;
|
|
fma.rn.f32 %f466, %f465, %f463, %f464;
|
|
mov.f32 %f467, 0f3DAAAABD;
|
|
fma.rn.f32 %f468, %f466, %f463, %f467;
|
|
mul.rn.f32 %f469, %f468, %f463;
|
|
mul.rn.f32 %f470, %f469, %f462;
|
|
sub.f32 %f471, %f458, %f462;
|
|
add.f32 %f472, %f471, %f471;
|
|
neg.f32 %f473, %f462;
|
|
fma.rn.f32 %f474, %f473, %f458, %f472;
|
|
mul.rn.f32 %f475, %f460, %f474;
|
|
add.f32 %f476, %f470, %f462;
|
|
sub.f32 %f477, %f462, %f476;
|
|
add.f32 %f478, %f470, %f477;
|
|
add.f32 %f479, %f475, %f478;
|
|
add.f32 %f480, %f476, %f479;
|
|
sub.f32 %f481, %f476, %f480;
|
|
add.f32 %f482, %f479, %f481;
|
|
mov.f32 %f483, 0f3F317200;
|
|
mul.rn.f32 %f484, %f456, %f483;
|
|
mov.f32 %f485, 0f35BFBE8E;
|
|
mul.rn.f32 %f486, %f456, %f485;
|
|
add.f32 %f487, %f484, %f480;
|
|
sub.f32 %f488, %f484, %f487;
|
|
add.f32 %f489, %f480, %f488;
|
|
add.f32 %f490, %f482, %f489;
|
|
add.f32 %f491, %f486, %f490;
|
|
add.f32 %f492, %f487, %f491;
|
|
sub.f32 %f493, %f487, %f492;
|
|
add.f32 %f494, %f491, %f493;
|
|
mov.f32 %f495, 0f3EE66666;
|
|
mul.rn.f32 %f496, %f495, %f492;
|
|
neg.f32 %f497, %f496;
|
|
fma.rn.f32 %f498, %f495, %f492, %f497;
|
|
fma.rn.f32 %f499, %f495, %f494, %f498;
|
|
mov.f32 %f500, 0f00000000;
|
|
fma.rn.f32 %f501, %f500, %f492, %f499;
|
|
add.rn.f32 %f502, %f496, %f501;
|
|
neg.f32 %f503, %f502;
|
|
add.rn.f32 %f504, %f496, %f503;
|
|
add.rn.f32 %f505, %f504, %f501;
|
|
mov.b32 %r328, %f502;
|
|
setp.eq.s32 %p61, %r328, 1118925336;
|
|
add.s32 %r329, %r328, -1;
|
|
mov.b32 %f506, %r329;
|
|
add.f32 %f507, %f505, 0f37000000;
|
|
selp.f32 %f118, %f507, %f505, %p61;
|
|
selp.f32 %f508, %f506, %f502, %p61;
|
|
mov.f32 %f509, 0f3FB8AA3B;
|
|
mul.rn.f32 %f510, %f508, %f509;
|
|
cvt.rzi.f32.f32 %f511, %f510;
|
|
abs.f32 %f512, %f511;
|
|
setp.gt.f32 %p62, %f512, 0f42FC0000;
|
|
mov.b32 %r330, %f511;
|
|
and.b32 %r331, %r330, -2147483648;
|
|
or.b32 %r332, %r331, 1123811328;
|
|
mov.b32 %f513, %r332;
|
|
selp.f32 %f514, %f513, %f511, %p62;
|
|
mov.f32 %f515, 0fBF317218;
|
|
fma.rn.f32 %f516, %f514, %f515, %f508;
|
|
mov.f32 %f517, 0f3102E308;
|
|
fma.rn.f32 %f518, %f514, %f517, %f516;
|
|
mul.f32 %f519, %f518, 0f3FB8AA3B;
|
|
add.f32 %f520, %f514, 0f4B40007F;
|
|
mov.b32 %r333, %f520;
|
|
shl.b32 %r334, %r333, 23;
|
|
mov.b32 %f521, %r334;
|
|
ex2.approx.ftz.f32 %f522, %f519;
|
|
mul.f32 %f119, %f522, %f521;
|
|
setp.eq.f32 %p63, %f119, 0f7F800000;
|
|
mov.f32 %f1054, 0f7F800000;
|
|
@%p63 bra $L__BB0_54;
|
|
|
|
fma.rn.f32 %f1054, %f119, %f118, %f119;
|
|
|
|
$L__BB0_54:
|
|
setp.lt.f32 %p64, %f102, 0f00000000;
|
|
and.pred %p2, %p64, %p50;
|
|
setp.eq.f32 %p66, %f102, 0f00000000;
|
|
@%p66 bra $L__BB0_58;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_58:
|
|
add.f32 %f527, %f102, %f102;
|
|
selp.f32 %f1056, %f527, 0f00000000, %p50;
|
|
bra.uni $L__BB0_59;
|
|
|
|
$L__BB0_55:
|
|
mov.b32 %r335, %f1054;
|
|
xor.b32 %r336, %r335, -2147483648;
|
|
mov.b32 %f523, %r336;
|
|
selp.f32 %f1056, %f523, %f1054, %p2;
|
|
setp.geu.f32 %p67, %f102, 0f00000000;
|
|
@%p67 bra $L__BB0_59;
|
|
|
|
mov.f32 %f524, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f525, %f524;
|
|
setp.eq.f32 %p68, %f525, 0f3EE66666;
|
|
@%p68 bra $L__BB0_59;
|
|
|
|
mov.f32 %f1056, 0f7FFFFFFF;
|
|
|
|
$L__BB0_59:
|
|
abs.f32 %f1001, %f102;
|
|
add.f32 %f528, %f1001, 0f3EE66666;
|
|
mov.b32 %r337, %f528;
|
|
setp.lt.s32 %p70, %r337, 2139095040;
|
|
@%p70 bra $L__BB0_64;
|
|
|
|
abs.f32 %f1002, %f102;
|
|
setp.gtu.f32 %p71, %f1002, 0f7F800000;
|
|
@%p71 bra $L__BB0_63;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_63:
|
|
add.f32 %f1056, %f102, 0f3EE66666;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_61:
|
|
abs.f32 %f1003, %f102;
|
|
setp.neu.f32 %p72, %f1003, 0f7F800000;
|
|
@%p72 bra $L__BB0_64;
|
|
|
|
selp.f32 %f1056, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_64:
|
|
setp.eq.f32 %p73, %f102, 0f3F800000;
|
|
selp.f32 %f128, 0f3F800000, %f1056, %p73;
|
|
abs.f32 %f129, %f103;
|
|
setp.lt.f32 %p74, %f129, 0f00800000;
|
|
mul.f32 %f530, %f129, 0f4B800000;
|
|
selp.f32 %f531, %f530, %f129, %p74;
|
|
selp.f32 %f532, 0fC3170000, 0fC2FE0000, %p74;
|
|
mov.b32 %r338, %f531;
|
|
and.b32 %r339, %r338, 8388607;
|
|
or.b32 %r340, %r339, 1065353216;
|
|
mov.b32 %f533, %r340;
|
|
shr.u32 %r341, %r338, 23;
|
|
cvt.rn.f32.u32 %f534, %r341;
|
|
add.f32 %f535, %f532, %f534;
|
|
setp.gt.f32 %p75, %f533, 0f3FB504F3;
|
|
mul.f32 %f536, %f533, 0f3F000000;
|
|
add.f32 %f537, %f535, 0f3F800000;
|
|
selp.f32 %f538, %f537, %f535, %p75;
|
|
selp.f32 %f539, %f536, %f533, %p75;
|
|
add.f32 %f540, %f539, 0fBF800000;
|
|
add.f32 %f541, %f539, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f542, %f541;
|
|
add.f32 %f543, %f540, %f540;
|
|
mul.f32 %f544, %f543, %f542;
|
|
mul.f32 %f545, %f544, %f544;
|
|
mov.f32 %f546, 0f3C4CAF63;
|
|
mov.f32 %f547, 0f3B18F0FE;
|
|
fma.rn.f32 %f548, %f547, %f545, %f546;
|
|
mov.f32 %f549, 0f3DAAAABD;
|
|
fma.rn.f32 %f550, %f548, %f545, %f549;
|
|
mul.rn.f32 %f551, %f550, %f545;
|
|
mul.rn.f32 %f552, %f551, %f544;
|
|
sub.f32 %f553, %f540, %f544;
|
|
add.f32 %f554, %f553, %f553;
|
|
neg.f32 %f555, %f544;
|
|
fma.rn.f32 %f556, %f555, %f540, %f554;
|
|
mul.rn.f32 %f557, %f542, %f556;
|
|
add.f32 %f558, %f552, %f544;
|
|
sub.f32 %f559, %f544, %f558;
|
|
add.f32 %f560, %f552, %f559;
|
|
add.f32 %f561, %f557, %f560;
|
|
add.f32 %f562, %f558, %f561;
|
|
sub.f32 %f563, %f558, %f562;
|
|
add.f32 %f564, %f561, %f563;
|
|
mov.f32 %f565, 0f3F317200;
|
|
mul.rn.f32 %f566, %f538, %f565;
|
|
mov.f32 %f567, 0f35BFBE8E;
|
|
mul.rn.f32 %f568, %f538, %f567;
|
|
add.f32 %f569, %f566, %f562;
|
|
sub.f32 %f570, %f566, %f569;
|
|
add.f32 %f571, %f562, %f570;
|
|
add.f32 %f572, %f564, %f571;
|
|
add.f32 %f573, %f568, %f572;
|
|
add.f32 %f574, %f569, %f573;
|
|
sub.f32 %f575, %f569, %f574;
|
|
add.f32 %f576, %f573, %f575;
|
|
mov.f32 %f577, 0f3EE66666;
|
|
mul.rn.f32 %f578, %f577, %f574;
|
|
neg.f32 %f579, %f578;
|
|
fma.rn.f32 %f580, %f577, %f574, %f579;
|
|
fma.rn.f32 %f581, %f577, %f576, %f580;
|
|
mov.f32 %f582, 0f00000000;
|
|
fma.rn.f32 %f583, %f582, %f574, %f581;
|
|
add.rn.f32 %f584, %f578, %f583;
|
|
neg.f32 %f585, %f584;
|
|
add.rn.f32 %f586, %f578, %f585;
|
|
add.rn.f32 %f587, %f586, %f583;
|
|
mov.b32 %r342, %f584;
|
|
setp.eq.s32 %p76, %r342, 1118925336;
|
|
add.s32 %r343, %r342, -1;
|
|
mov.b32 %f588, %r343;
|
|
add.f32 %f589, %f587, 0f37000000;
|
|
selp.f32 %f130, %f589, %f587, %p76;
|
|
selp.f32 %f590, %f588, %f584, %p76;
|
|
mov.f32 %f591, 0f3FB8AA3B;
|
|
mul.rn.f32 %f592, %f590, %f591;
|
|
cvt.rzi.f32.f32 %f593, %f592;
|
|
abs.f32 %f594, %f593;
|
|
setp.gt.f32 %p77, %f594, 0f42FC0000;
|
|
mov.b32 %r344, %f593;
|
|
and.b32 %r345, %r344, -2147483648;
|
|
or.b32 %r346, %r345, 1123811328;
|
|
mov.b32 %f595, %r346;
|
|
selp.f32 %f596, %f595, %f593, %p77;
|
|
mov.f32 %f597, 0fBF317218;
|
|
fma.rn.f32 %f598, %f596, %f597, %f590;
|
|
mov.f32 %f599, 0f3102E308;
|
|
fma.rn.f32 %f600, %f596, %f599, %f598;
|
|
mul.f32 %f601, %f600, 0f3FB8AA3B;
|
|
add.f32 %f602, %f596, 0f4B40007F;
|
|
mov.b32 %r347, %f602;
|
|
shl.b32 %r348, %r347, 23;
|
|
mov.b32 %f603, %r348;
|
|
ex2.approx.ftz.f32 %f604, %f601;
|
|
mul.f32 %f131, %f604, %f603;
|
|
setp.eq.f32 %p78, %f131, 0f7F800000;
|
|
mov.f32 %f1057, 0f7F800000;
|
|
@%p78 bra $L__BB0_66;
|
|
|
|
fma.rn.f32 %f1057, %f131, %f130, %f131;
|
|
|
|
$L__BB0_66:
|
|
setp.lt.f32 %p79, %f103, 0f00000000;
|
|
and.pred %p3, %p79, %p50;
|
|
setp.eq.f32 %p81, %f103, 0f00000000;
|
|
@%p81 bra $L__BB0_70;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_70:
|
|
add.f32 %f609, %f103, %f103;
|
|
selp.f32 %f1059, %f609, 0f00000000, %p50;
|
|
bra.uni $L__BB0_71;
|
|
|
|
$L__BB0_67:
|
|
mov.b32 %r349, %f1057;
|
|
xor.b32 %r350, %r349, -2147483648;
|
|
mov.b32 %f605, %r350;
|
|
selp.f32 %f1059, %f605, %f1057, %p3;
|
|
setp.geu.f32 %p82, %f103, 0f00000000;
|
|
@%p82 bra $L__BB0_71;
|
|
|
|
mov.f32 %f606, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f607, %f606;
|
|
setp.eq.f32 %p83, %f607, 0f3EE66666;
|
|
@%p83 bra $L__BB0_71;
|
|
|
|
mov.f32 %f1059, 0f7FFFFFFF;
|
|
|
|
$L__BB0_71:
|
|
abs.f32 %f1004, %f103;
|
|
add.f32 %f610, %f1004, 0f3EE66666;
|
|
mov.b32 %r351, %f610;
|
|
setp.lt.s32 %p85, %r351, 2139095040;
|
|
@%p85 bra $L__BB0_76;
|
|
|
|
abs.f32 %f1005, %f103;
|
|
setp.gtu.f32 %p86, %f1005, 0f7F800000;
|
|
@%p86 bra $L__BB0_75;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f1059, %f103, 0f3EE66666;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_73:
|
|
abs.f32 %f1006, %f103;
|
|
setp.neu.f32 %p87, %f1006, 0f7F800000;
|
|
@%p87 bra $L__BB0_76;
|
|
|
|
selp.f32 %f1059, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_76:
|
|
setp.eq.f32 %p88, %f103, 0f3F800000;
|
|
mov.f32 %f612, 0f3F800000;
|
|
selp.f32 %f613, 0f3F800000, %f1059, %p88;
|
|
ld.const.u32 %r352, [params+136];
|
|
mad.lo.s32 %r353, %r352, %r4, %r3;
|
|
cvt.u64.u32 %rd16, %r353;
|
|
min.f32 %f614, %f116, %f612;
|
|
mov.f32 %f615, 0f00000000;
|
|
max.f32 %f140, %f615, %f614;
|
|
min.f32 %f616, %f128, %f612;
|
|
max.f32 %f141, %f615, %f616;
|
|
min.f32 %f617, %f613, %f612;
|
|
max.f32 %f142, %f615, %f617;
|
|
mov.f32 %f621, 0f3ED55555;
|
|
abs.f32 %f144, %f140;
|
|
setp.lt.f32 %p89, %f144, 0f00800000;
|
|
mul.f32 %f623, %f144, 0f4B800000;
|
|
selp.f32 %f624, %f623, %f144, %p89;
|
|
selp.f32 %f625, 0fC3170000, 0fC2FE0000, %p89;
|
|
mov.b32 %r354, %f624;
|
|
and.b32 %r355, %r354, 8388607;
|
|
or.b32 %r356, %r355, 1065353216;
|
|
mov.b32 %f626, %r356;
|
|
shr.u32 %r357, %r354, 23;
|
|
cvt.rn.f32.u32 %f627, %r357;
|
|
add.f32 %f628, %f625, %f627;
|
|
setp.gt.f32 %p90, %f626, 0f3FB504F3;
|
|
mul.f32 %f629, %f626, 0f3F000000;
|
|
add.f32 %f630, %f628, 0f3F800000;
|
|
selp.f32 %f631, %f630, %f628, %p90;
|
|
selp.f32 %f632, %f629, %f626, %p90;
|
|
add.f32 %f633, %f632, 0fBF800000;
|
|
add.f32 %f634, %f632, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f635, %f634;
|
|
add.f32 %f636, %f633, %f633;
|
|
mul.f32 %f637, %f636, %f635;
|
|
mul.f32 %f638, %f637, %f637;
|
|
mov.f32 %f639, 0f3C4CAF63;
|
|
mov.f32 %f640, 0f3B18F0FE;
|
|
fma.rn.f32 %f641, %f640, %f638, %f639;
|
|
mov.f32 %f642, 0f3DAAAABD;
|
|
fma.rn.f32 %f643, %f641, %f638, %f642;
|
|
mul.rn.f32 %f644, %f643, %f638;
|
|
mul.rn.f32 %f645, %f644, %f637;
|
|
sub.f32 %f646, %f633, %f637;
|
|
add.f32 %f647, %f646, %f646;
|
|
neg.f32 %f648, %f637;
|
|
fma.rn.f32 %f649, %f648, %f633, %f647;
|
|
mul.rn.f32 %f650, %f635, %f649;
|
|
add.f32 %f651, %f645, %f637;
|
|
sub.f32 %f652, %f637, %f651;
|
|
add.f32 %f653, %f645, %f652;
|
|
add.f32 %f654, %f650, %f653;
|
|
add.f32 %f655, %f651, %f654;
|
|
sub.f32 %f656, %f651, %f655;
|
|
add.f32 %f657, %f654, %f656;
|
|
mov.f32 %f658, 0f3F317200;
|
|
mul.rn.f32 %f659, %f631, %f658;
|
|
mov.f32 %f660, 0f35BFBE8E;
|
|
mul.rn.f32 %f661, %f631, %f660;
|
|
add.f32 %f662, %f659, %f655;
|
|
sub.f32 %f663, %f659, %f662;
|
|
add.f32 %f664, %f655, %f663;
|
|
add.f32 %f665, %f657, %f664;
|
|
add.f32 %f666, %f661, %f665;
|
|
add.f32 %f667, %f662, %f666;
|
|
sub.f32 %f668, %f662, %f667;
|
|
add.f32 %f669, %f666, %f668;
|
|
mul.rn.f32 %f670, %f621, %f667;
|
|
neg.f32 %f671, %f670;
|
|
fma.rn.f32 %f672, %f621, %f667, %f671;
|
|
fma.rn.f32 %f673, %f621, %f669, %f672;
|
|
fma.rn.f32 %f674, %f615, %f667, %f673;
|
|
add.rn.f32 %f675, %f670, %f674;
|
|
neg.f32 %f676, %f675;
|
|
add.rn.f32 %f677, %f670, %f676;
|
|
add.rn.f32 %f678, %f677, %f674;
|
|
mov.b32 %r358, %f675;
|
|
setp.eq.s32 %p91, %r358, 1118925336;
|
|
add.s32 %r359, %r358, -1;
|
|
mov.b32 %f679, %r359;
|
|
add.f32 %f680, %f678, 0f37000000;
|
|
selp.f32 %f145, %f680, %f678, %p91;
|
|
selp.f32 %f681, %f679, %f675, %p91;
|
|
mov.f32 %f682, 0f3FB8AA3B;
|
|
mul.rn.f32 %f683, %f681, %f682;
|
|
cvt.rzi.f32.f32 %f684, %f683;
|
|
abs.f32 %f685, %f684;
|
|
setp.gt.f32 %p92, %f685, 0f42FC0000;
|
|
mov.b32 %r360, %f684;
|
|
and.b32 %r361, %r360, -2147483648;
|
|
or.b32 %r362, %r361, 1123811328;
|
|
mov.b32 %f686, %r362;
|
|
selp.f32 %f687, %f686, %f684, %p92;
|
|
mov.f32 %f688, 0fBF317218;
|
|
fma.rn.f32 %f689, %f687, %f688, %f681;
|
|
mov.f32 %f690, 0f3102E308;
|
|
fma.rn.f32 %f691, %f687, %f690, %f689;
|
|
mul.f32 %f692, %f691, 0f3FB8AA3B;
|
|
add.f32 %f693, %f687, 0f4B40007F;
|
|
mov.b32 %r363, %f693;
|
|
shl.b32 %r364, %r363, 23;
|
|
mov.b32 %f694, %r364;
|
|
ex2.approx.ftz.f32 %f695, %f692;
|
|
mul.f32 %f146, %f695, %f694;
|
|
setp.eq.f32 %p93, %f146, 0f7F800000;
|
|
mov.f32 %f1060, 0f7F800000;
|
|
@%p93 bra $L__BB0_78;
|
|
|
|
fma.rn.f32 %f1060, %f146, %f145, %f146;
|
|
|
|
$L__BB0_78:
|
|
mov.f32 %f1012, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1011, %f1012;
|
|
add.f32 %f1010, %f1011, %f1011;
|
|
mov.f32 %f1009, 0f3ED55555;
|
|
sub.f32 %f1008, %f1009, %f1010;
|
|
abs.f32 %f1007, %f1008;
|
|
setp.lt.f32 %p94, %f140, 0f00000000;
|
|
setp.eq.f32 %p95, %f1007, 0f3F800000;
|
|
and.pred %p4, %p94, %p95;
|
|
setp.eq.f32 %p96, %f140, 0f00000000;
|
|
@%p96 bra $L__BB0_82;
|
|
bra.uni $L__BB0_79;
|
|
|
|
$L__BB0_82:
|
|
add.f32 %f700, %f140, %f140;
|
|
selp.f32 %f1062, %f700, 0f00000000, %p95;
|
|
bra.uni $L__BB0_83;
|
|
|
|
$L__BB0_79:
|
|
mov.b32 %r365, %f1060;
|
|
xor.b32 %r366, %r365, -2147483648;
|
|
mov.b32 %f696, %r366;
|
|
selp.f32 %f1062, %f696, %f1060, %p4;
|
|
setp.geu.f32 %p97, %f140, 0f00000000;
|
|
@%p97 bra $L__BB0_83;
|
|
|
|
mov.f32 %f697, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f698, %f697;
|
|
setp.eq.f32 %p98, %f698, 0f3ED55555;
|
|
@%p98 bra $L__BB0_83;
|
|
|
|
mov.f32 %f1062, 0f7FFFFFFF;
|
|
|
|
$L__BB0_83:
|
|
add.f32 %f701, %f144, 0f3ED55555;
|
|
mov.b32 %r367, %f701;
|
|
setp.lt.s32 %p100, %r367, 2139095040;
|
|
@%p100 bra $L__BB0_88;
|
|
|
|
setp.gtu.f32 %p101, %f144, 0f7F800000;
|
|
@%p101 bra $L__BB0_87;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_87:
|
|
add.f32 %f1062, %f140, 0f3ED55555;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_85:
|
|
setp.neu.f32 %p102, %f144, 0f7F800000;
|
|
@%p102 bra $L__BB0_88;
|
|
|
|
selp.f32 %f1062, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_88:
|
|
abs.f32 %f155, %f141;
|
|
setp.lt.f32 %p103, %f155, 0f00800000;
|
|
mul.f32 %f703, %f155, 0f4B800000;
|
|
selp.f32 %f704, %f703, %f155, %p103;
|
|
selp.f32 %f705, 0fC3170000, 0fC2FE0000, %p103;
|
|
mov.b32 %r368, %f704;
|
|
and.b32 %r369, %r368, 8388607;
|
|
or.b32 %r370, %r369, 1065353216;
|
|
mov.b32 %f706, %r370;
|
|
shr.u32 %r371, %r368, 23;
|
|
cvt.rn.f32.u32 %f707, %r371;
|
|
add.f32 %f708, %f705, %f707;
|
|
setp.gt.f32 %p104, %f706, 0f3FB504F3;
|
|
mul.f32 %f709, %f706, 0f3F000000;
|
|
add.f32 %f710, %f708, 0f3F800000;
|
|
selp.f32 %f711, %f710, %f708, %p104;
|
|
selp.f32 %f712, %f709, %f706, %p104;
|
|
add.f32 %f713, %f712, 0fBF800000;
|
|
add.f32 %f714, %f712, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f715, %f714;
|
|
add.f32 %f716, %f713, %f713;
|
|
mul.f32 %f717, %f716, %f715;
|
|
mul.f32 %f718, %f717, %f717;
|
|
mov.f32 %f719, 0f3C4CAF63;
|
|
mov.f32 %f720, 0f3B18F0FE;
|
|
fma.rn.f32 %f721, %f720, %f718, %f719;
|
|
mov.f32 %f722, 0f3DAAAABD;
|
|
fma.rn.f32 %f723, %f721, %f718, %f722;
|
|
mul.rn.f32 %f724, %f723, %f718;
|
|
mul.rn.f32 %f725, %f724, %f717;
|
|
sub.f32 %f726, %f713, %f717;
|
|
add.f32 %f727, %f726, %f726;
|
|
neg.f32 %f728, %f717;
|
|
fma.rn.f32 %f729, %f728, %f713, %f727;
|
|
mul.rn.f32 %f730, %f715, %f729;
|
|
add.f32 %f731, %f725, %f717;
|
|
sub.f32 %f732, %f717, %f731;
|
|
add.f32 %f733, %f725, %f732;
|
|
add.f32 %f734, %f730, %f733;
|
|
add.f32 %f735, %f731, %f734;
|
|
sub.f32 %f736, %f731, %f735;
|
|
add.f32 %f737, %f734, %f736;
|
|
mov.f32 %f738, 0f3F317200;
|
|
mul.rn.f32 %f739, %f711, %f738;
|
|
mov.f32 %f740, 0f35BFBE8E;
|
|
mul.rn.f32 %f741, %f711, %f740;
|
|
add.f32 %f742, %f739, %f735;
|
|
sub.f32 %f743, %f739, %f742;
|
|
add.f32 %f744, %f735, %f743;
|
|
add.f32 %f745, %f737, %f744;
|
|
add.f32 %f746, %f741, %f745;
|
|
add.f32 %f747, %f742, %f746;
|
|
sub.f32 %f748, %f742, %f747;
|
|
add.f32 %f749, %f746, %f748;
|
|
mov.f32 %f750, 0f3ED55555;
|
|
mul.rn.f32 %f751, %f750, %f747;
|
|
neg.f32 %f752, %f751;
|
|
fma.rn.f32 %f753, %f750, %f747, %f752;
|
|
fma.rn.f32 %f754, %f750, %f749, %f753;
|
|
mov.f32 %f755, 0f00000000;
|
|
fma.rn.f32 %f756, %f755, %f747, %f754;
|
|
add.rn.f32 %f757, %f751, %f756;
|
|
neg.f32 %f758, %f757;
|
|
add.rn.f32 %f759, %f751, %f758;
|
|
add.rn.f32 %f760, %f759, %f756;
|
|
mov.b32 %r372, %f757;
|
|
setp.eq.s32 %p105, %r372, 1118925336;
|
|
add.s32 %r373, %r372, -1;
|
|
mov.b32 %f761, %r373;
|
|
add.f32 %f762, %f760, 0f37000000;
|
|
selp.f32 %f156, %f762, %f760, %p105;
|
|
selp.f32 %f763, %f761, %f757, %p105;
|
|
mov.f32 %f764, 0f3FB8AA3B;
|
|
mul.rn.f32 %f765, %f763, %f764;
|
|
cvt.rzi.f32.f32 %f766, %f765;
|
|
abs.f32 %f767, %f766;
|
|
setp.gt.f32 %p106, %f767, 0f42FC0000;
|
|
mov.b32 %r374, %f766;
|
|
and.b32 %r375, %r374, -2147483648;
|
|
or.b32 %r376, %r375, 1123811328;
|
|
mov.b32 %f768, %r376;
|
|
selp.f32 %f769, %f768, %f766, %p106;
|
|
mov.f32 %f770, 0fBF317218;
|
|
fma.rn.f32 %f771, %f769, %f770, %f763;
|
|
mov.f32 %f772, 0f3102E308;
|
|
fma.rn.f32 %f773, %f769, %f772, %f771;
|
|
mul.f32 %f774, %f773, 0f3FB8AA3B;
|
|
add.f32 %f775, %f769, 0f4B40007F;
|
|
mov.b32 %r377, %f775;
|
|
shl.b32 %r378, %r377, 23;
|
|
mov.b32 %f776, %r378;
|
|
ex2.approx.ftz.f32 %f777, %f774;
|
|
mul.f32 %f157, %f777, %f776;
|
|
setp.eq.f32 %p107, %f157, 0f7F800000;
|
|
mov.f32 %f1063, 0f7F800000;
|
|
@%p107 bra $L__BB0_90;
|
|
|
|
fma.rn.f32 %f1063, %f157, %f156, %f157;
|
|
|
|
$L__BB0_90:
|
|
setp.lt.f32 %p108, %f141, 0f00000000;
|
|
and.pred %p5, %p108, %p95;
|
|
setp.eq.f32 %p110, %f141, 0f00000000;
|
|
@%p110 bra $L__BB0_94;
|
|
bra.uni $L__BB0_91;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f782, %f141, %f141;
|
|
selp.f32 %f1065, %f782, 0f00000000, %p95;
|
|
bra.uni $L__BB0_95;
|
|
|
|
$L__BB0_91:
|
|
mov.b32 %r379, %f1063;
|
|
xor.b32 %r380, %r379, -2147483648;
|
|
mov.b32 %f778, %r380;
|
|
selp.f32 %f1065, %f778, %f1063, %p5;
|
|
setp.geu.f32 %p111, %f141, 0f00000000;
|
|
@%p111 bra $L__BB0_95;
|
|
|
|
mov.f32 %f779, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f780, %f779;
|
|
setp.eq.f32 %p112, %f780, 0f3ED55555;
|
|
@%p112 bra $L__BB0_95;
|
|
|
|
mov.f32 %f1065, 0f7FFFFFFF;
|
|
|
|
$L__BB0_95:
|
|
add.f32 %f783, %f155, 0f3ED55555;
|
|
mov.b32 %r381, %f783;
|
|
setp.lt.s32 %p114, %r381, 2139095040;
|
|
@%p114 bra $L__BB0_100;
|
|
|
|
setp.gtu.f32 %p115, %f155, 0f7F800000;
|
|
@%p115 bra $L__BB0_99;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f1065, %f141, 0f3ED55555;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_97:
|
|
setp.neu.f32 %p116, %f155, 0f7F800000;
|
|
@%p116 bra $L__BB0_100;
|
|
|
|
selp.f32 %f1065, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_100:
|
|
abs.f32 %f166, %f142;
|
|
setp.lt.f32 %p117, %f166, 0f00800000;
|
|
mul.f32 %f785, %f166, 0f4B800000;
|
|
selp.f32 %f786, %f785, %f166, %p117;
|
|
selp.f32 %f787, 0fC3170000, 0fC2FE0000, %p117;
|
|
mov.b32 %r382, %f786;
|
|
and.b32 %r383, %r382, 8388607;
|
|
or.b32 %r384, %r383, 1065353216;
|
|
mov.b32 %f788, %r384;
|
|
shr.u32 %r385, %r382, 23;
|
|
cvt.rn.f32.u32 %f789, %r385;
|
|
add.f32 %f790, %f787, %f789;
|
|
setp.gt.f32 %p118, %f788, 0f3FB504F3;
|
|
mul.f32 %f791, %f788, 0f3F000000;
|
|
add.f32 %f792, %f790, 0f3F800000;
|
|
selp.f32 %f793, %f792, %f790, %p118;
|
|
selp.f32 %f794, %f791, %f788, %p118;
|
|
add.f32 %f795, %f794, 0fBF800000;
|
|
add.f32 %f796, %f794, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f797, %f796;
|
|
add.f32 %f798, %f795, %f795;
|
|
mul.f32 %f799, %f798, %f797;
|
|
mul.f32 %f800, %f799, %f799;
|
|
mov.f32 %f801, 0f3C4CAF63;
|
|
mov.f32 %f802, 0f3B18F0FE;
|
|
fma.rn.f32 %f803, %f802, %f800, %f801;
|
|
mov.f32 %f804, 0f3DAAAABD;
|
|
fma.rn.f32 %f805, %f803, %f800, %f804;
|
|
mul.rn.f32 %f806, %f805, %f800;
|
|
mul.rn.f32 %f807, %f806, %f799;
|
|
sub.f32 %f808, %f795, %f799;
|
|
add.f32 %f809, %f808, %f808;
|
|
neg.f32 %f810, %f799;
|
|
fma.rn.f32 %f811, %f810, %f795, %f809;
|
|
mul.rn.f32 %f812, %f797, %f811;
|
|
add.f32 %f813, %f807, %f799;
|
|
sub.f32 %f814, %f799, %f813;
|
|
add.f32 %f815, %f807, %f814;
|
|
add.f32 %f816, %f812, %f815;
|
|
add.f32 %f817, %f813, %f816;
|
|
sub.f32 %f818, %f813, %f817;
|
|
add.f32 %f819, %f816, %f818;
|
|
mov.f32 %f820, 0f3F317200;
|
|
mul.rn.f32 %f821, %f793, %f820;
|
|
mov.f32 %f822, 0f35BFBE8E;
|
|
mul.rn.f32 %f823, %f793, %f822;
|
|
add.f32 %f824, %f821, %f817;
|
|
sub.f32 %f825, %f821, %f824;
|
|
add.f32 %f826, %f817, %f825;
|
|
add.f32 %f827, %f819, %f826;
|
|
add.f32 %f828, %f823, %f827;
|
|
add.f32 %f829, %f824, %f828;
|
|
sub.f32 %f830, %f824, %f829;
|
|
add.f32 %f831, %f828, %f830;
|
|
mov.f32 %f832, 0f3ED55555;
|
|
mul.rn.f32 %f833, %f832, %f829;
|
|
neg.f32 %f834, %f833;
|
|
fma.rn.f32 %f835, %f832, %f829, %f834;
|
|
fma.rn.f32 %f836, %f832, %f831, %f835;
|
|
mov.f32 %f837, 0f00000000;
|
|
fma.rn.f32 %f838, %f837, %f829, %f836;
|
|
add.rn.f32 %f839, %f833, %f838;
|
|
neg.f32 %f840, %f839;
|
|
add.rn.f32 %f841, %f833, %f840;
|
|
add.rn.f32 %f842, %f841, %f838;
|
|
mov.b32 %r386, %f839;
|
|
setp.eq.s32 %p119, %r386, 1118925336;
|
|
add.s32 %r387, %r386, -1;
|
|
mov.b32 %f843, %r387;
|
|
add.f32 %f844, %f842, 0f37000000;
|
|
selp.f32 %f167, %f844, %f842, %p119;
|
|
selp.f32 %f845, %f843, %f839, %p119;
|
|
mov.f32 %f846, 0f3FB8AA3B;
|
|
mul.rn.f32 %f847, %f845, %f846;
|
|
cvt.rzi.f32.f32 %f848, %f847;
|
|
abs.f32 %f849, %f848;
|
|
setp.gt.f32 %p120, %f849, 0f42FC0000;
|
|
mov.b32 %r388, %f848;
|
|
and.b32 %r389, %r388, -2147483648;
|
|
or.b32 %r390, %r389, 1123811328;
|
|
mov.b32 %f850, %r390;
|
|
selp.f32 %f851, %f850, %f848, %p120;
|
|
mov.f32 %f852, 0fBF317218;
|
|
fma.rn.f32 %f853, %f851, %f852, %f845;
|
|
mov.f32 %f854, 0f3102E308;
|
|
fma.rn.f32 %f855, %f851, %f854, %f853;
|
|
mul.f32 %f856, %f855, 0f3FB8AA3B;
|
|
add.f32 %f857, %f851, 0f4B40007F;
|
|
mov.b32 %r391, %f857;
|
|
shl.b32 %r392, %r391, 23;
|
|
mov.b32 %f858, %r392;
|
|
ex2.approx.ftz.f32 %f859, %f856;
|
|
mul.f32 %f168, %f859, %f858;
|
|
setp.eq.f32 %p121, %f168, 0f7F800000;
|
|
mov.f32 %f1066, 0f7F800000;
|
|
@%p121 bra $L__BB0_102;
|
|
|
|
fma.rn.f32 %f1066, %f168, %f167, %f168;
|
|
|
|
$L__BB0_102:
|
|
setp.lt.f32 %p122, %f142, 0f00000000;
|
|
and.pred %p6, %p122, %p95;
|
|
setp.eq.f32 %p124, %f142, 0f00000000;
|
|
@%p124 bra $L__BB0_106;
|
|
bra.uni $L__BB0_103;
|
|
|
|
$L__BB0_106:
|
|
add.f32 %f864, %f142, %f142;
|
|
selp.f32 %f1068, %f864, 0f00000000, %p95;
|
|
bra.uni $L__BB0_107;
|
|
|
|
$L__BB0_103:
|
|
mov.b32 %r393, %f1066;
|
|
xor.b32 %r394, %r393, -2147483648;
|
|
mov.b32 %f860, %r394;
|
|
selp.f32 %f1068, %f860, %f1066, %p6;
|
|
setp.geu.f32 %p125, %f142, 0f00000000;
|
|
@%p125 bra $L__BB0_107;
|
|
|
|
mov.f32 %f861, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f862, %f861;
|
|
setp.eq.f32 %p126, %f862, 0f3ED55555;
|
|
@%p126 bra $L__BB0_107;
|
|
|
|
mov.f32 %f1068, 0f7FFFFFFF;
|
|
|
|
$L__BB0_107:
|
|
add.f32 %f865, %f166, 0f3ED55555;
|
|
mov.b32 %r395, %f865;
|
|
setp.lt.s32 %p128, %r395, 2139095040;
|
|
@%p128 bra $L__BB0_112;
|
|
|
|
setp.gtu.f32 %p129, %f166, 0f7F800000;
|
|
@%p129 bra $L__BB0_111;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f1068, %f142, 0f3ED55555;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_109:
|
|
setp.neu.f32 %p130, %f166, 0f7F800000;
|
|
@%p130 bra $L__BB0_112;
|
|
|
|
selp.f32 %f1068, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_112:
|
|
ld.const.u64 %rd107, [params+144];
|
|
cvta.to.global.u64 %rd106, %rd107;
|
|
fma.rn.f32 %f866, %f1062, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p131, %f140, 0f3F800000;
|
|
mov.f32 %f867, 0f3F800000;
|
|
selp.f32 %f868, 0f3F7FFFFF, %f866, %p131;
|
|
mul.f32 %f869, %f140, 0f414EB852;
|
|
setp.lt.f32 %p132, %f140, 0f3B4D2E1C;
|
|
selp.f32 %f870, %f869, %f868, %p132;
|
|
fma.rn.f32 %f871, %f1065, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p133, %f141, 0f3F800000;
|
|
selp.f32 %f872, 0f3F7FFFFF, %f871, %p133;
|
|
mul.f32 %f873, %f141, 0f414EB852;
|
|
setp.lt.f32 %p134, %f141, 0f3B4D2E1C;
|
|
selp.f32 %f874, %f873, %f872, %p134;
|
|
fma.rn.f32 %f875, %f1068, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p135, %f142, 0f3F800000;
|
|
selp.f32 %f876, 0f3F7FFFFF, %f875, %p135;
|
|
mul.f32 %f877, %f142, 0f414EB852;
|
|
setp.lt.f32 %p136, %f142, 0f3B4D2E1C;
|
|
selp.f32 %f878, %f877, %f876, %p136;
|
|
min.f32 %f879, %f870, %f867;
|
|
mov.f32 %f880, 0f00000000;
|
|
max.f32 %f881, %f880, %f879;
|
|
mul.f32 %f882, %f881, 0f43800000;
|
|
cvt.rzi.u32.f32 %r396, %f882;
|
|
min.u32 %r397, %r396, 255;
|
|
min.f32 %f883, %f874, %f867;
|
|
max.f32 %f884, %f880, %f883;
|
|
mul.f32 %f885, %f884, 0f43800000;
|
|
cvt.rzi.u32.f32 %r398, %f885;
|
|
min.u32 %r399, %r398, 255;
|
|
min.f32 %f886, %f878, %f867;
|
|
max.f32 %f887, %f880, %f886;
|
|
mul.f32 %f888, %f887, 0f43800000;
|
|
cvt.rzi.u32.f32 %r400, %f888;
|
|
min.u32 %r401, %r400, 255;
|
|
shl.b64 %rd64, %rd16, 2;
|
|
add.s64 %rd65, %rd106, %rd64;
|
|
cvt.u16.u32 %rs15, %r401;
|
|
cvt.u16.u32 %rs16, %r399;
|
|
cvt.u16.u32 %rs17, %r397;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd65], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_113:
|
|
ld.const.u32 %r430, [params+104];
|
|
and.b32 %r402, %r430, 4;
|
|
setp.eq.s32 %p137, %r402, 0;
|
|
mul.f32 %f177, %f1044, %f100;
|
|
mul.f32 %f178, %f1043, %f100;
|
|
mul.f32 %f179, %f1042, %f100;
|
|
@%p137 bra $L__BB0_117;
|
|
|
|
ld.const.u32 %r403, [params+1128];
|
|
setp.eq.s32 %p138, %r403, 0;
|
|
mov.f32 %f1069, 0f00000000;
|
|
mov.f32 %f1070, %f1069;
|
|
mov.f32 %f1071, %f1069;
|
|
@%p138 bra $L__BB0_116;
|
|
|
|
ld.const.u64 %rd66, [params+496];
|
|
cvta.to.global.u64 %rd67, %rd66;
|
|
ld.const.u32 %r404, [params+488];
|
|
mad.lo.s32 %r405, %r404, %r85, %r84;
|
|
mul.wide.u32 %rd68, %r405, 8;
|
|
add.s64 %rd69, %rd67, %rd68;
|
|
ld.global.v4.u16 {%rs22, %rs23, %rs24, %rs25}, [%rd69];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1071, %rs22;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1070, %rs23;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1069, %rs24;}
|
|
|
|
// end inline asm
|
|
|
|
$L__BB0_116:
|
|
ld.const.u64 %rd70, [params+224];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r406, [params+216];
|
|
mad.lo.s32 %r407, %r406, %r4, %r3;
|
|
add.f32 %f895, %f101, %f1071;
|
|
add.f32 %f896, %f102, %f1070;
|
|
add.f32 %f897, %f103, %f1069;
|
|
mov.f32 %f898, 0f3F800000;
|
|
mul.wide.u32 %rd72, %r407, 8;
|
|
add.s64 %rd73, %rd71, %rd72;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f897;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f896;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f895;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f898;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd73], {%rs26, %rs27, %rs28, %rs29};
|
|
|
|
$L__BB0_117:
|
|
mul.f32 %f186, %f179, 0f3F000000;
|
|
mul.f32 %f187, %f178, 0f3F000000;
|
|
mul.f32 %f188, %f177, 0f3F000000;
|
|
ld.const.u32 %r81, [params+108];
|
|
setp.eq.s32 %p139, %r81, 0;
|
|
ld.const.u64 %rd74, [params+256];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r408, [params+248];
|
|
mad.lo.s32 %r409, %r408, %r4, %r3;
|
|
mul.wide.u32 %rd76, %r409, 8;
|
|
add.s64 %rd17, %rd75, %rd76;
|
|
@%p139 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs37, %rs38, %rs39, %rs40}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f899, %rs37;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f900, %rs38;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f901, %rs39;}
|
|
|
|
// end inline asm
|
|
add.f32 %f902, %f186, %f899;
|
|
add.f32 %f903, %f187, %f900;
|
|
add.f32 %f904, %f188, %f901;
|
|
mov.f32 %f905, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f904;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f903;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f902;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f905;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs33, %rs34, %rs35, %rs36};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f909, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f909;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f188;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f187;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f186;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs41, %rs42, %rs43, %rs44};
|
|
|
|
$L__BB0_120:
|
|
mul.f32 %f910, %f100, 0f00000000;
|
|
mul.f32 %f911, %f910, 0f3F000000;
|
|
mov.f32 %f912, 0f34000000;
|
|
max.f32 %f913, %f186, %f912;
|
|
div.rn.f32 %f914, %f911, %f913;
|
|
max.f32 %f915, %f187, %f912;
|
|
div.rn.f32 %f916, %f911, %f915;
|
|
max.f32 %f917, %f188, %f912;
|
|
div.rn.f32 %f918, %f911, %f917;
|
|
fma.rn.f32 %f189, %f914, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f190, %f916, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f191, %f918, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd77, [params+272];
|
|
cvta.to.global.u64 %rd78, %rd77;
|
|
ld.const.u32 %r410, [params+264];
|
|
mad.lo.s32 %r411, %r410, %r4, %r3;
|
|
mul.wide.u32 %rd79, %r411, 8;
|
|
add.s64 %rd18, %rd78, %rd79;
|
|
@%p139 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs52, %rs53, %rs54, %rs55}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f919, %rs52;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f920, %rs53;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f921, %rs54;}
|
|
|
|
// end inline asm
|
|
add.f32 %f922, %f189, %f919;
|
|
add.f32 %f923, %f190, %f920;
|
|
add.f32 %f924, %f191, %f921;
|
|
mov.f32 %f925, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f924;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f923;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f922;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f925;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs48, %rs49, %rs50, %rs51};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f929, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f929;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f190;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f189;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs56, %rs57, %rs58, %rs59};
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd80, [params+288];
|
|
cvta.to.global.u64 %rd81, %rd80;
|
|
ld.const.u32 %r412, [params+280];
|
|
mad.lo.s32 %r413, %r412, %r4, %r3;
|
|
mul.wide.u32 %rd82, %r413, 8;
|
|
add.s64 %rd19, %rd81, %rd82;
|
|
@%p139 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs67, %rs68, %rs69, %rs70}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f930, %rs67;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f931, %rs68;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f932, %rs69;}
|
|
|
|
// end inline asm
|
|
add.f32 %f933, %f189, %f930;
|
|
add.f32 %f934, %f190, %f931;
|
|
add.f32 %f935, %f191, %f932;
|
|
mov.f32 %f936, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f935;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f934;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f933;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f936;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs63, %rs64, %rs65, %rs66};
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f940, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f940;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f190;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f189;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs71, %rs72, %rs73, %rs74};
|
|
|
|
$L__BB0_126:
|
|
ld.const.u64 %rd83, [params+304];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r414, [params+296];
|
|
mad.lo.s32 %r415, %r414, %r4, %r3;
|
|
mul.wide.u32 %rd85, %r415, 8;
|
|
add.s64 %rd20, %rd84, %rd85;
|
|
@%p139 bra $L__BB0_128;
|
|
|
|
ld.global.v4.u16 {%rs82, %rs83, %rs84, %rs85}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f941, %rs82;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f942, %rs83;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f943, %rs84;}
|
|
|
|
// end inline asm
|
|
add.f32 %f944, %f189, %f941;
|
|
add.f32 %f945, %f190, %f942;
|
|
add.f32 %f946, %f191, %f943;
|
|
mov.f32 %f947, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f946;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f945;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f944;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f947;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs78, %rs79, %rs80, %rs81};
|
|
bra.uni $L__BB0_145;
|
|
|
|
$L__BB0_128:
|
|
mov.f32 %f951, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f951;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f190;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f189;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs86, %rs87, %rs88, %rs89};
|
|
|
|
$L__BB0_145:
|
|
ret;
|
|
|
|
}
|
|
|