2395 lines
64 KiB
Plaintext
2395 lines
64 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<171>;
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.reg .b16 %rs<178>;
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.reg .f32 %f<1154>;
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.reg .b32 %r<369>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<121>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r54), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r55), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd31, [params+400];
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cvta.to.global.u64 %rd32, %rd31;
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ld.const.u32 %r60, [params+392];
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mad.lo.s32 %r61, %r60, %r55, %r54;
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mul.wide.u32 %rd33, %r61, 4;
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add.s64 %rd2, %rd32, %rd33;
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ld.global.v2.u8 {%rs7, %rs177}, [%rd2];
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or.b16 %rs9, %rs7, %rs177;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p8, %rs10, 0;
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@%p8 bra $L__BB0_2;
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ld.global.u8 %rs176, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs176, [%rd2+2];
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setp.eq.s16 %p9, %rs176, 0;
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mov.f32 %f1112, 0f00000000;
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mov.u16 %rs177, 0;
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mov.f32 %f1113, %f1112;
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mov.f32 %f1114, %f1112;
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@%p9 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f170, %rs7;
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div.rn.f32 %f171, %f170, 0f437F0000;
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fma.rn.f32 %f172, %f171, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs177, 255;
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cvt.rn.f32.u16 %f173, %rs13;
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div.rn.f32 %f174, %f173, 0f437F0000;
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fma.rn.f32 %f175, %f174, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f176, %rs176;
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div.rn.f32 %f177, %f176, 0f437F0000;
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fma.rn.f32 %f178, %f177, 0f40000000, 0fBF800000;
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mul.f32 %f179, %f175, %f175;
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fma.rn.f32 %f180, %f172, %f172, %f179;
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fma.rn.f32 %f181, %f178, %f178, %f180;
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sqrt.rn.f32 %f182, %f181;
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rcp.rn.f32 %f183, %f182;
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mul.f32 %f1114, %f183, %f178;
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mul.f32 %f1113, %f183, %f175;
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mul.f32 %f1112, %f172, %f183;
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$L__BB0_4:
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ld.const.v2.u32 {%r62, %r63}, [params];
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add.s32 %r3, %r62, %r54;
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add.s32 %r4, %r63, %r55;
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setp.eq.f32 %p10, %f1112, 0f00000000;
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setp.eq.f32 %p11, %f1113, 0f00000000;
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and.pred %p12, %p10, %p11;
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setp.eq.f32 %p13, %f1114, 0f00000000;
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and.pred %p14, %p13, %p12;
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@%p14 bra $L__BB0_140;
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bra.uni $L__BB0_5;
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$L__BB0_140:
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ld.const.u32 %r51, [params+104];
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and.b32 %r331, %r51, 1;
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setp.eq.b32 %p160, %r331, 1;
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mov.pred %p161, 0;
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xor.pred %p162, %p160, %p161;
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not.pred %p163, %p162;
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@%p163 bra $L__BB0_142;
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ld.const.u64 %rd87, [params+144];
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cvta.to.global.u64 %rd88, %rd87;
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ld.const.u32 %r332, [params+136];
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mad.lo.s32 %r333, %r332, %r4, %r3;
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mul.wide.u32 %rd89, %r333, 4;
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add.s64 %rd90, %rd88, %rd89;
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mov.u16 %rs98, 0;
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st.global.v4.u8 [%rd90], {%rs98, %rs98, %rs98, %rs98};
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$L__BB0_142:
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and.b32 %r334, %r51, 8;
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setp.eq.s32 %p164, %r334, 0;
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@%p164 bra $L__BB0_144;
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ld.const.u64 %rd91, [params+192];
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cvta.to.global.u64 %rd92, %rd91;
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ld.const.u32 %r335, [params+184];
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mad.lo.s32 %r336, %r335, %r4, %r3;
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mov.f32 %f1017, 0f00000000;
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cvt.rzi.u32.f32 %r337, %f1017;
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mul.wide.u32 %rd93, %r336, 2;
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add.s64 %rd94, %rd92, %rd93;
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mov.u16 %rs99, 0;
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cvt.u16.u32 %rs100, %r337;
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st.global.v2.u8 [%rd94], {%rs100, %rs99};
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$L__BB0_144:
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and.b32 %r338, %r51, 4;
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setp.eq.s32 %p165, %r338, 0;
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ld.const.u32 %r368, [params+108];
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@%p165 bra $L__BB0_148;
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setp.eq.s32 %p166, %r368, 0;
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ld.const.u64 %rd95, [params+224];
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cvta.to.global.u64 %rd96, %rd95;
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ld.const.u32 %r339, [params+216];
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mad.lo.s32 %r340, %r339, %r4, %r3;
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mul.wide.u32 %rd97, %r340, 8;
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add.s64 %rd25, %rd96, %rd97;
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@%p166 bra $L__BB0_147;
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ld.global.v4.u16 {%rs107, %rs108, %rs109, %rs110}, [%rd25];
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// begin inline asm
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{ cvt.f32.f16 %f1018, %rs107;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1019, %rs108;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1020, %rs109;}
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// end inline asm
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add.f32 %f1021, %f1018, 0f00000000;
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add.f32 %f1022, %f1019, 0f00000000;
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add.f32 %f1023, %f1020, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs106, %f1023;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs105, %f1022;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs104, %f1021;}
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// end inline asm
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mov.u16 %rs111, 0;
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st.global.v4.u16 [%rd25], {%rs104, %rs105, %rs106, %rs111};
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bra.uni $L__BB0_148;
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$L__BB0_5:
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ld.const.v4.f32 {%f187, %f188, %f189, %f190}, [params+512];
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neg.f32 %f191, %f188;
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neg.f32 %f192, %f189;
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mul.f32 %f193, %f1112, %f187;
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mul.f32 %f194, %f1113, %f191;
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sub.f32 %f195, %f194, %f193;
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mul.f32 %f196, %f1114, %f189;
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sub.f32 %f13, %f195, %f196;
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ld.const.u64 %rd34, [params+432];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r66, [params+424];
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mad.lo.s32 %r67, %r66, %r55, %r54;
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mul.wide.u32 %rd36, %r67, 12;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.f32 %f197, [%rd37];
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mul.f32 %f198, %f197, 0f3456BF95;
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ld.global.f32 %f199, [%rd37+4];
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mul.f32 %f200, %f199, 0f3456BF95;
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ld.global.f32 %f201, [%rd37+8];
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mul.f32 %f202, %f201, 0f3456BF95;
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abs.f32 %f203, %f1112;
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div.rn.f32 %f204, %f198, %f203;
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abs.f32 %f205, %f1113;
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div.rn.f32 %f206, %f200, %f205;
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abs.f32 %f207, %f1114;
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div.rn.f32 %f208, %f202, %f207;
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abs.f32 %f209, %f204;
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abs.f32 %f210, %f206;
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abs.f32 %f211, %f208;
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mov.f32 %f212, 0f38D1B717;
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max.f32 %f213, %f209, %f212;
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max.f32 %f214, %f210, %f212;
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max.f32 %f215, %f211, %f212;
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fma.rn.f32 %f14, %f1112, %f213, %f197;
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fma.rn.f32 %f15, %f1113, %f214, %f199;
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fma.rn.f32 %f16, %f1114, %f215, %f201;
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abs.f32 %f216, %f187;
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abs.f32 %f217, %f189;
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setp.gt.f32 %p15, %f216, %f217;
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selp.f32 %f218, %f191, 0f00000000, %p15;
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mov.f32 %f1120, 0f00000000;
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selp.f32 %f219, %f187, %f192, %p15;
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selp.f32 %f220, 0f00000000, %f188, %p15;
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mul.f32 %f221, %f219, %f219;
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fma.rn.f32 %f222, %f218, %f218, %f221;
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fma.rn.f32 %f223, %f220, %f220, %f222;
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sqrt.rn.f32 %f224, %f223;
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rcp.rn.f32 %f225, %f224;
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mul.f32 %f17, %f218, %f225;
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mul.f32 %f18, %f219, %f225;
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mul.f32 %f19, %f220, %f225;
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ld.const.u64 %rd38, [params+128];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r68, [params+120];
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mad.lo.s32 %r69, %r68, %r55, %r54;
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mul.wide.u32 %rd40, %r69, 4;
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add.s64 %rd3, %rd39, %rd40;
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ld.const.u32 %r5, [params+540];
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setp.lt.s32 %p16, %r5, 1;
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mov.f32 %f1119, %f1120;
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mov.f32 %f1118, %f1120;
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@%p16 bra $L__BB0_34;
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cvt.rn.f32.s32 %f229, %r5;
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rcp.rn.f32 %f20, %f229;
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ld.global.u32 %r359, [%rd3];
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ld.const.f32 %f21, [params+536];
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ld.const.u8 %rs15, [params+104];
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and.b16 %rs16, %rs15, 32;
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setp.eq.s16 %p17, %rs16, 0;
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mov.u32 %r70, 0;
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selp.f32 %f22, 0f3F800000, 0f41200000, %p17;
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mul.f32 %f23, %f14, 0f3456BF95;
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mul.f32 %f24, %f15, 0f3456BF95;
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mul.f32 %f25, %f16, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f230, %f187, %f18;
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mul.f32 %f231, %f188, %f17;
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sub.f32 %f26, %f231, %f230;
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mul.f32 %f232, %f189, %f17;
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mul.f32 %f233, %f187, %f19;
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sub.f32 %f27, %f233, %f232;
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mul.f32 %f234, %f188, %f19;
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mul.f32 %f235, %f189, %f18;
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sub.f32 %f28, %f235, %f234;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd41, __cudart_i2opi_f;
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abs.f32 %f318, %f24;
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abs.f32 %f319, %f23;
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max.f32 %f320, %f319, %f318;
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abs.f32 %f321, %f25;
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max.f32 %f322, %f320, %f321;
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mov.u32 %r356, %r70;
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$L__BB0_7:
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mov.u32 %r358, %r70;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1069, %r356;
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mad.lo.s32 %r72, %r359, 1664525, 1013904223;
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and.b32 %r73, %r72, 16777215;
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cvt.rn.f32.u32 %f236, %r73;
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fma.rn.f32 %f237, %f236, 0f33800000, %f1069;
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mul.f32 %f238, %f20, %f237;
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mad.lo.s32 %r359, %r72, 1664525, 1013904223;
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and.b32 %r74, %r359, 16777215;
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cvt.rn.f32.u32 %f239, %r74;
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cvt.rn.f32.s32 %f240, %r358;
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fma.rn.f32 %f241, %f239, 0f33800000, %f240;
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mul.f32 %f242, %f20, %f241;
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sqrt.rn.f32 %f36, %f238;
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mul.f32 %f37, %f242, 0f40C90FDB;
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mul.f32 %f243, %f37, 0f3F22F983;
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cvt.rni.s32.f32 %r366, %f243;
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cvt.rn.f32.s32 %f244, %r366;
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mov.f32 %f245, 0fBFC90FDA;
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fma.rn.f32 %f246, %f244, %f245, %f37;
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mov.f32 %f247, 0fB3A22168;
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fma.rn.f32 %f248, %f244, %f247, %f246;
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mov.f32 %f249, 0fA7C234C5;
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fma.rn.f32 %f1124, %f244, %f249, %f248;
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abs.f32 %f39, %f37;
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setp.ltu.f32 %p18, %f39, 0f47CE4780;
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mov.u32 %r363, %r366;
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mov.f32 %f1121, %f1124;
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@%p18 bra $L__BB0_16;
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setp.eq.f32 %p19, %f39, 0f7F800000;
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@%p19 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f252, 0f00000000;
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mul.rn.f32 %f1121, %f37, %f252;
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mov.u32 %r363, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r13, %f37;
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bfe.u32 %r76, %r13, 23, 8;
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add.s32 %r14, %r76, -128;
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shl.b32 %r77, %r13, 8;
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or.b32 %r15, %r77, -2147483648;
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shr.u32 %r16, %r14, 5;
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mov.u64 %rd118, 0;
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mov.u32 %r360, 0;
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mov.u64 %rd116, %rd1;
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mov.u64 %rd117, %rd41;
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$L__BB0_11:
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.pragma "nounroll";
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ld.global.nc.u32 %r78, [%rd117];
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mad.wide.u32 %rd43, %r78, %r15, %rd118;
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shr.u64 %rd118, %rd43, 32;
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st.local.u32 [%rd116], %rd43;
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add.s64 %rd117, %rd117, 4;
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add.s64 %rd116, %rd116, 4;
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add.s32 %r360, %r360, 1;
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setp.ne.s32 %p20, %r360, 6;
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@%p20 bra $L__BB0_11;
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st.local.u32 [%rd5], %rd118;
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mov.u32 %r79, 4;
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sub.s32 %r19, %r79, %r16;
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mov.u32 %r80, 6;
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sub.s32 %r81, %r80, %r16;
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mul.wide.s32 %rd44, %r81, 4;
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add.s64 %rd45, %rd1, %rd44;
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ld.local.u32 %r361, [%rd45];
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ld.local.u32 %r362, [%rd45+-4];
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and.b32 %r22, %r14, 31;
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setp.eq.s32 %p21, %r22, 0;
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@%p21 bra $L__BB0_14;
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mov.u32 %r82, 32;
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sub.s32 %r83, %r82, %r22;
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shr.u32 %r84, %r362, %r83;
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shl.b32 %r85, %r361, %r22;
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add.s32 %r361, %r84, %r85;
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mul.wide.s32 %rd46, %r19, 4;
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add.s64 %rd47, %rd1, %rd46;
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ld.local.u32 %r86, [%rd47];
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shr.u32 %r87, %r86, %r83;
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shl.b32 %r88, %r362, %r22;
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add.s32 %r362, %r87, %r88;
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$L__BB0_14:
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and.b32 %r89, %r13, -2147483648;
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shr.u32 %r90, %r362, 30;
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shl.b32 %r91, %r361, 2;
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or.b32 %r92, %r90, %r91;
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shr.u32 %r93, %r92, 31;
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shr.u32 %r94, %r361, 30;
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add.s32 %r95, %r93, %r94;
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neg.s32 %r96, %r95;
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setp.eq.s32 %p22, %r89, 0;
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selp.b32 %r363, %r95, %r96, %p22;
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setp.ne.s32 %p23, %r93, 0;
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xor.b32 %r97, %r89, -2147483648;
|
|
selp.b32 %r98, %r97, %r89, %p23;
|
|
selp.b32 %r99, -1, 0, %p23;
|
|
xor.b32 %r100, %r92, %r99;
|
|
shl.b32 %r101, %r362, 2;
|
|
xor.b32 %r102, %r101, %r99;
|
|
cvt.u64.u32 %rd48, %r100;
|
|
cvt.u64.u32 %rd49, %r102;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f250, %fd2;
|
|
setp.eq.s32 %p24, %r98, 0;
|
|
neg.f32 %f251, %f250;
|
|
selp.f32 %f1121, %f250, %f251, %p24;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r29, %r363, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p25, %r30, 0;
|
|
selp.f32 %f43, %f1121, 0f3F800000, %p25;
|
|
mul.rn.f32 %f44, %f1121, %f1121;
|
|
mov.f32 %f1122, 0fB94D4153;
|
|
@%p25 bra $L__BB0_18;
|
|
|
|
mov.f32 %f254, 0fBAB607ED;
|
|
mov.f32 %f255, 0f37CBAC00;
|
|
fma.rn.f32 %f1122, %f255, %f44, %f254;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f256, 0f3C0885E4, 0f3D2AAABB, %p25;
|
|
fma.rn.f32 %f257, %f1122, %f44, %f256;
|
|
selp.f32 %f258, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
|
|
fma.rn.f32 %f259, %f257, %f44, %f258;
|
|
mov.f32 %f260, 0f00000000;
|
|
fma.rn.f32 %f261, %f44, %f43, %f260;
|
|
fma.rn.f32 %f1123, %f259, %f261, %f43;
|
|
and.b32 %r104, %r29, 2;
|
|
setp.eq.s32 %p27, %r104, 0;
|
|
@%p27 bra $L__BB0_20;
|
|
|
|
mov.f32 %f263, 0fBF800000;
|
|
fma.rn.f32 %f1123, %f1123, %f263, %f260;
|
|
|
|
$L__BB0_20:
|
|
@%p18 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p29, %f39, 0f7F800000;
|
|
@%p29 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f266, 0f00000000;
|
|
mul.rn.f32 %f1124, %f37, %f266;
|
|
mov.u32 %r366, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r31, %f37;
|
|
bfe.u32 %r105, %r31, 23, 8;
|
|
add.s32 %r32, %r105, -128;
|
|
shl.b32 %r106, %r31, 8;
|
|
or.b32 %r33, %r106, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd119, 0;
|
|
mov.u64 %rd120, %rd119;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd119, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r107, [%rd55];
|
|
mad.wide.u32 %rd56, %r107, %r33, %rd120;
|
|
shr.u64 %rd120, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r108, %rd119;
|
|
add.s32 %r109, %r108, 1;
|
|
cvt.s64.s32 %rd119, %r109;
|
|
setp.ne.s32 %p30, %r109, 6;
|
|
@%p30 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd120;
|
|
mov.u32 %r110, 4;
|
|
sub.s32 %r35, %r110, %r34;
|
|
mov.u32 %r111, 6;
|
|
sub.s32 %r112, %r111, %r34;
|
|
mul.wide.s32 %rd58, %r112, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r364, [%rd59];
|
|
ld.local.u32 %r365, [%rd59+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p31, %r38, 0;
|
|
@%p31 bra $L__BB0_26;
|
|
|
|
mov.u32 %r113, 32;
|
|
sub.s32 %r114, %r113, %r38;
|
|
shr.u32 %r115, %r365, %r114;
|
|
shl.b32 %r116, %r364, %r38;
|
|
add.s32 %r364, %r115, %r116;
|
|
mul.wide.s32 %rd60, %r35, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r117, [%rd61];
|
|
shr.u32 %r118, %r117, %r114;
|
|
shl.b32 %r119, %r365, %r38;
|
|
add.s32 %r365, %r118, %r119;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r120, %r31, -2147483648;
|
|
shr.u32 %r121, %r365, 30;
|
|
shl.b32 %r122, %r364, 2;
|
|
or.b32 %r123, %r121, %r122;
|
|
shr.u32 %r124, %r123, 31;
|
|
shr.u32 %r125, %r364, 30;
|
|
add.s32 %r126, %r124, %r125;
|
|
neg.s32 %r127, %r126;
|
|
setp.eq.s32 %p32, %r120, 0;
|
|
selp.b32 %r366, %r126, %r127, %p32;
|
|
setp.ne.s32 %p33, %r124, 0;
|
|
xor.b32 %r128, %r120, -2147483648;
|
|
selp.b32 %r129, %r128, %r120, %p33;
|
|
selp.b32 %r130, -1, 0, %p33;
|
|
xor.b32 %r131, %r123, %r130;
|
|
shl.b32 %r132, %r365, 2;
|
|
xor.b32 %r133, %r132, %r130;
|
|
cvt.u64.u32 %rd62, %r131;
|
|
cvt.u64.u32 %rd63, %r133;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f264, %fd4;
|
|
setp.eq.s32 %p34, %r129, 0;
|
|
neg.f32 %f265, %f264;
|
|
selp.f32 %f1124, %f264, %f265, %p34;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f53, %f36, %f1123;
|
|
and.b32 %r45, %r366, 1;
|
|
setp.eq.s32 %p35, %r45, 0;
|
|
selp.f32 %f54, %f1124, 0f3F800000, %p35;
|
|
mul.rn.f32 %f55, %f1124, %f1124;
|
|
mov.f32 %f1125, 0fB94D4153;
|
|
@%p35 bra $L__BB0_30;
|
|
|
|
mov.f32 %f268, 0fBAB607ED;
|
|
mov.f32 %f269, 0f37CBAC00;
|
|
fma.rn.f32 %f1125, %f269, %f55, %f268;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f270, 0f3C0885E4, 0f3D2AAABB, %p35;
|
|
fma.rn.f32 %f271, %f1125, %f55, %f270;
|
|
selp.f32 %f272, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
|
|
fma.rn.f32 %f273, %f271, %f55, %f272;
|
|
mov.f32 %f274, 0f00000000;
|
|
fma.rn.f32 %f275, %f55, %f54, %f274;
|
|
fma.rn.f32 %f1126, %f273, %f275, %f54;
|
|
and.b32 %r135, %r366, 2;
|
|
setp.eq.s32 %p37, %r135, 0;
|
|
@%p37 bra $L__BB0_32;
|
|
|
|
mov.f32 %f277, 0fBF800000;
|
|
fma.rn.f32 %f1126, %f1126, %f277, %f274;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f287, %f53, %f53;
|
|
mov.f32 %f288, 0f3F800000;
|
|
sub.f32 %f289, %f288, %f287;
|
|
mul.f32 %f290, %f36, %f1126;
|
|
mul.f32 %f291, %f290, %f290;
|
|
sub.f32 %f292, %f289, %f291;
|
|
max.f32 %f293, %f274, %f292;
|
|
sqrt.rn.f32 %f294, %f293;
|
|
mul.f32 %f295, %f17, %f290;
|
|
mul.f32 %f296, %f18, %f290;
|
|
mul.f32 %f297, %f19, %f290;
|
|
fma.rn.f32 %f298, %f28, %f53, %f295;
|
|
fma.rn.f32 %f299, %f27, %f53, %f296;
|
|
fma.rn.f32 %f300, %f26, %f53, %f297;
|
|
fma.rn.f32 %f301, %f187, %f294, %f298;
|
|
fma.rn.f32 %f302, %f188, %f294, %f299;
|
|
fma.rn.f32 %f303, %f189, %f294, %f300;
|
|
add.f32 %f304, %f187, %f301;
|
|
add.f32 %f305, %f188, %f302;
|
|
add.f32 %f306, %f189, %f303;
|
|
mul.f32 %f307, %f21, %f304;
|
|
mul.f32 %f308, %f21, %f305;
|
|
mul.f32 %f309, %f21, %f306;
|
|
sub.f32 %f310, %f307, %f187;
|
|
sub.f32 %f311, %f308, %f188;
|
|
sub.f32 %f312, %f309, %f189;
|
|
mul.f32 %f313, %f311, %f311;
|
|
fma.rn.f32 %f314, %f310, %f310, %f313;
|
|
fma.rn.f32 %f315, %f312, %f312, %f314;
|
|
sqrt.rn.f32 %f316, %f315;
|
|
rcp.rn.f32 %f317, %f316;
|
|
mul.f32 %f281, %f317, %f310;
|
|
mul.f32 %f282, %f317, %f311;
|
|
mul.f32 %f283, %f317, %f312;
|
|
mov.f32 %f323, 0f38D1B717;
|
|
max.f32 %f324, %f322, %f323;
|
|
mul.f32 %f284, %f22, %f324;
|
|
mov.f32 %f285, 0f6C4ECB8F;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r173, 1;
|
|
mov.u32 %r174, 3;
|
|
mov.u32 %r177, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f14,%f15,%f16,%f281,%f282,%f283,%f284,%f285,%f274,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f325, %r136;
|
|
mov.b32 %f326, %r137;
|
|
mov.b32 %f327, %r138;
|
|
add.f32 %f1120, %f1120, %f325;
|
|
add.f32 %f1119, %f1119, %f326;
|
|
add.f32 %f1118, %f1118, %f327;
|
|
add.s32 %r358, %r358, 1;
|
|
setp.lt.s32 %p38, %r358, %r5;
|
|
@%p38 bra $L__BB0_8;
|
|
|
|
add.s32 %r356, %r356, 1;
|
|
setp.lt.s32 %p39, %r356, %r5;
|
|
@%p39 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
setp.eq.s32 %p40, %r5, 0;
|
|
mov.f32 %f1130, 0f3F800000;
|
|
mov.f32 %f1131, %f1130;
|
|
mov.f32 %f1132, %f1130;
|
|
@%p40 bra $L__BB0_36;
|
|
|
|
mul.lo.s32 %r207, %r5, %r5;
|
|
cvt.rn.f32.s32 %f331, %r207;
|
|
rcp.rn.f32 %f332, %f331;
|
|
mul.f32 %f1130, %f1120, %f332;
|
|
mul.f32 %f1131, %f1119, %f332;
|
|
mul.f32 %f1132, %f1118, %f332;
|
|
|
|
$L__BB0_36:
|
|
ld.const.f32 %f333, [params+524];
|
|
mul.f32 %f334, %f1130, %f333;
|
|
ld.const.v2.f32 {%f335, %f336}, [params+528];
|
|
mul.f32 %f339, %f1131, %f335;
|
|
mul.f32 %f340, %f1132, %f336;
|
|
cvt.sat.f32.f32 %f341, %f13;
|
|
mul.f32 %f73, %f334, %f341;
|
|
mul.f32 %f74, %f339, %f341;
|
|
mul.f32 %f75, %f340, %f341;
|
|
mul.f32 %f76, %f334, 0f3E800000;
|
|
mul.f32 %f77, %f339, 0f3E800000;
|
|
mul.f32 %f78, %f340, 0f3E800000;
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r208, %r48, 8;
|
|
setp.eq.s32 %p41, %r208, 0;
|
|
@%p41 bra $L__BB0_50;
|
|
|
|
mov.f32 %f346, 0f3EE8BA2E;
|
|
abs.f32 %f80, %f1130;
|
|
setp.lt.f32 %p42, %f80, 0f00800000;
|
|
mul.f32 %f348, %f80, 0f4B800000;
|
|
selp.f32 %f349, %f348, %f80, %p42;
|
|
selp.f32 %f350, 0fC3170000, 0fC2FE0000, %p42;
|
|
mov.b32 %r211, %f349;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f351, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f352, %r214;
|
|
add.f32 %f353, %f350, %f352;
|
|
setp.gt.f32 %p43, %f351, 0f3FB504F3;
|
|
mul.f32 %f354, %f351, 0f3F000000;
|
|
add.f32 %f355, %f353, 0f3F800000;
|
|
selp.f32 %f356, %f355, %f353, %p43;
|
|
selp.f32 %f357, %f354, %f351, %p43;
|
|
add.f32 %f358, %f357, 0fBF800000;
|
|
add.f32 %f359, %f357, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f360, %f359;
|
|
add.f32 %f361, %f358, %f358;
|
|
mul.f32 %f362, %f361, %f360;
|
|
mul.f32 %f363, %f362, %f362;
|
|
mov.f32 %f364, 0f3C4CAF63;
|
|
mov.f32 %f365, 0f3B18F0FE;
|
|
fma.rn.f32 %f366, %f365, %f363, %f364;
|
|
mov.f32 %f367, 0f3DAAAABD;
|
|
fma.rn.f32 %f368, %f366, %f363, %f367;
|
|
mul.rn.f32 %f369, %f368, %f363;
|
|
mul.rn.f32 %f370, %f369, %f362;
|
|
sub.f32 %f371, %f358, %f362;
|
|
add.f32 %f372, %f371, %f371;
|
|
neg.f32 %f373, %f362;
|
|
fma.rn.f32 %f374, %f373, %f358, %f372;
|
|
mul.rn.f32 %f375, %f360, %f374;
|
|
add.f32 %f376, %f370, %f362;
|
|
sub.f32 %f377, %f362, %f376;
|
|
add.f32 %f378, %f370, %f377;
|
|
add.f32 %f379, %f375, %f378;
|
|
add.f32 %f380, %f376, %f379;
|
|
sub.f32 %f381, %f376, %f380;
|
|
add.f32 %f382, %f379, %f381;
|
|
mov.f32 %f383, 0f3F317200;
|
|
mul.rn.f32 %f384, %f356, %f383;
|
|
mov.f32 %f385, 0f35BFBE8E;
|
|
mul.rn.f32 %f386, %f356, %f385;
|
|
add.f32 %f387, %f384, %f380;
|
|
sub.f32 %f388, %f384, %f387;
|
|
add.f32 %f389, %f380, %f388;
|
|
add.f32 %f390, %f382, %f389;
|
|
add.f32 %f391, %f386, %f390;
|
|
add.f32 %f392, %f387, %f391;
|
|
sub.f32 %f393, %f387, %f392;
|
|
add.f32 %f394, %f391, %f393;
|
|
mul.rn.f32 %f395, %f346, %f392;
|
|
neg.f32 %f396, %f395;
|
|
fma.rn.f32 %f397, %f346, %f392, %f396;
|
|
fma.rn.f32 %f398, %f346, %f394, %f397;
|
|
mov.f32 %f399, 0f00000000;
|
|
fma.rn.f32 %f400, %f399, %f392, %f398;
|
|
add.rn.f32 %f401, %f395, %f400;
|
|
neg.f32 %f402, %f401;
|
|
add.rn.f32 %f403, %f395, %f402;
|
|
add.rn.f32 %f404, %f403, %f400;
|
|
mov.b32 %r215, %f401;
|
|
setp.eq.s32 %p44, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f405, %r216;
|
|
add.f32 %f406, %f404, 0f37000000;
|
|
selp.f32 %f81, %f406, %f404, %p44;
|
|
selp.f32 %f407, %f405, %f401, %p44;
|
|
mov.f32 %f408, 0f3FB8AA3B;
|
|
mul.rn.f32 %f409, %f407, %f408;
|
|
cvt.rzi.f32.f32 %f410, %f409;
|
|
abs.f32 %f411, %f410;
|
|
setp.gt.f32 %p45, %f411, 0f42FC0000;
|
|
mov.b32 %r217, %f410;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f412, %r219;
|
|
selp.f32 %f413, %f412, %f410, %p45;
|
|
mov.f32 %f414, 0fBF317218;
|
|
fma.rn.f32 %f415, %f413, %f414, %f407;
|
|
mov.f32 %f416, 0f3102E308;
|
|
fma.rn.f32 %f417, %f413, %f416, %f415;
|
|
mul.f32 %f418, %f417, 0f3FB8AA3B;
|
|
add.f32 %f419, %f413, 0f4B40007F;
|
|
mov.b32 %r220, %f419;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f420, %r221;
|
|
ex2.approx.ftz.f32 %f421, %f418;
|
|
mul.f32 %f82, %f421, %f420;
|
|
setp.eq.f32 %p46, %f82, 0f7F800000;
|
|
mov.f32 %f1133, 0f7F800000;
|
|
@%p46 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1133, %f82, %f81, %f82;
|
|
|
|
$L__BB0_39:
|
|
mov.f32 %f1075, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f1074, %f1075;
|
|
add.f32 %f1073, %f1074, %f1074;
|
|
mov.f32 %f1072, 0f3EE8BA2E;
|
|
sub.f32 %f1071, %f1072, %f1073;
|
|
abs.f32 %f1070, %f1071;
|
|
setp.lt.f32 %p47, %f1130, 0f00000000;
|
|
setp.eq.f32 %p48, %f1070, 0f3F800000;
|
|
and.pred %p1, %p47, %p48;
|
|
setp.eq.f32 %p49, %f1130, 0f00000000;
|
|
@%p49 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f426, %f1130, %f1130;
|
|
selp.f32 %f1135, %f426, 0f00000000, %p48;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_147:
|
|
mov.f32 %f1026, 0f00000000;
|
|
mov.u32 %r368, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1026;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1026;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1026;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs115, 0;
|
|
st.global.v4.u16 [%rd25], {%rs112, %rs113, %rs114, %rs115};
|
|
|
|
$L__BB0_148:
|
|
ld.const.u64 %rd98, [params+256];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r342, [params+248];
|
|
mad.lo.s32 %r343, %r342, %r4, %r3;
|
|
mul.wide.u32 %rd100, %r343, 8;
|
|
add.s64 %rd26, %rd99, %rd100;
|
|
setp.eq.s32 %p167, %r368, 0;
|
|
@%p167 bra $L__BB0_150;
|
|
|
|
ld.global.v4.u16 {%rs122, %rs123, %rs124, %rs125}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1027, %rs122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1028, %rs123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1029, %rs124;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1030, %f1027, 0f00000000;
|
|
add.f32 %f1031, %f1028, 0f00000000;
|
|
add.f32 %f1032, %f1029, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1032;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1031;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1030;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs126, 0;
|
|
st.global.v4.u16 [%rd26], {%rs119, %rs120, %rs121, %rs126};
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_150:
|
|
mov.f32 %f1035, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1035;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1035;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1035;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs130, 0;
|
|
st.global.v4.u16 [%rd26], {%rs127, %rs128, %rs129, %rs130};
|
|
|
|
$L__BB0_151:
|
|
ld.const.u64 %rd101, [params+272];
|
|
cvta.to.global.u64 %rd102, %rd101;
|
|
ld.const.u32 %r344, [params+264];
|
|
mad.lo.s32 %r345, %r344, %r4, %r3;
|
|
mul.wide.u32 %rd103, %r345, 8;
|
|
add.s64 %rd27, %rd102, %rd103;
|
|
@%p167 bra $L__BB0_153;
|
|
|
|
ld.global.v4.u16 {%rs137, %rs138, %rs139, %rs140}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1036, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1037, %rs138;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1038, %rs139;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1039, %f1036, 0f00000000;
|
|
add.f32 %f1040, %f1037, 0f00000000;
|
|
add.f32 %f1041, %f1038, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1041;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1040;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1039;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs141, 0;
|
|
st.global.v4.u16 [%rd27], {%rs134, %rs135, %rs136, %rs141};
|
|
bra.uni $L__BB0_154;
|
|
|
|
$L__BB0_153:
|
|
mov.f32 %f1044, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1044;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1044;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1044;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs145, 0;
|
|
st.global.v4.u16 [%rd27], {%rs142, %rs143, %rs144, %rs145};
|
|
|
|
$L__BB0_154:
|
|
ld.const.u64 %rd104, [params+288];
|
|
cvta.to.global.u64 %rd105, %rd104;
|
|
ld.const.u32 %r346, [params+280];
|
|
mad.lo.s32 %r347, %r346, %r4, %r3;
|
|
mul.wide.u32 %rd106, %r347, 8;
|
|
add.s64 %rd28, %rd105, %rd106;
|
|
@%p167 bra $L__BB0_156;
|
|
|
|
ld.global.v4.u16 {%rs152, %rs153, %rs154, %rs155}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1045, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1046, %rs153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1047, %rs154;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1048, %f1045, 0f00000000;
|
|
add.f32 %f1049, %f1046, 0f00000000;
|
|
add.f32 %f1050, %f1047, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1050;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1049;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1048;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs156, 0;
|
|
st.global.v4.u16 [%rd28], {%rs149, %rs150, %rs151, %rs156};
|
|
bra.uni $L__BB0_157;
|
|
|
|
$L__BB0_156:
|
|
mov.f32 %f1053, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1053;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1053;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1053;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs160, 0;
|
|
st.global.v4.u16 [%rd28], {%rs157, %rs158, %rs159, %rs160};
|
|
|
|
$L__BB0_157:
|
|
ld.const.u64 %rd107, [params+304];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r348, [params+296];
|
|
mad.lo.s32 %r349, %r348, %r4, %r3;
|
|
mul.wide.u32 %rd109, %r349, 8;
|
|
add.s64 %rd29, %rd108, %rd109;
|
|
@%p167 bra $L__BB0_159;
|
|
|
|
ld.global.v4.u16 {%rs167, %rs168, %rs169, %rs170}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1054, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1055, %rs168;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1056, %rs169;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1057, %f1054, 0f00000000;
|
|
add.f32 %f1058, %f1055, 0f00000000;
|
|
add.f32 %f1059, %f1056, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1059;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1058;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1057;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs171, 0;
|
|
st.global.v4.u16 [%rd29], {%rs164, %rs165, %rs166, %rs171};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_159:
|
|
mov.f32 %f1062, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs174, %f1062;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1062;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1062;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs175, 0;
|
|
st.global.v4.u16 [%rd29], {%rs172, %rs173, %rs174, %rs175};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r222, %f1133;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f422, %r223;
|
|
selp.f32 %f1135, %f422, %f1133, %p1;
|
|
setp.geu.f32 %p50, %f1130, 0f00000000;
|
|
@%p50 bra $L__BB0_44;
|
|
|
|
mov.f32 %f423, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f424, %f423;
|
|
setp.eq.f32 %p51, %f424, 0f3EE8BA2E;
|
|
@%p51 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1135, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
abs.f32 %f1076, %f1130;
|
|
add.f32 %f427, %f1076, 0f3EE8BA2E;
|
|
mov.b32 %r224, %f427;
|
|
setp.lt.s32 %p53, %r224, 2139095040;
|
|
@%p53 bra $L__BB0_49;
|
|
|
|
abs.f32 %f1077, %f1130;
|
|
setp.gtu.f32 %p54, %f1077, 0f7F800000;
|
|
@%p54 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1135, %f1130, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f1078, %f1130;
|
|
setp.neu.f32 %p55, %f1078, 0f7F800000;
|
|
@%p55 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1135, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
ld.const.u64 %rd115, [params+192];
|
|
cvta.to.global.u64 %rd114, %rd115;
|
|
ld.const.u32 %r354, [params+184];
|
|
mad.lo.s32 %r353, %r354, %r4, %r3;
|
|
cvt.u64.u32 %rd113, %r353;
|
|
mul.f32 %f428, %f1135, 0f437F0000;
|
|
setp.eq.f32 %p56, %f1130, 0f3F800000;
|
|
selp.f32 %f429, 0f437F0000, %f428, %p56;
|
|
cvt.rzi.u32.f32 %r225, %f429;
|
|
shl.b64 %rd67, %rd113, 1;
|
|
add.s64 %rd68, %rd114, %rd67;
|
|
cvt.u16.u32 %rs17, %r225;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v2.u8 [%rd68], {%rs17, %rs18};
|
|
|
|
$L__BB0_50:
|
|
ld.const.u32 %r355, [params+104];
|
|
and.b32 %r226, %r355, 1;
|
|
setp.eq.b32 %p57, %r226, 1;
|
|
mov.pred %p58, 0;
|
|
xor.pred %p59, %p57, %p58;
|
|
not.pred %p60, %p59;
|
|
@%p60 bra $L__BB0_124;
|
|
|
|
mov.f32 %f434, 0f3EE66666;
|
|
abs.f32 %f92, %f73;
|
|
setp.lt.f32 %p61, %f92, 0f00800000;
|
|
mul.f32 %f436, %f92, 0f4B800000;
|
|
selp.f32 %f437, %f436, %f92, %p61;
|
|
selp.f32 %f438, 0fC3170000, 0fC2FE0000, %p61;
|
|
mov.b32 %r227, %f437;
|
|
and.b32 %r228, %r227, 8388607;
|
|
or.b32 %r229, %r228, 1065353216;
|
|
mov.b32 %f439, %r229;
|
|
shr.u32 %r230, %r227, 23;
|
|
cvt.rn.f32.u32 %f440, %r230;
|
|
add.f32 %f441, %f438, %f440;
|
|
setp.gt.f32 %p62, %f439, 0f3FB504F3;
|
|
mul.f32 %f442, %f439, 0f3F000000;
|
|
add.f32 %f443, %f441, 0f3F800000;
|
|
selp.f32 %f444, %f443, %f441, %p62;
|
|
selp.f32 %f445, %f442, %f439, %p62;
|
|
add.f32 %f446, %f445, 0fBF800000;
|
|
add.f32 %f447, %f445, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f448, %f447;
|
|
add.f32 %f449, %f446, %f446;
|
|
mul.f32 %f450, %f449, %f448;
|
|
mul.f32 %f451, %f450, %f450;
|
|
mov.f32 %f452, 0f3C4CAF63;
|
|
mov.f32 %f453, 0f3B18F0FE;
|
|
fma.rn.f32 %f454, %f453, %f451, %f452;
|
|
mov.f32 %f455, 0f3DAAAABD;
|
|
fma.rn.f32 %f456, %f454, %f451, %f455;
|
|
mul.rn.f32 %f457, %f456, %f451;
|
|
mul.rn.f32 %f458, %f457, %f450;
|
|
sub.f32 %f459, %f446, %f450;
|
|
add.f32 %f460, %f459, %f459;
|
|
neg.f32 %f461, %f450;
|
|
fma.rn.f32 %f462, %f461, %f446, %f460;
|
|
mul.rn.f32 %f463, %f448, %f462;
|
|
add.f32 %f464, %f458, %f450;
|
|
sub.f32 %f465, %f450, %f464;
|
|
add.f32 %f466, %f458, %f465;
|
|
add.f32 %f467, %f463, %f466;
|
|
add.f32 %f468, %f464, %f467;
|
|
sub.f32 %f469, %f464, %f468;
|
|
add.f32 %f470, %f467, %f469;
|
|
mov.f32 %f471, 0f3F317200;
|
|
mul.rn.f32 %f472, %f444, %f471;
|
|
mov.f32 %f473, 0f35BFBE8E;
|
|
mul.rn.f32 %f474, %f444, %f473;
|
|
add.f32 %f475, %f472, %f468;
|
|
sub.f32 %f476, %f472, %f475;
|
|
add.f32 %f477, %f468, %f476;
|
|
add.f32 %f478, %f470, %f477;
|
|
add.f32 %f479, %f474, %f478;
|
|
add.f32 %f480, %f475, %f479;
|
|
sub.f32 %f481, %f475, %f480;
|
|
add.f32 %f482, %f479, %f481;
|
|
mul.rn.f32 %f483, %f434, %f480;
|
|
neg.f32 %f484, %f483;
|
|
fma.rn.f32 %f485, %f434, %f480, %f484;
|
|
fma.rn.f32 %f486, %f434, %f482, %f485;
|
|
mov.f32 %f487, 0f00000000;
|
|
fma.rn.f32 %f488, %f487, %f480, %f486;
|
|
add.rn.f32 %f489, %f483, %f488;
|
|
neg.f32 %f490, %f489;
|
|
add.rn.f32 %f491, %f483, %f490;
|
|
add.rn.f32 %f492, %f491, %f488;
|
|
mov.b32 %r231, %f489;
|
|
setp.eq.s32 %p63, %r231, 1118925336;
|
|
add.s32 %r232, %r231, -1;
|
|
mov.b32 %f493, %r232;
|
|
add.f32 %f494, %f492, 0f37000000;
|
|
selp.f32 %f93, %f494, %f492, %p63;
|
|
selp.f32 %f495, %f493, %f489, %p63;
|
|
mov.f32 %f496, 0f3FB8AA3B;
|
|
mul.rn.f32 %f497, %f495, %f496;
|
|
cvt.rzi.f32.f32 %f498, %f497;
|
|
abs.f32 %f499, %f498;
|
|
setp.gt.f32 %p64, %f499, 0f42FC0000;
|
|
mov.b32 %r233, %f498;
|
|
and.b32 %r234, %r233, -2147483648;
|
|
or.b32 %r235, %r234, 1123811328;
|
|
mov.b32 %f500, %r235;
|
|
selp.f32 %f501, %f500, %f498, %p64;
|
|
mov.f32 %f502, 0fBF317218;
|
|
fma.rn.f32 %f503, %f501, %f502, %f495;
|
|
mov.f32 %f504, 0f3102E308;
|
|
fma.rn.f32 %f505, %f501, %f504, %f503;
|
|
mul.f32 %f506, %f505, 0f3FB8AA3B;
|
|
add.f32 %f507, %f501, 0f4B40007F;
|
|
mov.b32 %r236, %f507;
|
|
shl.b32 %r237, %r236, 23;
|
|
mov.b32 %f508, %r237;
|
|
ex2.approx.ftz.f32 %f509, %f506;
|
|
mul.f32 %f94, %f509, %f508;
|
|
setp.eq.f32 %p65, %f94, 0f7F800000;
|
|
mov.f32 %f1136, 0f7F800000;
|
|
@%p65 bra $L__BB0_53;
|
|
|
|
fma.rn.f32 %f1136, %f94, %f93, %f94;
|
|
|
|
$L__BB0_53:
|
|
mov.f32 %f1084, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1083, %f1084;
|
|
add.f32 %f1082, %f1083, %f1083;
|
|
mov.f32 %f1081, 0f3EE66666;
|
|
sub.f32 %f1080, %f1081, %f1082;
|
|
abs.f32 %f1079, %f1080;
|
|
setp.lt.f32 %p66, %f73, 0f00000000;
|
|
setp.eq.f32 %p67, %f1079, 0f3F800000;
|
|
and.pred %p2, %p66, %p67;
|
|
setp.eq.f32 %p68, %f73, 0f00000000;
|
|
@%p68 bra $L__BB0_57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f514, %f73, %f73;
|
|
selp.f32 %f1138, %f514, 0f00000000, %p67;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_54:
|
|
mov.b32 %r238, %f1136;
|
|
xor.b32 %r239, %r238, -2147483648;
|
|
mov.b32 %f510, %r239;
|
|
selp.f32 %f1138, %f510, %f1136, %p2;
|
|
setp.geu.f32 %p69, %f73, 0f00000000;
|
|
@%p69 bra $L__BB0_58;
|
|
|
|
mov.f32 %f511, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f512, %f511;
|
|
setp.eq.f32 %p70, %f512, 0f3EE66666;
|
|
@%p70 bra $L__BB0_58;
|
|
|
|
mov.f32 %f1138, 0f7FFFFFFF;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1085, %f73;
|
|
add.f32 %f515, %f1085, 0f3EE66666;
|
|
mov.b32 %r240, %f515;
|
|
setp.lt.s32 %p72, %r240, 2139095040;
|
|
@%p72 bra $L__BB0_63;
|
|
|
|
abs.f32 %f1086, %f73;
|
|
setp.gtu.f32 %p73, %f1086, 0f7F800000;
|
|
@%p73 bra $L__BB0_62;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1138, %f73, 0f3EE66666;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f1087, %f73;
|
|
setp.neu.f32 %p74, %f1087, 0f7F800000;
|
|
@%p74 bra $L__BB0_63;
|
|
|
|
selp.f32 %f1138, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_63:
|
|
setp.eq.f32 %p75, %f73, 0f3F800000;
|
|
selp.f32 %f103, 0f3F800000, %f1138, %p75;
|
|
abs.f32 %f104, %f74;
|
|
setp.lt.f32 %p76, %f104, 0f00800000;
|
|
mul.f32 %f517, %f104, 0f4B800000;
|
|
selp.f32 %f518, %f517, %f104, %p76;
|
|
selp.f32 %f519, 0fC3170000, 0fC2FE0000, %p76;
|
|
mov.b32 %r241, %f518;
|
|
and.b32 %r242, %r241, 8388607;
|
|
or.b32 %r243, %r242, 1065353216;
|
|
mov.b32 %f520, %r243;
|
|
shr.u32 %r244, %r241, 23;
|
|
cvt.rn.f32.u32 %f521, %r244;
|
|
add.f32 %f522, %f519, %f521;
|
|
setp.gt.f32 %p77, %f520, 0f3FB504F3;
|
|
mul.f32 %f523, %f520, 0f3F000000;
|
|
add.f32 %f524, %f522, 0f3F800000;
|
|
selp.f32 %f525, %f524, %f522, %p77;
|
|
selp.f32 %f526, %f523, %f520, %p77;
|
|
add.f32 %f527, %f526, 0fBF800000;
|
|
add.f32 %f528, %f526, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f529, %f528;
|
|
add.f32 %f530, %f527, %f527;
|
|
mul.f32 %f531, %f530, %f529;
|
|
mul.f32 %f532, %f531, %f531;
|
|
mov.f32 %f533, 0f3C4CAF63;
|
|
mov.f32 %f534, 0f3B18F0FE;
|
|
fma.rn.f32 %f535, %f534, %f532, %f533;
|
|
mov.f32 %f536, 0f3DAAAABD;
|
|
fma.rn.f32 %f537, %f535, %f532, %f536;
|
|
mul.rn.f32 %f538, %f537, %f532;
|
|
mul.rn.f32 %f539, %f538, %f531;
|
|
sub.f32 %f540, %f527, %f531;
|
|
add.f32 %f541, %f540, %f540;
|
|
neg.f32 %f542, %f531;
|
|
fma.rn.f32 %f543, %f542, %f527, %f541;
|
|
mul.rn.f32 %f544, %f529, %f543;
|
|
add.f32 %f545, %f539, %f531;
|
|
sub.f32 %f546, %f531, %f545;
|
|
add.f32 %f547, %f539, %f546;
|
|
add.f32 %f548, %f544, %f547;
|
|
add.f32 %f549, %f545, %f548;
|
|
sub.f32 %f550, %f545, %f549;
|
|
add.f32 %f551, %f548, %f550;
|
|
mov.f32 %f552, 0f3F317200;
|
|
mul.rn.f32 %f553, %f525, %f552;
|
|
mov.f32 %f554, 0f35BFBE8E;
|
|
mul.rn.f32 %f555, %f525, %f554;
|
|
add.f32 %f556, %f553, %f549;
|
|
sub.f32 %f557, %f553, %f556;
|
|
add.f32 %f558, %f549, %f557;
|
|
add.f32 %f559, %f551, %f558;
|
|
add.f32 %f560, %f555, %f559;
|
|
add.f32 %f561, %f556, %f560;
|
|
sub.f32 %f562, %f556, %f561;
|
|
add.f32 %f563, %f560, %f562;
|
|
mov.f32 %f564, 0f3EE66666;
|
|
mul.rn.f32 %f565, %f564, %f561;
|
|
neg.f32 %f566, %f565;
|
|
fma.rn.f32 %f567, %f564, %f561, %f566;
|
|
fma.rn.f32 %f568, %f564, %f563, %f567;
|
|
mov.f32 %f569, 0f00000000;
|
|
fma.rn.f32 %f570, %f569, %f561, %f568;
|
|
add.rn.f32 %f571, %f565, %f570;
|
|
neg.f32 %f572, %f571;
|
|
add.rn.f32 %f573, %f565, %f572;
|
|
add.rn.f32 %f574, %f573, %f570;
|
|
mov.b32 %r245, %f571;
|
|
setp.eq.s32 %p78, %r245, 1118925336;
|
|
add.s32 %r246, %r245, -1;
|
|
mov.b32 %f575, %r246;
|
|
add.f32 %f576, %f574, 0f37000000;
|
|
selp.f32 %f105, %f576, %f574, %p78;
|
|
selp.f32 %f577, %f575, %f571, %p78;
|
|
mov.f32 %f578, 0f3FB8AA3B;
|
|
mul.rn.f32 %f579, %f577, %f578;
|
|
cvt.rzi.f32.f32 %f580, %f579;
|
|
abs.f32 %f581, %f580;
|
|
setp.gt.f32 %p79, %f581, 0f42FC0000;
|
|
mov.b32 %r247, %f580;
|
|
and.b32 %r248, %r247, -2147483648;
|
|
or.b32 %r249, %r248, 1123811328;
|
|
mov.b32 %f582, %r249;
|
|
selp.f32 %f583, %f582, %f580, %p79;
|
|
mov.f32 %f584, 0fBF317218;
|
|
fma.rn.f32 %f585, %f583, %f584, %f577;
|
|
mov.f32 %f586, 0f3102E308;
|
|
fma.rn.f32 %f587, %f583, %f586, %f585;
|
|
mul.f32 %f588, %f587, 0f3FB8AA3B;
|
|
add.f32 %f589, %f583, 0f4B40007F;
|
|
mov.b32 %r250, %f589;
|
|
shl.b32 %r251, %r250, 23;
|
|
mov.b32 %f590, %r251;
|
|
ex2.approx.ftz.f32 %f591, %f588;
|
|
mul.f32 %f106, %f591, %f590;
|
|
setp.eq.f32 %p80, %f106, 0f7F800000;
|
|
mov.f32 %f1139, 0f7F800000;
|
|
@%p80 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1139, %f106, %f105, %f106;
|
|
|
|
$L__BB0_65:
|
|
setp.lt.f32 %p81, %f74, 0f00000000;
|
|
and.pred %p3, %p81, %p67;
|
|
setp.eq.f32 %p83, %f74, 0f00000000;
|
|
@%p83 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f596, %f74, %f74;
|
|
selp.f32 %f1141, %f596, 0f00000000, %p67;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r252, %f1139;
|
|
xor.b32 %r253, %r252, -2147483648;
|
|
mov.b32 %f592, %r253;
|
|
selp.f32 %f1141, %f592, %f1139, %p3;
|
|
setp.geu.f32 %p84, %f74, 0f00000000;
|
|
@%p84 bra $L__BB0_70;
|
|
|
|
mov.f32 %f593, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f594, %f593;
|
|
setp.eq.f32 %p85, %f594, 0f3EE66666;
|
|
@%p85 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1141, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1088, %f74;
|
|
add.f32 %f597, %f1088, 0f3EE66666;
|
|
mov.b32 %r254, %f597;
|
|
setp.lt.s32 %p87, %r254, 2139095040;
|
|
@%p87 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1089, %f74;
|
|
setp.gtu.f32 %p88, %f1089, 0f7F800000;
|
|
@%p88 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1141, %f74, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1090, %f74;
|
|
setp.neu.f32 %p89, %f1090, 0f7F800000;
|
|
@%p89 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1141, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p90, %f74, 0f3F800000;
|
|
selp.f32 %f115, 0f3F800000, %f1141, %p90;
|
|
abs.f32 %f116, %f75;
|
|
setp.lt.f32 %p91, %f116, 0f00800000;
|
|
mul.f32 %f599, %f116, 0f4B800000;
|
|
selp.f32 %f600, %f599, %f116, %p91;
|
|
selp.f32 %f601, 0fC3170000, 0fC2FE0000, %p91;
|
|
mov.b32 %r255, %f600;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f602, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f603, %r258;
|
|
add.f32 %f604, %f601, %f603;
|
|
setp.gt.f32 %p92, %f602, 0f3FB504F3;
|
|
mul.f32 %f605, %f602, 0f3F000000;
|
|
add.f32 %f606, %f604, 0f3F800000;
|
|
selp.f32 %f607, %f606, %f604, %p92;
|
|
selp.f32 %f608, %f605, %f602, %p92;
|
|
add.f32 %f609, %f608, 0fBF800000;
|
|
add.f32 %f610, %f608, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f611, %f610;
|
|
add.f32 %f612, %f609, %f609;
|
|
mul.f32 %f613, %f612, %f611;
|
|
mul.f32 %f614, %f613, %f613;
|
|
mov.f32 %f615, 0f3C4CAF63;
|
|
mov.f32 %f616, 0f3B18F0FE;
|
|
fma.rn.f32 %f617, %f616, %f614, %f615;
|
|
mov.f32 %f618, 0f3DAAAABD;
|
|
fma.rn.f32 %f619, %f617, %f614, %f618;
|
|
mul.rn.f32 %f620, %f619, %f614;
|
|
mul.rn.f32 %f621, %f620, %f613;
|
|
sub.f32 %f622, %f609, %f613;
|
|
add.f32 %f623, %f622, %f622;
|
|
neg.f32 %f624, %f613;
|
|
fma.rn.f32 %f625, %f624, %f609, %f623;
|
|
mul.rn.f32 %f626, %f611, %f625;
|
|
add.f32 %f627, %f621, %f613;
|
|
sub.f32 %f628, %f613, %f627;
|
|
add.f32 %f629, %f621, %f628;
|
|
add.f32 %f630, %f626, %f629;
|
|
add.f32 %f631, %f627, %f630;
|
|
sub.f32 %f632, %f627, %f631;
|
|
add.f32 %f633, %f630, %f632;
|
|
mov.f32 %f634, 0f3F317200;
|
|
mul.rn.f32 %f635, %f607, %f634;
|
|
mov.f32 %f636, 0f35BFBE8E;
|
|
mul.rn.f32 %f637, %f607, %f636;
|
|
add.f32 %f638, %f635, %f631;
|
|
sub.f32 %f639, %f635, %f638;
|
|
add.f32 %f640, %f631, %f639;
|
|
add.f32 %f641, %f633, %f640;
|
|
add.f32 %f642, %f637, %f641;
|
|
add.f32 %f643, %f638, %f642;
|
|
sub.f32 %f644, %f638, %f643;
|
|
add.f32 %f645, %f642, %f644;
|
|
mov.f32 %f646, 0f3EE66666;
|
|
mul.rn.f32 %f647, %f646, %f643;
|
|
neg.f32 %f648, %f647;
|
|
fma.rn.f32 %f649, %f646, %f643, %f648;
|
|
fma.rn.f32 %f650, %f646, %f645, %f649;
|
|
mov.f32 %f651, 0f00000000;
|
|
fma.rn.f32 %f652, %f651, %f643, %f650;
|
|
add.rn.f32 %f653, %f647, %f652;
|
|
neg.f32 %f654, %f653;
|
|
add.rn.f32 %f655, %f647, %f654;
|
|
add.rn.f32 %f656, %f655, %f652;
|
|
mov.b32 %r259, %f653;
|
|
setp.eq.s32 %p93, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f657, %r260;
|
|
add.f32 %f658, %f656, 0f37000000;
|
|
selp.f32 %f117, %f658, %f656, %p93;
|
|
selp.f32 %f659, %f657, %f653, %p93;
|
|
mov.f32 %f660, 0f3FB8AA3B;
|
|
mul.rn.f32 %f661, %f659, %f660;
|
|
cvt.rzi.f32.f32 %f662, %f661;
|
|
abs.f32 %f663, %f662;
|
|
setp.gt.f32 %p94, %f663, 0f42FC0000;
|
|
mov.b32 %r261, %f662;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f664, %r263;
|
|
selp.f32 %f665, %f664, %f662, %p94;
|
|
mov.f32 %f666, 0fBF317218;
|
|
fma.rn.f32 %f667, %f665, %f666, %f659;
|
|
mov.f32 %f668, 0f3102E308;
|
|
fma.rn.f32 %f669, %f665, %f668, %f667;
|
|
mul.f32 %f670, %f669, 0f3FB8AA3B;
|
|
add.f32 %f671, %f665, 0f4B40007F;
|
|
mov.b32 %r264, %f671;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f672, %r265;
|
|
ex2.approx.ftz.f32 %f673, %f670;
|
|
mul.f32 %f118, %f673, %f672;
|
|
setp.eq.f32 %p95, %f118, 0f7F800000;
|
|
mov.f32 %f1142, 0f7F800000;
|
|
@%p95 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1142, %f118, %f117, %f118;
|
|
|
|
$L__BB0_77:
|
|
setp.lt.f32 %p96, %f75, 0f00000000;
|
|
and.pred %p4, %p96, %p67;
|
|
setp.eq.f32 %p98, %f75, 0f00000000;
|
|
@%p98 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f678, %f75, %f75;
|
|
selp.f32 %f1144, %f678, 0f00000000, %p67;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r266, %f1142;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f674, %r267;
|
|
selp.f32 %f1144, %f674, %f1142, %p4;
|
|
setp.geu.f32 %p99, %f75, 0f00000000;
|
|
@%p99 bra $L__BB0_82;
|
|
|
|
mov.f32 %f675, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f676, %f675;
|
|
setp.eq.f32 %p100, %f676, 0f3EE66666;
|
|
@%p100 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1144, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
abs.f32 %f1091, %f75;
|
|
add.f32 %f679, %f1091, 0f3EE66666;
|
|
mov.b32 %r268, %f679;
|
|
setp.lt.s32 %p102, %r268, 2139095040;
|
|
@%p102 bra $L__BB0_87;
|
|
|
|
abs.f32 %f1092, %f75;
|
|
setp.gtu.f32 %p103, %f1092, 0f7F800000;
|
|
@%p103 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1144, %f75, 0f3EE66666;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
abs.f32 %f1093, %f75;
|
|
setp.neu.f32 %p104, %f1093, 0f7F800000;
|
|
@%p104 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1144, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
setp.eq.f32 %p105, %f75, 0f3F800000;
|
|
mov.f32 %f681, 0f3F800000;
|
|
selp.f32 %f682, 0f3F800000, %f1144, %p105;
|
|
min.f32 %f683, %f103, %f681;
|
|
mov.f32 %f684, 0f00000000;
|
|
max.f32 %f127, %f684, %f683;
|
|
min.f32 %f685, %f115, %f681;
|
|
max.f32 %f128, %f684, %f685;
|
|
min.f32 %f686, %f682, %f681;
|
|
max.f32 %f129, %f684, %f686;
|
|
mov.f32 %f690, 0f3ED55555;
|
|
abs.f32 %f131, %f127;
|
|
setp.lt.f32 %p106, %f131, 0f00800000;
|
|
mul.f32 %f692, %f131, 0f4B800000;
|
|
selp.f32 %f693, %f692, %f131, %p106;
|
|
selp.f32 %f694, 0fC3170000, 0fC2FE0000, %p106;
|
|
mov.b32 %r271, %f693;
|
|
and.b32 %r272, %r271, 8388607;
|
|
or.b32 %r273, %r272, 1065353216;
|
|
mov.b32 %f695, %r273;
|
|
shr.u32 %r274, %r271, 23;
|
|
cvt.rn.f32.u32 %f696, %r274;
|
|
add.f32 %f697, %f694, %f696;
|
|
setp.gt.f32 %p107, %f695, 0f3FB504F3;
|
|
mul.f32 %f698, %f695, 0f3F000000;
|
|
add.f32 %f699, %f697, 0f3F800000;
|
|
selp.f32 %f700, %f699, %f697, %p107;
|
|
selp.f32 %f701, %f698, %f695, %p107;
|
|
add.f32 %f702, %f701, 0fBF800000;
|
|
add.f32 %f703, %f701, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f704, %f703;
|
|
add.f32 %f705, %f702, %f702;
|
|
mul.f32 %f706, %f705, %f704;
|
|
mul.f32 %f707, %f706, %f706;
|
|
mov.f32 %f708, 0f3C4CAF63;
|
|
mov.f32 %f709, 0f3B18F0FE;
|
|
fma.rn.f32 %f710, %f709, %f707, %f708;
|
|
mov.f32 %f711, 0f3DAAAABD;
|
|
fma.rn.f32 %f712, %f710, %f707, %f711;
|
|
mul.rn.f32 %f713, %f712, %f707;
|
|
mul.rn.f32 %f714, %f713, %f706;
|
|
sub.f32 %f715, %f702, %f706;
|
|
add.f32 %f716, %f715, %f715;
|
|
neg.f32 %f717, %f706;
|
|
fma.rn.f32 %f718, %f717, %f702, %f716;
|
|
mul.rn.f32 %f719, %f704, %f718;
|
|
add.f32 %f720, %f714, %f706;
|
|
sub.f32 %f721, %f706, %f720;
|
|
add.f32 %f722, %f714, %f721;
|
|
add.f32 %f723, %f719, %f722;
|
|
add.f32 %f724, %f720, %f723;
|
|
sub.f32 %f725, %f720, %f724;
|
|
add.f32 %f726, %f723, %f725;
|
|
mov.f32 %f727, 0f3F317200;
|
|
mul.rn.f32 %f728, %f700, %f727;
|
|
mov.f32 %f729, 0f35BFBE8E;
|
|
mul.rn.f32 %f730, %f700, %f729;
|
|
add.f32 %f731, %f728, %f724;
|
|
sub.f32 %f732, %f728, %f731;
|
|
add.f32 %f733, %f724, %f732;
|
|
add.f32 %f734, %f726, %f733;
|
|
add.f32 %f735, %f730, %f734;
|
|
add.f32 %f736, %f731, %f735;
|
|
sub.f32 %f737, %f731, %f736;
|
|
add.f32 %f738, %f735, %f737;
|
|
mul.rn.f32 %f739, %f690, %f736;
|
|
neg.f32 %f740, %f739;
|
|
fma.rn.f32 %f741, %f690, %f736, %f740;
|
|
fma.rn.f32 %f742, %f690, %f738, %f741;
|
|
fma.rn.f32 %f743, %f684, %f736, %f742;
|
|
add.rn.f32 %f744, %f739, %f743;
|
|
neg.f32 %f745, %f744;
|
|
add.rn.f32 %f746, %f739, %f745;
|
|
add.rn.f32 %f747, %f746, %f743;
|
|
mov.b32 %r275, %f744;
|
|
setp.eq.s32 %p108, %r275, 1118925336;
|
|
add.s32 %r276, %r275, -1;
|
|
mov.b32 %f748, %r276;
|
|
add.f32 %f749, %f747, 0f37000000;
|
|
selp.f32 %f132, %f749, %f747, %p108;
|
|
selp.f32 %f750, %f748, %f744, %p108;
|
|
mov.f32 %f751, 0f3FB8AA3B;
|
|
mul.rn.f32 %f752, %f750, %f751;
|
|
cvt.rzi.f32.f32 %f753, %f752;
|
|
abs.f32 %f754, %f753;
|
|
setp.gt.f32 %p109, %f754, 0f42FC0000;
|
|
mov.b32 %r277, %f753;
|
|
and.b32 %r278, %r277, -2147483648;
|
|
or.b32 %r279, %r278, 1123811328;
|
|
mov.b32 %f755, %r279;
|
|
selp.f32 %f756, %f755, %f753, %p109;
|
|
mov.f32 %f757, 0fBF317218;
|
|
fma.rn.f32 %f758, %f756, %f757, %f750;
|
|
mov.f32 %f759, 0f3102E308;
|
|
fma.rn.f32 %f760, %f756, %f759, %f758;
|
|
mul.f32 %f761, %f760, 0f3FB8AA3B;
|
|
add.f32 %f762, %f756, 0f4B40007F;
|
|
mov.b32 %r280, %f762;
|
|
shl.b32 %r281, %r280, 23;
|
|
mov.b32 %f763, %r281;
|
|
ex2.approx.ftz.f32 %f764, %f761;
|
|
mul.f32 %f133, %f764, %f763;
|
|
setp.eq.f32 %p110, %f133, 0f7F800000;
|
|
mov.f32 %f1145, 0f7F800000;
|
|
@%p110 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1145, %f133, %f132, %f133;
|
|
|
|
$L__BB0_89:
|
|
mov.f32 %f1068, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1067, %f1068;
|
|
add.f32 %f1066, %f1067, %f1067;
|
|
mov.f32 %f1065, 0f3ED55555;
|
|
sub.f32 %f1064, %f1065, %f1066;
|
|
abs.f32 %f1063, %f1064;
|
|
setp.lt.f32 %p111, %f127, 0f00000000;
|
|
setp.eq.f32 %p112, %f1063, 0f3F800000;
|
|
and.pred %p5, %p111, %p112;
|
|
setp.eq.f32 %p113, %f127, 0f00000000;
|
|
@%p113 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f769, %f127, %f127;
|
|
selp.f32 %f1147, %f769, 0f00000000, %p112;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.b32 %r282, %f1145;
|
|
xor.b32 %r283, %r282, -2147483648;
|
|
mov.b32 %f765, %r283;
|
|
selp.f32 %f1147, %f765, %f1145, %p5;
|
|
setp.geu.f32 %p114, %f127, 0f00000000;
|
|
@%p114 bra $L__BB0_94;
|
|
|
|
mov.f32 %f766, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f767, %f766;
|
|
setp.eq.f32 %p115, %f767, 0f3ED55555;
|
|
@%p115 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1147, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f770, %f131, 0f3ED55555;
|
|
mov.b32 %r284, %f770;
|
|
setp.lt.s32 %p117, %r284, 2139095040;
|
|
@%p117 bra $L__BB0_99;
|
|
|
|
setp.gtu.f32 %p118, %f131, 0f7F800000;
|
|
@%p118 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f1147, %f127, 0f3ED55555;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
setp.neu.f32 %p119, %f131, 0f7F800000;
|
|
@%p119 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1147, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
abs.f32 %f142, %f128;
|
|
setp.lt.f32 %p120, %f142, 0f00800000;
|
|
mul.f32 %f772, %f142, 0f4B800000;
|
|
selp.f32 %f773, %f772, %f142, %p120;
|
|
selp.f32 %f774, 0fC3170000, 0fC2FE0000, %p120;
|
|
mov.b32 %r285, %f773;
|
|
and.b32 %r286, %r285, 8388607;
|
|
or.b32 %r287, %r286, 1065353216;
|
|
mov.b32 %f775, %r287;
|
|
shr.u32 %r288, %r285, 23;
|
|
cvt.rn.f32.u32 %f776, %r288;
|
|
add.f32 %f777, %f774, %f776;
|
|
setp.gt.f32 %p121, %f775, 0f3FB504F3;
|
|
mul.f32 %f778, %f775, 0f3F000000;
|
|
add.f32 %f779, %f777, 0f3F800000;
|
|
selp.f32 %f780, %f779, %f777, %p121;
|
|
selp.f32 %f781, %f778, %f775, %p121;
|
|
add.f32 %f782, %f781, 0fBF800000;
|
|
add.f32 %f783, %f781, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f784, %f783;
|
|
add.f32 %f785, %f782, %f782;
|
|
mul.f32 %f786, %f785, %f784;
|
|
mul.f32 %f787, %f786, %f786;
|
|
mov.f32 %f788, 0f3C4CAF63;
|
|
mov.f32 %f789, 0f3B18F0FE;
|
|
fma.rn.f32 %f790, %f789, %f787, %f788;
|
|
mov.f32 %f791, 0f3DAAAABD;
|
|
fma.rn.f32 %f792, %f790, %f787, %f791;
|
|
mul.rn.f32 %f793, %f792, %f787;
|
|
mul.rn.f32 %f794, %f793, %f786;
|
|
sub.f32 %f795, %f782, %f786;
|
|
add.f32 %f796, %f795, %f795;
|
|
neg.f32 %f797, %f786;
|
|
fma.rn.f32 %f798, %f797, %f782, %f796;
|
|
mul.rn.f32 %f799, %f784, %f798;
|
|
add.f32 %f800, %f794, %f786;
|
|
sub.f32 %f801, %f786, %f800;
|
|
add.f32 %f802, %f794, %f801;
|
|
add.f32 %f803, %f799, %f802;
|
|
add.f32 %f804, %f800, %f803;
|
|
sub.f32 %f805, %f800, %f804;
|
|
add.f32 %f806, %f803, %f805;
|
|
mov.f32 %f807, 0f3F317200;
|
|
mul.rn.f32 %f808, %f780, %f807;
|
|
mov.f32 %f809, 0f35BFBE8E;
|
|
mul.rn.f32 %f810, %f780, %f809;
|
|
add.f32 %f811, %f808, %f804;
|
|
sub.f32 %f812, %f808, %f811;
|
|
add.f32 %f813, %f804, %f812;
|
|
add.f32 %f814, %f806, %f813;
|
|
add.f32 %f815, %f810, %f814;
|
|
add.f32 %f816, %f811, %f815;
|
|
sub.f32 %f817, %f811, %f816;
|
|
add.f32 %f818, %f815, %f817;
|
|
mov.f32 %f819, 0f3ED55555;
|
|
mul.rn.f32 %f820, %f819, %f816;
|
|
neg.f32 %f821, %f820;
|
|
fma.rn.f32 %f822, %f819, %f816, %f821;
|
|
fma.rn.f32 %f823, %f819, %f818, %f822;
|
|
mov.f32 %f824, 0f00000000;
|
|
fma.rn.f32 %f825, %f824, %f816, %f823;
|
|
add.rn.f32 %f826, %f820, %f825;
|
|
neg.f32 %f827, %f826;
|
|
add.rn.f32 %f828, %f820, %f827;
|
|
add.rn.f32 %f829, %f828, %f825;
|
|
mov.b32 %r289, %f826;
|
|
setp.eq.s32 %p122, %r289, 1118925336;
|
|
add.s32 %r290, %r289, -1;
|
|
mov.b32 %f830, %r290;
|
|
add.f32 %f831, %f829, 0f37000000;
|
|
selp.f32 %f143, %f831, %f829, %p122;
|
|
selp.f32 %f832, %f830, %f826, %p122;
|
|
mov.f32 %f833, 0f3FB8AA3B;
|
|
mul.rn.f32 %f834, %f832, %f833;
|
|
cvt.rzi.f32.f32 %f835, %f834;
|
|
abs.f32 %f836, %f835;
|
|
setp.gt.f32 %p123, %f836, 0f42FC0000;
|
|
mov.b32 %r291, %f835;
|
|
and.b32 %r292, %r291, -2147483648;
|
|
or.b32 %r293, %r292, 1123811328;
|
|
mov.b32 %f837, %r293;
|
|
selp.f32 %f838, %f837, %f835, %p123;
|
|
mov.f32 %f839, 0fBF317218;
|
|
fma.rn.f32 %f840, %f838, %f839, %f832;
|
|
mov.f32 %f841, 0f3102E308;
|
|
fma.rn.f32 %f842, %f838, %f841, %f840;
|
|
mul.f32 %f843, %f842, 0f3FB8AA3B;
|
|
add.f32 %f844, %f838, 0f4B40007F;
|
|
mov.b32 %r294, %f844;
|
|
shl.b32 %r295, %r294, 23;
|
|
mov.b32 %f845, %r295;
|
|
ex2.approx.ftz.f32 %f846, %f843;
|
|
mul.f32 %f144, %f846, %f845;
|
|
setp.eq.f32 %p124, %f144, 0f7F800000;
|
|
mov.f32 %f1148, 0f7F800000;
|
|
@%p124 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1148, %f144, %f143, %f144;
|
|
|
|
$L__BB0_101:
|
|
setp.lt.f32 %p125, %f128, 0f00000000;
|
|
and.pred %p6, %p125, %p112;
|
|
setp.eq.f32 %p127, %f128, 0f00000000;
|
|
@%p127 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f851, %f128, %f128;
|
|
selp.f32 %f1150, %f851, 0f00000000, %p112;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r296, %f1148;
|
|
xor.b32 %r297, %r296, -2147483648;
|
|
mov.b32 %f847, %r297;
|
|
selp.f32 %f1150, %f847, %f1148, %p6;
|
|
setp.geu.f32 %p128, %f128, 0f00000000;
|
|
@%p128 bra $L__BB0_106;
|
|
|
|
mov.f32 %f848, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f849, %f848;
|
|
setp.eq.f32 %p129, %f849, 0f3ED55555;
|
|
@%p129 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1150, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1096, 0f00000000;
|
|
max.f32 %f1095, %f1096, %f685;
|
|
abs.f32 %f1094, %f1095;
|
|
add.f32 %f852, %f1094, 0f3ED55555;
|
|
mov.b32 %r298, %f852;
|
|
setp.lt.s32 %p131, %r298, 2139095040;
|
|
@%p131 bra $L__BB0_111;
|
|
|
|
mov.f32 %f1099, 0f00000000;
|
|
max.f32 %f1098, %f1099, %f685;
|
|
abs.f32 %f1097, %f1098;
|
|
setp.gtu.f32 %p132, %f1097, 0f7F800000;
|
|
@%p132 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1150, %f128, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
mov.f32 %f1102, 0f00000000;
|
|
max.f32 %f1101, %f1102, %f685;
|
|
abs.f32 %f1100, %f1101;
|
|
setp.neu.f32 %p133, %f1100, 0f7F800000;
|
|
@%p133 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1150, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
abs.f32 %f153, %f129;
|
|
setp.lt.f32 %p134, %f153, 0f00800000;
|
|
mul.f32 %f854, %f153, 0f4B800000;
|
|
selp.f32 %f855, %f854, %f153, %p134;
|
|
selp.f32 %f856, 0fC3170000, 0fC2FE0000, %p134;
|
|
mov.b32 %r299, %f855;
|
|
and.b32 %r300, %r299, 8388607;
|
|
or.b32 %r301, %r300, 1065353216;
|
|
mov.b32 %f857, %r301;
|
|
shr.u32 %r302, %r299, 23;
|
|
cvt.rn.f32.u32 %f858, %r302;
|
|
add.f32 %f859, %f856, %f858;
|
|
setp.gt.f32 %p135, %f857, 0f3FB504F3;
|
|
mul.f32 %f860, %f857, 0f3F000000;
|
|
add.f32 %f861, %f859, 0f3F800000;
|
|
selp.f32 %f862, %f861, %f859, %p135;
|
|
selp.f32 %f863, %f860, %f857, %p135;
|
|
add.f32 %f864, %f863, 0fBF800000;
|
|
add.f32 %f865, %f863, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f866, %f865;
|
|
add.f32 %f867, %f864, %f864;
|
|
mul.f32 %f868, %f867, %f866;
|
|
mul.f32 %f869, %f868, %f868;
|
|
mov.f32 %f870, 0f3C4CAF63;
|
|
mov.f32 %f871, 0f3B18F0FE;
|
|
fma.rn.f32 %f872, %f871, %f869, %f870;
|
|
mov.f32 %f873, 0f3DAAAABD;
|
|
fma.rn.f32 %f874, %f872, %f869, %f873;
|
|
mul.rn.f32 %f875, %f874, %f869;
|
|
mul.rn.f32 %f876, %f875, %f868;
|
|
sub.f32 %f877, %f864, %f868;
|
|
add.f32 %f878, %f877, %f877;
|
|
neg.f32 %f879, %f868;
|
|
fma.rn.f32 %f880, %f879, %f864, %f878;
|
|
mul.rn.f32 %f881, %f866, %f880;
|
|
add.f32 %f882, %f876, %f868;
|
|
sub.f32 %f883, %f868, %f882;
|
|
add.f32 %f884, %f876, %f883;
|
|
add.f32 %f885, %f881, %f884;
|
|
add.f32 %f886, %f882, %f885;
|
|
sub.f32 %f887, %f882, %f886;
|
|
add.f32 %f888, %f885, %f887;
|
|
mov.f32 %f889, 0f3F317200;
|
|
mul.rn.f32 %f890, %f862, %f889;
|
|
mov.f32 %f891, 0f35BFBE8E;
|
|
mul.rn.f32 %f892, %f862, %f891;
|
|
add.f32 %f893, %f890, %f886;
|
|
sub.f32 %f894, %f890, %f893;
|
|
add.f32 %f895, %f886, %f894;
|
|
add.f32 %f896, %f888, %f895;
|
|
add.f32 %f897, %f892, %f896;
|
|
add.f32 %f898, %f893, %f897;
|
|
sub.f32 %f899, %f893, %f898;
|
|
add.f32 %f900, %f897, %f899;
|
|
mov.f32 %f901, 0f3ED55555;
|
|
mul.rn.f32 %f902, %f901, %f898;
|
|
neg.f32 %f903, %f902;
|
|
fma.rn.f32 %f904, %f901, %f898, %f903;
|
|
fma.rn.f32 %f905, %f901, %f900, %f904;
|
|
mov.f32 %f906, 0f00000000;
|
|
fma.rn.f32 %f907, %f906, %f898, %f905;
|
|
add.rn.f32 %f908, %f902, %f907;
|
|
neg.f32 %f909, %f908;
|
|
add.rn.f32 %f910, %f902, %f909;
|
|
add.rn.f32 %f911, %f910, %f907;
|
|
mov.b32 %r303, %f908;
|
|
setp.eq.s32 %p136, %r303, 1118925336;
|
|
add.s32 %r304, %r303, -1;
|
|
mov.b32 %f912, %r304;
|
|
add.f32 %f913, %f911, 0f37000000;
|
|
selp.f32 %f154, %f913, %f911, %p136;
|
|
selp.f32 %f914, %f912, %f908, %p136;
|
|
mov.f32 %f915, 0f3FB8AA3B;
|
|
mul.rn.f32 %f916, %f914, %f915;
|
|
cvt.rzi.f32.f32 %f917, %f916;
|
|
abs.f32 %f918, %f917;
|
|
setp.gt.f32 %p137, %f918, 0f42FC0000;
|
|
mov.b32 %r305, %f917;
|
|
and.b32 %r306, %r305, -2147483648;
|
|
or.b32 %r307, %r306, 1123811328;
|
|
mov.b32 %f919, %r307;
|
|
selp.f32 %f920, %f919, %f917, %p137;
|
|
mov.f32 %f921, 0fBF317218;
|
|
fma.rn.f32 %f922, %f920, %f921, %f914;
|
|
mov.f32 %f923, 0f3102E308;
|
|
fma.rn.f32 %f924, %f920, %f923, %f922;
|
|
mul.f32 %f925, %f924, 0f3FB8AA3B;
|
|
add.f32 %f926, %f920, 0f4B40007F;
|
|
mov.b32 %r308, %f926;
|
|
shl.b32 %r309, %r308, 23;
|
|
mov.b32 %f927, %r309;
|
|
ex2.approx.ftz.f32 %f928, %f925;
|
|
mul.f32 %f155, %f928, %f927;
|
|
setp.eq.f32 %p138, %f155, 0f7F800000;
|
|
mov.f32 %f1151, 0f7F800000;
|
|
@%p138 bra $L__BB0_113;
|
|
|
|
fma.rn.f32 %f1151, %f155, %f154, %f155;
|
|
|
|
$L__BB0_113:
|
|
setp.lt.f32 %p139, %f129, 0f00000000;
|
|
and.pred %p7, %p139, %p112;
|
|
setp.eq.f32 %p141, %f129, 0f00000000;
|
|
@%p141 bra $L__BB0_117;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f933, %f129, %f129;
|
|
selp.f32 %f1153, %f933, 0f00000000, %p112;
|
|
bra.uni $L__BB0_118;
|
|
|
|
$L__BB0_114:
|
|
mov.b32 %r310, %f1151;
|
|
xor.b32 %r311, %r310, -2147483648;
|
|
mov.b32 %f929, %r311;
|
|
selp.f32 %f1153, %f929, %f1151, %p7;
|
|
setp.geu.f32 %p142, %f129, 0f00000000;
|
|
@%p142 bra $L__BB0_118;
|
|
|
|
mov.f32 %f930, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f931, %f930;
|
|
setp.eq.f32 %p143, %f931, 0f3ED55555;
|
|
@%p143 bra $L__BB0_118;
|
|
|
|
mov.f32 %f1153, 0f7FFFFFFF;
|
|
|
|
$L__BB0_118:
|
|
mov.f32 %f1105, 0f00000000;
|
|
max.f32 %f1104, %f1105, %f686;
|
|
abs.f32 %f1103, %f1104;
|
|
add.f32 %f934, %f1103, 0f3ED55555;
|
|
mov.b32 %r312, %f934;
|
|
setp.lt.s32 %p145, %r312, 2139095040;
|
|
@%p145 bra $L__BB0_123;
|
|
|
|
mov.f32 %f1108, 0f00000000;
|
|
max.f32 %f1107, %f1108, %f686;
|
|
abs.f32 %f1106, %f1107;
|
|
setp.gtu.f32 %p146, %f1106, 0f7F800000;
|
|
@%p146 bra $L__BB0_122;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1153, %f129, 0f3ED55555;
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_120:
|
|
mov.f32 %f1111, 0f00000000;
|
|
max.f32 %f1110, %f1111, %f686;
|
|
abs.f32 %f1109, %f1110;
|
|
setp.neu.f32 %p147, %f1109, 0f7F800000;
|
|
@%p147 bra $L__BB0_123;
|
|
|
|
selp.f32 %f1153, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd112, [params+144];
|
|
cvta.to.global.u64 %rd111, %rd112;
|
|
ld.const.u32 %r351, [params+136];
|
|
mad.lo.s32 %r350, %r351, %r4, %r3;
|
|
cvt.u64.u32 %rd110, %r350;
|
|
fma.rn.f32 %f935, %f1147, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p148, %f127, 0f3F800000;
|
|
mov.f32 %f936, 0f3F800000;
|
|
selp.f32 %f937, 0f3F7FFFFF, %f935, %p148;
|
|
mul.f32 %f938, %f127, 0f414EB852;
|
|
setp.lt.f32 %p149, %f127, 0f3B4D2E1C;
|
|
selp.f32 %f939, %f938, %f937, %p149;
|
|
fma.rn.f32 %f940, %f1150, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p150, %f128, 0f3F800000;
|
|
selp.f32 %f941, 0f3F7FFFFF, %f940, %p150;
|
|
mul.f32 %f942, %f128, 0f414EB852;
|
|
setp.lt.f32 %p151, %f128, 0f3B4D2E1C;
|
|
selp.f32 %f943, %f942, %f941, %p151;
|
|
fma.rn.f32 %f944, %f1153, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p152, %f129, 0f3F800000;
|
|
selp.f32 %f945, 0f3F7FFFFF, %f944, %p152;
|
|
mul.f32 %f946, %f129, 0f414EB852;
|
|
setp.lt.f32 %p153, %f129, 0f3B4D2E1C;
|
|
selp.f32 %f947, %f946, %f945, %p153;
|
|
min.f32 %f948, %f939, %f936;
|
|
mov.f32 %f949, 0f00000000;
|
|
max.f32 %f950, %f949, %f948;
|
|
mul.f32 %f951, %f950, 0f43800000;
|
|
cvt.rzi.u32.f32 %r313, %f951;
|
|
min.u32 %r314, %r313, 255;
|
|
min.f32 %f952, %f943, %f936;
|
|
max.f32 %f953, %f949, %f952;
|
|
mul.f32 %f954, %f953, 0f43800000;
|
|
cvt.rzi.u32.f32 %r315, %f954;
|
|
min.u32 %r316, %r315, 255;
|
|
min.f32 %f955, %f947, %f936;
|
|
max.f32 %f956, %f949, %f955;
|
|
mul.f32 %f957, %f956, 0f43800000;
|
|
cvt.rzi.u32.f32 %r317, %f957;
|
|
min.u32 %r318, %r317, 255;
|
|
shl.b64 %rd70, %rd110, 2;
|
|
add.s64 %rd71, %rd111, %rd70;
|
|
cvt.u16.u32 %rs19, %r318;
|
|
cvt.u16.u32 %rs20, %r316;
|
|
cvt.u16.u32 %rs21, %r314;
|
|
mov.u16 %rs22, 255;
|
|
st.global.v4.u8 [%rd71], {%rs21, %rs20, %rs19, %rs22};
|
|
|
|
$L__BB0_124:
|
|
ld.const.u32 %r352, [params+104];
|
|
and.b32 %r319, %r352, 4;
|
|
setp.eq.s32 %p154, %r319, 0;
|
|
ld.const.u32 %r367, [params+108];
|
|
@%p154 bra $L__BB0_128;
|
|
|
|
setp.eq.s32 %p155, %r367, 0;
|
|
ld.const.u64 %rd72, [params+224];
|
|
cvta.to.global.u64 %rd73, %rd72;
|
|
ld.const.u32 %r320, [params+216];
|
|
mad.lo.s32 %r321, %r320, %r4, %r3;
|
|
mul.wide.u32 %rd74, %r321, 8;
|
|
add.s64 %rd20, %rd73, %rd74;
|
|
@%p155 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs30, %rs31, %rs32, %rs33}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f958, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f959, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f960, %rs32;}
|
|
|
|
// end inline asm
|
|
add.f32 %f961, %f73, %f958;
|
|
add.f32 %f962, %f74, %f959;
|
|
add.f32 %f963, %f75, %f960;
|
|
mov.f32 %f964, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f963;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f962;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f961;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f964;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs26, %rs27, %rs28, %rs29};
|
|
bra.uni $L__BB0_128;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f968, 0f3F800000;
|
|
mov.u32 %r367, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f968;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f73;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs34, %rs35, %rs36, %rs37};
|
|
|
|
$L__BB0_128:
|
|
ld.const.u64 %rd75, [params+256];
|
|
cvta.to.global.u64 %rd76, %rd75;
|
|
ld.const.u32 %r323, [params+248];
|
|
mad.lo.s32 %r324, %r323, %r4, %r3;
|
|
mul.wide.u32 %rd77, %r324, 8;
|
|
add.s64 %rd21, %rd76, %rd77;
|
|
setp.eq.s32 %p156, %r367, 0;
|
|
@%p156 bra $L__BB0_130;
|
|
|
|
ld.global.v4.u16 {%rs45, %rs46, %rs47, %rs48}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f969, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f970, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f971, %rs47;}
|
|
|
|
// end inline asm
|
|
add.f32 %f972, %f76, %f969;
|
|
add.f32 %f973, %f77, %f970;
|
|
add.f32 %f974, %f78, %f971;
|
|
mov.f32 %f975, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f974;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f973;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f972;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f975;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs41, %rs42, %rs43, %rs44};
|
|
bra.uni $L__BB0_131;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f979, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f979;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f78;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f77;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f76;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs49, %rs50, %rs51, %rs52};
|
|
|
|
$L__BB0_131:
|
|
mul.f32 %f980, %f187, 0f3F000000;
|
|
mov.f32 %f981, 0f3F000000;
|
|
sub.f32 %f164, %f981, %f980;
|
|
mul.f32 %f982, %f188, 0f3F000000;
|
|
sub.f32 %f165, %f981, %f982;
|
|
mul.f32 %f983, %f189, 0f3F000000;
|
|
sub.f32 %f166, %f981, %f983;
|
|
ld.const.u64 %rd78, [params+272];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r325, [params+264];
|
|
mad.lo.s32 %r326, %r325, %r4, %r3;
|
|
mul.wide.u32 %rd80, %r326, 8;
|
|
add.s64 %rd22, %rd79, %rd80;
|
|
@%p156 bra $L__BB0_133;
|
|
|
|
ld.global.v4.u16 {%rs60, %rs61, %rs62, %rs63}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f984, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f985, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f986, %rs62;}
|
|
|
|
// end inline asm
|
|
add.f32 %f987, %f164, %f984;
|
|
add.f32 %f988, %f164, %f985;
|
|
add.f32 %f989, %f164, %f986;
|
|
mov.f32 %f990, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f989;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f988;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f987;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f990;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs56, %rs57, %rs58, %rs59};
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_133:
|
|
mov.f32 %f994, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f994;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f164;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs64, %rs65, %rs66, %rs67};
|
|
|
|
$L__BB0_134:
|
|
ld.const.u64 %rd81, [params+288];
|
|
cvta.to.global.u64 %rd82, %rd81;
|
|
ld.const.u32 %r327, [params+280];
|
|
mad.lo.s32 %r328, %r327, %r4, %r3;
|
|
mul.wide.u32 %rd83, %r328, 8;
|
|
add.s64 %rd23, %rd82, %rd83;
|
|
@%p156 bra $L__BB0_136;
|
|
|
|
ld.global.v4.u16 {%rs75, %rs76, %rs77, %rs78}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f995, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f996, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f997, %rs77;}
|
|
|
|
// end inline asm
|
|
add.f32 %f998, %f165, %f995;
|
|
add.f32 %f999, %f165, %f996;
|
|
add.f32 %f1000, %f165, %f997;
|
|
mov.f32 %f1001, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1000;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f999;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f998;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f1001;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs71, %rs72, %rs73, %rs74};
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1005, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1005;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f165;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs79, %rs80, %rs81, %rs82};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd84, [params+304];
|
|
cvta.to.global.u64 %rd85, %rd84;
|
|
ld.const.u32 %r329, [params+296];
|
|
mad.lo.s32 %r330, %r329, %r4, %r3;
|
|
mul.wide.u32 %rd86, %r330, 8;
|
|
add.s64 %rd24, %rd85, %rd86;
|
|
@%p156 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs90, %rs91, %rs92, %rs93}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1006, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1007, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1008, %rs92;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1009, %f166, %f1006;
|
|
add.f32 %f1010, %f166, %f1007;
|
|
add.f32 %f1011, %f166, %f1008;
|
|
mov.f32 %f1012, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1011;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1009;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f1012;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs86, %rs87, %rs88, %rs89};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1016, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1016;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f166;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs94, %rs95, %rs96, %rs97};
|
|
|
|
$L__BB0_160:
|
|
ret;
|
|
|
|
}
|
|
|