2271 lines
62 KiB
Plaintext
2271 lines
62 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<159>;
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.reg .b16 %rs<175>;
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.reg .f32 %f<1189>;
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.reg .b32 %r<353>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<105>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r55), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r56), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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ld.const.u64 %rd27, [params+400];
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cvta.to.global.u64 %rd28, %rd27;
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ld.const.u32 %r61, [params+392];
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mad.lo.s32 %r62, %r61, %r56, %r55;
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mul.wide.u32 %rd29, %r62, 4;
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add.s64 %rd2, %rd28, %rd29;
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ld.global.v2.u8 {%rs16, %rs170}, [%rd2];
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or.b16 %rs18, %rs16, %rs170;
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and.b16 %rs19, %rs18, 255;
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setp.eq.s16 %p7, %rs19, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs169, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs169, [%rd2+2];
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setp.eq.s16 %p8, %rs169, 0;
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mov.f32 %f1137, 0f00000000;
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mov.u16 %rs170, 0;
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mov.f32 %f1138, %f1137;
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mov.f32 %f1139, %f1137;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f199, %rs16;
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div.rn.f32 %f200, %f199, 0f437F0000;
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fma.rn.f32 %f201, %f200, 0f40000000, 0fBF800000;
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and.b16 %rs22, %rs170, 255;
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cvt.rn.f32.u16 %f202, %rs22;
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div.rn.f32 %f203, %f202, 0f437F0000;
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fma.rn.f32 %f204, %f203, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f205, %rs169;
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div.rn.f32 %f206, %f205, 0f437F0000;
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fma.rn.f32 %f207, %f206, 0f40000000, 0fBF800000;
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mul.f32 %f208, %f204, %f204;
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fma.rn.f32 %f209, %f201, %f201, %f208;
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fma.rn.f32 %f210, %f207, %f207, %f209;
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sqrt.rn.f32 %f211, %f210;
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rcp.rn.f32 %f212, %f211;
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mul.f32 %f1139, %f212, %f207;
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mul.f32 %f1138, %f212, %f204;
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mul.f32 %f1137, %f201, %f212;
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$L__BB0_4:
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ld.const.v2.u32 {%r63, %r64}, [params];
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add.s32 %r4, %r63, %r55;
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add.s32 %r5, %r64, %r56;
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setp.eq.f32 %p9, %f1137, 0f00000000;
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setp.eq.f32 %p10, %f1138, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1139, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_131;
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bra.uni $L__BB0_5;
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$L__BB0_131:
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ld.const.u32 %r52, [params+104];
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and.b32 %r314, %r52, 1;
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setp.eq.b32 %p149, %r314, 1;
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mov.pred %p150, 0;
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xor.pred %p151, %p149, %p150;
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not.pred %p152, %p151;
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@%p152 bra $L__BB0_133;
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ld.const.u64 %rd81, [params+144];
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cvta.to.global.u64 %rd82, %rd81;
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ld.const.u32 %r315, [params+136];
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mad.lo.s32 %r316, %r315, %r5, %r4;
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mul.wide.u32 %rd83, %r316, 4;
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add.s64 %rd84, %rd82, %rd83;
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mov.u16 %rs108, 0;
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st.global.v4.u8 [%rd84], {%rs108, %rs108, %rs108, %rs108};
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$L__BB0_133:
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and.b32 %r317, %r52, 4;
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setp.eq.s32 %p153, %r317, 0;
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ld.const.u32 %r352, [params+108];
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@%p153 bra $L__BB0_137;
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setp.eq.s32 %p154, %r352, 0;
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ld.const.u64 %rd85, [params+224];
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cvta.to.global.u64 %rd86, %rd85;
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ld.const.u32 %r318, [params+216];
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mad.lo.s32 %r319, %r318, %r5, %r4;
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mul.wide.u32 %rd87, %r319, 8;
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add.s64 %rd22, %rd86, %rd87;
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@%p154 bra $L__BB0_136;
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ld.global.v4.u16 {%rs115, %rs116, %rs117, %rs118}, [%rd22];
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// begin inline asm
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{ cvt.f32.f16 %f1039, %rs115;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1040, %rs116;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1041, %rs117;}
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// end inline asm
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add.f32 %f1042, %f1039, 0f00000000;
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add.f32 %f1043, %f1040, 0f00000000;
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add.f32 %f1044, %f1041, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs114, %f1044;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs113, %f1043;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs112, %f1042;}
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// end inline asm
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mov.u16 %rs119, 0;
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st.global.v4.u16 [%rd22], {%rs112, %rs113, %rs114, %rs119};
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bra.uni $L__BB0_137;
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$L__BB0_5:
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ld.const.u64 %rd30, [params+432];
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cvta.to.global.u64 %rd31, %rd30;
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ld.const.u32 %r67, [params+424];
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mad.lo.s32 %r68, %r67, %r56, %r55;
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mul.wide.u32 %rd32, %r68, 12;
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add.s64 %rd33, %rd31, %rd32;
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ld.global.f32 %f213, [%rd33];
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mul.f32 %f214, %f213, 0f3456BF95;
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ld.global.f32 %f215, [%rd33+4];
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mul.f32 %f216, %f215, 0f3456BF95;
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ld.global.f32 %f217, [%rd33+8];
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mul.f32 %f218, %f217, 0f3456BF95;
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abs.f32 %f219, %f1137;
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div.rn.f32 %f220, %f214, %f219;
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abs.f32 %f221, %f1138;
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div.rn.f32 %f222, %f216, %f221;
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abs.f32 %f223, %f1139;
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div.rn.f32 %f224, %f218, %f223;
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abs.f32 %f225, %f220;
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abs.f32 %f226, %f222;
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abs.f32 %f227, %f224;
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mov.f32 %f228, 0f38D1B717;
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max.f32 %f229, %f225, %f228;
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max.f32 %f230, %f226, %f228;
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max.f32 %f231, %f227, %f228;
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fma.rn.f32 %f10, %f1137, %f229, %f213;
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fma.rn.f32 %f11, %f1138, %f230, %f215;
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fma.rn.f32 %f12, %f1139, %f231, %f217;
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ld.const.u32 %r6, [params+588];
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setp.gt.f32 %p14, %f219, %f223;
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neg.f32 %f232, %f1138;
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selp.f32 %f233, %f232, 0f00000000, %p14;
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neg.f32 %f234, %f1139;
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selp.f32 %f235, %f1137, %f234, %p14;
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selp.f32 %f236, 0f00000000, %f1138, %p14;
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mul.f32 %f237, %f235, %f235;
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fma.rn.f32 %f238, %f233, %f233, %f237;
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fma.rn.f32 %f239, %f236, %f236, %f238;
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sqrt.rn.f32 %f240, %f239;
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rcp.rn.f32 %f241, %f240;
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mul.f32 %f13, %f233, %f241;
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mul.f32 %f14, %f235, %f241;
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mul.f32 %f15, %f236, %f241;
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ld.const.u64 %rd34, [params+128];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r69, [params+120];
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mad.lo.s32 %r70, %r69, %r56, %r55;
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mul.wide.u32 %rd36, %r70, 4;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.u32 %r343, [%rd37];
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ld.const.u64 %rd38, [params+464];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r71, [params+456];
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mad.lo.s32 %r72, %r71, %r56, %r55;
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mul.wide.u32 %rd40, %r72, 4;
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add.s64 %rd3, %rd39, %rd40;
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ld.global.v2.u8 {%rs24, %rs173}, [%rd3];
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or.b16 %rs26, %rs24, %rs173;
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and.b16 %rs27, %rs26, 255;
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setp.eq.s16 %p15, %rs27, 0;
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@%p15 bra $L__BB0_7;
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ld.global.u8 %rs171, [%rd3+2];
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bra.uni $L__BB0_8;
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$L__BB0_7:
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ld.global.u8 %rs171, [%rd3+2];
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setp.eq.s16 %p16, %rs171, 0;
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mov.f32 %f1140, 0f00000000;
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mov.u16 %rs173, 0;
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mov.u16 %rs174, %rs173;
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mov.f32 %f1141, %f1140;
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mov.f32 %f1142, %f1140;
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@%p16 bra $L__BB0_9;
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$L__BB0_8:
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mov.u16 %rs174, %rs173;
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cvt.rn.f32.u16 %f245, %rs24;
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div.rn.f32 %f246, %f245, 0f437F0000;
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fma.rn.f32 %f247, %f246, 0f40000000, 0fBF800000;
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and.b16 %rs32, %rs174, 255;
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cvt.rn.f32.u16 %f248, %rs32;
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div.rn.f32 %f249, %f248, 0f437F0000;
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fma.rn.f32 %f250, %f249, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f251, %rs171;
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div.rn.f32 %f252, %f251, 0f437F0000;
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fma.rn.f32 %f253, %f252, 0f40000000, 0fBF800000;
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mul.f32 %f254, %f250, %f250;
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fma.rn.f32 %f255, %f247, %f247, %f254;
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fma.rn.f32 %f256, %f253, %f253, %f255;
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sqrt.rn.f32 %f257, %f256;
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rcp.rn.f32 %f258, %f257;
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mul.f32 %f1142, %f258, %f253;
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mul.f32 %f1141, %f258, %f250;
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mul.f32 %f1140, %f247, %f258;
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mov.u16 %rs173, %rs171;
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$L__BB0_9:
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mul.f32 %f262, %f1138, %f1142;
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mul.f32 %f263, %f1139, %f1141;
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sub.f32 %f264, %f262, %f263;
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mul.f32 %f265, %f1139, %f1140;
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mul.f32 %f266, %f1137, %f1142;
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sub.f32 %f267, %f265, %f266;
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mul.f32 %f268, %f1137, %f1141;
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mul.f32 %f269, %f1138, %f1140;
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sub.f32 %f270, %f268, %f269;
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ld.global.u8 %rs34, [%rd3+3];
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setp.eq.s16 %p17, %rs34, 0;
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selp.f32 %f22, 0fBF800000, 0f3F800000, %p17;
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mul.f32 %f271, %f264, %f22;
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mul.f32 %f272, %f267, %f22;
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mul.f32 %f273, %f270, %f22;
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mul.f32 %f274, %f271, 0f00000000;
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mul.f32 %f275, %f272, 0f00000000;
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mul.f32 %f276, %f273, 0f00000000;
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fma.rn.f32 %f277, %f1140, 0f3F5105EC, %f274;
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fma.rn.f32 %f278, %f1141, 0f3F5105EC, %f275;
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fma.rn.f32 %f279, %f1142, 0f3F5105EC, %f276;
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mul.f32 %f23, %f1137, 0f3F13CD3A;
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add.f32 %f24, %f23, %f277;
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mul.f32 %f25, %f1138, 0f3F13CD3A;
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add.f32 %f26, %f25, %f278;
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mul.f32 %f27, %f1139, 0f3F13CD3A;
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add.f32 %f28, %f27, %f279;
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or.b16 %rs35, %rs24, %rs174;
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or.b16 %rs15, %rs35, %rs173;
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and.b16 %rs36, %rs15, 255;
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setp.eq.s16 %p18, %rs36, 0;
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mov.f32 %f1146, 0f00000000;
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mov.f32 %f1143, %f1146;
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mov.f32 %f1144, %f1146;
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mov.f32 %f1145, %f1146;
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@%p18 bra $L__BB0_11;
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cvt.rn.f32.u16 %f280, %rs24;
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div.rn.f32 %f281, %f280, 0f437F0000;
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fma.rn.f32 %f282, %f281, 0f40000000, 0fBF800000;
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and.b16 %rs38, %rs174, 255;
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cvt.rn.f32.u16 %f283, %rs38;
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div.rn.f32 %f284, %f283, 0f437F0000;
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fma.rn.f32 %f285, %f284, 0f40000000, 0fBF800000;
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and.b16 %rs39, %rs173, 255;
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cvt.rn.f32.u16 %f286, %rs39;
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div.rn.f32 %f287, %f286, 0f437F0000;
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fma.rn.f32 %f288, %f287, 0f40000000, 0fBF800000;
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mul.f32 %f289, %f285, %f285;
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fma.rn.f32 %f290, %f282, %f282, %f289;
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fma.rn.f32 %f291, %f288, %f288, %f290;
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sqrt.rn.f32 %f292, %f291;
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rcp.rn.f32 %f293, %f292;
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mul.f32 %f1145, %f293, %f288;
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mul.f32 %f1144, %f293, %f285;
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mul.f32 %f1143, %f282, %f293;
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$L__BB0_11:
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mul.f32 %f297, %f1138, %f1145;
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mul.f32 %f298, %f1139, %f1144;
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sub.f32 %f299, %f297, %f298;
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mul.f32 %f300, %f1139, %f1143;
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mul.f32 %f301, %f1137, %f1145;
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sub.f32 %f302, %f300, %f301;
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mul.f32 %f303, %f1137, %f1144;
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mul.f32 %f304, %f1138, %f1143;
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sub.f32 %f305, %f303, %f304;
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mul.f32 %f306, %f299, %f22;
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mul.f32 %f307, %f302, %f22;
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mul.f32 %f308, %f305, %f22;
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mul.f32 %f309, %f1143, 0f3ED105EC;
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mul.f32 %f310, %f1144, 0f3ED105EC;
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mul.f32 %f311, %f1145, 0f3ED105EC;
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mul.f32 %f312, %f306, 0f3F3504F3;
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mul.f32 %f313, %f307, 0f3F3504F3;
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mul.f32 %f314, %f308, 0f3F3504F3;
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sub.f32 %f315, %f312, %f309;
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sub.f32 %f316, %f313, %f310;
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sub.f32 %f317, %f314, %f311;
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add.f32 %f35, %f23, %f315;
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add.f32 %f36, %f25, %f316;
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add.f32 %f37, %f27, %f317;
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mov.f32 %f1147, %f1146;
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mov.f32 %f1148, %f1146;
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@%p18 bra $L__BB0_13;
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cvt.rn.f32.u16 %f318, %rs24;
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div.rn.f32 %f319, %f318, 0f437F0000;
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fma.rn.f32 %f320, %f319, 0f40000000, 0fBF800000;
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and.b16 %rs42, %rs174, 255;
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cvt.rn.f32.u16 %f321, %rs42;
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div.rn.f32 %f322, %f321, 0f437F0000;
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fma.rn.f32 %f323, %f322, 0f40000000, 0fBF800000;
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and.b16 %rs43, %rs173, 255;
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cvt.rn.f32.u16 %f324, %rs43;
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div.rn.f32 %f325, %f324, 0f437F0000;
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fma.rn.f32 %f326, %f325, 0f40000000, 0fBF800000;
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mul.f32 %f327, %f323, %f323;
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fma.rn.f32 %f328, %f320, %f320, %f327;
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fma.rn.f32 %f329, %f326, %f326, %f328;
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sqrt.rn.f32 %f330, %f329;
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rcp.rn.f32 %f331, %f330;
|
|
mul.f32 %f1148, %f331, %f326;
|
|
mul.f32 %f1147, %f331, %f323;
|
|
mul.f32 %f1146, %f320, %f331;
|
|
|
|
$L__BB0_13:
|
|
mul.f32 %f336, %f1138, %f1148;
|
|
mul.f32 %f337, %f1139, %f1147;
|
|
sub.f32 %f338, %f336, %f337;
|
|
mul.f32 %f339, %f1139, %f1146;
|
|
mul.f32 %f340, %f1137, %f1148;
|
|
sub.f32 %f341, %f339, %f340;
|
|
mul.f32 %f342, %f1137, %f1147;
|
|
mul.f32 %f343, %f1138, %f1146;
|
|
sub.f32 %f344, %f342, %f343;
|
|
mul.f32 %f345, %f338, %f22;
|
|
mul.f32 %f346, %f341, %f22;
|
|
mul.f32 %f347, %f344, %f22;
|
|
mul.f32 %f348, %f1146, 0f3ED105EC;
|
|
mul.f32 %f349, %f1147, 0f3ED105EC;
|
|
mul.f32 %f350, %f1148, 0f3ED105EC;
|
|
mul.f32 %f351, %f345, 0fBF3504F3;
|
|
mul.f32 %f352, %f346, 0fBF3504F3;
|
|
mul.f32 %f353, %f347, 0fBF3504F3;
|
|
sub.f32 %f354, %f351, %f348;
|
|
sub.f32 %f355, %f352, %f349;
|
|
sub.f32 %f356, %f353, %f350;
|
|
add.f32 %f44, %f23, %f354;
|
|
add.f32 %f45, %f25, %f355;
|
|
add.f32 %f46, %f27, %f356;
|
|
setp.lt.s32 %p20, %r3, 1;
|
|
mov.f32 %f1163, 0f00000000;
|
|
mov.f32 %f1164, %f1163;
|
|
mov.f32 %f1165, %f1163;
|
|
mov.f32 %f1166, %f1163;
|
|
@%p20 bra $L__BB0_44;
|
|
|
|
cvt.rn.f32.s32 %f361, %r3;
|
|
rcp.rn.f32 %f47, %f361;
|
|
mul.f32 %f48, %f10, 0f3456BF95;
|
|
mul.f32 %f49, %f11, 0f3456BF95;
|
|
mul.f32 %f50, %f12, 0f3456BF95;
|
|
ld.const.u64 %rd4, [params+96];
|
|
mul.f32 %f362, %f1139, %f14;
|
|
mul.f32 %f363, %f1138, %f15;
|
|
sub.f32 %f51, %f362, %f363;
|
|
mul.f32 %f364, %f1137, %f15;
|
|
mul.f32 %f365, %f1139, %f13;
|
|
sub.f32 %f52, %f364, %f365;
|
|
mul.f32 %f366, %f1138, %f13;
|
|
mul.f32 %f367, %f1137, %f14;
|
|
sub.f32 %f53, %f366, %f367;
|
|
mov.u32 %r73, 0;
|
|
add.s64 %rd5, %rd1, 24;
|
|
mov.u64 %rd41, __cudart_i2opi_f;
|
|
abs.f32 %f430, %f48;
|
|
abs.f32 %f431, %f49;
|
|
max.f32 %f432, %f430, %f431;
|
|
abs.f32 %f433, %f50;
|
|
max.f32 %f434, %f432, %f433;
|
|
mov.u32 %r340, %r73;
|
|
|
|
$L__BB0_15:
|
|
mov.u32 %r342, %r73;
|
|
|
|
$L__BB0_16:
|
|
cvt.rn.f32.s32 %f1105, %r340;
|
|
mad.lo.s32 %r75, %r343, 1664525, 1013904223;
|
|
and.b32 %r76, %r75, 16777215;
|
|
cvt.rn.f32.u32 %f368, %r76;
|
|
fma.rn.f32 %f369, %f368, 0f33800000, %f1105;
|
|
mul.f32 %f63, %f47, %f369;
|
|
mad.lo.s32 %r343, %r75, 1664525, 1013904223;
|
|
and.b32 %r77, %r343, 16777215;
|
|
cvt.rn.f32.u32 %f370, %r77;
|
|
cvt.rn.f32.s32 %f371, %r342;
|
|
fma.rn.f32 %f372, %f370, 0f33800000, %f371;
|
|
mul.f32 %f373, %f47, %f372;
|
|
mul.f32 %f374, %f63, %f63;
|
|
mov.f32 %f375, 0f3F800000;
|
|
sub.f32 %f376, %f375, %f374;
|
|
mov.f32 %f377, 0f00000000;
|
|
max.f32 %f378, %f377, %f376;
|
|
sqrt.rn.f32 %f64, %f378;
|
|
mul.f32 %f65, %f373, 0f40C90FDB;
|
|
mul.f32 %f379, %f65, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r347, %f379;
|
|
cvt.rn.f32.s32 %f380, %r347;
|
|
mov.f32 %f381, 0fBFC90FDA;
|
|
fma.rn.f32 %f382, %f380, %f381, %f65;
|
|
mov.f32 %f383, 0fB3A22168;
|
|
fma.rn.f32 %f384, %f380, %f383, %f382;
|
|
mov.f32 %f385, 0fA7C234C5;
|
|
fma.rn.f32 %f1160, %f380, %f385, %f384;
|
|
abs.f32 %f67, %f65;
|
|
setp.ltu.f32 %p21, %f67, 0f47CE4780;
|
|
mov.f32 %f1157, %f1160;
|
|
@%p21 bra $L__BB0_24;
|
|
|
|
setp.eq.f32 %p22, %f67, 0f7F800000;
|
|
@%p22 bra $L__BB0_23;
|
|
bra.uni $L__BB0_18;
|
|
|
|
$L__BB0_23:
|
|
mov.f32 %f388, 0f00000000;
|
|
mul.rn.f32 %f1157, %f65, %f388;
|
|
mov.u32 %r347, 0;
|
|
bra.uni $L__BB0_24;
|
|
|
|
$L__BB0_18:
|
|
mov.b32 %r14, %f65;
|
|
bfe.u32 %r79, %r14, 23, 8;
|
|
mov.u64 %rd102, 0;
|
|
mov.u32 %r344, 0;
|
|
mov.u64 %rd100, %rd1;
|
|
mov.u64 %rd101, %rd41;
|
|
|
|
$L__BB0_19:
|
|
.pragma "nounroll";
|
|
mov.b32 %r332, %f65;
|
|
shl.b32 %r331, %r332, 8;
|
|
or.b32 %r330, %r331, -2147483648;
|
|
ld.global.nc.u32 %r81, [%rd101];
|
|
mad.wide.u32 %rd43, %r81, %r330, %rd102;
|
|
shr.u64 %rd102, %rd43, 32;
|
|
st.local.u32 [%rd100], %rd43;
|
|
add.s64 %rd101, %rd101, 4;
|
|
add.s64 %rd100, %rd100, 4;
|
|
add.s32 %r344, %r344, 1;
|
|
setp.ne.s32 %p23, %r344, 6;
|
|
@%p23 bra $L__BB0_19;
|
|
|
|
add.s32 %r337, %r79, -128;
|
|
mov.b32 %r336, %f65;
|
|
bfe.u32 %r335, %r336, 23, 8;
|
|
add.s32 %r334, %r335, -128;
|
|
shr.u32 %r333, %r334, 5;
|
|
st.local.u32 [%rd5], %rd102;
|
|
mov.u32 %r82, 4;
|
|
sub.s32 %r20, %r82, %r333;
|
|
mov.u32 %r83, 6;
|
|
sub.s32 %r84, %r83, %r333;
|
|
mul.wide.s32 %rd44, %r84, 4;
|
|
add.s64 %rd45, %rd1, %rd44;
|
|
ld.local.u32 %r345, [%rd45];
|
|
ld.local.u32 %r346, [%rd45+-4];
|
|
and.b32 %r23, %r334, 31;
|
|
setp.eq.s32 %p24, %r23, 0;
|
|
@%p24 bra $L__BB0_22;
|
|
|
|
mov.u32 %r85, 32;
|
|
sub.s32 %r86, %r85, %r23;
|
|
shr.u32 %r87, %r346, %r86;
|
|
shl.b32 %r88, %r345, %r23;
|
|
add.s32 %r345, %r87, %r88;
|
|
mul.wide.s32 %rd46, %r20, 4;
|
|
add.s64 %rd47, %rd1, %rd46;
|
|
ld.local.u32 %r89, [%rd47];
|
|
shr.u32 %r90, %r89, %r86;
|
|
shl.b32 %r91, %r346, %r23;
|
|
add.s32 %r346, %r90, %r91;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r338, %f65;
|
|
and.b32 %r92, %r338, -2147483648;
|
|
shr.u32 %r93, %r346, 30;
|
|
shl.b32 %r94, %r345, 2;
|
|
or.b32 %r95, %r93, %r94;
|
|
shr.u32 %r96, %r95, 31;
|
|
shr.u32 %r97, %r345, 30;
|
|
add.s32 %r98, %r96, %r97;
|
|
neg.s32 %r99, %r98;
|
|
setp.eq.s32 %p25, %r92, 0;
|
|
selp.b32 %r347, %r98, %r99, %p25;
|
|
setp.ne.s32 %p26, %r96, 0;
|
|
xor.b32 %r100, %r92, -2147483648;
|
|
selp.b32 %r101, %r100, %r92, %p26;
|
|
selp.b32 %r102, -1, 0, %p26;
|
|
xor.b32 %r103, %r95, %r102;
|
|
shl.b32 %r104, %r346, 2;
|
|
xor.b32 %r105, %r104, %r102;
|
|
cvt.u64.u32 %rd48, %r103;
|
|
cvt.u64.u32 %rd49, %r105;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f386, %fd2;
|
|
setp.eq.s32 %p27, %r101, 0;
|
|
neg.f32 %f387, %f386;
|
|
selp.f32 %f1157, %f386, %f387, %p27;
|
|
|
|
$L__BB0_24:
|
|
add.s32 %r30, %r347, 1;
|
|
and.b32 %r31, %r30, 1;
|
|
setp.eq.s32 %p28, %r31, 0;
|
|
selp.f32 %f71, %f1157, 0f3F800000, %p28;
|
|
mul.rn.f32 %f72, %f1157, %f1157;
|
|
mov.f32 %f1158, 0fB94D4153;
|
|
@%p28 bra $L__BB0_26;
|
|
|
|
mov.f32 %f390, 0fBAB607ED;
|
|
mov.f32 %f391, 0f37CBAC00;
|
|
fma.rn.f32 %f1158, %f391, %f72, %f390;
|
|
|
|
$L__BB0_26:
|
|
selp.f32 %f392, 0f3C0885E4, 0f3D2AAABB, %p28;
|
|
fma.rn.f32 %f393, %f1158, %f72, %f392;
|
|
selp.f32 %f394, 0fBE2AAAA8, 0fBEFFFFFF, %p28;
|
|
fma.rn.f32 %f395, %f393, %f72, %f394;
|
|
mov.f32 %f396, 0f00000000;
|
|
fma.rn.f32 %f397, %f72, %f71, %f396;
|
|
fma.rn.f32 %f1159, %f395, %f397, %f71;
|
|
and.b32 %r107, %r30, 2;
|
|
setp.eq.s32 %p30, %r107, 0;
|
|
@%p30 bra $L__BB0_28;
|
|
|
|
mov.f32 %f399, 0fBF800000;
|
|
fma.rn.f32 %f1159, %f1159, %f399, %f396;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f1106, %f65, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r350, %f1106;
|
|
setp.ltu.f32 %p158, %f67, 0f47CE4780;
|
|
@%p158 bra $L__BB0_36;
|
|
|
|
setp.eq.f32 %p32, %f67, 0f7F800000;
|
|
@%p32 bra $L__BB0_35;
|
|
bra.uni $L__BB0_30;
|
|
|
|
$L__BB0_35:
|
|
mov.f32 %f402, 0f00000000;
|
|
mul.rn.f32 %f1160, %f65, %f402;
|
|
mov.u32 %r350, 0;
|
|
bra.uni $L__BB0_36;
|
|
|
|
$L__BB0_30:
|
|
mov.b32 %r32, %f65;
|
|
bfe.u32 %r108, %r32, 23, 8;
|
|
add.s32 %r33, %r108, -128;
|
|
shl.b32 %r109, %r32, 8;
|
|
or.b32 %r34, %r109, -2147483648;
|
|
shr.u32 %r35, %r33, 5;
|
|
mov.u64 %rd103, 0;
|
|
mov.u64 %rd104, %rd103;
|
|
|
|
$L__BB0_31:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd103, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r110, [%rd55];
|
|
mad.wide.u32 %rd56, %r110, %r34, %rd104;
|
|
shr.u64 %rd104, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r111, %rd103;
|
|
add.s32 %r112, %r111, 1;
|
|
cvt.s64.s32 %rd103, %r112;
|
|
setp.ne.s32 %p33, %r112, 6;
|
|
@%p33 bra $L__BB0_31;
|
|
|
|
st.local.u32 [%rd5], %rd104;
|
|
mov.u32 %r113, 4;
|
|
sub.s32 %r36, %r113, %r35;
|
|
mov.u32 %r114, 6;
|
|
sub.s32 %r115, %r114, %r35;
|
|
mul.wide.s32 %rd58, %r115, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r348, [%rd59];
|
|
ld.local.u32 %r349, [%rd59+-4];
|
|
and.b32 %r39, %r33, 31;
|
|
setp.eq.s32 %p34, %r39, 0;
|
|
@%p34 bra $L__BB0_34;
|
|
|
|
mov.u32 %r116, 32;
|
|
sub.s32 %r117, %r116, %r39;
|
|
shr.u32 %r118, %r349, %r117;
|
|
shl.b32 %r119, %r348, %r39;
|
|
add.s32 %r348, %r118, %r119;
|
|
mul.wide.s32 %rd60, %r36, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r120, [%rd61];
|
|
shr.u32 %r121, %r120, %r117;
|
|
shl.b32 %r122, %r349, %r39;
|
|
add.s32 %r349, %r121, %r122;
|
|
|
|
$L__BB0_34:
|
|
and.b32 %r123, %r32, -2147483648;
|
|
shr.u32 %r124, %r349, 30;
|
|
shl.b32 %r125, %r348, 2;
|
|
or.b32 %r126, %r124, %r125;
|
|
shr.u32 %r127, %r126, 31;
|
|
shr.u32 %r128, %r348, 30;
|
|
add.s32 %r129, %r127, %r128;
|
|
neg.s32 %r130, %r129;
|
|
setp.eq.s32 %p35, %r123, 0;
|
|
selp.b32 %r350, %r129, %r130, %p35;
|
|
setp.ne.s32 %p36, %r127, 0;
|
|
xor.b32 %r131, %r123, -2147483648;
|
|
selp.b32 %r132, %r131, %r123, %p36;
|
|
selp.b32 %r133, -1, 0, %p36;
|
|
xor.b32 %r134, %r126, %r133;
|
|
shl.b32 %r135, %r349, 2;
|
|
xor.b32 %r136, %r135, %r133;
|
|
cvt.u64.u32 %rd62, %r134;
|
|
cvt.u64.u32 %rd63, %r136;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f400, %fd4;
|
|
setp.eq.s32 %p37, %r132, 0;
|
|
neg.f32 %f401, %f400;
|
|
selp.f32 %f1160, %f400, %f401, %p37;
|
|
|
|
$L__BB0_36:
|
|
mul.f32 %f81, %f64, %f1159;
|
|
and.b32 %r46, %r350, 1;
|
|
setp.eq.s32 %p38, %r46, 0;
|
|
selp.f32 %f82, %f1160, 0f3F800000, %p38;
|
|
mul.rn.f32 %f83, %f1160, %f1160;
|
|
mov.f32 %f1161, 0fB94D4153;
|
|
@%p38 bra $L__BB0_38;
|
|
|
|
mov.f32 %f404, 0fBAB607ED;
|
|
mov.f32 %f405, 0f37CBAC00;
|
|
fma.rn.f32 %f1161, %f405, %f83, %f404;
|
|
|
|
$L__BB0_38:
|
|
selp.f32 %f406, 0f3C0885E4, 0f3D2AAABB, %p38;
|
|
fma.rn.f32 %f407, %f1161, %f83, %f406;
|
|
selp.f32 %f408, 0fBE2AAAA8, 0fBEFFFFFF, %p38;
|
|
fma.rn.f32 %f409, %f407, %f83, %f408;
|
|
mov.f32 %f410, 0f00000000;
|
|
fma.rn.f32 %f411, %f83, %f82, %f410;
|
|
fma.rn.f32 %f1162, %f409, %f411, %f82;
|
|
and.b32 %r138, %r350, 2;
|
|
setp.eq.s32 %p40, %r138, 0;
|
|
@%p40 bra $L__BB0_40;
|
|
|
|
mov.f32 %f413, 0fBF800000;
|
|
fma.rn.f32 %f1162, %f1162, %f413, %f410;
|
|
|
|
$L__BB0_40:
|
|
mul.f32 %f414, %f64, %f1162;
|
|
mul.f32 %f415, %f13, %f414;
|
|
mul.f32 %f416, %f14, %f414;
|
|
mul.f32 %f417, %f15, %f414;
|
|
fma.rn.f32 %f418, %f51, %f81, %f415;
|
|
fma.rn.f32 %f419, %f52, %f81, %f416;
|
|
fma.rn.f32 %f420, %f53, %f81, %f417;
|
|
fma.rn.f32 %f89, %f1137, %f63, %f418;
|
|
fma.rn.f32 %f90, %f1138, %f63, %f419;
|
|
fma.rn.f32 %f91, %f1139, %f63, %f420;
|
|
setp.leu.f32 %p41, %f90, 0f00000000;
|
|
setp.ne.s32 %p42, %r6, 0;
|
|
and.pred %p43, %p42, %p41;
|
|
@%p43 bra $L__BB0_42;
|
|
|
|
mov.f32 %f435, 0f38D1B717;
|
|
max.f32 %f427, %f434, %f435;
|
|
mov.f32 %f428, 0f6C4ECB8F;
|
|
mov.f32 %f429, 0f00000000;
|
|
mov.u32 %r175, 2;
|
|
mov.u32 %r177, 1;
|
|
mov.u32 %r178, 1065353216;
|
|
mov.u32 %r209, 0;
|
|
// begin inline asm
|
|
call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd4,%f10,%f11,%f12,%f89,%f90,%f91,%f427,%f428,%f429,%r177,%r209,%r177,%r175,%r177,%r177,%r178,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
|
|
// end inline asm
|
|
mov.b32 %f436, %r139;
|
|
mul.f32 %f437, %f26, %f90;
|
|
fma.rn.f32 %f438, %f24, %f89, %f437;
|
|
fma.rn.f32 %f439, %f28, %f91, %f438;
|
|
cvt.sat.f32.f32 %f440, %f439;
|
|
fma.rn.f32 %f1163, %f440, %f436, %f1163;
|
|
mul.f32 %f441, %f36, %f90;
|
|
fma.rn.f32 %f442, %f35, %f89, %f441;
|
|
fma.rn.f32 %f443, %f37, %f91, %f442;
|
|
cvt.sat.f32.f32 %f444, %f443;
|
|
fma.rn.f32 %f1165, %f444, %f436, %f1165;
|
|
mul.f32 %f445, %f45, %f90;
|
|
fma.rn.f32 %f446, %f44, %f89, %f445;
|
|
fma.rn.f32 %f447, %f46, %f91, %f446;
|
|
cvt.sat.f32.f32 %f448, %f447;
|
|
fma.rn.f32 %f1166, %f448, %f436, %f1166;
|
|
mul.f32 %f449, %f1138, %f90;
|
|
fma.rn.f32 %f450, %f1137, %f89, %f449;
|
|
fma.rn.f32 %f451, %f1139, %f91, %f450;
|
|
cvt.sat.f32.f32 %f452, %f451;
|
|
fma.rn.f32 %f1164, %f452, %f436, %f1164;
|
|
|
|
$L__BB0_42:
|
|
add.s32 %r342, %r342, 1;
|
|
setp.lt.s32 %p44, %r342, %r3;
|
|
@%p44 bra $L__BB0_16;
|
|
|
|
add.s32 %r340, %r340, 1;
|
|
setp.lt.s32 %p45, %r340, %r3;
|
|
@%p45 bra $L__BB0_15;
|
|
|
|
$L__BB0_44:
|
|
mul.lo.s32 %r210, %r3, %r3;
|
|
cvt.rn.f32.s32 %f453, %r210;
|
|
div.rn.f32 %f454, %f1164, %f453;
|
|
div.rn.f32 %f104, %f1163, %f453;
|
|
div.rn.f32 %f105, %f1165, %f453;
|
|
div.rn.f32 %f106, %f1166, %f453;
|
|
add.f32 %f107, %f454, %f454;
|
|
ld.const.v4.f32 {%f455, %f456, %f457, %f458}, [params+576];
|
|
mul.f32 %f111, %f107, %f455;
|
|
mul.f32 %f112, %f107, %f456;
|
|
mul.f32 %f113, %f107, %f457;
|
|
ld.const.u32 %r49, [params+104];
|
|
and.b32 %r211, %r49, 1;
|
|
setp.eq.b32 %p46, %r211, 1;
|
|
mov.pred %p47, 0;
|
|
xor.pred %p48, %p46, %p47;
|
|
not.pred %p49, %p48;
|
|
@%p49 bra $L__BB0_118;
|
|
|
|
mov.f32 %f463, 0f3EE66666;
|
|
abs.f32 %f115, %f111;
|
|
setp.lt.f32 %p50, %f115, 0f00800000;
|
|
mul.f32 %f465, %f115, 0f4B800000;
|
|
selp.f32 %f466, %f465, %f115, %p50;
|
|
selp.f32 %f467, 0fC3170000, 0fC2FE0000, %p50;
|
|
mov.b32 %r212, %f466;
|
|
and.b32 %r213, %r212, 8388607;
|
|
or.b32 %r214, %r213, 1065353216;
|
|
mov.b32 %f468, %r214;
|
|
shr.u32 %r215, %r212, 23;
|
|
cvt.rn.f32.u32 %f469, %r215;
|
|
add.f32 %f470, %f467, %f469;
|
|
setp.gt.f32 %p51, %f468, 0f3FB504F3;
|
|
mul.f32 %f471, %f468, 0f3F000000;
|
|
add.f32 %f472, %f470, 0f3F800000;
|
|
selp.f32 %f473, %f472, %f470, %p51;
|
|
selp.f32 %f474, %f471, %f468, %p51;
|
|
add.f32 %f475, %f474, 0fBF800000;
|
|
add.f32 %f476, %f474, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f477, %f476;
|
|
add.f32 %f478, %f475, %f475;
|
|
mul.f32 %f479, %f478, %f477;
|
|
mul.f32 %f480, %f479, %f479;
|
|
mov.f32 %f481, 0f3C4CAF63;
|
|
mov.f32 %f482, 0f3B18F0FE;
|
|
fma.rn.f32 %f483, %f482, %f480, %f481;
|
|
mov.f32 %f484, 0f3DAAAABD;
|
|
fma.rn.f32 %f485, %f483, %f480, %f484;
|
|
mul.rn.f32 %f486, %f485, %f480;
|
|
mul.rn.f32 %f487, %f486, %f479;
|
|
sub.f32 %f488, %f475, %f479;
|
|
add.f32 %f489, %f488, %f488;
|
|
neg.f32 %f490, %f479;
|
|
fma.rn.f32 %f491, %f490, %f475, %f489;
|
|
mul.rn.f32 %f492, %f477, %f491;
|
|
add.f32 %f493, %f487, %f479;
|
|
sub.f32 %f494, %f479, %f493;
|
|
add.f32 %f495, %f487, %f494;
|
|
add.f32 %f496, %f492, %f495;
|
|
add.f32 %f497, %f493, %f496;
|
|
sub.f32 %f498, %f493, %f497;
|
|
add.f32 %f499, %f496, %f498;
|
|
mov.f32 %f500, 0f3F317200;
|
|
mul.rn.f32 %f501, %f473, %f500;
|
|
mov.f32 %f502, 0f35BFBE8E;
|
|
mul.rn.f32 %f503, %f473, %f502;
|
|
add.f32 %f504, %f501, %f497;
|
|
sub.f32 %f505, %f501, %f504;
|
|
add.f32 %f506, %f497, %f505;
|
|
add.f32 %f507, %f499, %f506;
|
|
add.f32 %f508, %f503, %f507;
|
|
add.f32 %f509, %f504, %f508;
|
|
sub.f32 %f510, %f504, %f509;
|
|
add.f32 %f511, %f508, %f510;
|
|
mul.rn.f32 %f512, %f463, %f509;
|
|
neg.f32 %f513, %f512;
|
|
fma.rn.f32 %f514, %f463, %f509, %f513;
|
|
fma.rn.f32 %f515, %f463, %f511, %f514;
|
|
mov.f32 %f516, 0f00000000;
|
|
fma.rn.f32 %f517, %f516, %f509, %f515;
|
|
add.rn.f32 %f518, %f512, %f517;
|
|
neg.f32 %f519, %f518;
|
|
add.rn.f32 %f520, %f512, %f519;
|
|
add.rn.f32 %f521, %f520, %f517;
|
|
mov.b32 %r216, %f518;
|
|
setp.eq.s32 %p52, %r216, 1118925336;
|
|
add.s32 %r217, %r216, -1;
|
|
mov.b32 %f522, %r217;
|
|
add.f32 %f523, %f521, 0f37000000;
|
|
selp.f32 %f116, %f523, %f521, %p52;
|
|
selp.f32 %f524, %f522, %f518, %p52;
|
|
mov.f32 %f525, 0f3FB8AA3B;
|
|
mul.rn.f32 %f526, %f524, %f525;
|
|
cvt.rzi.f32.f32 %f527, %f526;
|
|
abs.f32 %f528, %f527;
|
|
setp.gt.f32 %p53, %f528, 0f42FC0000;
|
|
mov.b32 %r218, %f527;
|
|
and.b32 %r219, %r218, -2147483648;
|
|
or.b32 %r220, %r219, 1123811328;
|
|
mov.b32 %f529, %r220;
|
|
selp.f32 %f530, %f529, %f527, %p53;
|
|
mov.f32 %f531, 0fBF317218;
|
|
fma.rn.f32 %f532, %f530, %f531, %f524;
|
|
mov.f32 %f533, 0f3102E308;
|
|
fma.rn.f32 %f534, %f530, %f533, %f532;
|
|
mul.f32 %f535, %f534, 0f3FB8AA3B;
|
|
add.f32 %f536, %f530, 0f4B40007F;
|
|
mov.b32 %r221, %f536;
|
|
shl.b32 %r222, %r221, 23;
|
|
mov.b32 %f537, %r222;
|
|
ex2.approx.ftz.f32 %f538, %f535;
|
|
mul.f32 %f117, %f538, %f537;
|
|
setp.eq.f32 %p54, %f117, 0f7F800000;
|
|
mov.f32 %f1171, 0f7F800000;
|
|
@%p54 bra $L__BB0_47;
|
|
|
|
fma.rn.f32 %f1171, %f117, %f116, %f117;
|
|
|
|
$L__BB0_47:
|
|
mov.f32 %f1112, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1111, %f1112;
|
|
add.f32 %f1110, %f1111, %f1111;
|
|
mov.f32 %f1109, 0f3EE66666;
|
|
sub.f32 %f1108, %f1109, %f1110;
|
|
abs.f32 %f1107, %f1108;
|
|
setp.lt.f32 %p55, %f111, 0f00000000;
|
|
setp.eq.f32 %p56, %f1107, 0f3F800000;
|
|
and.pred %p1, %p55, %p56;
|
|
setp.eq.f32 %p57, %f111, 0f00000000;
|
|
@%p57 bra $L__BB0_51;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_51:
|
|
add.f32 %f543, %f111, %f111;
|
|
selp.f32 %f1173, %f543, 0f00000000, %p56;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1047, 0f00000000;
|
|
mov.u32 %r352, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1047;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1047;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1047;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs123, 0;
|
|
st.global.v4.u16 [%rd22], {%rs120, %rs121, %rs122, %rs123};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd88, [params+256];
|
|
cvta.to.global.u64 %rd89, %rd88;
|
|
ld.const.u32 %r321, [params+248];
|
|
mad.lo.s32 %r322, %r321, %r5, %r4;
|
|
mul.wide.u32 %rd90, %r322, 8;
|
|
add.s64 %rd23, %rd89, %rd90;
|
|
setp.eq.s32 %p155, %r352, 0;
|
|
@%p155 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs130, %rs131, %rs132, %rs133}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1048, %rs130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1049, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1050, %rs132;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1051, %f1048, 0f00000000;
|
|
add.f32 %f1052, %f1049, 0f00000000;
|
|
add.f32 %f1053, %f1050, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1053;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1051;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs134, 0;
|
|
st.global.v4.u16 [%rd23], {%rs127, %rs128, %rs129, %rs134};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1056, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1056;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1056;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1056;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs138, 0;
|
|
st.global.v4.u16 [%rd23], {%rs135, %rs136, %rs137, %rs138};
|
|
|
|
$L__BB0_140:
|
|
ld.const.u64 %rd91, [params+272];
|
|
cvta.to.global.u64 %rd92, %rd91;
|
|
ld.const.u32 %r323, [params+264];
|
|
mad.lo.s32 %r324, %r323, %r5, %r4;
|
|
mul.wide.u32 %rd93, %r324, 8;
|
|
add.s64 %rd24, %rd92, %rd93;
|
|
@%p155 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs145, %rs146, %rs147, %rs148}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1057, %rs145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1058, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1059, %rs147;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1060, %f1057, 0f00000000;
|
|
add.f32 %f1061, %f1058, 0f00000000;
|
|
add.f32 %f1062, %f1059, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1062;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1061;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1060;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs149, 0;
|
|
st.global.v4.u16 [%rd24], {%rs142, %rs143, %rs144, %rs149};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1065, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1065;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1065;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1065;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs153, 0;
|
|
st.global.v4.u16 [%rd24], {%rs150, %rs151, %rs152, %rs153};
|
|
|
|
$L__BB0_143:
|
|
ld.const.u64 %rd94, [params+288];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r325, [params+280];
|
|
mad.lo.s32 %r326, %r325, %r5, %r4;
|
|
mul.wide.u32 %rd96, %r326, 8;
|
|
add.s64 %rd25, %rd95, %rd96;
|
|
@%p155 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs160, %rs161, %rs162, %rs163}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1066, %rs160;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1067, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1068, %rs162;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1069, %f1066, 0f00000000;
|
|
add.f32 %f1070, %f1067, 0f00000000;
|
|
add.f32 %f1071, %f1068, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1071;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1070;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1069;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs164, 0;
|
|
st.global.v4.u16 [%rd25], {%rs157, %rs158, %rs159, %rs164};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1074, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1074;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1074;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1074;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs168, 0;
|
|
st.global.v4.u16 [%rd25], {%rs165, %rs166, %rs167, %rs168};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_48:
|
|
mov.b32 %r223, %f1171;
|
|
xor.b32 %r224, %r223, -2147483648;
|
|
mov.b32 %f539, %r224;
|
|
selp.f32 %f1173, %f539, %f1171, %p1;
|
|
setp.geu.f32 %p58, %f111, 0f00000000;
|
|
@%p58 bra $L__BB0_52;
|
|
|
|
mov.f32 %f540, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f541, %f540;
|
|
setp.eq.f32 %p59, %f541, 0f3EE66666;
|
|
@%p59 bra $L__BB0_52;
|
|
|
|
mov.f32 %f1173, 0f7FFFFFFF;
|
|
|
|
$L__BB0_52:
|
|
add.f32 %f544, %f115, 0f3EE66666;
|
|
mov.b32 %r225, %f544;
|
|
setp.lt.s32 %p61, %r225, 2139095040;
|
|
@%p61 bra $L__BB0_57;
|
|
|
|
setp.gtu.f32 %p62, %f115, 0f7F800000;
|
|
@%p62 bra $L__BB0_56;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f1173, %f111, 0f3EE66666;
|
|
bra.uni $L__BB0_57;
|
|
|
|
$L__BB0_54:
|
|
setp.neu.f32 %p63, %f115, 0f7F800000;
|
|
@%p63 bra $L__BB0_57;
|
|
|
|
selp.f32 %f1173, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_57:
|
|
setp.eq.f32 %p64, %f111, 0f3F800000;
|
|
selp.f32 %f126, 0f3F800000, %f1173, %p64;
|
|
abs.f32 %f127, %f112;
|
|
setp.lt.f32 %p65, %f127, 0f00800000;
|
|
mul.f32 %f546, %f127, 0f4B800000;
|
|
selp.f32 %f547, %f546, %f127, %p65;
|
|
selp.f32 %f548, 0fC3170000, 0fC2FE0000, %p65;
|
|
mov.b32 %r226, %f547;
|
|
and.b32 %r227, %r226, 8388607;
|
|
or.b32 %r228, %r227, 1065353216;
|
|
mov.b32 %f549, %r228;
|
|
shr.u32 %r229, %r226, 23;
|
|
cvt.rn.f32.u32 %f550, %r229;
|
|
add.f32 %f551, %f548, %f550;
|
|
setp.gt.f32 %p66, %f549, 0f3FB504F3;
|
|
mul.f32 %f552, %f549, 0f3F000000;
|
|
add.f32 %f553, %f551, 0f3F800000;
|
|
selp.f32 %f554, %f553, %f551, %p66;
|
|
selp.f32 %f555, %f552, %f549, %p66;
|
|
add.f32 %f556, %f555, 0fBF800000;
|
|
add.f32 %f557, %f555, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f558, %f557;
|
|
add.f32 %f559, %f556, %f556;
|
|
mul.f32 %f560, %f559, %f558;
|
|
mul.f32 %f561, %f560, %f560;
|
|
mov.f32 %f562, 0f3C4CAF63;
|
|
mov.f32 %f563, 0f3B18F0FE;
|
|
fma.rn.f32 %f564, %f563, %f561, %f562;
|
|
mov.f32 %f565, 0f3DAAAABD;
|
|
fma.rn.f32 %f566, %f564, %f561, %f565;
|
|
mul.rn.f32 %f567, %f566, %f561;
|
|
mul.rn.f32 %f568, %f567, %f560;
|
|
sub.f32 %f569, %f556, %f560;
|
|
add.f32 %f570, %f569, %f569;
|
|
neg.f32 %f571, %f560;
|
|
fma.rn.f32 %f572, %f571, %f556, %f570;
|
|
mul.rn.f32 %f573, %f558, %f572;
|
|
add.f32 %f574, %f568, %f560;
|
|
sub.f32 %f575, %f560, %f574;
|
|
add.f32 %f576, %f568, %f575;
|
|
add.f32 %f577, %f573, %f576;
|
|
add.f32 %f578, %f574, %f577;
|
|
sub.f32 %f579, %f574, %f578;
|
|
add.f32 %f580, %f577, %f579;
|
|
mov.f32 %f581, 0f3F317200;
|
|
mul.rn.f32 %f582, %f554, %f581;
|
|
mov.f32 %f583, 0f35BFBE8E;
|
|
mul.rn.f32 %f584, %f554, %f583;
|
|
add.f32 %f585, %f582, %f578;
|
|
sub.f32 %f586, %f582, %f585;
|
|
add.f32 %f587, %f578, %f586;
|
|
add.f32 %f588, %f580, %f587;
|
|
add.f32 %f589, %f584, %f588;
|
|
add.f32 %f590, %f585, %f589;
|
|
sub.f32 %f591, %f585, %f590;
|
|
add.f32 %f592, %f589, %f591;
|
|
mov.f32 %f593, 0f3EE66666;
|
|
mul.rn.f32 %f594, %f593, %f590;
|
|
neg.f32 %f595, %f594;
|
|
fma.rn.f32 %f596, %f593, %f590, %f595;
|
|
fma.rn.f32 %f597, %f593, %f592, %f596;
|
|
mov.f32 %f598, 0f00000000;
|
|
fma.rn.f32 %f599, %f598, %f590, %f597;
|
|
add.rn.f32 %f600, %f594, %f599;
|
|
neg.f32 %f601, %f600;
|
|
add.rn.f32 %f602, %f594, %f601;
|
|
add.rn.f32 %f603, %f602, %f599;
|
|
mov.b32 %r230, %f600;
|
|
setp.eq.s32 %p67, %r230, 1118925336;
|
|
add.s32 %r231, %r230, -1;
|
|
mov.b32 %f604, %r231;
|
|
add.f32 %f605, %f603, 0f37000000;
|
|
selp.f32 %f128, %f605, %f603, %p67;
|
|
selp.f32 %f606, %f604, %f600, %p67;
|
|
mov.f32 %f607, 0f3FB8AA3B;
|
|
mul.rn.f32 %f608, %f606, %f607;
|
|
cvt.rzi.f32.f32 %f609, %f608;
|
|
abs.f32 %f610, %f609;
|
|
setp.gt.f32 %p68, %f610, 0f42FC0000;
|
|
mov.b32 %r232, %f609;
|
|
and.b32 %r233, %r232, -2147483648;
|
|
or.b32 %r234, %r233, 1123811328;
|
|
mov.b32 %f611, %r234;
|
|
selp.f32 %f612, %f611, %f609, %p68;
|
|
mov.f32 %f613, 0fBF317218;
|
|
fma.rn.f32 %f614, %f612, %f613, %f606;
|
|
mov.f32 %f615, 0f3102E308;
|
|
fma.rn.f32 %f616, %f612, %f615, %f614;
|
|
mul.f32 %f617, %f616, 0f3FB8AA3B;
|
|
add.f32 %f618, %f612, 0f4B40007F;
|
|
mov.b32 %r235, %f618;
|
|
shl.b32 %r236, %r235, 23;
|
|
mov.b32 %f619, %r236;
|
|
ex2.approx.ftz.f32 %f620, %f617;
|
|
mul.f32 %f129, %f620, %f619;
|
|
setp.eq.f32 %p69, %f129, 0f7F800000;
|
|
mov.f32 %f1174, 0f7F800000;
|
|
@%p69 bra $L__BB0_59;
|
|
|
|
fma.rn.f32 %f1174, %f129, %f128, %f129;
|
|
|
|
$L__BB0_59:
|
|
setp.lt.f32 %p70, %f112, 0f00000000;
|
|
and.pred %p2, %p70, %p56;
|
|
setp.eq.f32 %p72, %f112, 0f00000000;
|
|
@%p72 bra $L__BB0_63;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_63:
|
|
add.f32 %f625, %f112, %f112;
|
|
selp.f32 %f1176, %f625, 0f00000000, %p56;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_60:
|
|
mov.b32 %r237, %f1174;
|
|
xor.b32 %r238, %r237, -2147483648;
|
|
mov.b32 %f621, %r238;
|
|
selp.f32 %f1176, %f621, %f1174, %p2;
|
|
setp.geu.f32 %p73, %f112, 0f00000000;
|
|
@%p73 bra $L__BB0_64;
|
|
|
|
mov.f32 %f622, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f623, %f622;
|
|
setp.eq.f32 %p74, %f623, 0f3EE66666;
|
|
@%p74 bra $L__BB0_64;
|
|
|
|
mov.f32 %f1176, 0f7FFFFFFF;
|
|
|
|
$L__BB0_64:
|
|
add.f32 %f626, %f127, 0f3EE66666;
|
|
mov.b32 %r239, %f626;
|
|
setp.lt.s32 %p76, %r239, 2139095040;
|
|
@%p76 bra $L__BB0_69;
|
|
|
|
setp.gtu.f32 %p77, %f127, 0f7F800000;
|
|
@%p77 bra $L__BB0_68;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f1176, %f112, 0f3EE66666;
|
|
bra.uni $L__BB0_69;
|
|
|
|
$L__BB0_66:
|
|
setp.neu.f32 %p78, %f127, 0f7F800000;
|
|
@%p78 bra $L__BB0_69;
|
|
|
|
selp.f32 %f1176, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_69:
|
|
setp.eq.f32 %p79, %f112, 0f3F800000;
|
|
selp.f32 %f138, 0f3F800000, %f1176, %p79;
|
|
abs.f32 %f139, %f113;
|
|
setp.lt.f32 %p80, %f139, 0f00800000;
|
|
mul.f32 %f628, %f139, 0f4B800000;
|
|
selp.f32 %f629, %f628, %f139, %p80;
|
|
selp.f32 %f630, 0fC3170000, 0fC2FE0000, %p80;
|
|
mov.b32 %r240, %f629;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f631, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f632, %r243;
|
|
add.f32 %f633, %f630, %f632;
|
|
setp.gt.f32 %p81, %f631, 0f3FB504F3;
|
|
mul.f32 %f634, %f631, 0f3F000000;
|
|
add.f32 %f635, %f633, 0f3F800000;
|
|
selp.f32 %f636, %f635, %f633, %p81;
|
|
selp.f32 %f637, %f634, %f631, %p81;
|
|
add.f32 %f638, %f637, 0fBF800000;
|
|
add.f32 %f639, %f637, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f640, %f639;
|
|
add.f32 %f641, %f638, %f638;
|
|
mul.f32 %f642, %f641, %f640;
|
|
mul.f32 %f643, %f642, %f642;
|
|
mov.f32 %f644, 0f3C4CAF63;
|
|
mov.f32 %f645, 0f3B18F0FE;
|
|
fma.rn.f32 %f646, %f645, %f643, %f644;
|
|
mov.f32 %f647, 0f3DAAAABD;
|
|
fma.rn.f32 %f648, %f646, %f643, %f647;
|
|
mul.rn.f32 %f649, %f648, %f643;
|
|
mul.rn.f32 %f650, %f649, %f642;
|
|
sub.f32 %f651, %f638, %f642;
|
|
add.f32 %f652, %f651, %f651;
|
|
neg.f32 %f653, %f642;
|
|
fma.rn.f32 %f654, %f653, %f638, %f652;
|
|
mul.rn.f32 %f655, %f640, %f654;
|
|
add.f32 %f656, %f650, %f642;
|
|
sub.f32 %f657, %f642, %f656;
|
|
add.f32 %f658, %f650, %f657;
|
|
add.f32 %f659, %f655, %f658;
|
|
add.f32 %f660, %f656, %f659;
|
|
sub.f32 %f661, %f656, %f660;
|
|
add.f32 %f662, %f659, %f661;
|
|
mov.f32 %f663, 0f3F317200;
|
|
mul.rn.f32 %f664, %f636, %f663;
|
|
mov.f32 %f665, 0f35BFBE8E;
|
|
mul.rn.f32 %f666, %f636, %f665;
|
|
add.f32 %f667, %f664, %f660;
|
|
sub.f32 %f668, %f664, %f667;
|
|
add.f32 %f669, %f660, %f668;
|
|
add.f32 %f670, %f662, %f669;
|
|
add.f32 %f671, %f666, %f670;
|
|
add.f32 %f672, %f667, %f671;
|
|
sub.f32 %f673, %f667, %f672;
|
|
add.f32 %f674, %f671, %f673;
|
|
mov.f32 %f675, 0f3EE66666;
|
|
mul.rn.f32 %f676, %f675, %f672;
|
|
neg.f32 %f677, %f676;
|
|
fma.rn.f32 %f678, %f675, %f672, %f677;
|
|
fma.rn.f32 %f679, %f675, %f674, %f678;
|
|
mov.f32 %f680, 0f00000000;
|
|
fma.rn.f32 %f681, %f680, %f672, %f679;
|
|
add.rn.f32 %f682, %f676, %f681;
|
|
neg.f32 %f683, %f682;
|
|
add.rn.f32 %f684, %f676, %f683;
|
|
add.rn.f32 %f685, %f684, %f681;
|
|
mov.b32 %r244, %f682;
|
|
setp.eq.s32 %p82, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f686, %r245;
|
|
add.f32 %f687, %f685, 0f37000000;
|
|
selp.f32 %f140, %f687, %f685, %p82;
|
|
selp.f32 %f688, %f686, %f682, %p82;
|
|
mov.f32 %f689, 0f3FB8AA3B;
|
|
mul.rn.f32 %f690, %f688, %f689;
|
|
cvt.rzi.f32.f32 %f691, %f690;
|
|
abs.f32 %f692, %f691;
|
|
setp.gt.f32 %p83, %f692, 0f42FC0000;
|
|
mov.b32 %r246, %f691;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f693, %r248;
|
|
selp.f32 %f694, %f693, %f691, %p83;
|
|
mov.f32 %f695, 0fBF317218;
|
|
fma.rn.f32 %f696, %f694, %f695, %f688;
|
|
mov.f32 %f697, 0f3102E308;
|
|
fma.rn.f32 %f698, %f694, %f697, %f696;
|
|
mul.f32 %f699, %f698, 0f3FB8AA3B;
|
|
add.f32 %f700, %f694, 0f4B40007F;
|
|
mov.b32 %r249, %f700;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f701, %r250;
|
|
ex2.approx.ftz.f32 %f702, %f699;
|
|
mul.f32 %f141, %f702, %f701;
|
|
setp.eq.f32 %p84, %f141, 0f7F800000;
|
|
mov.f32 %f1177, 0f7F800000;
|
|
@%p84 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f1177, %f141, %f140, %f141;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p85, %f113, 0f00000000;
|
|
and.pred %p3, %p85, %p56;
|
|
setp.eq.f32 %p87, %f113, 0f00000000;
|
|
@%p87 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f707, %f113, %f113;
|
|
selp.f32 %f1179, %f707, 0f00000000, %p56;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r251, %f1177;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f703, %r252;
|
|
selp.f32 %f1179, %f703, %f1177, %p3;
|
|
setp.geu.f32 %p88, %f113, 0f00000000;
|
|
@%p88 bra $L__BB0_76;
|
|
|
|
mov.f32 %f704, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f705, %f704;
|
|
setp.eq.f32 %p89, %f705, 0f3EE66666;
|
|
@%p89 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1179, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f708, %f139, 0f3EE66666;
|
|
mov.b32 %r253, %f708;
|
|
setp.lt.s32 %p91, %r253, 2139095040;
|
|
@%p91 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p92, %f139, 0f7F800000;
|
|
@%p92 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1179, %f113, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p93, %f139, 0f7F800000;
|
|
@%p93 bra $L__BB0_81;
|
|
|
|
selp.f32 %f1179, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p94, %f113, 0f3F800000;
|
|
mov.f32 %f710, 0f3F800000;
|
|
selp.f32 %f711, 0f3F800000, %f1179, %p94;
|
|
min.f32 %f712, %f126, %f710;
|
|
mov.f32 %f713, 0f00000000;
|
|
max.f32 %f150, %f713, %f712;
|
|
min.f32 %f714, %f138, %f710;
|
|
max.f32 %f151, %f713, %f714;
|
|
min.f32 %f715, %f711, %f710;
|
|
max.f32 %f152, %f713, %f715;
|
|
mov.f32 %f719, 0f3ED55555;
|
|
abs.f32 %f154, %f150;
|
|
setp.lt.f32 %p95, %f154, 0f00800000;
|
|
mul.f32 %f721, %f154, 0f4B800000;
|
|
selp.f32 %f722, %f721, %f154, %p95;
|
|
selp.f32 %f723, 0fC3170000, 0fC2FE0000, %p95;
|
|
mov.b32 %r256, %f722;
|
|
and.b32 %r257, %r256, 8388607;
|
|
or.b32 %r258, %r257, 1065353216;
|
|
mov.b32 %f724, %r258;
|
|
shr.u32 %r259, %r256, 23;
|
|
cvt.rn.f32.u32 %f725, %r259;
|
|
add.f32 %f726, %f723, %f725;
|
|
setp.gt.f32 %p96, %f724, 0f3FB504F3;
|
|
mul.f32 %f727, %f724, 0f3F000000;
|
|
add.f32 %f728, %f726, 0f3F800000;
|
|
selp.f32 %f729, %f728, %f726, %p96;
|
|
selp.f32 %f730, %f727, %f724, %p96;
|
|
add.f32 %f731, %f730, 0fBF800000;
|
|
add.f32 %f732, %f730, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f733, %f732;
|
|
add.f32 %f734, %f731, %f731;
|
|
mul.f32 %f735, %f734, %f733;
|
|
mul.f32 %f736, %f735, %f735;
|
|
mov.f32 %f737, 0f3C4CAF63;
|
|
mov.f32 %f738, 0f3B18F0FE;
|
|
fma.rn.f32 %f739, %f738, %f736, %f737;
|
|
mov.f32 %f740, 0f3DAAAABD;
|
|
fma.rn.f32 %f741, %f739, %f736, %f740;
|
|
mul.rn.f32 %f742, %f741, %f736;
|
|
mul.rn.f32 %f743, %f742, %f735;
|
|
sub.f32 %f744, %f731, %f735;
|
|
add.f32 %f745, %f744, %f744;
|
|
neg.f32 %f746, %f735;
|
|
fma.rn.f32 %f747, %f746, %f731, %f745;
|
|
mul.rn.f32 %f748, %f733, %f747;
|
|
add.f32 %f749, %f743, %f735;
|
|
sub.f32 %f750, %f735, %f749;
|
|
add.f32 %f751, %f743, %f750;
|
|
add.f32 %f752, %f748, %f751;
|
|
add.f32 %f753, %f749, %f752;
|
|
sub.f32 %f754, %f749, %f753;
|
|
add.f32 %f755, %f752, %f754;
|
|
mov.f32 %f756, 0f3F317200;
|
|
mul.rn.f32 %f757, %f729, %f756;
|
|
mov.f32 %f758, 0f35BFBE8E;
|
|
mul.rn.f32 %f759, %f729, %f758;
|
|
add.f32 %f760, %f757, %f753;
|
|
sub.f32 %f761, %f757, %f760;
|
|
add.f32 %f762, %f753, %f761;
|
|
add.f32 %f763, %f755, %f762;
|
|
add.f32 %f764, %f759, %f763;
|
|
add.f32 %f765, %f760, %f764;
|
|
sub.f32 %f766, %f760, %f765;
|
|
add.f32 %f767, %f764, %f766;
|
|
mul.rn.f32 %f768, %f719, %f765;
|
|
neg.f32 %f769, %f768;
|
|
fma.rn.f32 %f770, %f719, %f765, %f769;
|
|
fma.rn.f32 %f771, %f719, %f767, %f770;
|
|
fma.rn.f32 %f772, %f713, %f765, %f771;
|
|
add.rn.f32 %f773, %f768, %f772;
|
|
neg.f32 %f774, %f773;
|
|
add.rn.f32 %f775, %f768, %f774;
|
|
add.rn.f32 %f776, %f775, %f772;
|
|
mov.b32 %r260, %f773;
|
|
setp.eq.s32 %p97, %r260, 1118925336;
|
|
add.s32 %r261, %r260, -1;
|
|
mov.b32 %f777, %r261;
|
|
add.f32 %f778, %f776, 0f37000000;
|
|
selp.f32 %f155, %f778, %f776, %p97;
|
|
selp.f32 %f779, %f777, %f773, %p97;
|
|
mov.f32 %f780, 0f3FB8AA3B;
|
|
mul.rn.f32 %f781, %f779, %f780;
|
|
cvt.rzi.f32.f32 %f782, %f781;
|
|
abs.f32 %f783, %f782;
|
|
setp.gt.f32 %p98, %f783, 0f42FC0000;
|
|
mov.b32 %r262, %f782;
|
|
and.b32 %r263, %r262, -2147483648;
|
|
or.b32 %r264, %r263, 1123811328;
|
|
mov.b32 %f784, %r264;
|
|
selp.f32 %f785, %f784, %f782, %p98;
|
|
mov.f32 %f786, 0fBF317218;
|
|
fma.rn.f32 %f787, %f785, %f786, %f779;
|
|
mov.f32 %f788, 0f3102E308;
|
|
fma.rn.f32 %f789, %f785, %f788, %f787;
|
|
mul.f32 %f790, %f789, 0f3FB8AA3B;
|
|
add.f32 %f791, %f785, 0f4B40007F;
|
|
mov.b32 %r265, %f791;
|
|
shl.b32 %r266, %r265, 23;
|
|
mov.b32 %f792, %r266;
|
|
ex2.approx.ftz.f32 %f793, %f790;
|
|
mul.f32 %f156, %f793, %f792;
|
|
setp.eq.f32 %p99, %f156, 0f7F800000;
|
|
mov.f32 %f1180, 0f7F800000;
|
|
@%p99 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f1180, %f156, %f155, %f156;
|
|
|
|
$L__BB0_83:
|
|
mov.f32 %f1082, 0f00000000;
|
|
max.f32 %f1081, %f1082, %f712;
|
|
mov.f32 %f1080, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1079, %f1080;
|
|
add.f32 %f1078, %f1079, %f1079;
|
|
mov.f32 %f1077, 0f3ED55555;
|
|
sub.f32 %f1076, %f1077, %f1078;
|
|
abs.f32 %f1075, %f1076;
|
|
setp.lt.f32 %p100, %f1081, 0f00000000;
|
|
setp.eq.f32 %p101, %f1075, 0f3F800000;
|
|
and.pred %p4, %p100, %p101;
|
|
setp.eq.f32 %p102, %f1081, 0f00000000;
|
|
@%p102 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
mov.f32 %f1104, 0f00000000;
|
|
max.f32 %f1103, %f1104, %f712;
|
|
add.f32 %f798, %f1103, %f1103;
|
|
selp.f32 %f1182, %f798, 0f00000000, %p101;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.f32 %f1084, 0f00000000;
|
|
max.f32 %f1083, %f1084, %f712;
|
|
mov.b32 %r267, %f1180;
|
|
xor.b32 %r268, %r267, -2147483648;
|
|
mov.b32 %f794, %r268;
|
|
selp.f32 %f1182, %f794, %f1180, %p4;
|
|
setp.geu.f32 %p103, %f1083, 0f00000000;
|
|
@%p103 bra $L__BB0_88;
|
|
|
|
mov.f32 %f795, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f796, %f795;
|
|
setp.eq.f32 %p104, %f796, 0f3ED55555;
|
|
@%p104 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1182, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
mov.f32 %f1087, 0f00000000;
|
|
max.f32 %f1086, %f1087, %f712;
|
|
abs.f32 %f1085, %f1086;
|
|
add.f32 %f799, %f1085, 0f3ED55555;
|
|
mov.b32 %r269, %f799;
|
|
setp.lt.s32 %p106, %r269, 2139095040;
|
|
@%p106 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1097, 0f00000000;
|
|
max.f32 %f1096, %f1097, %f712;
|
|
abs.f32 %f1095, %f1096;
|
|
setp.gtu.f32 %p107, %f1095, 0f7F800000;
|
|
@%p107 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f1102, 0f00000000;
|
|
max.f32 %f1101, %f1102, %f712;
|
|
add.f32 %f1182, %f1101, 0f3ED55555;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
mov.f32 %f1100, 0f00000000;
|
|
max.f32 %f1099, %f1100, %f712;
|
|
abs.f32 %f1098, %f1099;
|
|
setp.neu.f32 %p108, %f1098, 0f7F800000;
|
|
@%p108 bra $L__BB0_93;
|
|
|
|
selp.f32 %f1182, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_93:
|
|
abs.f32 %f165, %f151;
|
|
setp.lt.f32 %p109, %f165, 0f00800000;
|
|
mul.f32 %f801, %f165, 0f4B800000;
|
|
selp.f32 %f802, %f801, %f165, %p109;
|
|
selp.f32 %f803, 0fC3170000, 0fC2FE0000, %p109;
|
|
mov.b32 %r270, %f802;
|
|
and.b32 %r271, %r270, 8388607;
|
|
or.b32 %r272, %r271, 1065353216;
|
|
mov.b32 %f804, %r272;
|
|
shr.u32 %r273, %r270, 23;
|
|
cvt.rn.f32.u32 %f805, %r273;
|
|
add.f32 %f806, %f803, %f805;
|
|
setp.gt.f32 %p110, %f804, 0f3FB504F3;
|
|
mul.f32 %f807, %f804, 0f3F000000;
|
|
add.f32 %f808, %f806, 0f3F800000;
|
|
selp.f32 %f809, %f808, %f806, %p110;
|
|
selp.f32 %f810, %f807, %f804, %p110;
|
|
add.f32 %f811, %f810, 0fBF800000;
|
|
add.f32 %f812, %f810, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f813, %f812;
|
|
add.f32 %f814, %f811, %f811;
|
|
mul.f32 %f815, %f814, %f813;
|
|
mul.f32 %f816, %f815, %f815;
|
|
mov.f32 %f817, 0f3C4CAF63;
|
|
mov.f32 %f818, 0f3B18F0FE;
|
|
fma.rn.f32 %f819, %f818, %f816, %f817;
|
|
mov.f32 %f820, 0f3DAAAABD;
|
|
fma.rn.f32 %f821, %f819, %f816, %f820;
|
|
mul.rn.f32 %f822, %f821, %f816;
|
|
mul.rn.f32 %f823, %f822, %f815;
|
|
sub.f32 %f824, %f811, %f815;
|
|
add.f32 %f825, %f824, %f824;
|
|
neg.f32 %f826, %f815;
|
|
fma.rn.f32 %f827, %f826, %f811, %f825;
|
|
mul.rn.f32 %f828, %f813, %f827;
|
|
add.f32 %f829, %f823, %f815;
|
|
sub.f32 %f830, %f815, %f829;
|
|
add.f32 %f831, %f823, %f830;
|
|
add.f32 %f832, %f828, %f831;
|
|
add.f32 %f833, %f829, %f832;
|
|
sub.f32 %f834, %f829, %f833;
|
|
add.f32 %f835, %f832, %f834;
|
|
mov.f32 %f836, 0f3F317200;
|
|
mul.rn.f32 %f837, %f809, %f836;
|
|
mov.f32 %f838, 0f35BFBE8E;
|
|
mul.rn.f32 %f839, %f809, %f838;
|
|
add.f32 %f840, %f837, %f833;
|
|
sub.f32 %f841, %f837, %f840;
|
|
add.f32 %f842, %f833, %f841;
|
|
add.f32 %f843, %f835, %f842;
|
|
add.f32 %f844, %f839, %f843;
|
|
add.f32 %f845, %f840, %f844;
|
|
sub.f32 %f846, %f840, %f845;
|
|
add.f32 %f847, %f844, %f846;
|
|
mov.f32 %f848, 0f3ED55555;
|
|
mul.rn.f32 %f849, %f848, %f845;
|
|
neg.f32 %f850, %f849;
|
|
fma.rn.f32 %f851, %f848, %f845, %f850;
|
|
fma.rn.f32 %f852, %f848, %f847, %f851;
|
|
mov.f32 %f853, 0f00000000;
|
|
fma.rn.f32 %f854, %f853, %f845, %f852;
|
|
add.rn.f32 %f855, %f849, %f854;
|
|
neg.f32 %f856, %f855;
|
|
add.rn.f32 %f857, %f849, %f856;
|
|
add.rn.f32 %f858, %f857, %f854;
|
|
mov.b32 %r274, %f855;
|
|
setp.eq.s32 %p111, %r274, 1118925336;
|
|
add.s32 %r275, %r274, -1;
|
|
mov.b32 %f859, %r275;
|
|
add.f32 %f860, %f858, 0f37000000;
|
|
selp.f32 %f166, %f860, %f858, %p111;
|
|
selp.f32 %f861, %f859, %f855, %p111;
|
|
mov.f32 %f862, 0f3FB8AA3B;
|
|
mul.rn.f32 %f863, %f861, %f862;
|
|
cvt.rzi.f32.f32 %f864, %f863;
|
|
abs.f32 %f865, %f864;
|
|
setp.gt.f32 %p112, %f865, 0f42FC0000;
|
|
mov.b32 %r276, %f864;
|
|
and.b32 %r277, %r276, -2147483648;
|
|
or.b32 %r278, %r277, 1123811328;
|
|
mov.b32 %f866, %r278;
|
|
selp.f32 %f867, %f866, %f864, %p112;
|
|
mov.f32 %f868, 0fBF317218;
|
|
fma.rn.f32 %f869, %f867, %f868, %f861;
|
|
mov.f32 %f870, 0f3102E308;
|
|
fma.rn.f32 %f871, %f867, %f870, %f869;
|
|
mul.f32 %f872, %f871, 0f3FB8AA3B;
|
|
add.f32 %f873, %f867, 0f4B40007F;
|
|
mov.b32 %r279, %f873;
|
|
shl.b32 %r280, %r279, 23;
|
|
mov.b32 %f874, %r280;
|
|
ex2.approx.ftz.f32 %f875, %f872;
|
|
mul.f32 %f167, %f875, %f874;
|
|
setp.eq.f32 %p113, %f167, 0f7F800000;
|
|
mov.f32 %f1183, 0f7F800000;
|
|
@%p113 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f1183, %f167, %f166, %f167;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p114, %f151, 0f00000000;
|
|
and.pred %p5, %p114, %p101;
|
|
setp.eq.f32 %p116, %f151, 0f00000000;
|
|
@%p116 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f880, %f151, %f151;
|
|
selp.f32 %f1185, %f880, 0f00000000, %p101;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r281, %f1183;
|
|
xor.b32 %r282, %r281, -2147483648;
|
|
mov.b32 %f876, %r282;
|
|
selp.f32 %f1185, %f876, %f1183, %p5;
|
|
setp.geu.f32 %p117, %f151, 0f00000000;
|
|
@%p117 bra $L__BB0_100;
|
|
|
|
mov.f32 %f877, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f878, %f877;
|
|
setp.eq.f32 %p118, %f878, 0f3ED55555;
|
|
@%p118 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1185, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
mov.f32 %f1115, 0f00000000;
|
|
max.f32 %f1114, %f1115, %f714;
|
|
abs.f32 %f1113, %f1114;
|
|
add.f32 %f881, %f1113, 0f3ED55555;
|
|
mov.b32 %r283, %f881;
|
|
setp.lt.s32 %p120, %r283, 2139095040;
|
|
@%p120 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1124, 0f00000000;
|
|
max.f32 %f1123, %f1124, %f714;
|
|
abs.f32 %f1122, %f1123;
|
|
setp.gtu.f32 %p121, %f1122, 0f7F800000;
|
|
@%p121 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1185, %f151, 0f3ED55555;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
mov.f32 %f1127, 0f00000000;
|
|
max.f32 %f1126, %f1127, %f714;
|
|
abs.f32 %f1125, %f1126;
|
|
setp.neu.f32 %p122, %f1125, 0f7F800000;
|
|
@%p122 bra $L__BB0_105;
|
|
|
|
selp.f32 %f1185, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_105:
|
|
abs.f32 %f176, %f152;
|
|
setp.lt.f32 %p123, %f176, 0f00800000;
|
|
mul.f32 %f883, %f176, 0f4B800000;
|
|
selp.f32 %f884, %f883, %f176, %p123;
|
|
selp.f32 %f885, 0fC3170000, 0fC2FE0000, %p123;
|
|
mov.b32 %r284, %f884;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f886, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f887, %r287;
|
|
add.f32 %f888, %f885, %f887;
|
|
setp.gt.f32 %p124, %f886, 0f3FB504F3;
|
|
mul.f32 %f889, %f886, 0f3F000000;
|
|
add.f32 %f890, %f888, 0f3F800000;
|
|
selp.f32 %f891, %f890, %f888, %p124;
|
|
selp.f32 %f892, %f889, %f886, %p124;
|
|
add.f32 %f893, %f892, 0fBF800000;
|
|
add.f32 %f894, %f892, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f895, %f894;
|
|
add.f32 %f896, %f893, %f893;
|
|
mul.f32 %f897, %f896, %f895;
|
|
mul.f32 %f898, %f897, %f897;
|
|
mov.f32 %f899, 0f3C4CAF63;
|
|
mov.f32 %f900, 0f3B18F0FE;
|
|
fma.rn.f32 %f901, %f900, %f898, %f899;
|
|
mov.f32 %f902, 0f3DAAAABD;
|
|
fma.rn.f32 %f903, %f901, %f898, %f902;
|
|
mul.rn.f32 %f904, %f903, %f898;
|
|
mul.rn.f32 %f905, %f904, %f897;
|
|
sub.f32 %f906, %f893, %f897;
|
|
add.f32 %f907, %f906, %f906;
|
|
neg.f32 %f908, %f897;
|
|
fma.rn.f32 %f909, %f908, %f893, %f907;
|
|
mul.rn.f32 %f910, %f895, %f909;
|
|
add.f32 %f911, %f905, %f897;
|
|
sub.f32 %f912, %f897, %f911;
|
|
add.f32 %f913, %f905, %f912;
|
|
add.f32 %f914, %f910, %f913;
|
|
add.f32 %f915, %f911, %f914;
|
|
sub.f32 %f916, %f911, %f915;
|
|
add.f32 %f917, %f914, %f916;
|
|
mov.f32 %f918, 0f3F317200;
|
|
mul.rn.f32 %f919, %f891, %f918;
|
|
mov.f32 %f920, 0f35BFBE8E;
|
|
mul.rn.f32 %f921, %f891, %f920;
|
|
add.f32 %f922, %f919, %f915;
|
|
sub.f32 %f923, %f919, %f922;
|
|
add.f32 %f924, %f915, %f923;
|
|
add.f32 %f925, %f917, %f924;
|
|
add.f32 %f926, %f921, %f925;
|
|
add.f32 %f927, %f922, %f926;
|
|
sub.f32 %f928, %f922, %f927;
|
|
add.f32 %f929, %f926, %f928;
|
|
mov.f32 %f930, 0f3ED55555;
|
|
mul.rn.f32 %f931, %f930, %f927;
|
|
neg.f32 %f932, %f931;
|
|
fma.rn.f32 %f933, %f930, %f927, %f932;
|
|
fma.rn.f32 %f934, %f930, %f929, %f933;
|
|
mov.f32 %f935, 0f00000000;
|
|
fma.rn.f32 %f936, %f935, %f927, %f934;
|
|
add.rn.f32 %f937, %f931, %f936;
|
|
neg.f32 %f938, %f937;
|
|
add.rn.f32 %f939, %f931, %f938;
|
|
add.rn.f32 %f940, %f939, %f936;
|
|
mov.b32 %r288, %f937;
|
|
setp.eq.s32 %p125, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f941, %r289;
|
|
add.f32 %f942, %f940, 0f37000000;
|
|
selp.f32 %f177, %f942, %f940, %p125;
|
|
selp.f32 %f943, %f941, %f937, %p125;
|
|
mov.f32 %f944, 0f3FB8AA3B;
|
|
mul.rn.f32 %f945, %f943, %f944;
|
|
cvt.rzi.f32.f32 %f946, %f945;
|
|
abs.f32 %f947, %f946;
|
|
setp.gt.f32 %p126, %f947, 0f42FC0000;
|
|
mov.b32 %r290, %f946;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f948, %r292;
|
|
selp.f32 %f949, %f948, %f946, %p126;
|
|
mov.f32 %f950, 0fBF317218;
|
|
fma.rn.f32 %f951, %f949, %f950, %f943;
|
|
mov.f32 %f952, 0f3102E308;
|
|
fma.rn.f32 %f953, %f949, %f952, %f951;
|
|
mul.f32 %f954, %f953, 0f3FB8AA3B;
|
|
add.f32 %f955, %f949, 0f4B40007F;
|
|
mov.b32 %r293, %f955;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f956, %r294;
|
|
ex2.approx.ftz.f32 %f957, %f954;
|
|
mul.f32 %f178, %f957, %f956;
|
|
setp.eq.f32 %p127, %f178, 0f7F800000;
|
|
mov.f32 %f1186, 0f7F800000;
|
|
@%p127 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f1186, %f178, %f177, %f178;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p128, %f152, 0f00000000;
|
|
and.pred %p6, %p128, %p101;
|
|
setp.eq.f32 %p130, %f152, 0f00000000;
|
|
@%p130 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f962, %f152, %f152;
|
|
selp.f32 %f1188, %f962, 0f00000000, %p101;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r295, %f1186;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f958, %r296;
|
|
selp.f32 %f1188, %f958, %f1186, %p6;
|
|
setp.geu.f32 %p131, %f152, 0f00000000;
|
|
@%p131 bra $L__BB0_112;
|
|
|
|
mov.f32 %f959, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f960, %f959;
|
|
setp.eq.f32 %p132, %f960, 0f3ED55555;
|
|
@%p132 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1188, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
mov.f32 %f1130, 0f00000000;
|
|
max.f32 %f1129, %f1130, %f715;
|
|
abs.f32 %f1128, %f1129;
|
|
add.f32 %f963, %f1128, 0f3ED55555;
|
|
mov.b32 %r297, %f963;
|
|
setp.lt.s32 %p134, %r297, 2139095040;
|
|
@%p134 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1133, 0f00000000;
|
|
max.f32 %f1132, %f1133, %f715;
|
|
abs.f32 %f1131, %f1132;
|
|
setp.gtu.f32 %p135, %f1131, 0f7F800000;
|
|
@%p135 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1188, %f152, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
mov.f32 %f1136, 0f00000000;
|
|
max.f32 %f1135, %f1136, %f715;
|
|
abs.f32 %f1134, %f1135;
|
|
setp.neu.f32 %p136, %f1134, 0f7F800000;
|
|
@%p136 bra $L__BB0_117;
|
|
|
|
selp.f32 %f1188, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_117:
|
|
mov.f32 %f1089, 0f00000000;
|
|
max.f32 %f1088, %f1089, %f712;
|
|
ld.const.u64 %rd99, [params+144];
|
|
cvta.to.global.u64 %rd98, %rd99;
|
|
ld.const.u32 %r328, [params+136];
|
|
mad.lo.s32 %r327, %r328, %r5, %r4;
|
|
cvt.u64.u32 %rd97, %r327;
|
|
fma.rn.f32 %f964, %f1182, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p137, %f1088, 0f3F800000;
|
|
mov.f32 %f965, 0f3F800000;
|
|
selp.f32 %f966, 0f3F7FFFFF, %f964, %p137;
|
|
mul.f32 %f967, %f1088, 0f414EB852;
|
|
setp.lt.f32 %p138, %f1088, 0f3B4D2E1C;
|
|
selp.f32 %f968, %f967, %f966, %p138;
|
|
fma.rn.f32 %f969, %f1185, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p139, %f151, 0f3F800000;
|
|
selp.f32 %f970, 0f3F7FFFFF, %f969, %p139;
|
|
mul.f32 %f971, %f151, 0f414EB852;
|
|
setp.lt.f32 %p140, %f151, 0f3B4D2E1C;
|
|
selp.f32 %f972, %f971, %f970, %p140;
|
|
fma.rn.f32 %f973, %f1188, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p141, %f152, 0f3F800000;
|
|
selp.f32 %f974, 0f3F7FFFFF, %f973, %p141;
|
|
mul.f32 %f975, %f152, 0f414EB852;
|
|
setp.lt.f32 %p142, %f152, 0f3B4D2E1C;
|
|
selp.f32 %f976, %f975, %f974, %p142;
|
|
min.f32 %f977, %f968, %f965;
|
|
mov.f32 %f978, 0f00000000;
|
|
max.f32 %f979, %f978, %f977;
|
|
mul.f32 %f980, %f979, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f980;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f981, %f972, %f965;
|
|
max.f32 %f982, %f978, %f981;
|
|
mul.f32 %f983, %f982, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f983;
|
|
min.u32 %r301, %r300, 255;
|
|
min.f32 %f984, %f976, %f965;
|
|
max.f32 %f985, %f978, %f984;
|
|
mul.f32 %f986, %f985, 0f43800000;
|
|
cvt.rzi.u32.f32 %r302, %f986;
|
|
min.u32 %r303, %r302, 255;
|
|
shl.b64 %rd67, %rd97, 2;
|
|
add.s64 %rd68, %rd98, %rd67;
|
|
cvt.u16.u32 %rs44, %r303;
|
|
cvt.u16.u32 %rs45, %r301;
|
|
cvt.u16.u32 %rs46, %r299;
|
|
mov.u16 %rs47, 255;
|
|
st.global.v4.u8 [%rd68], {%rs46, %rs45, %rs44, %rs47};
|
|
|
|
$L__BB0_118:
|
|
ld.const.u32 %r329, [params+104];
|
|
and.b32 %r304, %r329, 4;
|
|
setp.eq.s32 %p143, %r304, 0;
|
|
ld.const.u32 %r351, [params+108];
|
|
@%p143 bra $L__BB0_122;
|
|
|
|
setp.eq.s32 %p144, %r351, 0;
|
|
ld.const.u64 %rd69, [params+224];
|
|
cvta.to.global.u64 %rd70, %rd69;
|
|
ld.const.u32 %r305, [params+216];
|
|
mad.lo.s32 %r306, %r305, %r5, %r4;
|
|
mul.wide.u32 %rd71, %r306, 8;
|
|
add.s64 %rd18, %rd70, %rd71;
|
|
@%p144 bra $L__BB0_121;
|
|
|
|
add.f32 %f1118, %f454, %f454;
|
|
mul.f32 %f1117, %f1118, %f457;
|
|
mul.f32 %f1116, %f1118, %f456;
|
|
add.f32 %f1091, %f454, %f454;
|
|
mul.f32 %f1090, %f1091, %f455;
|
|
ld.global.v4.u16 {%rs55, %rs56, %rs57, %rs58}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f987, %rs55;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f988, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f989, %rs57;}
|
|
|
|
// end inline asm
|
|
add.f32 %f990, %f1090, %f987;
|
|
add.f32 %f991, %f1116, %f988;
|
|
add.f32 %f992, %f1117, %f989;
|
|
mov.f32 %f993, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f992;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f991;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f990;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f993;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs51, %rs52, %rs53, %rs54};
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_121:
|
|
add.f32 %f1121, %f454, %f454;
|
|
mul.f32 %f1120, %f1121, %f457;
|
|
mul.f32 %f1119, %f1121, %f456;
|
|
add.f32 %f1093, %f454, %f454;
|
|
mul.f32 %f1092, %f1093, %f455;
|
|
mov.f32 %f997, 0f3F800000;
|
|
mov.u32 %r351, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f997;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f1120;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f1119;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1092;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs59, %rs60, %rs61, %rs62};
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1094, %f454, %f454;
|
|
add.f32 %f998, %f104, %f105;
|
|
add.f32 %f999, %f998, %f106;
|
|
mul.f32 %f1000, %f999, 0f3F13CD3A;
|
|
div.rn.f32 %f1001, %f1094, %f1000;
|
|
setp.eq.f32 %p145, %f1094, 0f00000000;
|
|
selp.f32 %f1002, 0f00000000, %f1001, %p145;
|
|
mul.f32 %f1003, %f104, %f1002;
|
|
mul.f32 %f1004, %f105, %f1002;
|
|
mul.f32 %f1005, %f106, %f1002;
|
|
mul.f32 %f187, %f1003, %f455;
|
|
mul.f32 %f188, %f1003, %f456;
|
|
mul.f32 %f189, %f1003, %f457;
|
|
mul.f32 %f190, %f1004, %f455;
|
|
mul.f32 %f191, %f1004, %f456;
|
|
mul.f32 %f192, %f1004, %f457;
|
|
mul.f32 %f193, %f1005, %f455;
|
|
mul.f32 %f194, %f1005, %f456;
|
|
mul.f32 %f195, %f1005, %f457;
|
|
ld.const.u64 %rd72, [params+256];
|
|
cvta.to.global.u64 %rd73, %rd72;
|
|
ld.const.u32 %r308, [params+248];
|
|
mad.lo.s32 %r309, %r308, %r5, %r4;
|
|
mul.wide.u32 %rd74, %r309, 8;
|
|
add.s64 %rd19, %rd73, %rd74;
|
|
setp.eq.s32 %p146, %r351, 0;
|
|
@%p146 bra $L__BB0_124;
|
|
|
|
ld.global.v4.u16 {%rs70, %rs71, %rs72, %rs73}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1006, %rs70;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1007, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1008, %rs72;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1009, %f187, %f1006;
|
|
add.f32 %f1010, %f188, %f1007;
|
|
add.f32 %f1011, %f189, %f1008;
|
|
mov.f32 %f1012, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1011;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1009;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1012;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs66, %rs67, %rs68, %rs69};
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_124:
|
|
mov.f32 %f1016, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f1016;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f189;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f188;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f187;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs74, %rs75, %rs76, %rs77};
|
|
|
|
$L__BB0_125:
|
|
ld.const.u64 %rd75, [params+272];
|
|
cvta.to.global.u64 %rd76, %rd75;
|
|
ld.const.u32 %r310, [params+264];
|
|
mad.lo.s32 %r311, %r310, %r5, %r4;
|
|
mul.wide.u32 %rd77, %r311, 8;
|
|
add.s64 %rd20, %rd76, %rd77;
|
|
@%p146 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs85, %rs86, %rs87, %rs88}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1017, %rs85;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1018, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1019, %rs87;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1020, %f190, %f1017;
|
|
add.f32 %f1021, %f191, %f1018;
|
|
add.f32 %f1022, %f192, %f1019;
|
|
mov.f32 %f1023, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1022;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1021;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1020;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1023;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs81, %rs82, %rs83, %rs84};
|
|
bra.uni $L__BB0_128;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f1027, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f1027;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f192;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f190;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs89, %rs90, %rs91, %rs92};
|
|
|
|
$L__BB0_128:
|
|
ld.const.u64 %rd78, [params+288];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r312, [params+280];
|
|
mad.lo.s32 %r313, %r312, %r5, %r4;
|
|
mul.wide.u32 %rd80, %r313, 8;
|
|
add.s64 %rd21, %rd79, %rd80;
|
|
@%p146 bra $L__BB0_130;
|
|
|
|
ld.global.v4.u16 {%rs100, %rs101, %rs102, %rs103}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1028, %rs100;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1029, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1030, %rs102;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1031, %f193, %f1028;
|
|
add.f32 %f1032, %f194, %f1029;
|
|
add.f32 %f1033, %f195, %f1030;
|
|
mov.f32 %f1034, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1033;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1032;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1031;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1034;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs96, %rs97, %rs98, %rs99};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f1038, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f1038;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f195;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f194;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs104, %f193;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs104, %rs105, %rs106, %rs107};
|
|
|
|
$L__BB0_146:
|
|
ret;
|
|
|
|
}
|
|
|