2598 lines
71 KiB
Plaintext
2598 lines
71 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<199>;
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.reg .b16 %rs<177>;
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.reg .f32 %f<1315>;
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.reg .b32 %r<465>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<127>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r60), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r61), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+616];
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abs.s32 %r4, %r3;
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ld.const.u32 %r5, [params+540];
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shl.b32 %r6, %r5, 1;
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ld.const.u64 %rd34, [params+400];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r66, [params+392];
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mad.lo.s32 %r67, %r66, %r61, %r60;
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mul.wide.u32 %rd36, %r67, 4;
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add.s64 %rd2, %rd35, %rd36;
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ld.global.v2.u8 {%rs7, %rs176}, [%rd2];
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or.b16 %rs9, %rs7, %rs176;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p10, %rs10, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs175, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs175, [%rd2+2];
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setp.eq.s16 %p11, %rs175, 0;
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mov.f32 %f1240, 0f00000000;
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mov.u16 %rs176, 0;
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mov.f32 %f1241, %f1240;
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mov.f32 %f1242, %f1240;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f243, %rs7;
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div.rn.f32 %f244, %f243, 0f437F0000;
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fma.rn.f32 %f245, %f244, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs176, 255;
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cvt.rn.f32.u16 %f246, %rs13;
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div.rn.f32 %f247, %f246, 0f437F0000;
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fma.rn.f32 %f248, %f247, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f249, %rs175;
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div.rn.f32 %f250, %f249, 0f437F0000;
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fma.rn.f32 %f251, %f250, 0f40000000, 0fBF800000;
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mul.f32 %f252, %f248, %f248;
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fma.rn.f32 %f253, %f245, %f245, %f252;
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fma.rn.f32 %f254, %f251, %f251, %f253;
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sqrt.rn.f32 %f255, %f254;
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rcp.rn.f32 %f256, %f255;
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mul.f32 %f1242, %f256, %f251;
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mul.f32 %f1241, %f256, %f248;
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mul.f32 %f1240, %f245, %f256;
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$L__BB0_4:
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ld.const.v2.u32 {%r68, %r69}, [params];
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add.s32 %r7, %r68, %r60;
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add.s32 %r8, %r69, %r61;
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setp.eq.f32 %p12, %f1240, 0f00000000;
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setp.eq.f32 %p13, %f1241, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1242, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_158;
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bra.uni $L__BB0_5;
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$L__BB0_158:
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ld.const.u32 %r57, [params+104];
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and.b32 %r429, %r57, 1;
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setp.eq.b32 %p187, %r429, 1;
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mov.pred %p188, 0;
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xor.pred %p189, %p187, %p188;
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not.pred %p190, %p189;
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@%p190 bra $L__BB0_160;
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ld.const.u64 %rd97, [params+144];
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cvta.to.global.u64 %rd98, %rd97;
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ld.const.u32 %r430, [params+136];
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mad.lo.s32 %r431, %r430, %r8, %r7;
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mul.wide.u32 %rd99, %r431, 4;
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add.s64 %rd100, %rd98, %rd99;
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mov.u16 %rs97, 0;
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st.global.v4.u8 [%rd100], {%rs97, %rs97, %rs97, %rs97};
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$L__BB0_160:
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and.b32 %r432, %r57, 8;
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setp.eq.s32 %p191, %r432, 0;
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@%p191 bra $L__BB0_162;
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ld.const.u64 %rd101, [params+192];
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cvta.to.global.u64 %rd102, %rd101;
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ld.const.u32 %r433, [params+184];
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mad.lo.s32 %r434, %r433, %r8, %r7;
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mov.f32 %f1188, 0f00000000;
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cvt.rzi.u32.f32 %r435, %f1188;
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mul.wide.u32 %rd103, %r434, 2;
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add.s64 %rd104, %rd102, %rd103;
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mov.u16 %rs98, 0;
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cvt.u16.u32 %rs99, %r435;
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st.global.v2.u8 [%rd104], {%rs99, %rs98};
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$L__BB0_162:
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and.b32 %r436, %r57, 4;
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setp.eq.s32 %p192, %r436, 0;
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ld.const.u32 %r464, [params+108];
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@%p192 bra $L__BB0_166;
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setp.eq.s32 %p193, %r464, 0;
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ld.const.u64 %rd105, [params+224];
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cvta.to.global.u64 %rd106, %rd105;
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ld.const.u32 %r437, [params+216];
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mad.lo.s32 %r438, %r437, %r8, %r7;
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mul.wide.u32 %rd107, %r438, 8;
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add.s64 %rd28, %rd106, %rd107;
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@%p193 bra $L__BB0_165;
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ld.global.v4.u16 {%rs106, %rs107, %rs108, %rs109}, [%rd28];
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// begin inline asm
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{ cvt.f32.f16 %f1189, %rs106;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1190, %rs107;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1191, %rs108;}
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// end inline asm
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add.f32 %f1192, %f1189, 0f00000000;
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add.f32 %f1193, %f1190, 0f00000000;
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add.f32 %f1194, %f1191, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs105, %f1194;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs104, %f1193;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs103, %f1192;}
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// end inline asm
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mov.u16 %rs110, 0;
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st.global.v4.u16 [%rd28], {%rs103, %rs104, %rs105, %rs110};
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bra.uni $L__BB0_166;
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$L__BB0_5:
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ld.const.u64 %rd37, [params+432];
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cvta.to.global.u64 %rd38, %rd37;
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ld.const.u32 %r73, [params+424];
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mad.lo.s32 %r74, %r73, %r61, %r60;
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mul.wide.u32 %rd39, %r74, 12;
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add.s64 %rd40, %rd38, %rd39;
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ld.global.f32 %f10, [%rd40];
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mul.f32 %f263, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd40+4];
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mul.f32 %f264, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd40+8];
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mul.f32 %f265, %f12, 0f3456BF95;
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abs.f32 %f266, %f1240;
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div.rn.f32 %f267, %f263, %f266;
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abs.f32 %f268, %f1241;
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div.rn.f32 %f269, %f264, %f268;
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abs.f32 %f270, %f1242;
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div.rn.f32 %f271, %f265, %f270;
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abs.f32 %f272, %f267;
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abs.f32 %f273, %f269;
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abs.f32 %f274, %f271;
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mov.f32 %f275, 0f38D1B717;
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max.f32 %f276, %f272, %f275;
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max.f32 %f277, %f273, %f275;
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max.f32 %f278, %f274, %f275;
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fma.rn.f32 %f13, %f1240, %f276, %f10;
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fma.rn.f32 %f14, %f1241, %f277, %f11;
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fma.rn.f32 %f15, %f1242, %f278, %f12;
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ld.const.u64 %rd41, [params+128];
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cvta.to.global.u64 %rd42, %rd41;
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ld.const.u32 %r75, [params+120];
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mad.lo.s32 %r76, %r75, %r61, %r60;
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mul.wide.u32 %rd43, %r76, 4;
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add.s64 %rd44, %rd42, %rd43;
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ld.global.u32 %r455, [%rd44];
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setp.lt.s32 %p18, %r4, 1;
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mov.pred %p17, 0;
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mov.f32 %f1252, 0f00000000;
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mov.u32 %r451, 0;
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mov.f32 %f1253, %f1252;
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mov.f32 %f1254, %f1252;
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mov.f32 %f1255, %f1252;
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mov.f32 %f1256, %f1252;
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mov.f32 %f1257, %f1252;
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mov.pred %p198, %p17;
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@%p18 bra $L__BB0_23;
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ld.const.f32 %f16, [params+620];
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ld.const.u64 %rd45, [params+624];
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cvta.to.global.u64 %rd3, %rd45;
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ld.const.u64 %rd46, [params+640];
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cvta.to.global.u64 %rd47, %rd46;
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ld.const.u32 %r78, [params+632];
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and.b32 %r79, %r61, 255;
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and.b32 %r80, %r60, 255;
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mad.lo.s32 %r81, %r78, %r79, %r80;
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mul.wide.u32 %rd48, %r81, 3;
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add.s64 %rd4, %rd47, %rd48;
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ld.const.f32 %f17, [params+660];
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mul.f32 %f18, %f13, 0f3456BF95;
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mul.f32 %f19, %f14, 0f3456BF95;
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mul.f32 %f20, %f15, 0f3456BF95;
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ld.const.u64 %rd5, [params+96];
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abs.f32 %f412, %f19;
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abs.f32 %f413, %f18;
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max.f32 %f414, %f413, %f412;
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abs.f32 %f415, %f20;
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max.f32 %f416, %f414, %f415;
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$L__BB0_7:
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shl.b32 %r82, %r451, 1;
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mul.wide.s32 %rd49, %r82, 12;
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add.s64 %rd6, %rd3, %rd49;
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ld.global.f32 %f285, [%rd6];
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sub.f32 %f286, %f285, %f10;
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ld.global.f32 %f287, [%rd6+4];
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sub.f32 %f288, %f287, %f11;
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ld.global.f32 %f289, [%rd6+8];
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sub.f32 %f290, %f289, %f12;
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mul.f32 %f291, %f288, %f288;
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fma.rn.f32 %f292, %f286, %f286, %f291;
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fma.rn.f32 %f293, %f290, %f290, %f292;
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sqrt.rn.f32 %f27, %f293;
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rcp.rn.f32 %f294, %f27;
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mul.f32 %f28, %f286, %f294;
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mul.f32 %f29, %f288, %f294;
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mul.f32 %f30, %f290, %f294;
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mul.f32 %f295, %f27, %f27;
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div.rn.f32 %f31, %f16, %f295;
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ld.global.u8 %rs15, [%rd4];
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cvt.rn.f32.u16 %f296, %rs15;
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div.rn.f32 %f297, %f296, 0fC37F0000;
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fma.rn.f32 %f298, %f297, 0f3F333333, 0f3F800000;
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setp.gt.f32 %p20, %f31, %f298;
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setp.ne.s32 %p21, %r5, 0;
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and.pred %p22, %p21, %p20;
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mov.pred %p198, -1;
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@%p22 bra $L__BB0_23;
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mul.f32 %f32, %f27, %f17;
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mov.f32 %f303, 0f40800000;
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abs.f32 %f34, %f32;
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setp.lt.f32 %p23, %f34, 0f00800000;
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mul.f32 %f305, %f34, 0f4B800000;
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selp.f32 %f306, %f305, %f34, %p23;
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selp.f32 %f307, 0fC3170000, 0fC2FE0000, %p23;
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mov.b32 %r83, %f306;
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and.b32 %r84, %r83, 8388607;
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or.b32 %r85, %r84, 1065353216;
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mov.b32 %f308, %r85;
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shr.u32 %r86, %r83, 23;
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cvt.rn.f32.u32 %f309, %r86;
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add.f32 %f310, %f307, %f309;
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setp.gt.f32 %p24, %f308, 0f3FB504F3;
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mul.f32 %f311, %f308, 0f3F000000;
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add.f32 %f312, %f310, 0f3F800000;
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selp.f32 %f313, %f312, %f310, %p24;
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selp.f32 %f314, %f311, %f308, %p24;
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add.f32 %f315, %f314, 0fBF800000;
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add.f32 %f316, %f314, 0f3F800000;
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rcp.approx.ftz.f32 %f317, %f316;
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add.f32 %f318, %f315, %f315;
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mul.f32 %f319, %f318, %f317;
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mul.f32 %f320, %f319, %f319;
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mov.f32 %f321, 0f3C4CAF63;
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mov.f32 %f322, 0f3B18F0FE;
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fma.rn.f32 %f323, %f322, %f320, %f321;
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mov.f32 %f324, 0f3DAAAABD;
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fma.rn.f32 %f325, %f323, %f320, %f324;
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mul.rn.f32 %f326, %f325, %f320;
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mul.rn.f32 %f327, %f326, %f319;
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sub.f32 %f328, %f315, %f319;
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add.f32 %f329, %f328, %f328;
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neg.f32 %f330, %f319;
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fma.rn.f32 %f331, %f330, %f315, %f329;
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mul.rn.f32 %f332, %f317, %f331;
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add.f32 %f333, %f327, %f319;
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sub.f32 %f334, %f319, %f333;
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add.f32 %f335, %f327, %f334;
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add.f32 %f336, %f332, %f335;
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add.f32 %f337, %f333, %f336;
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sub.f32 %f338, %f333, %f337;
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add.f32 %f339, %f336, %f338;
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mov.f32 %f340, 0f3F317200;
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mul.rn.f32 %f341, %f313, %f340;
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mov.f32 %f342, 0f35BFBE8E;
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mul.rn.f32 %f343, %f313, %f342;
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add.f32 %f344, %f341, %f337;
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sub.f32 %f345, %f341, %f344;
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add.f32 %f346, %f337, %f345;
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add.f32 %f347, %f339, %f346;
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add.f32 %f348, %f343, %f347;
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add.f32 %f349, %f344, %f348;
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sub.f32 %f350, %f344, %f349;
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add.f32 %f351, %f348, %f350;
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mul.rn.f32 %f352, %f303, %f349;
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neg.f32 %f353, %f352;
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fma.rn.f32 %f354, %f303, %f349, %f353;
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fma.rn.f32 %f355, %f303, %f351, %f354;
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mov.f32 %f356, 0f00000000;
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fma.rn.f32 %f357, %f356, %f349, %f355;
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add.rn.f32 %f358, %f352, %f357;
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neg.f32 %f359, %f358;
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add.rn.f32 %f360, %f352, %f359;
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add.rn.f32 %f361, %f360, %f357;
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mov.b32 %r87, %f358;
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setp.eq.s32 %p25, %r87, 1118925336;
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add.s32 %r88, %r87, -1;
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mov.b32 %f362, %r88;
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add.f32 %f363, %f361, 0f37000000;
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selp.f32 %f35, %f363, %f361, %p25;
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selp.f32 %f364, %f362, %f358, %p25;
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mov.f32 %f365, 0f3FB8AA3B;
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mul.rn.f32 %f366, %f364, %f365;
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cvt.rzi.f32.f32 %f367, %f366;
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abs.f32 %f368, %f367;
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setp.gt.f32 %p26, %f368, 0f42FC0000;
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mov.b32 %r89, %f367;
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and.b32 %r90, %r89, -2147483648;
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or.b32 %r91, %r90, 1123811328;
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mov.b32 %f369, %r91;
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selp.f32 %f370, %f369, %f367, %p26;
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mov.f32 %f371, 0fBF317218;
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fma.rn.f32 %f372, %f370, %f371, %f364;
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mov.f32 %f373, 0f3102E308;
|
|
fma.rn.f32 %f374, %f370, %f373, %f372;
|
|
mul.f32 %f375, %f374, 0f3FB8AA3B;
|
|
add.f32 %f376, %f370, 0f4B40007F;
|
|
mov.b32 %r92, %f376;
|
|
shl.b32 %r93, %r92, 23;
|
|
mov.b32 %f377, %r93;
|
|
ex2.approx.ftz.f32 %f378, %f375;
|
|
mul.f32 %f36, %f378, %f377;
|
|
setp.eq.f32 %p27, %f36, 0f7F800000;
|
|
mov.f32 %f1249, 0f7F800000;
|
|
@%p27 bra $L__BB0_10;
|
|
|
|
fma.rn.f32 %f1249, %f36, %f35, %f36;
|
|
|
|
$L__BB0_10:
|
|
mov.f32 %f1239, 0f40000000;
|
|
cvt.rzi.f32.f32 %f1238, %f1239;
|
|
add.f32 %f1237, %f1238, %f1238;
|
|
mov.f32 %f1236, 0f40800000;
|
|
sub.f32 %f1235, %f1236, %f1237;
|
|
abs.f32 %f1234, %f1235;
|
|
setp.lt.f32 %p28, %f32, 0f00000000;
|
|
setp.eq.f32 %p29, %f1234, 0f3F800000;
|
|
and.pred %p1, %p28, %p29;
|
|
setp.eq.f32 %p30, %f32, 0f00000000;
|
|
@%p30 bra $L__BB0_14;
|
|
bra.uni $L__BB0_11;
|
|
|
|
$L__BB0_14:
|
|
add.f32 %f383, %f32, %f32;
|
|
selp.f32 %f1251, %f383, 0f00000000, %p29;
|
|
bra.uni $L__BB0_15;
|
|
|
|
$L__BB0_11:
|
|
mov.b32 %r94, %f1249;
|
|
xor.b32 %r95, %r94, -2147483648;
|
|
mov.b32 %f379, %r95;
|
|
selp.f32 %f1251, %f379, %f1249, %p1;
|
|
setp.geu.f32 %p31, %f32, 0f00000000;
|
|
@%p31 bra $L__BB0_15;
|
|
|
|
mov.f32 %f380, 0f40800000;
|
|
cvt.rzi.f32.f32 %f381, %f380;
|
|
setp.eq.f32 %p32, %f381, 0f40800000;
|
|
@%p32 bra $L__BB0_15;
|
|
|
|
mov.f32 %f1251, 0f7FFFFFFF;
|
|
|
|
$L__BB0_15:
|
|
add.f32 %f384, %f34, 0f40800000;
|
|
mov.b32 %r96, %f384;
|
|
setp.lt.s32 %p34, %r96, 2139095040;
|
|
@%p34 bra $L__BB0_20;
|
|
|
|
setp.gtu.f32 %p35, %f34, 0f7F800000;
|
|
@%p35 bra $L__BB0_19;
|
|
bra.uni $L__BB0_17;
|
|
|
|
$L__BB0_19:
|
|
add.f32 %f1251, %f32, 0f40800000;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_17:
|
|
setp.neu.f32 %p36, %f34, 0f7F800000;
|
|
@%p36 bra $L__BB0_20;
|
|
|
|
selp.f32 %f1251, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_20:
|
|
shl.b32 %r448, %r451, 1;
|
|
mul.wide.s32 %rd121, %r448, 12;
|
|
add.s64 %rd120, %rd3, %rd121;
|
|
mov.f32 %f385, 0f3F800000;
|
|
sub.f32 %f386, %f385, %f1251;
|
|
setp.eq.f32 %p37, %f32, 0f3F800000;
|
|
selp.f32 %f387, 0f00000000, %f386, %p37;
|
|
cvt.sat.f32.f32 %f388, %f387;
|
|
mul.f32 %f389, %f31, %f388;
|
|
ld.global.f32 %f390, [%rd120+12];
|
|
mul.f32 %f391, %f28, %f390;
|
|
ld.global.f32 %f392, [%rd120+16];
|
|
mul.f32 %f393, %f29, %f392;
|
|
neg.f32 %f394, %f393;
|
|
sub.f32 %f395, %f394, %f391;
|
|
ld.global.f32 %f396, [%rd120+20];
|
|
mul.f32 %f397, %f30, %f396;
|
|
sub.f32 %f398, %f395, %f397;
|
|
cvt.sat.f32.f32 %f399, %f398;
|
|
mul.f32 %f45, %f389, %f399;
|
|
mul.f32 %f400, %f1241, %f29;
|
|
fma.rn.f32 %f401, %f1240, %f28, %f400;
|
|
fma.rn.f32 %f46, %f1242, %f30, %f401;
|
|
setp.leu.f32 %p38, %f45, 0f3727C5AC;
|
|
@%p38 bra $L__BB0_22;
|
|
|
|
cvt.sat.f32.f32 %f411, %f46;
|
|
mov.f32 %f417, 0f38D1B717;
|
|
max.f32 %f408, %f416, %f417;
|
|
sub.f32 %f409, %f27, %f408;
|
|
mov.f32 %f410, 0f00000000;
|
|
mov.u32 %r133, 2;
|
|
mov.u32 %r135, 1;
|
|
mov.u32 %r136, 1065353216;
|
|
mov.u32 %r167, 0;
|
|
// begin inline asm
|
|
call(%r97,%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128),_optix_trace_typed_32,(%r167,%rd5,%f13,%f14,%f15,%f28,%f29,%f30,%f408,%f409,%f410,%r135,%r167,%r135,%r133,%r135,%r135,%r136,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167);
|
|
// end inline asm
|
|
mov.b32 %f418, %r97;
|
|
mul.f32 %f419, %f45, 0f3EA2F983;
|
|
mul.f32 %f420, %f419, %f418;
|
|
fma.rn.f32 %f1257, %f411, %f420, %f1257;
|
|
fma.rn.f32 %f1255, %f28, %f420, %f1255;
|
|
fma.rn.f32 %f1254, %f29, %f420, %f1254;
|
|
fma.rn.f32 %f1253, %f30, %f420, %f1253;
|
|
add.f32 %f1256, %f1256, %f420;
|
|
add.f32 %f1252, %f1252, %f418;
|
|
|
|
$L__BB0_22:
|
|
add.s32 %r451, %r451, 1;
|
|
setp.lt.s32 %p40, %r451, %r4;
|
|
mov.pred %p198, %p17;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_23:
|
|
cvt.rn.f32.s32 %f421, %r451;
|
|
mov.f32 %f422, 0f3F800000;
|
|
max.f32 %f423, %f421, %f422;
|
|
div.rn.f32 %f1293, %f1257, %f423;
|
|
div.rn.f32 %f1288, %f1252, %f423;
|
|
div.rn.f32 %f1292, %f1256, %f423;
|
|
div.rn.f32 %f1291, %f1255, %f423;
|
|
div.rn.f32 %f1290, %f1254, %f423;
|
|
div.rn.f32 %f1289, %f1253, %f423;
|
|
not.pred %p41, %p198;
|
|
@%p41 bra $L__BB0_54;
|
|
|
|
setp.lt.s32 %p42, %r5, 1;
|
|
mov.f32 %f1275, 0f00000000;
|
|
mov.f32 %f1274, %f1275;
|
|
mov.f32 %f1273, %f1275;
|
|
mov.f32 %f1272, %f1275;
|
|
mov.f32 %f1271, %f1275;
|
|
mov.f32 %f1270, %f1275;
|
|
@%p42 bra $L__BB0_53;
|
|
|
|
cvt.rn.f32.s32 %f436, %r6;
|
|
rcp.rn.f32 %f71, %f436;
|
|
mul.f32 %f72, %f13, 0f3456BF95;
|
|
mul.f32 %f73, %f14, 0f3456BF95;
|
|
mul.f32 %f74, %f15, 0f3456BF95;
|
|
mov.u32 %r168, 0;
|
|
ld.const.u64 %rd7, [params+96];
|
|
add.s64 %rd8, %rd1, 24;
|
|
mov.u64 %rd51, __cudart_i2opi_f;
|
|
abs.f32 %f494, %f73;
|
|
abs.f32 %f495, %f72;
|
|
max.f32 %f496, %f495, %f494;
|
|
abs.f32 %f497, %f74;
|
|
max.f32 %f498, %f496, %f497;
|
|
mov.u32 %r452, %r168;
|
|
|
|
$L__BB0_26:
|
|
cvt.rn.f32.s32 %f81, %r452;
|
|
mov.u32 %r454, %r168;
|
|
|
|
$L__BB0_27:
|
|
mad.lo.s32 %r170, %r455, 1664525, 1013904223;
|
|
and.b32 %r171, %r170, 16777215;
|
|
cvt.rn.f32.u32 %f437, %r171;
|
|
fma.rn.f32 %f438, %f437, 0f33800000, %f81;
|
|
mul.f32 %f439, %f71, %f438;
|
|
mad.lo.s32 %r455, %r170, 1664525, 1013904223;
|
|
and.b32 %r172, %r455, 16777215;
|
|
cvt.rn.f32.u32 %f440, %r172;
|
|
cvt.rn.f32.s32 %f441, %r454;
|
|
fma.rn.f32 %f442, %f440, 0f33800000, %f441;
|
|
mul.f32 %f443, %f71, %f442;
|
|
fma.rn.f32 %f444, %f71, %f438, %f439;
|
|
mov.f32 %f445, 0f3F800000;
|
|
sub.f32 %f88, %f445, %f444;
|
|
mul.f32 %f446, %f88, %f88;
|
|
sub.f32 %f447, %f445, %f446;
|
|
mov.f32 %f448, 0f00000000;
|
|
max.f32 %f449, %f448, %f447;
|
|
sqrt.rn.f32 %f89, %f449;
|
|
mul.f32 %f90, %f443, 0f40C90FDB;
|
|
mul.f32 %f450, %f90, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r462, %f450;
|
|
cvt.rn.f32.s32 %f451, %r462;
|
|
mov.f32 %f452, 0fBFC90FDA;
|
|
fma.rn.f32 %f453, %f451, %f452, %f90;
|
|
mov.f32 %f454, 0fB3A22168;
|
|
fma.rn.f32 %f455, %f451, %f454, %f453;
|
|
mov.f32 %f456, 0fA7C234C5;
|
|
fma.rn.f32 %f1279, %f451, %f456, %f455;
|
|
abs.f32 %f92, %f90;
|
|
setp.ltu.f32 %p43, %f92, 0f47CE4780;
|
|
mov.u32 %r459, %r462;
|
|
mov.f32 %f1276, %f1279;
|
|
@%p43 bra $L__BB0_35;
|
|
|
|
setp.eq.f32 %p44, %f92, 0f7F800000;
|
|
@%p44 bra $L__BB0_34;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f459, 0f00000000;
|
|
mul.rn.f32 %f1276, %f90, %f459;
|
|
mov.u32 %r459, 0;
|
|
bra.uni $L__BB0_35;
|
|
|
|
$L__BB0_29:
|
|
mov.b32 %r19, %f90;
|
|
bfe.u32 %r174, %r19, 23, 8;
|
|
add.s32 %r20, %r174, -128;
|
|
shl.b32 %r175, %r19, 8;
|
|
or.b32 %r21, %r175, -2147483648;
|
|
shr.u32 %r22, %r20, 5;
|
|
mov.u64 %rd124, 0;
|
|
mov.u32 %r456, 0;
|
|
mov.u64 %rd122, %rd1;
|
|
mov.u64 %rd123, %rd51;
|
|
|
|
$L__BB0_30:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r176, [%rd123];
|
|
mad.wide.u32 %rd53, %r176, %r21, %rd124;
|
|
shr.u64 %rd124, %rd53, 32;
|
|
st.local.u32 [%rd122], %rd53;
|
|
add.s64 %rd123, %rd123, 4;
|
|
add.s64 %rd122, %rd122, 4;
|
|
add.s32 %r456, %r456, 1;
|
|
setp.ne.s32 %p45, %r456, 6;
|
|
@%p45 bra $L__BB0_30;
|
|
|
|
st.local.u32 [%rd8], %rd124;
|
|
mov.u32 %r177, 4;
|
|
sub.s32 %r25, %r177, %r22;
|
|
mov.u32 %r178, 6;
|
|
sub.s32 %r179, %r178, %r22;
|
|
mul.wide.s32 %rd54, %r179, 4;
|
|
add.s64 %rd55, %rd1, %rd54;
|
|
ld.local.u32 %r457, [%rd55];
|
|
ld.local.u32 %r458, [%rd55+-4];
|
|
and.b32 %r28, %r20, 31;
|
|
setp.eq.s32 %p46, %r28, 0;
|
|
@%p46 bra $L__BB0_33;
|
|
|
|
mov.u32 %r180, 32;
|
|
sub.s32 %r181, %r180, %r28;
|
|
shr.u32 %r182, %r458, %r181;
|
|
shl.b32 %r183, %r457, %r28;
|
|
add.s32 %r457, %r182, %r183;
|
|
mul.wide.s32 %rd56, %r25, 4;
|
|
add.s64 %rd57, %rd1, %rd56;
|
|
ld.local.u32 %r184, [%rd57];
|
|
shr.u32 %r185, %r184, %r181;
|
|
shl.b32 %r186, %r458, %r28;
|
|
add.s32 %r458, %r185, %r186;
|
|
|
|
$L__BB0_33:
|
|
and.b32 %r187, %r19, -2147483648;
|
|
shr.u32 %r188, %r458, 30;
|
|
shl.b32 %r189, %r457, 2;
|
|
or.b32 %r190, %r188, %r189;
|
|
shr.u32 %r191, %r190, 31;
|
|
shr.u32 %r192, %r457, 30;
|
|
add.s32 %r193, %r191, %r192;
|
|
neg.s32 %r194, %r193;
|
|
setp.eq.s32 %p47, %r187, 0;
|
|
selp.b32 %r459, %r193, %r194, %p47;
|
|
setp.ne.s32 %p48, %r191, 0;
|
|
xor.b32 %r195, %r187, -2147483648;
|
|
selp.b32 %r196, %r195, %r187, %p48;
|
|
selp.b32 %r197, -1, 0, %p48;
|
|
xor.b32 %r198, %r190, %r197;
|
|
shl.b32 %r199, %r458, 2;
|
|
xor.b32 %r200, %r199, %r197;
|
|
cvt.u64.u32 %rd58, %r198;
|
|
cvt.u64.u32 %rd59, %r200;
|
|
bfi.b64 %rd60, %rd58, %rd59, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd60;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f457, %fd2;
|
|
setp.eq.s32 %p49, %r196, 0;
|
|
neg.f32 %f458, %f457;
|
|
selp.f32 %f1276, %f457, %f458, %p49;
|
|
|
|
$L__BB0_35:
|
|
add.s32 %r35, %r459, 1;
|
|
and.b32 %r36, %r35, 1;
|
|
setp.eq.s32 %p50, %r36, 0;
|
|
selp.f32 %f96, %f1276, 0f3F800000, %p50;
|
|
mul.rn.f32 %f97, %f1276, %f1276;
|
|
mov.f32 %f1277, 0fB94D4153;
|
|
@%p50 bra $L__BB0_37;
|
|
|
|
mov.f32 %f461, 0fBAB607ED;
|
|
mov.f32 %f462, 0f37CBAC00;
|
|
fma.rn.f32 %f1277, %f462, %f97, %f461;
|
|
|
|
$L__BB0_37:
|
|
selp.f32 %f463, 0f3C0885E4, 0f3D2AAABB, %p50;
|
|
fma.rn.f32 %f464, %f1277, %f97, %f463;
|
|
selp.f32 %f465, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
|
|
fma.rn.f32 %f466, %f464, %f97, %f465;
|
|
mov.f32 %f467, 0f00000000;
|
|
fma.rn.f32 %f468, %f97, %f96, %f467;
|
|
fma.rn.f32 %f1278, %f466, %f468, %f96;
|
|
and.b32 %r202, %r35, 2;
|
|
setp.eq.s32 %p52, %r202, 0;
|
|
@%p52 bra $L__BB0_39;
|
|
|
|
mov.f32 %f470, 0fBF800000;
|
|
fma.rn.f32 %f1278, %f1278, %f470, %f467;
|
|
|
|
$L__BB0_39:
|
|
@%p43 bra $L__BB0_47;
|
|
|
|
setp.eq.f32 %p54, %f92, 0f7F800000;
|
|
@%p54 bra $L__BB0_46;
|
|
bra.uni $L__BB0_41;
|
|
|
|
$L__BB0_46:
|
|
mov.f32 %f473, 0f00000000;
|
|
mul.rn.f32 %f1279, %f90, %f473;
|
|
mov.u32 %r462, 0;
|
|
bra.uni $L__BB0_47;
|
|
|
|
$L__BB0_41:
|
|
mov.b32 %r37, %f90;
|
|
bfe.u32 %r203, %r37, 23, 8;
|
|
add.s32 %r38, %r203, -128;
|
|
shl.b32 %r204, %r37, 8;
|
|
or.b32 %r39, %r204, -2147483648;
|
|
shr.u32 %r40, %r38, 5;
|
|
mov.u64 %rd125, 0;
|
|
mov.u64 %rd126, %rd125;
|
|
|
|
$L__BB0_42:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd63, %rd125, 2;
|
|
mov.u64 %rd64, __cudart_i2opi_f;
|
|
add.s64 %rd65, %rd64, %rd63;
|
|
ld.global.nc.u32 %r205, [%rd65];
|
|
mad.wide.u32 %rd66, %r205, %r39, %rd126;
|
|
shr.u64 %rd126, %rd66, 32;
|
|
add.s64 %rd67, %rd1, %rd63;
|
|
st.local.u32 [%rd67], %rd66;
|
|
cvt.u32.u64 %r206, %rd125;
|
|
add.s32 %r207, %r206, 1;
|
|
cvt.s64.s32 %rd125, %r207;
|
|
setp.ne.s32 %p55, %r207, 6;
|
|
@%p55 bra $L__BB0_42;
|
|
|
|
st.local.u32 [%rd8], %rd126;
|
|
mov.u32 %r208, 4;
|
|
sub.s32 %r41, %r208, %r40;
|
|
mov.u32 %r209, 6;
|
|
sub.s32 %r210, %r209, %r40;
|
|
mul.wide.s32 %rd68, %r210, 4;
|
|
add.s64 %rd69, %rd1, %rd68;
|
|
ld.local.u32 %r460, [%rd69];
|
|
ld.local.u32 %r461, [%rd69+-4];
|
|
and.b32 %r44, %r38, 31;
|
|
setp.eq.s32 %p56, %r44, 0;
|
|
@%p56 bra $L__BB0_45;
|
|
|
|
mov.u32 %r211, 32;
|
|
sub.s32 %r212, %r211, %r44;
|
|
shr.u32 %r213, %r461, %r212;
|
|
shl.b32 %r214, %r460, %r44;
|
|
add.s32 %r460, %r213, %r214;
|
|
mul.wide.s32 %rd70, %r41, 4;
|
|
add.s64 %rd71, %rd1, %rd70;
|
|
ld.local.u32 %r215, [%rd71];
|
|
shr.u32 %r216, %r215, %r212;
|
|
shl.b32 %r217, %r461, %r44;
|
|
add.s32 %r461, %r216, %r217;
|
|
|
|
$L__BB0_45:
|
|
and.b32 %r218, %r37, -2147483648;
|
|
shr.u32 %r219, %r461, 30;
|
|
shl.b32 %r220, %r460, 2;
|
|
or.b32 %r221, %r219, %r220;
|
|
shr.u32 %r222, %r221, 31;
|
|
shr.u32 %r223, %r460, 30;
|
|
add.s32 %r224, %r222, %r223;
|
|
neg.s32 %r225, %r224;
|
|
setp.eq.s32 %p57, %r218, 0;
|
|
selp.b32 %r462, %r224, %r225, %p57;
|
|
setp.ne.s32 %p58, %r222, 0;
|
|
xor.b32 %r226, %r218, -2147483648;
|
|
selp.b32 %r227, %r226, %r218, %p58;
|
|
selp.b32 %r228, -1, 0, %p58;
|
|
xor.b32 %r229, %r221, %r228;
|
|
shl.b32 %r230, %r461, 2;
|
|
xor.b32 %r231, %r230, %r228;
|
|
cvt.u64.u32 %rd72, %r229;
|
|
cvt.u64.u32 %rd73, %r231;
|
|
bfi.b64 %rd74, %rd72, %rd73, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd74;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f471, %fd4;
|
|
setp.eq.s32 %p59, %r227, 0;
|
|
neg.f32 %f472, %f471;
|
|
selp.f32 %f1279, %f471, %f472, %p59;
|
|
|
|
$L__BB0_47:
|
|
mul.f32 %f106, %f89, %f1278;
|
|
and.b32 %r51, %r462, 1;
|
|
setp.eq.s32 %p60, %r51, 0;
|
|
selp.f32 %f107, %f1279, 0f3F800000, %p60;
|
|
mul.rn.f32 %f108, %f1279, %f1279;
|
|
mov.f32 %f1280, 0fB94D4153;
|
|
@%p60 bra $L__BB0_49;
|
|
|
|
mov.f32 %f475, 0fBAB607ED;
|
|
mov.f32 %f476, 0f37CBAC00;
|
|
fma.rn.f32 %f1280, %f476, %f108, %f475;
|
|
|
|
$L__BB0_49:
|
|
selp.f32 %f477, 0f3C0885E4, 0f3D2AAABB, %p60;
|
|
fma.rn.f32 %f478, %f1280, %f108, %f477;
|
|
selp.f32 %f479, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
|
|
fma.rn.f32 %f480, %f478, %f108, %f479;
|
|
mov.f32 %f481, 0f00000000;
|
|
fma.rn.f32 %f482, %f108, %f107, %f481;
|
|
fma.rn.f32 %f1281, %f480, %f482, %f107;
|
|
and.b32 %r233, %r462, 2;
|
|
setp.eq.s32 %p62, %r233, 0;
|
|
@%p62 bra $L__BB0_51;
|
|
|
|
mov.f32 %f484, 0fBF800000;
|
|
fma.rn.f32 %f1281, %f1281, %f484, %f481;
|
|
|
|
$L__BB0_51:
|
|
mov.f32 %f499, 0f38D1B717;
|
|
max.f32 %f491, %f498, %f499;
|
|
mul.f32 %f489, %f89, %f1281;
|
|
mov.f32 %f492, 0f6C4ECB8F;
|
|
mov.u32 %r270, 2;
|
|
mov.u32 %r272, 1;
|
|
mov.u32 %r304, 0;
|
|
// begin inline asm
|
|
call(%r234,%r235,%r236,%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265),_optix_trace_typed_32,(%r304,%rd7,%f13,%f14,%f15,%f106,%f489,%f88,%f491,%f492,%f481,%r272,%r304,%r304,%r270,%r304,%r272,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304);
|
|
// end inline asm
|
|
mov.b32 %f500, %r234;
|
|
setp.lt.f32 %p63, %f500, 0f00000000;
|
|
selp.f32 %f501, 0f00000000, %f500, %p63;
|
|
setp.geu.f32 %p64, %f500, 0f00000000;
|
|
selp.f32 %f502, 0f3F800000, 0f00000000, %p64;
|
|
add.f32 %f1275, %f1275, %f502;
|
|
fma.rn.f32 %f1272, %f106, %f501, %f1272;
|
|
fma.rn.f32 %f1273, %f489, %f501, %f1273;
|
|
fma.rn.f32 %f1274, %f88, %f501, %f1274;
|
|
add.f32 %f1271, %f1271, %f501;
|
|
mul.f32 %f503, %f1241, %f489;
|
|
fma.rn.f32 %f504, %f1240, %f106, %f503;
|
|
fma.rn.f32 %f505, %f1242, %f88, %f504;
|
|
cvt.sat.f32.f32 %f506, %f505;
|
|
fma.rn.f32 %f1270, %f506, %f501, %f1270;
|
|
add.s32 %r454, %r454, 1;
|
|
setp.lt.s32 %p65, %r454, %r6;
|
|
@%p65 bra $L__BB0_27;
|
|
|
|
add.s32 %r452, %r452, 1;
|
|
setp.lt.s32 %p66, %r452, %r6;
|
|
@%p66 bra $L__BB0_26;
|
|
|
|
$L__BB0_53:
|
|
mul.lo.s32 %r305, %r6, %r6;
|
|
cvt.rn.f32.s32 %f507, %r305;
|
|
div.rn.f32 %f508, %f1270, %f507;
|
|
div.rn.f32 %f1288, %f1275, %f507;
|
|
div.rn.f32 %f1292, %f1271, %f507;
|
|
div.rn.f32 %f1291, %f1272, %f507;
|
|
div.rn.f32 %f1290, %f1273, %f507;
|
|
div.rn.f32 %f1289, %f1274, %f507;
|
|
add.f32 %f1293, %f508, %f508;
|
|
|
|
$L__BB0_54:
|
|
ld.const.u32 %r449, [params+616];
|
|
setp.lt.s32 %p67, %r449, 0;
|
|
selp.f32 %f138, %f1293, %f1288, %p67;
|
|
ld.const.u32 %r54, [params+104];
|
|
and.b32 %r306, %r54, 8;
|
|
setp.eq.s32 %p68, %r306, 0;
|
|
@%p68 bra $L__BB0_68;
|
|
|
|
ld.const.u64 %rd76, [params+192];
|
|
cvta.to.global.u64 %rd19, %rd76;
|
|
ld.const.u32 %r307, [params+184];
|
|
mad.lo.s32 %r308, %r307, %r8, %r7;
|
|
cvt.u64.u32 %rd20, %r308;
|
|
mov.f32 %f510, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f511, %f510;
|
|
add.f32 %f512, %f511, %f511;
|
|
mov.f32 %f513, 0f3EE8BA2E;
|
|
sub.f32 %f514, %f513, %f512;
|
|
abs.f32 %f139, %f514;
|
|
abs.f32 %f140, %f138;
|
|
setp.lt.f32 %p69, %f140, 0f00800000;
|
|
mul.f32 %f515, %f140, 0f4B800000;
|
|
selp.f32 %f516, %f515, %f140, %p69;
|
|
selp.f32 %f517, 0fC3170000, 0fC2FE0000, %p69;
|
|
mov.b32 %r309, %f516;
|
|
and.b32 %r310, %r309, 8388607;
|
|
or.b32 %r311, %r310, 1065353216;
|
|
mov.b32 %f518, %r311;
|
|
shr.u32 %r312, %r309, 23;
|
|
cvt.rn.f32.u32 %f519, %r312;
|
|
add.f32 %f520, %f517, %f519;
|
|
setp.gt.f32 %p70, %f518, 0f3FB504F3;
|
|
mul.f32 %f521, %f518, 0f3F000000;
|
|
add.f32 %f522, %f520, 0f3F800000;
|
|
selp.f32 %f523, %f522, %f520, %p70;
|
|
selp.f32 %f524, %f521, %f518, %p70;
|
|
add.f32 %f525, %f524, 0fBF800000;
|
|
add.f32 %f526, %f524, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f527, %f526;
|
|
add.f32 %f528, %f525, %f525;
|
|
mul.f32 %f529, %f528, %f527;
|
|
mul.f32 %f530, %f529, %f529;
|
|
mov.f32 %f531, 0f3C4CAF63;
|
|
mov.f32 %f532, 0f3B18F0FE;
|
|
fma.rn.f32 %f533, %f532, %f530, %f531;
|
|
mov.f32 %f534, 0f3DAAAABD;
|
|
fma.rn.f32 %f535, %f533, %f530, %f534;
|
|
mul.rn.f32 %f536, %f535, %f530;
|
|
mul.rn.f32 %f537, %f536, %f529;
|
|
sub.f32 %f538, %f525, %f529;
|
|
add.f32 %f539, %f538, %f538;
|
|
neg.f32 %f540, %f529;
|
|
fma.rn.f32 %f541, %f540, %f525, %f539;
|
|
mul.rn.f32 %f542, %f527, %f541;
|
|
add.f32 %f543, %f537, %f529;
|
|
sub.f32 %f544, %f529, %f543;
|
|
add.f32 %f545, %f537, %f544;
|
|
add.f32 %f546, %f542, %f545;
|
|
add.f32 %f547, %f543, %f546;
|
|
sub.f32 %f548, %f543, %f547;
|
|
add.f32 %f549, %f546, %f548;
|
|
mov.f32 %f550, 0f3F317200;
|
|
mul.rn.f32 %f551, %f523, %f550;
|
|
mov.f32 %f552, 0f35BFBE8E;
|
|
mul.rn.f32 %f553, %f523, %f552;
|
|
add.f32 %f554, %f551, %f547;
|
|
sub.f32 %f555, %f551, %f554;
|
|
add.f32 %f556, %f547, %f555;
|
|
add.f32 %f557, %f549, %f556;
|
|
add.f32 %f558, %f553, %f557;
|
|
add.f32 %f559, %f554, %f558;
|
|
sub.f32 %f560, %f554, %f559;
|
|
add.f32 %f561, %f558, %f560;
|
|
mul.rn.f32 %f562, %f513, %f559;
|
|
neg.f32 %f563, %f562;
|
|
fma.rn.f32 %f564, %f513, %f559, %f563;
|
|
fma.rn.f32 %f565, %f513, %f561, %f564;
|
|
mov.f32 %f566, 0f00000000;
|
|
fma.rn.f32 %f567, %f566, %f559, %f565;
|
|
add.rn.f32 %f568, %f562, %f567;
|
|
neg.f32 %f569, %f568;
|
|
add.rn.f32 %f570, %f562, %f569;
|
|
add.rn.f32 %f571, %f570, %f567;
|
|
mov.b32 %r313, %f568;
|
|
setp.eq.s32 %p71, %r313, 1118925336;
|
|
add.s32 %r314, %r313, -1;
|
|
mov.b32 %f572, %r314;
|
|
add.f32 %f573, %f571, 0f37000000;
|
|
selp.f32 %f141, %f573, %f571, %p71;
|
|
selp.f32 %f574, %f572, %f568, %p71;
|
|
mov.f32 %f575, 0f3FB8AA3B;
|
|
mul.rn.f32 %f576, %f574, %f575;
|
|
cvt.rzi.f32.f32 %f577, %f576;
|
|
abs.f32 %f578, %f577;
|
|
setp.gt.f32 %p72, %f578, 0f42FC0000;
|
|
mov.b32 %r315, %f577;
|
|
and.b32 %r316, %r315, -2147483648;
|
|
or.b32 %r317, %r316, 1123811328;
|
|
mov.b32 %f579, %r317;
|
|
selp.f32 %f580, %f579, %f577, %p72;
|
|
mov.f32 %f581, 0fBF317218;
|
|
fma.rn.f32 %f582, %f580, %f581, %f574;
|
|
mov.f32 %f583, 0f3102E308;
|
|
fma.rn.f32 %f584, %f580, %f583, %f582;
|
|
mul.f32 %f585, %f584, 0f3FB8AA3B;
|
|
add.f32 %f586, %f580, 0f4B40007F;
|
|
mov.b32 %r318, %f586;
|
|
shl.b32 %r319, %r318, 23;
|
|
mov.b32 %f587, %r319;
|
|
ex2.approx.ftz.f32 %f588, %f585;
|
|
mul.f32 %f142, %f588, %f587;
|
|
setp.eq.f32 %p73, %f142, 0f7F800000;
|
|
mov.f32 %f1294, 0f7F800000;
|
|
@%p73 bra $L__BB0_57;
|
|
|
|
fma.rn.f32 %f1294, %f142, %f141, %f142;
|
|
|
|
$L__BB0_57:
|
|
setp.lt.f32 %p74, %f138, 0f00000000;
|
|
setp.eq.f32 %p75, %f139, 0f3F800000;
|
|
and.pred %p3, %p74, %p75;
|
|
setp.eq.f32 %p76, %f138, 0f00000000;
|
|
@%p76 bra $L__BB0_61;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_61:
|
|
add.f32 %f593, %f138, %f138;
|
|
selp.f32 %f1296, %f593, 0f00000000, %p75;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_165:
|
|
mov.f32 %f1197, 0f00000000;
|
|
mov.u32 %r464, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1197;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1197;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f1197;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs114, 0;
|
|
st.global.v4.u16 [%rd28], {%rs111, %rs112, %rs113, %rs114};
|
|
|
|
$L__BB0_166:
|
|
ld.const.u64 %rd108, [params+256];
|
|
cvta.to.global.u64 %rd109, %rd108;
|
|
ld.const.u32 %r440, [params+248];
|
|
mad.lo.s32 %r441, %r440, %r8, %r7;
|
|
mul.wide.u32 %rd110, %r441, 8;
|
|
add.s64 %rd29, %rd109, %rd110;
|
|
setp.eq.s32 %p194, %r464, 0;
|
|
@%p194 bra $L__BB0_168;
|
|
|
|
ld.global.v4.u16 {%rs121, %rs122, %rs123, %rs124}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1198, %rs121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1199, %rs122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1200, %rs123;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1201, %f1198, 0f00000000;
|
|
add.f32 %f1202, %f1199, 0f00000000;
|
|
add.f32 %f1203, %f1200, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1203;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1202;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1201;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs125, 0;
|
|
st.global.v4.u16 [%rd29], {%rs118, %rs119, %rs120, %rs125};
|
|
bra.uni $L__BB0_169;
|
|
|
|
$L__BB0_168:
|
|
mov.f32 %f1206, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1206;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1206;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1206;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs129, 0;
|
|
st.global.v4.u16 [%rd29], {%rs126, %rs127, %rs128, %rs129};
|
|
|
|
$L__BB0_169:
|
|
ld.const.u64 %rd111, [params+272];
|
|
cvta.to.global.u64 %rd112, %rd111;
|
|
ld.const.u32 %r442, [params+264];
|
|
mad.lo.s32 %r443, %r442, %r8, %r7;
|
|
mul.wide.u32 %rd113, %r443, 8;
|
|
add.s64 %rd30, %rd112, %rd113;
|
|
@%p194 bra $L__BB0_171;
|
|
|
|
ld.global.v4.u16 {%rs136, %rs137, %rs138, %rs139}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1207, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1208, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1209, %rs138;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1210, %f1207, 0f00000000;
|
|
add.f32 %f1211, %f1208, 0f00000000;
|
|
add.f32 %f1212, %f1209, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1211;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1210;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs140, 0;
|
|
st.global.v4.u16 [%rd30], {%rs133, %rs134, %rs135, %rs140};
|
|
bra.uni $L__BB0_172;
|
|
|
|
$L__BB0_171:
|
|
mov.f32 %f1215, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1215;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1215;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1215;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs144, 0;
|
|
st.global.v4.u16 [%rd30], {%rs141, %rs142, %rs143, %rs144};
|
|
|
|
$L__BB0_172:
|
|
ld.const.u64 %rd114, [params+288];
|
|
cvta.to.global.u64 %rd115, %rd114;
|
|
ld.const.u32 %r444, [params+280];
|
|
mad.lo.s32 %r445, %r444, %r8, %r7;
|
|
mul.wide.u32 %rd116, %r445, 8;
|
|
add.s64 %rd31, %rd115, %rd116;
|
|
@%p194 bra $L__BB0_174;
|
|
|
|
ld.global.v4.u16 {%rs151, %rs152, %rs153, %rs154}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1216, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1217, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1218, %rs153;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1219, %f1216, 0f00000000;
|
|
add.f32 %f1220, %f1217, 0f00000000;
|
|
add.f32 %f1221, %f1218, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1220;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1219;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs155, 0;
|
|
st.global.v4.u16 [%rd31], {%rs148, %rs149, %rs150, %rs155};
|
|
bra.uni $L__BB0_175;
|
|
|
|
$L__BB0_174:
|
|
mov.f32 %f1224, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1224;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1224;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1224;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs159, 0;
|
|
st.global.v4.u16 [%rd31], {%rs156, %rs157, %rs158, %rs159};
|
|
|
|
$L__BB0_175:
|
|
ld.const.u64 %rd117, [params+304];
|
|
cvta.to.global.u64 %rd118, %rd117;
|
|
ld.const.u32 %r446, [params+296];
|
|
mad.lo.s32 %r447, %r446, %r8, %r7;
|
|
mul.wide.u32 %rd119, %r447, 8;
|
|
add.s64 %rd32, %rd118, %rd119;
|
|
@%p194 bra $L__BB0_177;
|
|
|
|
ld.global.v4.u16 {%rs166, %rs167, %rs168, %rs169}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1225, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1226, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1227, %rs168;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1228, %f1225, 0f00000000;
|
|
add.f32 %f1229, %f1226, 0f00000000;
|
|
add.f32 %f1230, %f1227, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1230;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1229;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1228;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs170, 0;
|
|
st.global.v4.u16 [%rd32], {%rs163, %rs164, %rs165, %rs170};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_177:
|
|
mov.f32 %f1233, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1233;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs174, 0;
|
|
st.global.v4.u16 [%rd32], {%rs171, %rs172, %rs173, %rs174};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_58:
|
|
mov.b32 %r320, %f1294;
|
|
xor.b32 %r321, %r320, -2147483648;
|
|
mov.b32 %f589, %r321;
|
|
selp.f32 %f1296, %f589, %f1294, %p3;
|
|
setp.geu.f32 %p77, %f138, 0f00000000;
|
|
@%p77 bra $L__BB0_62;
|
|
|
|
mov.f32 %f590, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f591, %f590;
|
|
setp.eq.f32 %p78, %f591, 0f3EE8BA2E;
|
|
@%p78 bra $L__BB0_62;
|
|
|
|
mov.f32 %f1296, 0f7FFFFFFF;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f594, %f140, 0f3EE8BA2E;
|
|
mov.b32 %r322, %f594;
|
|
setp.lt.s32 %p80, %r322, 2139095040;
|
|
@%p80 bra $L__BB0_67;
|
|
|
|
setp.gtu.f32 %p81, %f140, 0f7F800000;
|
|
@%p81 bra $L__BB0_66;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f1296, %f138, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_64:
|
|
setp.neu.f32 %p82, %f140, 0f7F800000;
|
|
@%p82 bra $L__BB0_67;
|
|
|
|
selp.f32 %f1296, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_67:
|
|
mul.f32 %f595, %f1296, 0f437F0000;
|
|
setp.eq.f32 %p83, %f138, 0f3F800000;
|
|
selp.f32 %f596, 0f437F0000, %f595, %p83;
|
|
cvt.rzi.u32.f32 %r323, %f596;
|
|
shl.b64 %rd77, %rd20, 1;
|
|
add.s64 %rd78, %rd19, %rd77;
|
|
cvt.u16.u32 %rs16, %r323;
|
|
mov.u16 %rs17, 255;
|
|
st.global.v2.u8 [%rd78], {%rs16, %rs17};
|
|
|
|
$L__BB0_68:
|
|
ld.const.v2.f32 {%f597, %f598}, [params+648];
|
|
mul.f32 %f153, %f1293, %f597;
|
|
mul.f32 %f154, %f1293, %f598;
|
|
ld.const.f32 %f155, [params+656];
|
|
mul.f32 %f156, %f1293, %f155;
|
|
and.b32 %r324, %r54, 1;
|
|
setp.eq.b32 %p84, %r324, 1;
|
|
mov.pred %p85, 0;
|
|
xor.pred %p86, %p84, %p85;
|
|
not.pred %p87, %p86;
|
|
@%p87 bra $L__BB0_142;
|
|
|
|
mov.f32 %f600, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f601, %f600;
|
|
add.f32 %f602, %f601, %f601;
|
|
mov.f32 %f603, 0f3EE66666;
|
|
sub.f32 %f604, %f603, %f602;
|
|
abs.f32 %f157, %f604;
|
|
abs.f32 %f158, %f153;
|
|
setp.lt.f32 %p88, %f158, 0f00800000;
|
|
mul.f32 %f605, %f158, 0f4B800000;
|
|
selp.f32 %f606, %f605, %f158, %p88;
|
|
selp.f32 %f607, 0fC3170000, 0fC2FE0000, %p88;
|
|
mov.b32 %r325, %f606;
|
|
and.b32 %r326, %r325, 8388607;
|
|
or.b32 %r327, %r326, 1065353216;
|
|
mov.b32 %f608, %r327;
|
|
shr.u32 %r328, %r325, 23;
|
|
cvt.rn.f32.u32 %f609, %r328;
|
|
add.f32 %f610, %f607, %f609;
|
|
setp.gt.f32 %p89, %f608, 0f3FB504F3;
|
|
mul.f32 %f611, %f608, 0f3F000000;
|
|
add.f32 %f612, %f610, 0f3F800000;
|
|
selp.f32 %f613, %f612, %f610, %p89;
|
|
selp.f32 %f614, %f611, %f608, %p89;
|
|
add.f32 %f615, %f614, 0fBF800000;
|
|
add.f32 %f616, %f614, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f617, %f616;
|
|
add.f32 %f618, %f615, %f615;
|
|
mul.f32 %f619, %f618, %f617;
|
|
mul.f32 %f620, %f619, %f619;
|
|
mov.f32 %f621, 0f3C4CAF63;
|
|
mov.f32 %f622, 0f3B18F0FE;
|
|
fma.rn.f32 %f623, %f622, %f620, %f621;
|
|
mov.f32 %f624, 0f3DAAAABD;
|
|
fma.rn.f32 %f625, %f623, %f620, %f624;
|
|
mul.rn.f32 %f626, %f625, %f620;
|
|
mul.rn.f32 %f627, %f626, %f619;
|
|
sub.f32 %f628, %f615, %f619;
|
|
add.f32 %f629, %f628, %f628;
|
|
neg.f32 %f630, %f619;
|
|
fma.rn.f32 %f631, %f630, %f615, %f629;
|
|
mul.rn.f32 %f632, %f617, %f631;
|
|
add.f32 %f633, %f627, %f619;
|
|
sub.f32 %f634, %f619, %f633;
|
|
add.f32 %f635, %f627, %f634;
|
|
add.f32 %f636, %f632, %f635;
|
|
add.f32 %f637, %f633, %f636;
|
|
sub.f32 %f638, %f633, %f637;
|
|
add.f32 %f639, %f636, %f638;
|
|
mov.f32 %f640, 0f3F317200;
|
|
mul.rn.f32 %f641, %f613, %f640;
|
|
mov.f32 %f642, 0f35BFBE8E;
|
|
mul.rn.f32 %f643, %f613, %f642;
|
|
add.f32 %f644, %f641, %f637;
|
|
sub.f32 %f645, %f641, %f644;
|
|
add.f32 %f646, %f637, %f645;
|
|
add.f32 %f647, %f639, %f646;
|
|
add.f32 %f648, %f643, %f647;
|
|
add.f32 %f649, %f644, %f648;
|
|
sub.f32 %f650, %f644, %f649;
|
|
add.f32 %f651, %f648, %f650;
|
|
mul.rn.f32 %f652, %f603, %f649;
|
|
neg.f32 %f653, %f652;
|
|
fma.rn.f32 %f654, %f603, %f649, %f653;
|
|
fma.rn.f32 %f655, %f603, %f651, %f654;
|
|
mov.f32 %f656, 0f00000000;
|
|
fma.rn.f32 %f657, %f656, %f649, %f655;
|
|
add.rn.f32 %f658, %f652, %f657;
|
|
neg.f32 %f659, %f658;
|
|
add.rn.f32 %f660, %f652, %f659;
|
|
add.rn.f32 %f661, %f660, %f657;
|
|
mov.b32 %r329, %f658;
|
|
setp.eq.s32 %p90, %r329, 1118925336;
|
|
add.s32 %r330, %r329, -1;
|
|
mov.b32 %f662, %r330;
|
|
add.f32 %f663, %f661, 0f37000000;
|
|
selp.f32 %f159, %f663, %f661, %p90;
|
|
selp.f32 %f664, %f662, %f658, %p90;
|
|
mov.f32 %f665, 0f3FB8AA3B;
|
|
mul.rn.f32 %f666, %f664, %f665;
|
|
cvt.rzi.f32.f32 %f667, %f666;
|
|
abs.f32 %f668, %f667;
|
|
setp.gt.f32 %p91, %f668, 0f42FC0000;
|
|
mov.b32 %r331, %f667;
|
|
and.b32 %r332, %r331, -2147483648;
|
|
or.b32 %r333, %r332, 1123811328;
|
|
mov.b32 %f669, %r333;
|
|
selp.f32 %f670, %f669, %f667, %p91;
|
|
mov.f32 %f671, 0fBF317218;
|
|
fma.rn.f32 %f672, %f670, %f671, %f664;
|
|
mov.f32 %f673, 0f3102E308;
|
|
fma.rn.f32 %f674, %f670, %f673, %f672;
|
|
mul.f32 %f675, %f674, 0f3FB8AA3B;
|
|
add.f32 %f676, %f670, 0f4B40007F;
|
|
mov.b32 %r334, %f676;
|
|
shl.b32 %r335, %r334, 23;
|
|
mov.b32 %f677, %r335;
|
|
ex2.approx.ftz.f32 %f678, %f675;
|
|
mul.f32 %f160, %f678, %f677;
|
|
setp.eq.f32 %p92, %f160, 0f7F800000;
|
|
mov.f32 %f1297, 0f7F800000;
|
|
@%p92 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f1297, %f160, %f159, %f160;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p93, %f153, 0f00000000;
|
|
setp.eq.f32 %p94, %f157, 0f3F800000;
|
|
and.pred %p4, %p93, %p94;
|
|
setp.eq.f32 %p95, %f153, 0f00000000;
|
|
@%p95 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f683, %f153, %f153;
|
|
selp.f32 %f1299, %f683, 0f00000000, %p94;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r336, %f1297;
|
|
xor.b32 %r337, %r336, -2147483648;
|
|
mov.b32 %f679, %r337;
|
|
selp.f32 %f1299, %f679, %f1297, %p4;
|
|
setp.geu.f32 %p96, %f153, 0f00000000;
|
|
@%p96 bra $L__BB0_76;
|
|
|
|
mov.f32 %f680, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f681, %f680;
|
|
setp.eq.f32 %p97, %f681, 0f3EE66666;
|
|
@%p97 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1299, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f684, %f158, 0f3EE66666;
|
|
mov.b32 %r338, %f684;
|
|
setp.lt.s32 %p99, %r338, 2139095040;
|
|
@%p99 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p100, %f158, 0f7F800000;
|
|
@%p100 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1299, %f153, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p101, %f158, 0f7F800000;
|
|
@%p101 bra $L__BB0_81;
|
|
|
|
selp.f32 %f1299, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p102, %f153, 0f3F800000;
|
|
selp.f32 %f169, 0f3F800000, %f1299, %p102;
|
|
abs.f32 %f170, %f154;
|
|
setp.lt.f32 %p103, %f170, 0f00800000;
|
|
mul.f32 %f686, %f170, 0f4B800000;
|
|
selp.f32 %f687, %f686, %f170, %p103;
|
|
selp.f32 %f688, 0fC3170000, 0fC2FE0000, %p103;
|
|
mov.b32 %r339, %f687;
|
|
and.b32 %r340, %r339, 8388607;
|
|
or.b32 %r341, %r340, 1065353216;
|
|
mov.b32 %f689, %r341;
|
|
shr.u32 %r342, %r339, 23;
|
|
cvt.rn.f32.u32 %f690, %r342;
|
|
add.f32 %f691, %f688, %f690;
|
|
setp.gt.f32 %p104, %f689, 0f3FB504F3;
|
|
mul.f32 %f692, %f689, 0f3F000000;
|
|
add.f32 %f693, %f691, 0f3F800000;
|
|
selp.f32 %f694, %f693, %f691, %p104;
|
|
selp.f32 %f695, %f692, %f689, %p104;
|
|
add.f32 %f696, %f695, 0fBF800000;
|
|
add.f32 %f697, %f695, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f698, %f697;
|
|
add.f32 %f699, %f696, %f696;
|
|
mul.f32 %f700, %f699, %f698;
|
|
mul.f32 %f701, %f700, %f700;
|
|
mov.f32 %f702, 0f3C4CAF63;
|
|
mov.f32 %f703, 0f3B18F0FE;
|
|
fma.rn.f32 %f704, %f703, %f701, %f702;
|
|
mov.f32 %f705, 0f3DAAAABD;
|
|
fma.rn.f32 %f706, %f704, %f701, %f705;
|
|
mul.rn.f32 %f707, %f706, %f701;
|
|
mul.rn.f32 %f708, %f707, %f700;
|
|
sub.f32 %f709, %f696, %f700;
|
|
add.f32 %f710, %f709, %f709;
|
|
neg.f32 %f711, %f700;
|
|
fma.rn.f32 %f712, %f711, %f696, %f710;
|
|
mul.rn.f32 %f713, %f698, %f712;
|
|
add.f32 %f714, %f708, %f700;
|
|
sub.f32 %f715, %f700, %f714;
|
|
add.f32 %f716, %f708, %f715;
|
|
add.f32 %f717, %f713, %f716;
|
|
add.f32 %f718, %f714, %f717;
|
|
sub.f32 %f719, %f714, %f718;
|
|
add.f32 %f720, %f717, %f719;
|
|
mov.f32 %f721, 0f3F317200;
|
|
mul.rn.f32 %f722, %f694, %f721;
|
|
mov.f32 %f723, 0f35BFBE8E;
|
|
mul.rn.f32 %f724, %f694, %f723;
|
|
add.f32 %f725, %f722, %f718;
|
|
sub.f32 %f726, %f722, %f725;
|
|
add.f32 %f727, %f718, %f726;
|
|
add.f32 %f728, %f720, %f727;
|
|
add.f32 %f729, %f724, %f728;
|
|
add.f32 %f730, %f725, %f729;
|
|
sub.f32 %f731, %f725, %f730;
|
|
add.f32 %f732, %f729, %f731;
|
|
mov.f32 %f733, 0f3EE66666;
|
|
mul.rn.f32 %f734, %f733, %f730;
|
|
neg.f32 %f735, %f734;
|
|
fma.rn.f32 %f736, %f733, %f730, %f735;
|
|
fma.rn.f32 %f737, %f733, %f732, %f736;
|
|
mov.f32 %f738, 0f00000000;
|
|
fma.rn.f32 %f739, %f738, %f730, %f737;
|
|
add.rn.f32 %f740, %f734, %f739;
|
|
neg.f32 %f741, %f740;
|
|
add.rn.f32 %f742, %f734, %f741;
|
|
add.rn.f32 %f743, %f742, %f739;
|
|
mov.b32 %r343, %f740;
|
|
setp.eq.s32 %p105, %r343, 1118925336;
|
|
add.s32 %r344, %r343, -1;
|
|
mov.b32 %f744, %r344;
|
|
add.f32 %f745, %f743, 0f37000000;
|
|
selp.f32 %f171, %f745, %f743, %p105;
|
|
selp.f32 %f746, %f744, %f740, %p105;
|
|
mov.f32 %f747, 0f3FB8AA3B;
|
|
mul.rn.f32 %f748, %f746, %f747;
|
|
cvt.rzi.f32.f32 %f749, %f748;
|
|
abs.f32 %f750, %f749;
|
|
setp.gt.f32 %p106, %f750, 0f42FC0000;
|
|
mov.b32 %r345, %f749;
|
|
and.b32 %r346, %r345, -2147483648;
|
|
or.b32 %r347, %r346, 1123811328;
|
|
mov.b32 %f751, %r347;
|
|
selp.f32 %f752, %f751, %f749, %p106;
|
|
mov.f32 %f753, 0fBF317218;
|
|
fma.rn.f32 %f754, %f752, %f753, %f746;
|
|
mov.f32 %f755, 0f3102E308;
|
|
fma.rn.f32 %f756, %f752, %f755, %f754;
|
|
mul.f32 %f757, %f756, 0f3FB8AA3B;
|
|
add.f32 %f758, %f752, 0f4B40007F;
|
|
mov.b32 %r348, %f758;
|
|
shl.b32 %r349, %r348, 23;
|
|
mov.b32 %f759, %r349;
|
|
ex2.approx.ftz.f32 %f760, %f757;
|
|
mul.f32 %f172, %f760, %f759;
|
|
setp.eq.f32 %p107, %f172, 0f7F800000;
|
|
mov.f32 %f1300, 0f7F800000;
|
|
@%p107 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f1300, %f172, %f171, %f172;
|
|
|
|
$L__BB0_83:
|
|
setp.lt.f32 %p108, %f154, 0f00000000;
|
|
and.pred %p5, %p108, %p94;
|
|
setp.eq.f32 %p110, %f154, 0f00000000;
|
|
@%p110 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
add.f32 %f765, %f154, %f154;
|
|
selp.f32 %f1302, %f765, 0f00000000, %p94;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.b32 %r350, %f1300;
|
|
xor.b32 %r351, %r350, -2147483648;
|
|
mov.b32 %f761, %r351;
|
|
selp.f32 %f1302, %f761, %f1300, %p5;
|
|
setp.geu.f32 %p111, %f154, 0f00000000;
|
|
@%p111 bra $L__BB0_88;
|
|
|
|
mov.f32 %f762, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f763, %f762;
|
|
setp.eq.f32 %p112, %f763, 0f3EE66666;
|
|
@%p112 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1302, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
add.f32 %f766, %f170, 0f3EE66666;
|
|
mov.b32 %r352, %f766;
|
|
setp.lt.s32 %p114, %r352, 2139095040;
|
|
@%p114 bra $L__BB0_93;
|
|
|
|
setp.gtu.f32 %p115, %f170, 0f7F800000;
|
|
@%p115 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f1302, %f154, 0f3EE66666;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
setp.neu.f32 %p116, %f170, 0f7F800000;
|
|
@%p116 bra $L__BB0_93;
|
|
|
|
selp.f32 %f1302, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_93:
|
|
setp.eq.f32 %p117, %f154, 0f3F800000;
|
|
selp.f32 %f181, 0f3F800000, %f1302, %p117;
|
|
abs.f32 %f182, %f156;
|
|
setp.lt.f32 %p118, %f182, 0f00800000;
|
|
mul.f32 %f768, %f182, 0f4B800000;
|
|
selp.f32 %f769, %f768, %f182, %p118;
|
|
selp.f32 %f770, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r353, %f769;
|
|
and.b32 %r354, %r353, 8388607;
|
|
or.b32 %r355, %r354, 1065353216;
|
|
mov.b32 %f771, %r355;
|
|
shr.u32 %r356, %r353, 23;
|
|
cvt.rn.f32.u32 %f772, %r356;
|
|
add.f32 %f773, %f770, %f772;
|
|
setp.gt.f32 %p119, %f771, 0f3FB504F3;
|
|
mul.f32 %f774, %f771, 0f3F000000;
|
|
add.f32 %f775, %f773, 0f3F800000;
|
|
selp.f32 %f776, %f775, %f773, %p119;
|
|
selp.f32 %f777, %f774, %f771, %p119;
|
|
add.f32 %f778, %f777, 0fBF800000;
|
|
add.f32 %f779, %f777, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f780, %f779;
|
|
add.f32 %f781, %f778, %f778;
|
|
mul.f32 %f782, %f781, %f780;
|
|
mul.f32 %f783, %f782, %f782;
|
|
mov.f32 %f784, 0f3C4CAF63;
|
|
mov.f32 %f785, 0f3B18F0FE;
|
|
fma.rn.f32 %f786, %f785, %f783, %f784;
|
|
mov.f32 %f787, 0f3DAAAABD;
|
|
fma.rn.f32 %f788, %f786, %f783, %f787;
|
|
mul.rn.f32 %f789, %f788, %f783;
|
|
mul.rn.f32 %f790, %f789, %f782;
|
|
sub.f32 %f791, %f778, %f782;
|
|
add.f32 %f792, %f791, %f791;
|
|
neg.f32 %f793, %f782;
|
|
fma.rn.f32 %f794, %f793, %f778, %f792;
|
|
mul.rn.f32 %f795, %f780, %f794;
|
|
add.f32 %f796, %f790, %f782;
|
|
sub.f32 %f797, %f782, %f796;
|
|
add.f32 %f798, %f790, %f797;
|
|
add.f32 %f799, %f795, %f798;
|
|
add.f32 %f800, %f796, %f799;
|
|
sub.f32 %f801, %f796, %f800;
|
|
add.f32 %f802, %f799, %f801;
|
|
mov.f32 %f803, 0f3F317200;
|
|
mul.rn.f32 %f804, %f776, %f803;
|
|
mov.f32 %f805, 0f35BFBE8E;
|
|
mul.rn.f32 %f806, %f776, %f805;
|
|
add.f32 %f807, %f804, %f800;
|
|
sub.f32 %f808, %f804, %f807;
|
|
add.f32 %f809, %f800, %f808;
|
|
add.f32 %f810, %f802, %f809;
|
|
add.f32 %f811, %f806, %f810;
|
|
add.f32 %f812, %f807, %f811;
|
|
sub.f32 %f813, %f807, %f812;
|
|
add.f32 %f814, %f811, %f813;
|
|
mov.f32 %f815, 0f3EE66666;
|
|
mul.rn.f32 %f816, %f815, %f812;
|
|
neg.f32 %f817, %f816;
|
|
fma.rn.f32 %f818, %f815, %f812, %f817;
|
|
fma.rn.f32 %f819, %f815, %f814, %f818;
|
|
mov.f32 %f820, 0f00000000;
|
|
fma.rn.f32 %f821, %f820, %f812, %f819;
|
|
add.rn.f32 %f822, %f816, %f821;
|
|
neg.f32 %f823, %f822;
|
|
add.rn.f32 %f824, %f816, %f823;
|
|
add.rn.f32 %f825, %f824, %f821;
|
|
mov.b32 %r357, %f822;
|
|
setp.eq.s32 %p120, %r357, 1118925336;
|
|
add.s32 %r358, %r357, -1;
|
|
mov.b32 %f826, %r358;
|
|
add.f32 %f827, %f825, 0f37000000;
|
|
selp.f32 %f183, %f827, %f825, %p120;
|
|
selp.f32 %f828, %f826, %f822, %p120;
|
|
mov.f32 %f829, 0f3FB8AA3B;
|
|
mul.rn.f32 %f830, %f828, %f829;
|
|
cvt.rzi.f32.f32 %f831, %f830;
|
|
abs.f32 %f832, %f831;
|
|
setp.gt.f32 %p121, %f832, 0f42FC0000;
|
|
mov.b32 %r359, %f831;
|
|
and.b32 %r360, %r359, -2147483648;
|
|
or.b32 %r361, %r360, 1123811328;
|
|
mov.b32 %f833, %r361;
|
|
selp.f32 %f834, %f833, %f831, %p121;
|
|
mov.f32 %f835, 0fBF317218;
|
|
fma.rn.f32 %f836, %f834, %f835, %f828;
|
|
mov.f32 %f837, 0f3102E308;
|
|
fma.rn.f32 %f838, %f834, %f837, %f836;
|
|
mul.f32 %f839, %f838, 0f3FB8AA3B;
|
|
add.f32 %f840, %f834, 0f4B40007F;
|
|
mov.b32 %r362, %f840;
|
|
shl.b32 %r363, %r362, 23;
|
|
mov.b32 %f841, %r363;
|
|
ex2.approx.ftz.f32 %f842, %f839;
|
|
mul.f32 %f184, %f842, %f841;
|
|
setp.eq.f32 %p122, %f184, 0f7F800000;
|
|
mov.f32 %f1303, 0f7F800000;
|
|
@%p122 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f1303, %f184, %f183, %f184;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p123, %f156, 0f00000000;
|
|
and.pred %p6, %p123, %p94;
|
|
setp.eq.f32 %p125, %f156, 0f00000000;
|
|
@%p125 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f847, %f156, %f156;
|
|
selp.f32 %f1305, %f847, 0f00000000, %p94;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r364, %f1303;
|
|
xor.b32 %r365, %r364, -2147483648;
|
|
mov.b32 %f843, %r365;
|
|
selp.f32 %f1305, %f843, %f1303, %p6;
|
|
setp.geu.f32 %p126, %f156, 0f00000000;
|
|
@%p126 bra $L__BB0_100;
|
|
|
|
mov.f32 %f844, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f845, %f844;
|
|
setp.eq.f32 %p127, %f845, 0f3EE66666;
|
|
@%p127 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1305, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
add.f32 %f848, %f182, 0f3EE66666;
|
|
mov.b32 %r366, %f848;
|
|
setp.lt.s32 %p129, %r366, 2139095040;
|
|
@%p129 bra $L__BB0_105;
|
|
|
|
setp.gtu.f32 %p130, %f182, 0f7F800000;
|
|
@%p130 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1305, %f156, 0f3EE66666;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
setp.neu.f32 %p131, %f182, 0f7F800000;
|
|
@%p131 bra $L__BB0_105;
|
|
|
|
selp.f32 %f1305, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_105:
|
|
setp.eq.f32 %p132, %f156, 0f3F800000;
|
|
mov.f32 %f850, 0f3F800000;
|
|
selp.f32 %f851, 0f3F800000, %f1305, %p132;
|
|
ld.const.u64 %rd79, [params+144];
|
|
cvta.to.global.u64 %rd21, %rd79;
|
|
ld.const.u32 %r367, [params+136];
|
|
mad.lo.s32 %r368, %r367, %r8, %r7;
|
|
cvt.u64.u32 %rd22, %r368;
|
|
min.f32 %f852, %f169, %f850;
|
|
mov.f32 %f853, 0f00000000;
|
|
max.f32 %f193, %f853, %f852;
|
|
min.f32 %f854, %f181, %f850;
|
|
max.f32 %f194, %f853, %f854;
|
|
min.f32 %f855, %f851, %f850;
|
|
max.f32 %f195, %f853, %f855;
|
|
mov.f32 %f856, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f857, %f856;
|
|
add.f32 %f858, %f857, %f857;
|
|
mov.f32 %f859, 0f3ED55555;
|
|
sub.f32 %f860, %f859, %f858;
|
|
abs.f32 %f196, %f860;
|
|
abs.f32 %f197, %f193;
|
|
setp.lt.f32 %p133, %f197, 0f00800000;
|
|
mul.f32 %f861, %f197, 0f4B800000;
|
|
selp.f32 %f862, %f861, %f197, %p133;
|
|
selp.f32 %f863, 0fC3170000, 0fC2FE0000, %p133;
|
|
mov.b32 %r369, %f862;
|
|
and.b32 %r370, %r369, 8388607;
|
|
or.b32 %r371, %r370, 1065353216;
|
|
mov.b32 %f864, %r371;
|
|
shr.u32 %r372, %r369, 23;
|
|
cvt.rn.f32.u32 %f865, %r372;
|
|
add.f32 %f866, %f863, %f865;
|
|
setp.gt.f32 %p134, %f864, 0f3FB504F3;
|
|
mul.f32 %f867, %f864, 0f3F000000;
|
|
add.f32 %f868, %f866, 0f3F800000;
|
|
selp.f32 %f869, %f868, %f866, %p134;
|
|
selp.f32 %f870, %f867, %f864, %p134;
|
|
add.f32 %f871, %f870, 0fBF800000;
|
|
add.f32 %f872, %f870, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f873, %f872;
|
|
add.f32 %f874, %f871, %f871;
|
|
mul.f32 %f875, %f874, %f873;
|
|
mul.f32 %f876, %f875, %f875;
|
|
mov.f32 %f877, 0f3C4CAF63;
|
|
mov.f32 %f878, 0f3B18F0FE;
|
|
fma.rn.f32 %f879, %f878, %f876, %f877;
|
|
mov.f32 %f880, 0f3DAAAABD;
|
|
fma.rn.f32 %f881, %f879, %f876, %f880;
|
|
mul.rn.f32 %f882, %f881, %f876;
|
|
mul.rn.f32 %f883, %f882, %f875;
|
|
sub.f32 %f884, %f871, %f875;
|
|
add.f32 %f885, %f884, %f884;
|
|
neg.f32 %f886, %f875;
|
|
fma.rn.f32 %f887, %f886, %f871, %f885;
|
|
mul.rn.f32 %f888, %f873, %f887;
|
|
add.f32 %f889, %f883, %f875;
|
|
sub.f32 %f890, %f875, %f889;
|
|
add.f32 %f891, %f883, %f890;
|
|
add.f32 %f892, %f888, %f891;
|
|
add.f32 %f893, %f889, %f892;
|
|
sub.f32 %f894, %f889, %f893;
|
|
add.f32 %f895, %f892, %f894;
|
|
mov.f32 %f896, 0f3F317200;
|
|
mul.rn.f32 %f897, %f869, %f896;
|
|
mov.f32 %f898, 0f35BFBE8E;
|
|
mul.rn.f32 %f899, %f869, %f898;
|
|
add.f32 %f900, %f897, %f893;
|
|
sub.f32 %f901, %f897, %f900;
|
|
add.f32 %f902, %f893, %f901;
|
|
add.f32 %f903, %f895, %f902;
|
|
add.f32 %f904, %f899, %f903;
|
|
add.f32 %f905, %f900, %f904;
|
|
sub.f32 %f906, %f900, %f905;
|
|
add.f32 %f907, %f904, %f906;
|
|
mul.rn.f32 %f908, %f859, %f905;
|
|
neg.f32 %f909, %f908;
|
|
fma.rn.f32 %f910, %f859, %f905, %f909;
|
|
fma.rn.f32 %f911, %f859, %f907, %f910;
|
|
fma.rn.f32 %f912, %f853, %f905, %f911;
|
|
add.rn.f32 %f913, %f908, %f912;
|
|
neg.f32 %f914, %f913;
|
|
add.rn.f32 %f915, %f908, %f914;
|
|
add.rn.f32 %f916, %f915, %f912;
|
|
mov.b32 %r373, %f913;
|
|
setp.eq.s32 %p135, %r373, 1118925336;
|
|
add.s32 %r374, %r373, -1;
|
|
mov.b32 %f917, %r374;
|
|
add.f32 %f918, %f916, 0f37000000;
|
|
selp.f32 %f198, %f918, %f916, %p135;
|
|
selp.f32 %f919, %f917, %f913, %p135;
|
|
mov.f32 %f920, 0f3FB8AA3B;
|
|
mul.rn.f32 %f921, %f919, %f920;
|
|
cvt.rzi.f32.f32 %f922, %f921;
|
|
abs.f32 %f923, %f922;
|
|
setp.gt.f32 %p136, %f923, 0f42FC0000;
|
|
mov.b32 %r375, %f922;
|
|
and.b32 %r376, %r375, -2147483648;
|
|
or.b32 %r377, %r376, 1123811328;
|
|
mov.b32 %f924, %r377;
|
|
selp.f32 %f925, %f924, %f922, %p136;
|
|
mov.f32 %f926, 0fBF317218;
|
|
fma.rn.f32 %f927, %f925, %f926, %f919;
|
|
mov.f32 %f928, 0f3102E308;
|
|
fma.rn.f32 %f929, %f925, %f928, %f927;
|
|
mul.f32 %f930, %f929, 0f3FB8AA3B;
|
|
add.f32 %f931, %f925, 0f4B40007F;
|
|
mov.b32 %r378, %f931;
|
|
shl.b32 %r379, %r378, 23;
|
|
mov.b32 %f932, %r379;
|
|
ex2.approx.ftz.f32 %f933, %f930;
|
|
mul.f32 %f199, %f933, %f932;
|
|
setp.eq.f32 %p137, %f199, 0f7F800000;
|
|
mov.f32 %f1306, 0f7F800000;
|
|
@%p137 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f1306, %f199, %f198, %f199;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p138, %f193, 0f00000000;
|
|
setp.eq.f32 %p139, %f196, 0f3F800000;
|
|
and.pred %p7, %p138, %p139;
|
|
setp.eq.f32 %p140, %f193, 0f00000000;
|
|
@%p140 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f938, %f193, %f193;
|
|
selp.f32 %f1308, %f938, 0f00000000, %p139;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r380, %f1306;
|
|
xor.b32 %r381, %r380, -2147483648;
|
|
mov.b32 %f934, %r381;
|
|
selp.f32 %f1308, %f934, %f1306, %p7;
|
|
setp.geu.f32 %p141, %f193, 0f00000000;
|
|
@%p141 bra $L__BB0_112;
|
|
|
|
mov.f32 %f935, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f936, %f935;
|
|
setp.eq.f32 %p142, %f936, 0f3ED55555;
|
|
@%p142 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1308, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
add.f32 %f939, %f197, 0f3ED55555;
|
|
mov.b32 %r382, %f939;
|
|
setp.lt.s32 %p144, %r382, 2139095040;
|
|
@%p144 bra $L__BB0_117;
|
|
|
|
setp.gtu.f32 %p145, %f197, 0f7F800000;
|
|
@%p145 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1308, %f193, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
setp.neu.f32 %p146, %f197, 0f7F800000;
|
|
@%p146 bra $L__BB0_117;
|
|
|
|
selp.f32 %f1308, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_117:
|
|
abs.f32 %f208, %f194;
|
|
setp.lt.f32 %p147, %f208, 0f00800000;
|
|
mul.f32 %f941, %f208, 0f4B800000;
|
|
selp.f32 %f942, %f941, %f208, %p147;
|
|
selp.f32 %f943, 0fC3170000, 0fC2FE0000, %p147;
|
|
mov.b32 %r383, %f942;
|
|
and.b32 %r384, %r383, 8388607;
|
|
or.b32 %r385, %r384, 1065353216;
|
|
mov.b32 %f944, %r385;
|
|
shr.u32 %r386, %r383, 23;
|
|
cvt.rn.f32.u32 %f945, %r386;
|
|
add.f32 %f946, %f943, %f945;
|
|
setp.gt.f32 %p148, %f944, 0f3FB504F3;
|
|
mul.f32 %f947, %f944, 0f3F000000;
|
|
add.f32 %f948, %f946, 0f3F800000;
|
|
selp.f32 %f949, %f948, %f946, %p148;
|
|
selp.f32 %f950, %f947, %f944, %p148;
|
|
add.f32 %f951, %f950, 0fBF800000;
|
|
add.f32 %f952, %f950, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f953, %f952;
|
|
add.f32 %f954, %f951, %f951;
|
|
mul.f32 %f955, %f954, %f953;
|
|
mul.f32 %f956, %f955, %f955;
|
|
mov.f32 %f957, 0f3C4CAF63;
|
|
mov.f32 %f958, 0f3B18F0FE;
|
|
fma.rn.f32 %f959, %f958, %f956, %f957;
|
|
mov.f32 %f960, 0f3DAAAABD;
|
|
fma.rn.f32 %f961, %f959, %f956, %f960;
|
|
mul.rn.f32 %f962, %f961, %f956;
|
|
mul.rn.f32 %f963, %f962, %f955;
|
|
sub.f32 %f964, %f951, %f955;
|
|
add.f32 %f965, %f964, %f964;
|
|
neg.f32 %f966, %f955;
|
|
fma.rn.f32 %f967, %f966, %f951, %f965;
|
|
mul.rn.f32 %f968, %f953, %f967;
|
|
add.f32 %f969, %f963, %f955;
|
|
sub.f32 %f970, %f955, %f969;
|
|
add.f32 %f971, %f963, %f970;
|
|
add.f32 %f972, %f968, %f971;
|
|
add.f32 %f973, %f969, %f972;
|
|
sub.f32 %f974, %f969, %f973;
|
|
add.f32 %f975, %f972, %f974;
|
|
mov.f32 %f976, 0f3F317200;
|
|
mul.rn.f32 %f977, %f949, %f976;
|
|
mov.f32 %f978, 0f35BFBE8E;
|
|
mul.rn.f32 %f979, %f949, %f978;
|
|
add.f32 %f980, %f977, %f973;
|
|
sub.f32 %f981, %f977, %f980;
|
|
add.f32 %f982, %f973, %f981;
|
|
add.f32 %f983, %f975, %f982;
|
|
add.f32 %f984, %f979, %f983;
|
|
add.f32 %f985, %f980, %f984;
|
|
sub.f32 %f986, %f980, %f985;
|
|
add.f32 %f987, %f984, %f986;
|
|
mov.f32 %f988, 0f3ED55555;
|
|
mul.rn.f32 %f989, %f988, %f985;
|
|
neg.f32 %f990, %f989;
|
|
fma.rn.f32 %f991, %f988, %f985, %f990;
|
|
fma.rn.f32 %f992, %f988, %f987, %f991;
|
|
mov.f32 %f993, 0f00000000;
|
|
fma.rn.f32 %f994, %f993, %f985, %f992;
|
|
add.rn.f32 %f995, %f989, %f994;
|
|
neg.f32 %f996, %f995;
|
|
add.rn.f32 %f997, %f989, %f996;
|
|
add.rn.f32 %f998, %f997, %f994;
|
|
mov.b32 %r387, %f995;
|
|
setp.eq.s32 %p149, %r387, 1118925336;
|
|
add.s32 %r388, %r387, -1;
|
|
mov.b32 %f999, %r388;
|
|
add.f32 %f1000, %f998, 0f37000000;
|
|
selp.f32 %f209, %f1000, %f998, %p149;
|
|
selp.f32 %f1001, %f999, %f995, %p149;
|
|
mov.f32 %f1002, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1003, %f1001, %f1002;
|
|
cvt.rzi.f32.f32 %f1004, %f1003;
|
|
abs.f32 %f1005, %f1004;
|
|
setp.gt.f32 %p150, %f1005, 0f42FC0000;
|
|
mov.b32 %r389, %f1004;
|
|
and.b32 %r390, %r389, -2147483648;
|
|
or.b32 %r391, %r390, 1123811328;
|
|
mov.b32 %f1006, %r391;
|
|
selp.f32 %f1007, %f1006, %f1004, %p150;
|
|
mov.f32 %f1008, 0fBF317218;
|
|
fma.rn.f32 %f1009, %f1007, %f1008, %f1001;
|
|
mov.f32 %f1010, 0f3102E308;
|
|
fma.rn.f32 %f1011, %f1007, %f1010, %f1009;
|
|
mul.f32 %f1012, %f1011, 0f3FB8AA3B;
|
|
add.f32 %f1013, %f1007, 0f4B40007F;
|
|
mov.b32 %r392, %f1013;
|
|
shl.b32 %r393, %r392, 23;
|
|
mov.b32 %f1014, %r393;
|
|
ex2.approx.ftz.f32 %f1015, %f1012;
|
|
mul.f32 %f210, %f1015, %f1014;
|
|
setp.eq.f32 %p151, %f210, 0f7F800000;
|
|
mov.f32 %f1309, 0f7F800000;
|
|
@%p151 bra $L__BB0_119;
|
|
|
|
fma.rn.f32 %f1309, %f210, %f209, %f210;
|
|
|
|
$L__BB0_119:
|
|
setp.lt.f32 %p152, %f194, 0f00000000;
|
|
and.pred %p8, %p152, %p139;
|
|
setp.eq.f32 %p154, %f194, 0f00000000;
|
|
@%p154 bra $L__BB0_123;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_123:
|
|
add.f32 %f1020, %f194, %f194;
|
|
selp.f32 %f1311, %f1020, 0f00000000, %p139;
|
|
bra.uni $L__BB0_124;
|
|
|
|
$L__BB0_120:
|
|
mov.b32 %r394, %f1309;
|
|
xor.b32 %r395, %r394, -2147483648;
|
|
mov.b32 %f1016, %r395;
|
|
selp.f32 %f1311, %f1016, %f1309, %p8;
|
|
setp.geu.f32 %p155, %f194, 0f00000000;
|
|
@%p155 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1017, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1018, %f1017;
|
|
setp.eq.f32 %p156, %f1018, 0f3ED55555;
|
|
@%p156 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1311, 0f7FFFFFFF;
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1021, %f208, 0f3ED55555;
|
|
mov.b32 %r396, %f1021;
|
|
setp.lt.s32 %p158, %r396, 2139095040;
|
|
@%p158 bra $L__BB0_129;
|
|
|
|
setp.gtu.f32 %p159, %f208, 0f7F800000;
|
|
@%p159 bra $L__BB0_128;
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f1311, %f194, 0f3ED55555;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_126:
|
|
setp.neu.f32 %p160, %f208, 0f7F800000;
|
|
@%p160 bra $L__BB0_129;
|
|
|
|
selp.f32 %f1311, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_129:
|
|
abs.f32 %f219, %f195;
|
|
setp.lt.f32 %p161, %f219, 0f00800000;
|
|
mul.f32 %f1023, %f219, 0f4B800000;
|
|
selp.f32 %f1024, %f1023, %f219, %p161;
|
|
selp.f32 %f1025, 0fC3170000, 0fC2FE0000, %p161;
|
|
mov.b32 %r397, %f1024;
|
|
and.b32 %r398, %r397, 8388607;
|
|
or.b32 %r399, %r398, 1065353216;
|
|
mov.b32 %f1026, %r399;
|
|
shr.u32 %r400, %r397, 23;
|
|
cvt.rn.f32.u32 %f1027, %r400;
|
|
add.f32 %f1028, %f1025, %f1027;
|
|
setp.gt.f32 %p162, %f1026, 0f3FB504F3;
|
|
mul.f32 %f1029, %f1026, 0f3F000000;
|
|
add.f32 %f1030, %f1028, 0f3F800000;
|
|
selp.f32 %f1031, %f1030, %f1028, %p162;
|
|
selp.f32 %f1032, %f1029, %f1026, %p162;
|
|
add.f32 %f1033, %f1032, 0fBF800000;
|
|
add.f32 %f1034, %f1032, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1035, %f1034;
|
|
add.f32 %f1036, %f1033, %f1033;
|
|
mul.f32 %f1037, %f1036, %f1035;
|
|
mul.f32 %f1038, %f1037, %f1037;
|
|
mov.f32 %f1039, 0f3C4CAF63;
|
|
mov.f32 %f1040, 0f3B18F0FE;
|
|
fma.rn.f32 %f1041, %f1040, %f1038, %f1039;
|
|
mov.f32 %f1042, 0f3DAAAABD;
|
|
fma.rn.f32 %f1043, %f1041, %f1038, %f1042;
|
|
mul.rn.f32 %f1044, %f1043, %f1038;
|
|
mul.rn.f32 %f1045, %f1044, %f1037;
|
|
sub.f32 %f1046, %f1033, %f1037;
|
|
add.f32 %f1047, %f1046, %f1046;
|
|
neg.f32 %f1048, %f1037;
|
|
fma.rn.f32 %f1049, %f1048, %f1033, %f1047;
|
|
mul.rn.f32 %f1050, %f1035, %f1049;
|
|
add.f32 %f1051, %f1045, %f1037;
|
|
sub.f32 %f1052, %f1037, %f1051;
|
|
add.f32 %f1053, %f1045, %f1052;
|
|
add.f32 %f1054, %f1050, %f1053;
|
|
add.f32 %f1055, %f1051, %f1054;
|
|
sub.f32 %f1056, %f1051, %f1055;
|
|
add.f32 %f1057, %f1054, %f1056;
|
|
mov.f32 %f1058, 0f3F317200;
|
|
mul.rn.f32 %f1059, %f1031, %f1058;
|
|
mov.f32 %f1060, 0f35BFBE8E;
|
|
mul.rn.f32 %f1061, %f1031, %f1060;
|
|
add.f32 %f1062, %f1059, %f1055;
|
|
sub.f32 %f1063, %f1059, %f1062;
|
|
add.f32 %f1064, %f1055, %f1063;
|
|
add.f32 %f1065, %f1057, %f1064;
|
|
add.f32 %f1066, %f1061, %f1065;
|
|
add.f32 %f1067, %f1062, %f1066;
|
|
sub.f32 %f1068, %f1062, %f1067;
|
|
add.f32 %f1069, %f1066, %f1068;
|
|
mov.f32 %f1070, 0f3ED55555;
|
|
mul.rn.f32 %f1071, %f1070, %f1067;
|
|
neg.f32 %f1072, %f1071;
|
|
fma.rn.f32 %f1073, %f1070, %f1067, %f1072;
|
|
fma.rn.f32 %f1074, %f1070, %f1069, %f1073;
|
|
mov.f32 %f1075, 0f00000000;
|
|
fma.rn.f32 %f1076, %f1075, %f1067, %f1074;
|
|
add.rn.f32 %f1077, %f1071, %f1076;
|
|
neg.f32 %f1078, %f1077;
|
|
add.rn.f32 %f1079, %f1071, %f1078;
|
|
add.rn.f32 %f1080, %f1079, %f1076;
|
|
mov.b32 %r401, %f1077;
|
|
setp.eq.s32 %p163, %r401, 1118925336;
|
|
add.s32 %r402, %r401, -1;
|
|
mov.b32 %f1081, %r402;
|
|
add.f32 %f1082, %f1080, 0f37000000;
|
|
selp.f32 %f220, %f1082, %f1080, %p163;
|
|
selp.f32 %f1083, %f1081, %f1077, %p163;
|
|
mov.f32 %f1084, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1085, %f1083, %f1084;
|
|
cvt.rzi.f32.f32 %f1086, %f1085;
|
|
abs.f32 %f1087, %f1086;
|
|
setp.gt.f32 %p164, %f1087, 0f42FC0000;
|
|
mov.b32 %r403, %f1086;
|
|
and.b32 %r404, %r403, -2147483648;
|
|
or.b32 %r405, %r404, 1123811328;
|
|
mov.b32 %f1088, %r405;
|
|
selp.f32 %f1089, %f1088, %f1086, %p164;
|
|
mov.f32 %f1090, 0fBF317218;
|
|
fma.rn.f32 %f1091, %f1089, %f1090, %f1083;
|
|
mov.f32 %f1092, 0f3102E308;
|
|
fma.rn.f32 %f1093, %f1089, %f1092, %f1091;
|
|
mul.f32 %f1094, %f1093, 0f3FB8AA3B;
|
|
add.f32 %f1095, %f1089, 0f4B40007F;
|
|
mov.b32 %r406, %f1095;
|
|
shl.b32 %r407, %r406, 23;
|
|
mov.b32 %f1096, %r407;
|
|
ex2.approx.ftz.f32 %f1097, %f1094;
|
|
mul.f32 %f221, %f1097, %f1096;
|
|
setp.eq.f32 %p165, %f221, 0f7F800000;
|
|
mov.f32 %f1312, 0f7F800000;
|
|
@%p165 bra $L__BB0_131;
|
|
|
|
fma.rn.f32 %f1312, %f221, %f220, %f221;
|
|
|
|
$L__BB0_131:
|
|
setp.lt.f32 %p166, %f195, 0f00000000;
|
|
and.pred %p9, %p166, %p139;
|
|
setp.eq.f32 %p168, %f195, 0f00000000;
|
|
@%p168 bra $L__BB0_135;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_135:
|
|
add.f32 %f1102, %f195, %f195;
|
|
selp.f32 %f1314, %f1102, 0f00000000, %p139;
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_132:
|
|
mov.b32 %r408, %f1312;
|
|
xor.b32 %r409, %r408, -2147483648;
|
|
mov.b32 %f1098, %r409;
|
|
selp.f32 %f1314, %f1098, %f1312, %p9;
|
|
setp.geu.f32 %p169, %f195, 0f00000000;
|
|
@%p169 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1099, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1100, %f1099;
|
|
setp.eq.f32 %p170, %f1100, 0f3ED55555;
|
|
@%p170 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1314, 0f7FFFFFFF;
|
|
|
|
$L__BB0_136:
|
|
add.f32 %f1103, %f219, 0f3ED55555;
|
|
mov.b32 %r410, %f1103;
|
|
setp.lt.s32 %p172, %r410, 2139095040;
|
|
@%p172 bra $L__BB0_141;
|
|
|
|
setp.gtu.f32 %p173, %f219, 0f7F800000;
|
|
@%p173 bra $L__BB0_140;
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f1314, %f195, 0f3ED55555;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_138:
|
|
setp.neu.f32 %p174, %f219, 0f7F800000;
|
|
@%p174 bra $L__BB0_141;
|
|
|
|
selp.f32 %f1314, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_141:
|
|
fma.rn.f32 %f1104, %f1308, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p175, %f193, 0f3F800000;
|
|
mov.f32 %f1105, 0f3F800000;
|
|
selp.f32 %f1106, 0f3F7FFFFF, %f1104, %p175;
|
|
mul.f32 %f1107, %f193, 0f414EB852;
|
|
setp.lt.f32 %p176, %f193, 0f3B4D2E1C;
|
|
selp.f32 %f1108, %f1107, %f1106, %p176;
|
|
fma.rn.f32 %f1109, %f1311, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p177, %f194, 0f3F800000;
|
|
selp.f32 %f1110, 0f3F7FFFFF, %f1109, %p177;
|
|
mul.f32 %f1111, %f194, 0f414EB852;
|
|
setp.lt.f32 %p178, %f194, 0f3B4D2E1C;
|
|
selp.f32 %f1112, %f1111, %f1110, %p178;
|
|
fma.rn.f32 %f1113, %f1314, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p179, %f195, 0f3F800000;
|
|
selp.f32 %f1114, 0f3F7FFFFF, %f1113, %p179;
|
|
mul.f32 %f1115, %f195, 0f414EB852;
|
|
setp.lt.f32 %p180, %f195, 0f3B4D2E1C;
|
|
selp.f32 %f1116, %f1115, %f1114, %p180;
|
|
min.f32 %f1117, %f1108, %f1105;
|
|
mov.f32 %f1118, 0f00000000;
|
|
max.f32 %f1119, %f1118, %f1117;
|
|
mul.f32 %f1120, %f1119, 0f43800000;
|
|
cvt.rzi.u32.f32 %r411, %f1120;
|
|
min.u32 %r412, %r411, 255;
|
|
min.f32 %f1121, %f1112, %f1105;
|
|
max.f32 %f1122, %f1118, %f1121;
|
|
mul.f32 %f1123, %f1122, 0f43800000;
|
|
cvt.rzi.u32.f32 %r413, %f1123;
|
|
min.u32 %r414, %r413, 255;
|
|
min.f32 %f1124, %f1116, %f1105;
|
|
max.f32 %f1125, %f1118, %f1124;
|
|
mul.f32 %f1126, %f1125, 0f43800000;
|
|
cvt.rzi.u32.f32 %r415, %f1126;
|
|
min.u32 %r416, %r415, 255;
|
|
shl.b64 %rd80, %rd22, 2;
|
|
add.s64 %rd81, %rd21, %rd80;
|
|
cvt.u16.u32 %rs18, %r416;
|
|
cvt.u16.u32 %rs19, %r414;
|
|
cvt.u16.u32 %rs20, %r412;
|
|
mov.u16 %rs21, 255;
|
|
st.global.v4.u8 [%rd81], {%rs20, %rs19, %rs18, %rs21};
|
|
|
|
$L__BB0_142:
|
|
and.b32 %r417, %r54, 4;
|
|
setp.eq.s32 %p181, %r417, 0;
|
|
ld.const.u32 %r463, [params+108];
|
|
@%p181 bra $L__BB0_146;
|
|
|
|
setp.eq.s32 %p182, %r463, 0;
|
|
ld.const.u64 %rd82, [params+224];
|
|
cvta.to.global.u64 %rd83, %rd82;
|
|
ld.const.u32 %r418, [params+216];
|
|
mad.lo.s32 %r419, %r418, %r8, %r7;
|
|
mul.wide.u32 %rd84, %r419, 8;
|
|
add.s64 %rd23, %rd83, %rd84;
|
|
@%p182 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs29, %rs30, %rs31, %rs32}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1127, %rs29;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1128, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1129, %rs31;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1130, %f153, %f1127;
|
|
add.f32 %f1131, %f154, %f1128;
|
|
add.f32 %f1132, %f156, %f1129;
|
|
mov.f32 %f1133, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f1131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1133;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs25, %rs26, %rs27, %rs28};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1137, 0f3F800000;
|
|
mov.u32 %r463, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f153;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs33, %rs34, %rs35, %rs36};
|
|
|
|
$L__BB0_146:
|
|
selp.f32 %f1138, 0f3F800000, 0f3E800000, %p198;
|
|
mul.f32 %f230, %f1138, %f1292;
|
|
mul.f32 %f231, %f1138, %f1291;
|
|
mul.f32 %f232, %f1138, %f1290;
|
|
mul.f32 %f233, %f1138, %f1289;
|
|
mul.f32 %f234, %f230, %f597;
|
|
mul.f32 %f235, %f230, %f598;
|
|
mul.f32 %f236, %f230, %f155;
|
|
ld.const.u64 %rd85, [params+256];
|
|
cvta.to.global.u64 %rd86, %rd85;
|
|
ld.const.u32 %r421, [params+248];
|
|
mad.lo.s32 %r422, %r421, %r8, %r7;
|
|
mul.wide.u32 %rd87, %r422, 8;
|
|
add.s64 %rd24, %rd86, %rd87;
|
|
setp.eq.s32 %p183, %r463, 0;
|
|
@%p183 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs44, %rs45, %rs46, %rs47}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1139, %rs44;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1140, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1141, %rs46;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1142, %f234, %f1139;
|
|
add.f32 %f1143, %f235, %f1140;
|
|
add.f32 %f1144, %f236, %f1141;
|
|
mov.f32 %f1145, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f1143;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1142;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1145;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs40, %rs41, %rs42, %rs43};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1149, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1149;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f235;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f234;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs48, %rs49, %rs50, %rs51};
|
|
|
|
$L__BB0_149:
|
|
mov.f32 %f1150, 0f34000000;
|
|
max.f32 %f1151, %f230, %f1150;
|
|
div.rn.f32 %f1152, %f231, %f1151;
|
|
fma.rn.f32 %f237, %f1152, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1153, %f232, %f1151;
|
|
fma.rn.f32 %f238, %f1153, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1154, %f233, %f1151;
|
|
fma.rn.f32 %f239, %f1154, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd88, [params+272];
|
|
cvta.to.global.u64 %rd89, %rd88;
|
|
ld.const.u32 %r423, [params+264];
|
|
mad.lo.s32 %r424, %r423, %r8, %r7;
|
|
mul.wide.u32 %rd90, %r424, 8;
|
|
add.s64 %rd25, %rd89, %rd90;
|
|
@%p183 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs59, %rs60, %rs61, %rs62}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1155, %rs59;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1156, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1157, %rs61;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1158, %f237, %f1155;
|
|
add.f32 %f1159, %f237, %f1156;
|
|
add.f32 %f1160, %f237, %f1157;
|
|
mov.f32 %f1161, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1160;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1159;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1158;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1161;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs55, %rs56, %rs57, %rs58};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1165, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f237;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs63, %rs64, %rs65, %rs66};
|
|
|
|
$L__BB0_152:
|
|
ld.const.u64 %rd91, [params+288];
|
|
cvta.to.global.u64 %rd92, %rd91;
|
|
ld.const.u32 %r425, [params+280];
|
|
mad.lo.s32 %r426, %r425, %r8, %r7;
|
|
mul.wide.u32 %rd93, %r426, 8;
|
|
add.s64 %rd26, %rd92, %rd93;
|
|
@%p183 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs74, %rs75, %rs76, %rs77}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1166, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1167, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1168, %rs76;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1169, %f238, %f1166;
|
|
add.f32 %f1170, %f238, %f1167;
|
|
add.f32 %f1171, %f238, %f1168;
|
|
mov.f32 %f1172, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1171;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1170;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1169;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1172;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs70, %rs71, %rs72, %rs73};
|
|
bra.uni $L__BB0_155;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1176, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1176;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f238;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f238;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f238;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs78, %rs79, %rs80, %rs81};
|
|
|
|
$L__BB0_155:
|
|
ld.const.u64 %rd94, [params+304];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r427, [params+296];
|
|
mad.lo.s32 %r428, %r427, %r8, %r7;
|
|
mul.wide.u32 %rd96, %r428, 8;
|
|
add.s64 %rd27, %rd95, %rd96;
|
|
@%p183 bra $L__BB0_157;
|
|
|
|
ld.global.v4.u16 {%rs89, %rs90, %rs91, %rs92}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1177, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1178, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1179, %rs91;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1180, %f239, %f1177;
|
|
add.f32 %f1181, %f239, %f1178;
|
|
add.f32 %f1182, %f239, %f1179;
|
|
mov.f32 %f1183, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1182;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1181;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1180;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1183;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs85, %rs86, %rs87, %rs88};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_157:
|
|
mov.f32 %f1187, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1187;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f239;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs93, %rs94, %rs95, %rs96};
|
|
|
|
$L__BB0_178:
|
|
ret;
|
|
|
|
}
|
|
|