185 lines
4.8 KiB
Plaintext
185 lines
4.8 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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.const .align 16 .b8 params[1184];
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.visible .func (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
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.param .b32 __direct_callable__oxMain_param_0,
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.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
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)
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{
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.reg .pred %p<4>;
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.reg .b16 %rs<9>;
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.reg .f32 %f<93>;
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.reg .b32 %r<19>;
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.reg .b64 %rd<40>;
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ld.param.u32 %r2, [__direct_callable__oxMain_param_0];
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ld.param.f32 %f1, [__direct_callable__oxMain_param_1];
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ld.param.f32 %f2, [__direct_callable__oxMain_param_1+4];
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ld.const.u64 %rd6, [params+24];
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cvta.to.global.u64 %rd7, %rd6;
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mul.wide.u32 %rd8, %r2, 12;
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add.s64 %rd9, %rd7, %rd8;
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ld.global.s32 %rd1, [%rd9];
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ld.global.s32 %rd2, [%rd9+4];
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ld.global.s32 %rd3, [%rd9+8];
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ld.const.u32 %r1, [params+32];
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setp.gt.u32 %p1, %r1, %r2;
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@%p1 bra $L__BB0_2;
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bra.uni $L__BB0_1;
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$L__BB0_2:
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mov.f32 %f90, 0f3F800000;
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sub.f32 %f51, %f90, %f1;
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sub.f32 %f89, %f51, %f2;
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bra.uni $L__BB0_3;
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$L__BB0_1:
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sub.s32 %r3, %r2, %r1;
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ld.const.v2.u64 {%rd10, %rd11}, [params+48];
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cvta.to.global.u64 %rd14, %rd10;
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mul.wide.u32 %rd15, %r3, 4;
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add.s64 %rd16, %rd14, %rd15;
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ld.const.u64 %rd17, [params+40];
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cvta.to.global.u64 %rd18, %rd17;
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shl.b64 %rd19, %rd1, 3;
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add.s64 %rd20, %rd18, %rd19;
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ld.global.v2.f32 {%f20, %f21}, [%rd20];
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shl.b64 %rd21, %rd2, 3;
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add.s64 %rd22, %rd18, %rd21;
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ld.global.v2.f32 {%f24, %f25}, [%rd22];
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shl.b64 %rd23, %rd3, 3;
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add.s64 %rd24, %rd18, %rd23;
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ld.global.v2.f32 {%f28, %f29}, [%rd24];
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mov.f32 %f32, 0f3F800000;
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sub.f32 %f33, %f32, %f1;
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sub.f32 %f89, %f33, %f2;
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mul.f32 %f34, %f1, %f24;
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mul.f32 %f35, %f1, %f25;
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fma.rn.f32 %f36, %f89, %f20, %f34;
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fma.rn.f32 %f37, %f89, %f21, %f35;
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fma.rn.f32 %f38, %f2, %f28, %f36;
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fma.rn.f32 %f39, %f2, %f29, %f37;
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ld.global.u32 %r4, [%rd16];
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shr.u32 %r5, %r4, 16;
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abs.f32 %f40, %f38;
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cvt.rmi.f32.f32 %f41, %f40;
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sub.f32 %f42, %f40, %f41;
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abs.f32 %f43, %f39;
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cvt.rmi.f32.f32 %f44, %f43;
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sub.f32 %f45, %f43, %f44;
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cvta.to.global.u64 %rd25, %rd11;
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shl.b32 %r6, %r4, 4;
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cvt.u64.u32 %rd26, %r6;
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and.b64 %rd27, %rd26, 1048560;
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add.s64 %rd28, %rd25, %rd27;
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ld.global.v2.u32 {%r7, %r8}, [%rd28];
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cvt.rn.f32.u32 %f46, %r7;
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mul.f32 %f47, %f42, %f46;
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cvt.rzi.u32.f32 %r11, %f47;
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cvt.rn.f32.u32 %f48, %r8;
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mul.f32 %f49, %f45, %f48;
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cvt.rzi.u32.f32 %r12, %f49;
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mad.lo.s32 %r13, %r7, %r12, %r11;
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cvt.u64.u32 %rd29, %r13;
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ld.global.u64 %rd30, [%rd28+8];
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add.s64 %rd31, %rd30, %rd29;
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ld.u8 %r14, [%rd31];
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and.b32 %r15, %r5, %r14;
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setp.eq.s32 %p2, %r15, 0;
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selp.f32 %f90, 0f00000000, 0f3F800000, %p2;
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$L__BB0_3:
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cvt.u32.u64 %r16, %rd1;
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cvt.u32.u64 %r17, %rd2;
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cvt.u32.u64 %r18, %rd3;
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ld.const.u64 %rd32, [params+16];
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cvta.to.global.u64 %rd33, %rd32;
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mul.wide.s32 %rd34, %r16, 32;
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add.s64 %rd35, %rd33, %rd34;
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mul.wide.s32 %rd36, %r17, 32;
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add.s64 %rd37, %rd33, %rd36;
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add.s64 %rd4, %rd37, 12;
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mul.wide.s32 %rd38, %r18, 32;
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add.s64 %rd39, %rd33, %rd38;
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add.s64 %rd5, %rd39, 12;
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ld.global.f32 %f52, [%rd35+12];
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ld.global.f32 %f53, [%rd35+16];
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ld.global.f32 %f54, [%rd35+20];
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ld.global.f32 %f55, [%rd37+12];
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mul.f32 %f56, %f1, %f55;
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ld.global.f32 %f57, [%rd37+16];
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mul.f32 %f58, %f1, %f57;
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ld.global.f32 %f59, [%rd37+20];
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mul.f32 %f60, %f1, %f59;
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fma.rn.f32 %f61, %f89, %f52, %f56;
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fma.rn.f32 %f62, %f89, %f53, %f58;
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fma.rn.f32 %f63, %f89, %f54, %f60;
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ld.global.f32 %f64, [%rd39+12];
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ld.global.f32 %f65, [%rd39+16];
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ld.global.f32 %f66, [%rd39+20];
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fma.rn.f32 %f67, %f2, %f64, %f61;
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fma.rn.f32 %f68, %f2, %f65, %f62;
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fma.rn.f32 %f69, %f2, %f66, %f63;
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mul.f32 %f70, %f68, %f68;
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fma.rn.f32 %f71, %f67, %f67, %f70;
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fma.rn.f32 %f72, %f69, %f69, %f71;
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sqrt.rn.f32 %f73, %f72;
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rcp.rn.f32 %f74, %f73;
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mul.f32 %f8, %f67, %f74;
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mul.f32 %f9, %f68, %f74;
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mul.f32 %f10, %f69, %f74;
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ld.global.v2.f32 {%f91, %f76}, [%rd35+24];
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setp.lt.f32 %p3, %f76, 0f00000000;
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@%p3 bra $L__BB0_5;
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bra.uni $L__BB0_4;
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$L__BB0_5:
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add.f32 %f92, %f76, 0f3F800000;
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bra.uni $L__BB0_6;
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$L__BB0_4:
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ld.global.v2.f32 {%f77, %f78}, [%rd4+12];
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ld.global.v2.f32 {%f79, %f80}, [%rd5+12];
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mul.f32 %f82, %f1, %f77;
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mul.f32 %f84, %f1, %f78;
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fma.rn.f32 %f85, %f89, %f91, %f82;
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fma.rn.f32 %f86, %f89, %f76, %f84;
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fma.rn.f32 %f91, %f2, %f79, %f85;
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fma.rn.f32 %f92, %f2, %f80, %f86;
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$L__BB0_6:
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st.param.f32 [func_retval0+0], %f8;
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st.param.f32 [func_retval0+4], %f9;
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st.param.f32 [func_retval0+8], %f10;
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st.param.f32 [func_retval0+16], %f91;
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st.param.f32 [func_retval0+20], %f92;
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st.param.f32 [func_retval0+24], %f90;
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ret;
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}
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// .globl oxMain
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.visible .entry oxMain()
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{
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.reg .b64 %rd<2>;
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mov.u64 %rd1, __direct_callable__oxMain;
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// begin inline asm
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// end inline asm
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ret;
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}
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