2247 lines
60 KiB
Plaintext
2247 lines
60 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<155>;
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.reg .b16 %rs<166>;
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.reg .f32 %f<1167>;
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.reg .b32 %r<363>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<122>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r52), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r53), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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ld.const.u64 %rd27, [params+400];
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cvta.to.global.u64 %rd28, %rd27;
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ld.const.u32 %r58, [params+392];
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mad.lo.s32 %r59, %r58, %r53, %r52;
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mul.wide.u32 %rd29, %r59, 4;
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add.s64 %rd2, %rd28, %rd29;
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ld.global.v2.u8 {%rs7, %rs165}, [%rd2];
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or.b16 %rs9, %rs7, %rs165;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs164, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs164, [%rd2+2];
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setp.eq.s16 %p8, %rs164, 0;
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mov.f32 %f1092, 0f00000000;
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mov.u16 %rs165, 0;
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mov.f32 %f1093, %f1092;
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mov.f32 %f1094, %f1092;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f228, %rs7;
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div.rn.f32 %f229, %f228, 0f437F0000;
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fma.rn.f32 %f230, %f229, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs165, 255;
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cvt.rn.f32.u16 %f231, %rs13;
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div.rn.f32 %f232, %f231, 0f437F0000;
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fma.rn.f32 %f233, %f232, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f234, %rs164;
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div.rn.f32 %f235, %f234, 0f437F0000;
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fma.rn.f32 %f236, %f235, 0f40000000, 0fBF800000;
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mul.f32 %f237, %f233, %f233;
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fma.rn.f32 %f238, %f230, %f230, %f237;
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fma.rn.f32 %f239, %f236, %f236, %f238;
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sqrt.rn.f32 %f240, %f239;
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rcp.rn.f32 %f241, %f240;
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mul.f32 %f1094, %f241, %f236;
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mul.f32 %f1093, %f241, %f233;
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mul.f32 %f1092, %f230, %f241;
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$L__BB0_4:
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ld.const.v2.u32 {%r60, %r61}, [params];
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add.s32 %r4, %r60, %r52;
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add.s32 %r5, %r61, %r53;
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setp.eq.f32 %p9, %f1092, 0f00000000;
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setp.eq.f32 %p10, %f1093, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1094, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_128;
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bra.uni $L__BB0_5;
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$L__BB0_128:
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ld.const.u32 %r50, [params+104];
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and.b32 %r315, %r50, 1;
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setp.eq.b32 %p144, %r315, 1;
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mov.pred %p145, 0;
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xor.pred %p146, %p144, %p145;
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not.pred %p147, %p146;
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@%p147 bra $L__BB0_130;
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ld.const.u64 %rd90, [params+144];
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cvta.to.global.u64 %rd91, %rd90;
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ld.const.u32 %r316, [params+136];
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mad.lo.s32 %r317, %r316, %r5, %r4;
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mul.wide.u32 %rd92, %r317, 4;
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add.s64 %rd93, %rd91, %rd92;
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mov.u16 %rs95, 0;
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st.global.v4.u8 [%rd93], {%rs95, %rs95, %rs95, %rs95};
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$L__BB0_130:
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and.b32 %r318, %r50, 4;
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setp.eq.s32 %p148, %r318, 0;
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@%p148 bra $L__BB0_132;
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ld.const.u64 %rd94, [params+224];
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cvta.to.global.u64 %rd95, %rd94;
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ld.const.u32 %r319, [params+216];
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mad.lo.s32 %r320, %r319, %r5, %r4;
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mov.f32 %f1022, 0f00000000;
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mul.wide.u32 %rd96, %r320, 8;
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add.s64 %rd97, %rd95, %rd96;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs98, %f1022;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs97, %f1022;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs96, %f1022;}
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// end inline asm
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mov.u16 %rs99, 0;
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st.global.v4.u16 [%rd97], {%rs96, %rs97, %rs98, %rs99};
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$L__BB0_132:
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and.b32 %r321, %r50, 16;
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setp.eq.s32 %p149, %r321, 0;
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@%p149 bra $L__BB0_134;
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ld.const.u64 %rd98, [params+240];
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cvta.to.global.u64 %rd99, %rd98;
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ld.const.u32 %r322, [params+232];
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mad.lo.s32 %r323, %r322, %r5, %r4;
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mov.f32 %f1025, 0f00000000;
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mul.wide.u32 %rd100, %r323, 8;
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add.s64 %rd101, %rd99, %rd100;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs102, %f1025;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs101, %f1025;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs100, %f1025;}
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// end inline asm
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mov.u16 %rs103, 0;
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st.global.v4.u16 [%rd101], {%rs100, %rs101, %rs102, %rs103};
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$L__BB0_134:
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ld.const.u32 %r51, [params+108];
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setp.eq.s32 %p150, %r51, 0;
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ld.const.u64 %rd102, [params+256];
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cvta.to.global.u64 %rd103, %rd102;
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ld.const.u32 %r324, [params+248];
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mad.lo.s32 %r325, %r324, %r5, %r4;
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mul.wide.u32 %rd104, %r325, 8;
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add.s64 %rd22, %rd103, %rd104;
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@%p150 bra $L__BB0_136;
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ld.global.v4.u16 {%rs110, %rs111, %rs112, %rs113}, [%rd22];
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// begin inline asm
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{ cvt.f32.f16 %f1026, %rs110;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1027, %rs111;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1028, %rs112;}
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// end inline asm
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add.f32 %f1029, %f1026, 0f00000000;
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add.f32 %f1030, %f1027, 0f00000000;
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add.f32 %f1031, %f1028, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs109, %f1031;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs108, %f1030;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs107, %f1029;}
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// end inline asm
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mov.u16 %rs114, 0;
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st.global.v4.u16 [%rd22], {%rs107, %rs108, %rs109, %rs114};
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bra.uni $L__BB0_137;
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$L__BB0_5:
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ld.const.u64 %rd30, [params+496];
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cvta.to.global.u64 %rd31, %rd30;
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ld.const.u32 %r64, [params+488];
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mad.lo.s32 %r65, %r64, %r53, %r52;
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mul.wide.u32 %rd32, %r65, 8;
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add.s64 %rd33, %rd31, %rd32;
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ld.global.v4.u16 {%rs19, %rs20, %rs21, %rs22}, [%rd33];
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// begin inline asm
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{ cvt.f32.f16 %f242, %rs19;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f243, %rs20;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f244, %rs21;}
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// end inline asm
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ld.const.u64 %rd34, [params+432];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r66, [params+424];
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mad.lo.s32 %r67, %r66, %r53, %r52;
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mul.wide.u32 %rd36, %r67, 12;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.f32 %f261, [%rd37];
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mul.f32 %f262, %f261, 0f3456BF95;
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ld.global.f32 %f263, [%rd37+4];
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mul.f32 %f264, %f263, 0f3456BF95;
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ld.global.f32 %f265, [%rd37+8];
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mul.f32 %f266, %f265, 0f3456BF95;
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abs.f32 %f267, %f1092;
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div.rn.f32 %f268, %f262, %f267;
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abs.f32 %f269, %f1093;
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div.rn.f32 %f270, %f264, %f269;
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abs.f32 %f271, %f1094;
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div.rn.f32 %f272, %f266, %f271;
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abs.f32 %f273, %f268;
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abs.f32 %f274, %f270;
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abs.f32 %f275, %f272;
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mov.f32 %f276, 0f38D1B717;
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max.f32 %f277, %f273, %f276;
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max.f32 %f278, %f274, %f276;
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max.f32 %f279, %f275, %f276;
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fma.rn.f32 %f13, %f1092, %f277, %f261;
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fma.rn.f32 %f14, %f1093, %f278, %f263;
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fma.rn.f32 %f15, %f1094, %f279, %f265;
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setp.gt.f32 %p14, %f267, %f271;
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neg.f32 %f280, %f1093;
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selp.f32 %f281, %f280, 0f00000000, %p14;
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mov.f32 %f1124, 0f00000000;
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neg.f32 %f282, %f1094;
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selp.f32 %f283, %f1092, %f282, %p14;
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selp.f32 %f284, 0f00000000, %f1093, %p14;
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mul.f32 %f285, %f283, %f283;
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fma.rn.f32 %f286, %f281, %f281, %f285;
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fma.rn.f32 %f287, %f284, %f284, %f286;
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sqrt.rn.f32 %f288, %f287;
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rcp.rn.f32 %f289, %f288;
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mul.f32 %f16, %f281, %f289;
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mul.f32 %f17, %f283, %f289;
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mul.f32 %f18, %f284, %f289;
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ld.const.u64 %rd38, [params+128];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r68, [params+120];
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mad.lo.s32 %r69, %r68, %r53, %r52;
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mul.wide.u32 %rd40, %r69, 4;
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add.s64 %rd3, %rd39, %rd40;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1123, %f1124;
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mov.f32 %f1122, %f1124;
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mov.f32 %f1121, %f1124;
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mov.f32 %f1120, %f1124;
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mov.f32 %f1119, %f1124;
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mov.f32 %f1118, %f1124;
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mov.f32 %f1117, %f1124;
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mov.f32 %f1116, %f1124;
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mov.f32 %f1115, %f1124;
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mov.f32 %f1114, %f1124;
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mov.f32 %f1113, %f1124;
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mov.f32 %f1112, %f1124;
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mov.f32 %f1111, %f1124;
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mov.f32 %f1110, %f1124;
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@%p15 bra $L__BB0_34;
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cvt.rn.f32.s32 %f305, %r3;
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rcp.rn.f32 %f19, %f305;
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ld.global.u32 %r355, [%rd3];
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mul.f32 %f20, %f13, 0f3456BF95;
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mul.f32 %f21, %f14, 0f3456BF95;
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mul.f32 %f22, %f15, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f306, %f1092, %f17;
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mul.f32 %f307, %f1093, %f16;
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sub.f32 %f23, %f307, %f306;
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mul.f32 %f308, %f1094, %f16;
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mul.f32 %f309, %f1092, %f18;
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sub.f32 %f24, %f309, %f308;
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mul.f32 %f310, %f1093, %f18;
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mul.f32 %f311, %f1094, %f17;
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sub.f32 %f25, %f311, %f310;
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mov.u32 %r70, 0;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd41, __cudart_i2opi_f;
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abs.f32 %f374, %f21;
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abs.f32 %f375, %f20;
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max.f32 %f376, %f375, %f374;
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abs.f32 %f377, %f22;
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max.f32 %f378, %f376, %f377;
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mov.u32 %r352, %r70;
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$L__BB0_7:
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mov.u32 %r354, %r70;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1068, %r352;
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mad.lo.s32 %r72, %r355, 1664525, 1013904223;
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and.b32 %r73, %r72, 16777215;
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cvt.rn.f32.u32 %f312, %r73;
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fma.rn.f32 %f313, %f312, 0f33800000, %f1068;
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mul.f32 %f57, %f19, %f313;
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mad.lo.s32 %r355, %r72, 1664525, 1013904223;
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and.b32 %r74, %r355, 16777215;
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cvt.rn.f32.u32 %f314, %r74;
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cvt.rn.f32.s32 %f315, %r354;
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fma.rn.f32 %f316, %f314, 0f33800000, %f315;
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mul.f32 %f317, %f19, %f316;
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mul.f32 %f318, %f57, %f57;
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mov.f32 %f319, 0f3F800000;
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sub.f32 %f320, %f319, %f318;
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mov.f32 %f321, 0f00000000;
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max.f32 %f322, %f321, %f320;
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sqrt.rn.f32 %f58, %f322;
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mul.f32 %f59, %f317, 0f40C90FDB;
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mul.f32 %f323, %f59, 0f3F22F983;
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cvt.rni.s32.f32 %r359, %f323;
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cvt.rn.f32.s32 %f324, %r359;
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mov.f32 %f325, 0fBFC90FDA;
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fma.rn.f32 %f326, %f324, %f325, %f59;
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mov.f32 %f327, 0fB3A22168;
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fma.rn.f32 %f328, %f324, %f327, %f326;
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mov.f32 %f329, 0fA7C234C5;
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fma.rn.f32 %f1128, %f324, %f329, %f328;
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abs.f32 %f61, %f59;
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setp.ltu.f32 %p16, %f61, 0f47CE4780;
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mov.f32 %f1125, %f1128;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f61, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f332, 0f00000000;
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mul.rn.f32 %f1125, %f59, %f332;
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mov.u32 %r359, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r13, %f59;
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bfe.u32 %r76, %r13, 23, 8;
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mov.u64 %rd119, 0;
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mov.u32 %r356, 0;
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mov.u64 %rd117, %rd1;
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mov.u64 %rd118, %rd41;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r335, %f59;
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shl.b32 %r334, %r335, 8;
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or.b32 %r333, %r334, -2147483648;
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ld.global.nc.u32 %r78, [%rd118];
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mad.wide.u32 %rd43, %r78, %r333, %rd119;
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shr.u64 %rd119, %rd43, 32;
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st.local.u32 [%rd117], %rd43;
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add.s64 %rd118, %rd118, 4;
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add.s64 %rd117, %rd117, 4;
|
|
add.s32 %r356, %r356, 1;
|
|
setp.ne.s32 %p18, %r356, 6;
|
|
@%p18 bra $L__BB0_11;
|
|
|
|
add.s32 %r340, %r76, -128;
|
|
mov.b32 %r339, %f59;
|
|
bfe.u32 %r338, %r339, 23, 8;
|
|
add.s32 %r337, %r338, -128;
|
|
shr.u32 %r336, %r337, 5;
|
|
st.local.u32 [%rd5], %rd119;
|
|
mov.u32 %r80, 6;
|
|
sub.s32 %r81, %r80, %r336;
|
|
mul.wide.s32 %rd44, %r81, 4;
|
|
add.s64 %rd45, %rd1, %rd44;
|
|
ld.local.u32 %r357, [%rd45];
|
|
ld.local.u32 %r358, [%rd45+-4];
|
|
and.b32 %r22, %r337, 31;
|
|
setp.eq.s32 %p19, %r22, 0;
|
|
@%p19 bra $L__BB0_14;
|
|
|
|
mov.b32 %r347, %f59;
|
|
bfe.u32 %r346, %r347, 23, 8;
|
|
add.s32 %r345, %r346, -128;
|
|
shr.u32 %r344, %r345, 5;
|
|
mov.u32 %r343, 4;
|
|
sub.s32 %r342, %r343, %r344;
|
|
mov.u32 %r82, 32;
|
|
sub.s32 %r83, %r82, %r22;
|
|
shr.u32 %r84, %r358, %r83;
|
|
shl.b32 %r85, %r357, %r22;
|
|
add.s32 %r357, %r84, %r85;
|
|
mul.wide.s32 %rd46, %r342, 4;
|
|
add.s64 %rd47, %rd1, %rd46;
|
|
ld.local.u32 %r86, [%rd47];
|
|
shr.u32 %r87, %r86, %r83;
|
|
shl.b32 %r88, %r358, %r22;
|
|
add.s32 %r358, %r87, %r88;
|
|
|
|
$L__BB0_14:
|
|
mov.b32 %r341, %f59;
|
|
and.b32 %r89, %r341, -2147483648;
|
|
shr.u32 %r90, %r358, 30;
|
|
shl.b32 %r91, %r357, 2;
|
|
or.b32 %r92, %r90, %r91;
|
|
shr.u32 %r93, %r92, 31;
|
|
shr.u32 %r94, %r357, 30;
|
|
add.s32 %r95, %r93, %r94;
|
|
neg.s32 %r96, %r95;
|
|
setp.eq.s32 %p20, %r89, 0;
|
|
selp.b32 %r359, %r95, %r96, %p20;
|
|
setp.ne.s32 %p21, %r93, 0;
|
|
xor.b32 %r97, %r89, -2147483648;
|
|
selp.b32 %r98, %r97, %r89, %p21;
|
|
selp.b32 %r99, -1, 0, %p21;
|
|
xor.b32 %r100, %r92, %r99;
|
|
shl.b32 %r101, %r358, 2;
|
|
xor.b32 %r102, %r101, %r99;
|
|
cvt.u64.u32 %rd48, %r100;
|
|
cvt.u64.u32 %rd49, %r102;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f330, %fd2;
|
|
setp.eq.s32 %p22, %r98, 0;
|
|
neg.f32 %f331, %f330;
|
|
selp.f32 %f1125, %f330, %f331, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r29, %r359, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p23, %r30, 0;
|
|
selp.f32 %f65, %f1125, 0f3F800000, %p23;
|
|
mul.rn.f32 %f66, %f1125, %f1125;
|
|
mov.f32 %f1126, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f334, 0fBAB607ED;
|
|
mov.f32 %f335, 0f37CBAC00;
|
|
fma.rn.f32 %f1126, %f335, %f66, %f334;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f336, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f337, %f1126, %f66, %f336;
|
|
selp.f32 %f338, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f339, %f337, %f66, %f338;
|
|
mov.f32 %f340, 0f00000000;
|
|
fma.rn.f32 %f341, %f66, %f65, %f340;
|
|
fma.rn.f32 %f1127, %f339, %f341, %f65;
|
|
and.b32 %r104, %r29, 2;
|
|
setp.eq.s32 %p25, %r104, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f343, 0fBF800000;
|
|
fma.rn.f32 %f1127, %f1127, %f343, %f340;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1069, %f59, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r362, %f1069;
|
|
setp.ltu.f32 %p154, %f61, 0f47CE4780;
|
|
@%p154 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f61, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f346, 0f00000000;
|
|
mul.rn.f32 %f1128, %f59, %f346;
|
|
mov.u32 %r362, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r31, %f59;
|
|
bfe.u32 %r105, %r31, 23, 8;
|
|
add.s32 %r32, %r105, -128;
|
|
shl.b32 %r106, %r31, 8;
|
|
or.b32 %r33, %r106, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd120, 0;
|
|
mov.u64 %rd121, %rd120;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd120, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r107, [%rd55];
|
|
mad.wide.u32 %rd56, %r107, %r33, %rd121;
|
|
shr.u64 %rd121, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r108, %rd120;
|
|
add.s32 %r109, %r108, 1;
|
|
cvt.s64.s32 %rd120, %r109;
|
|
setp.ne.s32 %p28, %r109, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd121;
|
|
mov.u32 %r110, 4;
|
|
sub.s32 %r35, %r110, %r34;
|
|
mov.u32 %r111, 6;
|
|
sub.s32 %r112, %r111, %r34;
|
|
mul.wide.s32 %rd58, %r112, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r360, [%rd59];
|
|
ld.local.u32 %r361, [%rd59+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p29, %r38, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r113, 32;
|
|
sub.s32 %r114, %r113, %r38;
|
|
shr.u32 %r115, %r361, %r114;
|
|
shl.b32 %r116, %r360, %r38;
|
|
add.s32 %r360, %r115, %r116;
|
|
mul.wide.s32 %rd60, %r35, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r117, [%rd61];
|
|
shr.u32 %r118, %r117, %r114;
|
|
shl.b32 %r119, %r361, %r38;
|
|
add.s32 %r361, %r118, %r119;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r120, %r31, -2147483648;
|
|
shr.u32 %r121, %r361, 30;
|
|
shl.b32 %r122, %r360, 2;
|
|
or.b32 %r123, %r121, %r122;
|
|
shr.u32 %r124, %r123, 31;
|
|
shr.u32 %r125, %r360, 30;
|
|
add.s32 %r126, %r124, %r125;
|
|
neg.s32 %r127, %r126;
|
|
setp.eq.s32 %p30, %r120, 0;
|
|
selp.b32 %r362, %r126, %r127, %p30;
|
|
setp.ne.s32 %p31, %r124, 0;
|
|
xor.b32 %r128, %r120, -2147483648;
|
|
selp.b32 %r129, %r128, %r120, %p31;
|
|
selp.b32 %r130, -1, 0, %p31;
|
|
xor.b32 %r131, %r123, %r130;
|
|
shl.b32 %r132, %r361, 2;
|
|
xor.b32 %r133, %r132, %r130;
|
|
cvt.u64.u32 %rd62, %r131;
|
|
cvt.u64.u32 %rd63, %r133;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f344, %fd4;
|
|
setp.eq.s32 %p32, %r129, 0;
|
|
neg.f32 %f345, %f344;
|
|
selp.f32 %f1128, %f344, %f345, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f75, %f58, %f1127;
|
|
and.b32 %r45, %r362, 1;
|
|
setp.eq.s32 %p33, %r45, 0;
|
|
mul.rn.f32 %f77, %f1128, %f1128;
|
|
mov.f32 %f1129, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f348, 0fBAB607ED;
|
|
mov.f32 %f349, 0f37CBAC00;
|
|
fma.rn.f32 %f1129, %f349, %f77, %f348;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1070, %f1128, 0f3F800000, %p33;
|
|
selp.f32 %f350, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f351, %f1129, %f77, %f350;
|
|
selp.f32 %f352, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f353, %f351, %f77, %f352;
|
|
mov.f32 %f354, 0f00000000;
|
|
fma.rn.f32 %f355, %f77, %f1070, %f354;
|
|
fma.rn.f32 %f1130, %f353, %f355, %f1070;
|
|
and.b32 %r135, %r362, 2;
|
|
setp.eq.s32 %p35, %r135, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f357, 0fBF800000;
|
|
fma.rn.f32 %f1130, %f1130, %f357, %f354;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f367, %f58, %f1130;
|
|
mul.f32 %f368, %f16, %f367;
|
|
mul.f32 %f369, %f17, %f367;
|
|
mul.f32 %f370, %f18, %f367;
|
|
fma.rn.f32 %f371, %f25, %f75, %f368;
|
|
fma.rn.f32 %f372, %f24, %f75, %f369;
|
|
fma.rn.f32 %f373, %f23, %f75, %f370;
|
|
fma.rn.f32 %f361, %f1092, %f57, %f371;
|
|
fma.rn.f32 %f362, %f1093, %f57, %f372;
|
|
fma.rn.f32 %f363, %f1094, %f57, %f373;
|
|
mov.f32 %f379, 0f38D1B717;
|
|
max.f32 %f364, %f378, %f379;
|
|
mov.f32 %f365, 0f6C4ECB8F;
|
|
mov.u32 %r169, 1;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r174, 3;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f13,%f14,%f15,%f361,%f362,%f363,%f364,%f365,%f354,%r169,%r206,%r206,%r172,%r206,%r174,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f380, %r136;
|
|
mov.b32 %f381, %r137;
|
|
mov.b32 %f382, %r138;
|
|
mul.f32 %f383, %f1093, %f362;
|
|
fma.rn.f32 %f384, %f1092, %f361, %f383;
|
|
fma.rn.f32 %f385, %f1094, %f363, %f384;
|
|
mul.f32 %f386, %f385, 0f40800000;
|
|
cvt.sat.f32.f32 %f387, %f386;
|
|
mul.f32 %f388, %f387, %f380;
|
|
mul.f32 %f389, %f387, %f381;
|
|
mul.f32 %f390, %f387, %f382;
|
|
fma.rn.f32 %f1118, %f361, %f388, %f1118;
|
|
fma.rn.f32 %f1117, %f361, %f389, %f1117;
|
|
fma.rn.f32 %f1116, %f361, %f390, %f1116;
|
|
fma.rn.f32 %f1121, %f362, %f388, %f1121;
|
|
fma.rn.f32 %f1120, %f362, %f389, %f1120;
|
|
fma.rn.f32 %f1119, %f362, %f390, %f1119;
|
|
fma.rn.f32 %f1124, %f363, %f388, %f1124;
|
|
fma.rn.f32 %f1123, %f363, %f389, %f1123;
|
|
fma.rn.f32 %f1122, %f363, %f390, %f1122;
|
|
add.f32 %f1115, %f1115, %f388;
|
|
add.f32 %f1114, %f1114, %f389;
|
|
add.f32 %f1113, %f1113, %f390;
|
|
cvt.sat.f32.f32 %f391, %f385;
|
|
fma.rn.f32 %f1112, %f391, %f380, %f1112;
|
|
fma.rn.f32 %f1111, %f391, %f381, %f1111;
|
|
fma.rn.f32 %f1110, %f391, %f382, %f1110;
|
|
add.s32 %r354, %r354, 1;
|
|
setp.lt.s32 %p36, %r354, %r3;
|
|
@%p36 bra $L__BB0_8;
|
|
|
|
add.s32 %r352, %r352, 1;
|
|
setp.lt.s32 %p37, %r352, %r3;
|
|
@%p37 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f1146, 0f00000000;
|
|
mul.lo.s32 %r207, %r3, %r3;
|
|
cvt.rn.f32.s32 %f395, %r207;
|
|
rcp.rn.f32 %f396, %f395;
|
|
mul.f32 %f397, %f396, %f1112;
|
|
mul.f32 %f398, %f396, %f1111;
|
|
mul.f32 %f399, %f396, %f1110;
|
|
mul.f32 %f113, %f396, %f1115;
|
|
mul.f32 %f114, %f396, %f1114;
|
|
mul.f32 %f115, %f396, %f1113;
|
|
mul.f32 %f116, %f396, %f1118;
|
|
mul.f32 %f117, %f396, %f1117;
|
|
mul.f32 %f118, %f396, %f1116;
|
|
mul.f32 %f119, %f396, %f1121;
|
|
mul.f32 %f120, %f396, %f1120;
|
|
mul.f32 %f121, %f396, %f1119;
|
|
mul.f32 %f122, %f396, %f1124;
|
|
mul.f32 %f123, %f396, %f1123;
|
|
mul.f32 %f124, %f396, %f1122;
|
|
fma.rn.f32 %f400, %f396, %f1112, %f397;
|
|
fma.rn.f32 %f401, %f396, %f1111, %f398;
|
|
fma.rn.f32 %f402, %f396, %f1110, %f399;
|
|
ld.const.u64 %rd66, [params+504];
|
|
cvt.rn.f32.u32 %f403, %r5;
|
|
cvt.rn.f32.u32 %f404, %r4;
|
|
tex.2d.v4.f32.f32 {%f405, %f406, %f407, %f408}, [%rd66, {%f404, %f403}];
|
|
mul.f32 %f125, %f400, %f405;
|
|
mul.f32 %f126, %f401, %f406;
|
|
mul.f32 %f127, %f402, %f407;
|
|
add.f32 %f128, %f242, %f125;
|
|
add.f32 %f129, %f243, %f126;
|
|
add.f32 %f130, %f244, %f127;
|
|
abs.f32 %f409, %f128;
|
|
setp.gtu.f32 %p38, %f409, 0f7F800000;
|
|
mov.f32 %f1147, %f1146;
|
|
mov.f32 %f1148, %f1146;
|
|
@%p38 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1146, 0f00000000;
|
|
abs.f32 %f413, %f129;
|
|
setp.gtu.f32 %p39, %f413, 0f7F800000;
|
|
@%p39 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1146, 0f00000000;
|
|
abs.f32 %f417, %f130;
|
|
setp.gtu.f32 %p40, %f417, 0f7F800000;
|
|
mov.f32 %f1147, %f1146;
|
|
mov.f32 %f1148, %f1146;
|
|
@%p40 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1146, %f128;
|
|
mov.f32 %f1147, %f129;
|
|
mov.f32 %f1148, %f130;
|
|
|
|
$L__BB0_38:
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r208, %r48, 1;
|
|
setp.eq.b32 %p41, %r208, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_112;
|
|
|
|
mov.f32 %f422, 0f3EE66666;
|
|
abs.f32 %f141, %f1146;
|
|
setp.lt.f32 %p45, %f141, 0f00800000;
|
|
mul.f32 %f424, %f141, 0f4B800000;
|
|
selp.f32 %f425, %f424, %f141, %p45;
|
|
selp.f32 %f426, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r209, %f425;
|
|
and.b32 %r210, %r209, 8388607;
|
|
or.b32 %r211, %r210, 1065353216;
|
|
mov.b32 %f427, %r211;
|
|
shr.u32 %r212, %r209, 23;
|
|
cvt.rn.f32.u32 %f428, %r212;
|
|
add.f32 %f429, %f426, %f428;
|
|
setp.gt.f32 %p46, %f427, 0f3FB504F3;
|
|
mul.f32 %f430, %f427, 0f3F000000;
|
|
add.f32 %f431, %f429, 0f3F800000;
|
|
selp.f32 %f432, %f431, %f429, %p46;
|
|
selp.f32 %f433, %f430, %f427, %p46;
|
|
add.f32 %f434, %f433, 0fBF800000;
|
|
add.f32 %f435, %f433, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f436, %f435;
|
|
add.f32 %f437, %f434, %f434;
|
|
mul.f32 %f438, %f437, %f436;
|
|
mul.f32 %f439, %f438, %f438;
|
|
mov.f32 %f440, 0f3C4CAF63;
|
|
mov.f32 %f441, 0f3B18F0FE;
|
|
fma.rn.f32 %f442, %f441, %f439, %f440;
|
|
mov.f32 %f443, 0f3DAAAABD;
|
|
fma.rn.f32 %f444, %f442, %f439, %f443;
|
|
mul.rn.f32 %f445, %f444, %f439;
|
|
mul.rn.f32 %f446, %f445, %f438;
|
|
sub.f32 %f447, %f434, %f438;
|
|
add.f32 %f448, %f447, %f447;
|
|
neg.f32 %f449, %f438;
|
|
fma.rn.f32 %f450, %f449, %f434, %f448;
|
|
mul.rn.f32 %f451, %f436, %f450;
|
|
add.f32 %f452, %f446, %f438;
|
|
sub.f32 %f453, %f438, %f452;
|
|
add.f32 %f454, %f446, %f453;
|
|
add.f32 %f455, %f451, %f454;
|
|
add.f32 %f456, %f452, %f455;
|
|
sub.f32 %f457, %f452, %f456;
|
|
add.f32 %f458, %f455, %f457;
|
|
mov.f32 %f459, 0f3F317200;
|
|
mul.rn.f32 %f460, %f432, %f459;
|
|
mov.f32 %f461, 0f35BFBE8E;
|
|
mul.rn.f32 %f462, %f432, %f461;
|
|
add.f32 %f463, %f460, %f456;
|
|
sub.f32 %f464, %f460, %f463;
|
|
add.f32 %f465, %f456, %f464;
|
|
add.f32 %f466, %f458, %f465;
|
|
add.f32 %f467, %f462, %f466;
|
|
add.f32 %f468, %f463, %f467;
|
|
sub.f32 %f469, %f463, %f468;
|
|
add.f32 %f470, %f467, %f469;
|
|
mul.rn.f32 %f471, %f422, %f468;
|
|
neg.f32 %f472, %f471;
|
|
fma.rn.f32 %f473, %f422, %f468, %f472;
|
|
fma.rn.f32 %f474, %f422, %f470, %f473;
|
|
mov.f32 %f475, 0f00000000;
|
|
fma.rn.f32 %f476, %f475, %f468, %f474;
|
|
add.rn.f32 %f477, %f471, %f476;
|
|
neg.f32 %f478, %f477;
|
|
add.rn.f32 %f479, %f471, %f478;
|
|
add.rn.f32 %f480, %f479, %f476;
|
|
mov.b32 %r213, %f477;
|
|
setp.eq.s32 %p47, %r213, 1118925336;
|
|
add.s32 %r214, %r213, -1;
|
|
mov.b32 %f481, %r214;
|
|
add.f32 %f482, %f480, 0f37000000;
|
|
selp.f32 %f142, %f482, %f480, %p47;
|
|
selp.f32 %f483, %f481, %f477, %p47;
|
|
mov.f32 %f484, 0f3FB8AA3B;
|
|
mul.rn.f32 %f485, %f483, %f484;
|
|
cvt.rzi.f32.f32 %f486, %f485;
|
|
abs.f32 %f487, %f486;
|
|
setp.gt.f32 %p48, %f487, 0f42FC0000;
|
|
mov.b32 %r215, %f486;
|
|
and.b32 %r216, %r215, -2147483648;
|
|
or.b32 %r217, %r216, 1123811328;
|
|
mov.b32 %f488, %r217;
|
|
selp.f32 %f489, %f488, %f486, %p48;
|
|
mov.f32 %f490, 0fBF317218;
|
|
fma.rn.f32 %f491, %f489, %f490, %f483;
|
|
mov.f32 %f492, 0f3102E308;
|
|
fma.rn.f32 %f493, %f489, %f492, %f491;
|
|
mul.f32 %f494, %f493, 0f3FB8AA3B;
|
|
add.f32 %f495, %f489, 0f4B40007F;
|
|
mov.b32 %r218, %f495;
|
|
shl.b32 %r219, %r218, 23;
|
|
mov.b32 %f496, %r219;
|
|
ex2.approx.ftz.f32 %f497, %f494;
|
|
mul.f32 %f143, %f497, %f496;
|
|
setp.eq.f32 %p49, %f143, 0f7F800000;
|
|
mov.f32 %f1149, 0f7F800000;
|
|
@%p49 bra $L__BB0_41;
|
|
|
|
fma.rn.f32 %f1149, %f143, %f142, %f143;
|
|
|
|
$L__BB0_41:
|
|
mov.f32 %f1076, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1075, %f1076;
|
|
add.f32 %f1074, %f1075, %f1075;
|
|
mov.f32 %f1073, 0f3EE66666;
|
|
sub.f32 %f1072, %f1073, %f1074;
|
|
abs.f32 %f1071, %f1072;
|
|
setp.lt.f32 %p50, %f1146, 0f00000000;
|
|
setp.eq.f32 %p51, %f1071, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f1146, 0f00000000;
|
|
@%p52 bra $L__BB0_45;
|
|
bra.uni $L__BB0_42;
|
|
|
|
$L__BB0_45:
|
|
add.f32 %f502, %f1146, %f1146;
|
|
selp.f32 %f1151, %f502, 0f00000000, %p51;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1034, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1034;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs116, %f1034;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1034;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs118, 0;
|
|
st.global.v4.u16 [%rd22], {%rs115, %rs116, %rs117, %rs118};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd105, [params+272];
|
|
cvta.to.global.u64 %rd106, %rd105;
|
|
ld.const.u32 %r326, [params+264];
|
|
mad.lo.s32 %r327, %r326, %r5, %r4;
|
|
mul.wide.u32 %rd107, %r327, 8;
|
|
add.s64 %rd23, %rd106, %rd107;
|
|
@%p150 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs125, %rs126, %rs127, %rs128}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1035, %rs125;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1036, %rs126;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1037, %rs127;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1038, %f1035, 0f00000000;
|
|
add.f32 %f1039, %f1036, 0f00000000;
|
|
add.f32 %f1040, %f1037, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs124, %f1040;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1039;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1038;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs129, 0;
|
|
st.global.v4.u16 [%rd23], {%rs122, %rs123, %rs124, %rs129};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1043, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1043;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs131, %f1043;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1043;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs133, 0;
|
|
st.global.v4.u16 [%rd23], {%rs130, %rs131, %rs132, %rs133};
|
|
|
|
$L__BB0_140:
|
|
ld.const.u64 %rd108, [params+288];
|
|
cvta.to.global.u64 %rd109, %rd108;
|
|
ld.const.u32 %r328, [params+280];
|
|
mad.lo.s32 %r329, %r328, %r5, %r4;
|
|
mul.wide.u32 %rd110, %r329, 8;
|
|
add.s64 %rd24, %rd109, %rd110;
|
|
@%p150 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs140, %rs141, %rs142, %rs143}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1044, %rs140;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1045, %rs141;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1046, %rs142;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1047, %f1044, 0f00000000;
|
|
add.f32 %f1048, %f1045, 0f00000000;
|
|
add.f32 %f1049, %f1046, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs139, %f1049;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1048;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1047;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs144, 0;
|
|
st.global.v4.u16 [%rd24], {%rs137, %rs138, %rs139, %rs144};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1052, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1052;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs148, 0;
|
|
st.global.v4.u16 [%rd24], {%rs145, %rs146, %rs147, %rs148};
|
|
|
|
$L__BB0_143:
|
|
ld.const.u64 %rd111, [params+304];
|
|
cvta.to.global.u64 %rd112, %rd111;
|
|
ld.const.u32 %r330, [params+296];
|
|
mad.lo.s32 %r331, %r330, %r5, %r4;
|
|
mul.wide.u32 %rd113, %r331, 8;
|
|
add.s64 %rd25, %rd112, %rd113;
|
|
@%p150 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs155, %rs156, %rs157, %rs158}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1053, %rs155;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1054, %rs156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1055, %rs157;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1056, %f1053, 0f00000000;
|
|
add.f32 %f1057, %f1054, 0f00000000;
|
|
add.f32 %f1058, %f1055, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs154, %f1058;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1057;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1056;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs159, 0;
|
|
st.global.v4.u16 [%rd25], {%rs152, %rs153, %rs154, %rs159};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1061, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1061;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1061;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1061;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs163, 0;
|
|
st.global.v4.u16 [%rd25], {%rs160, %rs161, %rs162, %rs163};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_42:
|
|
mov.b32 %r220, %f1149;
|
|
xor.b32 %r221, %r220, -2147483648;
|
|
mov.b32 %f498, %r221;
|
|
selp.f32 %f1151, %f498, %f1149, %p1;
|
|
setp.geu.f32 %p53, %f1146, 0f00000000;
|
|
@%p53 bra $L__BB0_46;
|
|
|
|
mov.f32 %f499, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f500, %f499;
|
|
setp.eq.f32 %p54, %f500, 0f3EE66666;
|
|
@%p54 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1151, 0f7FFFFFFF;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f1077, %f1146;
|
|
add.f32 %f503, %f1077, 0f3EE66666;
|
|
mov.b32 %r222, %f503;
|
|
setp.lt.s32 %p56, %r222, 2139095040;
|
|
@%p56 bra $L__BB0_51;
|
|
|
|
abs.f32 %f1078, %f1146;
|
|
setp.gtu.f32 %p57, %f1078, 0f7F800000;
|
|
@%p57 bra $L__BB0_50;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_50:
|
|
add.f32 %f1151, %f1146, 0f3EE66666;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_48:
|
|
abs.f32 %f1079, %f1146;
|
|
setp.neu.f32 %p58, %f1079, 0f7F800000;
|
|
@%p58 bra $L__BB0_51;
|
|
|
|
selp.f32 %f1151, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_51:
|
|
setp.eq.f32 %p59, %f1146, 0f3F800000;
|
|
selp.f32 %f152, 0f3F800000, %f1151, %p59;
|
|
abs.f32 %f153, %f1147;
|
|
setp.lt.f32 %p60, %f153, 0f00800000;
|
|
mul.f32 %f505, %f153, 0f4B800000;
|
|
selp.f32 %f506, %f505, %f153, %p60;
|
|
selp.f32 %f507, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r223, %f506;
|
|
and.b32 %r224, %r223, 8388607;
|
|
or.b32 %r225, %r224, 1065353216;
|
|
mov.b32 %f508, %r225;
|
|
shr.u32 %r226, %r223, 23;
|
|
cvt.rn.f32.u32 %f509, %r226;
|
|
add.f32 %f510, %f507, %f509;
|
|
setp.gt.f32 %p61, %f508, 0f3FB504F3;
|
|
mul.f32 %f511, %f508, 0f3F000000;
|
|
add.f32 %f512, %f510, 0f3F800000;
|
|
selp.f32 %f513, %f512, %f510, %p61;
|
|
selp.f32 %f514, %f511, %f508, %p61;
|
|
add.f32 %f515, %f514, 0fBF800000;
|
|
add.f32 %f516, %f514, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f517, %f516;
|
|
add.f32 %f518, %f515, %f515;
|
|
mul.f32 %f519, %f518, %f517;
|
|
mul.f32 %f520, %f519, %f519;
|
|
mov.f32 %f521, 0f3C4CAF63;
|
|
mov.f32 %f522, 0f3B18F0FE;
|
|
fma.rn.f32 %f523, %f522, %f520, %f521;
|
|
mov.f32 %f524, 0f3DAAAABD;
|
|
fma.rn.f32 %f525, %f523, %f520, %f524;
|
|
mul.rn.f32 %f526, %f525, %f520;
|
|
mul.rn.f32 %f527, %f526, %f519;
|
|
sub.f32 %f528, %f515, %f519;
|
|
add.f32 %f529, %f528, %f528;
|
|
neg.f32 %f530, %f519;
|
|
fma.rn.f32 %f531, %f530, %f515, %f529;
|
|
mul.rn.f32 %f532, %f517, %f531;
|
|
add.f32 %f533, %f527, %f519;
|
|
sub.f32 %f534, %f519, %f533;
|
|
add.f32 %f535, %f527, %f534;
|
|
add.f32 %f536, %f532, %f535;
|
|
add.f32 %f537, %f533, %f536;
|
|
sub.f32 %f538, %f533, %f537;
|
|
add.f32 %f539, %f536, %f538;
|
|
mov.f32 %f540, 0f3F317200;
|
|
mul.rn.f32 %f541, %f513, %f540;
|
|
mov.f32 %f542, 0f35BFBE8E;
|
|
mul.rn.f32 %f543, %f513, %f542;
|
|
add.f32 %f544, %f541, %f537;
|
|
sub.f32 %f545, %f541, %f544;
|
|
add.f32 %f546, %f537, %f545;
|
|
add.f32 %f547, %f539, %f546;
|
|
add.f32 %f548, %f543, %f547;
|
|
add.f32 %f549, %f544, %f548;
|
|
sub.f32 %f550, %f544, %f549;
|
|
add.f32 %f551, %f548, %f550;
|
|
mov.f32 %f552, 0f3EE66666;
|
|
mul.rn.f32 %f553, %f552, %f549;
|
|
neg.f32 %f554, %f553;
|
|
fma.rn.f32 %f555, %f552, %f549, %f554;
|
|
fma.rn.f32 %f556, %f552, %f551, %f555;
|
|
mov.f32 %f557, 0f00000000;
|
|
fma.rn.f32 %f558, %f557, %f549, %f556;
|
|
add.rn.f32 %f559, %f553, %f558;
|
|
neg.f32 %f560, %f559;
|
|
add.rn.f32 %f561, %f553, %f560;
|
|
add.rn.f32 %f562, %f561, %f558;
|
|
mov.b32 %r227, %f559;
|
|
setp.eq.s32 %p62, %r227, 1118925336;
|
|
add.s32 %r228, %r227, -1;
|
|
mov.b32 %f563, %r228;
|
|
add.f32 %f564, %f562, 0f37000000;
|
|
selp.f32 %f154, %f564, %f562, %p62;
|
|
selp.f32 %f565, %f563, %f559, %p62;
|
|
mov.f32 %f566, 0f3FB8AA3B;
|
|
mul.rn.f32 %f567, %f565, %f566;
|
|
cvt.rzi.f32.f32 %f568, %f567;
|
|
abs.f32 %f569, %f568;
|
|
setp.gt.f32 %p63, %f569, 0f42FC0000;
|
|
mov.b32 %r229, %f568;
|
|
and.b32 %r230, %r229, -2147483648;
|
|
or.b32 %r231, %r230, 1123811328;
|
|
mov.b32 %f570, %r231;
|
|
selp.f32 %f571, %f570, %f568, %p63;
|
|
mov.f32 %f572, 0fBF317218;
|
|
fma.rn.f32 %f573, %f571, %f572, %f565;
|
|
mov.f32 %f574, 0f3102E308;
|
|
fma.rn.f32 %f575, %f571, %f574, %f573;
|
|
mul.f32 %f576, %f575, 0f3FB8AA3B;
|
|
add.f32 %f577, %f571, 0f4B40007F;
|
|
mov.b32 %r232, %f577;
|
|
shl.b32 %r233, %r232, 23;
|
|
mov.b32 %f578, %r233;
|
|
ex2.approx.ftz.f32 %f579, %f576;
|
|
mul.f32 %f155, %f579, %f578;
|
|
setp.eq.f32 %p64, %f155, 0f7F800000;
|
|
mov.f32 %f1152, 0f7F800000;
|
|
@%p64 bra $L__BB0_53;
|
|
|
|
fma.rn.f32 %f1152, %f155, %f154, %f155;
|
|
|
|
$L__BB0_53:
|
|
setp.lt.f32 %p65, %f1147, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f1147, 0f00000000;
|
|
@%p67 bra $L__BB0_57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f584, %f1147, %f1147;
|
|
selp.f32 %f1154, %f584, 0f00000000, %p51;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_54:
|
|
mov.b32 %r234, %f1152;
|
|
xor.b32 %r235, %r234, -2147483648;
|
|
mov.b32 %f580, %r235;
|
|
selp.f32 %f1154, %f580, %f1152, %p2;
|
|
setp.geu.f32 %p68, %f1147, 0f00000000;
|
|
@%p68 bra $L__BB0_58;
|
|
|
|
mov.f32 %f581, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f582, %f581;
|
|
setp.eq.f32 %p69, %f582, 0f3EE66666;
|
|
@%p69 bra $L__BB0_58;
|
|
|
|
mov.f32 %f1154, 0f7FFFFFFF;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1080, %f1147;
|
|
add.f32 %f585, %f1080, 0f3EE66666;
|
|
mov.b32 %r236, %f585;
|
|
setp.lt.s32 %p71, %r236, 2139095040;
|
|
@%p71 bra $L__BB0_63;
|
|
|
|
abs.f32 %f1081, %f1147;
|
|
setp.gtu.f32 %p72, %f1081, 0f7F800000;
|
|
@%p72 bra $L__BB0_62;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1154, %f1147, 0f3EE66666;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f1082, %f1147;
|
|
setp.neu.f32 %p73, %f1082, 0f7F800000;
|
|
@%p73 bra $L__BB0_63;
|
|
|
|
selp.f32 %f1154, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_63:
|
|
setp.eq.f32 %p74, %f1147, 0f3F800000;
|
|
selp.f32 %f164, 0f3F800000, %f1154, %p74;
|
|
abs.f32 %f165, %f1148;
|
|
setp.lt.f32 %p75, %f165, 0f00800000;
|
|
mul.f32 %f587, %f165, 0f4B800000;
|
|
selp.f32 %f588, %f587, %f165, %p75;
|
|
selp.f32 %f589, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r237, %f588;
|
|
and.b32 %r238, %r237, 8388607;
|
|
or.b32 %r239, %r238, 1065353216;
|
|
mov.b32 %f590, %r239;
|
|
shr.u32 %r240, %r237, 23;
|
|
cvt.rn.f32.u32 %f591, %r240;
|
|
add.f32 %f592, %f589, %f591;
|
|
setp.gt.f32 %p76, %f590, 0f3FB504F3;
|
|
mul.f32 %f593, %f590, 0f3F000000;
|
|
add.f32 %f594, %f592, 0f3F800000;
|
|
selp.f32 %f595, %f594, %f592, %p76;
|
|
selp.f32 %f596, %f593, %f590, %p76;
|
|
add.f32 %f597, %f596, 0fBF800000;
|
|
add.f32 %f598, %f596, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f599, %f598;
|
|
add.f32 %f600, %f597, %f597;
|
|
mul.f32 %f601, %f600, %f599;
|
|
mul.f32 %f602, %f601, %f601;
|
|
mov.f32 %f603, 0f3C4CAF63;
|
|
mov.f32 %f604, 0f3B18F0FE;
|
|
fma.rn.f32 %f605, %f604, %f602, %f603;
|
|
mov.f32 %f606, 0f3DAAAABD;
|
|
fma.rn.f32 %f607, %f605, %f602, %f606;
|
|
mul.rn.f32 %f608, %f607, %f602;
|
|
mul.rn.f32 %f609, %f608, %f601;
|
|
sub.f32 %f610, %f597, %f601;
|
|
add.f32 %f611, %f610, %f610;
|
|
neg.f32 %f612, %f601;
|
|
fma.rn.f32 %f613, %f612, %f597, %f611;
|
|
mul.rn.f32 %f614, %f599, %f613;
|
|
add.f32 %f615, %f609, %f601;
|
|
sub.f32 %f616, %f601, %f615;
|
|
add.f32 %f617, %f609, %f616;
|
|
add.f32 %f618, %f614, %f617;
|
|
add.f32 %f619, %f615, %f618;
|
|
sub.f32 %f620, %f615, %f619;
|
|
add.f32 %f621, %f618, %f620;
|
|
mov.f32 %f622, 0f3F317200;
|
|
mul.rn.f32 %f623, %f595, %f622;
|
|
mov.f32 %f624, 0f35BFBE8E;
|
|
mul.rn.f32 %f625, %f595, %f624;
|
|
add.f32 %f626, %f623, %f619;
|
|
sub.f32 %f627, %f623, %f626;
|
|
add.f32 %f628, %f619, %f627;
|
|
add.f32 %f629, %f621, %f628;
|
|
add.f32 %f630, %f625, %f629;
|
|
add.f32 %f631, %f626, %f630;
|
|
sub.f32 %f632, %f626, %f631;
|
|
add.f32 %f633, %f630, %f632;
|
|
mov.f32 %f634, 0f3EE66666;
|
|
mul.rn.f32 %f635, %f634, %f631;
|
|
neg.f32 %f636, %f635;
|
|
fma.rn.f32 %f637, %f634, %f631, %f636;
|
|
fma.rn.f32 %f638, %f634, %f633, %f637;
|
|
mov.f32 %f639, 0f00000000;
|
|
fma.rn.f32 %f640, %f639, %f631, %f638;
|
|
add.rn.f32 %f641, %f635, %f640;
|
|
neg.f32 %f642, %f641;
|
|
add.rn.f32 %f643, %f635, %f642;
|
|
add.rn.f32 %f644, %f643, %f640;
|
|
mov.b32 %r241, %f641;
|
|
setp.eq.s32 %p77, %r241, 1118925336;
|
|
add.s32 %r242, %r241, -1;
|
|
mov.b32 %f645, %r242;
|
|
add.f32 %f646, %f644, 0f37000000;
|
|
selp.f32 %f166, %f646, %f644, %p77;
|
|
selp.f32 %f647, %f645, %f641, %p77;
|
|
mov.f32 %f648, 0f3FB8AA3B;
|
|
mul.rn.f32 %f649, %f647, %f648;
|
|
cvt.rzi.f32.f32 %f650, %f649;
|
|
abs.f32 %f651, %f650;
|
|
setp.gt.f32 %p78, %f651, 0f42FC0000;
|
|
mov.b32 %r243, %f650;
|
|
and.b32 %r244, %r243, -2147483648;
|
|
or.b32 %r245, %r244, 1123811328;
|
|
mov.b32 %f652, %r245;
|
|
selp.f32 %f653, %f652, %f650, %p78;
|
|
mov.f32 %f654, 0fBF317218;
|
|
fma.rn.f32 %f655, %f653, %f654, %f647;
|
|
mov.f32 %f656, 0f3102E308;
|
|
fma.rn.f32 %f657, %f653, %f656, %f655;
|
|
mul.f32 %f658, %f657, 0f3FB8AA3B;
|
|
add.f32 %f659, %f653, 0f4B40007F;
|
|
mov.b32 %r246, %f659;
|
|
shl.b32 %r247, %r246, 23;
|
|
mov.b32 %f660, %r247;
|
|
ex2.approx.ftz.f32 %f661, %f658;
|
|
mul.f32 %f167, %f661, %f660;
|
|
setp.eq.f32 %p79, %f167, 0f7F800000;
|
|
mov.f32 %f1155, 0f7F800000;
|
|
@%p79 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1155, %f167, %f166, %f167;
|
|
|
|
$L__BB0_65:
|
|
setp.lt.f32 %p80, %f1148, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f1148, 0f00000000;
|
|
@%p82 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f666, %f1148, %f1148;
|
|
selp.f32 %f1157, %f666, 0f00000000, %p51;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r248, %f1155;
|
|
xor.b32 %r249, %r248, -2147483648;
|
|
mov.b32 %f662, %r249;
|
|
selp.f32 %f1157, %f662, %f1155, %p3;
|
|
setp.geu.f32 %p83, %f1148, 0f00000000;
|
|
@%p83 bra $L__BB0_70;
|
|
|
|
mov.f32 %f663, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f664, %f663;
|
|
setp.eq.f32 %p84, %f664, 0f3EE66666;
|
|
@%p84 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1157, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1083, %f1148;
|
|
add.f32 %f667, %f1083, 0f3EE66666;
|
|
mov.b32 %r250, %f667;
|
|
setp.lt.s32 %p86, %r250, 2139095040;
|
|
@%p86 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1084, %f1148;
|
|
setp.gtu.f32 %p87, %f1084, 0f7F800000;
|
|
@%p87 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1157, %f1148, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1085, %f1148;
|
|
setp.neu.f32 %p88, %f1085, 0f7F800000;
|
|
@%p88 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1157, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p89, %f1148, 0f3F800000;
|
|
mov.f32 %f669, 0f3F800000;
|
|
selp.f32 %f670, 0f3F800000, %f1157, %p89;
|
|
min.f32 %f671, %f152, %f669;
|
|
mov.f32 %f672, 0f00000000;
|
|
max.f32 %f176, %f672, %f671;
|
|
min.f32 %f673, %f164, %f669;
|
|
max.f32 %f177, %f672, %f673;
|
|
min.f32 %f674, %f670, %f669;
|
|
max.f32 %f178, %f672, %f674;
|
|
mov.f32 %f678, 0f3ED55555;
|
|
abs.f32 %f180, %f176;
|
|
setp.lt.f32 %p90, %f180, 0f00800000;
|
|
mul.f32 %f680, %f180, 0f4B800000;
|
|
selp.f32 %f681, %f680, %f180, %p90;
|
|
selp.f32 %f682, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r253, %f681;
|
|
and.b32 %r254, %r253, 8388607;
|
|
or.b32 %r255, %r254, 1065353216;
|
|
mov.b32 %f683, %r255;
|
|
shr.u32 %r256, %r253, 23;
|
|
cvt.rn.f32.u32 %f684, %r256;
|
|
add.f32 %f685, %f682, %f684;
|
|
setp.gt.f32 %p91, %f683, 0f3FB504F3;
|
|
mul.f32 %f686, %f683, 0f3F000000;
|
|
add.f32 %f687, %f685, 0f3F800000;
|
|
selp.f32 %f688, %f687, %f685, %p91;
|
|
selp.f32 %f689, %f686, %f683, %p91;
|
|
add.f32 %f690, %f689, 0fBF800000;
|
|
add.f32 %f691, %f689, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f692, %f691;
|
|
add.f32 %f693, %f690, %f690;
|
|
mul.f32 %f694, %f693, %f692;
|
|
mul.f32 %f695, %f694, %f694;
|
|
mov.f32 %f696, 0f3C4CAF63;
|
|
mov.f32 %f697, 0f3B18F0FE;
|
|
fma.rn.f32 %f698, %f697, %f695, %f696;
|
|
mov.f32 %f699, 0f3DAAAABD;
|
|
fma.rn.f32 %f700, %f698, %f695, %f699;
|
|
mul.rn.f32 %f701, %f700, %f695;
|
|
mul.rn.f32 %f702, %f701, %f694;
|
|
sub.f32 %f703, %f690, %f694;
|
|
add.f32 %f704, %f703, %f703;
|
|
neg.f32 %f705, %f694;
|
|
fma.rn.f32 %f706, %f705, %f690, %f704;
|
|
mul.rn.f32 %f707, %f692, %f706;
|
|
add.f32 %f708, %f702, %f694;
|
|
sub.f32 %f709, %f694, %f708;
|
|
add.f32 %f710, %f702, %f709;
|
|
add.f32 %f711, %f707, %f710;
|
|
add.f32 %f712, %f708, %f711;
|
|
sub.f32 %f713, %f708, %f712;
|
|
add.f32 %f714, %f711, %f713;
|
|
mov.f32 %f715, 0f3F317200;
|
|
mul.rn.f32 %f716, %f688, %f715;
|
|
mov.f32 %f717, 0f35BFBE8E;
|
|
mul.rn.f32 %f718, %f688, %f717;
|
|
add.f32 %f719, %f716, %f712;
|
|
sub.f32 %f720, %f716, %f719;
|
|
add.f32 %f721, %f712, %f720;
|
|
add.f32 %f722, %f714, %f721;
|
|
add.f32 %f723, %f718, %f722;
|
|
add.f32 %f724, %f719, %f723;
|
|
sub.f32 %f725, %f719, %f724;
|
|
add.f32 %f726, %f723, %f725;
|
|
mul.rn.f32 %f727, %f678, %f724;
|
|
neg.f32 %f728, %f727;
|
|
fma.rn.f32 %f729, %f678, %f724, %f728;
|
|
fma.rn.f32 %f730, %f678, %f726, %f729;
|
|
fma.rn.f32 %f731, %f672, %f724, %f730;
|
|
add.rn.f32 %f732, %f727, %f731;
|
|
neg.f32 %f733, %f732;
|
|
add.rn.f32 %f734, %f727, %f733;
|
|
add.rn.f32 %f735, %f734, %f731;
|
|
mov.b32 %r257, %f732;
|
|
setp.eq.s32 %p92, %r257, 1118925336;
|
|
add.s32 %r258, %r257, -1;
|
|
mov.b32 %f736, %r258;
|
|
add.f32 %f737, %f735, 0f37000000;
|
|
selp.f32 %f181, %f737, %f735, %p92;
|
|
selp.f32 %f738, %f736, %f732, %p92;
|
|
mov.f32 %f739, 0f3FB8AA3B;
|
|
mul.rn.f32 %f740, %f738, %f739;
|
|
cvt.rzi.f32.f32 %f741, %f740;
|
|
abs.f32 %f742, %f741;
|
|
setp.gt.f32 %p93, %f742, 0f42FC0000;
|
|
mov.b32 %r259, %f741;
|
|
and.b32 %r260, %r259, -2147483648;
|
|
or.b32 %r261, %r260, 1123811328;
|
|
mov.b32 %f743, %r261;
|
|
selp.f32 %f744, %f743, %f741, %p93;
|
|
mov.f32 %f745, 0fBF317218;
|
|
fma.rn.f32 %f746, %f744, %f745, %f738;
|
|
mov.f32 %f747, 0f3102E308;
|
|
fma.rn.f32 %f748, %f744, %f747, %f746;
|
|
mul.f32 %f749, %f748, 0f3FB8AA3B;
|
|
add.f32 %f750, %f744, 0f4B40007F;
|
|
mov.b32 %r262, %f750;
|
|
shl.b32 %r263, %r262, 23;
|
|
mov.b32 %f751, %r263;
|
|
ex2.approx.ftz.f32 %f752, %f749;
|
|
mul.f32 %f182, %f752, %f751;
|
|
setp.eq.f32 %p94, %f182, 0f7F800000;
|
|
mov.f32 %f1158, 0f7F800000;
|
|
@%p94 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1158, %f182, %f181, %f182;
|
|
|
|
$L__BB0_77:
|
|
mov.f32 %f1091, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1090, %f1091;
|
|
add.f32 %f1089, %f1090, %f1090;
|
|
mov.f32 %f1088, 0f3ED55555;
|
|
sub.f32 %f1087, %f1088, %f1089;
|
|
abs.f32 %f1086, %f1087;
|
|
setp.lt.f32 %p95, %f176, 0f00000000;
|
|
setp.eq.f32 %p96, %f1086, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f176, 0f00000000;
|
|
@%p97 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f757, %f176, %f176;
|
|
selp.f32 %f1160, %f757, 0f00000000, %p96;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r264, %f1158;
|
|
xor.b32 %r265, %r264, -2147483648;
|
|
mov.b32 %f753, %r265;
|
|
selp.f32 %f1160, %f753, %f1158, %p4;
|
|
setp.geu.f32 %p98, %f176, 0f00000000;
|
|
@%p98 bra $L__BB0_82;
|
|
|
|
mov.f32 %f754, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f755, %f754;
|
|
setp.eq.f32 %p99, %f755, 0f3ED55555;
|
|
@%p99 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1160, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
add.f32 %f758, %f180, 0f3ED55555;
|
|
mov.b32 %r266, %f758;
|
|
setp.lt.s32 %p101, %r266, 2139095040;
|
|
@%p101 bra $L__BB0_87;
|
|
|
|
setp.gtu.f32 %p102, %f180, 0f7F800000;
|
|
@%p102 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1160, %f176, 0f3ED55555;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
setp.neu.f32 %p103, %f180, 0f7F800000;
|
|
@%p103 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1160, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
abs.f32 %f191, %f177;
|
|
setp.lt.f32 %p104, %f191, 0f00800000;
|
|
mul.f32 %f760, %f191, 0f4B800000;
|
|
selp.f32 %f761, %f760, %f191, %p104;
|
|
selp.f32 %f762, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r267, %f761;
|
|
and.b32 %r268, %r267, 8388607;
|
|
or.b32 %r269, %r268, 1065353216;
|
|
mov.b32 %f763, %r269;
|
|
shr.u32 %r270, %r267, 23;
|
|
cvt.rn.f32.u32 %f764, %r270;
|
|
add.f32 %f765, %f762, %f764;
|
|
setp.gt.f32 %p105, %f763, 0f3FB504F3;
|
|
mul.f32 %f766, %f763, 0f3F000000;
|
|
add.f32 %f767, %f765, 0f3F800000;
|
|
selp.f32 %f768, %f767, %f765, %p105;
|
|
selp.f32 %f769, %f766, %f763, %p105;
|
|
add.f32 %f770, %f769, 0fBF800000;
|
|
add.f32 %f771, %f769, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f772, %f771;
|
|
add.f32 %f773, %f770, %f770;
|
|
mul.f32 %f774, %f773, %f772;
|
|
mul.f32 %f775, %f774, %f774;
|
|
mov.f32 %f776, 0f3C4CAF63;
|
|
mov.f32 %f777, 0f3B18F0FE;
|
|
fma.rn.f32 %f778, %f777, %f775, %f776;
|
|
mov.f32 %f779, 0f3DAAAABD;
|
|
fma.rn.f32 %f780, %f778, %f775, %f779;
|
|
mul.rn.f32 %f781, %f780, %f775;
|
|
mul.rn.f32 %f782, %f781, %f774;
|
|
sub.f32 %f783, %f770, %f774;
|
|
add.f32 %f784, %f783, %f783;
|
|
neg.f32 %f785, %f774;
|
|
fma.rn.f32 %f786, %f785, %f770, %f784;
|
|
mul.rn.f32 %f787, %f772, %f786;
|
|
add.f32 %f788, %f782, %f774;
|
|
sub.f32 %f789, %f774, %f788;
|
|
add.f32 %f790, %f782, %f789;
|
|
add.f32 %f791, %f787, %f790;
|
|
add.f32 %f792, %f788, %f791;
|
|
sub.f32 %f793, %f788, %f792;
|
|
add.f32 %f794, %f791, %f793;
|
|
mov.f32 %f795, 0f3F317200;
|
|
mul.rn.f32 %f796, %f768, %f795;
|
|
mov.f32 %f797, 0f35BFBE8E;
|
|
mul.rn.f32 %f798, %f768, %f797;
|
|
add.f32 %f799, %f796, %f792;
|
|
sub.f32 %f800, %f796, %f799;
|
|
add.f32 %f801, %f792, %f800;
|
|
add.f32 %f802, %f794, %f801;
|
|
add.f32 %f803, %f798, %f802;
|
|
add.f32 %f804, %f799, %f803;
|
|
sub.f32 %f805, %f799, %f804;
|
|
add.f32 %f806, %f803, %f805;
|
|
mov.f32 %f807, 0f3ED55555;
|
|
mul.rn.f32 %f808, %f807, %f804;
|
|
neg.f32 %f809, %f808;
|
|
fma.rn.f32 %f810, %f807, %f804, %f809;
|
|
fma.rn.f32 %f811, %f807, %f806, %f810;
|
|
mov.f32 %f812, 0f00000000;
|
|
fma.rn.f32 %f813, %f812, %f804, %f811;
|
|
add.rn.f32 %f814, %f808, %f813;
|
|
neg.f32 %f815, %f814;
|
|
add.rn.f32 %f816, %f808, %f815;
|
|
add.rn.f32 %f817, %f816, %f813;
|
|
mov.b32 %r271, %f814;
|
|
setp.eq.s32 %p106, %r271, 1118925336;
|
|
add.s32 %r272, %r271, -1;
|
|
mov.b32 %f818, %r272;
|
|
add.f32 %f819, %f817, 0f37000000;
|
|
selp.f32 %f192, %f819, %f817, %p106;
|
|
selp.f32 %f820, %f818, %f814, %p106;
|
|
mov.f32 %f821, 0f3FB8AA3B;
|
|
mul.rn.f32 %f822, %f820, %f821;
|
|
cvt.rzi.f32.f32 %f823, %f822;
|
|
abs.f32 %f824, %f823;
|
|
setp.gt.f32 %p107, %f824, 0f42FC0000;
|
|
mov.b32 %r273, %f823;
|
|
and.b32 %r274, %r273, -2147483648;
|
|
or.b32 %r275, %r274, 1123811328;
|
|
mov.b32 %f825, %r275;
|
|
selp.f32 %f826, %f825, %f823, %p107;
|
|
mov.f32 %f827, 0fBF317218;
|
|
fma.rn.f32 %f828, %f826, %f827, %f820;
|
|
mov.f32 %f829, 0f3102E308;
|
|
fma.rn.f32 %f830, %f826, %f829, %f828;
|
|
mul.f32 %f831, %f830, 0f3FB8AA3B;
|
|
add.f32 %f832, %f826, 0f4B40007F;
|
|
mov.b32 %r276, %f832;
|
|
shl.b32 %r277, %r276, 23;
|
|
mov.b32 %f833, %r277;
|
|
ex2.approx.ftz.f32 %f834, %f831;
|
|
mul.f32 %f193, %f834, %f833;
|
|
setp.eq.f32 %p108, %f193, 0f7F800000;
|
|
mov.f32 %f1161, 0f7F800000;
|
|
@%p108 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1161, %f193, %f192, %f193;
|
|
|
|
$L__BB0_89:
|
|
setp.lt.f32 %p109, %f177, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f177, 0f00000000;
|
|
@%p111 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f839, %f177, %f177;
|
|
selp.f32 %f1163, %f839, 0f00000000, %p96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.b32 %r278, %f1161;
|
|
xor.b32 %r279, %r278, -2147483648;
|
|
mov.b32 %f835, %r279;
|
|
selp.f32 %f1163, %f835, %f1161, %p5;
|
|
setp.geu.f32 %p112, %f177, 0f00000000;
|
|
@%p112 bra $L__BB0_94;
|
|
|
|
mov.f32 %f836, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f837, %f836;
|
|
setp.eq.f32 %p113, %f837, 0f3ED55555;
|
|
@%p113 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1163, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f840, %f191, 0f3ED55555;
|
|
mov.b32 %r280, %f840;
|
|
setp.lt.s32 %p115, %r280, 2139095040;
|
|
@%p115 bra $L__BB0_99;
|
|
|
|
setp.gtu.f32 %p116, %f191, 0f7F800000;
|
|
@%p116 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f1163, %f177, 0f3ED55555;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
setp.neu.f32 %p117, %f191, 0f7F800000;
|
|
@%p117 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1163, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
abs.f32 %f202, %f178;
|
|
setp.lt.f32 %p118, %f202, 0f00800000;
|
|
mul.f32 %f842, %f202, 0f4B800000;
|
|
selp.f32 %f843, %f842, %f202, %p118;
|
|
selp.f32 %f844, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r281, %f843;
|
|
and.b32 %r282, %r281, 8388607;
|
|
or.b32 %r283, %r282, 1065353216;
|
|
mov.b32 %f845, %r283;
|
|
shr.u32 %r284, %r281, 23;
|
|
cvt.rn.f32.u32 %f846, %r284;
|
|
add.f32 %f847, %f844, %f846;
|
|
setp.gt.f32 %p119, %f845, 0f3FB504F3;
|
|
mul.f32 %f848, %f845, 0f3F000000;
|
|
add.f32 %f849, %f847, 0f3F800000;
|
|
selp.f32 %f850, %f849, %f847, %p119;
|
|
selp.f32 %f851, %f848, %f845, %p119;
|
|
add.f32 %f852, %f851, 0fBF800000;
|
|
add.f32 %f853, %f851, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f854, %f853;
|
|
add.f32 %f855, %f852, %f852;
|
|
mul.f32 %f856, %f855, %f854;
|
|
mul.f32 %f857, %f856, %f856;
|
|
mov.f32 %f858, 0f3C4CAF63;
|
|
mov.f32 %f859, 0f3B18F0FE;
|
|
fma.rn.f32 %f860, %f859, %f857, %f858;
|
|
mov.f32 %f861, 0f3DAAAABD;
|
|
fma.rn.f32 %f862, %f860, %f857, %f861;
|
|
mul.rn.f32 %f863, %f862, %f857;
|
|
mul.rn.f32 %f864, %f863, %f856;
|
|
sub.f32 %f865, %f852, %f856;
|
|
add.f32 %f866, %f865, %f865;
|
|
neg.f32 %f867, %f856;
|
|
fma.rn.f32 %f868, %f867, %f852, %f866;
|
|
mul.rn.f32 %f869, %f854, %f868;
|
|
add.f32 %f870, %f864, %f856;
|
|
sub.f32 %f871, %f856, %f870;
|
|
add.f32 %f872, %f864, %f871;
|
|
add.f32 %f873, %f869, %f872;
|
|
add.f32 %f874, %f870, %f873;
|
|
sub.f32 %f875, %f870, %f874;
|
|
add.f32 %f876, %f873, %f875;
|
|
mov.f32 %f877, 0f3F317200;
|
|
mul.rn.f32 %f878, %f850, %f877;
|
|
mov.f32 %f879, 0f35BFBE8E;
|
|
mul.rn.f32 %f880, %f850, %f879;
|
|
add.f32 %f881, %f878, %f874;
|
|
sub.f32 %f882, %f878, %f881;
|
|
add.f32 %f883, %f874, %f882;
|
|
add.f32 %f884, %f876, %f883;
|
|
add.f32 %f885, %f880, %f884;
|
|
add.f32 %f886, %f881, %f885;
|
|
sub.f32 %f887, %f881, %f886;
|
|
add.f32 %f888, %f885, %f887;
|
|
mov.f32 %f889, 0f3ED55555;
|
|
mul.rn.f32 %f890, %f889, %f886;
|
|
neg.f32 %f891, %f890;
|
|
fma.rn.f32 %f892, %f889, %f886, %f891;
|
|
fma.rn.f32 %f893, %f889, %f888, %f892;
|
|
mov.f32 %f894, 0f00000000;
|
|
fma.rn.f32 %f895, %f894, %f886, %f893;
|
|
add.rn.f32 %f896, %f890, %f895;
|
|
neg.f32 %f897, %f896;
|
|
add.rn.f32 %f898, %f890, %f897;
|
|
add.rn.f32 %f899, %f898, %f895;
|
|
mov.b32 %r285, %f896;
|
|
setp.eq.s32 %p120, %r285, 1118925336;
|
|
add.s32 %r286, %r285, -1;
|
|
mov.b32 %f900, %r286;
|
|
add.f32 %f901, %f899, 0f37000000;
|
|
selp.f32 %f203, %f901, %f899, %p120;
|
|
selp.f32 %f902, %f900, %f896, %p120;
|
|
mov.f32 %f903, 0f3FB8AA3B;
|
|
mul.rn.f32 %f904, %f902, %f903;
|
|
cvt.rzi.f32.f32 %f905, %f904;
|
|
abs.f32 %f906, %f905;
|
|
setp.gt.f32 %p121, %f906, 0f42FC0000;
|
|
mov.b32 %r287, %f905;
|
|
and.b32 %r288, %r287, -2147483648;
|
|
or.b32 %r289, %r288, 1123811328;
|
|
mov.b32 %f907, %r289;
|
|
selp.f32 %f908, %f907, %f905, %p121;
|
|
mov.f32 %f909, 0fBF317218;
|
|
fma.rn.f32 %f910, %f908, %f909, %f902;
|
|
mov.f32 %f911, 0f3102E308;
|
|
fma.rn.f32 %f912, %f908, %f911, %f910;
|
|
mul.f32 %f913, %f912, 0f3FB8AA3B;
|
|
add.f32 %f914, %f908, 0f4B40007F;
|
|
mov.b32 %r290, %f914;
|
|
shl.b32 %r291, %r290, 23;
|
|
mov.b32 %f915, %r291;
|
|
ex2.approx.ftz.f32 %f916, %f913;
|
|
mul.f32 %f204, %f916, %f915;
|
|
setp.eq.f32 %p122, %f204, 0f7F800000;
|
|
mov.f32 %f1164, 0f7F800000;
|
|
@%p122 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1164, %f204, %f203, %f204;
|
|
|
|
$L__BB0_101:
|
|
setp.lt.f32 %p123, %f178, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f178, 0f00000000;
|
|
@%p125 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f921, %f178, %f178;
|
|
selp.f32 %f1166, %f921, 0f00000000, %p96;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r292, %f1164;
|
|
xor.b32 %r293, %r292, -2147483648;
|
|
mov.b32 %f917, %r293;
|
|
selp.f32 %f1166, %f917, %f1164, %p6;
|
|
setp.geu.f32 %p126, %f178, 0f00000000;
|
|
@%p126 bra $L__BB0_106;
|
|
|
|
mov.f32 %f918, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f919, %f918;
|
|
setp.eq.f32 %p127, %f919, 0f3ED55555;
|
|
@%p127 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1166, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
add.f32 %f922, %f202, 0f3ED55555;
|
|
mov.b32 %r294, %f922;
|
|
setp.lt.s32 %p129, %r294, 2139095040;
|
|
@%p129 bra $L__BB0_111;
|
|
|
|
setp.gtu.f32 %p130, %f202, 0f7F800000;
|
|
@%p130 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1166, %f178, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
setp.neu.f32 %p131, %f202, 0f7F800000;
|
|
@%p131 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1166, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
ld.const.u64 %rd116, [params+144];
|
|
cvta.to.global.u64 %rd115, %rd116;
|
|
ld.const.u32 %r351, [params+136];
|
|
mad.lo.s32 %r350, %r351, %r5, %r4;
|
|
cvt.u64.u32 %rd114, %r350;
|
|
fma.rn.f32 %f923, %f1160, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f176, 0f3F800000;
|
|
mov.f32 %f924, 0f3F800000;
|
|
selp.f32 %f925, 0f3F7FFFFF, %f923, %p132;
|
|
mul.f32 %f926, %f176, 0f414EB852;
|
|
setp.lt.f32 %p133, %f176, 0f3B4D2E1C;
|
|
selp.f32 %f927, %f926, %f925, %p133;
|
|
fma.rn.f32 %f928, %f1163, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f177, 0f3F800000;
|
|
selp.f32 %f929, 0f3F7FFFFF, %f928, %p134;
|
|
mul.f32 %f930, %f177, 0f414EB852;
|
|
setp.lt.f32 %p135, %f177, 0f3B4D2E1C;
|
|
selp.f32 %f931, %f930, %f929, %p135;
|
|
fma.rn.f32 %f932, %f1166, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f178, 0f3F800000;
|
|
selp.f32 %f933, 0f3F7FFFFF, %f932, %p136;
|
|
mul.f32 %f934, %f178, 0f414EB852;
|
|
setp.lt.f32 %p137, %f178, 0f3B4D2E1C;
|
|
selp.f32 %f935, %f934, %f933, %p137;
|
|
min.f32 %f936, %f927, %f924;
|
|
mov.f32 %f937, 0f00000000;
|
|
max.f32 %f938, %f937, %f936;
|
|
mul.f32 %f939, %f938, 0f43800000;
|
|
cvt.rzi.u32.f32 %r295, %f939;
|
|
min.u32 %r296, %r295, 255;
|
|
min.f32 %f940, %f931, %f924;
|
|
max.f32 %f941, %f937, %f940;
|
|
mul.f32 %f942, %f941, 0f43800000;
|
|
cvt.rzi.u32.f32 %r297, %f942;
|
|
min.u32 %r298, %r297, 255;
|
|
min.f32 %f943, %f935, %f924;
|
|
max.f32 %f944, %f937, %f943;
|
|
mul.f32 %f945, %f944, 0f43800000;
|
|
cvt.rzi.u32.f32 %r299, %f945;
|
|
min.u32 %r300, %r299, 255;
|
|
shl.b64 %rd68, %rd114, 2;
|
|
add.s64 %rd69, %rd115, %rd68;
|
|
cvt.u16.u32 %rs23, %r300;
|
|
cvt.u16.u32 %rs24, %r298;
|
|
cvt.u16.u32 %rs25, %r296;
|
|
mov.u16 %rs26, 255;
|
|
st.global.v4.u8 [%rd69], {%rs25, %rs24, %rs23, %rs26};
|
|
|
|
$L__BB0_112:
|
|
ld.const.u32 %r348, [params+104];
|
|
and.b32 %r301, %r348, 4;
|
|
setp.eq.s32 %p138, %r301, 0;
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
ld.const.u64 %rd70, [params+224];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r302, [params+216];
|
|
mad.lo.s32 %r303, %r302, %r5, %r4;
|
|
mov.f32 %f949, 0f3F800000;
|
|
mul.wide.u32 %rd72, %r303, 8;
|
|
add.s64 %rd73, %rd71, %rd72;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f949;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f1148;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1146;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd73], {%rs27, %rs28, %rs29, %rs30};
|
|
|
|
$L__BB0_114:
|
|
ld.const.u32 %r349, [params+104];
|
|
and.b32 %r304, %r349, 16;
|
|
setp.eq.s32 %p139, %r304, 0;
|
|
@%p139 bra $L__BB0_116;
|
|
|
|
ld.const.u64 %rd74, [params+240];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r305, [params+232];
|
|
mad.lo.s32 %r306, %r305, %r5, %r4;
|
|
mov.f32 %f953, 0f3F800000;
|
|
mul.wide.u32 %rd76, %r306, 8;
|
|
add.s64 %rd77, %rd75, %rd76;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f953;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f127;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f126;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f125;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd77], {%rs31, %rs32, %rs33, %rs34};
|
|
|
|
$L__BB0_116:
|
|
mul.f32 %f213, %f113, 0f3F000000;
|
|
mul.f32 %f214, %f114, 0f3F000000;
|
|
mul.f32 %f215, %f115, 0f3F000000;
|
|
ld.const.u32 %r49, [params+108];
|
|
setp.eq.s32 %p140, %r49, 0;
|
|
ld.const.u64 %rd78, [params+256];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r307, [params+248];
|
|
mad.lo.s32 %r308, %r307, %r5, %r4;
|
|
mul.wide.u32 %rd80, %r308, 8;
|
|
add.s64 %rd18, %rd79, %rd80;
|
|
@%p140 bra $L__BB0_118;
|
|
|
|
ld.global.v4.u16 {%rs42, %rs43, %rs44, %rs45}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f954, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f955, %rs43;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f956, %rs44;}
|
|
|
|
// end inline asm
|
|
add.f32 %f957, %f213, %f954;
|
|
add.f32 %f958, %f214, %f955;
|
|
add.f32 %f959, %f215, %f956;
|
|
mov.f32 %f960, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f959;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f958;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f957;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f960;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs38, %rs39, %rs40, %rs41};
|
|
bra.uni $L__BB0_119;
|
|
|
|
$L__BB0_118:
|
|
mov.f32 %f964, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f964;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f215;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f214;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f213;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs46, %rs47, %rs48, %rs49};
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f965, 0f34000000;
|
|
max.f32 %f966, %f213, %f965;
|
|
mul.f32 %f967, %f116, 0f3F000000;
|
|
div.rn.f32 %f968, %f967, %f966;
|
|
max.f32 %f969, %f214, %f965;
|
|
mul.f32 %f970, %f117, 0f3F000000;
|
|
div.rn.f32 %f971, %f970, %f969;
|
|
max.f32 %f972, %f215, %f965;
|
|
mul.f32 %f973, %f118, 0f3F000000;
|
|
div.rn.f32 %f974, %f973, %f972;
|
|
fma.rn.f32 %f216, %f968, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f217, %f971, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f218, %f974, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f975, %f119, 0f3F000000;
|
|
div.rn.f32 %f976, %f975, %f966;
|
|
mul.f32 %f977, %f120, 0f3F000000;
|
|
div.rn.f32 %f978, %f977, %f969;
|
|
mul.f32 %f979, %f121, 0f3F000000;
|
|
div.rn.f32 %f980, %f979, %f972;
|
|
fma.rn.f32 %f219, %f976, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f220, %f978, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f221, %f980, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f981, %f122, 0f3F000000;
|
|
div.rn.f32 %f982, %f981, %f966;
|
|
mul.f32 %f983, %f123, 0f3F000000;
|
|
div.rn.f32 %f984, %f983, %f969;
|
|
mul.f32 %f985, %f124, 0f3F000000;
|
|
div.rn.f32 %f986, %f985, %f972;
|
|
fma.rn.f32 %f222, %f982, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f223, %f984, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f224, %f986, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd81, [params+272];
|
|
cvta.to.global.u64 %rd82, %rd81;
|
|
ld.const.u32 %r309, [params+264];
|
|
mad.lo.s32 %r310, %r309, %r5, %r4;
|
|
mul.wide.u32 %rd83, %r310, 8;
|
|
add.s64 %rd19, %rd82, %rd83;
|
|
@%p140 bra $L__BB0_121;
|
|
|
|
ld.global.v4.u16 {%rs57, %rs58, %rs59, %rs60}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f987, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f988, %rs58;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f989, %rs59;}
|
|
|
|
// end inline asm
|
|
add.f32 %f990, %f216, %f987;
|
|
add.f32 %f991, %f217, %f988;
|
|
add.f32 %f992, %f218, %f989;
|
|
mov.f32 %f993, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f992;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f991;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f990;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f993;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs53, %rs54, %rs55, %rs56};
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_121:
|
|
mov.f32 %f997, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f997;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f218;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f217;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f216;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs61, %rs62, %rs63, %rs64};
|
|
|
|
$L__BB0_122:
|
|
ld.const.u64 %rd84, [params+288];
|
|
cvta.to.global.u64 %rd85, %rd84;
|
|
ld.const.u32 %r311, [params+280];
|
|
mad.lo.s32 %r312, %r311, %r5, %r4;
|
|
mul.wide.u32 %rd86, %r312, 8;
|
|
add.s64 %rd20, %rd85, %rd86;
|
|
@%p140 bra $L__BB0_124;
|
|
|
|
ld.global.v4.u16 {%rs72, %rs73, %rs74, %rs75}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f998, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f999, %rs73;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1000, %rs74;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1001, %f219, %f998;
|
|
add.f32 %f1002, %f220, %f999;
|
|
add.f32 %f1003, %f221, %f1000;
|
|
mov.f32 %f1004, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1003;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1002;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1001;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1004;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs68, %rs69, %rs70, %rs71};
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_124:
|
|
mov.f32 %f1008, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f1008;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f220;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f219;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs76, %rs77, %rs78, %rs79};
|
|
|
|
$L__BB0_125:
|
|
ld.const.u64 %rd87, [params+304];
|
|
cvta.to.global.u64 %rd88, %rd87;
|
|
ld.const.u32 %r313, [params+296];
|
|
mad.lo.s32 %r314, %r313, %r5, %r4;
|
|
mul.wide.u32 %rd89, %r314, 8;
|
|
add.s64 %rd21, %rd88, %rd89;
|
|
@%p140 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs87, %rs88, %rs89, %rs90}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1009, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1010, %rs88;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1011, %rs89;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1012, %f222, %f1009;
|
|
add.f32 %f1013, %f223, %f1010;
|
|
add.f32 %f1014, %f224, %f1011;
|
|
mov.f32 %f1015, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1014;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1013;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1012;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1015;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs83, %rs84, %rs85, %rs86};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f1019, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f1019;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f224;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f223;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f222;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs91, %rs92, %rs93, %rs94};
|
|
|
|
$L__BB0_146:
|
|
ret;
|
|
|
|
}
|
|
|