2699 lines
74 KiB
Plaintext
2699 lines
74 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<197>;
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.reg .b16 %rs<177>;
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.reg .f32 %f<1573>;
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.reg .b32 %r<464>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<125>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r60), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r61), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+616];
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abs.s32 %r4, %r3;
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ld.const.u32 %r5, [params+540];
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shl.b32 %r6, %r5, 1;
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ld.const.u64 %rd34, [params+400];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r66, [params+392];
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mad.lo.s32 %r67, %r66, %r61, %r60;
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mul.wide.u32 %rd36, %r67, 4;
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add.s64 %rd2, %rd35, %rd36;
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ld.global.v2.u8 {%rs7, %rs176}, [%rd2];
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or.b16 %rs9, %rs7, %rs176;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p10, %rs10, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs175, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs175, [%rd2+2];
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setp.eq.s16 %p11, %rs175, 0;
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mov.f32 %f1431, 0f00000000;
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mov.u16 %rs176, 0;
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mov.f32 %f1432, %f1431;
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mov.f32 %f1433, %f1431;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f360, %rs7;
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div.rn.f32 %f361, %f360, 0f437F0000;
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fma.rn.f32 %f362, %f361, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs176, 255;
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cvt.rn.f32.u16 %f363, %rs13;
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div.rn.f32 %f364, %f363, 0f437F0000;
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fma.rn.f32 %f365, %f364, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f366, %rs175;
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div.rn.f32 %f367, %f366, 0f437F0000;
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fma.rn.f32 %f368, %f367, 0f40000000, 0fBF800000;
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mul.f32 %f369, %f365, %f365;
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fma.rn.f32 %f370, %f362, %f362, %f369;
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fma.rn.f32 %f371, %f368, %f368, %f370;
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sqrt.rn.f32 %f372, %f371;
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rcp.rn.f32 %f373, %f372;
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mul.f32 %f1433, %f373, %f368;
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mul.f32 %f1432, %f373, %f365;
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mul.f32 %f1431, %f362, %f373;
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$L__BB0_4:
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ld.const.v2.u32 {%r68, %r69}, [params];
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add.s32 %r7, %r68, %r60;
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add.s32 %r8, %r69, %r61;
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setp.eq.f32 %p12, %f1431, 0f00000000;
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setp.eq.f32 %p13, %f1432, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1433, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_158;
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bra.uni $L__BB0_5;
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$L__BB0_158:
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ld.const.u32 %r57, [params+104];
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and.b32 %r429, %r57, 1;
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setp.eq.b32 %p185, %r429, 1;
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mov.pred %p186, 0;
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xor.pred %p187, %p185, %p186;
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not.pred %p188, %p187;
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@%p188 bra $L__BB0_160;
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ld.const.u64 %rd97, [params+144];
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cvta.to.global.u64 %rd98, %rd97;
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ld.const.u32 %r430, [params+136];
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mad.lo.s32 %r431, %r430, %r8, %r7;
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mul.wide.u32 %rd99, %r431, 4;
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add.s64 %rd100, %rd98, %rd99;
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mov.u16 %rs97, 0;
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st.global.v4.u8 [%rd100], {%rs97, %rs97, %rs97, %rs97};
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$L__BB0_160:
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and.b32 %r432, %r57, 8;
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setp.eq.s32 %p189, %r432, 0;
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@%p189 bra $L__BB0_162;
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ld.const.u64 %rd101, [params+192];
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cvta.to.global.u64 %rd102, %rd101;
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ld.const.u32 %r433, [params+184];
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mad.lo.s32 %r434, %r433, %r8, %r7;
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mov.f32 %f1379, 0f00000000;
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cvt.rzi.u32.f32 %r435, %f1379;
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mul.wide.u32 %rd103, %r434, 2;
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add.s64 %rd104, %rd102, %rd103;
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mov.u16 %rs98, 0;
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cvt.u16.u32 %rs99, %r435;
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st.global.v2.u8 [%rd104], {%rs99, %rs98};
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$L__BB0_162:
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and.b32 %r436, %r57, 4;
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setp.eq.s32 %p190, %r436, 0;
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ld.const.u32 %r463, [params+108];
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@%p190 bra $L__BB0_166;
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setp.eq.s32 %p191, %r463, 0;
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ld.const.u64 %rd105, [params+224];
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cvta.to.global.u64 %rd106, %rd105;
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ld.const.u32 %r437, [params+216];
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mad.lo.s32 %r438, %r437, %r8, %r7;
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mul.wide.u32 %rd107, %r438, 8;
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add.s64 %rd28, %rd106, %rd107;
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@%p191 bra $L__BB0_165;
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ld.global.v4.u16 {%rs106, %rs107, %rs108, %rs109}, [%rd28];
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// begin inline asm
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{ cvt.f32.f16 %f1380, %rs106;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1381, %rs107;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1382, %rs108;}
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// end inline asm
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add.f32 %f1383, %f1380, 0f00000000;
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add.f32 %f1384, %f1381, 0f00000000;
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add.f32 %f1385, %f1382, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs105, %f1385;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs104, %f1384;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs103, %f1383;}
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// end inline asm
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mov.u16 %rs110, 0;
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st.global.v4.u16 [%rd28], {%rs103, %rs104, %rs105, %rs110};
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bra.uni $L__BB0_166;
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$L__BB0_5:
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ld.const.u64 %rd37, [params+432];
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cvta.to.global.u64 %rd38, %rd37;
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ld.const.u32 %r73, [params+424];
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mad.lo.s32 %r74, %r73, %r61, %r60;
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mul.wide.u32 %rd39, %r74, 12;
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add.s64 %rd40, %rd38, %rd39;
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ld.global.f32 %f10, [%rd40];
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mul.f32 %f390, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd40+4];
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mul.f32 %f391, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd40+8];
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mul.f32 %f392, %f12, 0f3456BF95;
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abs.f32 %f393, %f1431;
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div.rn.f32 %f394, %f390, %f393;
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abs.f32 %f395, %f1432;
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div.rn.f32 %f396, %f391, %f395;
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abs.f32 %f397, %f1433;
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div.rn.f32 %f398, %f392, %f397;
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abs.f32 %f399, %f394;
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abs.f32 %f400, %f396;
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abs.f32 %f401, %f398;
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mov.f32 %f402, 0f38D1B717;
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max.f32 %f403, %f399, %f402;
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max.f32 %f404, %f400, %f402;
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max.f32 %f405, %f401, %f402;
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fma.rn.f32 %f13, %f1431, %f403, %f10;
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fma.rn.f32 %f14, %f1432, %f404, %f11;
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fma.rn.f32 %f15, %f1433, %f405, %f12;
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ld.const.u64 %rd41, [params+128];
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cvta.to.global.u64 %rd42, %rd41;
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ld.const.u32 %r75, [params+120];
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mad.lo.s32 %r76, %r75, %r61, %r60;
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mul.wide.u32 %rd43, %r76, 4;
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add.s64 %rd44, %rd42, %rd43;
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ld.global.u32 %r454, [%rd44];
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setp.lt.s32 %p18, %r4, 1;
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mov.pred %p17, 0;
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mov.f32 %f1453, 0f00000000;
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mov.u32 %r450, 0;
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mov.f32 %f1454, %f1453;
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mov.f32 %f1455, %f1453;
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mov.f32 %f1456, %f1453;
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mov.f32 %f1457, %f1453;
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mov.f32 %f1458, %f1453;
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mov.f32 %f1459, %f1453;
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mov.f32 %f1460, %f1453;
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mov.f32 %f1461, %f1453;
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mov.f32 %f1462, %f1453;
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mov.f32 %f1463, %f1453;
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mov.f32 %f1464, %f1453;
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mov.f32 %f1465, %f1453;
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mov.f32 %f1466, %f1453;
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mov.f32 %f1467, %f1453;
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mov.f32 %f1468, %f1453;
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mov.pred %p196, %p17;
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@%p18 bra $L__BB0_23;
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ld.const.f32 %f16, [params+620];
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ld.const.u64 %rd45, [params+624];
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cvta.to.global.u64 %rd3, %rd45;
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ld.const.u64 %rd46, [params+640];
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cvta.to.global.u64 %rd47, %rd46;
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ld.const.u32 %r78, [params+632];
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and.b32 %r79, %r61, 255;
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and.b32 %r80, %r60, 255;
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mad.lo.s32 %r81, %r78, %r79, %r80;
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mul.wide.u32 %rd48, %r81, 3;
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add.s64 %rd4, %rd47, %rd48;
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ld.const.f32 %f17, [params+660];
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mul.f32 %f18, %f13, 0f3456BF95;
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mul.f32 %f19, %f14, 0f3456BF95;
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mul.f32 %f20, %f15, 0f3456BF95;
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ld.const.u64 %rd5, [params+96];
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abs.f32 %f549, %f19;
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abs.f32 %f550, %f18;
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max.f32 %f551, %f550, %f549;
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abs.f32 %f552, %f20;
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max.f32 %f553, %f551, %f552;
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$L__BB0_7:
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mul.lo.s32 %r82, %r450, 3;
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mul.wide.s32 %rd49, %r82, 12;
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add.s64 %rd6, %rd3, %rd49;
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ld.global.f32 %f422, [%rd6];
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sub.f32 %f423, %f422, %f10;
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ld.global.f32 %f424, [%rd6+4];
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sub.f32 %f425, %f424, %f11;
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ld.global.f32 %f426, [%rd6+8];
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sub.f32 %f427, %f426, %f12;
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mul.f32 %f428, %f425, %f425;
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fma.rn.f32 %f429, %f423, %f423, %f428;
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fma.rn.f32 %f430, %f427, %f427, %f429;
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sqrt.rn.f32 %f37, %f430;
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rcp.rn.f32 %f431, %f37;
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mul.f32 %f38, %f423, %f431;
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mul.f32 %f39, %f425, %f431;
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mul.f32 %f40, %f427, %f431;
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mul.f32 %f432, %f37, %f37;
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div.rn.f32 %f41, %f16, %f432;
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ld.global.u8 %rs15, [%rd4];
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cvt.rn.f32.u16 %f433, %rs15;
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div.rn.f32 %f434, %f433, 0fC37F0000;
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fma.rn.f32 %f435, %f434, 0f3F333333, 0f3F800000;
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setp.gt.f32 %p20, %f41, %f435;
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setp.ne.s32 %p21, %r5, 0;
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and.pred %p22, %p21, %p20;
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mov.pred %p196, -1;
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@%p22 bra $L__BB0_23;
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mul.f32 %f42, %f37, %f17;
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mov.f32 %f440, 0f40800000;
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abs.f32 %f44, %f42;
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setp.lt.f32 %p23, %f44, 0f00800000;
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mul.f32 %f442, %f44, 0f4B800000;
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selp.f32 %f443, %f442, %f44, %p23;
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selp.f32 %f444, 0fC3170000, 0fC2FE0000, %p23;
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mov.b32 %r83, %f443;
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and.b32 %r84, %r83, 8388607;
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or.b32 %r85, %r84, 1065353216;
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mov.b32 %f445, %r85;
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shr.u32 %r86, %r83, 23;
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cvt.rn.f32.u32 %f446, %r86;
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add.f32 %f447, %f444, %f446;
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setp.gt.f32 %p24, %f445, 0f3FB504F3;
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mul.f32 %f448, %f445, 0f3F000000;
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add.f32 %f449, %f447, 0f3F800000;
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selp.f32 %f450, %f449, %f447, %p24;
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selp.f32 %f451, %f448, %f445, %p24;
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add.f32 %f452, %f451, 0fBF800000;
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add.f32 %f453, %f451, 0f3F800000;
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rcp.approx.ftz.f32 %f454, %f453;
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add.f32 %f455, %f452, %f452;
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mul.f32 %f456, %f455, %f454;
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mul.f32 %f457, %f456, %f456;
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mov.f32 %f458, 0f3C4CAF63;
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mov.f32 %f459, 0f3B18F0FE;
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fma.rn.f32 %f460, %f459, %f457, %f458;
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mov.f32 %f461, 0f3DAAAABD;
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fma.rn.f32 %f462, %f460, %f457, %f461;
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mul.rn.f32 %f463, %f462, %f457;
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mul.rn.f32 %f464, %f463, %f456;
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sub.f32 %f465, %f452, %f456;
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add.f32 %f466, %f465, %f465;
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neg.f32 %f467, %f456;
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fma.rn.f32 %f468, %f467, %f452, %f466;
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mul.rn.f32 %f469, %f454, %f468;
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add.f32 %f470, %f464, %f456;
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sub.f32 %f471, %f456, %f470;
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add.f32 %f472, %f464, %f471;
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add.f32 %f473, %f469, %f472;
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add.f32 %f474, %f470, %f473;
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sub.f32 %f475, %f470, %f474;
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add.f32 %f476, %f473, %f475;
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mov.f32 %f477, 0f3F317200;
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mul.rn.f32 %f478, %f450, %f477;
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mov.f32 %f479, 0f35BFBE8E;
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mul.rn.f32 %f480, %f450, %f479;
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add.f32 %f481, %f478, %f474;
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sub.f32 %f482, %f478, %f481;
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add.f32 %f483, %f474, %f482;
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add.f32 %f484, %f476, %f483;
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add.f32 %f485, %f480, %f484;
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add.f32 %f486, %f481, %f485;
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sub.f32 %f487, %f481, %f486;
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add.f32 %f488, %f485, %f487;
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mul.rn.f32 %f489, %f440, %f486;
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neg.f32 %f490, %f489;
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fma.rn.f32 %f491, %f440, %f486, %f490;
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fma.rn.f32 %f492, %f440, %f488, %f491;
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mov.f32 %f493, 0f00000000;
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fma.rn.f32 %f494, %f493, %f486, %f492;
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add.rn.f32 %f495, %f489, %f494;
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neg.f32 %f496, %f495;
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add.rn.f32 %f497, %f489, %f496;
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add.rn.f32 %f498, %f497, %f494;
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mov.b32 %r87, %f495;
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setp.eq.s32 %p25, %r87, 1118925336;
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add.s32 %r88, %r87, -1;
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mov.b32 %f499, %r88;
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add.f32 %f500, %f498, 0f37000000;
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selp.f32 %f45, %f500, %f498, %p25;
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selp.f32 %f501, %f499, %f495, %p25;
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mov.f32 %f502, 0f3FB8AA3B;
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mul.rn.f32 %f503, %f501, %f502;
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cvt.rzi.f32.f32 %f504, %f503;
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abs.f32 %f505, %f504;
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setp.gt.f32 %p26, %f505, 0f42FC0000;
|
|
mov.b32 %r89, %f504;
|
|
and.b32 %r90, %r89, -2147483648;
|
|
or.b32 %r91, %r90, 1123811328;
|
|
mov.b32 %f506, %r91;
|
|
selp.f32 %f507, %f506, %f504, %p26;
|
|
mov.f32 %f508, 0fBF317218;
|
|
fma.rn.f32 %f509, %f507, %f508, %f501;
|
|
mov.f32 %f510, 0f3102E308;
|
|
fma.rn.f32 %f511, %f507, %f510, %f509;
|
|
mul.f32 %f512, %f511, 0f3FB8AA3B;
|
|
add.f32 %f513, %f507, 0f4B40007F;
|
|
mov.b32 %r92, %f513;
|
|
shl.b32 %r93, %r92, 23;
|
|
mov.b32 %f514, %r93;
|
|
ex2.approx.ftz.f32 %f515, %f512;
|
|
mul.f32 %f46, %f515, %f514;
|
|
setp.eq.f32 %p27, %f46, 0f7F800000;
|
|
mov.f32 %f1450, 0f7F800000;
|
|
@%p27 bra $L__BB0_10;
|
|
|
|
fma.rn.f32 %f1450, %f46, %f45, %f46;
|
|
|
|
$L__BB0_10:
|
|
mov.f32 %f1430, 0f40000000;
|
|
cvt.rzi.f32.f32 %f1429, %f1430;
|
|
add.f32 %f1428, %f1429, %f1429;
|
|
mov.f32 %f1427, 0f40800000;
|
|
sub.f32 %f1426, %f1427, %f1428;
|
|
abs.f32 %f1425, %f1426;
|
|
setp.lt.f32 %p28, %f42, 0f00000000;
|
|
setp.eq.f32 %p29, %f1425, 0f3F800000;
|
|
and.pred %p1, %p28, %p29;
|
|
setp.eq.f32 %p30, %f42, 0f00000000;
|
|
@%p30 bra $L__BB0_14;
|
|
bra.uni $L__BB0_11;
|
|
|
|
$L__BB0_14:
|
|
add.f32 %f520, %f42, %f42;
|
|
selp.f32 %f1452, %f520, 0f00000000, %p29;
|
|
bra.uni $L__BB0_15;
|
|
|
|
$L__BB0_11:
|
|
mov.b32 %r94, %f1450;
|
|
xor.b32 %r95, %r94, -2147483648;
|
|
mov.b32 %f516, %r95;
|
|
selp.f32 %f1452, %f516, %f1450, %p1;
|
|
setp.geu.f32 %p31, %f42, 0f00000000;
|
|
@%p31 bra $L__BB0_15;
|
|
|
|
mov.f32 %f517, 0f40800000;
|
|
cvt.rzi.f32.f32 %f518, %f517;
|
|
setp.eq.f32 %p32, %f518, 0f40800000;
|
|
@%p32 bra $L__BB0_15;
|
|
|
|
mov.f32 %f1452, 0f7FFFFFFF;
|
|
|
|
$L__BB0_15:
|
|
add.f32 %f521, %f44, 0f40800000;
|
|
mov.b32 %r96, %f521;
|
|
setp.lt.s32 %p34, %r96, 2139095040;
|
|
@%p34 bra $L__BB0_20;
|
|
|
|
setp.gtu.f32 %p35, %f44, 0f7F800000;
|
|
@%p35 bra $L__BB0_19;
|
|
bra.uni $L__BB0_17;
|
|
|
|
$L__BB0_19:
|
|
add.f32 %f1452, %f42, 0f40800000;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_17:
|
|
setp.neu.f32 %p36, %f44, 0f7F800000;
|
|
@%p36 bra $L__BB0_20;
|
|
|
|
selp.f32 %f1452, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_20:
|
|
mov.f32 %f522, 0f3F800000;
|
|
sub.f32 %f523, %f522, %f1452;
|
|
setp.eq.f32 %p37, %f42, 0f3F800000;
|
|
selp.f32 %f524, 0f00000000, %f523, %p37;
|
|
cvt.sat.f32.f32 %f525, %f524;
|
|
mul.f32 %f526, %f41, %f525;
|
|
ld.global.f32 %f527, [%rd6+12];
|
|
mul.f32 %f528, %f38, %f527;
|
|
ld.global.f32 %f529, [%rd6+16];
|
|
mul.f32 %f530, %f39, %f529;
|
|
neg.f32 %f531, %f530;
|
|
sub.f32 %f532, %f531, %f528;
|
|
ld.global.f32 %f533, [%rd6+20];
|
|
mul.f32 %f534, %f40, %f533;
|
|
sub.f32 %f535, %f532, %f534;
|
|
cvt.sat.f32.f32 %f536, %f535;
|
|
mul.f32 %f55, %f526, %f536;
|
|
mul.f32 %f537, %f1432, %f39;
|
|
fma.rn.f32 %f538, %f1431, %f38, %f537;
|
|
fma.rn.f32 %f56, %f1433, %f40, %f538;
|
|
setp.leu.f32 %p38, %f55, 0f3727C5AC;
|
|
@%p38 bra $L__BB0_22;
|
|
|
|
cvt.sat.f32.f32 %f548, %f56;
|
|
mov.f32 %f554, 0f38D1B717;
|
|
max.f32 %f545, %f553, %f554;
|
|
sub.f32 %f546, %f37, %f545;
|
|
mov.f32 %f547, 0f00000000;
|
|
mov.u32 %r133, 2;
|
|
mov.u32 %r135, 1;
|
|
mov.u32 %r136, 1065353216;
|
|
mov.u32 %r167, 0;
|
|
// begin inline asm
|
|
call(%r97,%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128),_optix_trace_typed_32,(%r167,%rd5,%f13,%f14,%f15,%f38,%f39,%f40,%f545,%f546,%f547,%r135,%r167,%r135,%r133,%r135,%r135,%r136,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167);
|
|
// end inline asm
|
|
mov.b32 %f555, %r97;
|
|
ld.global.f32 %f556, [%rd6+24];
|
|
mul.f32 %f557, %f556, %f555;
|
|
ld.global.f32 %f558, [%rd6+28];
|
|
mul.f32 %f559, %f558, %f555;
|
|
ld.global.f32 %f560, [%rd6+32];
|
|
mul.f32 %f561, %f560, %f555;
|
|
mul.f32 %f562, %f55, 0f3EA2F983;
|
|
mul.f32 %f563, %f562, %f557;
|
|
mul.f32 %f564, %f562, %f559;
|
|
mul.f32 %f565, %f562, %f561;
|
|
fma.rn.f32 %f1465, %f548, %f563, %f1465;
|
|
fma.rn.f32 %f1466, %f548, %f564, %f1466;
|
|
fma.rn.f32 %f1467, %f548, %f565, %f1467;
|
|
fma.rn.f32 %f1459, %f38, %f563, %f1459;
|
|
fma.rn.f32 %f1460, %f38, %f564, %f1460;
|
|
fma.rn.f32 %f1461, %f38, %f565, %f1461;
|
|
fma.rn.f32 %f1456, %f39, %f563, %f1456;
|
|
fma.rn.f32 %f1457, %f39, %f564, %f1457;
|
|
fma.rn.f32 %f1458, %f39, %f565, %f1458;
|
|
fma.rn.f32 %f1453, %f40, %f563, %f1453;
|
|
fma.rn.f32 %f1454, %f40, %f564, %f1454;
|
|
fma.rn.f32 %f1455, %f40, %f565, %f1455;
|
|
add.f32 %f1462, %f1462, %f563;
|
|
add.f32 %f1463, %f1463, %f564;
|
|
add.f32 %f1464, %f1464, %f565;
|
|
add.f32 %f1468, %f1468, %f555;
|
|
|
|
$L__BB0_22:
|
|
add.s32 %r450, %r450, 1;
|
|
setp.lt.s32 %p40, %r450, %r4;
|
|
mov.pred %p196, %p17;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_23:
|
|
cvt.rn.f32.s32 %f566, %r450;
|
|
mov.f32 %f567, 0f3F800000;
|
|
max.f32 %f568, %f566, %f567;
|
|
rcp.rn.f32 %f569, %f568;
|
|
mul.f32 %f1548, %f1465, %f569;
|
|
mul.f32 %f1549, %f1466, %f569;
|
|
mul.f32 %f1550, %f1467, %f569;
|
|
div.rn.f32 %f1551, %f1468, %f568;
|
|
mul.f32 %f1545, %f1462, %f569;
|
|
mul.f32 %f1546, %f1463, %f569;
|
|
mul.f32 %f1547, %f1464, %f569;
|
|
mul.f32 %f1542, %f1459, %f569;
|
|
mul.f32 %f1543, %f1460, %f569;
|
|
mul.f32 %f1544, %f1461, %f569;
|
|
mul.f32 %f1539, %f1456, %f569;
|
|
mul.f32 %f1540, %f1457, %f569;
|
|
mul.f32 %f1541, %f1458, %f569;
|
|
mul.f32 %f1536, %f1453, %f569;
|
|
mul.f32 %f1537, %f1454, %f569;
|
|
mul.f32 %f1538, %f1455, %f569;
|
|
not.pred %p41, %p196;
|
|
@%p41 bra $L__BB0_54;
|
|
|
|
setp.lt.s32 %p42, %r5, 1;
|
|
mov.f32 %f584, 0f00000000;
|
|
mov.f32 %f1514, %f584;
|
|
mov.f32 %f1513, %f584;
|
|
mov.f32 %f1512, %f584;
|
|
mov.f32 %f1511, %f584;
|
|
mov.f32 %f1510, %f584;
|
|
mov.f32 %f1509, %f584;
|
|
mov.f32 %f1508, %f584;
|
|
mov.f32 %f1507, %f584;
|
|
mov.f32 %f1506, %f584;
|
|
mov.f32 %f1505, %f584;
|
|
mov.f32 %f1504, %f584;
|
|
mov.f32 %f1503, %f584;
|
|
mov.f32 %f1502, %f584;
|
|
mov.f32 %f1501, %f584;
|
|
mov.f32 %f1500, %f584;
|
|
@%p42 bra $L__BB0_53;
|
|
|
|
cvt.rn.f32.s32 %f600, %r6;
|
|
rcp.rn.f32 %f121, %f600;
|
|
mul.f32 %f122, %f13, 0f3456BF95;
|
|
mul.f32 %f123, %f14, 0f3456BF95;
|
|
mul.f32 %f124, %f15, 0f3456BF95;
|
|
mov.u32 %r168, 0;
|
|
ld.const.u64 %rd7, [params+96];
|
|
add.s64 %rd8, %rd1, 24;
|
|
mov.u64 %rd51, __cudart_i2opi_f;
|
|
abs.f32 %f658, %f123;
|
|
abs.f32 %f659, %f122;
|
|
max.f32 %f660, %f659, %f658;
|
|
abs.f32 %f661, %f124;
|
|
max.f32 %f662, %f660, %f661;
|
|
mov.u32 %r451, %r168;
|
|
|
|
$L__BB0_26:
|
|
cvt.rn.f32.s32 %f140, %r451;
|
|
mov.u32 %r453, %r168;
|
|
|
|
$L__BB0_27:
|
|
mad.lo.s32 %r170, %r454, 1664525, 1013904223;
|
|
and.b32 %r171, %r170, 16777215;
|
|
cvt.rn.f32.u32 %f601, %r171;
|
|
fma.rn.f32 %f602, %f601, 0f33800000, %f140;
|
|
mul.f32 %f603, %f121, %f602;
|
|
mad.lo.s32 %r454, %r170, 1664525, 1013904223;
|
|
and.b32 %r172, %r454, 16777215;
|
|
cvt.rn.f32.u32 %f604, %r172;
|
|
cvt.rn.f32.s32 %f605, %r453;
|
|
fma.rn.f32 %f606, %f604, 0f33800000, %f605;
|
|
mul.f32 %f607, %f121, %f606;
|
|
fma.rn.f32 %f608, %f121, %f602, %f603;
|
|
mov.f32 %f609, 0f3F800000;
|
|
sub.f32 %f156, %f609, %f608;
|
|
mul.f32 %f610, %f156, %f156;
|
|
sub.f32 %f611, %f609, %f610;
|
|
mov.f32 %f612, 0f00000000;
|
|
max.f32 %f613, %f612, %f611;
|
|
sqrt.rn.f32 %f157, %f613;
|
|
mul.f32 %f158, %f607, 0f40C90FDB;
|
|
mul.f32 %f614, %f158, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r461, %f614;
|
|
cvt.rn.f32.s32 %f615, %r461;
|
|
mov.f32 %f616, 0fBFC90FDA;
|
|
fma.rn.f32 %f617, %f615, %f616, %f158;
|
|
mov.f32 %f618, 0fB3A22168;
|
|
fma.rn.f32 %f619, %f615, %f618, %f617;
|
|
mov.f32 %f620, 0fA7C234C5;
|
|
fma.rn.f32 %f1518, %f615, %f620, %f619;
|
|
abs.f32 %f160, %f158;
|
|
setp.ltu.f32 %p43, %f160, 0f47CE4780;
|
|
mov.u32 %r458, %r461;
|
|
mov.f32 %f1515, %f1518;
|
|
@%p43 bra $L__BB0_35;
|
|
|
|
setp.eq.f32 %p44, %f160, 0f7F800000;
|
|
@%p44 bra $L__BB0_34;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f623, 0f00000000;
|
|
mul.rn.f32 %f1515, %f158, %f623;
|
|
mov.u32 %r458, 0;
|
|
bra.uni $L__BB0_35;
|
|
|
|
$L__BB0_29:
|
|
mov.b32 %r19, %f158;
|
|
bfe.u32 %r174, %r19, 23, 8;
|
|
add.s32 %r20, %r174, -128;
|
|
shl.b32 %r175, %r19, 8;
|
|
or.b32 %r21, %r175, -2147483648;
|
|
shr.u32 %r22, %r20, 5;
|
|
mov.u64 %rd122, 0;
|
|
mov.u32 %r455, 0;
|
|
mov.u64 %rd120, %rd1;
|
|
mov.u64 %rd121, %rd51;
|
|
|
|
$L__BB0_30:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r176, [%rd121];
|
|
mad.wide.u32 %rd53, %r176, %r21, %rd122;
|
|
shr.u64 %rd122, %rd53, 32;
|
|
st.local.u32 [%rd120], %rd53;
|
|
add.s64 %rd121, %rd121, 4;
|
|
add.s64 %rd120, %rd120, 4;
|
|
add.s32 %r455, %r455, 1;
|
|
setp.ne.s32 %p45, %r455, 6;
|
|
@%p45 bra $L__BB0_30;
|
|
|
|
st.local.u32 [%rd8], %rd122;
|
|
mov.u32 %r177, 4;
|
|
sub.s32 %r25, %r177, %r22;
|
|
mov.u32 %r178, 6;
|
|
sub.s32 %r179, %r178, %r22;
|
|
mul.wide.s32 %rd54, %r179, 4;
|
|
add.s64 %rd55, %rd1, %rd54;
|
|
ld.local.u32 %r456, [%rd55];
|
|
ld.local.u32 %r457, [%rd55+-4];
|
|
and.b32 %r28, %r20, 31;
|
|
setp.eq.s32 %p46, %r28, 0;
|
|
@%p46 bra $L__BB0_33;
|
|
|
|
mov.u32 %r180, 32;
|
|
sub.s32 %r181, %r180, %r28;
|
|
shr.u32 %r182, %r457, %r181;
|
|
shl.b32 %r183, %r456, %r28;
|
|
add.s32 %r456, %r182, %r183;
|
|
mul.wide.s32 %rd56, %r25, 4;
|
|
add.s64 %rd57, %rd1, %rd56;
|
|
ld.local.u32 %r184, [%rd57];
|
|
shr.u32 %r185, %r184, %r181;
|
|
shl.b32 %r186, %r457, %r28;
|
|
add.s32 %r457, %r185, %r186;
|
|
|
|
$L__BB0_33:
|
|
and.b32 %r187, %r19, -2147483648;
|
|
shr.u32 %r188, %r457, 30;
|
|
shl.b32 %r189, %r456, 2;
|
|
or.b32 %r190, %r188, %r189;
|
|
shr.u32 %r191, %r190, 31;
|
|
shr.u32 %r192, %r456, 30;
|
|
add.s32 %r193, %r191, %r192;
|
|
neg.s32 %r194, %r193;
|
|
setp.eq.s32 %p47, %r187, 0;
|
|
selp.b32 %r458, %r193, %r194, %p47;
|
|
setp.ne.s32 %p48, %r191, 0;
|
|
xor.b32 %r195, %r187, -2147483648;
|
|
selp.b32 %r196, %r195, %r187, %p48;
|
|
selp.b32 %r197, -1, 0, %p48;
|
|
xor.b32 %r198, %r190, %r197;
|
|
shl.b32 %r199, %r457, 2;
|
|
xor.b32 %r200, %r199, %r197;
|
|
cvt.u64.u32 %rd58, %r198;
|
|
cvt.u64.u32 %rd59, %r200;
|
|
bfi.b64 %rd60, %rd58, %rd59, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd60;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f621, %fd2;
|
|
setp.eq.s32 %p49, %r196, 0;
|
|
neg.f32 %f622, %f621;
|
|
selp.f32 %f1515, %f621, %f622, %p49;
|
|
|
|
$L__BB0_35:
|
|
add.s32 %r35, %r458, 1;
|
|
and.b32 %r36, %r35, 1;
|
|
setp.eq.s32 %p50, %r36, 0;
|
|
selp.f32 %f164, %f1515, 0f3F800000, %p50;
|
|
mul.rn.f32 %f165, %f1515, %f1515;
|
|
mov.f32 %f1516, 0fB94D4153;
|
|
@%p50 bra $L__BB0_37;
|
|
|
|
mov.f32 %f625, 0fBAB607ED;
|
|
mov.f32 %f626, 0f37CBAC00;
|
|
fma.rn.f32 %f1516, %f626, %f165, %f625;
|
|
|
|
$L__BB0_37:
|
|
selp.f32 %f627, 0f3C0885E4, 0f3D2AAABB, %p50;
|
|
fma.rn.f32 %f628, %f1516, %f165, %f627;
|
|
selp.f32 %f629, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
|
|
fma.rn.f32 %f630, %f628, %f165, %f629;
|
|
mov.f32 %f631, 0f00000000;
|
|
fma.rn.f32 %f632, %f165, %f164, %f631;
|
|
fma.rn.f32 %f1517, %f630, %f632, %f164;
|
|
and.b32 %r202, %r35, 2;
|
|
setp.eq.s32 %p52, %r202, 0;
|
|
@%p52 bra $L__BB0_39;
|
|
|
|
mov.f32 %f634, 0fBF800000;
|
|
fma.rn.f32 %f1517, %f1517, %f634, %f631;
|
|
|
|
$L__BB0_39:
|
|
@%p43 bra $L__BB0_47;
|
|
|
|
setp.eq.f32 %p54, %f160, 0f7F800000;
|
|
@%p54 bra $L__BB0_46;
|
|
bra.uni $L__BB0_41;
|
|
|
|
$L__BB0_46:
|
|
mov.f32 %f637, 0f00000000;
|
|
mul.rn.f32 %f1518, %f158, %f637;
|
|
mov.u32 %r461, 0;
|
|
bra.uni $L__BB0_47;
|
|
|
|
$L__BB0_41:
|
|
mov.b32 %r37, %f158;
|
|
bfe.u32 %r203, %r37, 23, 8;
|
|
add.s32 %r38, %r203, -128;
|
|
shl.b32 %r204, %r37, 8;
|
|
or.b32 %r39, %r204, -2147483648;
|
|
shr.u32 %r40, %r38, 5;
|
|
mov.u64 %rd123, 0;
|
|
mov.u64 %rd124, %rd123;
|
|
|
|
$L__BB0_42:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd63, %rd123, 2;
|
|
mov.u64 %rd64, __cudart_i2opi_f;
|
|
add.s64 %rd65, %rd64, %rd63;
|
|
ld.global.nc.u32 %r205, [%rd65];
|
|
mad.wide.u32 %rd66, %r205, %r39, %rd124;
|
|
shr.u64 %rd124, %rd66, 32;
|
|
add.s64 %rd67, %rd1, %rd63;
|
|
st.local.u32 [%rd67], %rd66;
|
|
cvt.u32.u64 %r206, %rd123;
|
|
add.s32 %r207, %r206, 1;
|
|
cvt.s64.s32 %rd123, %r207;
|
|
setp.ne.s32 %p55, %r207, 6;
|
|
@%p55 bra $L__BB0_42;
|
|
|
|
st.local.u32 [%rd8], %rd124;
|
|
mov.u32 %r208, 4;
|
|
sub.s32 %r41, %r208, %r40;
|
|
mov.u32 %r209, 6;
|
|
sub.s32 %r210, %r209, %r40;
|
|
mul.wide.s32 %rd68, %r210, 4;
|
|
add.s64 %rd69, %rd1, %rd68;
|
|
ld.local.u32 %r459, [%rd69];
|
|
ld.local.u32 %r460, [%rd69+-4];
|
|
and.b32 %r44, %r38, 31;
|
|
setp.eq.s32 %p56, %r44, 0;
|
|
@%p56 bra $L__BB0_45;
|
|
|
|
mov.u32 %r211, 32;
|
|
sub.s32 %r212, %r211, %r44;
|
|
shr.u32 %r213, %r460, %r212;
|
|
shl.b32 %r214, %r459, %r44;
|
|
add.s32 %r459, %r213, %r214;
|
|
mul.wide.s32 %rd70, %r41, 4;
|
|
add.s64 %rd71, %rd1, %rd70;
|
|
ld.local.u32 %r215, [%rd71];
|
|
shr.u32 %r216, %r215, %r212;
|
|
shl.b32 %r217, %r460, %r44;
|
|
add.s32 %r460, %r216, %r217;
|
|
|
|
$L__BB0_45:
|
|
and.b32 %r218, %r37, -2147483648;
|
|
shr.u32 %r219, %r460, 30;
|
|
shl.b32 %r220, %r459, 2;
|
|
or.b32 %r221, %r219, %r220;
|
|
shr.u32 %r222, %r221, 31;
|
|
shr.u32 %r223, %r459, 30;
|
|
add.s32 %r224, %r222, %r223;
|
|
neg.s32 %r225, %r224;
|
|
setp.eq.s32 %p57, %r218, 0;
|
|
selp.b32 %r461, %r224, %r225, %p57;
|
|
setp.ne.s32 %p58, %r222, 0;
|
|
xor.b32 %r226, %r218, -2147483648;
|
|
selp.b32 %r227, %r226, %r218, %p58;
|
|
selp.b32 %r228, -1, 0, %p58;
|
|
xor.b32 %r229, %r221, %r228;
|
|
shl.b32 %r230, %r460, 2;
|
|
xor.b32 %r231, %r230, %r228;
|
|
cvt.u64.u32 %rd72, %r229;
|
|
cvt.u64.u32 %rd73, %r231;
|
|
bfi.b64 %rd74, %rd72, %rd73, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd74;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f635, %fd4;
|
|
setp.eq.s32 %p59, %r227, 0;
|
|
neg.f32 %f636, %f635;
|
|
selp.f32 %f1518, %f635, %f636, %p59;
|
|
|
|
$L__BB0_47:
|
|
mul.f32 %f174, %f157, %f1517;
|
|
and.b32 %r51, %r461, 1;
|
|
setp.eq.s32 %p60, %r51, 0;
|
|
selp.f32 %f175, %f1518, 0f3F800000, %p60;
|
|
mul.rn.f32 %f176, %f1518, %f1518;
|
|
mov.f32 %f1519, 0fB94D4153;
|
|
@%p60 bra $L__BB0_49;
|
|
|
|
mov.f32 %f639, 0fBAB607ED;
|
|
mov.f32 %f640, 0f37CBAC00;
|
|
fma.rn.f32 %f1519, %f640, %f176, %f639;
|
|
|
|
$L__BB0_49:
|
|
selp.f32 %f641, 0f3C0885E4, 0f3D2AAABB, %p60;
|
|
fma.rn.f32 %f642, %f1519, %f176, %f641;
|
|
selp.f32 %f643, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
|
|
fma.rn.f32 %f644, %f642, %f176, %f643;
|
|
mov.f32 %f645, 0f00000000;
|
|
fma.rn.f32 %f646, %f176, %f175, %f645;
|
|
fma.rn.f32 %f1520, %f644, %f646, %f175;
|
|
and.b32 %r233, %r461, 2;
|
|
setp.eq.s32 %p62, %r233, 0;
|
|
@%p62 bra $L__BB0_51;
|
|
|
|
mov.f32 %f648, 0fBF800000;
|
|
fma.rn.f32 %f1520, %f1520, %f648, %f645;
|
|
|
|
$L__BB0_51:
|
|
mov.f32 %f663, 0f38D1B717;
|
|
max.f32 %f655, %f662, %f663;
|
|
mul.f32 %f653, %f157, %f1520;
|
|
mov.f32 %f656, 0f6C4ECB8F;
|
|
mov.u32 %r267, 1;
|
|
mov.u32 %r270, 2;
|
|
mov.u32 %r272, 3;
|
|
mov.u32 %r304, 0;
|
|
// begin inline asm
|
|
call(%r234,%r235,%r236,%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265),_optix_trace_typed_32,(%r304,%rd7,%f13,%f14,%f15,%f174,%f653,%f156,%f655,%f656,%f645,%r267,%r304,%r304,%r270,%r304,%r272,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304);
|
|
// end inline asm
|
|
mov.b32 %f664, %r234;
|
|
mov.b32 %f665, %r235;
|
|
mov.b32 %f666, %r236;
|
|
max.f32 %f667, %f664, %f645;
|
|
max.f32 %f668, %f665, %f645;
|
|
max.f32 %f669, %f666, %f645;
|
|
fma.rn.f32 %f1508, %f174, %f667, %f1508;
|
|
fma.rn.f32 %f1507, %f174, %f668, %f1507;
|
|
fma.rn.f32 %f1506, %f174, %f669, %f1506;
|
|
fma.rn.f32 %f1511, %f653, %f667, %f1511;
|
|
fma.rn.f32 %f1510, %f653, %f668, %f1510;
|
|
fma.rn.f32 %f1509, %f653, %f669, %f1509;
|
|
fma.rn.f32 %f1514, %f156, %f667, %f1514;
|
|
fma.rn.f32 %f1513, %f156, %f668, %f1513;
|
|
fma.rn.f32 %f1512, %f156, %f669, %f1512;
|
|
add.f32 %f1505, %f1505, %f667;
|
|
add.f32 %f1504, %f1504, %f668;
|
|
add.f32 %f1503, %f1503, %f669;
|
|
mul.f32 %f670, %f1432, %f653;
|
|
fma.rn.f32 %f671, %f1431, %f174, %f670;
|
|
fma.rn.f32 %f672, %f1433, %f156, %f671;
|
|
cvt.sat.f32.f32 %f673, %f672;
|
|
fma.rn.f32 %f1502, %f667, %f673, %f1502;
|
|
fma.rn.f32 %f1501, %f668, %f673, %f1501;
|
|
fma.rn.f32 %f1500, %f669, %f673, %f1500;
|
|
add.s32 %r453, %r453, 1;
|
|
setp.lt.s32 %p63, %r453, %r6;
|
|
@%p63 bra $L__BB0_27;
|
|
|
|
add.s32 %r451, %r451, 1;
|
|
setp.lt.s32 %p64, %r451, %r6;
|
|
@%p64 bra $L__BB0_26;
|
|
|
|
$L__BB0_53:
|
|
mul.lo.s32 %r305, %r6, %r6;
|
|
cvt.rn.f32.s32 %f674, %r305;
|
|
rcp.rn.f32 %f675, %f674;
|
|
mul.f32 %f676, %f675, %f1502;
|
|
mul.f32 %f677, %f675, %f1501;
|
|
mul.f32 %f678, %f675, %f1500;
|
|
div.rn.f32 %f1551, %f584, %f674;
|
|
mul.f32 %f1545, %f675, %f1505;
|
|
mul.f32 %f1546, %f675, %f1504;
|
|
mul.f32 %f1547, %f675, %f1503;
|
|
mul.f32 %f1542, %f675, %f1508;
|
|
mul.f32 %f1543, %f675, %f1507;
|
|
mul.f32 %f1544, %f675, %f1506;
|
|
mul.f32 %f1539, %f675, %f1511;
|
|
mul.f32 %f1540, %f675, %f1510;
|
|
mul.f32 %f1541, %f675, %f1509;
|
|
mul.f32 %f1536, %f675, %f1514;
|
|
mul.f32 %f1537, %f675, %f1513;
|
|
mul.f32 %f1538, %f675, %f1512;
|
|
fma.rn.f32 %f1548, %f675, %f1502, %f676;
|
|
fma.rn.f32 %f1549, %f675, %f1501, %f677;
|
|
fma.rn.f32 %f1550, %f675, %f1500, %f678;
|
|
|
|
$L__BB0_54:
|
|
ld.const.u32 %r448, [params+616];
|
|
setp.lt.s32 %p65, %r448, 0;
|
|
selp.f32 %f244, %f1548, %f1551, %p65;
|
|
ld.const.u32 %r54, [params+104];
|
|
and.b32 %r306, %r54, 8;
|
|
setp.eq.s32 %p66, %r306, 0;
|
|
@%p66 bra $L__BB0_68;
|
|
|
|
ld.const.u64 %rd76, [params+192];
|
|
cvta.to.global.u64 %rd19, %rd76;
|
|
ld.const.u32 %r307, [params+184];
|
|
mad.lo.s32 %r308, %r307, %r8, %r7;
|
|
cvt.u64.u32 %rd20, %r308;
|
|
mov.f32 %f681, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f682, %f681;
|
|
add.f32 %f683, %f682, %f682;
|
|
mov.f32 %f684, 0f3EE8BA2E;
|
|
sub.f32 %f685, %f684, %f683;
|
|
abs.f32 %f245, %f685;
|
|
abs.f32 %f246, %f244;
|
|
setp.lt.f32 %p67, %f246, 0f00800000;
|
|
mul.f32 %f686, %f246, 0f4B800000;
|
|
selp.f32 %f687, %f686, %f246, %p67;
|
|
selp.f32 %f688, 0fC3170000, 0fC2FE0000, %p67;
|
|
mov.b32 %r309, %f687;
|
|
and.b32 %r310, %r309, 8388607;
|
|
or.b32 %r311, %r310, 1065353216;
|
|
mov.b32 %f689, %r311;
|
|
shr.u32 %r312, %r309, 23;
|
|
cvt.rn.f32.u32 %f690, %r312;
|
|
add.f32 %f691, %f688, %f690;
|
|
setp.gt.f32 %p68, %f689, 0f3FB504F3;
|
|
mul.f32 %f692, %f689, 0f3F000000;
|
|
add.f32 %f693, %f691, 0f3F800000;
|
|
selp.f32 %f694, %f693, %f691, %p68;
|
|
selp.f32 %f695, %f692, %f689, %p68;
|
|
add.f32 %f696, %f695, 0fBF800000;
|
|
add.f32 %f697, %f695, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f698, %f697;
|
|
add.f32 %f699, %f696, %f696;
|
|
mul.f32 %f700, %f699, %f698;
|
|
mul.f32 %f701, %f700, %f700;
|
|
mov.f32 %f702, 0f3C4CAF63;
|
|
mov.f32 %f703, 0f3B18F0FE;
|
|
fma.rn.f32 %f704, %f703, %f701, %f702;
|
|
mov.f32 %f705, 0f3DAAAABD;
|
|
fma.rn.f32 %f706, %f704, %f701, %f705;
|
|
mul.rn.f32 %f707, %f706, %f701;
|
|
mul.rn.f32 %f708, %f707, %f700;
|
|
sub.f32 %f709, %f696, %f700;
|
|
add.f32 %f710, %f709, %f709;
|
|
neg.f32 %f711, %f700;
|
|
fma.rn.f32 %f712, %f711, %f696, %f710;
|
|
mul.rn.f32 %f713, %f698, %f712;
|
|
add.f32 %f714, %f708, %f700;
|
|
sub.f32 %f715, %f700, %f714;
|
|
add.f32 %f716, %f708, %f715;
|
|
add.f32 %f717, %f713, %f716;
|
|
add.f32 %f718, %f714, %f717;
|
|
sub.f32 %f719, %f714, %f718;
|
|
add.f32 %f720, %f717, %f719;
|
|
mov.f32 %f721, 0f3F317200;
|
|
mul.rn.f32 %f722, %f694, %f721;
|
|
mov.f32 %f723, 0f35BFBE8E;
|
|
mul.rn.f32 %f724, %f694, %f723;
|
|
add.f32 %f725, %f722, %f718;
|
|
sub.f32 %f726, %f722, %f725;
|
|
add.f32 %f727, %f718, %f726;
|
|
add.f32 %f728, %f720, %f727;
|
|
add.f32 %f729, %f724, %f728;
|
|
add.f32 %f730, %f725, %f729;
|
|
sub.f32 %f731, %f725, %f730;
|
|
add.f32 %f732, %f729, %f731;
|
|
mul.rn.f32 %f733, %f684, %f730;
|
|
neg.f32 %f734, %f733;
|
|
fma.rn.f32 %f735, %f684, %f730, %f734;
|
|
fma.rn.f32 %f736, %f684, %f732, %f735;
|
|
mov.f32 %f737, 0f00000000;
|
|
fma.rn.f32 %f738, %f737, %f730, %f736;
|
|
add.rn.f32 %f739, %f733, %f738;
|
|
neg.f32 %f740, %f739;
|
|
add.rn.f32 %f741, %f733, %f740;
|
|
add.rn.f32 %f742, %f741, %f738;
|
|
mov.b32 %r313, %f739;
|
|
setp.eq.s32 %p69, %r313, 1118925336;
|
|
add.s32 %r314, %r313, -1;
|
|
mov.b32 %f743, %r314;
|
|
add.f32 %f744, %f742, 0f37000000;
|
|
selp.f32 %f247, %f744, %f742, %p69;
|
|
selp.f32 %f745, %f743, %f739, %p69;
|
|
mov.f32 %f746, 0f3FB8AA3B;
|
|
mul.rn.f32 %f747, %f745, %f746;
|
|
cvt.rzi.f32.f32 %f748, %f747;
|
|
abs.f32 %f749, %f748;
|
|
setp.gt.f32 %p70, %f749, 0f42FC0000;
|
|
mov.b32 %r315, %f748;
|
|
and.b32 %r316, %r315, -2147483648;
|
|
or.b32 %r317, %r316, 1123811328;
|
|
mov.b32 %f750, %r317;
|
|
selp.f32 %f751, %f750, %f748, %p70;
|
|
mov.f32 %f752, 0fBF317218;
|
|
fma.rn.f32 %f753, %f751, %f752, %f745;
|
|
mov.f32 %f754, 0f3102E308;
|
|
fma.rn.f32 %f755, %f751, %f754, %f753;
|
|
mul.f32 %f756, %f755, 0f3FB8AA3B;
|
|
add.f32 %f757, %f751, 0f4B40007F;
|
|
mov.b32 %r318, %f757;
|
|
shl.b32 %r319, %r318, 23;
|
|
mov.b32 %f758, %r319;
|
|
ex2.approx.ftz.f32 %f759, %f756;
|
|
mul.f32 %f248, %f759, %f758;
|
|
setp.eq.f32 %p71, %f248, 0f7F800000;
|
|
mov.f32 %f1552, 0f7F800000;
|
|
@%p71 bra $L__BB0_57;
|
|
|
|
fma.rn.f32 %f1552, %f248, %f247, %f248;
|
|
|
|
$L__BB0_57:
|
|
setp.lt.f32 %p72, %f244, 0f00000000;
|
|
setp.eq.f32 %p73, %f245, 0f3F800000;
|
|
and.pred %p3, %p72, %p73;
|
|
setp.eq.f32 %p74, %f244, 0f00000000;
|
|
@%p74 bra $L__BB0_61;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_61:
|
|
add.f32 %f764, %f244, %f244;
|
|
selp.f32 %f1554, %f764, 0f00000000, %p73;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_165:
|
|
mov.f32 %f1388, 0f00000000;
|
|
mov.u32 %r463, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1388;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1388;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f1388;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs114, 0;
|
|
st.global.v4.u16 [%rd28], {%rs111, %rs112, %rs113, %rs114};
|
|
|
|
$L__BB0_166:
|
|
ld.const.u64 %rd108, [params+256];
|
|
cvta.to.global.u64 %rd109, %rd108;
|
|
ld.const.u32 %r440, [params+248];
|
|
mad.lo.s32 %r441, %r440, %r8, %r7;
|
|
mul.wide.u32 %rd110, %r441, 8;
|
|
add.s64 %rd29, %rd109, %rd110;
|
|
setp.eq.s32 %p192, %r463, 0;
|
|
@%p192 bra $L__BB0_168;
|
|
|
|
ld.global.v4.u16 {%rs121, %rs122, %rs123, %rs124}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1389, %rs121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1390, %rs122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1391, %rs123;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1392, %f1389, 0f00000000;
|
|
add.f32 %f1393, %f1390, 0f00000000;
|
|
add.f32 %f1394, %f1391, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1394;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1393;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1392;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs125, 0;
|
|
st.global.v4.u16 [%rd29], {%rs118, %rs119, %rs120, %rs125};
|
|
bra.uni $L__BB0_169;
|
|
|
|
$L__BB0_168:
|
|
mov.f32 %f1397, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1397;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1397;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1397;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs129, 0;
|
|
st.global.v4.u16 [%rd29], {%rs126, %rs127, %rs128, %rs129};
|
|
|
|
$L__BB0_169:
|
|
ld.const.u64 %rd111, [params+272];
|
|
cvta.to.global.u64 %rd112, %rd111;
|
|
ld.const.u32 %r442, [params+264];
|
|
mad.lo.s32 %r443, %r442, %r8, %r7;
|
|
mul.wide.u32 %rd113, %r443, 8;
|
|
add.s64 %rd30, %rd112, %rd113;
|
|
@%p192 bra $L__BB0_171;
|
|
|
|
ld.global.v4.u16 {%rs136, %rs137, %rs138, %rs139}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1398, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1399, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1400, %rs138;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1401, %f1398, 0f00000000;
|
|
add.f32 %f1402, %f1399, 0f00000000;
|
|
add.f32 %f1403, %f1400, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1403;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1402;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1401;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs140, 0;
|
|
st.global.v4.u16 [%rd30], {%rs133, %rs134, %rs135, %rs140};
|
|
bra.uni $L__BB0_172;
|
|
|
|
$L__BB0_171:
|
|
mov.f32 %f1406, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1406;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1406;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1406;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs144, 0;
|
|
st.global.v4.u16 [%rd30], {%rs141, %rs142, %rs143, %rs144};
|
|
|
|
$L__BB0_172:
|
|
ld.const.u64 %rd114, [params+288];
|
|
cvta.to.global.u64 %rd115, %rd114;
|
|
ld.const.u32 %r444, [params+280];
|
|
mad.lo.s32 %r445, %r444, %r8, %r7;
|
|
mul.wide.u32 %rd116, %r445, 8;
|
|
add.s64 %rd31, %rd115, %rd116;
|
|
@%p192 bra $L__BB0_174;
|
|
|
|
ld.global.v4.u16 {%rs151, %rs152, %rs153, %rs154}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1407, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1408, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1409, %rs153;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1410, %f1407, 0f00000000;
|
|
add.f32 %f1411, %f1408, 0f00000000;
|
|
add.f32 %f1412, %f1409, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1412;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1411;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1410;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs155, 0;
|
|
st.global.v4.u16 [%rd31], {%rs148, %rs149, %rs150, %rs155};
|
|
bra.uni $L__BB0_175;
|
|
|
|
$L__BB0_174:
|
|
mov.f32 %f1415, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1415;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1415;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1415;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs159, 0;
|
|
st.global.v4.u16 [%rd31], {%rs156, %rs157, %rs158, %rs159};
|
|
|
|
$L__BB0_175:
|
|
ld.const.u64 %rd117, [params+304];
|
|
cvta.to.global.u64 %rd118, %rd117;
|
|
ld.const.u32 %r446, [params+296];
|
|
mad.lo.s32 %r447, %r446, %r8, %r7;
|
|
mul.wide.u32 %rd119, %r447, 8;
|
|
add.s64 %rd32, %rd118, %rd119;
|
|
@%p192 bra $L__BB0_177;
|
|
|
|
ld.global.v4.u16 {%rs166, %rs167, %rs168, %rs169}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1416, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1417, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1418, %rs168;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1419, %f1416, 0f00000000;
|
|
add.f32 %f1420, %f1417, 0f00000000;
|
|
add.f32 %f1421, %f1418, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1421;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1420;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1419;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs170, 0;
|
|
st.global.v4.u16 [%rd32], {%rs163, %rs164, %rs165, %rs170};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_177:
|
|
mov.f32 %f1424, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1424;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1424;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1424;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs174, 0;
|
|
st.global.v4.u16 [%rd32], {%rs171, %rs172, %rs173, %rs174};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_58:
|
|
mov.b32 %r320, %f1552;
|
|
xor.b32 %r321, %r320, -2147483648;
|
|
mov.b32 %f760, %r321;
|
|
selp.f32 %f1554, %f760, %f1552, %p3;
|
|
setp.geu.f32 %p75, %f244, 0f00000000;
|
|
@%p75 bra $L__BB0_62;
|
|
|
|
mov.f32 %f761, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f762, %f761;
|
|
setp.eq.f32 %p76, %f762, 0f3EE8BA2E;
|
|
@%p76 bra $L__BB0_62;
|
|
|
|
mov.f32 %f1554, 0f7FFFFFFF;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f765, %f246, 0f3EE8BA2E;
|
|
mov.b32 %r322, %f765;
|
|
setp.lt.s32 %p78, %r322, 2139095040;
|
|
@%p78 bra $L__BB0_67;
|
|
|
|
setp.gtu.f32 %p79, %f246, 0f7F800000;
|
|
@%p79 bra $L__BB0_66;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f1554, %f244, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_64:
|
|
setp.neu.f32 %p80, %f246, 0f7F800000;
|
|
@%p80 bra $L__BB0_67;
|
|
|
|
selp.f32 %f1554, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_67:
|
|
mul.f32 %f766, %f1554, 0f437F0000;
|
|
setp.eq.f32 %p81, %f244, 0f3F800000;
|
|
selp.f32 %f767, 0f437F0000, %f766, %p81;
|
|
cvt.rzi.u32.f32 %r323, %f767;
|
|
shl.b64 %rd77, %rd20, 1;
|
|
add.s64 %rd78, %rd19, %rd77;
|
|
cvt.u16.u32 %rs16, %r323;
|
|
mov.u16 %rs17, 255;
|
|
st.global.v2.u8 [%rd78], {%rs16, %rs17};
|
|
|
|
$L__BB0_68:
|
|
ld.const.v2.f32 {%f768, %f769}, [params+648];
|
|
mul.f32 %f259, %f1548, %f768;
|
|
mul.f32 %f260, %f1549, %f769;
|
|
ld.const.f32 %f261, [params+656];
|
|
mul.f32 %f262, %f1550, %f261;
|
|
and.b32 %r324, %r54, 1;
|
|
setp.eq.b32 %p82, %r324, 1;
|
|
mov.pred %p83, 0;
|
|
xor.pred %p84, %p82, %p83;
|
|
not.pred %p85, %p84;
|
|
@%p85 bra $L__BB0_142;
|
|
|
|
mov.f32 %f771, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f772, %f771;
|
|
add.f32 %f773, %f772, %f772;
|
|
mov.f32 %f774, 0f3EE66666;
|
|
sub.f32 %f775, %f774, %f773;
|
|
abs.f32 %f263, %f775;
|
|
abs.f32 %f264, %f259;
|
|
setp.lt.f32 %p86, %f264, 0f00800000;
|
|
mul.f32 %f776, %f264, 0f4B800000;
|
|
selp.f32 %f777, %f776, %f264, %p86;
|
|
selp.f32 %f778, 0fC3170000, 0fC2FE0000, %p86;
|
|
mov.b32 %r325, %f777;
|
|
and.b32 %r326, %r325, 8388607;
|
|
or.b32 %r327, %r326, 1065353216;
|
|
mov.b32 %f779, %r327;
|
|
shr.u32 %r328, %r325, 23;
|
|
cvt.rn.f32.u32 %f780, %r328;
|
|
add.f32 %f781, %f778, %f780;
|
|
setp.gt.f32 %p87, %f779, 0f3FB504F3;
|
|
mul.f32 %f782, %f779, 0f3F000000;
|
|
add.f32 %f783, %f781, 0f3F800000;
|
|
selp.f32 %f784, %f783, %f781, %p87;
|
|
selp.f32 %f785, %f782, %f779, %p87;
|
|
add.f32 %f786, %f785, 0fBF800000;
|
|
add.f32 %f787, %f785, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f788, %f787;
|
|
add.f32 %f789, %f786, %f786;
|
|
mul.f32 %f790, %f789, %f788;
|
|
mul.f32 %f791, %f790, %f790;
|
|
mov.f32 %f792, 0f3C4CAF63;
|
|
mov.f32 %f793, 0f3B18F0FE;
|
|
fma.rn.f32 %f794, %f793, %f791, %f792;
|
|
mov.f32 %f795, 0f3DAAAABD;
|
|
fma.rn.f32 %f796, %f794, %f791, %f795;
|
|
mul.rn.f32 %f797, %f796, %f791;
|
|
mul.rn.f32 %f798, %f797, %f790;
|
|
sub.f32 %f799, %f786, %f790;
|
|
add.f32 %f800, %f799, %f799;
|
|
neg.f32 %f801, %f790;
|
|
fma.rn.f32 %f802, %f801, %f786, %f800;
|
|
mul.rn.f32 %f803, %f788, %f802;
|
|
add.f32 %f804, %f798, %f790;
|
|
sub.f32 %f805, %f790, %f804;
|
|
add.f32 %f806, %f798, %f805;
|
|
add.f32 %f807, %f803, %f806;
|
|
add.f32 %f808, %f804, %f807;
|
|
sub.f32 %f809, %f804, %f808;
|
|
add.f32 %f810, %f807, %f809;
|
|
mov.f32 %f811, 0f3F317200;
|
|
mul.rn.f32 %f812, %f784, %f811;
|
|
mov.f32 %f813, 0f35BFBE8E;
|
|
mul.rn.f32 %f814, %f784, %f813;
|
|
add.f32 %f815, %f812, %f808;
|
|
sub.f32 %f816, %f812, %f815;
|
|
add.f32 %f817, %f808, %f816;
|
|
add.f32 %f818, %f810, %f817;
|
|
add.f32 %f819, %f814, %f818;
|
|
add.f32 %f820, %f815, %f819;
|
|
sub.f32 %f821, %f815, %f820;
|
|
add.f32 %f822, %f819, %f821;
|
|
mul.rn.f32 %f823, %f774, %f820;
|
|
neg.f32 %f824, %f823;
|
|
fma.rn.f32 %f825, %f774, %f820, %f824;
|
|
fma.rn.f32 %f826, %f774, %f822, %f825;
|
|
mov.f32 %f827, 0f00000000;
|
|
fma.rn.f32 %f828, %f827, %f820, %f826;
|
|
add.rn.f32 %f829, %f823, %f828;
|
|
neg.f32 %f830, %f829;
|
|
add.rn.f32 %f831, %f823, %f830;
|
|
add.rn.f32 %f832, %f831, %f828;
|
|
mov.b32 %r329, %f829;
|
|
setp.eq.s32 %p88, %r329, 1118925336;
|
|
add.s32 %r330, %r329, -1;
|
|
mov.b32 %f833, %r330;
|
|
add.f32 %f834, %f832, 0f37000000;
|
|
selp.f32 %f265, %f834, %f832, %p88;
|
|
selp.f32 %f835, %f833, %f829, %p88;
|
|
mov.f32 %f836, 0f3FB8AA3B;
|
|
mul.rn.f32 %f837, %f835, %f836;
|
|
cvt.rzi.f32.f32 %f838, %f837;
|
|
abs.f32 %f839, %f838;
|
|
setp.gt.f32 %p89, %f839, 0f42FC0000;
|
|
mov.b32 %r331, %f838;
|
|
and.b32 %r332, %r331, -2147483648;
|
|
or.b32 %r333, %r332, 1123811328;
|
|
mov.b32 %f840, %r333;
|
|
selp.f32 %f841, %f840, %f838, %p89;
|
|
mov.f32 %f842, 0fBF317218;
|
|
fma.rn.f32 %f843, %f841, %f842, %f835;
|
|
mov.f32 %f844, 0f3102E308;
|
|
fma.rn.f32 %f845, %f841, %f844, %f843;
|
|
mul.f32 %f846, %f845, 0f3FB8AA3B;
|
|
add.f32 %f847, %f841, 0f4B40007F;
|
|
mov.b32 %r334, %f847;
|
|
shl.b32 %r335, %r334, 23;
|
|
mov.b32 %f848, %r335;
|
|
ex2.approx.ftz.f32 %f849, %f846;
|
|
mul.f32 %f266, %f849, %f848;
|
|
setp.eq.f32 %p90, %f266, 0f7F800000;
|
|
mov.f32 %f1555, 0f7F800000;
|
|
@%p90 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f1555, %f266, %f265, %f266;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p91, %f259, 0f00000000;
|
|
setp.eq.f32 %p92, %f263, 0f3F800000;
|
|
and.pred %p4, %p91, %p92;
|
|
setp.eq.f32 %p93, %f259, 0f00000000;
|
|
@%p93 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f854, %f259, %f259;
|
|
selp.f32 %f1557, %f854, 0f00000000, %p92;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r336, %f1555;
|
|
xor.b32 %r337, %r336, -2147483648;
|
|
mov.b32 %f850, %r337;
|
|
selp.f32 %f1557, %f850, %f1555, %p4;
|
|
setp.geu.f32 %p94, %f259, 0f00000000;
|
|
@%p94 bra $L__BB0_76;
|
|
|
|
mov.f32 %f851, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f852, %f851;
|
|
setp.eq.f32 %p95, %f852, 0f3EE66666;
|
|
@%p95 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1557, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f855, %f264, 0f3EE66666;
|
|
mov.b32 %r338, %f855;
|
|
setp.lt.s32 %p97, %r338, 2139095040;
|
|
@%p97 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p98, %f264, 0f7F800000;
|
|
@%p98 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1557, %f259, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p99, %f264, 0f7F800000;
|
|
@%p99 bra $L__BB0_81;
|
|
|
|
selp.f32 %f1557, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p100, %f259, 0f3F800000;
|
|
selp.f32 %f275, 0f3F800000, %f1557, %p100;
|
|
abs.f32 %f276, %f260;
|
|
setp.lt.f32 %p101, %f276, 0f00800000;
|
|
mul.f32 %f857, %f276, 0f4B800000;
|
|
selp.f32 %f858, %f857, %f276, %p101;
|
|
selp.f32 %f859, 0fC3170000, 0fC2FE0000, %p101;
|
|
mov.b32 %r339, %f858;
|
|
and.b32 %r340, %r339, 8388607;
|
|
or.b32 %r341, %r340, 1065353216;
|
|
mov.b32 %f860, %r341;
|
|
shr.u32 %r342, %r339, 23;
|
|
cvt.rn.f32.u32 %f861, %r342;
|
|
add.f32 %f862, %f859, %f861;
|
|
setp.gt.f32 %p102, %f860, 0f3FB504F3;
|
|
mul.f32 %f863, %f860, 0f3F000000;
|
|
add.f32 %f864, %f862, 0f3F800000;
|
|
selp.f32 %f865, %f864, %f862, %p102;
|
|
selp.f32 %f866, %f863, %f860, %p102;
|
|
add.f32 %f867, %f866, 0fBF800000;
|
|
add.f32 %f868, %f866, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f869, %f868;
|
|
add.f32 %f870, %f867, %f867;
|
|
mul.f32 %f871, %f870, %f869;
|
|
mul.f32 %f872, %f871, %f871;
|
|
mov.f32 %f873, 0f3C4CAF63;
|
|
mov.f32 %f874, 0f3B18F0FE;
|
|
fma.rn.f32 %f875, %f874, %f872, %f873;
|
|
mov.f32 %f876, 0f3DAAAABD;
|
|
fma.rn.f32 %f877, %f875, %f872, %f876;
|
|
mul.rn.f32 %f878, %f877, %f872;
|
|
mul.rn.f32 %f879, %f878, %f871;
|
|
sub.f32 %f880, %f867, %f871;
|
|
add.f32 %f881, %f880, %f880;
|
|
neg.f32 %f882, %f871;
|
|
fma.rn.f32 %f883, %f882, %f867, %f881;
|
|
mul.rn.f32 %f884, %f869, %f883;
|
|
add.f32 %f885, %f879, %f871;
|
|
sub.f32 %f886, %f871, %f885;
|
|
add.f32 %f887, %f879, %f886;
|
|
add.f32 %f888, %f884, %f887;
|
|
add.f32 %f889, %f885, %f888;
|
|
sub.f32 %f890, %f885, %f889;
|
|
add.f32 %f891, %f888, %f890;
|
|
mov.f32 %f892, 0f3F317200;
|
|
mul.rn.f32 %f893, %f865, %f892;
|
|
mov.f32 %f894, 0f35BFBE8E;
|
|
mul.rn.f32 %f895, %f865, %f894;
|
|
add.f32 %f896, %f893, %f889;
|
|
sub.f32 %f897, %f893, %f896;
|
|
add.f32 %f898, %f889, %f897;
|
|
add.f32 %f899, %f891, %f898;
|
|
add.f32 %f900, %f895, %f899;
|
|
add.f32 %f901, %f896, %f900;
|
|
sub.f32 %f902, %f896, %f901;
|
|
add.f32 %f903, %f900, %f902;
|
|
mov.f32 %f904, 0f3EE66666;
|
|
mul.rn.f32 %f905, %f904, %f901;
|
|
neg.f32 %f906, %f905;
|
|
fma.rn.f32 %f907, %f904, %f901, %f906;
|
|
fma.rn.f32 %f908, %f904, %f903, %f907;
|
|
mov.f32 %f909, 0f00000000;
|
|
fma.rn.f32 %f910, %f909, %f901, %f908;
|
|
add.rn.f32 %f911, %f905, %f910;
|
|
neg.f32 %f912, %f911;
|
|
add.rn.f32 %f913, %f905, %f912;
|
|
add.rn.f32 %f914, %f913, %f910;
|
|
mov.b32 %r343, %f911;
|
|
setp.eq.s32 %p103, %r343, 1118925336;
|
|
add.s32 %r344, %r343, -1;
|
|
mov.b32 %f915, %r344;
|
|
add.f32 %f916, %f914, 0f37000000;
|
|
selp.f32 %f277, %f916, %f914, %p103;
|
|
selp.f32 %f917, %f915, %f911, %p103;
|
|
mov.f32 %f918, 0f3FB8AA3B;
|
|
mul.rn.f32 %f919, %f917, %f918;
|
|
cvt.rzi.f32.f32 %f920, %f919;
|
|
abs.f32 %f921, %f920;
|
|
setp.gt.f32 %p104, %f921, 0f42FC0000;
|
|
mov.b32 %r345, %f920;
|
|
and.b32 %r346, %r345, -2147483648;
|
|
or.b32 %r347, %r346, 1123811328;
|
|
mov.b32 %f922, %r347;
|
|
selp.f32 %f923, %f922, %f920, %p104;
|
|
mov.f32 %f924, 0fBF317218;
|
|
fma.rn.f32 %f925, %f923, %f924, %f917;
|
|
mov.f32 %f926, 0f3102E308;
|
|
fma.rn.f32 %f927, %f923, %f926, %f925;
|
|
mul.f32 %f928, %f927, 0f3FB8AA3B;
|
|
add.f32 %f929, %f923, 0f4B40007F;
|
|
mov.b32 %r348, %f929;
|
|
shl.b32 %r349, %r348, 23;
|
|
mov.b32 %f930, %r349;
|
|
ex2.approx.ftz.f32 %f931, %f928;
|
|
mul.f32 %f278, %f931, %f930;
|
|
setp.eq.f32 %p105, %f278, 0f7F800000;
|
|
mov.f32 %f1558, 0f7F800000;
|
|
@%p105 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f1558, %f278, %f277, %f278;
|
|
|
|
$L__BB0_83:
|
|
setp.lt.f32 %p106, %f260, 0f00000000;
|
|
and.pred %p5, %p106, %p92;
|
|
setp.eq.f32 %p108, %f260, 0f00000000;
|
|
@%p108 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
add.f32 %f936, %f260, %f260;
|
|
selp.f32 %f1560, %f936, 0f00000000, %p92;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.b32 %r350, %f1558;
|
|
xor.b32 %r351, %r350, -2147483648;
|
|
mov.b32 %f932, %r351;
|
|
selp.f32 %f1560, %f932, %f1558, %p5;
|
|
setp.geu.f32 %p109, %f260, 0f00000000;
|
|
@%p109 bra $L__BB0_88;
|
|
|
|
mov.f32 %f933, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f934, %f933;
|
|
setp.eq.f32 %p110, %f934, 0f3EE66666;
|
|
@%p110 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1560, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
add.f32 %f937, %f276, 0f3EE66666;
|
|
mov.b32 %r352, %f937;
|
|
setp.lt.s32 %p112, %r352, 2139095040;
|
|
@%p112 bra $L__BB0_93;
|
|
|
|
setp.gtu.f32 %p113, %f276, 0f7F800000;
|
|
@%p113 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f1560, %f260, 0f3EE66666;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
setp.neu.f32 %p114, %f276, 0f7F800000;
|
|
@%p114 bra $L__BB0_93;
|
|
|
|
selp.f32 %f1560, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_93:
|
|
setp.eq.f32 %p115, %f260, 0f3F800000;
|
|
selp.f32 %f287, 0f3F800000, %f1560, %p115;
|
|
abs.f32 %f288, %f262;
|
|
setp.lt.f32 %p116, %f288, 0f00800000;
|
|
mul.f32 %f939, %f288, 0f4B800000;
|
|
selp.f32 %f940, %f939, %f288, %p116;
|
|
selp.f32 %f941, 0fC3170000, 0fC2FE0000, %p116;
|
|
mov.b32 %r353, %f940;
|
|
and.b32 %r354, %r353, 8388607;
|
|
or.b32 %r355, %r354, 1065353216;
|
|
mov.b32 %f942, %r355;
|
|
shr.u32 %r356, %r353, 23;
|
|
cvt.rn.f32.u32 %f943, %r356;
|
|
add.f32 %f944, %f941, %f943;
|
|
setp.gt.f32 %p117, %f942, 0f3FB504F3;
|
|
mul.f32 %f945, %f942, 0f3F000000;
|
|
add.f32 %f946, %f944, 0f3F800000;
|
|
selp.f32 %f947, %f946, %f944, %p117;
|
|
selp.f32 %f948, %f945, %f942, %p117;
|
|
add.f32 %f949, %f948, 0fBF800000;
|
|
add.f32 %f950, %f948, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f951, %f950;
|
|
add.f32 %f952, %f949, %f949;
|
|
mul.f32 %f953, %f952, %f951;
|
|
mul.f32 %f954, %f953, %f953;
|
|
mov.f32 %f955, 0f3C4CAF63;
|
|
mov.f32 %f956, 0f3B18F0FE;
|
|
fma.rn.f32 %f957, %f956, %f954, %f955;
|
|
mov.f32 %f958, 0f3DAAAABD;
|
|
fma.rn.f32 %f959, %f957, %f954, %f958;
|
|
mul.rn.f32 %f960, %f959, %f954;
|
|
mul.rn.f32 %f961, %f960, %f953;
|
|
sub.f32 %f962, %f949, %f953;
|
|
add.f32 %f963, %f962, %f962;
|
|
neg.f32 %f964, %f953;
|
|
fma.rn.f32 %f965, %f964, %f949, %f963;
|
|
mul.rn.f32 %f966, %f951, %f965;
|
|
add.f32 %f967, %f961, %f953;
|
|
sub.f32 %f968, %f953, %f967;
|
|
add.f32 %f969, %f961, %f968;
|
|
add.f32 %f970, %f966, %f969;
|
|
add.f32 %f971, %f967, %f970;
|
|
sub.f32 %f972, %f967, %f971;
|
|
add.f32 %f973, %f970, %f972;
|
|
mov.f32 %f974, 0f3F317200;
|
|
mul.rn.f32 %f975, %f947, %f974;
|
|
mov.f32 %f976, 0f35BFBE8E;
|
|
mul.rn.f32 %f977, %f947, %f976;
|
|
add.f32 %f978, %f975, %f971;
|
|
sub.f32 %f979, %f975, %f978;
|
|
add.f32 %f980, %f971, %f979;
|
|
add.f32 %f981, %f973, %f980;
|
|
add.f32 %f982, %f977, %f981;
|
|
add.f32 %f983, %f978, %f982;
|
|
sub.f32 %f984, %f978, %f983;
|
|
add.f32 %f985, %f982, %f984;
|
|
mov.f32 %f986, 0f3EE66666;
|
|
mul.rn.f32 %f987, %f986, %f983;
|
|
neg.f32 %f988, %f987;
|
|
fma.rn.f32 %f989, %f986, %f983, %f988;
|
|
fma.rn.f32 %f990, %f986, %f985, %f989;
|
|
mov.f32 %f991, 0f00000000;
|
|
fma.rn.f32 %f992, %f991, %f983, %f990;
|
|
add.rn.f32 %f993, %f987, %f992;
|
|
neg.f32 %f994, %f993;
|
|
add.rn.f32 %f995, %f987, %f994;
|
|
add.rn.f32 %f996, %f995, %f992;
|
|
mov.b32 %r357, %f993;
|
|
setp.eq.s32 %p118, %r357, 1118925336;
|
|
add.s32 %r358, %r357, -1;
|
|
mov.b32 %f997, %r358;
|
|
add.f32 %f998, %f996, 0f37000000;
|
|
selp.f32 %f289, %f998, %f996, %p118;
|
|
selp.f32 %f999, %f997, %f993, %p118;
|
|
mov.f32 %f1000, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1001, %f999, %f1000;
|
|
cvt.rzi.f32.f32 %f1002, %f1001;
|
|
abs.f32 %f1003, %f1002;
|
|
setp.gt.f32 %p119, %f1003, 0f42FC0000;
|
|
mov.b32 %r359, %f1002;
|
|
and.b32 %r360, %r359, -2147483648;
|
|
or.b32 %r361, %r360, 1123811328;
|
|
mov.b32 %f1004, %r361;
|
|
selp.f32 %f1005, %f1004, %f1002, %p119;
|
|
mov.f32 %f1006, 0fBF317218;
|
|
fma.rn.f32 %f1007, %f1005, %f1006, %f999;
|
|
mov.f32 %f1008, 0f3102E308;
|
|
fma.rn.f32 %f1009, %f1005, %f1008, %f1007;
|
|
mul.f32 %f1010, %f1009, 0f3FB8AA3B;
|
|
add.f32 %f1011, %f1005, 0f4B40007F;
|
|
mov.b32 %r362, %f1011;
|
|
shl.b32 %r363, %r362, 23;
|
|
mov.b32 %f1012, %r363;
|
|
ex2.approx.ftz.f32 %f1013, %f1010;
|
|
mul.f32 %f290, %f1013, %f1012;
|
|
setp.eq.f32 %p120, %f290, 0f7F800000;
|
|
mov.f32 %f1561, 0f7F800000;
|
|
@%p120 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f1561, %f290, %f289, %f290;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p121, %f262, 0f00000000;
|
|
and.pred %p6, %p121, %p92;
|
|
setp.eq.f32 %p123, %f262, 0f00000000;
|
|
@%p123 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f1018, %f262, %f262;
|
|
selp.f32 %f1563, %f1018, 0f00000000, %p92;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r364, %f1561;
|
|
xor.b32 %r365, %r364, -2147483648;
|
|
mov.b32 %f1014, %r365;
|
|
selp.f32 %f1563, %f1014, %f1561, %p6;
|
|
setp.geu.f32 %p124, %f262, 0f00000000;
|
|
@%p124 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1015, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1016, %f1015;
|
|
setp.eq.f32 %p125, %f1016, 0f3EE66666;
|
|
@%p125 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1563, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
add.f32 %f1019, %f288, 0f3EE66666;
|
|
mov.b32 %r366, %f1019;
|
|
setp.lt.s32 %p127, %r366, 2139095040;
|
|
@%p127 bra $L__BB0_105;
|
|
|
|
setp.gtu.f32 %p128, %f288, 0f7F800000;
|
|
@%p128 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1563, %f262, 0f3EE66666;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
setp.neu.f32 %p129, %f288, 0f7F800000;
|
|
@%p129 bra $L__BB0_105;
|
|
|
|
selp.f32 %f1563, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_105:
|
|
setp.eq.f32 %p130, %f262, 0f3F800000;
|
|
mov.f32 %f1021, 0f3F800000;
|
|
selp.f32 %f1022, 0f3F800000, %f1563, %p130;
|
|
ld.const.u64 %rd79, [params+144];
|
|
cvta.to.global.u64 %rd21, %rd79;
|
|
ld.const.u32 %r367, [params+136];
|
|
mad.lo.s32 %r368, %r367, %r8, %r7;
|
|
cvt.u64.u32 %rd22, %r368;
|
|
min.f32 %f1023, %f275, %f1021;
|
|
mov.f32 %f1024, 0f00000000;
|
|
max.f32 %f299, %f1024, %f1023;
|
|
min.f32 %f1025, %f287, %f1021;
|
|
max.f32 %f300, %f1024, %f1025;
|
|
min.f32 %f1026, %f1022, %f1021;
|
|
max.f32 %f301, %f1024, %f1026;
|
|
mov.f32 %f1027, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1028, %f1027;
|
|
add.f32 %f1029, %f1028, %f1028;
|
|
mov.f32 %f1030, 0f3ED55555;
|
|
sub.f32 %f1031, %f1030, %f1029;
|
|
abs.f32 %f302, %f1031;
|
|
abs.f32 %f303, %f299;
|
|
setp.lt.f32 %p131, %f303, 0f00800000;
|
|
mul.f32 %f1032, %f303, 0f4B800000;
|
|
selp.f32 %f1033, %f1032, %f303, %p131;
|
|
selp.f32 %f1034, 0fC3170000, 0fC2FE0000, %p131;
|
|
mov.b32 %r369, %f1033;
|
|
and.b32 %r370, %r369, 8388607;
|
|
or.b32 %r371, %r370, 1065353216;
|
|
mov.b32 %f1035, %r371;
|
|
shr.u32 %r372, %r369, 23;
|
|
cvt.rn.f32.u32 %f1036, %r372;
|
|
add.f32 %f1037, %f1034, %f1036;
|
|
setp.gt.f32 %p132, %f1035, 0f3FB504F3;
|
|
mul.f32 %f1038, %f1035, 0f3F000000;
|
|
add.f32 %f1039, %f1037, 0f3F800000;
|
|
selp.f32 %f1040, %f1039, %f1037, %p132;
|
|
selp.f32 %f1041, %f1038, %f1035, %p132;
|
|
add.f32 %f1042, %f1041, 0fBF800000;
|
|
add.f32 %f1043, %f1041, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1044, %f1043;
|
|
add.f32 %f1045, %f1042, %f1042;
|
|
mul.f32 %f1046, %f1045, %f1044;
|
|
mul.f32 %f1047, %f1046, %f1046;
|
|
mov.f32 %f1048, 0f3C4CAF63;
|
|
mov.f32 %f1049, 0f3B18F0FE;
|
|
fma.rn.f32 %f1050, %f1049, %f1047, %f1048;
|
|
mov.f32 %f1051, 0f3DAAAABD;
|
|
fma.rn.f32 %f1052, %f1050, %f1047, %f1051;
|
|
mul.rn.f32 %f1053, %f1052, %f1047;
|
|
mul.rn.f32 %f1054, %f1053, %f1046;
|
|
sub.f32 %f1055, %f1042, %f1046;
|
|
add.f32 %f1056, %f1055, %f1055;
|
|
neg.f32 %f1057, %f1046;
|
|
fma.rn.f32 %f1058, %f1057, %f1042, %f1056;
|
|
mul.rn.f32 %f1059, %f1044, %f1058;
|
|
add.f32 %f1060, %f1054, %f1046;
|
|
sub.f32 %f1061, %f1046, %f1060;
|
|
add.f32 %f1062, %f1054, %f1061;
|
|
add.f32 %f1063, %f1059, %f1062;
|
|
add.f32 %f1064, %f1060, %f1063;
|
|
sub.f32 %f1065, %f1060, %f1064;
|
|
add.f32 %f1066, %f1063, %f1065;
|
|
mov.f32 %f1067, 0f3F317200;
|
|
mul.rn.f32 %f1068, %f1040, %f1067;
|
|
mov.f32 %f1069, 0f35BFBE8E;
|
|
mul.rn.f32 %f1070, %f1040, %f1069;
|
|
add.f32 %f1071, %f1068, %f1064;
|
|
sub.f32 %f1072, %f1068, %f1071;
|
|
add.f32 %f1073, %f1064, %f1072;
|
|
add.f32 %f1074, %f1066, %f1073;
|
|
add.f32 %f1075, %f1070, %f1074;
|
|
add.f32 %f1076, %f1071, %f1075;
|
|
sub.f32 %f1077, %f1071, %f1076;
|
|
add.f32 %f1078, %f1075, %f1077;
|
|
mul.rn.f32 %f1079, %f1030, %f1076;
|
|
neg.f32 %f1080, %f1079;
|
|
fma.rn.f32 %f1081, %f1030, %f1076, %f1080;
|
|
fma.rn.f32 %f1082, %f1030, %f1078, %f1081;
|
|
fma.rn.f32 %f1083, %f1024, %f1076, %f1082;
|
|
add.rn.f32 %f1084, %f1079, %f1083;
|
|
neg.f32 %f1085, %f1084;
|
|
add.rn.f32 %f1086, %f1079, %f1085;
|
|
add.rn.f32 %f1087, %f1086, %f1083;
|
|
mov.b32 %r373, %f1084;
|
|
setp.eq.s32 %p133, %r373, 1118925336;
|
|
add.s32 %r374, %r373, -1;
|
|
mov.b32 %f1088, %r374;
|
|
add.f32 %f1089, %f1087, 0f37000000;
|
|
selp.f32 %f304, %f1089, %f1087, %p133;
|
|
selp.f32 %f1090, %f1088, %f1084, %p133;
|
|
mov.f32 %f1091, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1092, %f1090, %f1091;
|
|
cvt.rzi.f32.f32 %f1093, %f1092;
|
|
abs.f32 %f1094, %f1093;
|
|
setp.gt.f32 %p134, %f1094, 0f42FC0000;
|
|
mov.b32 %r375, %f1093;
|
|
and.b32 %r376, %r375, -2147483648;
|
|
or.b32 %r377, %r376, 1123811328;
|
|
mov.b32 %f1095, %r377;
|
|
selp.f32 %f1096, %f1095, %f1093, %p134;
|
|
mov.f32 %f1097, 0fBF317218;
|
|
fma.rn.f32 %f1098, %f1096, %f1097, %f1090;
|
|
mov.f32 %f1099, 0f3102E308;
|
|
fma.rn.f32 %f1100, %f1096, %f1099, %f1098;
|
|
mul.f32 %f1101, %f1100, 0f3FB8AA3B;
|
|
add.f32 %f1102, %f1096, 0f4B40007F;
|
|
mov.b32 %r378, %f1102;
|
|
shl.b32 %r379, %r378, 23;
|
|
mov.b32 %f1103, %r379;
|
|
ex2.approx.ftz.f32 %f1104, %f1101;
|
|
mul.f32 %f305, %f1104, %f1103;
|
|
setp.eq.f32 %p135, %f305, 0f7F800000;
|
|
mov.f32 %f1564, 0f7F800000;
|
|
@%p135 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f1564, %f305, %f304, %f305;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p136, %f299, 0f00000000;
|
|
setp.eq.f32 %p137, %f302, 0f3F800000;
|
|
and.pred %p7, %p136, %p137;
|
|
setp.eq.f32 %p138, %f299, 0f00000000;
|
|
@%p138 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f1109, %f299, %f299;
|
|
selp.f32 %f1566, %f1109, 0f00000000, %p137;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r380, %f1564;
|
|
xor.b32 %r381, %r380, -2147483648;
|
|
mov.b32 %f1105, %r381;
|
|
selp.f32 %f1566, %f1105, %f1564, %p7;
|
|
setp.geu.f32 %p139, %f299, 0f00000000;
|
|
@%p139 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1106, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1107, %f1106;
|
|
setp.eq.f32 %p140, %f1107, 0f3ED55555;
|
|
@%p140 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1566, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
add.f32 %f1110, %f303, 0f3ED55555;
|
|
mov.b32 %r382, %f1110;
|
|
setp.lt.s32 %p142, %r382, 2139095040;
|
|
@%p142 bra $L__BB0_117;
|
|
|
|
setp.gtu.f32 %p143, %f303, 0f7F800000;
|
|
@%p143 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1566, %f299, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
setp.neu.f32 %p144, %f303, 0f7F800000;
|
|
@%p144 bra $L__BB0_117;
|
|
|
|
selp.f32 %f1566, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_117:
|
|
abs.f32 %f314, %f300;
|
|
setp.lt.f32 %p145, %f314, 0f00800000;
|
|
mul.f32 %f1112, %f314, 0f4B800000;
|
|
selp.f32 %f1113, %f1112, %f314, %p145;
|
|
selp.f32 %f1114, 0fC3170000, 0fC2FE0000, %p145;
|
|
mov.b32 %r383, %f1113;
|
|
and.b32 %r384, %r383, 8388607;
|
|
or.b32 %r385, %r384, 1065353216;
|
|
mov.b32 %f1115, %r385;
|
|
shr.u32 %r386, %r383, 23;
|
|
cvt.rn.f32.u32 %f1116, %r386;
|
|
add.f32 %f1117, %f1114, %f1116;
|
|
setp.gt.f32 %p146, %f1115, 0f3FB504F3;
|
|
mul.f32 %f1118, %f1115, 0f3F000000;
|
|
add.f32 %f1119, %f1117, 0f3F800000;
|
|
selp.f32 %f1120, %f1119, %f1117, %p146;
|
|
selp.f32 %f1121, %f1118, %f1115, %p146;
|
|
add.f32 %f1122, %f1121, 0fBF800000;
|
|
add.f32 %f1123, %f1121, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1124, %f1123;
|
|
add.f32 %f1125, %f1122, %f1122;
|
|
mul.f32 %f1126, %f1125, %f1124;
|
|
mul.f32 %f1127, %f1126, %f1126;
|
|
mov.f32 %f1128, 0f3C4CAF63;
|
|
mov.f32 %f1129, 0f3B18F0FE;
|
|
fma.rn.f32 %f1130, %f1129, %f1127, %f1128;
|
|
mov.f32 %f1131, 0f3DAAAABD;
|
|
fma.rn.f32 %f1132, %f1130, %f1127, %f1131;
|
|
mul.rn.f32 %f1133, %f1132, %f1127;
|
|
mul.rn.f32 %f1134, %f1133, %f1126;
|
|
sub.f32 %f1135, %f1122, %f1126;
|
|
add.f32 %f1136, %f1135, %f1135;
|
|
neg.f32 %f1137, %f1126;
|
|
fma.rn.f32 %f1138, %f1137, %f1122, %f1136;
|
|
mul.rn.f32 %f1139, %f1124, %f1138;
|
|
add.f32 %f1140, %f1134, %f1126;
|
|
sub.f32 %f1141, %f1126, %f1140;
|
|
add.f32 %f1142, %f1134, %f1141;
|
|
add.f32 %f1143, %f1139, %f1142;
|
|
add.f32 %f1144, %f1140, %f1143;
|
|
sub.f32 %f1145, %f1140, %f1144;
|
|
add.f32 %f1146, %f1143, %f1145;
|
|
mov.f32 %f1147, 0f3F317200;
|
|
mul.rn.f32 %f1148, %f1120, %f1147;
|
|
mov.f32 %f1149, 0f35BFBE8E;
|
|
mul.rn.f32 %f1150, %f1120, %f1149;
|
|
add.f32 %f1151, %f1148, %f1144;
|
|
sub.f32 %f1152, %f1148, %f1151;
|
|
add.f32 %f1153, %f1144, %f1152;
|
|
add.f32 %f1154, %f1146, %f1153;
|
|
add.f32 %f1155, %f1150, %f1154;
|
|
add.f32 %f1156, %f1151, %f1155;
|
|
sub.f32 %f1157, %f1151, %f1156;
|
|
add.f32 %f1158, %f1155, %f1157;
|
|
mov.f32 %f1159, 0f3ED55555;
|
|
mul.rn.f32 %f1160, %f1159, %f1156;
|
|
neg.f32 %f1161, %f1160;
|
|
fma.rn.f32 %f1162, %f1159, %f1156, %f1161;
|
|
fma.rn.f32 %f1163, %f1159, %f1158, %f1162;
|
|
mov.f32 %f1164, 0f00000000;
|
|
fma.rn.f32 %f1165, %f1164, %f1156, %f1163;
|
|
add.rn.f32 %f1166, %f1160, %f1165;
|
|
neg.f32 %f1167, %f1166;
|
|
add.rn.f32 %f1168, %f1160, %f1167;
|
|
add.rn.f32 %f1169, %f1168, %f1165;
|
|
mov.b32 %r387, %f1166;
|
|
setp.eq.s32 %p147, %r387, 1118925336;
|
|
add.s32 %r388, %r387, -1;
|
|
mov.b32 %f1170, %r388;
|
|
add.f32 %f1171, %f1169, 0f37000000;
|
|
selp.f32 %f315, %f1171, %f1169, %p147;
|
|
selp.f32 %f1172, %f1170, %f1166, %p147;
|
|
mov.f32 %f1173, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1174, %f1172, %f1173;
|
|
cvt.rzi.f32.f32 %f1175, %f1174;
|
|
abs.f32 %f1176, %f1175;
|
|
setp.gt.f32 %p148, %f1176, 0f42FC0000;
|
|
mov.b32 %r389, %f1175;
|
|
and.b32 %r390, %r389, -2147483648;
|
|
or.b32 %r391, %r390, 1123811328;
|
|
mov.b32 %f1177, %r391;
|
|
selp.f32 %f1178, %f1177, %f1175, %p148;
|
|
mov.f32 %f1179, 0fBF317218;
|
|
fma.rn.f32 %f1180, %f1178, %f1179, %f1172;
|
|
mov.f32 %f1181, 0f3102E308;
|
|
fma.rn.f32 %f1182, %f1178, %f1181, %f1180;
|
|
mul.f32 %f1183, %f1182, 0f3FB8AA3B;
|
|
add.f32 %f1184, %f1178, 0f4B40007F;
|
|
mov.b32 %r392, %f1184;
|
|
shl.b32 %r393, %r392, 23;
|
|
mov.b32 %f1185, %r393;
|
|
ex2.approx.ftz.f32 %f1186, %f1183;
|
|
mul.f32 %f316, %f1186, %f1185;
|
|
setp.eq.f32 %p149, %f316, 0f7F800000;
|
|
mov.f32 %f1567, 0f7F800000;
|
|
@%p149 bra $L__BB0_119;
|
|
|
|
fma.rn.f32 %f1567, %f316, %f315, %f316;
|
|
|
|
$L__BB0_119:
|
|
setp.lt.f32 %p150, %f300, 0f00000000;
|
|
and.pred %p8, %p150, %p137;
|
|
setp.eq.f32 %p152, %f300, 0f00000000;
|
|
@%p152 bra $L__BB0_123;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_123:
|
|
add.f32 %f1191, %f300, %f300;
|
|
selp.f32 %f1569, %f1191, 0f00000000, %p137;
|
|
bra.uni $L__BB0_124;
|
|
|
|
$L__BB0_120:
|
|
mov.b32 %r394, %f1567;
|
|
xor.b32 %r395, %r394, -2147483648;
|
|
mov.b32 %f1187, %r395;
|
|
selp.f32 %f1569, %f1187, %f1567, %p8;
|
|
setp.geu.f32 %p153, %f300, 0f00000000;
|
|
@%p153 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1188, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1189, %f1188;
|
|
setp.eq.f32 %p154, %f1189, 0f3ED55555;
|
|
@%p154 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1569, 0f7FFFFFFF;
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1192, %f314, 0f3ED55555;
|
|
mov.b32 %r396, %f1192;
|
|
setp.lt.s32 %p156, %r396, 2139095040;
|
|
@%p156 bra $L__BB0_129;
|
|
|
|
setp.gtu.f32 %p157, %f314, 0f7F800000;
|
|
@%p157 bra $L__BB0_128;
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f1569, %f300, 0f3ED55555;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_126:
|
|
setp.neu.f32 %p158, %f314, 0f7F800000;
|
|
@%p158 bra $L__BB0_129;
|
|
|
|
selp.f32 %f1569, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_129:
|
|
abs.f32 %f325, %f301;
|
|
setp.lt.f32 %p159, %f325, 0f00800000;
|
|
mul.f32 %f1194, %f325, 0f4B800000;
|
|
selp.f32 %f1195, %f1194, %f325, %p159;
|
|
selp.f32 %f1196, 0fC3170000, 0fC2FE0000, %p159;
|
|
mov.b32 %r397, %f1195;
|
|
and.b32 %r398, %r397, 8388607;
|
|
or.b32 %r399, %r398, 1065353216;
|
|
mov.b32 %f1197, %r399;
|
|
shr.u32 %r400, %r397, 23;
|
|
cvt.rn.f32.u32 %f1198, %r400;
|
|
add.f32 %f1199, %f1196, %f1198;
|
|
setp.gt.f32 %p160, %f1197, 0f3FB504F3;
|
|
mul.f32 %f1200, %f1197, 0f3F000000;
|
|
add.f32 %f1201, %f1199, 0f3F800000;
|
|
selp.f32 %f1202, %f1201, %f1199, %p160;
|
|
selp.f32 %f1203, %f1200, %f1197, %p160;
|
|
add.f32 %f1204, %f1203, 0fBF800000;
|
|
add.f32 %f1205, %f1203, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1206, %f1205;
|
|
add.f32 %f1207, %f1204, %f1204;
|
|
mul.f32 %f1208, %f1207, %f1206;
|
|
mul.f32 %f1209, %f1208, %f1208;
|
|
mov.f32 %f1210, 0f3C4CAF63;
|
|
mov.f32 %f1211, 0f3B18F0FE;
|
|
fma.rn.f32 %f1212, %f1211, %f1209, %f1210;
|
|
mov.f32 %f1213, 0f3DAAAABD;
|
|
fma.rn.f32 %f1214, %f1212, %f1209, %f1213;
|
|
mul.rn.f32 %f1215, %f1214, %f1209;
|
|
mul.rn.f32 %f1216, %f1215, %f1208;
|
|
sub.f32 %f1217, %f1204, %f1208;
|
|
add.f32 %f1218, %f1217, %f1217;
|
|
neg.f32 %f1219, %f1208;
|
|
fma.rn.f32 %f1220, %f1219, %f1204, %f1218;
|
|
mul.rn.f32 %f1221, %f1206, %f1220;
|
|
add.f32 %f1222, %f1216, %f1208;
|
|
sub.f32 %f1223, %f1208, %f1222;
|
|
add.f32 %f1224, %f1216, %f1223;
|
|
add.f32 %f1225, %f1221, %f1224;
|
|
add.f32 %f1226, %f1222, %f1225;
|
|
sub.f32 %f1227, %f1222, %f1226;
|
|
add.f32 %f1228, %f1225, %f1227;
|
|
mov.f32 %f1229, 0f3F317200;
|
|
mul.rn.f32 %f1230, %f1202, %f1229;
|
|
mov.f32 %f1231, 0f35BFBE8E;
|
|
mul.rn.f32 %f1232, %f1202, %f1231;
|
|
add.f32 %f1233, %f1230, %f1226;
|
|
sub.f32 %f1234, %f1230, %f1233;
|
|
add.f32 %f1235, %f1226, %f1234;
|
|
add.f32 %f1236, %f1228, %f1235;
|
|
add.f32 %f1237, %f1232, %f1236;
|
|
add.f32 %f1238, %f1233, %f1237;
|
|
sub.f32 %f1239, %f1233, %f1238;
|
|
add.f32 %f1240, %f1237, %f1239;
|
|
mov.f32 %f1241, 0f3ED55555;
|
|
mul.rn.f32 %f1242, %f1241, %f1238;
|
|
neg.f32 %f1243, %f1242;
|
|
fma.rn.f32 %f1244, %f1241, %f1238, %f1243;
|
|
fma.rn.f32 %f1245, %f1241, %f1240, %f1244;
|
|
mov.f32 %f1246, 0f00000000;
|
|
fma.rn.f32 %f1247, %f1246, %f1238, %f1245;
|
|
add.rn.f32 %f1248, %f1242, %f1247;
|
|
neg.f32 %f1249, %f1248;
|
|
add.rn.f32 %f1250, %f1242, %f1249;
|
|
add.rn.f32 %f1251, %f1250, %f1247;
|
|
mov.b32 %r401, %f1248;
|
|
setp.eq.s32 %p161, %r401, 1118925336;
|
|
add.s32 %r402, %r401, -1;
|
|
mov.b32 %f1252, %r402;
|
|
add.f32 %f1253, %f1251, 0f37000000;
|
|
selp.f32 %f326, %f1253, %f1251, %p161;
|
|
selp.f32 %f1254, %f1252, %f1248, %p161;
|
|
mov.f32 %f1255, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1256, %f1254, %f1255;
|
|
cvt.rzi.f32.f32 %f1257, %f1256;
|
|
abs.f32 %f1258, %f1257;
|
|
setp.gt.f32 %p162, %f1258, 0f42FC0000;
|
|
mov.b32 %r403, %f1257;
|
|
and.b32 %r404, %r403, -2147483648;
|
|
or.b32 %r405, %r404, 1123811328;
|
|
mov.b32 %f1259, %r405;
|
|
selp.f32 %f1260, %f1259, %f1257, %p162;
|
|
mov.f32 %f1261, 0fBF317218;
|
|
fma.rn.f32 %f1262, %f1260, %f1261, %f1254;
|
|
mov.f32 %f1263, 0f3102E308;
|
|
fma.rn.f32 %f1264, %f1260, %f1263, %f1262;
|
|
mul.f32 %f1265, %f1264, 0f3FB8AA3B;
|
|
add.f32 %f1266, %f1260, 0f4B40007F;
|
|
mov.b32 %r406, %f1266;
|
|
shl.b32 %r407, %r406, 23;
|
|
mov.b32 %f1267, %r407;
|
|
ex2.approx.ftz.f32 %f1268, %f1265;
|
|
mul.f32 %f327, %f1268, %f1267;
|
|
setp.eq.f32 %p163, %f327, 0f7F800000;
|
|
mov.f32 %f1570, 0f7F800000;
|
|
@%p163 bra $L__BB0_131;
|
|
|
|
fma.rn.f32 %f1570, %f327, %f326, %f327;
|
|
|
|
$L__BB0_131:
|
|
setp.lt.f32 %p164, %f301, 0f00000000;
|
|
and.pred %p9, %p164, %p137;
|
|
setp.eq.f32 %p166, %f301, 0f00000000;
|
|
@%p166 bra $L__BB0_135;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_135:
|
|
add.f32 %f1273, %f301, %f301;
|
|
selp.f32 %f1572, %f1273, 0f00000000, %p137;
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_132:
|
|
mov.b32 %r408, %f1570;
|
|
xor.b32 %r409, %r408, -2147483648;
|
|
mov.b32 %f1269, %r409;
|
|
selp.f32 %f1572, %f1269, %f1570, %p9;
|
|
setp.geu.f32 %p167, %f301, 0f00000000;
|
|
@%p167 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1270, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1271, %f1270;
|
|
setp.eq.f32 %p168, %f1271, 0f3ED55555;
|
|
@%p168 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1572, 0f7FFFFFFF;
|
|
|
|
$L__BB0_136:
|
|
add.f32 %f1274, %f325, 0f3ED55555;
|
|
mov.b32 %r410, %f1274;
|
|
setp.lt.s32 %p170, %r410, 2139095040;
|
|
@%p170 bra $L__BB0_141;
|
|
|
|
setp.gtu.f32 %p171, %f325, 0f7F800000;
|
|
@%p171 bra $L__BB0_140;
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f1572, %f301, 0f3ED55555;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_138:
|
|
setp.neu.f32 %p172, %f325, 0f7F800000;
|
|
@%p172 bra $L__BB0_141;
|
|
|
|
selp.f32 %f1572, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_141:
|
|
fma.rn.f32 %f1275, %f1566, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p173, %f299, 0f3F800000;
|
|
mov.f32 %f1276, 0f3F800000;
|
|
selp.f32 %f1277, 0f3F7FFFFF, %f1275, %p173;
|
|
mul.f32 %f1278, %f299, 0f414EB852;
|
|
setp.lt.f32 %p174, %f299, 0f3B4D2E1C;
|
|
selp.f32 %f1279, %f1278, %f1277, %p174;
|
|
fma.rn.f32 %f1280, %f1569, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p175, %f300, 0f3F800000;
|
|
selp.f32 %f1281, 0f3F7FFFFF, %f1280, %p175;
|
|
mul.f32 %f1282, %f300, 0f414EB852;
|
|
setp.lt.f32 %p176, %f300, 0f3B4D2E1C;
|
|
selp.f32 %f1283, %f1282, %f1281, %p176;
|
|
fma.rn.f32 %f1284, %f1572, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p177, %f301, 0f3F800000;
|
|
selp.f32 %f1285, 0f3F7FFFFF, %f1284, %p177;
|
|
mul.f32 %f1286, %f301, 0f414EB852;
|
|
setp.lt.f32 %p178, %f301, 0f3B4D2E1C;
|
|
selp.f32 %f1287, %f1286, %f1285, %p178;
|
|
min.f32 %f1288, %f1279, %f1276;
|
|
mov.f32 %f1289, 0f00000000;
|
|
max.f32 %f1290, %f1289, %f1288;
|
|
mul.f32 %f1291, %f1290, 0f43800000;
|
|
cvt.rzi.u32.f32 %r411, %f1291;
|
|
min.u32 %r412, %r411, 255;
|
|
min.f32 %f1292, %f1283, %f1276;
|
|
max.f32 %f1293, %f1289, %f1292;
|
|
mul.f32 %f1294, %f1293, 0f43800000;
|
|
cvt.rzi.u32.f32 %r413, %f1294;
|
|
min.u32 %r414, %r413, 255;
|
|
min.f32 %f1295, %f1287, %f1276;
|
|
max.f32 %f1296, %f1289, %f1295;
|
|
mul.f32 %f1297, %f1296, 0f43800000;
|
|
cvt.rzi.u32.f32 %r415, %f1297;
|
|
min.u32 %r416, %r415, 255;
|
|
shl.b64 %rd80, %rd22, 2;
|
|
add.s64 %rd81, %rd21, %rd80;
|
|
cvt.u16.u32 %rs18, %r416;
|
|
cvt.u16.u32 %rs19, %r414;
|
|
cvt.u16.u32 %rs20, %r412;
|
|
mov.u16 %rs21, 255;
|
|
st.global.v4.u8 [%rd81], {%rs20, %rs19, %rs18, %rs21};
|
|
|
|
$L__BB0_142:
|
|
and.b32 %r417, %r54, 4;
|
|
setp.eq.s32 %p179, %r417, 0;
|
|
ld.const.u32 %r462, [params+108];
|
|
@%p179 bra $L__BB0_146;
|
|
|
|
setp.eq.s32 %p180, %r462, 0;
|
|
ld.const.u64 %rd82, [params+224];
|
|
cvta.to.global.u64 %rd83, %rd82;
|
|
ld.const.u32 %r418, [params+216];
|
|
mad.lo.s32 %r419, %r418, %r8, %r7;
|
|
mul.wide.u32 %rd84, %r419, 8;
|
|
add.s64 %rd23, %rd83, %rd84;
|
|
@%p180 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs29, %rs30, %rs31, %rs32}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1298, %rs29;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1299, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1300, %rs31;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1301, %f259, %f1298;
|
|
add.f32 %f1302, %f260, %f1299;
|
|
add.f32 %f1303, %f262, %f1300;
|
|
mov.f32 %f1304, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1303;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f1302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1301;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1304;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs25, %rs26, %rs27, %rs28};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1308, 0f3F800000;
|
|
mov.u32 %r462, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1308;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f262;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f260;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f259;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs33, %rs34, %rs35, %rs36};
|
|
|
|
$L__BB0_146:
|
|
selp.f32 %f1309, 0f3F800000, 0f3E800000, %p196;
|
|
mul.f32 %f1310, %f1309, %f1545;
|
|
mul.f32 %f1311, %f1309, %f1546;
|
|
mul.f32 %f1312, %f1309, %f1547;
|
|
mul.f32 %f1313, %f1309, %f1542;
|
|
mul.f32 %f1314, %f1309, %f1543;
|
|
mul.f32 %f1315, %f1309, %f1544;
|
|
mul.f32 %f1316, %f1309, %f1539;
|
|
mul.f32 %f1317, %f1309, %f1540;
|
|
mul.f32 %f1318, %f1309, %f1541;
|
|
mul.f32 %f1319, %f1309, %f1536;
|
|
mul.f32 %f1320, %f1309, %f1537;
|
|
mul.f32 %f1321, %f1309, %f1538;
|
|
mul.f32 %f336, %f1310, %f768;
|
|
mul.f32 %f337, %f1311, %f769;
|
|
mul.f32 %f338, %f1312, %f261;
|
|
mul.f32 %f339, %f1313, %f768;
|
|
mul.f32 %f340, %f1314, %f769;
|
|
mul.f32 %f341, %f1315, %f261;
|
|
mul.f32 %f342, %f1316, %f768;
|
|
mul.f32 %f343, %f1317, %f769;
|
|
mul.f32 %f344, %f1318, %f261;
|
|
mul.f32 %f345, %f1319, %f768;
|
|
mul.f32 %f346, %f1320, %f769;
|
|
mul.f32 %f347, %f1321, %f261;
|
|
ld.const.u64 %rd85, [params+256];
|
|
cvta.to.global.u64 %rd86, %rd85;
|
|
ld.const.u32 %r421, [params+248];
|
|
mad.lo.s32 %r422, %r421, %r8, %r7;
|
|
mul.wide.u32 %rd87, %r422, 8;
|
|
add.s64 %rd24, %rd86, %rd87;
|
|
setp.eq.s32 %p181, %r462, 0;
|
|
@%p181 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs44, %rs45, %rs46, %rs47}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1322, %rs44;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1323, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1324, %rs46;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1325, %f336, %f1322;
|
|
add.f32 %f1326, %f337, %f1323;
|
|
add.f32 %f1327, %f338, %f1324;
|
|
mov.f32 %f1328, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1327;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f1326;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1328;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs40, %rs41, %rs42, %rs43};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1332, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1332;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f338;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f337;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f336;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs48, %rs49, %rs50, %rs51};
|
|
|
|
$L__BB0_149:
|
|
mov.f32 %f1333, 0f34000000;
|
|
max.f32 %f1334, %f336, %f1333;
|
|
div.rn.f32 %f1335, %f339, %f1334;
|
|
max.f32 %f1336, %f337, %f1333;
|
|
div.rn.f32 %f1337, %f340, %f1336;
|
|
max.f32 %f1338, %f338, %f1333;
|
|
div.rn.f32 %f1339, %f341, %f1338;
|
|
fma.rn.f32 %f348, %f1335, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f349, %f1337, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f350, %f1339, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1340, %f342, %f1334;
|
|
div.rn.f32 %f1341, %f343, %f1336;
|
|
div.rn.f32 %f1342, %f344, %f1338;
|
|
fma.rn.f32 %f351, %f1340, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f352, %f1341, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f353, %f1342, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1343, %f345, %f1334;
|
|
div.rn.f32 %f1344, %f346, %f1336;
|
|
div.rn.f32 %f1345, %f347, %f1338;
|
|
fma.rn.f32 %f354, %f1343, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f355, %f1344, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f356, %f1345, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd88, [params+272];
|
|
cvta.to.global.u64 %rd89, %rd88;
|
|
ld.const.u32 %r423, [params+264];
|
|
mad.lo.s32 %r424, %r423, %r8, %r7;
|
|
mul.wide.u32 %rd90, %r424, 8;
|
|
add.s64 %rd25, %rd89, %rd90;
|
|
@%p181 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs59, %rs60, %rs61, %rs62}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1346, %rs59;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1347, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1348, %rs61;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1349, %f348, %f1346;
|
|
add.f32 %f1350, %f349, %f1347;
|
|
add.f32 %f1351, %f350, %f1348;
|
|
mov.f32 %f1352, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1351;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1350;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1349;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1352;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs55, %rs56, %rs57, %rs58};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1356, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1356;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f350;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f349;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f348;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs63, %rs64, %rs65, %rs66};
|
|
|
|
$L__BB0_152:
|
|
ld.const.u64 %rd91, [params+288];
|
|
cvta.to.global.u64 %rd92, %rd91;
|
|
ld.const.u32 %r425, [params+280];
|
|
mad.lo.s32 %r426, %r425, %r8, %r7;
|
|
mul.wide.u32 %rd93, %r426, 8;
|
|
add.s64 %rd26, %rd92, %rd93;
|
|
@%p181 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs74, %rs75, %rs76, %rs77}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1357, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1358, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1359, %rs76;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1360, %f351, %f1357;
|
|
add.f32 %f1361, %f352, %f1358;
|
|
add.f32 %f1362, %f353, %f1359;
|
|
mov.f32 %f1363, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1362;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1361;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1360;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1363;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs70, %rs71, %rs72, %rs73};
|
|
bra.uni $L__BB0_155;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1367, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1367;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f353;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f352;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f351;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs78, %rs79, %rs80, %rs81};
|
|
|
|
$L__BB0_155:
|
|
ld.const.u64 %rd94, [params+304];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r427, [params+296];
|
|
mad.lo.s32 %r428, %r427, %r8, %r7;
|
|
mul.wide.u32 %rd96, %r428, 8;
|
|
add.s64 %rd27, %rd95, %rd96;
|
|
@%p181 bra $L__BB0_157;
|
|
|
|
ld.global.v4.u16 {%rs89, %rs90, %rs91, %rs92}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1368, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1369, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1370, %rs91;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1371, %f354, %f1368;
|
|
add.f32 %f1372, %f355, %f1369;
|
|
add.f32 %f1373, %f356, %f1370;
|
|
mov.f32 %f1374, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1373;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1372;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1371;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1374;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs85, %rs86, %rs87, %rs88};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_157:
|
|
mov.f32 %f1378, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1378;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f356;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f355;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f354;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs93, %rs94, %rs95, %rs96};
|
|
|
|
$L__BB0_178:
|
|
ret;
|
|
|
|
}
|
|
|