2301 lines
63 KiB
Plaintext
2301 lines
63 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<162>;
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.reg .b16 %rs<169>;
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.reg .f32 %f<1268>;
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.reg .b32 %r<361>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<118>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r52), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r53), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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ld.const.u64 %rd25, [params+400];
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cvta.to.global.u64 %rd26, %rd25;
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ld.const.u32 %r58, [params+392];
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mad.lo.s32 %r59, %r58, %r53, %r52;
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mul.wide.u32 %rd27, %r59, 4;
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add.s64 %rd2, %rd26, %rd27;
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ld.global.v2.u8 {%rs16, %rs164}, [%rd2];
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or.b16 %rs18, %rs16, %rs164;
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and.b16 %rs19, %rs18, 255;
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setp.eq.s16 %p7, %rs19, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs163, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs163, [%rd2+2];
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setp.eq.s16 %p8, %rs163, 0;
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mov.f32 %f1193, 0f00000000;
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mov.u16 %rs164, 0;
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mov.f32 %f1194, %f1193;
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mov.f32 %f1195, %f1193;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f244, %rs16;
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div.rn.f32 %f245, %f244, 0f437F0000;
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fma.rn.f32 %f246, %f245, 0f40000000, 0fBF800000;
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and.b16 %rs22, %rs164, 255;
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cvt.rn.f32.u16 %f247, %rs22;
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div.rn.f32 %f248, %f247, 0f437F0000;
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fma.rn.f32 %f249, %f248, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f250, %rs163;
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div.rn.f32 %f251, %f250, 0f437F0000;
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fma.rn.f32 %f252, %f251, 0f40000000, 0fBF800000;
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mul.f32 %f253, %f249, %f249;
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fma.rn.f32 %f254, %f246, %f246, %f253;
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fma.rn.f32 %f255, %f252, %f252, %f254;
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sqrt.rn.f32 %f256, %f255;
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rcp.rn.f32 %f257, %f256;
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mul.f32 %f1195, %f257, %f252;
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mul.f32 %f1194, %f257, %f249;
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mul.f32 %f1193, %f246, %f257;
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$L__BB0_4:
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ld.const.v2.u32 {%r60, %r61}, [params];
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add.s32 %r4, %r60, %r52;
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add.s32 %r5, %r61, %r53;
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setp.eq.f32 %p9, %f1193, 0f00000000;
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setp.eq.f32 %p10, %f1194, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1195, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_133;
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bra.uni $L__BB0_5;
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$L__BB0_133:
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ld.const.u32 %r50, [params+104];
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and.b32 %r315, %r50, 1;
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setp.eq.b32 %p152, %r315, 1;
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mov.pred %p153, 0;
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xor.pred %p154, %p152, %p153;
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not.pred %p155, %p154;
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@%p155 bra $L__BB0_135;
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ld.const.u64 %rd89, [params+144];
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cvta.to.global.u64 %rd90, %rd89;
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ld.const.u32 %r316, [params+136];
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mad.lo.s32 %r317, %r316, %r5, %r4;
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mul.wide.u32 %rd91, %r317, 4;
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add.s64 %rd92, %rd90, %rd91;
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mov.u16 %rs109, 0;
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st.global.v4.u8 [%rd92], {%rs109, %rs109, %rs109, %rs109};
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$L__BB0_135:
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and.b32 %r318, %r50, 4;
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setp.eq.s32 %p156, %r318, 0;
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@%p156 bra $L__BB0_137;
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ld.const.u64 %rd93, [params+224];
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cvta.to.global.u64 %rd94, %rd93;
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ld.const.u32 %r319, [params+216];
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mad.lo.s32 %r320, %r319, %r5, %r4;
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mov.f32 %f1133, 0f00000000;
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mul.wide.u32 %rd95, %r320, 8;
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add.s64 %rd96, %rd94, %rd95;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs112, %f1133;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs111, %f1133;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs110, %f1133;}
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// end inline asm
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mov.u16 %rs113, 0;
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st.global.v4.u16 [%rd96], {%rs110, %rs111, %rs112, %rs113};
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$L__BB0_137:
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and.b32 %r321, %r50, 16;
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setp.eq.s32 %p157, %r321, 0;
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@%p157 bra $L__BB0_139;
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ld.const.u64 %rd97, [params+240];
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cvta.to.global.u64 %rd98, %rd97;
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ld.const.u32 %r322, [params+232];
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mad.lo.s32 %r323, %r322, %r5, %r4;
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mov.f32 %f1136, 0f00000000;
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mul.wide.u32 %rd99, %r323, 8;
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add.s64 %rd100, %rd98, %rd99;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs116, %f1136;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs115, %f1136;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs114, %f1136;}
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// end inline asm
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mov.u16 %rs117, 0;
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st.global.v4.u16 [%rd100], {%rs114, %rs115, %rs116, %rs117};
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$L__BB0_139:
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ld.const.u32 %r51, [params+108];
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setp.eq.s32 %p158, %r51, 0;
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ld.const.u64 %rd101, [params+256];
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cvta.to.global.u64 %rd102, %rd101;
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ld.const.u32 %r324, [params+248];
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mad.lo.s32 %r325, %r324, %r5, %r4;
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mul.wide.u32 %rd103, %r325, 8;
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add.s64 %rd21, %rd102, %rd103;
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@%p158 bra $L__BB0_141;
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ld.global.v4.u16 {%rs124, %rs125, %rs126, %rs127}, [%rd21];
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// begin inline asm
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{ cvt.f32.f16 %f1137, %rs124;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1138, %rs125;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1139, %rs126;}
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// end inline asm
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add.f32 %f1140, %f1137, 0f00000000;
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add.f32 %f1141, %f1138, 0f00000000;
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add.f32 %f1142, %f1139, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs123, %f1142;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs122, %f1141;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs121, %f1140;}
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// end inline asm
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mov.u16 %rs128, 0;
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st.global.v4.u16 [%rd21], {%rs121, %rs122, %rs123, %rs128};
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bra.uni $L__BB0_142;
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$L__BB0_5:
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ld.const.u64 %rd28, [params+496];
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cvta.to.global.u64 %rd29, %rd28;
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ld.const.u32 %r64, [params+488];
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mad.lo.s32 %r65, %r64, %r53, %r52;
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mul.wide.u32 %rd30, %r65, 8;
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add.s64 %rd31, %rd29, %rd30;
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ld.global.v4.u16 {%rs28, %rs29, %rs30, %rs31}, [%rd31];
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// begin inline asm
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{ cvt.f32.f16 %f258, %rs28;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f259, %rs29;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f260, %rs30;}
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// end inline asm
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ld.const.u64 %rd32, [params+432];
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cvta.to.global.u64 %rd33, %rd32;
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ld.const.u32 %r66, [params+424];
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mad.lo.s32 %r67, %r66, %r53, %r52;
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mul.wide.u32 %rd34, %r67, 12;
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add.s64 %rd35, %rd33, %rd34;
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ld.global.f32 %f262, [%rd35];
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mul.f32 %f263, %f262, 0f3456BF95;
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ld.global.f32 %f264, [%rd35+4];
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mul.f32 %f265, %f264, 0f3456BF95;
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ld.global.f32 %f266, [%rd35+8];
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mul.f32 %f267, %f266, 0f3456BF95;
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abs.f32 %f268, %f1193;
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div.rn.f32 %f269, %f263, %f268;
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abs.f32 %f270, %f1194;
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div.rn.f32 %f271, %f265, %f270;
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abs.f32 %f272, %f1195;
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div.rn.f32 %f273, %f267, %f272;
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abs.f32 %f274, %f269;
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abs.f32 %f275, %f271;
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abs.f32 %f276, %f273;
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mov.f32 %f277, 0f38D1B717;
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max.f32 %f278, %f274, %f277;
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max.f32 %f279, %f275, %f277;
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max.f32 %f280, %f276, %f277;
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fma.rn.f32 %f13, %f1193, %f278, %f262;
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fma.rn.f32 %f14, %f1194, %f279, %f264;
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fma.rn.f32 %f15, %f1195, %f280, %f266;
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setp.gt.f32 %p14, %f268, %f272;
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neg.f32 %f281, %f1194;
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selp.f32 %f282, %f281, 0f00000000, %p14;
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neg.f32 %f283, %f1195;
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selp.f32 %f284, %f1193, %f283, %p14;
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selp.f32 %f285, 0f00000000, %f1194, %p14;
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mul.f32 %f286, %f284, %f284;
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fma.rn.f32 %f287, %f282, %f282, %f286;
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fma.rn.f32 %f288, %f285, %f285, %f287;
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sqrt.rn.f32 %f289, %f288;
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rcp.rn.f32 %f290, %f289;
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mul.f32 %f16, %f282, %f290;
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mul.f32 %f17, %f284, %f290;
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mul.f32 %f18, %f285, %f290;
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ld.const.u64 %rd36, [params+128];
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cvta.to.global.u64 %rd37, %rd36;
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ld.const.u32 %r68, [params+120];
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mad.lo.s32 %r69, %r68, %r53, %r52;
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mul.wide.u32 %rd38, %r69, 4;
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add.s64 %rd39, %rd37, %rd38;
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ld.global.u32 %r353, [%rd39];
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ld.const.u64 %rd40, [params+464];
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cvta.to.global.u64 %rd41, %rd40;
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ld.const.u32 %r70, [params+456];
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mad.lo.s32 %r71, %r70, %r53, %r52;
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mul.wide.u32 %rd42, %r71, 4;
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add.s64 %rd3, %rd41, %rd42;
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ld.global.v2.u8 {%rs32, %rs167}, [%rd3];
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or.b16 %rs34, %rs32, %rs167;
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and.b16 %rs35, %rs34, 255;
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setp.eq.s16 %p15, %rs35, 0;
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@%p15 bra $L__BB0_7;
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ld.global.u8 %rs165, [%rd3+2];
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bra.uni $L__BB0_8;
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$L__BB0_141:
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mov.f32 %f1145, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs131, %f1145;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs130, %f1145;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs129, %f1145;}
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// end inline asm
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mov.u16 %rs132, 0;
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st.global.v4.u16 [%rd21], {%rs129, %rs130, %rs131, %rs132};
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$L__BB0_142:
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ld.const.u64 %rd104, [params+272];
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cvta.to.global.u64 %rd105, %rd104;
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ld.const.u32 %r326, [params+264];
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mad.lo.s32 %r327, %r326, %r5, %r4;
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mul.wide.u32 %rd106, %r327, 8;
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add.s64 %rd22, %rd105, %rd106;
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@%p158 bra $L__BB0_144;
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ld.global.v4.u16 {%rs139, %rs140, %rs141, %rs142}, [%rd22];
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// begin inline asm
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{ cvt.f32.f16 %f1146, %rs139;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1147, %rs140;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1148, %rs141;}
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// end inline asm
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add.f32 %f1149, %f1146, 0f00000000;
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add.f32 %f1150, %f1147, 0f00000000;
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add.f32 %f1151, %f1148, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs138, %f1151;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs137, %f1150;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs136, %f1149;}
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// end inline asm
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mov.u16 %rs143, 0;
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st.global.v4.u16 [%rd22], {%rs136, %rs137, %rs138, %rs143};
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bra.uni $L__BB0_145;
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$L__BB0_7:
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ld.global.u8 %rs165, [%rd3+2];
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setp.eq.s16 %p16, %rs165, 0;
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mov.f32 %f1196, 0f00000000;
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mov.u16 %rs167, 0;
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mov.u16 %rs168, %rs167;
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mov.f32 %f1197, %f1196;
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mov.f32 %f1198, %f1196;
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@%p16 bra $L__BB0_9;
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$L__BB0_8:
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mov.u16 %rs168, %rs167;
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cvt.rn.f32.u16 %f294, %rs32;
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div.rn.f32 %f295, %f294, 0f437F0000;
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fma.rn.f32 %f296, %f295, 0f40000000, 0fBF800000;
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and.b16 %rs40, %rs168, 255;
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cvt.rn.f32.u16 %f297, %rs40;
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div.rn.f32 %f298, %f297, 0f437F0000;
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fma.rn.f32 %f299, %f298, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f300, %rs165;
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div.rn.f32 %f301, %f300, 0f437F0000;
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fma.rn.f32 %f302, %f301, 0f40000000, 0fBF800000;
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mul.f32 %f303, %f299, %f299;
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fma.rn.f32 %f304, %f296, %f296, %f303;
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fma.rn.f32 %f305, %f302, %f302, %f304;
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sqrt.rn.f32 %f306, %f305;
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rcp.rn.f32 %f307, %f306;
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mul.f32 %f1198, %f307, %f302;
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mul.f32 %f1197, %f307, %f299;
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mul.f32 %f1196, %f296, %f307;
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mov.u16 %rs167, %rs165;
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$L__BB0_9:
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mul.f32 %f311, %f1194, %f1198;
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mul.f32 %f312, %f1195, %f1197;
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sub.f32 %f313, %f311, %f312;
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mul.f32 %f314, %f1195, %f1196;
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mul.f32 %f315, %f1193, %f1198;
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sub.f32 %f316, %f314, %f315;
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mul.f32 %f317, %f1193, %f1197;
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mul.f32 %f318, %f1194, %f1196;
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sub.f32 %f319, %f317, %f318;
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ld.global.u8 %rs42, [%rd3+3];
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setp.eq.s16 %p17, %rs42, 0;
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selp.f32 %f25, 0fBF800000, 0f3F800000, %p17;
|
|
mul.f32 %f320, %f313, %f25;
|
|
mul.f32 %f321, %f316, %f25;
|
|
mul.f32 %f322, %f319, %f25;
|
|
mul.f32 %f323, %f320, 0f00000000;
|
|
mul.f32 %f324, %f321, 0f00000000;
|
|
mul.f32 %f325, %f322, 0f00000000;
|
|
fma.rn.f32 %f326, %f1196, 0f3F5105EC, %f323;
|
|
fma.rn.f32 %f327, %f1197, 0f3F5105EC, %f324;
|
|
fma.rn.f32 %f328, %f1198, 0f3F5105EC, %f325;
|
|
mul.f32 %f26, %f1193, 0f3F13CD3A;
|
|
add.f32 %f27, %f26, %f326;
|
|
mul.f32 %f28, %f1194, 0f3F13CD3A;
|
|
add.f32 %f29, %f28, %f327;
|
|
mul.f32 %f30, %f1195, 0f3F13CD3A;
|
|
add.f32 %f31, %f30, %f328;
|
|
or.b16 %rs43, %rs32, %rs168;
|
|
or.b16 %rs15, %rs43, %rs167;
|
|
and.b16 %rs44, %rs15, 255;
|
|
setp.eq.s16 %p18, %rs44, 0;
|
|
mov.f32 %f1202, 0f00000000;
|
|
mov.f32 %f1199, %f1202;
|
|
mov.f32 %f1200, %f1202;
|
|
mov.f32 %f1201, %f1202;
|
|
@%p18 bra $L__BB0_11;
|
|
|
|
cvt.rn.f32.u16 %f329, %rs32;
|
|
div.rn.f32 %f330, %f329, 0f437F0000;
|
|
fma.rn.f32 %f331, %f330, 0f40000000, 0fBF800000;
|
|
and.b16 %rs46, %rs168, 255;
|
|
cvt.rn.f32.u16 %f332, %rs46;
|
|
div.rn.f32 %f333, %f332, 0f437F0000;
|
|
fma.rn.f32 %f334, %f333, 0f40000000, 0fBF800000;
|
|
and.b16 %rs47, %rs167, 255;
|
|
cvt.rn.f32.u16 %f335, %rs47;
|
|
div.rn.f32 %f336, %f335, 0f437F0000;
|
|
fma.rn.f32 %f337, %f336, 0f40000000, 0fBF800000;
|
|
mul.f32 %f338, %f334, %f334;
|
|
fma.rn.f32 %f339, %f331, %f331, %f338;
|
|
fma.rn.f32 %f340, %f337, %f337, %f339;
|
|
sqrt.rn.f32 %f341, %f340;
|
|
rcp.rn.f32 %f342, %f341;
|
|
mul.f32 %f1201, %f342, %f337;
|
|
mul.f32 %f1200, %f342, %f334;
|
|
mul.f32 %f1199, %f331, %f342;
|
|
|
|
$L__BB0_11:
|
|
mul.f32 %f346, %f1194, %f1201;
|
|
mul.f32 %f347, %f1195, %f1200;
|
|
sub.f32 %f348, %f346, %f347;
|
|
mul.f32 %f349, %f1195, %f1199;
|
|
mul.f32 %f350, %f1193, %f1201;
|
|
sub.f32 %f351, %f349, %f350;
|
|
mul.f32 %f352, %f1193, %f1200;
|
|
mul.f32 %f353, %f1194, %f1199;
|
|
sub.f32 %f354, %f352, %f353;
|
|
mul.f32 %f355, %f348, %f25;
|
|
mul.f32 %f356, %f351, %f25;
|
|
mul.f32 %f357, %f354, %f25;
|
|
mul.f32 %f358, %f1199, 0f3ED105EC;
|
|
mul.f32 %f359, %f1200, 0f3ED105EC;
|
|
mul.f32 %f360, %f1201, 0f3ED105EC;
|
|
mul.f32 %f361, %f355, 0f3F3504F3;
|
|
mul.f32 %f362, %f356, 0f3F3504F3;
|
|
mul.f32 %f363, %f357, 0f3F3504F3;
|
|
sub.f32 %f364, %f361, %f358;
|
|
sub.f32 %f365, %f362, %f359;
|
|
sub.f32 %f366, %f363, %f360;
|
|
add.f32 %f38, %f26, %f364;
|
|
add.f32 %f39, %f28, %f365;
|
|
add.f32 %f40, %f30, %f366;
|
|
mov.f32 %f1203, %f1202;
|
|
mov.f32 %f1204, %f1202;
|
|
@%p18 bra $L__BB0_13;
|
|
|
|
cvt.rn.f32.u16 %f367, %rs32;
|
|
div.rn.f32 %f368, %f367, 0f437F0000;
|
|
fma.rn.f32 %f369, %f368, 0f40000000, 0fBF800000;
|
|
and.b16 %rs50, %rs168, 255;
|
|
cvt.rn.f32.u16 %f370, %rs50;
|
|
div.rn.f32 %f371, %f370, 0f437F0000;
|
|
fma.rn.f32 %f372, %f371, 0f40000000, 0fBF800000;
|
|
and.b16 %rs51, %rs167, 255;
|
|
cvt.rn.f32.u16 %f373, %rs51;
|
|
div.rn.f32 %f374, %f373, 0f437F0000;
|
|
fma.rn.f32 %f375, %f374, 0f40000000, 0fBF800000;
|
|
mul.f32 %f376, %f372, %f372;
|
|
fma.rn.f32 %f377, %f369, %f369, %f376;
|
|
fma.rn.f32 %f378, %f375, %f375, %f377;
|
|
sqrt.rn.f32 %f379, %f378;
|
|
rcp.rn.f32 %f380, %f379;
|
|
mul.f32 %f1204, %f380, %f375;
|
|
mul.f32 %f1203, %f380, %f372;
|
|
mul.f32 %f1202, %f369, %f380;
|
|
|
|
$L__BB0_13:
|
|
mul.f32 %f393, %f1194, %f1204;
|
|
mul.f32 %f394, %f1195, %f1203;
|
|
sub.f32 %f395, %f393, %f394;
|
|
mul.f32 %f396, %f1195, %f1202;
|
|
mul.f32 %f397, %f1193, %f1204;
|
|
sub.f32 %f398, %f396, %f397;
|
|
mul.f32 %f399, %f1193, %f1203;
|
|
mul.f32 %f400, %f1194, %f1202;
|
|
sub.f32 %f401, %f399, %f400;
|
|
mul.f32 %f402, %f395, %f25;
|
|
mul.f32 %f403, %f398, %f25;
|
|
mul.f32 %f404, %f401, %f25;
|
|
mul.f32 %f405, %f1202, 0f3ED105EC;
|
|
mul.f32 %f406, %f1203, 0f3ED105EC;
|
|
mul.f32 %f407, %f1204, 0f3ED105EC;
|
|
mul.f32 %f408, %f402, 0fBF3504F3;
|
|
mul.f32 %f409, %f403, 0fBF3504F3;
|
|
mul.f32 %f410, %f404, 0fBF3504F3;
|
|
sub.f32 %f411, %f408, %f405;
|
|
sub.f32 %f412, %f409, %f406;
|
|
sub.f32 %f413, %f410, %f407;
|
|
add.f32 %f47, %f26, %f411;
|
|
add.f32 %f48, %f28, %f412;
|
|
add.f32 %f49, %f30, %f413;
|
|
setp.lt.s32 %p20, %r3, 1;
|
|
mov.f32 %f1228, 0f00000000;
|
|
mov.f32 %f1227, %f1228;
|
|
mov.f32 %f1226, %f1228;
|
|
mov.f32 %f1225, %f1228;
|
|
mov.f32 %f1224, %f1228;
|
|
mov.f32 %f1223, %f1228;
|
|
mov.f32 %f1222, %f1228;
|
|
mov.f32 %f1221, %f1228;
|
|
mov.f32 %f1220, %f1228;
|
|
mov.f32 %f1219, %f1228;
|
|
mov.f32 %f1218, %f1228;
|
|
mov.f32 %f1217, %f1228;
|
|
@%p20 bra $L__BB0_42;
|
|
|
|
cvt.rn.f32.s32 %f426, %r3;
|
|
rcp.rn.f32 %f50, %f426;
|
|
mul.f32 %f51, %f13, 0f3456BF95;
|
|
mul.f32 %f52, %f14, 0f3456BF95;
|
|
mul.f32 %f53, %f15, 0f3456BF95;
|
|
ld.const.u64 %rd4, [params+96];
|
|
mul.f32 %f427, %f1195, %f17;
|
|
mul.f32 %f428, %f1194, %f18;
|
|
sub.f32 %f54, %f427, %f428;
|
|
mul.f32 %f429, %f1193, %f18;
|
|
mul.f32 %f430, %f1195, %f16;
|
|
sub.f32 %f55, %f429, %f430;
|
|
mul.f32 %f431, %f1194, %f16;
|
|
mul.f32 %f432, %f1193, %f17;
|
|
sub.f32 %f56, %f431, %f432;
|
|
mov.u32 %r72, 0;
|
|
add.s64 %rd5, %rd1, 24;
|
|
mov.u64 %rd43, __cudart_i2opi_f;
|
|
abs.f32 %f495, %f52;
|
|
abs.f32 %f496, %f51;
|
|
max.f32 %f497, %f496, %f495;
|
|
abs.f32 %f498, %f53;
|
|
max.f32 %f499, %f497, %f498;
|
|
mov.u32 %r350, %r72;
|
|
|
|
$L__BB0_15:
|
|
mov.u32 %r352, %r72;
|
|
|
|
$L__BB0_16:
|
|
cvt.rn.f32.s32 %f1170, %r350;
|
|
mad.lo.s32 %r74, %r353, 1664525, 1013904223;
|
|
and.b32 %r75, %r74, 16777215;
|
|
cvt.rn.f32.u32 %f433, %r75;
|
|
fma.rn.f32 %f434, %f433, 0f33800000, %f1170;
|
|
mul.f32 %f82, %f50, %f434;
|
|
mad.lo.s32 %r353, %r74, 1664525, 1013904223;
|
|
and.b32 %r76, %r353, 16777215;
|
|
cvt.rn.f32.u32 %f435, %r76;
|
|
cvt.rn.f32.s32 %f436, %r352;
|
|
fma.rn.f32 %f437, %f435, 0f33800000, %f436;
|
|
mul.f32 %f438, %f50, %f437;
|
|
mul.f32 %f439, %f82, %f82;
|
|
mov.f32 %f440, 0f3F800000;
|
|
sub.f32 %f441, %f440, %f439;
|
|
mov.f32 %f442, 0f00000000;
|
|
max.f32 %f443, %f442, %f441;
|
|
sqrt.rn.f32 %f83, %f443;
|
|
mul.f32 %f84, %f438, 0f40C90FDB;
|
|
mul.f32 %f444, %f84, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r357, %f444;
|
|
cvt.rn.f32.s32 %f445, %r357;
|
|
mov.f32 %f446, 0fBFC90FDA;
|
|
fma.rn.f32 %f447, %f445, %f446, %f84;
|
|
mov.f32 %f448, 0fB3A22168;
|
|
fma.rn.f32 %f449, %f445, %f448, %f447;
|
|
mov.f32 %f450, 0fA7C234C5;
|
|
fma.rn.f32 %f1232, %f445, %f450, %f449;
|
|
abs.f32 %f86, %f84;
|
|
setp.ltu.f32 %p21, %f86, 0f47CE4780;
|
|
mov.f32 %f1229, %f1232;
|
|
@%p21 bra $L__BB0_24;
|
|
|
|
setp.eq.f32 %p22, %f86, 0f7F800000;
|
|
@%p22 bra $L__BB0_23;
|
|
bra.uni $L__BB0_18;
|
|
|
|
$L__BB0_23:
|
|
mov.f32 %f453, 0f00000000;
|
|
mul.rn.f32 %f1229, %f84, %f453;
|
|
mov.u32 %r357, 0;
|
|
bra.uni $L__BB0_24;
|
|
|
|
$L__BB0_18:
|
|
mov.b32 %r13, %f84;
|
|
bfe.u32 %r78, %r13, 23, 8;
|
|
mov.u64 %rd115, 0;
|
|
mov.u32 %r354, 0;
|
|
mov.u64 %rd113, %rd1;
|
|
mov.u64 %rd114, %rd43;
|
|
|
|
$L__BB0_19:
|
|
.pragma "nounroll";
|
|
mov.b32 %r333, %f84;
|
|
shl.b32 %r332, %r333, 8;
|
|
or.b32 %r331, %r332, -2147483648;
|
|
ld.global.nc.u32 %r80, [%rd114];
|
|
mad.wide.u32 %rd45, %r80, %r331, %rd115;
|
|
shr.u64 %rd115, %rd45, 32;
|
|
st.local.u32 [%rd113], %rd45;
|
|
add.s64 %rd114, %rd114, 4;
|
|
add.s64 %rd113, %rd113, 4;
|
|
add.s32 %r354, %r354, 1;
|
|
setp.ne.s32 %p23, %r354, 6;
|
|
@%p23 bra $L__BB0_19;
|
|
|
|
add.s32 %r338, %r78, -128;
|
|
mov.b32 %r337, %f84;
|
|
bfe.u32 %r336, %r337, 23, 8;
|
|
add.s32 %r335, %r336, -128;
|
|
shr.u32 %r334, %r335, 5;
|
|
st.local.u32 [%rd5], %rd115;
|
|
mov.u32 %r82, 6;
|
|
sub.s32 %r83, %r82, %r334;
|
|
mul.wide.s32 %rd46, %r83, 4;
|
|
add.s64 %rd47, %rd1, %rd46;
|
|
ld.local.u32 %r355, [%rd47];
|
|
ld.local.u32 %r356, [%rd47+-4];
|
|
and.b32 %r22, %r335, 31;
|
|
setp.eq.s32 %p24, %r22, 0;
|
|
@%p24 bra $L__BB0_22;
|
|
|
|
mov.b32 %r345, %f84;
|
|
bfe.u32 %r344, %r345, 23, 8;
|
|
add.s32 %r343, %r344, -128;
|
|
shr.u32 %r342, %r343, 5;
|
|
mov.u32 %r341, 4;
|
|
sub.s32 %r340, %r341, %r342;
|
|
mov.u32 %r84, 32;
|
|
sub.s32 %r85, %r84, %r22;
|
|
shr.u32 %r86, %r356, %r85;
|
|
shl.b32 %r87, %r355, %r22;
|
|
add.s32 %r355, %r86, %r87;
|
|
mul.wide.s32 %rd48, %r340, 4;
|
|
add.s64 %rd49, %rd1, %rd48;
|
|
ld.local.u32 %r88, [%rd49];
|
|
shr.u32 %r89, %r88, %r85;
|
|
shl.b32 %r90, %r356, %r22;
|
|
add.s32 %r356, %r89, %r90;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r339, %f84;
|
|
and.b32 %r91, %r339, -2147483648;
|
|
shr.u32 %r92, %r356, 30;
|
|
shl.b32 %r93, %r355, 2;
|
|
or.b32 %r94, %r92, %r93;
|
|
shr.u32 %r95, %r94, 31;
|
|
shr.u32 %r96, %r355, 30;
|
|
add.s32 %r97, %r95, %r96;
|
|
neg.s32 %r98, %r97;
|
|
setp.eq.s32 %p25, %r91, 0;
|
|
selp.b32 %r357, %r97, %r98, %p25;
|
|
setp.ne.s32 %p26, %r95, 0;
|
|
xor.b32 %r99, %r91, -2147483648;
|
|
selp.b32 %r100, %r99, %r91, %p26;
|
|
selp.b32 %r101, -1, 0, %p26;
|
|
xor.b32 %r102, %r94, %r101;
|
|
shl.b32 %r103, %r356, 2;
|
|
xor.b32 %r104, %r103, %r101;
|
|
cvt.u64.u32 %rd50, %r102;
|
|
cvt.u64.u32 %rd51, %r104;
|
|
bfi.b64 %rd52, %rd50, %rd51, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd52;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f451, %fd2;
|
|
setp.eq.s32 %p27, %r100, 0;
|
|
neg.f32 %f452, %f451;
|
|
selp.f32 %f1229, %f451, %f452, %p27;
|
|
|
|
$L__BB0_24:
|
|
add.s32 %r29, %r357, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p28, %r30, 0;
|
|
selp.f32 %f90, %f1229, 0f3F800000, %p28;
|
|
mul.rn.f32 %f91, %f1229, %f1229;
|
|
mov.f32 %f1230, 0fB94D4153;
|
|
@%p28 bra $L__BB0_26;
|
|
|
|
mov.f32 %f455, 0fBAB607ED;
|
|
mov.f32 %f456, 0f37CBAC00;
|
|
fma.rn.f32 %f1230, %f456, %f91, %f455;
|
|
|
|
$L__BB0_26:
|
|
selp.f32 %f457, 0f3C0885E4, 0f3D2AAABB, %p28;
|
|
fma.rn.f32 %f458, %f1230, %f91, %f457;
|
|
selp.f32 %f459, 0fBE2AAAA8, 0fBEFFFFFF, %p28;
|
|
fma.rn.f32 %f460, %f458, %f91, %f459;
|
|
mov.f32 %f461, 0f00000000;
|
|
fma.rn.f32 %f462, %f91, %f90, %f461;
|
|
fma.rn.f32 %f1231, %f460, %f462, %f90;
|
|
and.b32 %r106, %r29, 2;
|
|
setp.eq.s32 %p30, %r106, 0;
|
|
@%p30 bra $L__BB0_28;
|
|
|
|
mov.f32 %f464, 0fBF800000;
|
|
fma.rn.f32 %f1231, %f1231, %f464, %f461;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f1171, %f84, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r360, %f1171;
|
|
setp.ltu.f32 %p161, %f86, 0f47CE4780;
|
|
@%p161 bra $L__BB0_36;
|
|
|
|
setp.eq.f32 %p32, %f86, 0f7F800000;
|
|
@%p32 bra $L__BB0_35;
|
|
bra.uni $L__BB0_30;
|
|
|
|
$L__BB0_35:
|
|
mov.f32 %f467, 0f00000000;
|
|
mul.rn.f32 %f1232, %f84, %f467;
|
|
mov.u32 %r360, 0;
|
|
bra.uni $L__BB0_36;
|
|
|
|
$L__BB0_30:
|
|
mov.b32 %r31, %f84;
|
|
bfe.u32 %r107, %r31, 23, 8;
|
|
add.s32 %r32, %r107, -128;
|
|
shl.b32 %r108, %r31, 8;
|
|
or.b32 %r33, %r108, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd116, 0;
|
|
mov.u64 %rd117, %rd116;
|
|
|
|
$L__BB0_31:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd55, %rd116, 2;
|
|
mov.u64 %rd56, __cudart_i2opi_f;
|
|
add.s64 %rd57, %rd56, %rd55;
|
|
ld.global.nc.u32 %r109, [%rd57];
|
|
mad.wide.u32 %rd58, %r109, %r33, %rd117;
|
|
shr.u64 %rd117, %rd58, 32;
|
|
add.s64 %rd59, %rd1, %rd55;
|
|
st.local.u32 [%rd59], %rd58;
|
|
cvt.u32.u64 %r110, %rd116;
|
|
add.s32 %r111, %r110, 1;
|
|
cvt.s64.s32 %rd116, %r111;
|
|
setp.ne.s32 %p33, %r111, 6;
|
|
@%p33 bra $L__BB0_31;
|
|
|
|
st.local.u32 [%rd5], %rd117;
|
|
mov.u32 %r112, 4;
|
|
sub.s32 %r35, %r112, %r34;
|
|
mov.u32 %r113, 6;
|
|
sub.s32 %r114, %r113, %r34;
|
|
mul.wide.s32 %rd60, %r114, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r358, [%rd61];
|
|
ld.local.u32 %r359, [%rd61+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p34, %r38, 0;
|
|
@%p34 bra $L__BB0_34;
|
|
|
|
mov.u32 %r115, 32;
|
|
sub.s32 %r116, %r115, %r38;
|
|
shr.u32 %r117, %r359, %r116;
|
|
shl.b32 %r118, %r358, %r38;
|
|
add.s32 %r358, %r117, %r118;
|
|
mul.wide.s32 %rd62, %r35, 4;
|
|
add.s64 %rd63, %rd1, %rd62;
|
|
ld.local.u32 %r119, [%rd63];
|
|
shr.u32 %r120, %r119, %r116;
|
|
shl.b32 %r121, %r359, %r38;
|
|
add.s32 %r359, %r120, %r121;
|
|
|
|
$L__BB0_34:
|
|
and.b32 %r122, %r31, -2147483648;
|
|
shr.u32 %r123, %r359, 30;
|
|
shl.b32 %r124, %r358, 2;
|
|
or.b32 %r125, %r123, %r124;
|
|
shr.u32 %r126, %r125, 31;
|
|
shr.u32 %r127, %r358, 30;
|
|
add.s32 %r128, %r126, %r127;
|
|
neg.s32 %r129, %r128;
|
|
setp.eq.s32 %p35, %r122, 0;
|
|
selp.b32 %r360, %r128, %r129, %p35;
|
|
setp.ne.s32 %p36, %r126, 0;
|
|
xor.b32 %r130, %r122, -2147483648;
|
|
selp.b32 %r131, %r130, %r122, %p36;
|
|
selp.b32 %r132, -1, 0, %p36;
|
|
xor.b32 %r133, %r125, %r132;
|
|
shl.b32 %r134, %r359, 2;
|
|
xor.b32 %r135, %r134, %r132;
|
|
cvt.u64.u32 %rd64, %r133;
|
|
cvt.u64.u32 %rd65, %r135;
|
|
bfi.b64 %rd66, %rd64, %rd65, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd66;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f465, %fd4;
|
|
setp.eq.s32 %p37, %r131, 0;
|
|
neg.f32 %f466, %f465;
|
|
selp.f32 %f1232, %f465, %f466, %p37;
|
|
|
|
$L__BB0_36:
|
|
mul.f32 %f100, %f83, %f1231;
|
|
and.b32 %r45, %r360, 1;
|
|
setp.eq.s32 %p38, %r45, 0;
|
|
selp.f32 %f101, %f1232, 0f3F800000, %p38;
|
|
mul.rn.f32 %f102, %f1232, %f1232;
|
|
mov.f32 %f1233, 0fB94D4153;
|
|
@%p38 bra $L__BB0_38;
|
|
|
|
mov.f32 %f469, 0fBAB607ED;
|
|
mov.f32 %f470, 0f37CBAC00;
|
|
fma.rn.f32 %f1233, %f470, %f102, %f469;
|
|
|
|
$L__BB0_38:
|
|
selp.f32 %f471, 0f3C0885E4, 0f3D2AAABB, %p38;
|
|
fma.rn.f32 %f472, %f1233, %f102, %f471;
|
|
selp.f32 %f473, 0fBE2AAAA8, 0fBEFFFFFF, %p38;
|
|
fma.rn.f32 %f474, %f472, %f102, %f473;
|
|
mov.f32 %f475, 0f00000000;
|
|
fma.rn.f32 %f476, %f102, %f101, %f475;
|
|
fma.rn.f32 %f1234, %f474, %f476, %f101;
|
|
and.b32 %r137, %r360, 2;
|
|
setp.eq.s32 %p40, %r137, 0;
|
|
@%p40 bra $L__BB0_40;
|
|
|
|
mov.f32 %f478, 0fBF800000;
|
|
fma.rn.f32 %f1234, %f1234, %f478, %f475;
|
|
|
|
$L__BB0_40:
|
|
mul.f32 %f488, %f83, %f1234;
|
|
mul.f32 %f489, %f16, %f488;
|
|
mul.f32 %f490, %f17, %f488;
|
|
mul.f32 %f491, %f18, %f488;
|
|
fma.rn.f32 %f492, %f54, %f100, %f489;
|
|
fma.rn.f32 %f493, %f55, %f100, %f490;
|
|
fma.rn.f32 %f494, %f56, %f100, %f491;
|
|
fma.rn.f32 %f482, %f1193, %f82, %f492;
|
|
fma.rn.f32 %f483, %f1194, %f82, %f493;
|
|
fma.rn.f32 %f484, %f1195, %f82, %f494;
|
|
mov.f32 %f500, 0f38D1B717;
|
|
max.f32 %f485, %f499, %f500;
|
|
mov.f32 %f486, 0f6C4ECB8F;
|
|
mov.u32 %r171, 1;
|
|
mov.u32 %r174, 2;
|
|
mov.u32 %r176, 4;
|
|
mov.u32 %r179, 1065353216;
|
|
mov.u32 %r180, 2139095039;
|
|
mov.u32 %r208, 0;
|
|
// begin inline asm
|
|
call(%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169),_optix_trace_typed_32,(%r208,%rd4,%f13,%f14,%f15,%f482,%f483,%f484,%f485,%f486,%f475,%r171,%r208,%r208,%r174,%r208,%r176,%r179,%r179,%r179,%r180,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208,%r208);
|
|
// end inline asm
|
|
mov.b32 %f501, %r138;
|
|
mov.b32 %f502, %r139;
|
|
mov.b32 %f503, %r140;
|
|
mov.b32 %f504, %r141;
|
|
setp.ltu.f32 %p41, %f504, 0f00000000;
|
|
selp.f32 %f505, %f503, 0f00000000, %p41;
|
|
selp.f32 %f506, %f502, 0f00000000, %p41;
|
|
selp.f32 %f507, %f501, 0f00000000, %p41;
|
|
mul.f32 %f508, %f29, %f483;
|
|
fma.rn.f32 %f509, %f27, %f482, %f508;
|
|
fma.rn.f32 %f510, %f31, %f484, %f509;
|
|
cvt.sat.f32.f32 %f511, %f510;
|
|
fma.rn.f32 %f1222, %f511, %f507, %f1222;
|
|
fma.rn.f32 %f1221, %f511, %f506, %f1221;
|
|
fma.rn.f32 %f1220, %f511, %f505, %f1220;
|
|
mul.f32 %f512, %f39, %f483;
|
|
fma.rn.f32 %f513, %f38, %f482, %f512;
|
|
fma.rn.f32 %f514, %f40, %f484, %f513;
|
|
cvt.sat.f32.f32 %f515, %f514;
|
|
fma.rn.f32 %f1225, %f515, %f507, %f1225;
|
|
fma.rn.f32 %f1224, %f515, %f506, %f1224;
|
|
fma.rn.f32 %f1223, %f515, %f505, %f1223;
|
|
mul.f32 %f516, %f48, %f483;
|
|
fma.rn.f32 %f517, %f47, %f482, %f516;
|
|
fma.rn.f32 %f518, %f49, %f484, %f517;
|
|
cvt.sat.f32.f32 %f519, %f518;
|
|
fma.rn.f32 %f1228, %f519, %f507, %f1228;
|
|
fma.rn.f32 %f1227, %f519, %f506, %f1227;
|
|
fma.rn.f32 %f1226, %f519, %f505, %f1226;
|
|
mul.f32 %f520, %f1194, %f483;
|
|
fma.rn.f32 %f521, %f1193, %f482, %f520;
|
|
fma.rn.f32 %f522, %f1195, %f484, %f521;
|
|
cvt.sat.f32.f32 %f523, %f522;
|
|
fma.rn.f32 %f1219, %f507, %f523, %f1219;
|
|
fma.rn.f32 %f1218, %f506, %f523, %f1218;
|
|
fma.rn.f32 %f1217, %f505, %f523, %f1217;
|
|
add.s32 %r352, %r352, 1;
|
|
setp.lt.s32 %p42, %r352, %r3;
|
|
@%p42 bra $L__BB0_16;
|
|
|
|
add.s32 %r350, %r350, 1;
|
|
setp.lt.s32 %p43, %r350, %r3;
|
|
@%p43 bra $L__BB0_15;
|
|
|
|
$L__BB0_42:
|
|
mov.f32 %f1247, 0f00000000;
|
|
mul.lo.s32 %r209, %r3, %r3;
|
|
cvt.rn.f32.s32 %f527, %r209;
|
|
rcp.rn.f32 %f528, %f527;
|
|
mul.f32 %f529, %f528, %f1219;
|
|
mul.f32 %f530, %f528, %f1218;
|
|
mul.f32 %f531, %f528, %f1217;
|
|
mul.f32 %f132, %f528, %f1222;
|
|
mul.f32 %f133, %f528, %f1221;
|
|
mul.f32 %f134, %f528, %f1220;
|
|
mul.f32 %f135, %f528, %f1225;
|
|
mul.f32 %f136, %f528, %f1224;
|
|
mul.f32 %f137, %f528, %f1223;
|
|
mul.f32 %f138, %f528, %f1228;
|
|
mul.f32 %f139, %f528, %f1227;
|
|
mul.f32 %f140, %f528, %f1226;
|
|
fma.rn.f32 %f141, %f528, %f1219, %f529;
|
|
fma.rn.f32 %f142, %f528, %f1218, %f530;
|
|
fma.rn.f32 %f143, %f528, %f1217, %f531;
|
|
ld.const.u64 %rd68, [params+504];
|
|
cvt.rn.f32.u32 %f532, %r5;
|
|
cvt.rn.f32.u32 %f533, %r4;
|
|
tex.2d.v4.f32.f32 {%f534, %f535, %f536, %f537}, [%rd68, {%f533, %f532}];
|
|
mul.f32 %f144, %f141, %f534;
|
|
mul.f32 %f145, %f142, %f535;
|
|
mul.f32 %f146, %f143, %f536;
|
|
add.f32 %f147, %f258, %f144;
|
|
add.f32 %f148, %f259, %f145;
|
|
add.f32 %f149, %f260, %f146;
|
|
abs.f32 %f538, %f147;
|
|
setp.gtu.f32 %p44, %f538, 0f7F800000;
|
|
mov.f32 %f1248, %f1247;
|
|
mov.f32 %f1249, %f1247;
|
|
@%p44 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1247, 0f00000000;
|
|
abs.f32 %f542, %f148;
|
|
setp.gtu.f32 %p45, %f542, 0f7F800000;
|
|
@%p45 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1247, 0f00000000;
|
|
abs.f32 %f546, %f149;
|
|
setp.gtu.f32 %p46, %f546, 0f7F800000;
|
|
mov.f32 %f1248, %f1247;
|
|
mov.f32 %f1249, %f1247;
|
|
@%p46 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1247, %f147;
|
|
mov.f32 %f1248, %f148;
|
|
mov.f32 %f1249, %f149;
|
|
|
|
$L__BB0_46:
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r210, %r48, 1;
|
|
setp.eq.b32 %p47, %r210, 1;
|
|
mov.pred %p48, 0;
|
|
xor.pred %p49, %p47, %p48;
|
|
not.pred %p50, %p49;
|
|
@%p50 bra $L__BB0_120;
|
|
|
|
mov.f32 %f551, 0f3EE66666;
|
|
abs.f32 %f160, %f1247;
|
|
setp.lt.f32 %p51, %f160, 0f00800000;
|
|
mul.f32 %f553, %f160, 0f4B800000;
|
|
selp.f32 %f554, %f553, %f160, %p51;
|
|
selp.f32 %f555, 0fC3170000, 0fC2FE0000, %p51;
|
|
mov.b32 %r211, %f554;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f556, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f557, %r214;
|
|
add.f32 %f558, %f555, %f557;
|
|
setp.gt.f32 %p52, %f556, 0f3FB504F3;
|
|
mul.f32 %f559, %f556, 0f3F000000;
|
|
add.f32 %f560, %f558, 0f3F800000;
|
|
selp.f32 %f561, %f560, %f558, %p52;
|
|
selp.f32 %f562, %f559, %f556, %p52;
|
|
add.f32 %f563, %f562, 0fBF800000;
|
|
add.f32 %f564, %f562, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f565, %f564;
|
|
add.f32 %f566, %f563, %f563;
|
|
mul.f32 %f567, %f566, %f565;
|
|
mul.f32 %f568, %f567, %f567;
|
|
mov.f32 %f569, 0f3C4CAF63;
|
|
mov.f32 %f570, 0f3B18F0FE;
|
|
fma.rn.f32 %f571, %f570, %f568, %f569;
|
|
mov.f32 %f572, 0f3DAAAABD;
|
|
fma.rn.f32 %f573, %f571, %f568, %f572;
|
|
mul.rn.f32 %f574, %f573, %f568;
|
|
mul.rn.f32 %f575, %f574, %f567;
|
|
sub.f32 %f576, %f563, %f567;
|
|
add.f32 %f577, %f576, %f576;
|
|
neg.f32 %f578, %f567;
|
|
fma.rn.f32 %f579, %f578, %f563, %f577;
|
|
mul.rn.f32 %f580, %f565, %f579;
|
|
add.f32 %f581, %f575, %f567;
|
|
sub.f32 %f582, %f567, %f581;
|
|
add.f32 %f583, %f575, %f582;
|
|
add.f32 %f584, %f580, %f583;
|
|
add.f32 %f585, %f581, %f584;
|
|
sub.f32 %f586, %f581, %f585;
|
|
add.f32 %f587, %f584, %f586;
|
|
mov.f32 %f588, 0f3F317200;
|
|
mul.rn.f32 %f589, %f561, %f588;
|
|
mov.f32 %f590, 0f35BFBE8E;
|
|
mul.rn.f32 %f591, %f561, %f590;
|
|
add.f32 %f592, %f589, %f585;
|
|
sub.f32 %f593, %f589, %f592;
|
|
add.f32 %f594, %f585, %f593;
|
|
add.f32 %f595, %f587, %f594;
|
|
add.f32 %f596, %f591, %f595;
|
|
add.f32 %f597, %f592, %f596;
|
|
sub.f32 %f598, %f592, %f597;
|
|
add.f32 %f599, %f596, %f598;
|
|
mul.rn.f32 %f600, %f551, %f597;
|
|
neg.f32 %f601, %f600;
|
|
fma.rn.f32 %f602, %f551, %f597, %f601;
|
|
fma.rn.f32 %f603, %f551, %f599, %f602;
|
|
mov.f32 %f604, 0f00000000;
|
|
fma.rn.f32 %f605, %f604, %f597, %f603;
|
|
add.rn.f32 %f606, %f600, %f605;
|
|
neg.f32 %f607, %f606;
|
|
add.rn.f32 %f608, %f600, %f607;
|
|
add.rn.f32 %f609, %f608, %f605;
|
|
mov.b32 %r215, %f606;
|
|
setp.eq.s32 %p53, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f610, %r216;
|
|
add.f32 %f611, %f609, 0f37000000;
|
|
selp.f32 %f161, %f611, %f609, %p53;
|
|
selp.f32 %f612, %f610, %f606, %p53;
|
|
mov.f32 %f613, 0f3FB8AA3B;
|
|
mul.rn.f32 %f614, %f612, %f613;
|
|
cvt.rzi.f32.f32 %f615, %f614;
|
|
abs.f32 %f616, %f615;
|
|
setp.gt.f32 %p54, %f616, 0f42FC0000;
|
|
mov.b32 %r217, %f615;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f617, %r219;
|
|
selp.f32 %f618, %f617, %f615, %p54;
|
|
mov.f32 %f619, 0fBF317218;
|
|
fma.rn.f32 %f620, %f618, %f619, %f612;
|
|
mov.f32 %f621, 0f3102E308;
|
|
fma.rn.f32 %f622, %f618, %f621, %f620;
|
|
mul.f32 %f623, %f622, 0f3FB8AA3B;
|
|
add.f32 %f624, %f618, 0f4B40007F;
|
|
mov.b32 %r220, %f624;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f625, %r221;
|
|
ex2.approx.ftz.f32 %f626, %f623;
|
|
mul.f32 %f162, %f626, %f625;
|
|
setp.eq.f32 %p55, %f162, 0f7F800000;
|
|
mov.f32 %f1250, 0f7F800000;
|
|
@%p55 bra $L__BB0_49;
|
|
|
|
fma.rn.f32 %f1250, %f162, %f161, %f162;
|
|
|
|
$L__BB0_49:
|
|
mov.f32 %f1183, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1182, %f1183;
|
|
add.f32 %f1181, %f1182, %f1182;
|
|
mov.f32 %f1180, 0f3EE66666;
|
|
sub.f32 %f1179, %f1180, %f1181;
|
|
abs.f32 %f1178, %f1179;
|
|
setp.lt.f32 %p56, %f1247, 0f00000000;
|
|
setp.eq.f32 %p57, %f1178, 0f3F800000;
|
|
and.pred %p1, %p56, %p57;
|
|
setp.eq.f32 %p58, %f1247, 0f00000000;
|
|
@%p58 bra $L__BB0_53;
|
|
bra.uni $L__BB0_50;
|
|
|
|
$L__BB0_53:
|
|
add.f32 %f631, %f1247, %f1247;
|
|
selp.f32 %f1252, %f631, 0f00000000, %p57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_144:
|
|
mov.f32 %f1154, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1154;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs147, 0;
|
|
st.global.v4.u16 [%rd22], {%rs144, %rs145, %rs146, %rs147};
|
|
|
|
$L__BB0_145:
|
|
ld.const.u64 %rd107, [params+288];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r328, [params+280];
|
|
mad.lo.s32 %r329, %r328, %r5, %r4;
|
|
mul.wide.u32 %rd109, %r329, 8;
|
|
add.s64 %rd23, %rd108, %rd109;
|
|
@%p158 bra $L__BB0_147;
|
|
|
|
ld.global.v4.u16 {%rs154, %rs155, %rs156, %rs157}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1155, %rs154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1156, %rs155;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1157, %rs156;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1158, %f1155, 0f00000000;
|
|
add.f32 %f1159, %f1156, 0f00000000;
|
|
add.f32 %f1160, %f1157, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1160;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1159;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1158;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs158, 0;
|
|
st.global.v4.u16 [%rd23], {%rs151, %rs152, %rs153, %rs158};
|
|
bra.uni $L__BB0_148;
|
|
|
|
$L__BB0_147:
|
|
mov.f32 %f1163, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1163;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs162, 0;
|
|
st.global.v4.u16 [%rd23], {%rs159, %rs160, %rs161, %rs162};
|
|
bra.uni $L__BB0_148;
|
|
|
|
$L__BB0_50:
|
|
mov.b32 %r222, %f1250;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f627, %r223;
|
|
selp.f32 %f1252, %f627, %f1250, %p1;
|
|
setp.geu.f32 %p59, %f1247, 0f00000000;
|
|
@%p59 bra $L__BB0_54;
|
|
|
|
mov.f32 %f628, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f629, %f628;
|
|
setp.eq.f32 %p60, %f629, 0f3EE66666;
|
|
@%p60 bra $L__BB0_54;
|
|
|
|
mov.f32 %f1252, 0f7FFFFFFF;
|
|
|
|
$L__BB0_54:
|
|
abs.f32 %f1184, %f1247;
|
|
add.f32 %f632, %f1184, 0f3EE66666;
|
|
mov.b32 %r224, %f632;
|
|
setp.lt.s32 %p62, %r224, 2139095040;
|
|
@%p62 bra $L__BB0_59;
|
|
|
|
abs.f32 %f1185, %f1247;
|
|
setp.gtu.f32 %p63, %f1185, 0f7F800000;
|
|
@%p63 bra $L__BB0_58;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_58:
|
|
add.f32 %f1252, %f1247, 0f3EE66666;
|
|
bra.uni $L__BB0_59;
|
|
|
|
$L__BB0_56:
|
|
abs.f32 %f1186, %f1247;
|
|
setp.neu.f32 %p64, %f1186, 0f7F800000;
|
|
@%p64 bra $L__BB0_59;
|
|
|
|
selp.f32 %f1252, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_59:
|
|
setp.eq.f32 %p65, %f1247, 0f3F800000;
|
|
selp.f32 %f171, 0f3F800000, %f1252, %p65;
|
|
abs.f32 %f172, %f1248;
|
|
setp.lt.f32 %p66, %f172, 0f00800000;
|
|
mul.f32 %f634, %f172, 0f4B800000;
|
|
selp.f32 %f635, %f634, %f172, %p66;
|
|
selp.f32 %f636, 0fC3170000, 0fC2FE0000, %p66;
|
|
mov.b32 %r225, %f635;
|
|
and.b32 %r226, %r225, 8388607;
|
|
or.b32 %r227, %r226, 1065353216;
|
|
mov.b32 %f637, %r227;
|
|
shr.u32 %r228, %r225, 23;
|
|
cvt.rn.f32.u32 %f638, %r228;
|
|
add.f32 %f639, %f636, %f638;
|
|
setp.gt.f32 %p67, %f637, 0f3FB504F3;
|
|
mul.f32 %f640, %f637, 0f3F000000;
|
|
add.f32 %f641, %f639, 0f3F800000;
|
|
selp.f32 %f642, %f641, %f639, %p67;
|
|
selp.f32 %f643, %f640, %f637, %p67;
|
|
add.f32 %f644, %f643, 0fBF800000;
|
|
add.f32 %f645, %f643, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f646, %f645;
|
|
add.f32 %f647, %f644, %f644;
|
|
mul.f32 %f648, %f647, %f646;
|
|
mul.f32 %f649, %f648, %f648;
|
|
mov.f32 %f650, 0f3C4CAF63;
|
|
mov.f32 %f651, 0f3B18F0FE;
|
|
fma.rn.f32 %f652, %f651, %f649, %f650;
|
|
mov.f32 %f653, 0f3DAAAABD;
|
|
fma.rn.f32 %f654, %f652, %f649, %f653;
|
|
mul.rn.f32 %f655, %f654, %f649;
|
|
mul.rn.f32 %f656, %f655, %f648;
|
|
sub.f32 %f657, %f644, %f648;
|
|
add.f32 %f658, %f657, %f657;
|
|
neg.f32 %f659, %f648;
|
|
fma.rn.f32 %f660, %f659, %f644, %f658;
|
|
mul.rn.f32 %f661, %f646, %f660;
|
|
add.f32 %f662, %f656, %f648;
|
|
sub.f32 %f663, %f648, %f662;
|
|
add.f32 %f664, %f656, %f663;
|
|
add.f32 %f665, %f661, %f664;
|
|
add.f32 %f666, %f662, %f665;
|
|
sub.f32 %f667, %f662, %f666;
|
|
add.f32 %f668, %f665, %f667;
|
|
mov.f32 %f669, 0f3F317200;
|
|
mul.rn.f32 %f670, %f642, %f669;
|
|
mov.f32 %f671, 0f35BFBE8E;
|
|
mul.rn.f32 %f672, %f642, %f671;
|
|
add.f32 %f673, %f670, %f666;
|
|
sub.f32 %f674, %f670, %f673;
|
|
add.f32 %f675, %f666, %f674;
|
|
add.f32 %f676, %f668, %f675;
|
|
add.f32 %f677, %f672, %f676;
|
|
add.f32 %f678, %f673, %f677;
|
|
sub.f32 %f679, %f673, %f678;
|
|
add.f32 %f680, %f677, %f679;
|
|
mov.f32 %f681, 0f3EE66666;
|
|
mul.rn.f32 %f682, %f681, %f678;
|
|
neg.f32 %f683, %f682;
|
|
fma.rn.f32 %f684, %f681, %f678, %f683;
|
|
fma.rn.f32 %f685, %f681, %f680, %f684;
|
|
mov.f32 %f686, 0f00000000;
|
|
fma.rn.f32 %f687, %f686, %f678, %f685;
|
|
add.rn.f32 %f688, %f682, %f687;
|
|
neg.f32 %f689, %f688;
|
|
add.rn.f32 %f690, %f682, %f689;
|
|
add.rn.f32 %f691, %f690, %f687;
|
|
mov.b32 %r229, %f688;
|
|
setp.eq.s32 %p68, %r229, 1118925336;
|
|
add.s32 %r230, %r229, -1;
|
|
mov.b32 %f692, %r230;
|
|
add.f32 %f693, %f691, 0f37000000;
|
|
selp.f32 %f173, %f693, %f691, %p68;
|
|
selp.f32 %f694, %f692, %f688, %p68;
|
|
mov.f32 %f695, 0f3FB8AA3B;
|
|
mul.rn.f32 %f696, %f694, %f695;
|
|
cvt.rzi.f32.f32 %f697, %f696;
|
|
abs.f32 %f698, %f697;
|
|
setp.gt.f32 %p69, %f698, 0f42FC0000;
|
|
mov.b32 %r231, %f697;
|
|
and.b32 %r232, %r231, -2147483648;
|
|
or.b32 %r233, %r232, 1123811328;
|
|
mov.b32 %f699, %r233;
|
|
selp.f32 %f700, %f699, %f697, %p69;
|
|
mov.f32 %f701, 0fBF317218;
|
|
fma.rn.f32 %f702, %f700, %f701, %f694;
|
|
mov.f32 %f703, 0f3102E308;
|
|
fma.rn.f32 %f704, %f700, %f703, %f702;
|
|
mul.f32 %f705, %f704, 0f3FB8AA3B;
|
|
add.f32 %f706, %f700, 0f4B40007F;
|
|
mov.b32 %r234, %f706;
|
|
shl.b32 %r235, %r234, 23;
|
|
mov.b32 %f707, %r235;
|
|
ex2.approx.ftz.f32 %f708, %f705;
|
|
mul.f32 %f174, %f708, %f707;
|
|
setp.eq.f32 %p70, %f174, 0f7F800000;
|
|
mov.f32 %f1253, 0f7F800000;
|
|
@%p70 bra $L__BB0_61;
|
|
|
|
fma.rn.f32 %f1253, %f174, %f173, %f174;
|
|
|
|
$L__BB0_61:
|
|
setp.lt.f32 %p71, %f1248, 0f00000000;
|
|
and.pred %p2, %p71, %p57;
|
|
setp.eq.f32 %p73, %f1248, 0f00000000;
|
|
@%p73 bra $L__BB0_65;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_65:
|
|
add.f32 %f713, %f1248, %f1248;
|
|
selp.f32 %f1255, %f713, 0f00000000, %p57;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_62:
|
|
mov.b32 %r236, %f1253;
|
|
xor.b32 %r237, %r236, -2147483648;
|
|
mov.b32 %f709, %r237;
|
|
selp.f32 %f1255, %f709, %f1253, %p2;
|
|
setp.geu.f32 %p74, %f1248, 0f00000000;
|
|
@%p74 bra $L__BB0_66;
|
|
|
|
mov.f32 %f710, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f711, %f710;
|
|
setp.eq.f32 %p75, %f711, 0f3EE66666;
|
|
@%p75 bra $L__BB0_66;
|
|
|
|
mov.f32 %f1255, 0f7FFFFFFF;
|
|
|
|
$L__BB0_66:
|
|
abs.f32 %f1187, %f1248;
|
|
add.f32 %f714, %f1187, 0f3EE66666;
|
|
mov.b32 %r238, %f714;
|
|
setp.lt.s32 %p77, %r238, 2139095040;
|
|
@%p77 bra $L__BB0_71;
|
|
|
|
abs.f32 %f1188, %f1248;
|
|
setp.gtu.f32 %p78, %f1188, 0f7F800000;
|
|
@%p78 bra $L__BB0_70;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_70:
|
|
add.f32 %f1255, %f1248, 0f3EE66666;
|
|
bra.uni $L__BB0_71;
|
|
|
|
$L__BB0_68:
|
|
abs.f32 %f1189, %f1248;
|
|
setp.neu.f32 %p79, %f1189, 0f7F800000;
|
|
@%p79 bra $L__BB0_71;
|
|
|
|
selp.f32 %f1255, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_71:
|
|
setp.eq.f32 %p80, %f1248, 0f3F800000;
|
|
selp.f32 %f183, 0f3F800000, %f1255, %p80;
|
|
abs.f32 %f184, %f1249;
|
|
setp.lt.f32 %p81, %f184, 0f00800000;
|
|
mul.f32 %f716, %f184, 0f4B800000;
|
|
selp.f32 %f717, %f716, %f184, %p81;
|
|
selp.f32 %f718, 0fC3170000, 0fC2FE0000, %p81;
|
|
mov.b32 %r239, %f717;
|
|
and.b32 %r240, %r239, 8388607;
|
|
or.b32 %r241, %r240, 1065353216;
|
|
mov.b32 %f719, %r241;
|
|
shr.u32 %r242, %r239, 23;
|
|
cvt.rn.f32.u32 %f720, %r242;
|
|
add.f32 %f721, %f718, %f720;
|
|
setp.gt.f32 %p82, %f719, 0f3FB504F3;
|
|
mul.f32 %f722, %f719, 0f3F000000;
|
|
add.f32 %f723, %f721, 0f3F800000;
|
|
selp.f32 %f724, %f723, %f721, %p82;
|
|
selp.f32 %f725, %f722, %f719, %p82;
|
|
add.f32 %f726, %f725, 0fBF800000;
|
|
add.f32 %f727, %f725, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f728, %f727;
|
|
add.f32 %f729, %f726, %f726;
|
|
mul.f32 %f730, %f729, %f728;
|
|
mul.f32 %f731, %f730, %f730;
|
|
mov.f32 %f732, 0f3C4CAF63;
|
|
mov.f32 %f733, 0f3B18F0FE;
|
|
fma.rn.f32 %f734, %f733, %f731, %f732;
|
|
mov.f32 %f735, 0f3DAAAABD;
|
|
fma.rn.f32 %f736, %f734, %f731, %f735;
|
|
mul.rn.f32 %f737, %f736, %f731;
|
|
mul.rn.f32 %f738, %f737, %f730;
|
|
sub.f32 %f739, %f726, %f730;
|
|
add.f32 %f740, %f739, %f739;
|
|
neg.f32 %f741, %f730;
|
|
fma.rn.f32 %f742, %f741, %f726, %f740;
|
|
mul.rn.f32 %f743, %f728, %f742;
|
|
add.f32 %f744, %f738, %f730;
|
|
sub.f32 %f745, %f730, %f744;
|
|
add.f32 %f746, %f738, %f745;
|
|
add.f32 %f747, %f743, %f746;
|
|
add.f32 %f748, %f744, %f747;
|
|
sub.f32 %f749, %f744, %f748;
|
|
add.f32 %f750, %f747, %f749;
|
|
mov.f32 %f751, 0f3F317200;
|
|
mul.rn.f32 %f752, %f724, %f751;
|
|
mov.f32 %f753, 0f35BFBE8E;
|
|
mul.rn.f32 %f754, %f724, %f753;
|
|
add.f32 %f755, %f752, %f748;
|
|
sub.f32 %f756, %f752, %f755;
|
|
add.f32 %f757, %f748, %f756;
|
|
add.f32 %f758, %f750, %f757;
|
|
add.f32 %f759, %f754, %f758;
|
|
add.f32 %f760, %f755, %f759;
|
|
sub.f32 %f761, %f755, %f760;
|
|
add.f32 %f762, %f759, %f761;
|
|
mov.f32 %f763, 0f3EE66666;
|
|
mul.rn.f32 %f764, %f763, %f760;
|
|
neg.f32 %f765, %f764;
|
|
fma.rn.f32 %f766, %f763, %f760, %f765;
|
|
fma.rn.f32 %f767, %f763, %f762, %f766;
|
|
mov.f32 %f768, 0f00000000;
|
|
fma.rn.f32 %f769, %f768, %f760, %f767;
|
|
add.rn.f32 %f770, %f764, %f769;
|
|
neg.f32 %f771, %f770;
|
|
add.rn.f32 %f772, %f764, %f771;
|
|
add.rn.f32 %f773, %f772, %f769;
|
|
mov.b32 %r243, %f770;
|
|
setp.eq.s32 %p83, %r243, 1118925336;
|
|
add.s32 %r244, %r243, -1;
|
|
mov.b32 %f774, %r244;
|
|
add.f32 %f775, %f773, 0f37000000;
|
|
selp.f32 %f185, %f775, %f773, %p83;
|
|
selp.f32 %f776, %f774, %f770, %p83;
|
|
mov.f32 %f777, 0f3FB8AA3B;
|
|
mul.rn.f32 %f778, %f776, %f777;
|
|
cvt.rzi.f32.f32 %f779, %f778;
|
|
abs.f32 %f780, %f779;
|
|
setp.gt.f32 %p84, %f780, 0f42FC0000;
|
|
mov.b32 %r245, %f779;
|
|
and.b32 %r246, %r245, -2147483648;
|
|
or.b32 %r247, %r246, 1123811328;
|
|
mov.b32 %f781, %r247;
|
|
selp.f32 %f782, %f781, %f779, %p84;
|
|
mov.f32 %f783, 0fBF317218;
|
|
fma.rn.f32 %f784, %f782, %f783, %f776;
|
|
mov.f32 %f785, 0f3102E308;
|
|
fma.rn.f32 %f786, %f782, %f785, %f784;
|
|
mul.f32 %f787, %f786, 0f3FB8AA3B;
|
|
add.f32 %f788, %f782, 0f4B40007F;
|
|
mov.b32 %r248, %f788;
|
|
shl.b32 %r249, %r248, 23;
|
|
mov.b32 %f789, %r249;
|
|
ex2.approx.ftz.f32 %f790, %f787;
|
|
mul.f32 %f186, %f790, %f789;
|
|
setp.eq.f32 %p85, %f186, 0f7F800000;
|
|
mov.f32 %f1256, 0f7F800000;
|
|
@%p85 bra $L__BB0_73;
|
|
|
|
fma.rn.f32 %f1256, %f186, %f185, %f186;
|
|
|
|
$L__BB0_73:
|
|
setp.lt.f32 %p86, %f1249, 0f00000000;
|
|
and.pred %p3, %p86, %p57;
|
|
setp.eq.f32 %p88, %f1249, 0f00000000;
|
|
@%p88 bra $L__BB0_77;
|
|
bra.uni $L__BB0_74;
|
|
|
|
$L__BB0_77:
|
|
add.f32 %f795, %f1249, %f1249;
|
|
selp.f32 %f1258, %f795, 0f00000000, %p57;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_74:
|
|
mov.b32 %r250, %f1256;
|
|
xor.b32 %r251, %r250, -2147483648;
|
|
mov.b32 %f791, %r251;
|
|
selp.f32 %f1258, %f791, %f1256, %p3;
|
|
setp.geu.f32 %p89, %f1249, 0f00000000;
|
|
@%p89 bra $L__BB0_78;
|
|
|
|
mov.f32 %f792, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f793, %f792;
|
|
setp.eq.f32 %p90, %f793, 0f3EE66666;
|
|
@%p90 bra $L__BB0_78;
|
|
|
|
mov.f32 %f1258, 0f7FFFFFFF;
|
|
|
|
$L__BB0_78:
|
|
abs.f32 %f1190, %f1249;
|
|
add.f32 %f796, %f1190, 0f3EE66666;
|
|
mov.b32 %r252, %f796;
|
|
setp.lt.s32 %p92, %r252, 2139095040;
|
|
@%p92 bra $L__BB0_83;
|
|
|
|
abs.f32 %f1191, %f1249;
|
|
setp.gtu.f32 %p93, %f1191, 0f7F800000;
|
|
@%p93 bra $L__BB0_82;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_82:
|
|
add.f32 %f1258, %f1249, 0f3EE66666;
|
|
bra.uni $L__BB0_83;
|
|
|
|
$L__BB0_80:
|
|
abs.f32 %f1192, %f1249;
|
|
setp.neu.f32 %p94, %f1192, 0f7F800000;
|
|
@%p94 bra $L__BB0_83;
|
|
|
|
selp.f32 %f1258, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_83:
|
|
setp.eq.f32 %p95, %f1249, 0f3F800000;
|
|
mov.f32 %f798, 0f3F800000;
|
|
selp.f32 %f799, 0f3F800000, %f1258, %p95;
|
|
min.f32 %f800, %f171, %f798;
|
|
mov.f32 %f801, 0f00000000;
|
|
max.f32 %f195, %f801, %f800;
|
|
min.f32 %f802, %f183, %f798;
|
|
max.f32 %f196, %f801, %f802;
|
|
min.f32 %f803, %f799, %f798;
|
|
max.f32 %f197, %f801, %f803;
|
|
mov.f32 %f807, 0f3ED55555;
|
|
abs.f32 %f199, %f195;
|
|
setp.lt.f32 %p96, %f199, 0f00800000;
|
|
mul.f32 %f809, %f199, 0f4B800000;
|
|
selp.f32 %f810, %f809, %f199, %p96;
|
|
selp.f32 %f811, 0fC3170000, 0fC2FE0000, %p96;
|
|
mov.b32 %r255, %f810;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f812, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f813, %r258;
|
|
add.f32 %f814, %f811, %f813;
|
|
setp.gt.f32 %p97, %f812, 0f3FB504F3;
|
|
mul.f32 %f815, %f812, 0f3F000000;
|
|
add.f32 %f816, %f814, 0f3F800000;
|
|
selp.f32 %f817, %f816, %f814, %p97;
|
|
selp.f32 %f818, %f815, %f812, %p97;
|
|
add.f32 %f819, %f818, 0fBF800000;
|
|
add.f32 %f820, %f818, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f821, %f820;
|
|
add.f32 %f822, %f819, %f819;
|
|
mul.f32 %f823, %f822, %f821;
|
|
mul.f32 %f824, %f823, %f823;
|
|
mov.f32 %f825, 0f3C4CAF63;
|
|
mov.f32 %f826, 0f3B18F0FE;
|
|
fma.rn.f32 %f827, %f826, %f824, %f825;
|
|
mov.f32 %f828, 0f3DAAAABD;
|
|
fma.rn.f32 %f829, %f827, %f824, %f828;
|
|
mul.rn.f32 %f830, %f829, %f824;
|
|
mul.rn.f32 %f831, %f830, %f823;
|
|
sub.f32 %f832, %f819, %f823;
|
|
add.f32 %f833, %f832, %f832;
|
|
neg.f32 %f834, %f823;
|
|
fma.rn.f32 %f835, %f834, %f819, %f833;
|
|
mul.rn.f32 %f836, %f821, %f835;
|
|
add.f32 %f837, %f831, %f823;
|
|
sub.f32 %f838, %f823, %f837;
|
|
add.f32 %f839, %f831, %f838;
|
|
add.f32 %f840, %f836, %f839;
|
|
add.f32 %f841, %f837, %f840;
|
|
sub.f32 %f842, %f837, %f841;
|
|
add.f32 %f843, %f840, %f842;
|
|
mov.f32 %f844, 0f3F317200;
|
|
mul.rn.f32 %f845, %f817, %f844;
|
|
mov.f32 %f846, 0f35BFBE8E;
|
|
mul.rn.f32 %f847, %f817, %f846;
|
|
add.f32 %f848, %f845, %f841;
|
|
sub.f32 %f849, %f845, %f848;
|
|
add.f32 %f850, %f841, %f849;
|
|
add.f32 %f851, %f843, %f850;
|
|
add.f32 %f852, %f847, %f851;
|
|
add.f32 %f853, %f848, %f852;
|
|
sub.f32 %f854, %f848, %f853;
|
|
add.f32 %f855, %f852, %f854;
|
|
mul.rn.f32 %f856, %f807, %f853;
|
|
neg.f32 %f857, %f856;
|
|
fma.rn.f32 %f858, %f807, %f853, %f857;
|
|
fma.rn.f32 %f859, %f807, %f855, %f858;
|
|
fma.rn.f32 %f860, %f801, %f853, %f859;
|
|
add.rn.f32 %f861, %f856, %f860;
|
|
neg.f32 %f862, %f861;
|
|
add.rn.f32 %f863, %f856, %f862;
|
|
add.rn.f32 %f864, %f863, %f860;
|
|
mov.b32 %r259, %f861;
|
|
setp.eq.s32 %p98, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f865, %r260;
|
|
add.f32 %f866, %f864, 0f37000000;
|
|
selp.f32 %f200, %f866, %f864, %p98;
|
|
selp.f32 %f867, %f865, %f861, %p98;
|
|
mov.f32 %f868, 0f3FB8AA3B;
|
|
mul.rn.f32 %f869, %f867, %f868;
|
|
cvt.rzi.f32.f32 %f870, %f869;
|
|
abs.f32 %f871, %f870;
|
|
setp.gt.f32 %p99, %f871, 0f42FC0000;
|
|
mov.b32 %r261, %f870;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f872, %r263;
|
|
selp.f32 %f873, %f872, %f870, %p99;
|
|
mov.f32 %f874, 0fBF317218;
|
|
fma.rn.f32 %f875, %f873, %f874, %f867;
|
|
mov.f32 %f876, 0f3102E308;
|
|
fma.rn.f32 %f877, %f873, %f876, %f875;
|
|
mul.f32 %f878, %f877, 0f3FB8AA3B;
|
|
add.f32 %f879, %f873, 0f4B40007F;
|
|
mov.b32 %r264, %f879;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f880, %r265;
|
|
ex2.approx.ftz.f32 %f881, %f878;
|
|
mul.f32 %f201, %f881, %f880;
|
|
setp.eq.f32 %p100, %f201, 0f7F800000;
|
|
mov.f32 %f1259, 0f7F800000;
|
|
@%p100 bra $L__BB0_85;
|
|
|
|
fma.rn.f32 %f1259, %f201, %f200, %f201;
|
|
|
|
$L__BB0_85:
|
|
mov.f32 %f1177, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1176, %f1177;
|
|
add.f32 %f1175, %f1176, %f1176;
|
|
mov.f32 %f1174, 0f3ED55555;
|
|
sub.f32 %f1173, %f1174, %f1175;
|
|
abs.f32 %f1172, %f1173;
|
|
setp.lt.f32 %p101, %f195, 0f00000000;
|
|
setp.eq.f32 %p102, %f1172, 0f3F800000;
|
|
and.pred %p4, %p101, %p102;
|
|
setp.eq.f32 %p103, %f195, 0f00000000;
|
|
@%p103 bra $L__BB0_89;
|
|
bra.uni $L__BB0_86;
|
|
|
|
$L__BB0_89:
|
|
add.f32 %f886, %f195, %f195;
|
|
selp.f32 %f1261, %f886, 0f00000000, %p102;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_86:
|
|
mov.b32 %r266, %f1259;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f882, %r267;
|
|
selp.f32 %f1261, %f882, %f1259, %p4;
|
|
setp.geu.f32 %p104, %f195, 0f00000000;
|
|
@%p104 bra $L__BB0_90;
|
|
|
|
mov.f32 %f883, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f884, %f883;
|
|
setp.eq.f32 %p105, %f884, 0f3ED55555;
|
|
@%p105 bra $L__BB0_90;
|
|
|
|
mov.f32 %f1261, 0f7FFFFFFF;
|
|
|
|
$L__BB0_90:
|
|
add.f32 %f887, %f199, 0f3ED55555;
|
|
mov.b32 %r268, %f887;
|
|
setp.lt.s32 %p107, %r268, 2139095040;
|
|
@%p107 bra $L__BB0_95;
|
|
|
|
setp.gtu.f32 %p108, %f199, 0f7F800000;
|
|
@%p108 bra $L__BB0_94;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f1261, %f195, 0f3ED55555;
|
|
bra.uni $L__BB0_95;
|
|
|
|
$L__BB0_92:
|
|
setp.neu.f32 %p109, %f199, 0f7F800000;
|
|
@%p109 bra $L__BB0_95;
|
|
|
|
selp.f32 %f1261, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_95:
|
|
abs.f32 %f210, %f196;
|
|
setp.lt.f32 %p110, %f210, 0f00800000;
|
|
mul.f32 %f889, %f210, 0f4B800000;
|
|
selp.f32 %f890, %f889, %f210, %p110;
|
|
selp.f32 %f891, 0fC3170000, 0fC2FE0000, %p110;
|
|
mov.b32 %r269, %f890;
|
|
and.b32 %r270, %r269, 8388607;
|
|
or.b32 %r271, %r270, 1065353216;
|
|
mov.b32 %f892, %r271;
|
|
shr.u32 %r272, %r269, 23;
|
|
cvt.rn.f32.u32 %f893, %r272;
|
|
add.f32 %f894, %f891, %f893;
|
|
setp.gt.f32 %p111, %f892, 0f3FB504F3;
|
|
mul.f32 %f895, %f892, 0f3F000000;
|
|
add.f32 %f896, %f894, 0f3F800000;
|
|
selp.f32 %f897, %f896, %f894, %p111;
|
|
selp.f32 %f898, %f895, %f892, %p111;
|
|
add.f32 %f899, %f898, 0fBF800000;
|
|
add.f32 %f900, %f898, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f901, %f900;
|
|
add.f32 %f902, %f899, %f899;
|
|
mul.f32 %f903, %f902, %f901;
|
|
mul.f32 %f904, %f903, %f903;
|
|
mov.f32 %f905, 0f3C4CAF63;
|
|
mov.f32 %f906, 0f3B18F0FE;
|
|
fma.rn.f32 %f907, %f906, %f904, %f905;
|
|
mov.f32 %f908, 0f3DAAAABD;
|
|
fma.rn.f32 %f909, %f907, %f904, %f908;
|
|
mul.rn.f32 %f910, %f909, %f904;
|
|
mul.rn.f32 %f911, %f910, %f903;
|
|
sub.f32 %f912, %f899, %f903;
|
|
add.f32 %f913, %f912, %f912;
|
|
neg.f32 %f914, %f903;
|
|
fma.rn.f32 %f915, %f914, %f899, %f913;
|
|
mul.rn.f32 %f916, %f901, %f915;
|
|
add.f32 %f917, %f911, %f903;
|
|
sub.f32 %f918, %f903, %f917;
|
|
add.f32 %f919, %f911, %f918;
|
|
add.f32 %f920, %f916, %f919;
|
|
add.f32 %f921, %f917, %f920;
|
|
sub.f32 %f922, %f917, %f921;
|
|
add.f32 %f923, %f920, %f922;
|
|
mov.f32 %f924, 0f3F317200;
|
|
mul.rn.f32 %f925, %f897, %f924;
|
|
mov.f32 %f926, 0f35BFBE8E;
|
|
mul.rn.f32 %f927, %f897, %f926;
|
|
add.f32 %f928, %f925, %f921;
|
|
sub.f32 %f929, %f925, %f928;
|
|
add.f32 %f930, %f921, %f929;
|
|
add.f32 %f931, %f923, %f930;
|
|
add.f32 %f932, %f927, %f931;
|
|
add.f32 %f933, %f928, %f932;
|
|
sub.f32 %f934, %f928, %f933;
|
|
add.f32 %f935, %f932, %f934;
|
|
mov.f32 %f936, 0f3ED55555;
|
|
mul.rn.f32 %f937, %f936, %f933;
|
|
neg.f32 %f938, %f937;
|
|
fma.rn.f32 %f939, %f936, %f933, %f938;
|
|
fma.rn.f32 %f940, %f936, %f935, %f939;
|
|
mov.f32 %f941, 0f00000000;
|
|
fma.rn.f32 %f942, %f941, %f933, %f940;
|
|
add.rn.f32 %f943, %f937, %f942;
|
|
neg.f32 %f944, %f943;
|
|
add.rn.f32 %f945, %f937, %f944;
|
|
add.rn.f32 %f946, %f945, %f942;
|
|
mov.b32 %r273, %f943;
|
|
setp.eq.s32 %p112, %r273, 1118925336;
|
|
add.s32 %r274, %r273, -1;
|
|
mov.b32 %f947, %r274;
|
|
add.f32 %f948, %f946, 0f37000000;
|
|
selp.f32 %f211, %f948, %f946, %p112;
|
|
selp.f32 %f949, %f947, %f943, %p112;
|
|
mov.f32 %f950, 0f3FB8AA3B;
|
|
mul.rn.f32 %f951, %f949, %f950;
|
|
cvt.rzi.f32.f32 %f952, %f951;
|
|
abs.f32 %f953, %f952;
|
|
setp.gt.f32 %p113, %f953, 0f42FC0000;
|
|
mov.b32 %r275, %f952;
|
|
and.b32 %r276, %r275, -2147483648;
|
|
or.b32 %r277, %r276, 1123811328;
|
|
mov.b32 %f954, %r277;
|
|
selp.f32 %f955, %f954, %f952, %p113;
|
|
mov.f32 %f956, 0fBF317218;
|
|
fma.rn.f32 %f957, %f955, %f956, %f949;
|
|
mov.f32 %f958, 0f3102E308;
|
|
fma.rn.f32 %f959, %f955, %f958, %f957;
|
|
mul.f32 %f960, %f959, 0f3FB8AA3B;
|
|
add.f32 %f961, %f955, 0f4B40007F;
|
|
mov.b32 %r278, %f961;
|
|
shl.b32 %r279, %r278, 23;
|
|
mov.b32 %f962, %r279;
|
|
ex2.approx.ftz.f32 %f963, %f960;
|
|
mul.f32 %f212, %f963, %f962;
|
|
setp.eq.f32 %p114, %f212, 0f7F800000;
|
|
mov.f32 %f1262, 0f7F800000;
|
|
@%p114 bra $L__BB0_97;
|
|
|
|
fma.rn.f32 %f1262, %f212, %f211, %f212;
|
|
|
|
$L__BB0_97:
|
|
setp.lt.f32 %p115, %f196, 0f00000000;
|
|
and.pred %p5, %p115, %p102;
|
|
setp.eq.f32 %p117, %f196, 0f00000000;
|
|
@%p117 bra $L__BB0_101;
|
|
bra.uni $L__BB0_98;
|
|
|
|
$L__BB0_101:
|
|
add.f32 %f968, %f196, %f196;
|
|
selp.f32 %f1264, %f968, 0f00000000, %p102;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_98:
|
|
mov.b32 %r280, %f1262;
|
|
xor.b32 %r281, %r280, -2147483648;
|
|
mov.b32 %f964, %r281;
|
|
selp.f32 %f1264, %f964, %f1262, %p5;
|
|
setp.geu.f32 %p118, %f196, 0f00000000;
|
|
@%p118 bra $L__BB0_102;
|
|
|
|
mov.f32 %f965, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f966, %f965;
|
|
setp.eq.f32 %p119, %f966, 0f3ED55555;
|
|
@%p119 bra $L__BB0_102;
|
|
|
|
mov.f32 %f1264, 0f7FFFFFFF;
|
|
|
|
$L__BB0_102:
|
|
add.f32 %f969, %f210, 0f3ED55555;
|
|
mov.b32 %r282, %f969;
|
|
setp.lt.s32 %p121, %r282, 2139095040;
|
|
@%p121 bra $L__BB0_107;
|
|
|
|
setp.gtu.f32 %p122, %f210, 0f7F800000;
|
|
@%p122 bra $L__BB0_106;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_106:
|
|
add.f32 %f1264, %f196, 0f3ED55555;
|
|
bra.uni $L__BB0_107;
|
|
|
|
$L__BB0_104:
|
|
setp.neu.f32 %p123, %f210, 0f7F800000;
|
|
@%p123 bra $L__BB0_107;
|
|
|
|
selp.f32 %f1264, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_107:
|
|
abs.f32 %f221, %f197;
|
|
setp.lt.f32 %p124, %f221, 0f00800000;
|
|
mul.f32 %f971, %f221, 0f4B800000;
|
|
selp.f32 %f972, %f971, %f221, %p124;
|
|
selp.f32 %f973, 0fC3170000, 0fC2FE0000, %p124;
|
|
mov.b32 %r283, %f972;
|
|
and.b32 %r284, %r283, 8388607;
|
|
or.b32 %r285, %r284, 1065353216;
|
|
mov.b32 %f974, %r285;
|
|
shr.u32 %r286, %r283, 23;
|
|
cvt.rn.f32.u32 %f975, %r286;
|
|
add.f32 %f976, %f973, %f975;
|
|
setp.gt.f32 %p125, %f974, 0f3FB504F3;
|
|
mul.f32 %f977, %f974, 0f3F000000;
|
|
add.f32 %f978, %f976, 0f3F800000;
|
|
selp.f32 %f979, %f978, %f976, %p125;
|
|
selp.f32 %f980, %f977, %f974, %p125;
|
|
add.f32 %f981, %f980, 0fBF800000;
|
|
add.f32 %f982, %f980, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f983, %f982;
|
|
add.f32 %f984, %f981, %f981;
|
|
mul.f32 %f985, %f984, %f983;
|
|
mul.f32 %f986, %f985, %f985;
|
|
mov.f32 %f987, 0f3C4CAF63;
|
|
mov.f32 %f988, 0f3B18F0FE;
|
|
fma.rn.f32 %f989, %f988, %f986, %f987;
|
|
mov.f32 %f990, 0f3DAAAABD;
|
|
fma.rn.f32 %f991, %f989, %f986, %f990;
|
|
mul.rn.f32 %f992, %f991, %f986;
|
|
mul.rn.f32 %f993, %f992, %f985;
|
|
sub.f32 %f994, %f981, %f985;
|
|
add.f32 %f995, %f994, %f994;
|
|
neg.f32 %f996, %f985;
|
|
fma.rn.f32 %f997, %f996, %f981, %f995;
|
|
mul.rn.f32 %f998, %f983, %f997;
|
|
add.f32 %f999, %f993, %f985;
|
|
sub.f32 %f1000, %f985, %f999;
|
|
add.f32 %f1001, %f993, %f1000;
|
|
add.f32 %f1002, %f998, %f1001;
|
|
add.f32 %f1003, %f999, %f1002;
|
|
sub.f32 %f1004, %f999, %f1003;
|
|
add.f32 %f1005, %f1002, %f1004;
|
|
mov.f32 %f1006, 0f3F317200;
|
|
mul.rn.f32 %f1007, %f979, %f1006;
|
|
mov.f32 %f1008, 0f35BFBE8E;
|
|
mul.rn.f32 %f1009, %f979, %f1008;
|
|
add.f32 %f1010, %f1007, %f1003;
|
|
sub.f32 %f1011, %f1007, %f1010;
|
|
add.f32 %f1012, %f1003, %f1011;
|
|
add.f32 %f1013, %f1005, %f1012;
|
|
add.f32 %f1014, %f1009, %f1013;
|
|
add.f32 %f1015, %f1010, %f1014;
|
|
sub.f32 %f1016, %f1010, %f1015;
|
|
add.f32 %f1017, %f1014, %f1016;
|
|
mov.f32 %f1018, 0f3ED55555;
|
|
mul.rn.f32 %f1019, %f1018, %f1015;
|
|
neg.f32 %f1020, %f1019;
|
|
fma.rn.f32 %f1021, %f1018, %f1015, %f1020;
|
|
fma.rn.f32 %f1022, %f1018, %f1017, %f1021;
|
|
mov.f32 %f1023, 0f00000000;
|
|
fma.rn.f32 %f1024, %f1023, %f1015, %f1022;
|
|
add.rn.f32 %f1025, %f1019, %f1024;
|
|
neg.f32 %f1026, %f1025;
|
|
add.rn.f32 %f1027, %f1019, %f1026;
|
|
add.rn.f32 %f1028, %f1027, %f1024;
|
|
mov.b32 %r287, %f1025;
|
|
setp.eq.s32 %p126, %r287, 1118925336;
|
|
add.s32 %r288, %r287, -1;
|
|
mov.b32 %f1029, %r288;
|
|
add.f32 %f1030, %f1028, 0f37000000;
|
|
selp.f32 %f222, %f1030, %f1028, %p126;
|
|
selp.f32 %f1031, %f1029, %f1025, %p126;
|
|
mov.f32 %f1032, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1033, %f1031, %f1032;
|
|
cvt.rzi.f32.f32 %f1034, %f1033;
|
|
abs.f32 %f1035, %f1034;
|
|
setp.gt.f32 %p127, %f1035, 0f42FC0000;
|
|
mov.b32 %r289, %f1034;
|
|
and.b32 %r290, %r289, -2147483648;
|
|
or.b32 %r291, %r290, 1123811328;
|
|
mov.b32 %f1036, %r291;
|
|
selp.f32 %f1037, %f1036, %f1034, %p127;
|
|
mov.f32 %f1038, 0fBF317218;
|
|
fma.rn.f32 %f1039, %f1037, %f1038, %f1031;
|
|
mov.f32 %f1040, 0f3102E308;
|
|
fma.rn.f32 %f1041, %f1037, %f1040, %f1039;
|
|
mul.f32 %f1042, %f1041, 0f3FB8AA3B;
|
|
add.f32 %f1043, %f1037, 0f4B40007F;
|
|
mov.b32 %r292, %f1043;
|
|
shl.b32 %r293, %r292, 23;
|
|
mov.b32 %f1044, %r293;
|
|
ex2.approx.ftz.f32 %f1045, %f1042;
|
|
mul.f32 %f223, %f1045, %f1044;
|
|
setp.eq.f32 %p128, %f223, 0f7F800000;
|
|
mov.f32 %f1265, 0f7F800000;
|
|
@%p128 bra $L__BB0_109;
|
|
|
|
fma.rn.f32 %f1265, %f223, %f222, %f223;
|
|
|
|
$L__BB0_109:
|
|
setp.lt.f32 %p129, %f197, 0f00000000;
|
|
and.pred %p6, %p129, %p102;
|
|
setp.eq.f32 %p131, %f197, 0f00000000;
|
|
@%p131 bra $L__BB0_113;
|
|
bra.uni $L__BB0_110;
|
|
|
|
$L__BB0_113:
|
|
add.f32 %f1050, %f197, %f197;
|
|
selp.f32 %f1267, %f1050, 0f00000000, %p102;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_110:
|
|
mov.b32 %r294, %f1265;
|
|
xor.b32 %r295, %r294, -2147483648;
|
|
mov.b32 %f1046, %r295;
|
|
selp.f32 %f1267, %f1046, %f1265, %p6;
|
|
setp.geu.f32 %p132, %f197, 0f00000000;
|
|
@%p132 bra $L__BB0_114;
|
|
|
|
mov.f32 %f1047, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1048, %f1047;
|
|
setp.eq.f32 %p133, %f1048, 0f3ED55555;
|
|
@%p133 bra $L__BB0_114;
|
|
|
|
mov.f32 %f1267, 0f7FFFFFFF;
|
|
|
|
$L__BB0_114:
|
|
add.f32 %f1051, %f221, 0f3ED55555;
|
|
mov.b32 %r296, %f1051;
|
|
setp.lt.s32 %p135, %r296, 2139095040;
|
|
@%p135 bra $L__BB0_119;
|
|
|
|
setp.gtu.f32 %p136, %f221, 0f7F800000;
|
|
@%p136 bra $L__BB0_118;
|
|
bra.uni $L__BB0_116;
|
|
|
|
$L__BB0_118:
|
|
add.f32 %f1267, %f197, 0f3ED55555;
|
|
bra.uni $L__BB0_119;
|
|
|
|
$L__BB0_116:
|
|
setp.neu.f32 %p137, %f221, 0f7F800000;
|
|
@%p137 bra $L__BB0_119;
|
|
|
|
selp.f32 %f1267, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_119:
|
|
ld.const.u64 %rd112, [params+144];
|
|
cvta.to.global.u64 %rd111, %rd112;
|
|
ld.const.u32 %r347, [params+136];
|
|
mad.lo.s32 %r346, %r347, %r5, %r4;
|
|
cvt.u64.u32 %rd110, %r346;
|
|
fma.rn.f32 %f1052, %f1261, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p138, %f195, 0f3F800000;
|
|
mov.f32 %f1053, 0f3F800000;
|
|
selp.f32 %f1054, 0f3F7FFFFF, %f1052, %p138;
|
|
mul.f32 %f1055, %f195, 0f414EB852;
|
|
setp.lt.f32 %p139, %f195, 0f3B4D2E1C;
|
|
selp.f32 %f1056, %f1055, %f1054, %p139;
|
|
fma.rn.f32 %f1057, %f1264, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p140, %f196, 0f3F800000;
|
|
selp.f32 %f1058, 0f3F7FFFFF, %f1057, %p140;
|
|
mul.f32 %f1059, %f196, 0f414EB852;
|
|
setp.lt.f32 %p141, %f196, 0f3B4D2E1C;
|
|
selp.f32 %f1060, %f1059, %f1058, %p141;
|
|
fma.rn.f32 %f1061, %f1267, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p142, %f197, 0f3F800000;
|
|
selp.f32 %f1062, 0f3F7FFFFF, %f1061, %p142;
|
|
mul.f32 %f1063, %f197, 0f414EB852;
|
|
setp.lt.f32 %p143, %f197, 0f3B4D2E1C;
|
|
selp.f32 %f1064, %f1063, %f1062, %p143;
|
|
min.f32 %f1065, %f1056, %f1053;
|
|
mov.f32 %f1066, 0f00000000;
|
|
max.f32 %f1067, %f1066, %f1065;
|
|
mul.f32 %f1068, %f1067, 0f43800000;
|
|
cvt.rzi.u32.f32 %r297, %f1068;
|
|
min.u32 %r298, %r297, 255;
|
|
min.f32 %f1069, %f1060, %f1053;
|
|
max.f32 %f1070, %f1066, %f1069;
|
|
mul.f32 %f1071, %f1070, 0f43800000;
|
|
cvt.rzi.u32.f32 %r299, %f1071;
|
|
min.u32 %r300, %r299, 255;
|
|
min.f32 %f1072, %f1064, %f1053;
|
|
max.f32 %f1073, %f1066, %f1072;
|
|
mul.f32 %f1074, %f1073, 0f43800000;
|
|
cvt.rzi.u32.f32 %r301, %f1074;
|
|
min.u32 %r302, %r301, 255;
|
|
shl.b64 %rd70, %rd110, 2;
|
|
add.s64 %rd71, %rd111, %rd70;
|
|
cvt.u16.u32 %rs52, %r302;
|
|
cvt.u16.u32 %rs53, %r300;
|
|
cvt.u16.u32 %rs54, %r298;
|
|
mov.u16 %rs55, 255;
|
|
st.global.v4.u8 [%rd71], {%rs54, %rs53, %rs52, %rs55};
|
|
|
|
$L__BB0_120:
|
|
ld.const.u32 %r348, [params+104];
|
|
and.b32 %r303, %r348, 4;
|
|
setp.eq.s32 %p144, %r303, 0;
|
|
@%p144 bra $L__BB0_122;
|
|
|
|
ld.const.u64 %rd72, [params+224];
|
|
cvta.to.global.u64 %rd73, %rd72;
|
|
ld.const.u32 %r304, [params+216];
|
|
mad.lo.s32 %r305, %r304, %r5, %r4;
|
|
mov.f32 %f1078, 0f3F800000;
|
|
mul.wide.u32 %rd74, %r305, 8;
|
|
add.s64 %rd75, %rd73, %rd74;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1078;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1249;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1248;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1247;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd75], {%rs56, %rs57, %rs58, %rs59};
|
|
|
|
$L__BB0_122:
|
|
ld.const.u32 %r349, [params+104];
|
|
and.b32 %r306, %r349, 16;
|
|
setp.eq.s32 %p145, %r306, 0;
|
|
@%p145 bra $L__BB0_124;
|
|
|
|
ld.const.u64 %rd76, [params+240];
|
|
cvta.to.global.u64 %rd77, %rd76;
|
|
ld.const.u32 %r307, [params+232];
|
|
mad.lo.s32 %r308, %r307, %r5, %r4;
|
|
mov.f32 %f1082, 0f3F800000;
|
|
mul.wide.u32 %rd78, %r308, 8;
|
|
add.s64 %rd79, %rd77, %rd78;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f1082;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f144;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd79], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1083, %f135, %f132;
|
|
add.f32 %f1084, %f138, %f1083;
|
|
add.f32 %f1085, %f136, %f133;
|
|
add.f32 %f1086, %f139, %f1085;
|
|
add.f32 %f1087, %f137, %f134;
|
|
add.f32 %f1088, %f140, %f1087;
|
|
mul.f32 %f1089, %f1084, 0f3F13CD3A;
|
|
mul.f32 %f1090, %f1086, 0f3F13CD3A;
|
|
mul.f32 %f1091, %f1088, 0f3F13CD3A;
|
|
div.rn.f32 %f1092, %f141, %f1089;
|
|
div.rn.f32 %f1093, %f142, %f1090;
|
|
div.rn.f32 %f1094, %f143, %f1091;
|
|
setp.eq.f32 %p146, %f141, 0f00000000;
|
|
selp.f32 %f1095, 0f00000000, %f1092, %p146;
|
|
setp.eq.f32 %p147, %f142, 0f00000000;
|
|
selp.f32 %f1096, 0f00000000, %f1093, %p147;
|
|
setp.eq.f32 %p148, %f143, 0f00000000;
|
|
selp.f32 %f1097, 0f00000000, %f1094, %p148;
|
|
mul.f32 %f232, %f132, %f1095;
|
|
mul.f32 %f233, %f133, %f1096;
|
|
mul.f32 %f234, %f134, %f1097;
|
|
mul.f32 %f235, %f135, %f1095;
|
|
mul.f32 %f236, %f136, %f1096;
|
|
mul.f32 %f237, %f137, %f1097;
|
|
mul.f32 %f238, %f138, %f1095;
|
|
mul.f32 %f239, %f139, %f1096;
|
|
mul.f32 %f240, %f140, %f1097;
|
|
ld.const.u32 %r49, [params+108];
|
|
setp.eq.s32 %p149, %r49, 0;
|
|
ld.const.u64 %rd80, [params+256];
|
|
cvta.to.global.u64 %rd81, %rd80;
|
|
ld.const.u32 %r309, [params+248];
|
|
mad.lo.s32 %r310, %r309, %r5, %r4;
|
|
mul.wide.u32 %rd82, %r310, 8;
|
|
add.s64 %rd18, %rd81, %rd82;
|
|
@%p149 bra $L__BB0_126;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1098, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1099, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1100, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1101, %f232, %f1098;
|
|
add.f32 %f1102, %f233, %f1099;
|
|
add.f32 %f1103, %f234, %f1100;
|
|
mov.f32 %f1104, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1103;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1104;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_127;
|
|
|
|
$L__BB0_126:
|
|
mov.f32 %f1108, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f1108;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f234;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f232;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_127:
|
|
ld.const.u64 %rd83, [params+272];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r311, [params+264];
|
|
mad.lo.s32 %r312, %r311, %r5, %r4;
|
|
mul.wide.u32 %rd85, %r312, 8;
|
|
add.s64 %rd19, %rd84, %rd85;
|
|
@%p149 bra $L__BB0_129;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1109, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1110, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1111, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1112, %f235, %f1109;
|
|
add.f32 %f1113, %f236, %f1110;
|
|
add.f32 %f1114, %f237, %f1111;
|
|
mov.f32 %f1115, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1114;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1113;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1112;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1115;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_130;
|
|
|
|
$L__BB0_129:
|
|
mov.f32 %f1119, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f1119;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f235;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs90, %rs91, %rs92, %rs93};
|
|
|
|
$L__BB0_130:
|
|
ld.const.u64 %rd86, [params+288];
|
|
cvta.to.global.u64 %rd87, %rd86;
|
|
ld.const.u32 %r313, [params+280];
|
|
mad.lo.s32 %r314, %r313, %r5, %r4;
|
|
mul.wide.u32 %rd88, %r314, 8;
|
|
add.s64 %rd20, %rd87, %rd88;
|
|
@%p149 bra $L__BB0_132;
|
|
|
|
ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1120, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1121, %rs102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1122, %rs103;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1123, %f238, %f1120;
|
|
add.f32 %f1124, %f239, %f1121;
|
|
add.f32 %f1125, %f240, %f1122;
|
|
mov.f32 %f1126, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1125;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1124;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1126;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs97, %rs98, %rs99, %rs100};
|
|
bra.uni $L__BB0_148;
|
|
|
|
$L__BB0_132:
|
|
mov.f32 %f1130, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f1130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f240;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f238;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs105, %rs106, %rs107, %rs108};
|
|
|
|
$L__BB0_148:
|
|
ret;
|
|
|
|
}
|
|
|