2821 lines
79 KiB
Plaintext
2821 lines
79 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.visible .entry __raygen__oxMain()
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{
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.reg .pred %p<210>;
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.reg .b16 %rs<180>;
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.reg .f32 %f<1726>;
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.reg .b32 %r<454>;
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.reg .b64 %rd<78>;
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// begin inline asm
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call (%r26), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r27), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd21, [params+400];
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cvta.to.global.u64 %rd22, %rd21;
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ld.const.u32 %r32, [params+392];
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mad.lo.s32 %r33, %r32, %r27, %r26;
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mul.wide.u32 %rd23, %r33, 4;
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add.s64 %rd1, %rd22, %rd23;
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ld.global.v2.u8 {%rs9, %rs178}, [%rd1];
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or.b16 %rs11, %rs9, %rs178;
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and.b16 %rs12, %rs11, 255;
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setp.eq.s16 %p11, %rs12, 0;
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@%p11 bra $L__BB0_2;
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ld.global.u8 %rs177, [%rd1+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs177, [%rd1+2];
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setp.eq.s16 %p12, %rs177, 0;
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mov.f32 %f1619, 0f00000000;
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mov.u16 %rs178, 0;
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mov.f32 %f1620, %f1619;
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mov.f32 %f1621, %f1619;
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@%p12 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f315, %rs9;
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div.rn.f32 %f316, %f315, 0f437F0000;
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fma.rn.f32 %f317, %f316, 0f40000000, 0fBF800000;
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and.b16 %rs15, %rs178, 255;
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cvt.rn.f32.u16 %f318, %rs15;
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div.rn.f32 %f319, %f318, 0f437F0000;
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fma.rn.f32 %f320, %f319, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f321, %rs177;
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div.rn.f32 %f322, %f321, 0f437F0000;
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fma.rn.f32 %f323, %f322, 0f40000000, 0fBF800000;
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mul.f32 %f324, %f320, %f320;
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fma.rn.f32 %f325, %f317, %f317, %f324;
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fma.rn.f32 %f326, %f323, %f323, %f325;
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sqrt.rn.f32 %f327, %f326;
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rcp.rn.f32 %f328, %f327;
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mul.f32 %f1621, %f328, %f323;
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mul.f32 %f1620, %f328, %f320;
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mul.f32 %f1619, %f317, %f328;
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$L__BB0_4:
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ld.const.v2.u32 {%r34, %r35}, [params];
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add.s32 %r3, %r34, %r26;
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add.s32 %r4, %r35, %r27;
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setp.eq.f32 %p13, %f1619, 0f00000000;
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setp.eq.f32 %p14, %f1620, 0f00000000;
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and.pred %p15, %p13, %p14;
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setp.eq.f32 %p16, %f1621, 0f00000000;
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and.pred %p17, %p16, %p15;
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@%p17 bra $L__BB0_163;
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bra.uni $L__BB0_5;
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$L__BB0_163:
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ld.const.u32 %r23, [params+104];
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and.b32 %r428, %r23, 1;
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setp.eq.b32 %p198, %r428, 1;
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mov.pred %p199, 0;
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xor.pred %p200, %p198, %p199;
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not.pred %p201, %p200;
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@%p201 bra $L__BB0_165;
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ld.const.u64 %rd54, [params+144];
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cvta.to.global.u64 %rd55, %rd54;
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ld.const.u32 %r429, [params+136];
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mad.lo.s32 %r430, %r429, %r4, %r3;
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mul.wide.u32 %rd56, %r430, 4;
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add.s64 %rd57, %rd55, %rd56;
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mov.u16 %rs99, 0;
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st.global.v4.u8 [%rd57], {%rs99, %rs99, %rs99, %rs99};
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$L__BB0_165:
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and.b32 %r431, %r23, 8;
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setp.eq.s32 %p202, %r431, 0;
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@%p202 bra $L__BB0_167;
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ld.const.u64 %rd58, [params+192];
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cvta.to.global.u64 %rd59, %rd58;
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ld.const.u32 %r432, [params+184];
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mad.lo.s32 %r433, %r432, %r4, %r3;
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mov.f32 %f1570, 0f00000000;
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cvt.rzi.u32.f32 %r434, %f1570;
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mul.wide.u32 %rd60, %r433, 2;
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add.s64 %rd61, %rd59, %rd60;
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mov.u16 %rs100, 0;
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cvt.u16.u32 %rs101, %r434;
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st.global.v2.u8 [%rd61], {%rs101, %rs100};
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$L__BB0_167:
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and.b32 %r435, %r23, 4;
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setp.eq.s32 %p203, %r435, 0;
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ld.const.u32 %r453, [params+108];
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@%p203 bra $L__BB0_171;
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setp.eq.s32 %p204, %r453, 0;
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ld.const.u64 %rd62, [params+224];
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cvta.to.global.u64 %rd63, %rd62;
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ld.const.u32 %r436, [params+216];
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mad.lo.s32 %r437, %r436, %r4, %r3;
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mul.wide.u32 %rd64, %r437, 8;
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add.s64 %rd16, %rd63, %rd64;
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@%p204 bra $L__BB0_170;
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ld.global.v4.u16 {%rs108, %rs109, %rs110, %rs111}, [%rd16];
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// begin inline asm
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{ cvt.f32.f16 %f1571, %rs108;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1572, %rs109;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1573, %rs110;}
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// end inline asm
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add.f32 %f1574, %f1571, 0f00000000;
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add.f32 %f1575, %f1572, 0f00000000;
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add.f32 %f1576, %f1573, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs107, %f1576;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs106, %f1575;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs105, %f1574;}
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// end inline asm
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mov.u16 %rs112, 0;
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st.global.v4.u16 [%rd16], {%rs105, %rs106, %rs107, %rs112};
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bra.uni $L__BB0_171;
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$L__BB0_5:
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ld.const.u64 %rd24, [params+432];
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cvta.to.global.u64 %rd25, %rd24;
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ld.const.u32 %r38, [params+424];
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mad.lo.s32 %r39, %r38, %r27, %r26;
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mul.wide.u32 %rd26, %r39, 12;
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add.s64 %rd27, %rd25, %rd26;
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ld.global.f32 %f10, [%rd27];
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mul.f32 %f329, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd27+4];
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mul.f32 %f330, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd27+8];
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mul.f32 %f331, %f12, 0f3456BF95;
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abs.f32 %f332, %f1619;
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div.rn.f32 %f333, %f329, %f332;
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abs.f32 %f334, %f1620;
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div.rn.f32 %f335, %f330, %f334;
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abs.f32 %f336, %f1621;
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div.rn.f32 %f337, %f331, %f336;
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abs.f32 %f338, %f333;
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abs.f32 %f339, %f335;
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abs.f32 %f340, %f337;
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mov.f32 %f341, 0f38D1B717;
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max.f32 %f342, %f338, %f341;
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max.f32 %f343, %f339, %f341;
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max.f32 %f344, %f340, %f341;
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fma.rn.f32 %f13, %f1619, %f342, %f10;
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fma.rn.f32 %f14, %f1620, %f343, %f11;
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fma.rn.f32 %f15, %f1621, %f344, %f12;
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cvt.rn.f32.u32 %f16, %r26;
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cvt.rn.f32.u32 %f17, %r27;
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ld.const.u32 %r5, [params+600];
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setp.eq.s32 %p18, %r5, 0;
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@%p18 bra $L__BB0_58;
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ld.const.u64 %rd28, [params+608];
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cvta.to.global.u64 %rd2, %rd28;
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mov.f32 %f361, 0f40000000;
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cvt.rzi.f32.f32 %f362, %f361;
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add.f32 %f363, %f362, %f362;
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mov.f32 %f364, 0f40800000;
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sub.f32 %f365, %f364, %f363;
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abs.f32 %f18, %f365;
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ld.const.u32 %r6, [params+544];
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ld.const.u32 %r451, [params+104];
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mul.f32 %f19, %f13, 0f3456BF95;
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mul.f32 %f20, %f14, 0f3456BF95;
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mul.f32 %f21, %f15, 0f3456BF95;
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mov.f32 %f360, 0f00000000;
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mov.u32 %r447, 0;
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ld.const.u64 %rd3, [params+96];
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abs.f32 %f567, %f19;
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abs.f32 %f568, %f20;
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max.f32 %f569, %f567, %f568;
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abs.f32 %f570, %f21;
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max.f32 %f571, %f569, %f570;
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mov.f32 %f1688, %f360;
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mov.f32 %f1687, %f360;
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mov.f32 %f1686, %f360;
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mov.f32 %f1685, %f360;
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mov.f32 %f1684, %f360;
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mov.f32 %f1683, %f360;
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mov.f32 %f1682, %f360;
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mov.f32 %f1681, %f360;
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mov.f32 %f1680, %f360;
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mov.f32 %f1679, %f360;
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mov.f32 %f1678, %f360;
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mov.f32 %f1677, %f360;
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mov.f32 %f1676, %f360;
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mov.f32 %f1675, %f360;
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mov.f32 %f1674, %f360;
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mov.f32 %f1673, %f360;
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$L__BB0_7:
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mul.wide.u32 %rd29, %r447, 112;
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add.s64 %rd5, %rd2, %rd29;
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ld.global.v4.f32 {%f367, %f368, %f369, %f370}, [%rd5];
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ld.global.v4.f32 {%f371, %f372, %f373, %f374}, [%rd5+16];
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ld.global.v4.f32 {%f377, %f1646, %f1647, %f380}, [%rd5+32];
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ld.global.v4.f32 {%f381, %f382, %f383, %f1644}, [%rd5+48];
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ld.global.v4.f32 {%f385, %f386, %f387, %f388}, [%rd5+64];
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ld.global.v4.u32 {%r41, %r42, %r43, %r44}, [%rd5+80];
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mov.b32 %f57, %r43;
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mov.b32 %f56, %r42;
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mov.b32 %f55, %r41;
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ld.global.u64 %rd6, [%rd5+96];
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sub.f32 %f389, %f368, %f10;
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sub.f32 %f390, %f369, %f11;
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sub.f32 %f391, %f370, %f12;
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mul.f32 %f392, %f390, %f390;
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fma.rn.f32 %f393, %f389, %f389, %f392;
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fma.rn.f32 %f394, %f391, %f391, %f393;
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sqrt.rn.f32 %f395, %f394;
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rcp.rn.f32 %f396, %f395;
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mul.f32 %f59, %f389, %f396;
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mul.f32 %f60, %f390, %f396;
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mul.f32 %f61, %f391, %f396;
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mul.f32 %f62, %f395, %f372;
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mul.f32 %f63, %f395, %f374;
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abs.f32 %f64, %f63;
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setp.lt.f32 %p19, %f64, 0f00800000;
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mul.f32 %f397, %f64, 0f4B800000;
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selp.f32 %f398, %f397, %f64, %p19;
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selp.f32 %f399, 0fC3170000, 0fC2FE0000, %p19;
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mov.b32 %r48, %f398;
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and.b32 %r49, %r48, 8388607;
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or.b32 %r50, %r49, 1065353216;
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mov.b32 %f400, %r50;
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shr.u32 %r51, %r48, 23;
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cvt.rn.f32.u32 %f401, %r51;
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add.f32 %f402, %f399, %f401;
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setp.gt.f32 %p20, %f400, 0f3FB504F3;
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mul.f32 %f403, %f400, 0f3F000000;
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add.f32 %f404, %f402, 0f3F800000;
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selp.f32 %f405, %f404, %f402, %p20;
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selp.f32 %f406, %f403, %f400, %p20;
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add.f32 %f407, %f406, 0fBF800000;
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add.f32 %f408, %f406, 0f3F800000;
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rcp.approx.ftz.f32 %f409, %f408;
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add.f32 %f410, %f407, %f407;
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mul.f32 %f411, %f410, %f409;
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mul.f32 %f412, %f411, %f411;
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mov.f32 %f413, 0f3C4CAF63;
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mov.f32 %f414, 0f3B18F0FE;
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fma.rn.f32 %f415, %f414, %f412, %f413;
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mov.f32 %f416, 0f3DAAAABD;
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fma.rn.f32 %f417, %f415, %f412, %f416;
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mul.rn.f32 %f418, %f417, %f412;
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mul.rn.f32 %f419, %f418, %f411;
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sub.f32 %f420, %f407, %f411;
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add.f32 %f421, %f420, %f420;
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neg.f32 %f422, %f411;
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fma.rn.f32 %f423, %f422, %f407, %f421;
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mul.rn.f32 %f424, %f409, %f423;
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add.f32 %f425, %f419, %f411;
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sub.f32 %f426, %f411, %f425;
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add.f32 %f427, %f419, %f426;
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add.f32 %f428, %f424, %f427;
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add.f32 %f429, %f425, %f428;
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sub.f32 %f430, %f425, %f429;
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add.f32 %f431, %f428, %f430;
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mov.f32 %f432, 0f3F317200;
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mul.rn.f32 %f433, %f405, %f432;
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mov.f32 %f434, 0f35BFBE8E;
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mul.rn.f32 %f435, %f405, %f434;
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add.f32 %f436, %f433, %f429;
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sub.f32 %f437, %f433, %f436;
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add.f32 %f438, %f429, %f437;
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add.f32 %f439, %f431, %f438;
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add.f32 %f440, %f435, %f439;
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add.f32 %f441, %f436, %f440;
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sub.f32 %f442, %f436, %f441;
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add.f32 %f443, %f440, %f442;
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mul.rn.f32 %f445, %f364, %f441;
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neg.f32 %f446, %f445;
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fma.rn.f32 %f447, %f364, %f441, %f446;
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fma.rn.f32 %f448, %f364, %f443, %f447;
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fma.rn.f32 %f450, %f360, %f441, %f448;
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add.rn.f32 %f451, %f445, %f450;
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neg.f32 %f452, %f451;
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add.rn.f32 %f453, %f445, %f452;
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add.rn.f32 %f454, %f453, %f450;
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mov.b32 %r52, %f451;
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setp.eq.s32 %p21, %r52, 1118925336;
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add.s32 %r53, %r52, -1;
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mov.b32 %f455, %r53;
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add.f32 %f456, %f454, 0f37000000;
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selp.f32 %f65, %f456, %f454, %p21;
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selp.f32 %f457, %f455, %f451, %p21;
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mov.f32 %f458, 0f3FB8AA3B;
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mul.rn.f32 %f459, %f457, %f458;
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cvt.rzi.f32.f32 %f460, %f459;
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abs.f32 %f461, %f460;
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setp.gt.f32 %p22, %f461, 0f42FC0000;
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mov.b32 %r54, %f460;
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and.b32 %r55, %r54, -2147483648;
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or.b32 %r56, %r55, 1123811328;
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mov.b32 %f462, %r56;
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selp.f32 %f463, %f462, %f460, %p22;
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mov.f32 %f464, 0fBF317218;
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fma.rn.f32 %f465, %f463, %f464, %f457;
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mov.f32 %f466, 0f3102E308;
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fma.rn.f32 %f467, %f463, %f466, %f465;
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mul.f32 %f468, %f467, 0f3FB8AA3B;
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add.f32 %f469, %f463, 0f4B40007F;
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mov.b32 %r57, %f469;
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shl.b32 %r58, %r57, 23;
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mov.b32 %f470, %r58;
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ex2.approx.ftz.f32 %f471, %f468;
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mul.f32 %f66, %f471, %f470;
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setp.eq.f32 %p23, %f66, 0f7F800000;
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mov.f32 %f1638, 0f7F800000;
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@%p23 bra $L__BB0_9;
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fma.rn.f32 %f1638, %f66, %f65, %f66;
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$L__BB0_9:
|
|
setp.lt.f32 %p24, %f63, 0f00000000;
|
|
setp.eq.f32 %p25, %f18, 0f3F800000;
|
|
and.pred %p1, %p24, %p25;
|
|
setp.eq.f32 %p26, %f63, 0f00000000;
|
|
@%p26 bra $L__BB0_13;
|
|
bra.uni $L__BB0_10;
|
|
|
|
$L__BB0_13:
|
|
add.f32 %f476, %f63, %f63;
|
|
selp.f32 %f1640, %f476, 0f00000000, %p25;
|
|
bra.uni $L__BB0_14;
|
|
|
|
$L__BB0_10:
|
|
mov.b32 %r59, %f1638;
|
|
xor.b32 %r60, %r59, -2147483648;
|
|
mov.b32 %f472, %r60;
|
|
selp.f32 %f1640, %f472, %f1638, %p1;
|
|
setp.geu.f32 %p27, %f63, 0f00000000;
|
|
@%p27 bra $L__BB0_14;
|
|
|
|
mov.f32 %f473, 0f40800000;
|
|
cvt.rzi.f32.f32 %f474, %f473;
|
|
setp.eq.f32 %p28, %f474, 0f40800000;
|
|
@%p28 bra $L__BB0_14;
|
|
|
|
mov.f32 %f1640, 0f7FFFFFFF;
|
|
|
|
$L__BB0_14:
|
|
abs.f32 %f1616, %f63;
|
|
add.f32 %f477, %f1616, 0f40800000;
|
|
mov.b32 %r61, %f477;
|
|
setp.lt.s32 %p30, %r61, 2139095040;
|
|
@%p30 bra $L__BB0_19;
|
|
|
|
abs.f32 %f1617, %f63;
|
|
setp.gtu.f32 %p31, %f1617, 0f7F800000;
|
|
@%p31 bra $L__BB0_18;
|
|
bra.uni $L__BB0_16;
|
|
|
|
$L__BB0_18:
|
|
add.f32 %f1640, %f63, 0f40800000;
|
|
bra.uni $L__BB0_19;
|
|
|
|
$L__BB0_16:
|
|
abs.f32 %f1618, %f63;
|
|
setp.neu.f32 %p32, %f1618, 0f7F800000;
|
|
@%p32 bra $L__BB0_19;
|
|
|
|
selp.f32 %f1640, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_19:
|
|
mov.f32 %f478, 0f3F800000;
|
|
sub.f32 %f479, %f478, %f1640;
|
|
setp.eq.f32 %p33, %f63, 0f3F800000;
|
|
selp.f32 %f480, 0f00000000, %f479, %p33;
|
|
cvt.sat.f32.f32 %f481, %f480;
|
|
fma.rn.f32 %f482, %f62, %f62, %f373;
|
|
div.rn.f32 %f75, %f481, %f482;
|
|
mul.f32 %f483, %f1620, %f60;
|
|
fma.rn.f32 %f484, %f1619, %f59, %f483;
|
|
fma.rn.f32 %f485, %f1621, %f61, %f484;
|
|
setp.eq.s32 %p34, %r6, 0;
|
|
selp.f32 %f76, %f485, 0f3F800000, %p34;
|
|
mul.f32 %f486, %f76, 0f40800000;
|
|
cvt.sat.f32.f32 %f77, %f486;
|
|
setp.eq.f32 %p35, %f367, 0f3F800000;
|
|
@%p35 bra $L__BB0_25;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_25:
|
|
setp.eq.s64 %p39, %rd6, 0;
|
|
mov.f32 %f1645, %f377;
|
|
mov.f32 %f1648, %f75;
|
|
@%p39 bra $L__BB0_29;
|
|
|
|
setp.geu.f32 %p40, %f1644, 0f00000000;
|
|
mov.f32 %f1641, %f59;
|
|
mov.f32 %f1642, %f60;
|
|
mov.f32 %f1643, %f61;
|
|
@%p40 bra $L__BB0_28;
|
|
|
|
mul.f32 %f511, %f56, %f390;
|
|
fma.rn.f32 %f512, %f55, %f389, %f511;
|
|
fma.rn.f32 %f514, %f57, %f391, %f512;
|
|
rcp.rn.f32 %f515, %f514;
|
|
mul.f32 %f1641, %f389, %f515;
|
|
mul.f32 %f1642, %f390, %f515;
|
|
mul.f32 %f1643, %f391, %f515;
|
|
neg.f32 %f1644, %f1644;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f516, %f57, %f61;
|
|
mul.f32 %f517, %f56, %f60;
|
|
neg.f32 %f518, %f517;
|
|
mul.f32 %f519, %f55, %f59;
|
|
sub.f32 %f520, %f518, %f519;
|
|
sub.f32 %f521, %f520, %f516;
|
|
setp.gt.f32 %p41, %f521, 0f00000000;
|
|
selp.f32 %f522, 0f3F800000, 0f00000000, %p41;
|
|
mov.f32 %f523, 0f3F800000;
|
|
mul.f32 %f524, %f382, %f1642;
|
|
mul.f32 %f525, %f386, %f1642;
|
|
fma.rn.f32 %f526, %f381, %f1641, %f524;
|
|
fma.rn.f32 %f527, %f385, %f1641, %f525;
|
|
fma.rn.f32 %f528, %f383, %f1643, %f526;
|
|
fma.rn.f32 %f529, %f387, %f1643, %f527;
|
|
fma.rn.f32 %f530, %f1644, %f528, 0f3F000000;
|
|
sub.f32 %f531, %f523, %f530;
|
|
fma.rn.f32 %f532, %f1644, %f529, 0f3F000000;
|
|
tex.2d.v4.f32.f32 {%f533, %f534, %f535, %f536}, [%rd6, {%f531, %f532}];
|
|
mul.f32 %f537, %f522, %f533;
|
|
mul.f32 %f538, %f522, %f534;
|
|
mul.f32 %f539, %f522, %f535;
|
|
mul.f32 %f1645, %f377, %f537;
|
|
mul.f32 %f1646, %f1646, %f538;
|
|
mul.f32 %f1647, %f1647, %f539;
|
|
mov.f32 %f1648, %f75;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_20:
|
|
setp.eq.f32 %p36, %f367, 0f40000000;
|
|
@%p36 bra $L__BB0_23;
|
|
bra.uni $L__BB0_21;
|
|
|
|
$L__BB0_23:
|
|
setp.eq.s64 %p38, %rd6, 0;
|
|
mov.f32 %f1645, %f377;
|
|
mov.f32 %f1648, %f75;
|
|
@%p38 bra $L__BB0_29;
|
|
|
|
mul.f32 %f496, %f382, %f60;
|
|
mul.f32 %f497, %f386, %f60;
|
|
mul.f32 %f498, %f56, %f60;
|
|
fma.rn.f32 %f499, %f381, %f59, %f496;
|
|
fma.rn.f32 %f500, %f385, %f59, %f497;
|
|
fma.rn.f32 %f501, %f55, %f59, %f498;
|
|
fma.rn.f32 %f502, %f383, %f61, %f499;
|
|
fma.rn.f32 %f503, %f387, %f61, %f500;
|
|
fma.rn.f32 %f504, %f57, %f61, %f501;
|
|
tex.cube.v4.f32.f32 {%f505, %f506, %f507, %f508}, [%rd6, {%f502, %f503, %f504, %f504}];
|
|
mul.f32 %f1645, %f377, %f505;
|
|
mul.f32 %f1646, %f1646, %f506;
|
|
mul.f32 %f1647, %f1647, %f507;
|
|
mov.f32 %f1648, %f75;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_21:
|
|
setp.neu.f32 %p37, %f367, 0f40800000;
|
|
mov.f32 %f1645, %f377;
|
|
mov.f32 %f1648, %f75;
|
|
@%p37 bra $L__BB0_29;
|
|
|
|
mul.f32 %f487, %f55, %f59;
|
|
mul.f32 %f488, %f56, %f60;
|
|
neg.f32 %f489, %f488;
|
|
sub.f32 %f490, %f489, %f487;
|
|
mul.f32 %f491, %f57, %f61;
|
|
sub.f32 %f492, %f490, %f491;
|
|
fma.rn.f32 %f493, %f380, %f492, %f1644;
|
|
cvt.sat.f32.f32 %f494, %f493;
|
|
mul.f32 %f495, %f494, %f494;
|
|
mul.f32 %f1648, %f75, %f495;
|
|
mov.f32 %f1645, %f377;
|
|
|
|
$L__BB0_29:
|
|
max.f32 %f555, %f1645, %f1646;
|
|
max.f32 %f556, %f555, %f1647;
|
|
mul.f32 %f557, %f77, %f1648;
|
|
mul.f32 %f558, %f557, %f556;
|
|
setp.lt.f32 %p43, %f558, 0f3727C5AC;
|
|
mov.pred %p209, -1;
|
|
mov.f32 %f1649, 0f00000000;
|
|
mov.f32 %f1650, %f1649;
|
|
mov.f32 %f1651, %f1649;
|
|
mov.f32 %f1652, %f1649;
|
|
mov.f32 %f1653, %f1649;
|
|
mov.f32 %f1654, %f1649;
|
|
mov.f32 %f1655, %f1649;
|
|
mov.f32 %f1656, %f1649;
|
|
mov.f32 %f1657, %f1649;
|
|
mov.f32 %f1658, %f1649;
|
|
mov.f32 %f1659, %f1649;
|
|
mov.f32 %f1660, %f1649;
|
|
mov.f32 %f1661, %f1649;
|
|
mov.f32 %f1662, %f1649;
|
|
mov.f32 %f1663, %f1649;
|
|
@%p43 bra $L__BB0_31;
|
|
|
|
cvt.sat.f32.f32 %f559, %f76;
|
|
mul.f32 %f560, %f1648, %f559;
|
|
mul.f32 %f1650, %f1645, %f560;
|
|
mul.f32 %f1649, %f1646, %f560;
|
|
mul.f32 %f1651, %f1647, %f560;
|
|
mul.f32 %f561, %f1648, 0f3E800000;
|
|
mul.f32 %f562, %f77, %f561;
|
|
mul.f32 %f1652, %f1645, %f562;
|
|
mul.f32 %f1653, %f1646, %f562;
|
|
mul.f32 %f1654, %f1647, %f562;
|
|
mul.f32 %f1655, %f59, %f1652;
|
|
mul.f32 %f1656, %f59, %f1653;
|
|
mul.f32 %f1657, %f59, %f1654;
|
|
mul.f32 %f1658, %f60, %f1652;
|
|
mul.f32 %f1659, %f60, %f1653;
|
|
mul.f32 %f1660, %f60, %f1654;
|
|
mul.f32 %f1661, %f61, %f1652;
|
|
mul.f32 %f1662, %f61, %f1653;
|
|
mul.f32 %f1663, %f61, %f1654;
|
|
mov.pred %p209, 0;
|
|
|
|
$L__BB0_31:
|
|
@%p209 bra $L__BB0_57;
|
|
|
|
setp.eq.s32 %p45, %r44, 0;
|
|
mov.u16 %rs179, 0;
|
|
mov.f32 %f1672, 0f3F800000;
|
|
@%p45 bra $L__BB0_40;
|
|
|
|
abs.s32 %r10, %r44;
|
|
setp.lt.s32 %p46, %r10, 1;
|
|
mov.f32 %f1665, 0f00000000;
|
|
@%p46 bra $L__BB0_39;
|
|
|
|
mov.f32 %f572, 0f38D1B717;
|
|
max.f32 %f573, %f571, %f572;
|
|
and.b32 %r63, %r451, 32;
|
|
setp.eq.s32 %p47, %r63, 0;
|
|
mov.u32 %r450, 0;
|
|
selp.f32 %f574, 0f3F800000, 0f41200000, %p47;
|
|
mul.f32 %f140, %f574, %f573;
|
|
and.b32 %r11, %r10, 1;
|
|
setp.eq.s32 %p48, %r10, 1;
|
|
mov.f32 %f1665, 0f00000000;
|
|
@%p48 bra $L__BB0_37;
|
|
|
|
sub.s32 %r449, %r10, %r11;
|
|
|
|
$L__BB0_36:
|
|
cvt.rn.f32.s32 %f594, %r450;
|
|
add.f32 %f595, %f16, %f594;
|
|
sub.f32 %f596, %f17, %f594;
|
|
mul.f32 %f597, %f595, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f598, %f597;
|
|
sub.f32 %f599, %f597, %f598;
|
|
mul.f32 %f600, %f596, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f601, %f600;
|
|
sub.f32 %f602, %f600, %f601;
|
|
mul.f32 %f603, %f594, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f604, %f603;
|
|
sub.f32 %f605, %f603, %f604;
|
|
add.f32 %f606, %f602, 0f420551EC;
|
|
add.f32 %f607, %f599, 0f420551EC;
|
|
add.f32 %f608, %f605, 0f420551EC;
|
|
mul.f32 %f609, %f599, %f606;
|
|
fma.rn.f32 %f610, %f602, %f607, %f609;
|
|
fma.rn.f32 %f611, %f605, %f608, %f610;
|
|
add.f32 %f612, %f599, %f611;
|
|
add.f32 %f613, %f602, %f611;
|
|
add.f32 %f614, %f605, %f611;
|
|
add.f32 %f615, %f612, %f613;
|
|
mul.f32 %f616, %f614, %f615;
|
|
cvt.rmi.f32.f32 %f617, %f616;
|
|
sub.f32 %f618, %f616, %f617;
|
|
add.f32 %f619, %f612, %f612;
|
|
mul.f32 %f620, %f613, %f619;
|
|
cvt.rmi.f32.f32 %f621, %f620;
|
|
sub.f32 %f622, %f620, %f621;
|
|
mul.f32 %f623, %f612, %f615;
|
|
cvt.rmi.f32.f32 %f624, %f623;
|
|
sub.f32 %f625, %f623, %f624;
|
|
fma.rn.f32 %f626, %f618, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f627, %f622, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f628, %f625, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f629, [%rd5+16];
|
|
ld.global.f32 %f630, [%rd5+4];
|
|
fma.rn.f32 %f631, %f629, %f626, %f630;
|
|
ld.global.f32 %f632, [%rd5+8];
|
|
fma.rn.f32 %f633, %f629, %f627, %f632;
|
|
ld.global.f32 %f634, [%rd5+12];
|
|
fma.rn.f32 %f635, %f629, %f628, %f634;
|
|
sub.f32 %f636, %f631, %f10;
|
|
sub.f32 %f637, %f633, %f11;
|
|
sub.f32 %f638, %f635, %f12;
|
|
mul.f32 %f639, %f637, %f637;
|
|
fma.rn.f32 %f640, %f636, %f636, %f639;
|
|
fma.rn.f32 %f641, %f638, %f638, %f640;
|
|
sqrt.rn.f32 %f583, %f641;
|
|
rcp.rn.f32 %f642, %f583;
|
|
mul.f32 %f579, %f642, %f636;
|
|
mul.f32 %f580, %f642, %f637;
|
|
mul.f32 %f581, %f642, %f638;
|
|
mov.f32 %f593, 0f00000000;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r174, 1;
|
|
mov.u32 %r175, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f579,%f580,%f581,%f140,%f583,%f593,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f643, %r65;
|
|
add.f32 %f644, %f1665, %f643;
|
|
add.s32 %r207, %r450, 1;
|
|
cvt.rn.f32.s32 %f645, %r207;
|
|
add.f32 %f646, %f16, %f645;
|
|
sub.f32 %f647, %f17, %f645;
|
|
mul.f32 %f648, %f646, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f649, %f648;
|
|
sub.f32 %f650, %f648, %f649;
|
|
mul.f32 %f651, %f647, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f652, %f651;
|
|
sub.f32 %f653, %f651, %f652;
|
|
mul.f32 %f654, %f645, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f655, %f654;
|
|
sub.f32 %f656, %f654, %f655;
|
|
add.f32 %f657, %f653, 0f420551EC;
|
|
add.f32 %f658, %f650, 0f420551EC;
|
|
add.f32 %f659, %f656, 0f420551EC;
|
|
mul.f32 %f660, %f650, %f657;
|
|
fma.rn.f32 %f661, %f653, %f658, %f660;
|
|
fma.rn.f32 %f662, %f656, %f659, %f661;
|
|
add.f32 %f663, %f650, %f662;
|
|
add.f32 %f664, %f653, %f662;
|
|
add.f32 %f665, %f656, %f662;
|
|
add.f32 %f666, %f663, %f664;
|
|
mul.f32 %f667, %f665, %f666;
|
|
cvt.rmi.f32.f32 %f668, %f667;
|
|
sub.f32 %f669, %f667, %f668;
|
|
add.f32 %f670, %f663, %f663;
|
|
mul.f32 %f671, %f664, %f670;
|
|
cvt.rmi.f32.f32 %f672, %f671;
|
|
sub.f32 %f673, %f671, %f672;
|
|
mul.f32 %f674, %f663, %f666;
|
|
cvt.rmi.f32.f32 %f675, %f674;
|
|
sub.f32 %f676, %f674, %f675;
|
|
fma.rn.f32 %f677, %f669, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f678, %f673, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f679, %f676, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f680, [%rd5+16];
|
|
ld.global.f32 %f681, [%rd5+4];
|
|
fma.rn.f32 %f682, %f680, %f677, %f681;
|
|
ld.global.f32 %f683, [%rd5+8];
|
|
fma.rn.f32 %f684, %f680, %f678, %f683;
|
|
ld.global.f32 %f685, [%rd5+12];
|
|
fma.rn.f32 %f686, %f680, %f679, %f685;
|
|
sub.f32 %f687, %f682, %f10;
|
|
sub.f32 %f688, %f684, %f11;
|
|
sub.f32 %f689, %f686, %f12;
|
|
mul.f32 %f690, %f688, %f688;
|
|
fma.rn.f32 %f691, %f687, %f687, %f690;
|
|
fma.rn.f32 %f692, %f689, %f689, %f691;
|
|
sqrt.rn.f32 %f592, %f692;
|
|
rcp.rn.f32 %f693, %f592;
|
|
mul.f32 %f588, %f693, %f687;
|
|
mul.f32 %f589, %f693, %f688;
|
|
mul.f32 %f590, %f693, %f689;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f588,%f589,%f590,%f140,%f592,%f593,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f694, %r136;
|
|
add.f32 %f1665, %f644, %f694;
|
|
add.s32 %r450, %r450, 2;
|
|
add.s32 %r449, %r449, -2;
|
|
setp.ne.s32 %p49, %r449, 0;
|
|
@%p49 bra $L__BB0_36;
|
|
|
|
$L__BB0_37:
|
|
setp.eq.s32 %p50, %r11, 0;
|
|
@%p50 bra $L__BB0_39;
|
|
|
|
cvt.rn.f32.s32 %f704, %r450;
|
|
add.f32 %f705, %f16, %f704;
|
|
sub.f32 %f706, %f17, %f704;
|
|
mul.f32 %f707, %f705, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f708, %f707;
|
|
sub.f32 %f709, %f707, %f708;
|
|
mul.f32 %f710, %f706, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f711, %f710;
|
|
sub.f32 %f712, %f710, %f711;
|
|
mul.f32 %f713, %f704, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f714, %f713;
|
|
sub.f32 %f715, %f713, %f714;
|
|
add.f32 %f716, %f712, 0f420551EC;
|
|
add.f32 %f717, %f709, 0f420551EC;
|
|
add.f32 %f718, %f715, 0f420551EC;
|
|
mul.f32 %f719, %f709, %f716;
|
|
fma.rn.f32 %f720, %f712, %f717, %f719;
|
|
fma.rn.f32 %f721, %f715, %f718, %f720;
|
|
add.f32 %f722, %f709, %f721;
|
|
add.f32 %f723, %f712, %f721;
|
|
add.f32 %f724, %f715, %f721;
|
|
add.f32 %f725, %f722, %f723;
|
|
mul.f32 %f726, %f724, %f725;
|
|
cvt.rmi.f32.f32 %f727, %f726;
|
|
sub.f32 %f728, %f726, %f727;
|
|
add.f32 %f729, %f722, %f722;
|
|
mul.f32 %f730, %f723, %f729;
|
|
cvt.rmi.f32.f32 %f731, %f730;
|
|
sub.f32 %f732, %f730, %f731;
|
|
mul.f32 %f733, %f722, %f725;
|
|
cvt.rmi.f32.f32 %f734, %f733;
|
|
sub.f32 %f735, %f733, %f734;
|
|
fma.rn.f32 %f736, %f728, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f737, %f732, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f738, %f735, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f739, [%rd5+16];
|
|
ld.global.f32 %f740, [%rd5+4];
|
|
fma.rn.f32 %f741, %f739, %f736, %f740;
|
|
ld.global.f32 %f742, [%rd5+8];
|
|
fma.rn.f32 %f743, %f739, %f737, %f742;
|
|
ld.global.f32 %f744, [%rd5+12];
|
|
fma.rn.f32 %f745, %f739, %f738, %f744;
|
|
sub.f32 %f746, %f741, %f10;
|
|
sub.f32 %f747, %f743, %f11;
|
|
sub.f32 %f748, %f745, %f12;
|
|
mul.f32 %f749, %f747, %f747;
|
|
fma.rn.f32 %f750, %f746, %f746, %f749;
|
|
fma.rn.f32 %f751, %f748, %f748, %f750;
|
|
sqrt.rn.f32 %f702, %f751;
|
|
rcp.rn.f32 %f752, %f702;
|
|
mul.f32 %f698, %f752, %f746;
|
|
mul.f32 %f699, %f752, %f747;
|
|
mul.f32 %f700, %f752, %f748;
|
|
mov.f32 %f703, 0f00000000;
|
|
mov.u32 %r244, 2;
|
|
mov.u32 %r246, 1;
|
|
mov.u32 %r247, 1065353216;
|
|
mov.u32 %r278, 0;
|
|
// begin inline asm
|
|
call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f698,%f699,%f700,%f140,%f702,%f703,%r246,%r278,%r246,%r244,%r246,%r246,%r247,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
|
|
// end inline asm
|
|
mov.b32 %f753, %r208;
|
|
add.f32 %f1665, %f1665, %f753;
|
|
|
|
$L__BB0_39:
|
|
cvt.rn.f32.s32 %f754, %r10;
|
|
div.rn.f32 %f1672, %f1665, %f754;
|
|
shr.u32 %r279, %r44, 31;
|
|
cvt.u16.u32 %rs179, %r279;
|
|
|
|
$L__BB0_40:
|
|
fma.rn.f32 %f1673, %f1650, %f1672, %f1673;
|
|
fma.rn.f32 %f1674, %f1649, %f1672, %f1674;
|
|
fma.rn.f32 %f1675, %f1651, %f1672, %f1675;
|
|
fma.rn.f32 %f1676, %f1652, %f1672, %f1676;
|
|
fma.rn.f32 %f1677, %f1653, %f1672, %f1677;
|
|
fma.rn.f32 %f1678, %f1654, %f1672, %f1678;
|
|
fma.rn.f32 %f1679, %f1655, %f1672, %f1679;
|
|
fma.rn.f32 %f1680, %f1656, %f1672, %f1680;
|
|
fma.rn.f32 %f1681, %f1657, %f1672, %f1681;
|
|
fma.rn.f32 %f1682, %f1658, %f1672, %f1682;
|
|
fma.rn.f32 %f1683, %f1659, %f1672, %f1683;
|
|
fma.rn.f32 %f1684, %f1660, %f1672, %f1684;
|
|
fma.rn.f32 %f1685, %f1661, %f1672, %f1685;
|
|
fma.rn.f32 %f1686, %f1662, %f1672, %f1686;
|
|
fma.rn.f32 %f1687, %f1663, %f1672, %f1687;
|
|
setp.eq.s16 %p51, %rs179, 0;
|
|
@%p51 bra $L__BB0_56;
|
|
|
|
mul.f32 %f756, %f1655, 0f3F000000;
|
|
mul.f32 %f757, %f1658, 0f3F000000;
|
|
mul.f32 %f758, %f757, %f757;
|
|
fma.rn.f32 %f759, %f756, %f756, %f758;
|
|
mul.f32 %f760, %f1661, 0f3F000000;
|
|
fma.rn.f32 %f761, %f760, %f760, %f759;
|
|
sqrt.rn.f32 %f762, %f761;
|
|
rcp.rn.f32 %f763, %f762;
|
|
mov.f32 %f764, 0f3F800000;
|
|
mul.f32 %f765, %f756, %f763;
|
|
mul.f32 %f766, %f757, %f763;
|
|
mul.f32 %f767, %f760, %f763;
|
|
mul.f32 %f768, %f1620, %f766;
|
|
fma.rn.f32 %f769, %f1619, %f765, %f768;
|
|
fma.rn.f32 %f770, %f1621, %f767, %f769;
|
|
fma.rn.f32 %f164, %f770, 0f3F000000, 0f3F000000;
|
|
add.f32 %f771, %f762, %f762;
|
|
div.rn.f32 %f772, %f771, %f1652;
|
|
add.f32 %f165, %f772, 0f3F800000;
|
|
div.rn.f32 %f773, %f762, %f1652;
|
|
sub.f32 %f774, %f764, %f773;
|
|
add.f32 %f775, %f773, 0f3F800000;
|
|
div.rn.f32 %f166, %f774, %f775;
|
|
sub.f32 %f776, %f764, %f166;
|
|
add.f32 %f777, %f165, 0f3F800000;
|
|
mul.f32 %f167, %f776, %f777;
|
|
mul.f32 %f778, %f165, 0f3F000000;
|
|
cvt.rzi.f32.f32 %f779, %f778;
|
|
add.f32 %f780, %f779, %f779;
|
|
sub.f32 %f781, %f165, %f780;
|
|
abs.f32 %f168, %f781;
|
|
abs.f32 %f169, %f164;
|
|
setp.lt.f32 %p52, %f169, 0f00800000;
|
|
mul.f32 %f782, %f169, 0f4B800000;
|
|
selp.f32 %f783, %f782, %f169, %p52;
|
|
selp.f32 %f784, 0fC3170000, 0fC2FE0000, %p52;
|
|
mov.b32 %r280, %f783;
|
|
and.b32 %r281, %r280, 8388607;
|
|
or.b32 %r282, %r281, 1065353216;
|
|
mov.b32 %f785, %r282;
|
|
shr.u32 %r283, %r280, 23;
|
|
cvt.rn.f32.u32 %f786, %r283;
|
|
add.f32 %f787, %f784, %f786;
|
|
setp.gt.f32 %p53, %f785, 0f3FB504F3;
|
|
mul.f32 %f788, %f785, 0f3F000000;
|
|
add.f32 %f789, %f787, 0f3F800000;
|
|
selp.f32 %f790, %f789, %f787, %p53;
|
|
selp.f32 %f791, %f788, %f785, %p53;
|
|
add.f32 %f792, %f791, 0fBF800000;
|
|
add.f32 %f793, %f791, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f794, %f793;
|
|
add.f32 %f795, %f792, %f792;
|
|
mul.f32 %f796, %f795, %f794;
|
|
mul.f32 %f797, %f796, %f796;
|
|
mov.f32 %f798, 0f3C4CAF63;
|
|
mov.f32 %f799, 0f3B18F0FE;
|
|
fma.rn.f32 %f800, %f799, %f797, %f798;
|
|
mov.f32 %f801, 0f3DAAAABD;
|
|
fma.rn.f32 %f802, %f800, %f797, %f801;
|
|
mul.rn.f32 %f803, %f802, %f797;
|
|
mul.rn.f32 %f804, %f803, %f796;
|
|
sub.f32 %f805, %f792, %f796;
|
|
add.f32 %f806, %f805, %f805;
|
|
neg.f32 %f807, %f796;
|
|
fma.rn.f32 %f808, %f807, %f792, %f806;
|
|
mul.rn.f32 %f809, %f794, %f808;
|
|
add.f32 %f810, %f804, %f796;
|
|
sub.f32 %f811, %f796, %f810;
|
|
add.f32 %f812, %f804, %f811;
|
|
add.f32 %f813, %f809, %f812;
|
|
add.f32 %f814, %f810, %f813;
|
|
sub.f32 %f815, %f810, %f814;
|
|
add.f32 %f816, %f813, %f815;
|
|
mov.f32 %f817, 0f3F317200;
|
|
mul.rn.f32 %f818, %f790, %f817;
|
|
mov.f32 %f819, 0f35BFBE8E;
|
|
mul.rn.f32 %f820, %f790, %f819;
|
|
add.f32 %f821, %f818, %f814;
|
|
sub.f32 %f822, %f818, %f821;
|
|
add.f32 %f823, %f814, %f822;
|
|
add.f32 %f824, %f816, %f823;
|
|
add.f32 %f825, %f820, %f824;
|
|
add.f32 %f826, %f821, %f825;
|
|
sub.f32 %f827, %f821, %f826;
|
|
add.f32 %f828, %f825, %f827;
|
|
abs.f32 %f170, %f165;
|
|
setp.gt.f32 %p54, %f170, 0f77F684DF;
|
|
mul.f32 %f829, %f165, 0f39000000;
|
|
selp.f32 %f830, %f829, %f165, %p54;
|
|
mul.rn.f32 %f831, %f830, %f826;
|
|
neg.f32 %f832, %f831;
|
|
fma.rn.f32 %f833, %f830, %f826, %f832;
|
|
fma.rn.f32 %f834, %f830, %f828, %f833;
|
|
mov.f32 %f835, 0f00000000;
|
|
fma.rn.f32 %f836, %f835, %f826, %f834;
|
|
add.rn.f32 %f837, %f831, %f836;
|
|
neg.f32 %f838, %f837;
|
|
add.rn.f32 %f839, %f831, %f838;
|
|
add.rn.f32 %f840, %f839, %f836;
|
|
mov.b32 %r284, %f837;
|
|
setp.eq.s32 %p55, %r284, 1118925336;
|
|
add.s32 %r285, %r284, -1;
|
|
mov.b32 %f841, %r285;
|
|
add.f32 %f842, %f840, 0f37000000;
|
|
selp.f32 %f171, %f842, %f840, %p55;
|
|
selp.f32 %f843, %f841, %f837, %p55;
|
|
mov.f32 %f844, 0f3FB8AA3B;
|
|
mul.rn.f32 %f845, %f843, %f844;
|
|
cvt.rzi.f32.f32 %f846, %f845;
|
|
abs.f32 %f847, %f846;
|
|
setp.gt.f32 %p56, %f847, 0f42FC0000;
|
|
mov.b32 %r286, %f846;
|
|
and.b32 %r287, %r286, -2147483648;
|
|
or.b32 %r288, %r287, 1123811328;
|
|
mov.b32 %f848, %r288;
|
|
selp.f32 %f849, %f848, %f846, %p56;
|
|
mov.f32 %f850, 0fBF317218;
|
|
fma.rn.f32 %f851, %f849, %f850, %f843;
|
|
mov.f32 %f852, 0f3102E308;
|
|
fma.rn.f32 %f853, %f849, %f852, %f851;
|
|
mul.f32 %f854, %f853, 0f3FB8AA3B;
|
|
add.f32 %f855, %f849, 0f4B40007F;
|
|
mov.b32 %r289, %f855;
|
|
shl.b32 %r290, %r289, 23;
|
|
mov.b32 %f856, %r290;
|
|
ex2.approx.ftz.f32 %f857, %f854;
|
|
mul.f32 %f172, %f857, %f856;
|
|
setp.eq.f32 %p57, %f172, 0f7F800000;
|
|
mov.f32 %f1669, 0f7F800000;
|
|
@%p57 bra $L__BB0_43;
|
|
|
|
fma.rn.f32 %f1669, %f172, %f171, %f172;
|
|
|
|
$L__BB0_43:
|
|
setp.lt.f32 %p58, %f164, 0f00000000;
|
|
setp.eq.f32 %p59, %f168, 0f3F800000;
|
|
and.pred %p3, %p59, %p58;
|
|
setp.eq.f32 %p60, %f164, 0f00000000;
|
|
@%p60 bra $L__BB0_47;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_47:
|
|
add.f32 %f861, %f164, %f164;
|
|
mov.b32 %r293, %f861;
|
|
selp.b32 %r294, %r293, 0, %p59;
|
|
or.b32 %r295, %r294, 2139095040;
|
|
setp.lt.f32 %p64, %f165, 0f00000000;
|
|
selp.b32 %r296, %r295, %r294, %p64;
|
|
mov.b32 %f1671, %r296;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_44:
|
|
mov.b32 %r291, %f1669;
|
|
xor.b32 %r292, %r291, -2147483648;
|
|
mov.b32 %f858, %r292;
|
|
selp.f32 %f1671, %f858, %f1669, %p3;
|
|
setp.geu.f32 %p61, %f164, 0f00000000;
|
|
@%p61 bra $L__BB0_48;
|
|
|
|
cvt.rzi.f32.f32 %f859, %f165;
|
|
setp.eq.f32 %p62, %f859, %f165;
|
|
@%p62 bra $L__BB0_48;
|
|
|
|
mov.f32 %f1671, 0f7FFFFFFF;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f862, %f169, %f170;
|
|
mov.b32 %r297, %f862;
|
|
setp.lt.s32 %p65, %r297, 2139095040;
|
|
@%p65 bra $L__BB0_55;
|
|
|
|
setp.gtu.f32 %p66, %f169, 0f7F800000;
|
|
setp.gtu.f32 %p67, %f170, 0f7F800000;
|
|
or.pred %p68, %p66, %p67;
|
|
@%p68 bra $L__BB0_54;
|
|
bra.uni $L__BB0_50;
|
|
|
|
$L__BB0_54:
|
|
add.f32 %f1671, %f165, %f164;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_50:
|
|
setp.eq.f32 %p69, %f170, 0f7F800000;
|
|
@%p69 bra $L__BB0_53;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_53:
|
|
setp.gt.f32 %p72, %f169, 0f3F800000;
|
|
selp.b32 %r301, 2139095040, 0, %p72;
|
|
xor.b32 %r302, %r301, 2139095040;
|
|
setp.lt.f32 %p73, %f165, 0f00000000;
|
|
selp.b32 %r303, %r302, %r301, %p73;
|
|
mov.b32 %f863, %r303;
|
|
setp.eq.f32 %p74, %f164, 0fBF800000;
|
|
selp.f32 %f1671, 0f3F800000, %f863, %p74;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_51:
|
|
setp.neu.f32 %p70, %f169, 0f7F800000;
|
|
@%p70 bra $L__BB0_55;
|
|
|
|
setp.ge.f32 %p71, %f165, 0f00000000;
|
|
selp.b32 %r298, 2139095040, 0, %p71;
|
|
or.b32 %r299, %r298, -2147483648;
|
|
selp.b32 %r300, %r299, %r298, %p3;
|
|
mov.b32 %f1671, %r300;
|
|
|
|
$L__BB0_55:
|
|
setp.eq.f32 %p75, %f165, 0f00000000;
|
|
setp.eq.f32 %p76, %f164, 0f3F800000;
|
|
or.pred %p77, %p75, %p76;
|
|
selp.f32 %f864, 0f3F800000, %f1671, %p77;
|
|
fma.rn.f32 %f865, %f167, %f864, %f166;
|
|
mul.f32 %f866, %f1652, %f865;
|
|
div.rn.f32 %f867, %f866, %f377;
|
|
div.rn.f32 %f868, %f867, %f75;
|
|
cvt.sat.f32.f32 %f869, %f868;
|
|
mul.f32 %f1672, %f1672, %f869;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f1688, %f1688, %f1672;
|
|
|
|
$L__BB0_57:
|
|
cvt.u64.u32 %rd77, %r447;
|
|
cvt.u32.u64 %r304, %rd77;
|
|
add.s32 %r447, %r304, 1;
|
|
setp.lt.u32 %p78, %r447, %r5;
|
|
@%p78 bra $L__BB0_7;
|
|
bra.uni $L__BB0_59;
|
|
|
|
$L__BB0_58:
|
|
mov.f32 %f1673, 0f00000000;
|
|
ld.const.u32 %r451, [params+104];
|
|
mov.f32 %f1674, %f1673;
|
|
mov.f32 %f1675, %f1673;
|
|
mov.f32 %f1676, %f1673;
|
|
mov.f32 %f1677, %f1673;
|
|
mov.f32 %f1678, %f1673;
|
|
mov.f32 %f1679, %f1673;
|
|
mov.f32 %f1680, %f1673;
|
|
mov.f32 %f1681, %f1673;
|
|
mov.f32 %f1682, %f1673;
|
|
mov.f32 %f1683, %f1673;
|
|
mov.f32 %f1684, %f1673;
|
|
mov.f32 %f1685, %f1673;
|
|
mov.f32 %f1686, %f1673;
|
|
mov.f32 %f1687, %f1673;
|
|
mov.f32 %f1688, %f1673;
|
|
|
|
$L__BB0_59:
|
|
and.b32 %r305, %r451, 8;
|
|
setp.eq.s32 %p79, %r305, 0;
|
|
@%p79 bra $L__BB0_73;
|
|
|
|
cvt.sat.f32.f32 %f217, %f1688;
|
|
ld.const.u64 %rd33, [params+192];
|
|
cvta.to.global.u64 %rd7, %rd33;
|
|
ld.const.u32 %r306, [params+184];
|
|
mad.lo.s32 %r307, %r306, %r4, %r3;
|
|
cvt.u64.u32 %rd8, %r307;
|
|
mov.f32 %f887, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f888, %f887;
|
|
add.f32 %f889, %f888, %f888;
|
|
mov.f32 %f890, 0f3EE8BA2E;
|
|
sub.f32 %f891, %f890, %f889;
|
|
abs.f32 %f218, %f891;
|
|
abs.f32 %f219, %f217;
|
|
setp.lt.f32 %p80, %f219, 0f00800000;
|
|
mul.f32 %f892, %f219, 0f4B800000;
|
|
selp.f32 %f893, %f892, %f219, %p80;
|
|
selp.f32 %f894, 0fC3170000, 0fC2FE0000, %p80;
|
|
mov.b32 %r308, %f893;
|
|
and.b32 %r309, %r308, 8388607;
|
|
or.b32 %r310, %r309, 1065353216;
|
|
mov.b32 %f895, %r310;
|
|
shr.u32 %r311, %r308, 23;
|
|
cvt.rn.f32.u32 %f896, %r311;
|
|
add.f32 %f897, %f894, %f896;
|
|
setp.gt.f32 %p81, %f895, 0f3FB504F3;
|
|
mul.f32 %f898, %f895, 0f3F000000;
|
|
add.f32 %f899, %f897, 0f3F800000;
|
|
selp.f32 %f900, %f899, %f897, %p81;
|
|
selp.f32 %f901, %f898, %f895, %p81;
|
|
add.f32 %f902, %f901, 0fBF800000;
|
|
add.f32 %f903, %f901, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f904, %f903;
|
|
add.f32 %f905, %f902, %f902;
|
|
mul.f32 %f906, %f905, %f904;
|
|
mul.f32 %f907, %f906, %f906;
|
|
mov.f32 %f908, 0f3C4CAF63;
|
|
mov.f32 %f909, 0f3B18F0FE;
|
|
fma.rn.f32 %f910, %f909, %f907, %f908;
|
|
mov.f32 %f911, 0f3DAAAABD;
|
|
fma.rn.f32 %f912, %f910, %f907, %f911;
|
|
mul.rn.f32 %f913, %f912, %f907;
|
|
mul.rn.f32 %f914, %f913, %f906;
|
|
sub.f32 %f915, %f902, %f906;
|
|
add.f32 %f916, %f915, %f915;
|
|
neg.f32 %f917, %f906;
|
|
fma.rn.f32 %f918, %f917, %f902, %f916;
|
|
mul.rn.f32 %f919, %f904, %f918;
|
|
add.f32 %f920, %f914, %f906;
|
|
sub.f32 %f921, %f906, %f920;
|
|
add.f32 %f922, %f914, %f921;
|
|
add.f32 %f923, %f919, %f922;
|
|
add.f32 %f924, %f920, %f923;
|
|
sub.f32 %f925, %f920, %f924;
|
|
add.f32 %f926, %f923, %f925;
|
|
mov.f32 %f927, 0f3F317200;
|
|
mul.rn.f32 %f928, %f900, %f927;
|
|
mov.f32 %f929, 0f35BFBE8E;
|
|
mul.rn.f32 %f930, %f900, %f929;
|
|
add.f32 %f931, %f928, %f924;
|
|
sub.f32 %f932, %f928, %f931;
|
|
add.f32 %f933, %f924, %f932;
|
|
add.f32 %f934, %f926, %f933;
|
|
add.f32 %f935, %f930, %f934;
|
|
add.f32 %f936, %f931, %f935;
|
|
sub.f32 %f937, %f931, %f936;
|
|
add.f32 %f938, %f935, %f937;
|
|
mul.rn.f32 %f939, %f890, %f936;
|
|
neg.f32 %f940, %f939;
|
|
fma.rn.f32 %f941, %f890, %f936, %f940;
|
|
fma.rn.f32 %f942, %f890, %f938, %f941;
|
|
mov.f32 %f943, 0f00000000;
|
|
fma.rn.f32 %f944, %f943, %f936, %f942;
|
|
add.rn.f32 %f945, %f939, %f944;
|
|
neg.f32 %f946, %f945;
|
|
add.rn.f32 %f947, %f939, %f946;
|
|
add.rn.f32 %f948, %f947, %f944;
|
|
mov.b32 %r312, %f945;
|
|
setp.eq.s32 %p82, %r312, 1118925336;
|
|
add.s32 %r313, %r312, -1;
|
|
mov.b32 %f949, %r313;
|
|
add.f32 %f950, %f948, 0f37000000;
|
|
selp.f32 %f220, %f950, %f948, %p82;
|
|
selp.f32 %f951, %f949, %f945, %p82;
|
|
mov.f32 %f952, 0f3FB8AA3B;
|
|
mul.rn.f32 %f953, %f951, %f952;
|
|
cvt.rzi.f32.f32 %f954, %f953;
|
|
abs.f32 %f955, %f954;
|
|
setp.gt.f32 %p83, %f955, 0f42FC0000;
|
|
mov.b32 %r314, %f954;
|
|
and.b32 %r315, %r314, -2147483648;
|
|
or.b32 %r316, %r315, 1123811328;
|
|
mov.b32 %f956, %r316;
|
|
selp.f32 %f957, %f956, %f954, %p83;
|
|
mov.f32 %f958, 0fBF317218;
|
|
fma.rn.f32 %f959, %f957, %f958, %f951;
|
|
mov.f32 %f960, 0f3102E308;
|
|
fma.rn.f32 %f961, %f957, %f960, %f959;
|
|
mul.f32 %f962, %f961, 0f3FB8AA3B;
|
|
add.f32 %f963, %f957, 0f4B40007F;
|
|
mov.b32 %r317, %f963;
|
|
shl.b32 %r318, %r317, 23;
|
|
mov.b32 %f964, %r318;
|
|
ex2.approx.ftz.f32 %f965, %f962;
|
|
mul.f32 %f221, %f965, %f964;
|
|
setp.eq.f32 %p84, %f221, 0f7F800000;
|
|
mov.f32 %f1705, 0f7F800000;
|
|
@%p84 bra $L__BB0_62;
|
|
|
|
fma.rn.f32 %f1705, %f221, %f220, %f221;
|
|
|
|
$L__BB0_62:
|
|
setp.lt.f32 %p85, %f217, 0f00000000;
|
|
setp.eq.f32 %p86, %f218, 0f3F800000;
|
|
and.pred %p4, %p85, %p86;
|
|
setp.eq.f32 %p87, %f217, 0f00000000;
|
|
@%p87 bra $L__BB0_66;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f970, %f217, %f217;
|
|
selp.f32 %f1707, %f970, 0f00000000, %p86;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_170:
|
|
mov.f32 %f1579, 0f00000000;
|
|
mov.u32 %r453, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1579;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1579;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1579;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs116, 0;
|
|
st.global.v4.u16 [%rd16], {%rs113, %rs114, %rs115, %rs116};
|
|
|
|
$L__BB0_171:
|
|
ld.const.u64 %rd65, [params+256];
|
|
cvta.to.global.u64 %rd66, %rd65;
|
|
ld.const.u32 %r439, [params+248];
|
|
mad.lo.s32 %r440, %r439, %r4, %r3;
|
|
mul.wide.u32 %rd67, %r440, 8;
|
|
add.s64 %rd17, %rd66, %rd67;
|
|
setp.eq.s32 %p205, %r453, 0;
|
|
@%p205 bra $L__BB0_173;
|
|
|
|
ld.global.v4.u16 {%rs123, %rs124, %rs125, %rs126}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1580, %rs123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1581, %rs124;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1582, %rs125;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1583, %f1580, 0f00000000;
|
|
add.f32 %f1584, %f1581, 0f00000000;
|
|
add.f32 %f1585, %f1582, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1585;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1584;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1583;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs127, 0;
|
|
st.global.v4.u16 [%rd17], {%rs120, %rs121, %rs122, %rs127};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_173:
|
|
mov.f32 %f1588, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1588;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1588;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1588;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs131, 0;
|
|
st.global.v4.u16 [%rd17], {%rs128, %rs129, %rs130, %rs131};
|
|
|
|
$L__BB0_174:
|
|
ld.const.u64 %rd68, [params+272];
|
|
cvta.to.global.u64 %rd69, %rd68;
|
|
ld.const.u32 %r441, [params+264];
|
|
mad.lo.s32 %r442, %r441, %r4, %r3;
|
|
mul.wide.u32 %rd70, %r442, 8;
|
|
add.s64 %rd18, %rd69, %rd70;
|
|
@%p205 bra $L__BB0_176;
|
|
|
|
ld.global.v4.u16 {%rs138, %rs139, %rs140, %rs141}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1589, %rs138;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1590, %rs139;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1591, %rs140;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1592, %f1589, 0f00000000;
|
|
add.f32 %f1593, %f1590, 0f00000000;
|
|
add.f32 %f1594, %f1591, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1594;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1593;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1592;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs142, 0;
|
|
st.global.v4.u16 [%rd18], {%rs135, %rs136, %rs137, %rs142};
|
|
bra.uni $L__BB0_177;
|
|
|
|
$L__BB0_176:
|
|
mov.f32 %f1597, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1597;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1597;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1597;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs146, 0;
|
|
st.global.v4.u16 [%rd18], {%rs143, %rs144, %rs145, %rs146};
|
|
|
|
$L__BB0_177:
|
|
ld.const.u64 %rd71, [params+288];
|
|
cvta.to.global.u64 %rd72, %rd71;
|
|
ld.const.u32 %r443, [params+280];
|
|
mad.lo.s32 %r444, %r443, %r4, %r3;
|
|
mul.wide.u32 %rd73, %r444, 8;
|
|
add.s64 %rd19, %rd72, %rd73;
|
|
@%p205 bra $L__BB0_179;
|
|
|
|
ld.global.v4.u16 {%rs153, %rs154, %rs155, %rs156}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1598, %rs153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1599, %rs154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1600, %rs155;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1601, %f1598, 0f00000000;
|
|
add.f32 %f1602, %f1599, 0f00000000;
|
|
add.f32 %f1603, %f1600, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1603;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1602;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1601;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs157, 0;
|
|
st.global.v4.u16 [%rd19], {%rs150, %rs151, %rs152, %rs157};
|
|
bra.uni $L__BB0_180;
|
|
|
|
$L__BB0_179:
|
|
mov.f32 %f1606, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1606;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1606;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1606;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs161, 0;
|
|
st.global.v4.u16 [%rd19], {%rs158, %rs159, %rs160, %rs161};
|
|
|
|
$L__BB0_180:
|
|
ld.const.u64 %rd74, [params+304];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r445, [params+296];
|
|
mad.lo.s32 %r446, %r445, %r4, %r3;
|
|
mul.wide.u32 %rd76, %r446, 8;
|
|
add.s64 %rd20, %rd75, %rd76;
|
|
@%p205 bra $L__BB0_182;
|
|
|
|
ld.global.v4.u16 {%rs168, %rs169, %rs170, %rs171}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1607, %rs168;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1608, %rs169;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1609, %rs170;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1610, %f1607, 0f00000000;
|
|
add.f32 %f1611, %f1608, 0f00000000;
|
|
add.f32 %f1612, %f1609, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1612;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1611;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1610;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs172, 0;
|
|
st.global.v4.u16 [%rd20], {%rs165, %rs166, %rs167, %rs172};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_182:
|
|
mov.f32 %f1615, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs175, %f1615;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs174, %f1615;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1615;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs176, 0;
|
|
st.global.v4.u16 [%rd20], {%rs173, %rs174, %rs175, %rs176};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_63:
|
|
mov.b32 %r319, %f1705;
|
|
xor.b32 %r320, %r319, -2147483648;
|
|
mov.b32 %f966, %r320;
|
|
selp.f32 %f1707, %f966, %f1705, %p4;
|
|
setp.geu.f32 %p88, %f217, 0f00000000;
|
|
@%p88 bra $L__BB0_67;
|
|
|
|
mov.f32 %f967, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f968, %f967;
|
|
setp.eq.f32 %p89, %f968, 0f3EE8BA2E;
|
|
@%p89 bra $L__BB0_67;
|
|
|
|
mov.f32 %f1707, 0f7FFFFFFF;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f971, %f219, 0f3EE8BA2E;
|
|
mov.b32 %r321, %f971;
|
|
setp.lt.s32 %p91, %r321, 2139095040;
|
|
@%p91 bra $L__BB0_72;
|
|
|
|
setp.gtu.f32 %p92, %f219, 0f7F800000;
|
|
@%p92 bra $L__BB0_71;
|
|
bra.uni $L__BB0_69;
|
|
|
|
$L__BB0_71:
|
|
add.f32 %f1707, %f217, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_69:
|
|
setp.neu.f32 %p93, %f219, 0f7F800000;
|
|
@%p93 bra $L__BB0_72;
|
|
|
|
selp.f32 %f1707, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_72:
|
|
mul.f32 %f972, %f1707, 0f437F0000;
|
|
setp.eq.f32 %p94, %f217, 0f3F800000;
|
|
selp.f32 %f973, 0f437F0000, %f972, %p94;
|
|
cvt.rzi.u32.f32 %r322, %f973;
|
|
shl.b64 %rd34, %rd8, 1;
|
|
add.s64 %rd35, %rd7, %rd34;
|
|
cvt.u16.u32 %rs18, %r322;
|
|
mov.u16 %rs19, 255;
|
|
st.global.v2.u8 [%rd35], {%rs18, %rs19};
|
|
|
|
$L__BB0_73:
|
|
and.b32 %r323, %r451, 1;
|
|
setp.eq.b32 %p95, %r323, 1;
|
|
mov.pred %p96, 0;
|
|
xor.pred %p97, %p95, %p96;
|
|
not.pred %p98, %p97;
|
|
@%p98 bra $L__BB0_147;
|
|
|
|
mov.f32 %f975, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f976, %f975;
|
|
add.f32 %f977, %f976, %f976;
|
|
mov.f32 %f978, 0f3EE66666;
|
|
sub.f32 %f979, %f978, %f977;
|
|
abs.f32 %f230, %f979;
|
|
abs.f32 %f231, %f1673;
|
|
setp.lt.f32 %p99, %f231, 0f00800000;
|
|
mul.f32 %f980, %f231, 0f4B800000;
|
|
selp.f32 %f981, %f980, %f231, %p99;
|
|
selp.f32 %f982, 0fC3170000, 0fC2FE0000, %p99;
|
|
mov.b32 %r324, %f981;
|
|
and.b32 %r325, %r324, 8388607;
|
|
or.b32 %r326, %r325, 1065353216;
|
|
mov.b32 %f983, %r326;
|
|
shr.u32 %r327, %r324, 23;
|
|
cvt.rn.f32.u32 %f984, %r327;
|
|
add.f32 %f985, %f982, %f984;
|
|
setp.gt.f32 %p100, %f983, 0f3FB504F3;
|
|
mul.f32 %f986, %f983, 0f3F000000;
|
|
add.f32 %f987, %f985, 0f3F800000;
|
|
selp.f32 %f988, %f987, %f985, %p100;
|
|
selp.f32 %f989, %f986, %f983, %p100;
|
|
add.f32 %f990, %f989, 0fBF800000;
|
|
add.f32 %f991, %f989, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f992, %f991;
|
|
add.f32 %f993, %f990, %f990;
|
|
mul.f32 %f994, %f993, %f992;
|
|
mul.f32 %f995, %f994, %f994;
|
|
mov.f32 %f996, 0f3C4CAF63;
|
|
mov.f32 %f997, 0f3B18F0FE;
|
|
fma.rn.f32 %f998, %f997, %f995, %f996;
|
|
mov.f32 %f999, 0f3DAAAABD;
|
|
fma.rn.f32 %f1000, %f998, %f995, %f999;
|
|
mul.rn.f32 %f1001, %f1000, %f995;
|
|
mul.rn.f32 %f1002, %f1001, %f994;
|
|
sub.f32 %f1003, %f990, %f994;
|
|
add.f32 %f1004, %f1003, %f1003;
|
|
neg.f32 %f1005, %f994;
|
|
fma.rn.f32 %f1006, %f1005, %f990, %f1004;
|
|
mul.rn.f32 %f1007, %f992, %f1006;
|
|
add.f32 %f1008, %f1002, %f994;
|
|
sub.f32 %f1009, %f994, %f1008;
|
|
add.f32 %f1010, %f1002, %f1009;
|
|
add.f32 %f1011, %f1007, %f1010;
|
|
add.f32 %f1012, %f1008, %f1011;
|
|
sub.f32 %f1013, %f1008, %f1012;
|
|
add.f32 %f1014, %f1011, %f1013;
|
|
mov.f32 %f1015, 0f3F317200;
|
|
mul.rn.f32 %f1016, %f988, %f1015;
|
|
mov.f32 %f1017, 0f35BFBE8E;
|
|
mul.rn.f32 %f1018, %f988, %f1017;
|
|
add.f32 %f1019, %f1016, %f1012;
|
|
sub.f32 %f1020, %f1016, %f1019;
|
|
add.f32 %f1021, %f1012, %f1020;
|
|
add.f32 %f1022, %f1014, %f1021;
|
|
add.f32 %f1023, %f1018, %f1022;
|
|
add.f32 %f1024, %f1019, %f1023;
|
|
sub.f32 %f1025, %f1019, %f1024;
|
|
add.f32 %f1026, %f1023, %f1025;
|
|
mul.rn.f32 %f1027, %f978, %f1024;
|
|
neg.f32 %f1028, %f1027;
|
|
fma.rn.f32 %f1029, %f978, %f1024, %f1028;
|
|
fma.rn.f32 %f1030, %f978, %f1026, %f1029;
|
|
mov.f32 %f1031, 0f00000000;
|
|
fma.rn.f32 %f1032, %f1031, %f1024, %f1030;
|
|
add.rn.f32 %f1033, %f1027, %f1032;
|
|
neg.f32 %f1034, %f1033;
|
|
add.rn.f32 %f1035, %f1027, %f1034;
|
|
add.rn.f32 %f1036, %f1035, %f1032;
|
|
mov.b32 %r328, %f1033;
|
|
setp.eq.s32 %p101, %r328, 1118925336;
|
|
add.s32 %r329, %r328, -1;
|
|
mov.b32 %f1037, %r329;
|
|
add.f32 %f1038, %f1036, 0f37000000;
|
|
selp.f32 %f232, %f1038, %f1036, %p101;
|
|
selp.f32 %f1039, %f1037, %f1033, %p101;
|
|
mov.f32 %f1040, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1041, %f1039, %f1040;
|
|
cvt.rzi.f32.f32 %f1042, %f1041;
|
|
abs.f32 %f1043, %f1042;
|
|
setp.gt.f32 %p102, %f1043, 0f42FC0000;
|
|
mov.b32 %r330, %f1042;
|
|
and.b32 %r331, %r330, -2147483648;
|
|
or.b32 %r332, %r331, 1123811328;
|
|
mov.b32 %f1044, %r332;
|
|
selp.f32 %f1045, %f1044, %f1042, %p102;
|
|
mov.f32 %f1046, 0fBF317218;
|
|
fma.rn.f32 %f1047, %f1045, %f1046, %f1039;
|
|
mov.f32 %f1048, 0f3102E308;
|
|
fma.rn.f32 %f1049, %f1045, %f1048, %f1047;
|
|
mul.f32 %f1050, %f1049, 0f3FB8AA3B;
|
|
add.f32 %f1051, %f1045, 0f4B40007F;
|
|
mov.b32 %r333, %f1051;
|
|
shl.b32 %r334, %r333, 23;
|
|
mov.b32 %f1052, %r334;
|
|
ex2.approx.ftz.f32 %f1053, %f1050;
|
|
mul.f32 %f233, %f1053, %f1052;
|
|
setp.eq.f32 %p103, %f233, 0f7F800000;
|
|
mov.f32 %f1708, 0f7F800000;
|
|
@%p103 bra $L__BB0_76;
|
|
|
|
fma.rn.f32 %f1708, %f233, %f232, %f233;
|
|
|
|
$L__BB0_76:
|
|
setp.lt.f32 %p104, %f1673, 0f00000000;
|
|
setp.eq.f32 %p105, %f230, 0f3F800000;
|
|
and.pred %p5, %p104, %p105;
|
|
setp.eq.f32 %p106, %f1673, 0f00000000;
|
|
@%p106 bra $L__BB0_80;
|
|
bra.uni $L__BB0_77;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1058, %f1673, %f1673;
|
|
selp.f32 %f1710, %f1058, 0f00000000, %p105;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_77:
|
|
mov.b32 %r335, %f1708;
|
|
xor.b32 %r336, %r335, -2147483648;
|
|
mov.b32 %f1054, %r336;
|
|
selp.f32 %f1710, %f1054, %f1708, %p5;
|
|
setp.geu.f32 %p107, %f1673, 0f00000000;
|
|
@%p107 bra $L__BB0_81;
|
|
|
|
mov.f32 %f1055, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1056, %f1055;
|
|
setp.eq.f32 %p108, %f1056, 0f3EE66666;
|
|
@%p108 bra $L__BB0_81;
|
|
|
|
mov.f32 %f1710, 0f7FFFFFFF;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f1059, %f231, 0f3EE66666;
|
|
mov.b32 %r337, %f1059;
|
|
setp.lt.s32 %p110, %r337, 2139095040;
|
|
@%p110 bra $L__BB0_86;
|
|
|
|
setp.gtu.f32 %p111, %f231, 0f7F800000;
|
|
@%p111 bra $L__BB0_85;
|
|
bra.uni $L__BB0_83;
|
|
|
|
$L__BB0_85:
|
|
add.f32 %f1710, %f1673, 0f3EE66666;
|
|
bra.uni $L__BB0_86;
|
|
|
|
$L__BB0_83:
|
|
setp.neu.f32 %p112, %f231, 0f7F800000;
|
|
@%p112 bra $L__BB0_86;
|
|
|
|
selp.f32 %f1710, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_86:
|
|
setp.eq.f32 %p113, %f1673, 0f3F800000;
|
|
selp.f32 %f242, 0f3F800000, %f1710, %p113;
|
|
abs.f32 %f243, %f1674;
|
|
setp.lt.f32 %p114, %f243, 0f00800000;
|
|
mul.f32 %f1061, %f243, 0f4B800000;
|
|
selp.f32 %f1062, %f1061, %f243, %p114;
|
|
selp.f32 %f1063, 0fC3170000, 0fC2FE0000, %p114;
|
|
mov.b32 %r338, %f1062;
|
|
and.b32 %r339, %r338, 8388607;
|
|
or.b32 %r340, %r339, 1065353216;
|
|
mov.b32 %f1064, %r340;
|
|
shr.u32 %r341, %r338, 23;
|
|
cvt.rn.f32.u32 %f1065, %r341;
|
|
add.f32 %f1066, %f1063, %f1065;
|
|
setp.gt.f32 %p115, %f1064, 0f3FB504F3;
|
|
mul.f32 %f1067, %f1064, 0f3F000000;
|
|
add.f32 %f1068, %f1066, 0f3F800000;
|
|
selp.f32 %f1069, %f1068, %f1066, %p115;
|
|
selp.f32 %f1070, %f1067, %f1064, %p115;
|
|
add.f32 %f1071, %f1070, 0fBF800000;
|
|
add.f32 %f1072, %f1070, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1073, %f1072;
|
|
add.f32 %f1074, %f1071, %f1071;
|
|
mul.f32 %f1075, %f1074, %f1073;
|
|
mul.f32 %f1076, %f1075, %f1075;
|
|
mov.f32 %f1077, 0f3C4CAF63;
|
|
mov.f32 %f1078, 0f3B18F0FE;
|
|
fma.rn.f32 %f1079, %f1078, %f1076, %f1077;
|
|
mov.f32 %f1080, 0f3DAAAABD;
|
|
fma.rn.f32 %f1081, %f1079, %f1076, %f1080;
|
|
mul.rn.f32 %f1082, %f1081, %f1076;
|
|
mul.rn.f32 %f1083, %f1082, %f1075;
|
|
sub.f32 %f1084, %f1071, %f1075;
|
|
add.f32 %f1085, %f1084, %f1084;
|
|
neg.f32 %f1086, %f1075;
|
|
fma.rn.f32 %f1087, %f1086, %f1071, %f1085;
|
|
mul.rn.f32 %f1088, %f1073, %f1087;
|
|
add.f32 %f1089, %f1083, %f1075;
|
|
sub.f32 %f1090, %f1075, %f1089;
|
|
add.f32 %f1091, %f1083, %f1090;
|
|
add.f32 %f1092, %f1088, %f1091;
|
|
add.f32 %f1093, %f1089, %f1092;
|
|
sub.f32 %f1094, %f1089, %f1093;
|
|
add.f32 %f1095, %f1092, %f1094;
|
|
mov.f32 %f1096, 0f3F317200;
|
|
mul.rn.f32 %f1097, %f1069, %f1096;
|
|
mov.f32 %f1098, 0f35BFBE8E;
|
|
mul.rn.f32 %f1099, %f1069, %f1098;
|
|
add.f32 %f1100, %f1097, %f1093;
|
|
sub.f32 %f1101, %f1097, %f1100;
|
|
add.f32 %f1102, %f1093, %f1101;
|
|
add.f32 %f1103, %f1095, %f1102;
|
|
add.f32 %f1104, %f1099, %f1103;
|
|
add.f32 %f1105, %f1100, %f1104;
|
|
sub.f32 %f1106, %f1100, %f1105;
|
|
add.f32 %f1107, %f1104, %f1106;
|
|
mov.f32 %f1108, 0f3EE66666;
|
|
mul.rn.f32 %f1109, %f1108, %f1105;
|
|
neg.f32 %f1110, %f1109;
|
|
fma.rn.f32 %f1111, %f1108, %f1105, %f1110;
|
|
fma.rn.f32 %f1112, %f1108, %f1107, %f1111;
|
|
mov.f32 %f1113, 0f00000000;
|
|
fma.rn.f32 %f1114, %f1113, %f1105, %f1112;
|
|
add.rn.f32 %f1115, %f1109, %f1114;
|
|
neg.f32 %f1116, %f1115;
|
|
add.rn.f32 %f1117, %f1109, %f1116;
|
|
add.rn.f32 %f1118, %f1117, %f1114;
|
|
mov.b32 %r342, %f1115;
|
|
setp.eq.s32 %p116, %r342, 1118925336;
|
|
add.s32 %r343, %r342, -1;
|
|
mov.b32 %f1119, %r343;
|
|
add.f32 %f1120, %f1118, 0f37000000;
|
|
selp.f32 %f244, %f1120, %f1118, %p116;
|
|
selp.f32 %f1121, %f1119, %f1115, %p116;
|
|
mov.f32 %f1122, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1123, %f1121, %f1122;
|
|
cvt.rzi.f32.f32 %f1124, %f1123;
|
|
abs.f32 %f1125, %f1124;
|
|
setp.gt.f32 %p117, %f1125, 0f42FC0000;
|
|
mov.b32 %r344, %f1124;
|
|
and.b32 %r345, %r344, -2147483648;
|
|
or.b32 %r346, %r345, 1123811328;
|
|
mov.b32 %f1126, %r346;
|
|
selp.f32 %f1127, %f1126, %f1124, %p117;
|
|
mov.f32 %f1128, 0fBF317218;
|
|
fma.rn.f32 %f1129, %f1127, %f1128, %f1121;
|
|
mov.f32 %f1130, 0f3102E308;
|
|
fma.rn.f32 %f1131, %f1127, %f1130, %f1129;
|
|
mul.f32 %f1132, %f1131, 0f3FB8AA3B;
|
|
add.f32 %f1133, %f1127, 0f4B40007F;
|
|
mov.b32 %r347, %f1133;
|
|
shl.b32 %r348, %r347, 23;
|
|
mov.b32 %f1134, %r348;
|
|
ex2.approx.ftz.f32 %f1135, %f1132;
|
|
mul.f32 %f245, %f1135, %f1134;
|
|
setp.eq.f32 %p118, %f245, 0f7F800000;
|
|
mov.f32 %f1711, 0f7F800000;
|
|
@%p118 bra $L__BB0_88;
|
|
|
|
fma.rn.f32 %f1711, %f245, %f244, %f245;
|
|
|
|
$L__BB0_88:
|
|
setp.lt.f32 %p119, %f1674, 0f00000000;
|
|
and.pred %p6, %p119, %p105;
|
|
setp.eq.f32 %p121, %f1674, 0f00000000;
|
|
@%p121 bra $L__BB0_92;
|
|
bra.uni $L__BB0_89;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f1140, %f1674, %f1674;
|
|
selp.f32 %f1713, %f1140, 0f00000000, %p105;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_89:
|
|
mov.b32 %r349, %f1711;
|
|
xor.b32 %r350, %r349, -2147483648;
|
|
mov.b32 %f1136, %r350;
|
|
selp.f32 %f1713, %f1136, %f1711, %p6;
|
|
setp.geu.f32 %p122, %f1674, 0f00000000;
|
|
@%p122 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1137, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1138, %f1137;
|
|
setp.eq.f32 %p123, %f1138, 0f3EE66666;
|
|
@%p123 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1713, 0f7FFFFFFF;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f1141, %f243, 0f3EE66666;
|
|
mov.b32 %r351, %f1141;
|
|
setp.lt.s32 %p125, %r351, 2139095040;
|
|
@%p125 bra $L__BB0_98;
|
|
|
|
setp.gtu.f32 %p126, %f243, 0f7F800000;
|
|
@%p126 bra $L__BB0_97;
|
|
bra.uni $L__BB0_95;
|
|
|
|
$L__BB0_97:
|
|
add.f32 %f1713, %f1674, 0f3EE66666;
|
|
bra.uni $L__BB0_98;
|
|
|
|
$L__BB0_95:
|
|
setp.neu.f32 %p127, %f243, 0f7F800000;
|
|
@%p127 bra $L__BB0_98;
|
|
|
|
selp.f32 %f1713, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_98:
|
|
setp.eq.f32 %p128, %f1674, 0f3F800000;
|
|
selp.f32 %f254, 0f3F800000, %f1713, %p128;
|
|
abs.f32 %f255, %f1675;
|
|
setp.lt.f32 %p129, %f255, 0f00800000;
|
|
mul.f32 %f1143, %f255, 0f4B800000;
|
|
selp.f32 %f1144, %f1143, %f255, %p129;
|
|
selp.f32 %f1145, 0fC3170000, 0fC2FE0000, %p129;
|
|
mov.b32 %r352, %f1144;
|
|
and.b32 %r353, %r352, 8388607;
|
|
or.b32 %r354, %r353, 1065353216;
|
|
mov.b32 %f1146, %r354;
|
|
shr.u32 %r355, %r352, 23;
|
|
cvt.rn.f32.u32 %f1147, %r355;
|
|
add.f32 %f1148, %f1145, %f1147;
|
|
setp.gt.f32 %p130, %f1146, 0f3FB504F3;
|
|
mul.f32 %f1149, %f1146, 0f3F000000;
|
|
add.f32 %f1150, %f1148, 0f3F800000;
|
|
selp.f32 %f1151, %f1150, %f1148, %p130;
|
|
selp.f32 %f1152, %f1149, %f1146, %p130;
|
|
add.f32 %f1153, %f1152, 0fBF800000;
|
|
add.f32 %f1154, %f1152, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1155, %f1154;
|
|
add.f32 %f1156, %f1153, %f1153;
|
|
mul.f32 %f1157, %f1156, %f1155;
|
|
mul.f32 %f1158, %f1157, %f1157;
|
|
mov.f32 %f1159, 0f3C4CAF63;
|
|
mov.f32 %f1160, 0f3B18F0FE;
|
|
fma.rn.f32 %f1161, %f1160, %f1158, %f1159;
|
|
mov.f32 %f1162, 0f3DAAAABD;
|
|
fma.rn.f32 %f1163, %f1161, %f1158, %f1162;
|
|
mul.rn.f32 %f1164, %f1163, %f1158;
|
|
mul.rn.f32 %f1165, %f1164, %f1157;
|
|
sub.f32 %f1166, %f1153, %f1157;
|
|
add.f32 %f1167, %f1166, %f1166;
|
|
neg.f32 %f1168, %f1157;
|
|
fma.rn.f32 %f1169, %f1168, %f1153, %f1167;
|
|
mul.rn.f32 %f1170, %f1155, %f1169;
|
|
add.f32 %f1171, %f1165, %f1157;
|
|
sub.f32 %f1172, %f1157, %f1171;
|
|
add.f32 %f1173, %f1165, %f1172;
|
|
add.f32 %f1174, %f1170, %f1173;
|
|
add.f32 %f1175, %f1171, %f1174;
|
|
sub.f32 %f1176, %f1171, %f1175;
|
|
add.f32 %f1177, %f1174, %f1176;
|
|
mov.f32 %f1178, 0f3F317200;
|
|
mul.rn.f32 %f1179, %f1151, %f1178;
|
|
mov.f32 %f1180, 0f35BFBE8E;
|
|
mul.rn.f32 %f1181, %f1151, %f1180;
|
|
add.f32 %f1182, %f1179, %f1175;
|
|
sub.f32 %f1183, %f1179, %f1182;
|
|
add.f32 %f1184, %f1175, %f1183;
|
|
add.f32 %f1185, %f1177, %f1184;
|
|
add.f32 %f1186, %f1181, %f1185;
|
|
add.f32 %f1187, %f1182, %f1186;
|
|
sub.f32 %f1188, %f1182, %f1187;
|
|
add.f32 %f1189, %f1186, %f1188;
|
|
mov.f32 %f1190, 0f3EE66666;
|
|
mul.rn.f32 %f1191, %f1190, %f1187;
|
|
neg.f32 %f1192, %f1191;
|
|
fma.rn.f32 %f1193, %f1190, %f1187, %f1192;
|
|
fma.rn.f32 %f1194, %f1190, %f1189, %f1193;
|
|
mov.f32 %f1195, 0f00000000;
|
|
fma.rn.f32 %f1196, %f1195, %f1187, %f1194;
|
|
add.rn.f32 %f1197, %f1191, %f1196;
|
|
neg.f32 %f1198, %f1197;
|
|
add.rn.f32 %f1199, %f1191, %f1198;
|
|
add.rn.f32 %f1200, %f1199, %f1196;
|
|
mov.b32 %r356, %f1197;
|
|
setp.eq.s32 %p131, %r356, 1118925336;
|
|
add.s32 %r357, %r356, -1;
|
|
mov.b32 %f1201, %r357;
|
|
add.f32 %f1202, %f1200, 0f37000000;
|
|
selp.f32 %f256, %f1202, %f1200, %p131;
|
|
selp.f32 %f1203, %f1201, %f1197, %p131;
|
|
mov.f32 %f1204, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1205, %f1203, %f1204;
|
|
cvt.rzi.f32.f32 %f1206, %f1205;
|
|
abs.f32 %f1207, %f1206;
|
|
setp.gt.f32 %p132, %f1207, 0f42FC0000;
|
|
mov.b32 %r358, %f1206;
|
|
and.b32 %r359, %r358, -2147483648;
|
|
or.b32 %r360, %r359, 1123811328;
|
|
mov.b32 %f1208, %r360;
|
|
selp.f32 %f1209, %f1208, %f1206, %p132;
|
|
mov.f32 %f1210, 0fBF317218;
|
|
fma.rn.f32 %f1211, %f1209, %f1210, %f1203;
|
|
mov.f32 %f1212, 0f3102E308;
|
|
fma.rn.f32 %f1213, %f1209, %f1212, %f1211;
|
|
mul.f32 %f1214, %f1213, 0f3FB8AA3B;
|
|
add.f32 %f1215, %f1209, 0f4B40007F;
|
|
mov.b32 %r361, %f1215;
|
|
shl.b32 %r362, %r361, 23;
|
|
mov.b32 %f1216, %r362;
|
|
ex2.approx.ftz.f32 %f1217, %f1214;
|
|
mul.f32 %f257, %f1217, %f1216;
|
|
setp.eq.f32 %p133, %f257, 0f7F800000;
|
|
mov.f32 %f1714, 0f7F800000;
|
|
@%p133 bra $L__BB0_100;
|
|
|
|
fma.rn.f32 %f1714, %f257, %f256, %f257;
|
|
|
|
$L__BB0_100:
|
|
setp.lt.f32 %p134, %f1675, 0f00000000;
|
|
and.pred %p7, %p134, %p105;
|
|
setp.eq.f32 %p136, %f1675, 0f00000000;
|
|
@%p136 bra $L__BB0_104;
|
|
bra.uni $L__BB0_101;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1222, %f1675, %f1675;
|
|
selp.f32 %f1716, %f1222, 0f00000000, %p105;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_101:
|
|
mov.b32 %r363, %f1714;
|
|
xor.b32 %r364, %r363, -2147483648;
|
|
mov.b32 %f1218, %r364;
|
|
selp.f32 %f1716, %f1218, %f1714, %p7;
|
|
setp.geu.f32 %p137, %f1675, 0f00000000;
|
|
@%p137 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1219, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1220, %f1219;
|
|
setp.eq.f32 %p138, %f1220, 0f3EE66666;
|
|
@%p138 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1716, 0f7FFFFFFF;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f1223, %f255, 0f3EE66666;
|
|
mov.b32 %r365, %f1223;
|
|
setp.lt.s32 %p140, %r365, 2139095040;
|
|
@%p140 bra $L__BB0_110;
|
|
|
|
setp.gtu.f32 %p141, %f255, 0f7F800000;
|
|
@%p141 bra $L__BB0_109;
|
|
bra.uni $L__BB0_107;
|
|
|
|
$L__BB0_109:
|
|
add.f32 %f1716, %f1675, 0f3EE66666;
|
|
bra.uni $L__BB0_110;
|
|
|
|
$L__BB0_107:
|
|
setp.neu.f32 %p142, %f255, 0f7F800000;
|
|
@%p142 bra $L__BB0_110;
|
|
|
|
selp.f32 %f1716, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_110:
|
|
setp.eq.f32 %p143, %f1675, 0f3F800000;
|
|
mov.f32 %f1225, 0f3F800000;
|
|
selp.f32 %f1226, 0f3F800000, %f1716, %p143;
|
|
ld.const.u64 %rd36, [params+144];
|
|
cvta.to.global.u64 %rd9, %rd36;
|
|
ld.const.u32 %r366, [params+136];
|
|
mad.lo.s32 %r367, %r366, %r4, %r3;
|
|
cvt.u64.u32 %rd10, %r367;
|
|
min.f32 %f1227, %f242, %f1225;
|
|
mov.f32 %f1228, 0f00000000;
|
|
max.f32 %f266, %f1228, %f1227;
|
|
min.f32 %f1229, %f254, %f1225;
|
|
max.f32 %f267, %f1228, %f1229;
|
|
min.f32 %f1230, %f1226, %f1225;
|
|
max.f32 %f268, %f1228, %f1230;
|
|
mov.f32 %f1231, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1232, %f1231;
|
|
add.f32 %f1233, %f1232, %f1232;
|
|
mov.f32 %f1234, 0f3ED55555;
|
|
sub.f32 %f1235, %f1234, %f1233;
|
|
abs.f32 %f269, %f1235;
|
|
abs.f32 %f270, %f266;
|
|
setp.lt.f32 %p144, %f270, 0f00800000;
|
|
mul.f32 %f1236, %f270, 0f4B800000;
|
|
selp.f32 %f1237, %f1236, %f270, %p144;
|
|
selp.f32 %f1238, 0fC3170000, 0fC2FE0000, %p144;
|
|
mov.b32 %r368, %f1237;
|
|
and.b32 %r369, %r368, 8388607;
|
|
or.b32 %r370, %r369, 1065353216;
|
|
mov.b32 %f1239, %r370;
|
|
shr.u32 %r371, %r368, 23;
|
|
cvt.rn.f32.u32 %f1240, %r371;
|
|
add.f32 %f1241, %f1238, %f1240;
|
|
setp.gt.f32 %p145, %f1239, 0f3FB504F3;
|
|
mul.f32 %f1242, %f1239, 0f3F000000;
|
|
add.f32 %f1243, %f1241, 0f3F800000;
|
|
selp.f32 %f1244, %f1243, %f1241, %p145;
|
|
selp.f32 %f1245, %f1242, %f1239, %p145;
|
|
add.f32 %f1246, %f1245, 0fBF800000;
|
|
add.f32 %f1247, %f1245, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1248, %f1247;
|
|
add.f32 %f1249, %f1246, %f1246;
|
|
mul.f32 %f1250, %f1249, %f1248;
|
|
mul.f32 %f1251, %f1250, %f1250;
|
|
mov.f32 %f1252, 0f3C4CAF63;
|
|
mov.f32 %f1253, 0f3B18F0FE;
|
|
fma.rn.f32 %f1254, %f1253, %f1251, %f1252;
|
|
mov.f32 %f1255, 0f3DAAAABD;
|
|
fma.rn.f32 %f1256, %f1254, %f1251, %f1255;
|
|
mul.rn.f32 %f1257, %f1256, %f1251;
|
|
mul.rn.f32 %f1258, %f1257, %f1250;
|
|
sub.f32 %f1259, %f1246, %f1250;
|
|
add.f32 %f1260, %f1259, %f1259;
|
|
neg.f32 %f1261, %f1250;
|
|
fma.rn.f32 %f1262, %f1261, %f1246, %f1260;
|
|
mul.rn.f32 %f1263, %f1248, %f1262;
|
|
add.f32 %f1264, %f1258, %f1250;
|
|
sub.f32 %f1265, %f1250, %f1264;
|
|
add.f32 %f1266, %f1258, %f1265;
|
|
add.f32 %f1267, %f1263, %f1266;
|
|
add.f32 %f1268, %f1264, %f1267;
|
|
sub.f32 %f1269, %f1264, %f1268;
|
|
add.f32 %f1270, %f1267, %f1269;
|
|
mov.f32 %f1271, 0f3F317200;
|
|
mul.rn.f32 %f1272, %f1244, %f1271;
|
|
mov.f32 %f1273, 0f35BFBE8E;
|
|
mul.rn.f32 %f1274, %f1244, %f1273;
|
|
add.f32 %f1275, %f1272, %f1268;
|
|
sub.f32 %f1276, %f1272, %f1275;
|
|
add.f32 %f1277, %f1268, %f1276;
|
|
add.f32 %f1278, %f1270, %f1277;
|
|
add.f32 %f1279, %f1274, %f1278;
|
|
add.f32 %f1280, %f1275, %f1279;
|
|
sub.f32 %f1281, %f1275, %f1280;
|
|
add.f32 %f1282, %f1279, %f1281;
|
|
mul.rn.f32 %f1283, %f1234, %f1280;
|
|
neg.f32 %f1284, %f1283;
|
|
fma.rn.f32 %f1285, %f1234, %f1280, %f1284;
|
|
fma.rn.f32 %f1286, %f1234, %f1282, %f1285;
|
|
fma.rn.f32 %f1287, %f1228, %f1280, %f1286;
|
|
add.rn.f32 %f1288, %f1283, %f1287;
|
|
neg.f32 %f1289, %f1288;
|
|
add.rn.f32 %f1290, %f1283, %f1289;
|
|
add.rn.f32 %f1291, %f1290, %f1287;
|
|
mov.b32 %r372, %f1288;
|
|
setp.eq.s32 %p146, %r372, 1118925336;
|
|
add.s32 %r373, %r372, -1;
|
|
mov.b32 %f1292, %r373;
|
|
add.f32 %f1293, %f1291, 0f37000000;
|
|
selp.f32 %f271, %f1293, %f1291, %p146;
|
|
selp.f32 %f1294, %f1292, %f1288, %p146;
|
|
mov.f32 %f1295, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1296, %f1294, %f1295;
|
|
cvt.rzi.f32.f32 %f1297, %f1296;
|
|
abs.f32 %f1298, %f1297;
|
|
setp.gt.f32 %p147, %f1298, 0f42FC0000;
|
|
mov.b32 %r374, %f1297;
|
|
and.b32 %r375, %r374, -2147483648;
|
|
or.b32 %r376, %r375, 1123811328;
|
|
mov.b32 %f1299, %r376;
|
|
selp.f32 %f1300, %f1299, %f1297, %p147;
|
|
mov.f32 %f1301, 0fBF317218;
|
|
fma.rn.f32 %f1302, %f1300, %f1301, %f1294;
|
|
mov.f32 %f1303, 0f3102E308;
|
|
fma.rn.f32 %f1304, %f1300, %f1303, %f1302;
|
|
mul.f32 %f1305, %f1304, 0f3FB8AA3B;
|
|
add.f32 %f1306, %f1300, 0f4B40007F;
|
|
mov.b32 %r377, %f1306;
|
|
shl.b32 %r378, %r377, 23;
|
|
mov.b32 %f1307, %r378;
|
|
ex2.approx.ftz.f32 %f1308, %f1305;
|
|
mul.f32 %f272, %f1308, %f1307;
|
|
setp.eq.f32 %p148, %f272, 0f7F800000;
|
|
mov.f32 %f1717, 0f7F800000;
|
|
@%p148 bra $L__BB0_112;
|
|
|
|
fma.rn.f32 %f1717, %f272, %f271, %f272;
|
|
|
|
$L__BB0_112:
|
|
setp.lt.f32 %p149, %f266, 0f00000000;
|
|
setp.eq.f32 %p150, %f269, 0f3F800000;
|
|
and.pred %p8, %p149, %p150;
|
|
setp.eq.f32 %p151, %f266, 0f00000000;
|
|
@%p151 bra $L__BB0_116;
|
|
bra.uni $L__BB0_113;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1313, %f266, %f266;
|
|
selp.f32 %f1719, %f1313, 0f00000000, %p150;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_113:
|
|
mov.b32 %r379, %f1717;
|
|
xor.b32 %r380, %r379, -2147483648;
|
|
mov.b32 %f1309, %r380;
|
|
selp.f32 %f1719, %f1309, %f1717, %p8;
|
|
setp.geu.f32 %p152, %f266, 0f00000000;
|
|
@%p152 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1310, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1311, %f1310;
|
|
setp.eq.f32 %p153, %f1311, 0f3ED55555;
|
|
@%p153 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1719, 0f7FFFFFFF;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f1314, %f270, 0f3ED55555;
|
|
mov.b32 %r381, %f1314;
|
|
setp.lt.s32 %p155, %r381, 2139095040;
|
|
@%p155 bra $L__BB0_122;
|
|
|
|
setp.gtu.f32 %p156, %f270, 0f7F800000;
|
|
@%p156 bra $L__BB0_121;
|
|
bra.uni $L__BB0_119;
|
|
|
|
$L__BB0_121:
|
|
add.f32 %f1719, %f266, 0f3ED55555;
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_119:
|
|
setp.neu.f32 %p157, %f270, 0f7F800000;
|
|
@%p157 bra $L__BB0_122;
|
|
|
|
selp.f32 %f1719, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_122:
|
|
abs.f32 %f281, %f267;
|
|
setp.lt.f32 %p158, %f281, 0f00800000;
|
|
mul.f32 %f1316, %f281, 0f4B800000;
|
|
selp.f32 %f1317, %f1316, %f281, %p158;
|
|
selp.f32 %f1318, 0fC3170000, 0fC2FE0000, %p158;
|
|
mov.b32 %r382, %f1317;
|
|
and.b32 %r383, %r382, 8388607;
|
|
or.b32 %r384, %r383, 1065353216;
|
|
mov.b32 %f1319, %r384;
|
|
shr.u32 %r385, %r382, 23;
|
|
cvt.rn.f32.u32 %f1320, %r385;
|
|
add.f32 %f1321, %f1318, %f1320;
|
|
setp.gt.f32 %p159, %f1319, 0f3FB504F3;
|
|
mul.f32 %f1322, %f1319, 0f3F000000;
|
|
add.f32 %f1323, %f1321, 0f3F800000;
|
|
selp.f32 %f1324, %f1323, %f1321, %p159;
|
|
selp.f32 %f1325, %f1322, %f1319, %p159;
|
|
add.f32 %f1326, %f1325, 0fBF800000;
|
|
add.f32 %f1327, %f1325, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1328, %f1327;
|
|
add.f32 %f1329, %f1326, %f1326;
|
|
mul.f32 %f1330, %f1329, %f1328;
|
|
mul.f32 %f1331, %f1330, %f1330;
|
|
mov.f32 %f1332, 0f3C4CAF63;
|
|
mov.f32 %f1333, 0f3B18F0FE;
|
|
fma.rn.f32 %f1334, %f1333, %f1331, %f1332;
|
|
mov.f32 %f1335, 0f3DAAAABD;
|
|
fma.rn.f32 %f1336, %f1334, %f1331, %f1335;
|
|
mul.rn.f32 %f1337, %f1336, %f1331;
|
|
mul.rn.f32 %f1338, %f1337, %f1330;
|
|
sub.f32 %f1339, %f1326, %f1330;
|
|
add.f32 %f1340, %f1339, %f1339;
|
|
neg.f32 %f1341, %f1330;
|
|
fma.rn.f32 %f1342, %f1341, %f1326, %f1340;
|
|
mul.rn.f32 %f1343, %f1328, %f1342;
|
|
add.f32 %f1344, %f1338, %f1330;
|
|
sub.f32 %f1345, %f1330, %f1344;
|
|
add.f32 %f1346, %f1338, %f1345;
|
|
add.f32 %f1347, %f1343, %f1346;
|
|
add.f32 %f1348, %f1344, %f1347;
|
|
sub.f32 %f1349, %f1344, %f1348;
|
|
add.f32 %f1350, %f1347, %f1349;
|
|
mov.f32 %f1351, 0f3F317200;
|
|
mul.rn.f32 %f1352, %f1324, %f1351;
|
|
mov.f32 %f1353, 0f35BFBE8E;
|
|
mul.rn.f32 %f1354, %f1324, %f1353;
|
|
add.f32 %f1355, %f1352, %f1348;
|
|
sub.f32 %f1356, %f1352, %f1355;
|
|
add.f32 %f1357, %f1348, %f1356;
|
|
add.f32 %f1358, %f1350, %f1357;
|
|
add.f32 %f1359, %f1354, %f1358;
|
|
add.f32 %f1360, %f1355, %f1359;
|
|
sub.f32 %f1361, %f1355, %f1360;
|
|
add.f32 %f1362, %f1359, %f1361;
|
|
mov.f32 %f1363, 0f3ED55555;
|
|
mul.rn.f32 %f1364, %f1363, %f1360;
|
|
neg.f32 %f1365, %f1364;
|
|
fma.rn.f32 %f1366, %f1363, %f1360, %f1365;
|
|
fma.rn.f32 %f1367, %f1363, %f1362, %f1366;
|
|
mov.f32 %f1368, 0f00000000;
|
|
fma.rn.f32 %f1369, %f1368, %f1360, %f1367;
|
|
add.rn.f32 %f1370, %f1364, %f1369;
|
|
neg.f32 %f1371, %f1370;
|
|
add.rn.f32 %f1372, %f1364, %f1371;
|
|
add.rn.f32 %f1373, %f1372, %f1369;
|
|
mov.b32 %r386, %f1370;
|
|
setp.eq.s32 %p160, %r386, 1118925336;
|
|
add.s32 %r387, %r386, -1;
|
|
mov.b32 %f1374, %r387;
|
|
add.f32 %f1375, %f1373, 0f37000000;
|
|
selp.f32 %f282, %f1375, %f1373, %p160;
|
|
selp.f32 %f1376, %f1374, %f1370, %p160;
|
|
mov.f32 %f1377, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1378, %f1376, %f1377;
|
|
cvt.rzi.f32.f32 %f1379, %f1378;
|
|
abs.f32 %f1380, %f1379;
|
|
setp.gt.f32 %p161, %f1380, 0f42FC0000;
|
|
mov.b32 %r388, %f1379;
|
|
and.b32 %r389, %r388, -2147483648;
|
|
or.b32 %r390, %r389, 1123811328;
|
|
mov.b32 %f1381, %r390;
|
|
selp.f32 %f1382, %f1381, %f1379, %p161;
|
|
mov.f32 %f1383, 0fBF317218;
|
|
fma.rn.f32 %f1384, %f1382, %f1383, %f1376;
|
|
mov.f32 %f1385, 0f3102E308;
|
|
fma.rn.f32 %f1386, %f1382, %f1385, %f1384;
|
|
mul.f32 %f1387, %f1386, 0f3FB8AA3B;
|
|
add.f32 %f1388, %f1382, 0f4B40007F;
|
|
mov.b32 %r391, %f1388;
|
|
shl.b32 %r392, %r391, 23;
|
|
mov.b32 %f1389, %r392;
|
|
ex2.approx.ftz.f32 %f1390, %f1387;
|
|
mul.f32 %f283, %f1390, %f1389;
|
|
setp.eq.f32 %p162, %f283, 0f7F800000;
|
|
mov.f32 %f1720, 0f7F800000;
|
|
@%p162 bra $L__BB0_124;
|
|
|
|
fma.rn.f32 %f1720, %f283, %f282, %f283;
|
|
|
|
$L__BB0_124:
|
|
setp.lt.f32 %p163, %f267, 0f00000000;
|
|
and.pred %p9, %p163, %p150;
|
|
setp.eq.f32 %p165, %f267, 0f00000000;
|
|
@%p165 bra $L__BB0_128;
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f1395, %f267, %f267;
|
|
selp.f32 %f1722, %f1395, 0f00000000, %p150;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_125:
|
|
mov.b32 %r393, %f1720;
|
|
xor.b32 %r394, %r393, -2147483648;
|
|
mov.b32 %f1391, %r394;
|
|
selp.f32 %f1722, %f1391, %f1720, %p9;
|
|
setp.geu.f32 %p166, %f267, 0f00000000;
|
|
@%p166 bra $L__BB0_129;
|
|
|
|
mov.f32 %f1392, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1393, %f1392;
|
|
setp.eq.f32 %p167, %f1393, 0f3ED55555;
|
|
@%p167 bra $L__BB0_129;
|
|
|
|
mov.f32 %f1722, 0f7FFFFFFF;
|
|
|
|
$L__BB0_129:
|
|
add.f32 %f1396, %f281, 0f3ED55555;
|
|
mov.b32 %r395, %f1396;
|
|
setp.lt.s32 %p169, %r395, 2139095040;
|
|
@%p169 bra $L__BB0_134;
|
|
|
|
setp.gtu.f32 %p170, %f281, 0f7F800000;
|
|
@%p170 bra $L__BB0_133;
|
|
bra.uni $L__BB0_131;
|
|
|
|
$L__BB0_133:
|
|
add.f32 %f1722, %f267, 0f3ED55555;
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_131:
|
|
setp.neu.f32 %p171, %f281, 0f7F800000;
|
|
@%p171 bra $L__BB0_134;
|
|
|
|
selp.f32 %f1722, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_134:
|
|
abs.f32 %f292, %f268;
|
|
setp.lt.f32 %p172, %f292, 0f00800000;
|
|
mul.f32 %f1398, %f292, 0f4B800000;
|
|
selp.f32 %f1399, %f1398, %f292, %p172;
|
|
selp.f32 %f1400, 0fC3170000, 0fC2FE0000, %p172;
|
|
mov.b32 %r396, %f1399;
|
|
and.b32 %r397, %r396, 8388607;
|
|
or.b32 %r398, %r397, 1065353216;
|
|
mov.b32 %f1401, %r398;
|
|
shr.u32 %r399, %r396, 23;
|
|
cvt.rn.f32.u32 %f1402, %r399;
|
|
add.f32 %f1403, %f1400, %f1402;
|
|
setp.gt.f32 %p173, %f1401, 0f3FB504F3;
|
|
mul.f32 %f1404, %f1401, 0f3F000000;
|
|
add.f32 %f1405, %f1403, 0f3F800000;
|
|
selp.f32 %f1406, %f1405, %f1403, %p173;
|
|
selp.f32 %f1407, %f1404, %f1401, %p173;
|
|
add.f32 %f1408, %f1407, 0fBF800000;
|
|
add.f32 %f1409, %f1407, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1410, %f1409;
|
|
add.f32 %f1411, %f1408, %f1408;
|
|
mul.f32 %f1412, %f1411, %f1410;
|
|
mul.f32 %f1413, %f1412, %f1412;
|
|
mov.f32 %f1414, 0f3C4CAF63;
|
|
mov.f32 %f1415, 0f3B18F0FE;
|
|
fma.rn.f32 %f1416, %f1415, %f1413, %f1414;
|
|
mov.f32 %f1417, 0f3DAAAABD;
|
|
fma.rn.f32 %f1418, %f1416, %f1413, %f1417;
|
|
mul.rn.f32 %f1419, %f1418, %f1413;
|
|
mul.rn.f32 %f1420, %f1419, %f1412;
|
|
sub.f32 %f1421, %f1408, %f1412;
|
|
add.f32 %f1422, %f1421, %f1421;
|
|
neg.f32 %f1423, %f1412;
|
|
fma.rn.f32 %f1424, %f1423, %f1408, %f1422;
|
|
mul.rn.f32 %f1425, %f1410, %f1424;
|
|
add.f32 %f1426, %f1420, %f1412;
|
|
sub.f32 %f1427, %f1412, %f1426;
|
|
add.f32 %f1428, %f1420, %f1427;
|
|
add.f32 %f1429, %f1425, %f1428;
|
|
add.f32 %f1430, %f1426, %f1429;
|
|
sub.f32 %f1431, %f1426, %f1430;
|
|
add.f32 %f1432, %f1429, %f1431;
|
|
mov.f32 %f1433, 0f3F317200;
|
|
mul.rn.f32 %f1434, %f1406, %f1433;
|
|
mov.f32 %f1435, 0f35BFBE8E;
|
|
mul.rn.f32 %f1436, %f1406, %f1435;
|
|
add.f32 %f1437, %f1434, %f1430;
|
|
sub.f32 %f1438, %f1434, %f1437;
|
|
add.f32 %f1439, %f1430, %f1438;
|
|
add.f32 %f1440, %f1432, %f1439;
|
|
add.f32 %f1441, %f1436, %f1440;
|
|
add.f32 %f1442, %f1437, %f1441;
|
|
sub.f32 %f1443, %f1437, %f1442;
|
|
add.f32 %f1444, %f1441, %f1443;
|
|
mov.f32 %f1445, 0f3ED55555;
|
|
mul.rn.f32 %f1446, %f1445, %f1442;
|
|
neg.f32 %f1447, %f1446;
|
|
fma.rn.f32 %f1448, %f1445, %f1442, %f1447;
|
|
fma.rn.f32 %f1449, %f1445, %f1444, %f1448;
|
|
mov.f32 %f1450, 0f00000000;
|
|
fma.rn.f32 %f1451, %f1450, %f1442, %f1449;
|
|
add.rn.f32 %f1452, %f1446, %f1451;
|
|
neg.f32 %f1453, %f1452;
|
|
add.rn.f32 %f1454, %f1446, %f1453;
|
|
add.rn.f32 %f1455, %f1454, %f1451;
|
|
mov.b32 %r400, %f1452;
|
|
setp.eq.s32 %p174, %r400, 1118925336;
|
|
add.s32 %r401, %r400, -1;
|
|
mov.b32 %f1456, %r401;
|
|
add.f32 %f1457, %f1455, 0f37000000;
|
|
selp.f32 %f293, %f1457, %f1455, %p174;
|
|
selp.f32 %f1458, %f1456, %f1452, %p174;
|
|
mov.f32 %f1459, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1460, %f1458, %f1459;
|
|
cvt.rzi.f32.f32 %f1461, %f1460;
|
|
abs.f32 %f1462, %f1461;
|
|
setp.gt.f32 %p175, %f1462, 0f42FC0000;
|
|
mov.b32 %r402, %f1461;
|
|
and.b32 %r403, %r402, -2147483648;
|
|
or.b32 %r404, %r403, 1123811328;
|
|
mov.b32 %f1463, %r404;
|
|
selp.f32 %f1464, %f1463, %f1461, %p175;
|
|
mov.f32 %f1465, 0fBF317218;
|
|
fma.rn.f32 %f1466, %f1464, %f1465, %f1458;
|
|
mov.f32 %f1467, 0f3102E308;
|
|
fma.rn.f32 %f1468, %f1464, %f1467, %f1466;
|
|
mul.f32 %f1469, %f1468, 0f3FB8AA3B;
|
|
add.f32 %f1470, %f1464, 0f4B40007F;
|
|
mov.b32 %r405, %f1470;
|
|
shl.b32 %r406, %r405, 23;
|
|
mov.b32 %f1471, %r406;
|
|
ex2.approx.ftz.f32 %f1472, %f1469;
|
|
mul.f32 %f294, %f1472, %f1471;
|
|
setp.eq.f32 %p176, %f294, 0f7F800000;
|
|
mov.f32 %f1723, 0f7F800000;
|
|
@%p176 bra $L__BB0_136;
|
|
|
|
fma.rn.f32 %f1723, %f294, %f293, %f294;
|
|
|
|
$L__BB0_136:
|
|
setp.lt.f32 %p177, %f268, 0f00000000;
|
|
and.pred %p10, %p177, %p150;
|
|
setp.eq.f32 %p179, %f268, 0f00000000;
|
|
@%p179 bra $L__BB0_140;
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f1477, %f268, %f268;
|
|
selp.f32 %f1725, %f1477, 0f00000000, %p150;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_137:
|
|
mov.b32 %r407, %f1723;
|
|
xor.b32 %r408, %r407, -2147483648;
|
|
mov.b32 %f1473, %r408;
|
|
selp.f32 %f1725, %f1473, %f1723, %p10;
|
|
setp.geu.f32 %p180, %f268, 0f00000000;
|
|
@%p180 bra $L__BB0_141;
|
|
|
|
mov.f32 %f1474, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1475, %f1474;
|
|
setp.eq.f32 %p181, %f1475, 0f3ED55555;
|
|
@%p181 bra $L__BB0_141;
|
|
|
|
mov.f32 %f1725, 0f7FFFFFFF;
|
|
|
|
$L__BB0_141:
|
|
add.f32 %f1478, %f292, 0f3ED55555;
|
|
mov.b32 %r409, %f1478;
|
|
setp.lt.s32 %p183, %r409, 2139095040;
|
|
@%p183 bra $L__BB0_146;
|
|
|
|
setp.gtu.f32 %p184, %f292, 0f7F800000;
|
|
@%p184 bra $L__BB0_145;
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_145:
|
|
add.f32 %f1725, %f268, 0f3ED55555;
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_143:
|
|
setp.neu.f32 %p185, %f292, 0f7F800000;
|
|
@%p185 bra $L__BB0_146;
|
|
|
|
selp.f32 %f1725, 0fFF800000, 0f7F800000, %p10;
|
|
|
|
$L__BB0_146:
|
|
fma.rn.f32 %f1479, %f1719, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p186, %f266, 0f3F800000;
|
|
mov.f32 %f1480, 0f3F800000;
|
|
selp.f32 %f1481, 0f3F7FFFFF, %f1479, %p186;
|
|
mul.f32 %f1482, %f266, 0f414EB852;
|
|
setp.lt.f32 %p187, %f266, 0f3B4D2E1C;
|
|
selp.f32 %f1483, %f1482, %f1481, %p187;
|
|
fma.rn.f32 %f1484, %f1722, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p188, %f267, 0f3F800000;
|
|
selp.f32 %f1485, 0f3F7FFFFF, %f1484, %p188;
|
|
mul.f32 %f1486, %f267, 0f414EB852;
|
|
setp.lt.f32 %p189, %f267, 0f3B4D2E1C;
|
|
selp.f32 %f1487, %f1486, %f1485, %p189;
|
|
fma.rn.f32 %f1488, %f1725, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p190, %f268, 0f3F800000;
|
|
selp.f32 %f1489, 0f3F7FFFFF, %f1488, %p190;
|
|
mul.f32 %f1490, %f268, 0f414EB852;
|
|
setp.lt.f32 %p191, %f268, 0f3B4D2E1C;
|
|
selp.f32 %f1491, %f1490, %f1489, %p191;
|
|
min.f32 %f1492, %f1483, %f1480;
|
|
mov.f32 %f1493, 0f00000000;
|
|
max.f32 %f1494, %f1493, %f1492;
|
|
mul.f32 %f1495, %f1494, 0f43800000;
|
|
cvt.rzi.u32.f32 %r410, %f1495;
|
|
min.u32 %r411, %r410, 255;
|
|
min.f32 %f1496, %f1487, %f1480;
|
|
max.f32 %f1497, %f1493, %f1496;
|
|
mul.f32 %f1498, %f1497, 0f43800000;
|
|
cvt.rzi.u32.f32 %r412, %f1498;
|
|
min.u32 %r413, %r412, 255;
|
|
min.f32 %f1499, %f1491, %f1480;
|
|
max.f32 %f1500, %f1493, %f1499;
|
|
mul.f32 %f1501, %f1500, 0f43800000;
|
|
cvt.rzi.u32.f32 %r414, %f1501;
|
|
min.u32 %r415, %r414, 255;
|
|
shl.b64 %rd37, %rd10, 2;
|
|
add.s64 %rd38, %rd9, %rd37;
|
|
cvt.u16.u32 %rs20, %r415;
|
|
cvt.u16.u32 %rs21, %r413;
|
|
cvt.u16.u32 %rs22, %r411;
|
|
mov.u16 %rs23, 255;
|
|
st.global.v4.u8 [%rd38], {%rs22, %rs21, %rs20, %rs23};
|
|
|
|
$L__BB0_147:
|
|
and.b32 %r416, %r451, 4;
|
|
setp.eq.s32 %p192, %r416, 0;
|
|
ld.const.u32 %r452, [params+108];
|
|
@%p192 bra $L__BB0_151;
|
|
|
|
setp.eq.s32 %p193, %r452, 0;
|
|
ld.const.u64 %rd39, [params+224];
|
|
cvta.to.global.u64 %rd40, %rd39;
|
|
ld.const.u32 %r417, [params+216];
|
|
mad.lo.s32 %r418, %r417, %r4, %r3;
|
|
mul.wide.u32 %rd41, %r418, 8;
|
|
add.s64 %rd11, %rd40, %rd41;
|
|
@%p193 bra $L__BB0_150;
|
|
|
|
ld.global.v4.u16 {%rs31, %rs32, %rs33, %rs34}, [%rd11];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1502, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1503, %rs32;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1504, %rs33;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1505, %f1673, %f1502;
|
|
add.f32 %f1506, %f1674, %f1503;
|
|
add.f32 %f1507, %f1675, %f1504;
|
|
mov.f32 %f1508, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f1507;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1506;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1505;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f1508;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs27, %rs28, %rs29, %rs30};
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_150:
|
|
mov.f32 %f1512, 0f3F800000;
|
|
mov.u32 %r452, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1512;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1675;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1674;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f1673;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs35, %rs36, %rs37, %rs38};
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1513, 0f34000000;
|
|
max.f32 %f1514, %f1676, %f1513;
|
|
div.rn.f32 %f1515, %f1679, %f1514;
|
|
max.f32 %f1516, %f1677, %f1513;
|
|
div.rn.f32 %f1517, %f1680, %f1516;
|
|
max.f32 %f1518, %f1678, %f1513;
|
|
div.rn.f32 %f1519, %f1681, %f1518;
|
|
fma.rn.f32 %f303, %f1515, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f304, %f1517, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f305, %f1519, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1520, %f1682, %f1514;
|
|
div.rn.f32 %f1521, %f1683, %f1516;
|
|
div.rn.f32 %f1522, %f1684, %f1518;
|
|
fma.rn.f32 %f306, %f1520, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f307, %f1521, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f308, %f1522, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1523, %f1685, %f1514;
|
|
div.rn.f32 %f1524, %f1686, %f1516;
|
|
div.rn.f32 %f1525, %f1687, %f1518;
|
|
fma.rn.f32 %f309, %f1523, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f310, %f1524, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f311, %f1525, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd42, [params+256];
|
|
cvta.to.global.u64 %rd43, %rd42;
|
|
ld.const.u32 %r420, [params+248];
|
|
mad.lo.s32 %r421, %r420, %r4, %r3;
|
|
mul.wide.u32 %rd44, %r421, 8;
|
|
add.s64 %rd12, %rd43, %rd44;
|
|
setp.eq.s32 %p194, %r452, 0;
|
|
@%p194 bra $L__BB0_153;
|
|
|
|
ld.global.v4.u16 {%rs46, %rs47, %rs48, %rs49}, [%rd12];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1526, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1527, %rs47;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1528, %rs48;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1529, %f1676, %f1526;
|
|
add.f32 %f1530, %f1677, %f1527;
|
|
add.f32 %f1531, %f1678, %f1528;
|
|
mov.f32 %f1532, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f1531;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1530;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1529;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f1532;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs42, %rs43, %rs44, %rs45};
|
|
bra.uni $L__BB0_154;
|
|
|
|
$L__BB0_153:
|
|
mov.f32 %f1536, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1536;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1678;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1677;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f1676;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs50, %rs51, %rs52, %rs53};
|
|
|
|
$L__BB0_154:
|
|
ld.const.u64 %rd45, [params+272];
|
|
cvta.to.global.u64 %rd46, %rd45;
|
|
ld.const.u32 %r422, [params+264];
|
|
mad.lo.s32 %r423, %r422, %r4, %r3;
|
|
mul.wide.u32 %rd47, %r423, 8;
|
|
add.s64 %rd13, %rd46, %rd47;
|
|
@%p194 bra $L__BB0_156;
|
|
|
|
ld.global.v4.u16 {%rs61, %rs62, %rs63, %rs64}, [%rd13];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1537, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1538, %rs62;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1539, %rs63;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1540, %f303, %f1537;
|
|
add.f32 %f1541, %f304, %f1538;
|
|
add.f32 %f1542, %f305, %f1539;
|
|
mov.f32 %f1543, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1542;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1541;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1540;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f1543;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs57, %rs58, %rs59, %rs60};
|
|
bra.uni $L__BB0_157;
|
|
|
|
$L__BB0_156:
|
|
mov.f32 %f1547, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1547;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f305;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f304;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f303;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs65, %rs66, %rs67, %rs68};
|
|
|
|
$L__BB0_157:
|
|
ld.const.u64 %rd48, [params+288];
|
|
cvta.to.global.u64 %rd49, %rd48;
|
|
ld.const.u32 %r424, [params+280];
|
|
mad.lo.s32 %r425, %r424, %r4, %r3;
|
|
mul.wide.u32 %rd50, %r425, 8;
|
|
add.s64 %rd14, %rd49, %rd50;
|
|
@%p194 bra $L__BB0_159;
|
|
|
|
ld.global.v4.u16 {%rs76, %rs77, %rs78, %rs79}, [%rd14];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1548, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1549, %rs77;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1550, %rs78;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1551, %f306, %f1548;
|
|
add.f32 %f1552, %f307, %f1549;
|
|
add.f32 %f1553, %f308, %f1550;
|
|
mov.f32 %f1554, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f1553;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1552;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1551;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f1554;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs72, %rs73, %rs74, %rs75};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_159:
|
|
mov.f32 %f1558, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1558;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f308;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f307;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f306;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs80, %rs81, %rs82, %rs83};
|
|
|
|
$L__BB0_160:
|
|
ld.const.u64 %rd51, [params+304];
|
|
cvta.to.global.u64 %rd52, %rd51;
|
|
ld.const.u32 %r426, [params+296];
|
|
mad.lo.s32 %r427, %r426, %r4, %r3;
|
|
mul.wide.u32 %rd53, %r427, 8;
|
|
add.s64 %rd15, %rd52, %rd53;
|
|
@%p194 bra $L__BB0_162;
|
|
|
|
ld.global.v4.u16 {%rs91, %rs92, %rs93, %rs94}, [%rd15];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1559, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1560, %rs92;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1561, %rs93;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1562, %f309, %f1559;
|
|
add.f32 %f1563, %f310, %f1560;
|
|
add.f32 %f1564, %f311, %f1561;
|
|
mov.f32 %f1565, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f1564;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1563;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1562;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f1565;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs87, %rs88, %rs89, %rs90};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_162:
|
|
mov.f32 %f1569, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1569;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f311;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f310;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f309;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs95, %rs96, %rs97, %rs98};
|
|
|
|
$L__BB0_183:
|
|
ret;
|
|
|
|
}
|
|
|